diff options
Diffstat (limited to 'arch/arm/include/asm/arch-rockchip/grf_rk3399.h')
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index 62d8496..e709fda 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -334,23 +334,60 @@ enum { GRF_SPI2TPM_CSN0 = 1, /* GRF_GPIO3A_IOMUX */ + GRF_GPIO3A0_SEL_SHIFT = 0, + GRF_GPIO3A0_SEL_MASK = 3 << GRF_GPIO3A0_SEL_SHIFT, + GRF_MAC_TXD2 = 1, + GRF_GPIO3A1_SEL_SHIFT = 2, + GRF_GPIO3A1_SEL_MASK = 3 << GRF_GPIO3A1_SEL_SHIFT, + GRF_MAC_TXD3 = 1, + GRF_GPIO3A2_SEL_SHIFT = 4, + GRF_GPIO3A2_SEL_MASK = 3 << GRF_GPIO3A2_SEL_SHIFT, + GRF_MAC_RXD2 = 1, + GRF_GPIO3A3_SEL_SHIFT = 6, + GRF_GPIO3A3_SEL_MASK = 3 << GRF_GPIO3A3_SEL_SHIFT, + GRF_MAC_RXD3 = 1, GRF_GPIO3A4_SEL_SHIFT = 8, GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT, + GRF_MAC_TXD0 = 1, GRF_SPI0NORCODEC_RXD = 2, GRF_GPIO3A5_SEL_SHIFT = 10, GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT, + GRF_MAC_TXD1 = 1, GRF_SPI0NORCODEC_TXD = 2, GRF_GPIO3A6_SEL_SHIFT = 12, GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT, + GRF_MAC_RXD0 = 1, GRF_SPI0NORCODEC_CLK = 2, GRF_GPIO3A7_SEL_SHIFT = 14, GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT, + GRF_MAC_RXD1 = 1, GRF_SPI0NORCODEC_CSN0 = 2, /* GRF_GPIO3B_IOMUX */ GRF_GPIO3B0_SEL_SHIFT = 0, GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT, + GRF_MAC_MDC = 1, GRF_SPI0NORCODEC_CSN1 = 2, + GRF_GPIO3B1_SEL_SHIFT = 2, + GRF_GPIO3B1_SEL_MASK = 3 << GRF_GPIO3B1_SEL_SHIFT, + GRF_MAC_RXDV = 1, + GRF_GPIO3B3_SEL_SHIFT = 6, + GRF_GPIO3B3_SEL_MASK = 3 << GRF_GPIO3B3_SEL_SHIFT, + GRF_MAC_CLK = 1, + GRF_GPIO3B4_SEL_SHIFT = 8, + GRF_GPIO3B4_SEL_MASK = 3 << GRF_GPIO3B4_SEL_SHIFT, + GRF_MAC_TXEN = 1, + GRF_GPIO3B5_SEL_SHIFT = 10, + GRF_GPIO3B5_SEL_MASK = 3 << GRF_GPIO3B5_SEL_SHIFT, + GRF_MAC_MDIO = 1, + GRF_GPIO3B6_SEL_SHIFT = 12, + GRF_GPIO3B6_SEL_MASK = 3 << GRF_GPIO3B6_SEL_SHIFT, + GRF_MAC_RXCLK = 1, + + /* GRF_GPIO3C_IOMUX */ + GRF_GPIO3C1_SEL_SHIFT = 2, + GRF_GPIO3C1_SEL_MASK = 3 << GRF_GPIO3C1_SEL_SHIFT, + GRF_MAC_TXCLK = 1, /* GRF_GPIO4B_IOMUX */ GRF_GPIO4B0_SEL_SHIFT = 0, |