13 files changed, 1474 insertions, 477 deletions

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index a7056d4..7818aa5 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014-2017 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -29,17 +29,23 @@
 #define SOCFPGA_MPUL2_ADDRESS			0xfffff000
 #define SOCFPGA_I2C0_ADDRESS			0xffc02200
 #define SOCFPGA_I2C1_ADDRESS			0xffc02300
+#define SOCFPGA_I2C2_ADDRESS			0xffc02400
+#define SOCFPGA_I2C3_ADDRESS			0xffc02500
+#define SOCFPGA_I2C4_ADDRESS			0xffc02600
 
 #define SOCFPGA_ECC_OCRAM_ADDRESS		0xff8c3000
 #define SOCFPGA_UART0_ADDRESS			0xffc02000
 #define SOCFPGA_OSC1TIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_OSC1TIMER1_ADDRESS		0xffd00100
 #define SOCFPGA_CLKMGR_ADDRESS			0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS			0xffd05000
 
 #define SOCFPGA_SDR_ADDRESS			0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST		0xffd11000
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xffd12400
 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS	0xffd13200
 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS	0xffd13300
 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS		0xffd13400
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST		0xffd13500
 
 #endif /* _SOCFPGA_A10_BASE_HARDWARE_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 803c926..4c6b1f8 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -1,317 +1,22 @@
 /*
- *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef	_CLOCK_MANAGER_H_
-#define	_CLOCK_MANAGER_H_
+#ifndef _CLOCK_MANAGER_H_
+#define _CLOCK_MANAGER_H_
 
 #ifndef __ASSEMBLER__
-/* Clock speed accessors */
-unsigned long cm_get_mpu_clk_hz(void);
-unsigned long cm_get_sdram_clk_hz(void);
-unsigned int cm_get_l4_sp_clk_hz(void);
-unsigned int cm_get_mmc_controller_clk_hz(void);
-unsigned int cm_get_qspi_controller_clk_hz(void);
-unsigned int cm_get_spi_controller_clk_hz(void);
-const unsigned int cm_get_osc_clk_hz(const int osc);
-const unsigned int cm_get_f2s_per_ref_clk_hz(void);
-const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
-
-/* Clock configuration accessors */
-const struct cm_config * const cm_get_default_config(void);
+void cm_wait_for_lock(u32 mask);
+int cm_wait_for_fsm(void);
+void cm_print_clock_quick_summary(void);
 #endif
 
-struct cm_config {
-	/* main group */
-	uint32_t main_vco_base;
-	uint32_t mpuclk;
-	uint32_t mainclk;
-	uint32_t dbgatclk;
-	uint32_t mainqspiclk;
-	uint32_t mainnandsdmmcclk;
-	uint32_t cfg2fuser0clk;
-	uint32_t maindiv;
-	uint32_t dbgdiv;
-	uint32_t tracediv;
-	uint32_t l4src;
-
-	/* peripheral group */
-	uint32_t peri_vco_base;
-	uint32_t emac0clk;
-	uint32_t emac1clk;
-	uint32_t perqspiclk;
-	uint32_t pernandsdmmcclk;
-	uint32_t perbaseclk;
-	uint32_t s2fuser1clk;
-	uint32_t perdiv;
-	uint32_t gpiodiv;
-	uint32_t persrc;
-
-	/* sdram pll group */
-	uint32_t sdram_vco_base;
-	uint32_t ddrdqsclk;
-	uint32_t ddr2xdqsclk;
-	uint32_t ddrdqclk;
-	uint32_t s2fuser2clk;
-
-	/* altera group */
-	uint32_t altera_grp_mpuclk;
-};
-
-void cm_basic_init(const struct cm_config * const cfg);
-
-struct socfpga_clock_manager_main_pll {
-	u32	vco;
-	u32	misc;
-	u32	mpuclk;
-	u32	mainclk;
-	u32	dbgatclk;
-	u32	mainqspiclk;
-	u32	mainnandsdmmcclk;
-	u32	cfgs2fuser0clk;
-	u32	en;
-	u32	maindiv;
-	u32	dbgdiv;
-	u32	tracediv;
-	u32	l4src;
-	u32	stat;
-	u32	_pad_0x38_0x40[2];
-};
-
-struct socfpga_clock_manager_per_pll {
-	u32	vco;
-	u32	misc;
-	u32	emac0clk;
-	u32	emac1clk;
-	u32	perqspiclk;
-	u32	pernandsdmmcclk;
-	u32	perbaseclk;
-	u32	s2fuser1clk;
-	u32	en;
-	u32	div;
-	u32	gpiodiv;
-	u32	src;
-	u32	stat;
-	u32	_pad_0x34_0x40[3];
-};
-
-struct socfpga_clock_manager_sdr_pll {
-	u32	vco;
-	u32	ctrl;
-	u32	ddrdqsclk;
-	u32	ddr2xdqsclk;
-	u32	ddrdqclk;
-	u32	s2fuser2clk;
-	u32	en;
-	u32	stat;
-};
-
-struct socfpga_clock_manager_altera {
-	u32	mpuclk;
-	u32	mainclk;
-};
-
-struct socfpga_clock_manager {
-	u32	ctrl;
-	u32	bypass;
-	u32	inter;
-	u32	intren;
-	u32	dbctrl;
-	u32	stat;
-	u32	_pad_0x18_0x3f[10];
-	struct socfpga_clock_manager_main_pll main_pll;
-	struct socfpga_clock_manager_per_pll per_pll;
-	struct socfpga_clock_manager_sdr_pll sdr_pll;
-	struct socfpga_clock_manager_altera altera;
-	u32	_pad_0xe8_0x200[70];
-};
-
-#define CLKMGR_CTRL_SAFEMODE				(1 << 0)
-#define CLKMGR_CTRL_SAFEMODE_OFFSET			0
-
-#define CLKMGR_BYPASS_PERPLLSRC				(1 << 4)
-#define CLKMGR_BYPASS_PERPLLSRC_OFFSET			4
-#define CLKMGR_BYPASS_PERPLL				(1 << 3)
-#define CLKMGR_BYPASS_PERPLL_OFFSET			3
-#define CLKMGR_BYPASS_SDRPLLSRC				(1 << 2)
-#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET			2
-#define CLKMGR_BYPASS_SDRPLL				(1 << 1)
-#define CLKMGR_BYPASS_SDRPLL_OFFSET			1
-#define CLKMGR_BYPASS_MAINPLL				(1 << 0)
-#define CLKMGR_BYPASS_MAINPLL_OFFSET			0
-
-#define CLKMGR_INTER_SDRPLLLOCKED_MASK			0x00000100
-#define CLKMGR_INTER_PERPLLLOCKED_MASK			0x00000080
-#define CLKMGR_INTER_MAINPLLLOCKED_MASK			0x00000040
-#define CLKMGR_INTER_PERPLLLOST_MASK			0x00000010
-#define CLKMGR_INTER_SDRPLLLOST_MASK			0x00000020
-#define CLKMGR_INTER_MAINPLLLOST_MASK			0x00000008
-
-#define CLKMGR_STAT_BUSY				(1 << 0)
-
-/* Main PLL */
-#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN			(1 << 0)
-#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET		0
-#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET		16
-#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK		0x003f0000
-#define CLKMGR_MAINPLLGRP_VCO_EN			(1 << 1)
-#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET			1
-#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET		3
-#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK		0x0000fff8
-#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK		0x01000000
-#define CLKMGR_MAINPLLGRP_VCO_PWRDN			(1 << 2)
-#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET		2
-#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK		0x80000000
-#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE		0x8001000d
-
-#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET		0
-#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK		0x000001ff
-
-#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET		0
-#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK		0x000001ff
-
-#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET		0
-#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK		0x000001ff
-
-#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET	0
-#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK		0x000001ff
-
-#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET	0
-#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK	0x000001ff
-
-#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET	0
-#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK	0x000001ff
-
-#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK		0x00000010
-#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK		0x00000020
-#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK		0x00000080
-#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK		0x00000040
-#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK		0x00000004
-#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK		0x00000200
-
-#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET	0
-#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK		0x00000003
-#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET	2
-#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK		0x0000000c
-#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET	4
-#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK		0x00000070
-#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET	7
-#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK		0x00000380
-
-#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET	0
-#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK		0x00000003
-#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET		2
-#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK		0x0000000c
-
-#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET	0
-#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK	0x00000007
-
-#define CLKMGR_MAINPLLGRP_L4SRC_L4MP			(1 << 0)
-#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET		0
-#define CLKMGR_MAINPLLGRP_L4SRC_L4SP			(1 << 1)
-#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET		1
-#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE		0x00000000
-#define CLKMGR_L4_SP_CLK_SRC_MAINPLL			0x0
-#define CLKMGR_L4_SP_CLK_SRC_PERPLL			0x1
-
-/* Per PLL */
-#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET		16
-#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK			0x003f0000
-#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET		3
-#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK			0x0000fff8
-#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK		0x01000000
-#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET		22
-#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK			0x00c00000
-#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK		0x80000000
-#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE		0x8001000d
-#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET		22
-#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK			0x00c00000
-
-#define CLKMGR_VCO_SSRC_EOSC1				0x0
-#define CLKMGR_VCO_SSRC_EOSC2				0x1
-#define CLKMGR_VCO_SSRC_F2S				0x2
-
-#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET		0
-#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK		0x000001ff
-
-#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET		0
-#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK		0x000001ff
-
-#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET		0
-#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK		0x000001ff
-
-#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET	0
-#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK	0x000001ff
-
-#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET		0
-#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK		0x000001ff
-
-#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET		0
-#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK		0x000001ff
-
-#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK		0x00000400
-#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		0x00000100
-
-#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET		6
-#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK		0x000001c0
-#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET		9
-#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK		0x00000e00
-#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET		3
-#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET		3
-#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET		0
-#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK		0x00000007
-
-#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET	0
-#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK		0x00ffffff
-
-#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET		2
-#define CLKMGR_PERPLLGRP_SRC_NAND_MASK			0x0000000c
-#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET		4
-#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK			0x00000030
-#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE		0x00000015
-#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET		0
-#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK			0x00000003
-#define CLKMGR_SDMMC_CLK_SRC_F2S			0x0
-#define CLKMGR_SDMMC_CLK_SRC_MAIN			0x1
-#define CLKMGR_SDMMC_CLK_SRC_PER			0x2
-#define CLKMGR_QSPI_CLK_SRC_F2S				0x0
-#define CLKMGR_QSPI_CLK_SRC_MAIN			0x1
-#define CLKMGR_QSPI_CLK_SRC_PER				0x2
-
-/* SDR PLL */
-#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET		16
-#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK			0x003f0000
-#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET		3
-#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK			0x0000fff8
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL		(1 << 24)
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET		24
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET		25
-#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK		0x7e000000
-#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK		0x80000000
-#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE		0x8001000d
-#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET		22
-#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK			0x00c00000
-
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET		0
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK		0x000001ff
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET		9
-#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK		0x00000e00
-
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET		0
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK		0x000001ff
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET	9
-#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK		0x00000e00
-
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET		0
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK		0x000001ff
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET		9
-#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK		0x00000e00
-
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET		0
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK		0x000001ff
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET	9
-#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK		0x00000e00
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/clock_manager_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/clock_manager_arria10.h>
+#endif
 
 #endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
new file mode 100644
index 0000000..1b55bb8
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
@@ -0,0 +1,224 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef CLOCK_MANAGER_ARRIA10
+#define CLOCK_MANAGER_ARRIA10
+
+#ifndef __ASSEMBLER__
+
+struct socfpga_clock_manager_main_pll {
+	u32  vco0;
+	u32  vco1;
+	u32  en;
+	u32  ens;
+	u32  enr;
+	u32  bypass;
+	u32  bypasss;
+	u32  bypassr;
+	u32  mpuclk;
+	u32  nocclk;
+	u32  cntr2clk;
+	u32  cntr3clk;
+	u32  cntr4clk;
+	u32  cntr5clk;
+	u32  cntr6clk;
+	u32  cntr7clk;
+	u32  cntr8clk;
+	u32  cntr9clk;
+	u32  pad_0x48_0x5b[5];
+	u32  cntr15clk;
+	u32  outrst;
+	u32  outrststat;
+	u32  nocdiv;
+	u32  pad_0x6c_0x80[5];
+};
+
+struct socfpga_clock_manager_per_pll {
+	u32  vco0;
+	u32  vco1;
+	u32  en;
+	u32  ens;
+	u32  enr;
+	u32  bypass;
+	u32  bypasss;
+	u32  bypassr;
+	u32  pad_0x20_0x27[2];
+	u32  cntr2clk;
+	u32  cntr3clk;
+	u32  cntr4clk;
+	u32  cntr5clk;
+	u32  cntr6clk;
+	u32  cntr7clk;
+	u32  cntr8clk;
+	u32  cntr9clk;
+	u32  pad_0x48_0x5f[6];
+	u32  outrst;
+	u32  outrststat;
+	u32  emacctl;
+	u32  gpiodiv;
+	u32  pad_0x70_0x80[4];
+};
+
+struct socfpga_clock_manager_altera {
+	u32	mpuclk;
+	u32	nocclk;
+	u32	mainmisc0;
+	u32	mainmisc1;
+	u32	perimisc0;
+	u32	perimisc1;
+};
+
+struct socfpga_clock_manager {
+	/* clkmgr */
+	u32  ctrl;
+	u32  intr;
+	u32  intrs;
+	u32  intrr;
+	u32  intren;
+	u32  intrens;
+	u32  intrenr;
+	u32  stat;
+	u32  testioctrl;
+	u32  _pad_0x24_0x40[7];
+	/* mainpllgrp */
+	struct socfpga_clock_manager_main_pll main_pll;
+	/* perpllgrp */
+	struct socfpga_clock_manager_per_pll per_pll;
+	struct socfpga_clock_manager_altera altera;
+};
+
+void cm_use_intosc(void);
+unsigned int cm_get_noc_clk_hz(void);
+unsigned int cm_get_l4_noc_hz(unsigned int nocdivshift);
+int cm_basic_init(const void *blob);
+
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_main_vco_clk_hz(void);
+unsigned int cm_get_per_vco_clk_hz(void);
+unsigned long cm_get_mpu_clk_hz(void);
+
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+
+#endif /* __ASSEMBLER__ */
+
+#define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET			0x140
+#define CLKMGR_MAINPLL_NOC_CLK_OFFSET			0x144
+#define LOCKED_MASK	(CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK  | \
+			 CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
+
+/* value */
+#define CLKMGR_MAINPLL_BYPASS_RESET			0x0000003f
+#define CLKMGR_PERPLL_BYPASS_RESET			0x000000ff
+#define CLKMGR_MAINPLL_VCO0_RESET			0x00010053
+#define CLKMGR_MAINPLL_VCO1_RESET			0x00010001
+#define CLKMGR_PERPLL_VCO0_RESET			0x00010053
+#define CLKMGR_PERPLL_VCO1_RESET			0x00010001
+#define CLKMGR_MAINPLL_VCO0_PSRC_EOSC			0x0
+#define CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC		0x1
+#define CLKMGR_MAINPLL_VCO0_PSRC_F2S			0x2
+#define CLKMGR_PERPLL_VCO0_PSRC_EOSC			0x0
+#define CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC		0x1
+#define CLKMGR_PERPLL_VCO0_PSRC_F2S			0x2
+#define CLKMGR_PERPLL_VCO0_PSRC_MAIN			0x3
+
+/* mask */
+#define CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK		BIT(6)
+#define CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK	BIT(7)
+#define CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK	BIT(8)
+#define CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK		BIT(9)
+#define CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK		BIT(17)
+#define CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK		BIT(0)
+#define CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK		BIT(1)
+#define CLKMGR_MAINPLL_VCO0_EN_SET_MSK			BIT(2)
+#define CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK		BIT(3)
+#define CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK		BIT(4)
+#define CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK		BIT(0)
+#define CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK		BIT(1)
+#define CLKMGR_PERPLL_VCO0_EN_SET_MSK			BIT(2)
+#define CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK		BIT(3)
+#define CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK		BIT(4)
+#define CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK	BIT(0)
+#define CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK	BIT(1)
+#define CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK		BIT(2)
+#define CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK		BIT(3)
+#define CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK	BIT(8)
+#define CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK		BIT(9)
+#define CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK	BIT(10)
+#define CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK		BIT(11)
+#define CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK		BIT(0)
+#define CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK	0x00000300
+#define CLKMGR_PERPLL_EN_RESET				0x00000f7f
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		BIT(5)
+#define CLKMGR_MAINPLL_VCO0_PSRC_MSK			0x00000003
+#define CLKMGR_MAINPLL_VCO1_NUMER_MSK			0x00001fff
+#define CLKMGR_MAINPLL_VCO1_DENOM_MSK			0x0000003f
+#define CLKMGR_MAINPLL_CNTRCLK_MSK			0x000003ff
+#define CLKMGR_PERPLL_VCO0_PSRC_MSK			0x00000003
+#define CLKMGR_PERPLL_VCO1_NUMER_MSK			0x00001fff
+#define CLKMGR_PERPLL_VCO1_DENOM_MSK			0x0000003f
+#define CLKMGR_PERPLL_CNTRCLK_MSK			0x000003ff
+#define CLKMGR_MAINPLL_MPUCLK_SRC_MSK			0x00000007
+#define CLKMGR_MAINPLL_MPUCLK_CNT_MSK			0x000003ff
+#define CLKMGR_MAINPLL_MPUCLK_SRC_MAIN			0
+#define CLKMGR_MAINPLL_MPUCLK_SRC_PERI			1
+#define CLKMGR_MAINPLL_MPUCLK_SRC_OSC1			2
+#define CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC		3
+#define CLKMGR_MAINPLL_MPUCLK_SRC_FPGA			4
+#define CLKMGR_MAINPLL_NOCDIV_MSK			0x00000003
+#define CLKMGR_MAINPLL_NOCCLK_CNT_MSK			0x000003ff
+#define CLKMGR_MAINPLL_NOCCLK_SRC_MSK			0x00000007
+#define CLKMGR_MAINPLL_NOCCLK_SRC_MAIN			0
+#define CLKMGR_MAINPLL_NOCCLK_SRC_PERI			1
+#define CLKMGR_MAINPLL_NOCCLK_SRC_OSC1			2
+#define CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC		3
+#define CLKMGR_MAINPLL_NOCCLK_SRC_FPGA			4
+
+#define CLKMGR_PERPLLGRP_SRC_MSK			0x00000007
+#define CLKMGR_PERPLLGRP_SRC_MAIN			0
+#define CLKMGR_PERPLLGRP_SRC_PERI			1
+#define CLKMGR_PERPLLGRP_SRC_OSC1			2
+#define CLKMGR_PERPLLGRP_SRC_INTOSC			3
+#define CLKMGR_PERPLLGRP_SRC_FPGA			4
+
+/* bit shifting macro */
+#define CLKMGR_MAINPLL_VCO0_PSRC_LSB		8
+#define CLKMGR_PERPLL_VCO0_PSRC_LSB		8
+#define CLKMGR_MAINPLL_VCO1_DENOM_LSB		16
+#define CLKMGR_PERPLL_VCO1_DENOM_LSB		16
+#define CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB	16
+#define CLKMGR_MAINPLL_NOCCLK_SRC_LSB		16
+#define CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB	0
+#define CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB	8
+#define CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB	16
+#define CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB	24
+#define CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB	26
+#define CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB	28
+#define CLKMGR_MAINPLL_MPUCLK_SRC_LSB		16
+#define CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB	16
+#define CLKMGR_MAINPLL_NOCCLK_SRC_LSB		16
+#define CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB		16
+#define CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB		16
+#define CLKMGR_PERPLL_CNTR2CLK_SRC_LSB		16
+#define CLKMGR_PERPLL_CNTR3CLK_SRC_LSB		16
+#define CLKMGR_PERPLL_CNTR4CLK_SRC_LSB		16
+#define CLKMGR_PERPLL_CNTR5CLK_SRC_LSB		16
+#define CLKMGR_PERPLL_CNTR6CLK_SRC_LSB		16
+#define CLKMGR_PERPLL_CNTR8CLK_SRC_LSB		16
+#define CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB	26
+#define CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB	27
+#define CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB	28
+
+/* PLL ramping work around */
+#define CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ	900000000
+#define CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ	300000000
+#define CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ	100000000
+#define CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ	33000000
+
+#define CLKMGR_STAT_BUSY			BIT(0)
+
+#endif /* CLOCK_MANAGER_ARRIA10 */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
new file mode 100644
index 0000000..9227dfb
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
@@ -0,0 +1,322 @@
+/*
+ *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CLOCK_MANAGER_GEN5_H_
+#define _CLOCK_MANAGER_GEN5_H_
+
+#ifndef __ASSEMBLER__
+
+struct cm_config {
+	/* main group */
+	u32 main_vco_base;
+	u32 mpuclk;
+	u32 mainclk;
+	u32 dbgatclk;
+	u32 mainqspiclk;
+	u32 mainnandsdmmcclk;
+	u32 cfg2fuser0clk;
+	u32 maindiv;
+	u32 dbgdiv;
+	u32 tracediv;
+	u32 l4src;
+
+	/* peripheral group */
+	u32 peri_vco_base;
+	u32 emac0clk;
+	u32 emac1clk;
+	u32 perqspiclk;
+	u32 pernandsdmmcclk;
+	u32 perbaseclk;
+	u32 s2fuser1clk;
+	u32 perdiv;
+	u32 gpiodiv;
+	u32 persrc;
+
+	/* sdram pll group */
+	u32 sdram_vco_base;
+	u32 ddrdqsclk;
+	u32 ddr2xdqsclk;
+	u32 ddrdqclk;
+	u32 s2fuser2clk;
+
+	/* altera group */
+	u32 altera_grp_mpuclk;
+};
+
+struct socfpga_clock_manager_main_pll {
+	u32	vco;
+	u32	misc;
+	u32	mpuclk;
+	u32	mainclk;
+	u32	dbgatclk;
+	u32	mainqspiclk;
+	u32	mainnandsdmmcclk;
+	u32	cfgs2fuser0clk;
+	u32	en;
+	u32	maindiv;
+	u32	dbgdiv;
+	u32	tracediv;
+	u32	l4src;
+	u32	stat;
+	u32	_pad_0x38_0x40[2];
+};
+
+struct socfpga_clock_manager_per_pll {
+	u32	vco;
+	u32	misc;
+	u32	emac0clk;
+	u32	emac1clk;
+	u32	perqspiclk;
+	u32	pernandsdmmcclk;
+	u32	perbaseclk;
+	u32	s2fuser1clk;
+	u32	en;
+	u32	div;
+	u32	gpiodiv;
+	u32	src;
+	u32	stat;
+	u32	_pad_0x34_0x40[3];
+};
+
+struct socfpga_clock_manager_sdr_pll {
+	u32	vco;
+	u32	ctrl;
+	u32	ddrdqsclk;
+	u32	ddr2xdqsclk;
+	u32	ddrdqclk;
+	u32	s2fuser2clk;
+	u32	en;
+	u32	stat;
+};
+
+struct socfpga_clock_manager_altera {
+	u32	mpuclk;
+	u32	mainclk;
+};
+
+struct socfpga_clock_manager {
+	u32	ctrl;
+	u32	bypass;
+	u32	inter;
+	u32	intren;
+	u32	dbctrl;
+	u32	stat;
+	u32	_pad_0x18_0x3f[10];
+	struct socfpga_clock_manager_main_pll main_pll;
+	struct socfpga_clock_manager_per_pll per_pll;
+	struct socfpga_clock_manager_sdr_pll sdr_pll;
+	struct socfpga_clock_manager_altera altera;
+	u32	_pad_0xe8_0x200[70];
+};
+
+/* Clock speed accessors */
+unsigned long cm_get_mpu_clk_hz(void);
+unsigned long cm_get_sdram_clk_hz(void);
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+const unsigned int cm_get_osc_clk_hz(const int osc);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+
+/* Clock configuration accessors */
+int cm_basic_init(const struct cm_config * const cfg);
+const struct cm_config * const cm_get_default_config(void);
+#endif /* __ASSEMBLER__ */
+
+#define LOCKED_MASK \
+	(CLKMGR_INTER_SDRPLLLOCKED_MASK  | \
+	CLKMGR_INTER_PERPLLLOCKED_MASK  | \
+	CLKMGR_INTER_MAINPLLLOCKED_MASK)
+
+#define CLKMGR_CTRL_SAFEMODE				BIT(0)
+#define CLKMGR_CTRL_SAFEMODE_OFFSET			0
+
+#define CLKMGR_BYPASS_PERPLLSRC				BIT(4)
+#define CLKMGR_BYPASS_PERPLLSRC_OFFSET			4
+#define CLKMGR_BYPASS_PERPLL				BIT(3)
+#define CLKMGR_BYPASS_PERPLL_OFFSET			3
+#define CLKMGR_BYPASS_SDRPLLSRC				BIT(2)
+#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET			2
+#define CLKMGR_BYPASS_SDRPLL				BIT(1)
+#define CLKMGR_BYPASS_SDRPLL_OFFSET			1
+#define CLKMGR_BYPASS_MAINPLL				BIT(0)
+#define CLKMGR_BYPASS_MAINPLL_OFFSET			0
+
+#define CLKMGR_INTER_MAINPLLLOST_MASK			BIT(3)
+#define CLKMGR_INTER_PERPLLLOST_MASK			BIT(4)
+#define CLKMGR_INTER_SDRPLLLOST_MASK			BIT(5)
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK			BIT(6)
+#define CLKMGR_INTER_PERPLLLOCKED_MASK			BIT(7)
+#define CLKMGR_INTER_SDRPLLLOCKED_MASK			BIT(8)
+
+#define CLKMGR_STAT_BUSY				BIT(0)
+
+/* Main PLL */
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN			BIT(0)
+#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET		0
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET		16
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK		0x003f0000
+#define CLKMGR_MAINPLLGRP_VCO_EN			BIT(1)
+#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET			1
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET		3
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK		0x0000fff8
+#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK		0x01000000
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN			BIT(2)
+#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET		2
+#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK		0x80000000
+#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE		0x8001000d
+
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET		0
+#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET		0
+#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET		0
+#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET	0
+#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET	0
+#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK	0x000001ff
+
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET	0
+#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK	0x000001ff
+
+#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK		BIT(2)
+#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK		BIT(4)
+#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK		BIT(5)
+#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK		BIT(6)
+#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK		BIT(7)
+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK		BIT(9)
+
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET	0
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK		0x00000003
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET	2
+#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK		0x0000000c
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET	4
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK		0x00000070
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET	7
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK		0x00000380
+
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET	0
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK		0x00000003
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET		2
+#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK		0x0000000c
+
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET	0
+#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK	0x00000007
+
+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP			BIT(0)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET		0
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP			BIT(1)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET		1
+#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE		0x00000000
+#define CLKMGR_L4_SP_CLK_SRC_MAINPLL			0x0
+#define CLKMGR_L4_SP_CLK_SRC_PERPLL			0x1
+
+/* Per PLL */
+#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET		16
+#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK			0x003f0000
+#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET		3
+#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK			0x0000fff8
+#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK		0x01000000
+#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET		22
+#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK			0x00c00000
+#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK		0x80000000
+#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE		0x8001000d
+#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET		22
+#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK			0x00c00000
+
+#define CLKMGR_VCO_SSRC_EOSC1				0x0
+#define CLKMGR_VCO_SSRC_EOSC2				0x1
+#define CLKMGR_VCO_SSRC_F2S				0x2
+
+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET	0
+#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK	0x000001ff
+
+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET		0
+#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK		0x000001ff
+
+#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK		0x00000400
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		0x00000100
+
+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET		6
+#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK		0x000001c0
+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET		9
+#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK		0x00000e00
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET		3
+#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET		3
+#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET		0
+#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK		0x00000007
+
+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET	0
+#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK		0x00ffffff
+
+#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET		2
+#define CLKMGR_PERPLLGRP_SRC_NAND_MASK			0x0000000c
+#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET		4
+#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK			0x00000030
+#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE		0x00000015
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET		0
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK			0x00000003
+#define CLKMGR_SDMMC_CLK_SRC_F2S			0x0
+#define CLKMGR_SDMMC_CLK_SRC_MAIN			0x1
+#define CLKMGR_SDMMC_CLK_SRC_PER			0x2
+#define CLKMGR_QSPI_CLK_SRC_F2S				0x0
+#define CLKMGR_QSPI_CLK_SRC_MAIN			0x1
+#define CLKMGR_QSPI_CLK_SRC_PER				0x2
+
+/* SDR PLL */
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET		16
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK			0x003f0000
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET		3
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK			0x0000fff8
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL		BIT(24)
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET		24
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET		25
+#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK		0x7e000000
+#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK		BIT(31)
+#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE		0x8001000d
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET		22
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK			0x00c00000
+
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET		0
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK		0x000001ff
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET		9
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK		0x00000e00
+
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET		0
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK		0x000001ff
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET	9
+#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK		0x00000e00
+
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET		0
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK		0x000001ff
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET		9
+#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK		0x00000e00
+
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET		0
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK		0x000001ff
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET	9
+#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK		0x00000e00
+
+#endif /* _CLOCK_MANAGER_GEN5_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
new file mode 100644
index 0000000..0b65783
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#ifndef _MISC_H_
+#define _MISC_H_
+
+void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
+
+struct bsel {
+	const char	*mode;
+	const char	*name;
+};
+
+extern struct bsel bsel_str[];
+
+#ifdef CONFIG_FPGA
+void socfpga_fpga_add(void);
+#else
+static inline void socfpga_fpga_add(void) {}
+#endif
+
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+unsigned int dedicated_uart_com_port(const void *blob);
+unsigned int shared_uart_com_port(const void *blob);
+unsigned int uart_com_port(const void *blob);
+#endif
+
+#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h b/arch/arm/mach-socfpga/include/mach/pinmux.h
new file mode 100644
index 0000000..563a3db
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/pinmux.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _PINMUX_H_
+#define _PINMUX_H_
+
+#define PINMUX_UART		0xD
+
+#ifndef __ASSEMBLY__
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+#endif
+
+#endif /* _PINMUX_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 2f070f2..6591745 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -1,34 +1,17 @@
 /*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef	_RESET_MANAGER_H_
-#define	_RESET_MANAGER_H_
+#ifndef _RESET_MANAGER_H_
+#define _RESET_MANAGER_H_
 
 void reset_cpu(ulong addr);
-void reset_deassert_peripherals_handoff(void);
-
-void socfpga_bridges_reset(int enable);
 
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
-struct socfpga_reset_manager {
-	u32	status;
-	u32	ctrl;
-	u32	counts;
-	u32	padding1;
-	u32	mpu_mod_reset;
-	u32	per_mod_reset;
-	u32	per2_mod_reset;
-	u32	brg_mod_reset;
-	u32	misc_mod_reset;
-	u32	padding2[12];
-	u32	tstscratch;
-};
-
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
 #else
@@ -55,28 +38,13 @@ struct socfpga_reset_manager {
 #define RSTMGR_BANK(_reset)			\
 	(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
 
-/*
- * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
- * 0 ... mpumodrst
- * 1 ... permodrst
- * 2 ... per2modrst
- * 3 ... brgmodrst
- * 4 ... miscmodrst
- */
-#define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
-#define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
-#define RSTMGR_NAND		RSTMGR_DEFINE(1, 4)
-#define RSTMGR_QSPI		RSTMGR_DEFINE(1, 5)
-#define RSTMGR_L4WD0		RSTMGR_DEFINE(1, 6)
-#define RSTMGR_OSC1TIMER0	RSTMGR_DEFINE(1, 8)
-#define RSTMGR_UART0		RSTMGR_DEFINE(1, 16)
-#define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 18)
-#define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 19)
-#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 22)
-#define RSTMGR_DMA		RSTMGR_DEFINE(1, 28)
-#define RSTMGR_SDR		RSTMGR_DEFINE(1, 29)
-
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)	RSTMGR_##_name
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/reset_manager_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/reset_manager_arria10.h>
+#endif
+
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
new file mode 100644
index 0000000..7922db8
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _RESET_MANAGER_ARRIA10_H_
+#define _RESET_MANAGER_ARRIA10_H_
+
+#include <dt-bindings/reset/altr,rst-mgr-a10.h>
+
+void socfpga_watchdog_disable(void);
+void socfpga_reset_deassert_noc_ddr_scheduler(void);
+int socfpga_is_wdt_in_reset(void);
+void socfpga_emac_manage_reset(ulong emacbase, u32 state);
+int socfpga_reset_deassert_bridges_handoff(void);
+void socfpga_reset_assert_fpga_connected_peripherals(void);
+void socfpga_reset_deassert_osc1wd0(void);
+void socfpga_reset_uart(int assert);
+int socfpga_bridges_reset(int enable);
+
+struct socfpga_reset_manager {
+	u32	stat;
+	u32	ramstat;
+	u32	miscstat;
+	u32	ctrl;
+	u32	hdsken;
+	u32	hdskreq;
+	u32	hdskack;
+	u32	counts;
+	u32	mpumodrst;
+	u32	per0modrst;
+	u32	per1modrst;
+	u32	brgmodrst;
+	u32	sysmodrst;
+	u32	coldmodrst;
+	u32	nrstmodrst;
+	u32	dbgmodrst;
+	u32	mpuwarmmask;
+	u32	per0warmmask;
+	u32	per1warmmask;
+	u32	brgwarmmask;
+	u32	syswarmmask;
+	u32	nrstwarmmask;
+	u32	l3warmmask;
+	u32	tststa;
+	u32	tstscratch;
+	u32	hdsktimeout;
+	u32	hmcintr;
+	u32	hmcintren;
+	u32	hmcintrens;
+	u32	hmcintrenr;
+	u32	hmcgpout;
+	u32	hmcgpin;
+};
+
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2		RSTMGR_DEFINE(1, 2)
+#define RSTMGR_NAND		RSTMGR_DEFINE(1, 5)
+#define RSTMGR_QSPI		RSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA		RSTMGR_DEFINE(1, 16)
+#define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 18)
+#define RSTMGR_L4WD0		RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1		RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0	RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1	RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0		RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1		RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0		RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1		RSTMGR_DEFINE(2, 17)
+#define RSTMGR_DDRSCH		RSTMGR_DEFINE(3, 6)
+
+#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK	BIT(1)
+#define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK	BIT(0)
+#define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK	BIT(1)
+#define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK	BIT(2)
+#define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK	BIT(3)
+#define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK	BIT(4)
+#define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK	BIT(5)
+#define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK	BIT(6)
+#define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK	BIT(7)
+#define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK	BIT(8)
+#define ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK	BIT(9)
+#define ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK	BIT(10)
+#define ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK	BIT(11)
+#define ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK	BIT(12)
+#define ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK	BIT(13)
+#define ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK	BIT(14)
+#define ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK	BIT(15)
+#define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK	BIT(16)
+#define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK	BIT(17)
+#define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK	BIT(18)
+#define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK	BIT(19)
+#define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK	BIT(20)
+#define ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK	BIT(21)
+#define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK	BIT(22)
+#define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK	BIT(24)
+#define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK	BIT(25)
+#define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK	BIT(26)
+#define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK	BIT(27)
+#define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK	BIT(28)
+#define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK	BIT(29)
+#define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK	BIT(30)
+#define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK	BIT(31)
+
+#define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK	BIT(0)
+#define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK	BIT(1)
+#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK	BIT(2)
+#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK	BIT(3)
+#define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK	BIT(4)
+#define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK	BIT(5)
+#define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK	BIT(8)
+#define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK	BIT(9)
+#define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK	BIT(10)
+#define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK	BIT(11)
+#define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK	BIT(12)
+#define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK	BIT(16)
+#define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK	BIT(17)
+#define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK	BIT(24)
+#define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK	BIT(25)
+#define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK	BIT(26)
+
+#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK	BIT(0)
+#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK	BIT(1)
+#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK	BIT(2)
+#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK	BIT(3)
+#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK	BIT(4)
+#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK	BIT(5)
+#define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK	BIT(6)
+
+#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK	BIT(0)
+#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK	BIT(1)
+#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK	BIT(2)
+#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK	BIT(3)
+
+#endif /* _RESET_MANAGER_ARRIA10_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
new file mode 100644
index 0000000..6d9cffe
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -0,0 +1,50 @@
+/*
+ *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _RESET_MANAGER_GEN5_H_
+#define _RESET_MANAGER_GEN5_H_
+
+#include <dt-bindings/reset/altr,rst-mgr.h>
+
+void reset_deassert_peripherals_handoff(void);
+void socfpga_bridges_reset(int enable);
+
+struct socfpga_reset_manager {
+	u32	status;
+	u32	ctrl;
+	u32	counts;
+	u32	padding1;
+	u32	mpu_mod_reset;
+	u32	per_mod_reset;
+	u32	per2_mod_reset;
+	u32	brg_mod_reset;
+	u32	misc_mod_reset;
+	u32	padding2[12];
+	u32	tstscratch;
+};
+
+/*
+ * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... permodrst
+ * 2 ... per2modrst
+ * 3 ... brgmodrst
+ * 4 ... miscmodrst
+ */
+#define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
+#define RSTMGR_NAND		RSTMGR_DEFINE(1, 4)
+#define RSTMGR_QSPI		RSTMGR_DEFINE(1, 5)
+#define RSTMGR_L4WD0		RSTMGR_DEFINE(1, 6)
+#define RSTMGR_OSC1TIMER0	RSTMGR_DEFINE(1, 8)
+#define RSTMGR_UART0		RSTMGR_DEFINE(1, 16)
+#define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 18)
+#define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 19)
+#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 22)
+#define RSTMGR_DMA		RSTMGR_DEFINE(1, 28)
+#define RSTMGR_SDR		RSTMGR_DEFINE(1, 29)
+
+#endif /* _RESET_MANAGER_GEN5_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
new file mode 100644
index 0000000..1d7b7c1
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2015-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _SOCFPGA_SDRAM_ARRIA10_H_
+#define _SOCFPGA_SDRAM_ARRIA10_H_
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_ecc_hmc {
+	u32 ip_rev_id;
+	u32 _pad_0x4_0x7;
+	u32 ddrioctrl;
+	u32 ddrcalstat;
+	u32 mpr_0beat1;
+	u32 mpr_1beat1;
+	u32 mpr_2beat1;
+	u32 mpr_3beat1;
+	u32 mpr_4beat1;
+	u32 mpr_5beat1;
+	u32 mpr_6beat1;
+	u32 mpr_7beat1;
+	u32 mpr_8beat1;
+	u32 mpr_0beat2;
+	u32 mpr_1beat2;
+	u32 mpr_2beat2;
+	u32 mpr_3beat2;
+	u32 mpr_4beat2;
+	u32 mpr_5beat2;
+	u32 mpr_6beat2;
+	u32 mpr_7beat2;
+	u32 mpr_8beat2;
+	u32 _pad_0x58_0x5f[2];
+	u32 auto_precharge;
+	u32 _pad_0x64_0xff[39];
+	u32 eccctrl;
+	u32 eccctrl2;
+	u32 _pad_0x108_0x10f[2];
+	u32 errinten;
+	u32 errintens;
+	u32 errintenr;
+	u32 intmode;
+	u32 intstat;
+	u32 diaginttest;
+	u32 modstat;
+	u32 derraddra;
+	u32 serraddra;
+	u32 _pad_0x134_0x137;
+	u32 autowb_corraddr;
+	u32 serrcntreg;
+	u32 autowb_drop_cntreg;
+	u32 _pad_0x144_0x147;
+	u32 ecc_reg2wreccdatabus;
+	u32 ecc_rdeccdata2regbus;
+	u32 ecc_reg2rdeccdatabus;
+	u32 _pad_0x154_0x15f[3];
+	u32 ecc_diagon;
+	u32 ecc_decstat;
+	u32 _pad_0x168_0x16f[2];
+	u32 ecc_errgenaddr_0;
+	u32 ecc_errgenaddr_1;
+	u32 ecc_errgenaddr_2;
+	u32 ecc_errgenaddr_3;
+};
+
+struct socfpga_noc_ddr_scheduler {
+	u32 ddr_t_main_scheduler_id_coreid;
+	u32 ddr_t_main_scheduler_id_revisionid;
+	u32 ddr_t_main_scheduler_ddrconf;
+	u32 ddr_t_main_scheduler_ddrtiming;
+	u32 ddr_t_main_scheduler_ddrmode;
+	u32 ddr_t_main_scheduler_readlatency;
+	u32 _pad_0x20_0x34[8];
+	u32 ddr_t_main_scheduler_activate;
+	u32 ddr_t_main_scheduler_devtodev;
+};
+
+/*
+ * OCRAM firewall
+ */
+struct socfpga_noc_fw_ocram {
+	u32 enable;
+	u32 enable_set;
+	u32 enable_clear;
+	u32 region0;
+	u32 region1;
+	u32 region2;
+	u32 region3;
+	u32 region4;
+	u32 region5;
+};
+
+/* for master such as MPU and FPGA */
+struct socfpga_noc_fw_ddr_mpu_fpga2sdram {
+	u32 enable;
+	u32 enable_set;
+	u32 enable_clear;
+	u32 _pad_0xc_0xf;
+	u32 mpuregion0addr;
+	u32 mpuregion1addr;
+	u32 mpuregion2addr;
+	u32 mpuregion3addr;
+	u32 fpga2sdram0region0addr;
+	u32 fpga2sdram0region1addr;
+	u32 fpga2sdram0region2addr;
+	u32 fpga2sdram0region3addr;
+	u32 fpga2sdram1region0addr;
+	u32 fpga2sdram1region1addr;
+	u32 fpga2sdram1region2addr;
+	u32 fpga2sdram1region3addr;
+	u32 fpga2sdram2region0addr;
+	u32 fpga2sdram2region1addr;
+	u32 fpga2sdram2region2addr;
+	u32 fpga2sdram2region3addr;
+};
+
+/* for L3 master */
+struct socfpga_noc_fw_ddr_l3 {
+	u32 enable;
+	u32 enable_set;
+	u32 enable_clear;
+	u32 hpsregion0addr;
+	u32 hpsregion1addr;
+	u32 hpsregion2addr;
+	u32 hpsregion3addr;
+	u32 hpsregion4addr;
+	u32 hpsregion5addr;
+	u32 hpsregion6addr;
+	u32 hpsregion7addr;
+};
+
+struct socfpga_io48_mmr {
+	u32 dbgcfg0;
+	u32 dbgcfg1;
+	u32 dbgcfg2;
+	u32 dbgcfg3;
+	u32 dbgcfg4;
+	u32 dbgcfg5;
+	u32 dbgcfg6;
+	u32 reserve0;
+	u32 reserve1;
+	u32 reserve2;
+	u32 ctrlcfg0;
+	u32 ctrlcfg1;
+	u32 ctrlcfg2;
+	u32 ctrlcfg3;
+	u32 ctrlcfg4;
+	u32 ctrlcfg5;
+	u32 ctrlcfg6;
+	u32 ctrlcfg7;
+	u32 ctrlcfg8;
+	u32 ctrlcfg9;
+	u32 dramtiming0;
+	u32 dramodt0;
+	u32 dramodt1;
+	u32 sbcfg0;
+	u32 sbcfg1;
+	u32 sbcfg2;
+	u32 sbcfg3;
+	u32 sbcfg4;
+	u32 sbcfg5;
+	u32 sbcfg6;
+	u32 sbcfg7;
+	u32 caltiming0;
+	u32 caltiming1;
+	u32 caltiming2;
+	u32 caltiming3;
+	u32 caltiming4;
+	u32 caltiming5;
+	u32 caltiming6;
+	u32 caltiming7;
+	u32 caltiming8;
+	u32 caltiming9;
+	u32 caltiming10;
+	u32 dramaddrw;
+	u32 sideband0;
+	u32 sideband1;
+	u32 sideband2;
+	u32 sideband3;
+	u32 sideband4;
+	u32 sideband5;
+	u32 sideband6;
+	u32 sideband7;
+	u32 sideband8;
+	u32 sideband9;
+	u32 sideband10;
+	u32 sideband11;
+	u32 sideband12;
+	u32 sideband13;
+	u32 sideband14;
+	u32 sideband15;
+	u32 dramsts;
+	u32 dbgdone;
+	u32 dbgsignals;
+	u32 dbgreset;
+	u32 dbgmatch;
+	u32 counter0mask;
+	u32 counter1mask;
+	u32 counter0match;
+	u32 counter1match;
+	u32 niosreserve0;
+	u32 niosreserve1;
+	u32 niosreserve2;
+};
+#endif /*__ASSEMBLY__*/
+
+#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK		0x1F000000
+#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_SHIFT	24
+#define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_MASK		0x00F80000
+#define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_SHIFT	19
+#define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_MASK		0x0007C000
+#define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_SHIFT	14
+#define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK	0x00003E00
+#define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT	9
+#define IO48_MMR_CTRLCFG0_AC_POS_MASK			0x00000180
+#define IO48_MMR_CTRLCFG0_AC_POS_SHIFT			7
+#define IO48_MMR_CTRLCFG0_DIMM_TYPE_MASK		0x00000070
+#define IO48_MMR_CTRLCFG0_DIM_TYPE_SHIFT		4
+#define IO48_MMR_CTRLCFG0_MEM_TYPE_MASK			0x0000000F
+#define IO48_MMR_CTRLCFG0_MEM_TYPE_SHIFT		0
+
+#define IO48_MMR_CTRLCFG1_DBC3_ENABLE_DM		BIT(30)
+#define IO48_MMR_CTRLCFG1_DBC2_ENABLE_DM		BIT(29)
+#define IO48_MMR_CTRLCFG1_DBC1_ENABLE_DM		BIT(28)
+#define IO48_MMR_CTRLCFG1_DBC0_ENABLE_DM		BIT(27)
+#define IO48_MMR_CTRLCFG1_CTRL_ENABLE_DM		BIT(26)
+#define IO48_MMR_CTRLCFG1_DQSTRK_EN			BIT(25)
+#define IO48_MMR_CTRLCFG1_STARVE_LIMIT_MASK		0x01F80000
+#define IO48_MMR_CTRLCFG1_STARVE_LIMIT_SHIFT		19
+#define IO48_MMR_CTRLCFG1_REORDER_READ			BIT(18)
+#define IO48_MMR_CTRLCFG1_DBC3_REORDER_RDATA		BIT(17)
+#define IO48_MMR_CTRLCFG1_DBC2_REORDER_RDATA		BIT(16)
+#define IO48_MMR_CTRLCFG1_DBC1_REORDER_RDATA		BIT(15)
+#define IO48_MMR_CTRLCFG1_DBC0_REORDER_RDATA		BIT(14)
+#define IO48_MMR_CTRLCFG1_CTRL_REORDER_RDATA		BIT(13)
+#define IO48_MMR_CTRLCFG1_REORDER_DATA			BIT(12)
+#define IO48_MMR_CTRLCFG1_DBC3_ENABLE_ECC		BIT(11)
+#define IO48_MMR_CTRLCFG1_DBC2_ENABLE_ECC		BIT(10)
+#define IO48_MMR_CTRLCFG1_DBC1_ENABLE_ECC		BIT(9)
+#define IO48_MMR_CTRLCFG1_DBC0_ENABLE_ECC		BIT(8)
+#define IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC		BIT(7)
+#define IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK		0x00000060
+#define IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT		5
+#define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_MASK	0x0000001F
+#define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_SHIFT	0
+
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_MASK		0x3F000000
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_SHIFT	24
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK	0x00FC0000
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT	18
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK			0x0003F000
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT		12
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_MASK			0x00000FC0
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_SHIFT		6
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK		0x0000003F
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_SHIFT		0
+
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK		0x3F000000
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT	24
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK			0x00FC0000
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT			18
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_MASK		0x0003F000
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_SHIFT		12
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK		0x00000FC0
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT		6
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_MASK			0x0000003F
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_SHIFT			0
+
+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_MASK		0x3F000000
+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_SHIFT	24
+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_MASK			0x00FC0000
+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_SHIFT			18
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_MASK		0x0003F000
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_SHIFT		12
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK			0x00000FC0
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT			6
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_MASK		0x0000003F
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_SHIFT		0
+
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_MASK			0x3F000000
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_SHIFT			24
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_MASK		0x00FC0000
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_SHIFT		18
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK		0x0003F000
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT	12
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK			0x00000FC0
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT			6
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_MASK		0x0000003F
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_SHIFT		0
+
+#define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_MASK		0xFC000000
+#define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_SHIFT		26
+#define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_MASK		0x03FC0000
+#define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_SHIFT		18
+#define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_MASK		0x0003F000
+#define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_SHIFT		12
+#define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK		0x00000FC0
+#define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT		6
+#define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_MASK		0x0000003F
+#define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_SHIFT		0
+
+#define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK		0x000000FF
+#define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_SHIFT		0
+
+#define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK		0x00070000
+#define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT		16
+#define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK	0x0000C000
+#define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT	14
+#define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK		0x00003C00
+#define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT		10
+#define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK		0x000003E0
+#define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT		5
+#define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK		0x0000001F
+#define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SHIFT		0
+
+#define ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK		0x00000003
+
+#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET_MSK	BIT(0)
+#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET_MSK	BIT(1)
+#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET_MSK	BIT(0)
+#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET_MSK	BIT(1)
+#define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_SET_MSK		BIT(16)
+#define ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK	BIT(16)
+#define ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK		BIT(8)
+#define ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK		BIT(0)
+#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK		BIT(8)
+#define ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK		BIT(0)
+
+#define ALT_ECC_HMC_OCP_SERRCNTREG_VALUE		8
+
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB	0
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB	6
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB	12
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB	18
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB	21
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB	26
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB	31
+
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB	0
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB	1
+
+#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB	0
+#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB	4
+#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB	10
+
+#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB	0
+#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB	2
+#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB	4
+
+#define ALT_NOC_FW_DDR_END_ADDR_LSB	16
+#define ALT_NOC_FW_DDR_ADDR_MASK	0xFFFF
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK		BIT(0)
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK		BIT(1)
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK		BIT(2)
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK		BIT(3)
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK		BIT(4)
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK		BIT(5)
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK		BIT(6)
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK		BIT(7)
+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK		BIT(0)
+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK		BIT(1)
+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK		BIT(2)
+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK		BIT(3)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK	BIT(4)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK	BIT(5)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK	BIT(6)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK	BIT(7)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK	BIT(8)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK	BIT(9)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK	BIT(10)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK	BIT(11)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK	BIT(12)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK	BIT(13)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK	BIT(14)
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK	BIT(15)
+
+#define ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK		0x0000003F
+#endif /* _SOCFPGA_SDRAM_ARRIA10_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
index c45edea..e6d4280 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -1,139 +1,24 @@
 /*
- * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef	_SYSTEM_MANAGER_H_
-#define	_SYSTEM_MANAGER_H_
+#ifndef _SYSTEM_MANAGER_H_
+#define _SYSTEM_MANAGER_H_
 
-#ifndef __ASSEMBLY__
-
-void sysmgr_pinmux_init(void);
-void sysmgr_config_warmrstcfgio(int enable);
-
-void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
-#endif
-
-struct socfpga_system_manager {
-	/* System Manager Module */
-	u32	siliconid1;			/* 0x00 */
-	u32	siliconid2;
-	u32	_pad_0x8_0xf[2];
-	u32	wddbg;				/* 0x10 */
-	u32	bootinfo;
-	u32	hpsinfo;
-	u32	parityinj;
-	/* FPGA Interface Group */
-	u32	fpgaintfgrp_gbl;		/* 0x20 */
-	u32	fpgaintfgrp_indiv;
-	u32	fpgaintfgrp_module;
-	u32	_pad_0x2c_0x2f;
-	/* Scan Manager Group */
-	u32	scanmgrgrp_ctrl;		/* 0x30 */
-	u32	_pad_0x34_0x3f[3];
-	/* Freeze Control Group */
-	u32	frzctrl_vioctrl;		/* 0x40 */
-	u32	_pad_0x44_0x4f[3];
-	u32	frzctrl_hioctrl;		/* 0x50 */
-	u32	frzctrl_src;
-	u32	frzctrl_hwctrl;
-	u32	_pad_0x5c_0x5f;
-	/* EMAC Group */
-	u32	emacgrp_ctrl;			/* 0x60 */
-	u32	emacgrp_l3master;
-	u32	_pad_0x68_0x6f[2];
-	/* DMA Controller Group */
-	u32	dmagrp_ctrl;			/* 0x70 */
-	u32	dmagrp_persecurity;
-	u32	_pad_0x78_0x7f[2];
-	/* Preloader (initial software) Group */
-	u32	iswgrp_handoff[8];		/* 0x80 */
-	u32	_pad_0xa0_0xbf[8];		/* 0xa0 */
-	/* Boot ROM Code Register Group */
-	u32	romcodegrp_ctrl;		/* 0xc0 */
-	u32	romcodegrp_cpu1startaddr;
-	u32	romcodegrp_initswstate;
-	u32	romcodegrp_initswlastld;
-	u32	romcodegrp_bootromswstate;	/* 0xd0 */
-	u32	__pad_0xd4_0xdf[3];
-	/* Warm Boot from On-Chip RAM Group */
-	u32	romcodegrp_warmramgrp_enable;	/* 0xe0 */
-	u32	romcodegrp_warmramgrp_datastart;
-	u32	romcodegrp_warmramgrp_length;
-	u32	romcodegrp_warmramgrp_execution;
-	u32	romcodegrp_warmramgrp_crc;	/* 0xf0 */
-	u32	__pad_0xf4_0xff[3];
-	/* Boot ROM Hardware Register Group */
-	u32	romhwgrp_ctrl;			/* 0x100 */
-	u32	_pad_0x104_0x107;
-	/* SDMMC Controller Group */
-	u32	sdmmcgrp_ctrl;
-	u32	sdmmcgrp_l3master;
-	/* NAND Flash Controller Register Group */
-	u32	nandgrp_bootstrap;		/* 0x110 */
-	u32	nandgrp_l3master;
-	/* USB Controller Group */
-	u32	usbgrp_l3master;
-	u32	_pad_0x11c_0x13f[9];
-	/* ECC Management Register Group */
-	u32	eccgrp_l2;			/* 0x140 */
-	u32	eccgrp_ocram;
-	u32	eccgrp_usb0;
-	u32	eccgrp_usb1;
-	u32	eccgrp_emac0;			/* 0x150 */
-	u32	eccgrp_emac1;
-	u32	eccgrp_dma;
-	u32	eccgrp_can0;
-	u32	eccgrp_can1;			/* 0x160 */
-	u32	eccgrp_nand;
-	u32	eccgrp_qspi;
-	u32	eccgrp_sdmmc;
-	u32	_pad_0x170_0x3ff[164];
-	/* Pin Mux Control Group */
-	u32	emacio[20];			/* 0x400 */
-	u32	flashio[12];			/* 0x450 */
-	u32	generalio[28];			/* 0x480 */
-	u32	_pad_0x4f0_0x4ff[4];
-	u32	mixed1io[22];			/* 0x500 */
-	u32	mixed2io[8];			/* 0x558 */
-	u32	gplinmux[23];			/* 0x578 */
-	u32	gplmux[71];			/* 0x5d4 */
-	u32	nandusefpga;			/* 0x6f0 */
-	u32	_pad_0x6f4;
-	u32	rgmii1usefpga;			/* 0x6f8 */
-	u32	_pad_0x6fc_0x700[2];
-	u32	i2c0usefpga;			/* 0x704 */
-	u32	sdmmcusefpga;			/* 0x708 */
-	u32	_pad_0x70c_0x710[2];
-	u32	rgmii0usefpga;			/* 0x714 */
-	u32	_pad_0x718_0x720[3];
-	u32	i2c3usefpga;			/* 0x724 */
-	u32	i2c2usefpga;			/* 0x728 */
-	u32	i2c1usefpga;			/* 0x72c */
-	u32	spim1usefpga;			/* 0x730 */
-	u32	_pad_0x734;
-	u32	spim0usefpga;			/* 0x738 */
-};
-
-#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX	(1 << 0)
-#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO	(1 << 1)
-#define SYSMGR_ECC_OCRAM_EN	(1 << 0)
-#define SYSMGR_ECC_OCRAM_SERR	(1 << 3)
-#define SYSMGR_ECC_OCRAM_DERR	(1 << 4)
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX	BIT(0)
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO	BIT(1)
+#define SYSMGR_ECC_OCRAM_EN	BIT(0)
+#define SYSMGR_ECC_OCRAM_SERR	BIT(3)
+#define SYSMGR_ECC_OCRAM_DERR	BIT(4)
 #define SYSMGR_FPGAINTF_USEFPGA	0x1
-#define SYSMGR_FPGAINTF_SPIM0	(1 << 0)
-#define SYSMGR_FPGAINTF_SPIM1	(1 << 1)
-#define SYSMGR_FPGAINTF_EMAC0	(1 << 2)
-#define SYSMGR_FPGAINTF_EMAC1	(1 << 3)
-#define SYSMGR_FPGAINTF_NAND	(1 << 4)
-#define SYSMGR_FPGAINTF_SDMMC	(1 << 5)
-
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#define SYSMGR_SDMMC_SMPLSEL_SHIFT	3
-#else
-#define SYSMGR_SDMMC_SMPLSEL_SHIFT	4
-#endif
+#define SYSMGR_FPGAINTF_SPIM0	BIT(0)
+#define SYSMGR_FPGAINTF_SPIM1	BIT(1)
+#define SYSMGR_FPGAINTF_EMAC0	BIT(2)
+#define SYSMGR_FPGAINTF_EMAC1	BIT(3)
+#define SYSMGR_FPGAINTF_NAND	BIT(4)
+#define SYSMGR_FPGAINTF_SDMMC	BIT(5)
 
 #define SYSMGR_SDMMC_DRVSEL_SHIFT	0
 
@@ -146,4 +31,63 @@ struct socfpga_system_manager {
 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB			2
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			0x3
 
+/* For dedicated IO configuration */
+/* Voltage select enums */
+#define VOLTAGE_SEL_3V		0x0
+#define VOLTAGE_SEL_1P8V	0x1
+#define VOLTAGE_SEL_2P5V	0x2
+
+/* Input buffer enable */
+#define INPUT_BUF_DISABLE	0
+#define INPUT_BUF_1P8V		1
+#define INPUT_BUF_2P5V3V	2
+
+/* Weak pull up enable */
+#define WK_PU_DISABLE		0
+#define WK_PU_ENABLE		1
+
+/* Pull up slew rate control */
+#define PU_SLW_RT_SLOW		0
+#define PU_SLW_RT_FAST		1
+#define PU_SLW_RT_DEFAULT	PU_SLW_RT_SLOW
+
+/* Pull down slew rate control */
+#define PD_SLW_RT_SLOW		0
+#define PD_SLW_RT_FAST		1
+#define PD_SLW_RT_DEFAULT	PD_SLW_RT_SLOW
+
+/* Drive strength control */
+#define PU_DRV_STRG_DEFAULT	0x10
+#define PD_DRV_STRG_DEFAULT	0x10
+
+/* bit position */
+#define PD_DRV_STRG_LSB		0
+#define PD_SLW_RT_LSB		5
+#define PU_DRV_STRG_LSB		8
+#define PU_SLW_RT_LSB		13
+#define WK_PU_LSB		16
+#define INPUT_BUF_LSB		17
+#define BIAS_TRIM_LSB		19
+#define VOLTAGE_SEL_LSB		0
+
+#define ALT_SYSMGR_NOC_H2F_SET_MSK	BIT(0)
+#define ALT_SYSMGR_NOC_LWH2F_SET_MSK	BIT(4)
+#define ALT_SYSMGR_NOC_F2H_SET_MSK	BIT(8)
+#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK	BIT(16)
+#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK	BIT(20)
+#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK	BIT(24)
+#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK	BIT(0)
+
+#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK	BIT(1)
+#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK	BIT(1)
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/system_manager_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/system_manager_arria10.h>
+#endif
+
+#define SYSMGR_GET_BOOTINFO_BSEL(bsel)		\
+		(((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
+
 #endif /* _SYSTEM_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
new file mode 100644
index 0000000..f235aba
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _SYSTEM_MANAGER_ARRIA10_H_
+#define _SYSTEM_MANAGER_ARRIA10_H_
+
+struct socfpga_system_manager {
+	u32  siliconid1;
+	u32  siliconid2;
+	u32  wddbg;
+	u32  bootinfo;
+	u32  mpu_ctrl_l2_ecc;
+	u32  _pad_0x14_0x1f[3];
+	u32  dma;
+	u32  dma_periph;
+	u32  sdmmcgrp_ctrl;
+	u32  sdmmc_l3master;
+	u32  nand_bootstrap;
+	u32  nand_l3master;
+	u32  usb0_l3master;
+	u32  usb1_l3master;
+	u32  emac_global;
+	u32  emac[3];
+	u32  _pad_0x50_0x5f[4];
+	u32  fpgaintf_en_global;
+	u32  fpgaintf_en_0;
+	u32  fpgaintf_en_1;
+	u32  fpgaintf_en_2;
+	u32  fpgaintf_en_3;
+	u32  _pad_0x74_0x7f[3];
+	u32  noc_addr_remap_value;
+	u32  noc_addr_remap_set;
+	u32  noc_addr_remap_clear;
+	u32  _pad_0x8c_0x8f;
+	u32  ecc_intmask_value;
+	u32  ecc_intmask_set;
+	u32  ecc_intmask_clr;
+	u32  ecc_intstatus_serr;
+	u32  ecc_intstatus_derr;
+	u32  mpu_status_l2_ecc;
+	u32  mpu_clear_l2_ecc;
+	u32  mpu_status_l1_parity;
+	u32  mpu_clear_l1_parity;
+	u32  mpu_set_l1_parity;
+	u32  _pad_0xb8_0xbf[2];
+	u32  noc_timeout;
+	u32  noc_idlereq_set;
+	u32  noc_idlereq_clr;
+	u32  noc_idlereq_value;
+	u32  noc_idleack;
+	u32  noc_idlestatus;
+	u32  fpga2soc_ctrl;
+	u32  _pad_0xdc_0xff[9];
+	u32  tsmc_tsel_0;
+	u32  tsmc_tsel_1;
+	u32  tsmc_tsel_2;
+	u32  tsmc_tsel_3;
+	u32  _pad_0x110_0x200[60];
+	u32  romhw_ctrl;
+	u32  romcode_ctrl;
+	u32  romcode_cpu1startaddr;
+	u32  romcode_initswstate;
+	u32  romcode_initswlastld;
+	u32  _pad_0x214_0x217;
+	u32  warmram_enable;
+	u32  warmram_datastart;
+	u32  warmram_length;
+	u32  warmram_execution;
+	u32  warmram_crc;
+	u32  _pad_0x22c_0x22f;
+	u32  isw_handoff[8];
+	u32  romcode_bootromswstate[8];
+};
+
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT	4
+#define SYSMGR_BOOTINFO_BSEL_SHIFT	12
+
+#endif /* _SYSTEM_MANAGER_ARRIA10_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
new file mode 100644
index 0000000..285c1a2
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SYSTEM_MANAGER_GEN5_H_
+#define _SYSTEM_MANAGER_GEN5_H_
+
+#ifndef __ASSEMBLY__
+
+void sysmgr_pinmux_init(void);
+void sysmgr_config_warmrstcfgio(int enable);
+
+void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
+
+struct socfpga_system_manager {
+	/* System Manager Module */
+	u32	siliconid1;			/* 0x00 */
+	u32	siliconid2;
+	u32	_pad_0x8_0xf[2];
+	u32	wddbg;				/* 0x10 */
+	u32	bootinfo;
+	u32	hpsinfo;
+	u32	parityinj;
+	/* FPGA Interface Group */
+	u32	fpgaintfgrp_gbl;		/* 0x20 */
+	u32	fpgaintfgrp_indiv;
+	u32	fpgaintfgrp_module;
+	u32	_pad_0x2c_0x2f;
+	/* Scan Manager Group */
+	u32	scanmgrgrp_ctrl;		/* 0x30 */
+	u32	_pad_0x34_0x3f[3];
+	/* Freeze Control Group */
+	u32	frzctrl_vioctrl;		/* 0x40 */
+	u32	_pad_0x44_0x4f[3];
+	u32	frzctrl_hioctrl;		/* 0x50 */
+	u32	frzctrl_src;
+	u32	frzctrl_hwctrl;
+	u32	_pad_0x5c_0x5f;
+	/* EMAC Group */
+	u32	emacgrp_ctrl;			/* 0x60 */
+	u32	emacgrp_l3master;
+	u32	_pad_0x68_0x6f[2];
+	/* DMA Controller Group */
+	u32	dmagrp_ctrl;			/* 0x70 */
+	u32	dmagrp_persecurity;
+	u32	_pad_0x78_0x7f[2];
+	/* Preloader (initial software) Group */
+	u32	iswgrp_handoff[8];		/* 0x80 */
+	u32	_pad_0xa0_0xbf[8];		/* 0xa0 */
+	/* Boot ROM Code Register Group */
+	u32	romcodegrp_ctrl;		/* 0xc0 */
+	u32	romcodegrp_cpu1startaddr;
+	u32	romcodegrp_initswstate;
+	u32	romcodegrp_initswlastld;
+	u32	romcodegrp_bootromswstate;	/* 0xd0 */
+	u32	__pad_0xd4_0xdf[3];
+	/* Warm Boot from On-Chip RAM Group */
+	u32	romcodegrp_warmramgrp_enable;	/* 0xe0 */
+	u32	romcodegrp_warmramgrp_datastart;
+	u32	romcodegrp_warmramgrp_length;
+	u32	romcodegrp_warmramgrp_execution;
+	u32	romcodegrp_warmramgrp_crc;	/* 0xf0 */
+	u32	__pad_0xf4_0xff[3];
+	/* Boot ROM Hardware Register Group */
+	u32	romhwgrp_ctrl;			/* 0x100 */
+	u32	_pad_0x104_0x107;
+	/* SDMMC Controller Group */
+	u32	sdmmcgrp_ctrl;
+	u32	sdmmcgrp_l3master;
+	/* NAND Flash Controller Register Group */
+	u32	nandgrp_bootstrap;		/* 0x110 */
+	u32	nandgrp_l3master;
+	/* USB Controller Group */
+	u32	usbgrp_l3master;
+	u32	_pad_0x11c_0x13f[9];
+	/* ECC Management Register Group */
+	u32	eccgrp_l2;			/* 0x140 */
+	u32	eccgrp_ocram;
+	u32	eccgrp_usb0;
+	u32	eccgrp_usb1;
+	u32	eccgrp_emac0;			/* 0x150 */
+	u32	eccgrp_emac1;
+	u32	eccgrp_dma;
+	u32	eccgrp_can0;
+	u32	eccgrp_can1;			/* 0x160 */
+	u32	eccgrp_nand;
+	u32	eccgrp_qspi;
+	u32	eccgrp_sdmmc;
+	u32	_pad_0x170_0x3ff[164];
+	/* Pin Mux Control Group */
+	u32	emacio[20];			/* 0x400 */
+	u32	flashio[12];			/* 0x450 */
+	u32	generalio[28];			/* 0x480 */
+	u32	_pad_0x4f0_0x4ff[4];
+	u32	mixed1io[22];			/* 0x500 */
+	u32	mixed2io[8];			/* 0x558 */
+	u32	gplinmux[23];			/* 0x578 */
+	u32	gplmux[71];			/* 0x5d4 */
+	u32	nandusefpga;			/* 0x6f0 */
+	u32	_pad_0x6f4;
+	u32	rgmii1usefpga;			/* 0x6f8 */
+	u32	_pad_0x6fc_0x700[2];
+	u32	i2c0usefpga;			/* 0x704 */
+	u32	sdmmcusefpga;			/* 0x708 */
+	u32	_pad_0x70c_0x710[2];
+	u32	rgmii0usefpga;			/* 0x714 */
+	u32	_pad_0x718_0x720[3];
+	u32	i2c3usefpga;			/* 0x724 */
+	u32	i2c2usefpga;			/* 0x728 */
+	u32	i2c1usefpga;			/* 0x72c */
+	u32	spim1usefpga;			/* 0x730 */
+	u32	_pad_0x734;
+	u32	spim0usefpga;			/* 0x738 */
+};
+#endif
+
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT	3
+#define SYSMGR_BOOTINFO_BSEL_SHIFT	0
+
+#endif /* _SYSTEM_MANAGER_GEN5_H_ */