diff options
Diffstat (limited to 'arch/arm')
39 files changed, 396 insertions, 152 deletions
diff --git a/arch/arm/dts/rk3036-sdk-u-boot.dtsi b/arch/arm/dts/rk3036-sdk-u-boot.dtsi new file mode 100644 index 0000000..6f15f4a --- /dev/null +++ b/arch/arm/dts/rk3036-sdk-u-boot.dtsi @@ -0,0 +1,11 @@ +&uart2 { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts index ccdac1c..37137c2 100644 --- a/arch/arm/dts/rk3229-evb.dts +++ b/arch/arm/dts/rk3229-evb.dts @@ -75,3 +75,7 @@ &uart2 { status = "okay"; }; + +&usb20_otg { + status = "okay"; +}; diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi index 7237da4..4f2a1f6 100644 --- a/arch/arm/dts/rk322x.dtsi +++ b/arch/arm/dts/rk322x.dtsi @@ -403,6 +403,16 @@ status = "disabled"; }; + usb20_otg: usb@30040000 { + compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb", + "snps,dwc2"; + reg = <0x30040000 0x40000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + hnp-srp-disable; + dr_mode = "otg"; + status = "disabled"; + }; + gmac: ethernet@30200000 { compatible = "rockchip,rk3228-gmac"; reg = <0x30200000 0x10000>; diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi index fd463f4..02d1196 100644 --- a/arch/arm/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/dts/rk3288-phycore-som.dtsi @@ -61,6 +61,7 @@ aliases { rtc0 = &i2c_rtc; rtc1 = &rk818; + eeprom0 = &i2c_eeprom_id; }; ext_gmac: external-gmac-clock { @@ -383,6 +384,13 @@ pagesize = <32>; }; + /* M24C32-D Identification page */ + i2c_eeprom_id: eeprom@58 { + compatible = "atmel,24c32"; + reg = <0x58>; + pagesize = <32>; + }; + vdd_cpu: regulator@60 { compatible = "fcs,fan53555"; reg = <0x60>; diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts index 91d3193..3d3f507 100644 --- a/arch/arm/dts/rk3399-firefly.dts +++ b/arch/arm/dts/rk3399-firefly.dts @@ -8,7 +8,7 @@ #include <dt-bindings/pwm/pwm.h> #include <dt-bindings/pinctrl/rockchip.h> #include "rk3399.dtsi" -#include "rk3399-sdram-ddr3-1333.dtsi" +#include "rk3399-sdram-ddr3-1600.dtsi" / { model = "Firefly-RK3399 Board"; @@ -157,8 +157,9 @@ regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <800000>; + regulator-min-microvolt = <430000>; regulator-max-microvolt = <1400000>; + regulator-init-microvolt = <950000>; }; vccadc_ref: vccadc-ref { diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 1aad6c5..dd1baea 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -12,7 +12,9 @@ compatible = "tsd,rk3399-q7", "tsd,puma", "rockchip,rk3399"; config { - u-boot,spl-payload-offset = <0x40000>; /* 256kbyte */ + u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */ + u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */ + u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */ u-boot,boot-led = "module_led"; }; diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts b/arch/arm/dts/sun7i-a20-pcduino3.dts index 1a8b39b..37b1e0e 100644 --- a/arch/arm/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/dts/sun7i-a20-pcduino3.dts @@ -164,7 +164,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ cd-inverted; status = "okay"; }; diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts index 62f89d0..f1c9705 100644 --- a/arch/arm/dts/tegra124-nyan-big.dts +++ b/arch/arm/dts/tegra124-nyan-big.dts @@ -8,7 +8,6 @@ aliases { console = &uarta; - stdout-path = &uarta; i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c400"; @@ -26,6 +25,10 @@ usb2 = "/usb@7d004000"; }; + chosen { + stdout-path = &uarta; + }; + host1x@50000000 { dc@54200000 { display-timings { diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h index 7346876..72d264b 100644 --- a/arch/arm/include/asm/arch-rockchip/boot0.h +++ b/arch/arm/include/asm/arch-rockchip/boot0.h @@ -1,3 +1,4 @@ + /* * Copyright 2017 Theobroma Systems Design und Consulting GmbH * @@ -13,7 +14,17 @@ */ #ifdef CONFIG_SPL_BUILD - .space 0x4 /* space for the 'RK33' */ + /* + * We need to add 4 bytes of space for the 'RK33' at the + * beginning of the executable. However, as we want to keep + * this generic and make it applicable to builds that are like + * the RK3368 (TPL needs this, SPL doesn't) or the RK3399 (no + * TPL, but extra space needed in the SPL), we simply repeat + * the 'b reset' with the expectation that the first one will + * be overwritten, if this is the first stage contained in the + * final image created with mkimage)... + */ + b reset /* may be overwritten --- should be 'nop' or a 'b reset' */ #endif b reset diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h index 4910ee7..24a9cc0 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h @@ -51,8 +51,6 @@ check_member(rk3368_cru, emmc_con[1], 0x41c); struct rk3368_clk_priv { struct rk3368_cru *cru; - ulong rate; - bool has_bwadj; }; enum { diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h index cf830d0..033f067 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -12,12 +12,10 @@ /* Private data for the clock driver - used by rockchip_get_cru() */ struct rk3399_clk_priv { struct rk3399_cru *cru; - ulong rate; }; struct rk3399_pmuclk_priv { struct rk3399_pmucru *pmucru; - ulong rate; }; struct rk3399_pmucru { diff --git a/arch/arm/include/asm/arch-rockchip/pwm.h b/arch/arm/include/asm/arch-rockchip/pwm.h index 08ff945..b1d8047 100644 --- a/arch/arm/include/asm/arch-rockchip/pwm.h +++ b/arch/arm/include/asm/arch-rockchip/pwm.h @@ -25,9 +25,11 @@ check_member(rk3288_pwm, ctrl, 0xc); #define PWM_DUTY_POSTIVE (1 << 3) #define PWM_DUTY_NEGATIVE (0 << 3) +#define PWM_DUTY_MASK (1 << 3) #define PWM_INACTIVE_POSTIVE (1 << 4) #define PWM_INACTIVE_NEGATIVE (0 << 4) +#define PWM_INACTIVE_MASK (1 << 4) #define PWM_OUTPUT_LEFT (0 << 5) #define PWM_OUTPUT_CENTER (1 << 5) diff --git a/arch/arm/include/asm/arch-rockchip/timer.h b/arch/arm/include/asm/arch-rockchip/timer.h index 1d044bb..c23c509 100644 --- a/arch/arm/include/asm/arch-rockchip/timer.h +++ b/arch/arm/include/asm/arch-rockchip/timer.h @@ -8,12 +8,12 @@ #define __ASM_ARCH_TIMER_H struct rk_timer { - unsigned int timer_load_count0; - unsigned int timer_load_count1; - unsigned int timer_curr_value0; - unsigned int timer_curr_value1; - unsigned int timer_ctrl_reg; - unsigned int timer_int_status; + u32 timer_load_count0; + u32 timer_load_count1; + u32 timer_curr_value0; + u32 timer_curr_value1; + u32 timer_ctrl_reg; + u32 timer_int_status; }; void rockchip_timer_init(void); diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index f62b2a4..92180db 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -266,7 +266,7 @@ void clock_ll_start_uart(enum periph_id periph_id); * @param node Node to look at * @return peripheral ID, or PERIPH_ID_NONE if none */ -enum periph_id clock_decode_periph_id(const void *blob, int node); +int clock_decode_periph_id(struct udevice *dev); /** * Checks if the oscillator bypass is enabled (XOBP bit) diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 3add1b3..3b9711d 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -97,6 +97,11 @@ enum { TEGRA_SOC_UNKNOWN = -1, }; +/* Tegra system controller (SYSCON) devices */ +enum { + TEGRA_SYSCON_PMC, +}; + #else /* __ASSEMBLY__ */ #define PRM_RSTCTRL NV_PA_PMC_BASE #endif diff --git a/arch/arm/include/asm/arch-tegra/xusb-padctl.h b/arch/arm/include/asm/arch-tegra/xusb-padctl.h index b4b4c8b..deccdf4 100644 --- a/arch/arm/include/asm/arch-tegra/xusb-padctl.h +++ b/arch/arm/include/asm/arch-tegra/xusb-padctl.h @@ -15,7 +15,7 @@ struct tegra_xusb_phy; */ struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type); -void tegra_xusb_padctl_init(const void *fdt); +void tegra_xusb_padctl_init(void); int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy); int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy); int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy); diff --git a/arch/arm/include/asm/ehci-omap.h b/arch/arm/include/asm/ehci-omap.h index 5a53e40..9dbb2c4 100644 --- a/arch/arm/include/asm/ehci-omap.h +++ b/arch/arm/include/asm/ehci-omap.h @@ -19,11 +19,7 @@ enum usbhs_omap_port_mode { OMAP_EHCI_PORT_MODE_HSIC, }; -#ifdef CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS -#define OMAP_HS_USB_PORTS CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS -#else #define OMAP_HS_USB_PORTS 3 -#endif #define is_ehci_phy_mode(x) ((x) == OMAP_EHCI_PORT_MODE_PHY) #define is_ehci_tll_mode(x) ((x) == OMAP_EHCI_PORT_MODE_TLL) diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 030b36f..2d54a31 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -112,8 +112,8 @@ int secure_boot_verify_image(void **image, size_t *size) /* Perform cache writeback on input buffer */ flush_dcache_range( - (u32)*image, - (u32)*image + roundup(*size, ARCH_DMA_MINALIGN)); + rounddown((u32)*image, ARCH_DMA_MINALIGN), + roundup((u32)*image + *size, ARCH_DMA_MINALIGN)); cert_addr = (uint32_t)*image; sig_addr = find_sig_start((char *)*image, *size); @@ -151,8 +151,8 @@ int secure_boot_verify_image(void **image, size_t *size) /* Perform cache writeback on output buffer */ flush_dcache_range( - (u32)*image, - (u32)*image + roundup(*size, ARCH_DMA_MINALIGN)); + rounddown((u32)*image, ARCH_DMA_MINALIGN), + roundup((u32)*image + *size, ARCH_DMA_MINALIGN)); auth_exit: if (result != 0) { diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index bb44c61..c924613 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -82,6 +82,8 @@ config ROCKCHIP_RK3399 select SUPPORT_SPL select SPL select SPL_SEPARATE_BSS + select SPL_SERIAL_SUPPORT + select SPL_DRIVERS_MISC_SUPPORT select ENABLE_ARM_SOC_BOOT0_HOOK select DEBUG_UART_BOARD_INIT help diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c index da36f92..4ca9962 100644 --- a/arch/arm/mach-rockchip/bootrom.c +++ b/arch/arm/mach-rockchip/bootrom.c @@ -9,8 +9,8 @@ void back_to_bootrom(void) { -#if defined(CONFIG_SPL_LIBGENERIC_SUPPORT) && !defined(CONFIG_TPL_BUILD) - printf("Returning to boot ROM..."); +#if defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && !defined(CONFIG_TPL_BUILD) + puts("Returning to boot ROM..."); #endif _back_to_bootrom_s(); } diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c index 7b8d0ee..9458201 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -53,9 +53,3 @@ void board_init_r(gd_t *id, ulong dest_addr) while (1) ; } - -void hang(void) -{ - while (1) - ; -} diff --git a/arch/arm/mach-rockchip/rk_timer.c b/arch/arm/mach-rockchip/rk_timer.c index ae5123d..853b986 100644 --- a/arch/arm/mach-rockchip/rk_timer.c +++ b/arch/arm/mach-rockchip/rk_timer.c @@ -4,9 +4,9 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <common.h> #include <asm/arch/timer.h> #include <asm/io.h> -#include <common.h> #include <linux/types.h> struct rk_timer * const timer_ptr = (void *)CONFIG_SYS_TIMER_BASE; diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 41b779c..286bfef 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -9,7 +9,6 @@ obj-y += board.o obj-y += clock_manager.o -obj-y += fpga_manager.o obj-y += misc.o obj-y += reset_manager.o obj-y += timer.o @@ -21,6 +20,7 @@ obj-y += reset_manager_gen5.o obj-y += scan_manager.o obj-y += system_manager_gen5.o obj-y += wrap_pll_config.o +obj-y += fpga_manager.o endif ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h index a077e22..a21c716 100644 --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Altera Corporation <www.altera.com> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -10,58 +10,11 @@ #include <altera.h> -struct socfpga_fpga_manager { - /* FPGA Manager Module */ - u32 stat; /* 0x00 */ - u32 ctrl; - u32 dclkcnt; - u32 dclkstat; - u32 gpo; /* 0x10 */ - u32 gpi; - u32 misci; /* 0x18 */ - u32 _pad_0x1c_0x82c[517]; - - /* Configuration Monitor (MON) Registers */ - u32 gpio_inten; /* 0x830 */ - u32 gpio_intmask; - u32 gpio_inttype_level; - u32 gpio_int_polarity; - u32 gpio_intstatus; /* 0x840 */ - u32 gpio_raw_intstatus; - u32 _pad_0x848; - u32 gpio_porta_eoi; - u32 gpio_ext_porta; /* 0x850 */ - u32 _pad_0x854_0x85c[3]; - u32 gpio_1s_sync; /* 0x860 */ - u32 _pad_0x864_0x868[2]; - u32 gpio_ver_id_code; - u32 gpio_config_reg2; /* 0x870 */ - u32 gpio_config_reg1; -}; - -#define FPGAMGRREGS_STAT_MODE_MASK 0x7 -#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 -#define FPGAMGRREGS_STAT_MSEL_LSB 3 - -#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200 -#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100 -#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4 -#define FPGAMGRREGS_CTRL_NCE_MASK 0x2 -#define FPGAMGRREGS_CTRL_EN_MASK 0x1 -#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 - -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1 - -/* FPGA Mode */ -#define FPGAMGRREGS_MODE_FPGAOFF 0x0 -#define FPGAMGRREGS_MODE_RESETPHASE 0x1 -#define FPGAMGRREGS_MODE_CFGPHASE 0x2 -#define FPGAMGRREGS_MODE_INITPHASE 0x3 -#define FPGAMGRREGS_MODE_USERMODE 0x4 -#define FPGAMGRREGS_MODE_UNKNOWN 0x5 +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#include <asm/arch/fpga_manager_gen5.h> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include <asm/arch/fpga_manager_arria10.h> +#endif /* FPGA CD Ratio Value */ #define CDRATIO_x1 0x0 @@ -69,9 +22,14 @@ struct socfpga_fpga_manager { #define CDRATIO_x4 0x2 #define CDRATIO_x8 0x3 -/* SoCFPGA support functions */ -int fpgamgr_test_fpga_ready(void); -int fpgamgr_poll_fpga_ready(void); +#ifndef __ASSEMBLY__ + +/* Common prototypes */ int fpgamgr_get_mode(void); +int fpgamgr_poll_fpga_ready(void); +void fpgamgr_program_write(const void *rbf_data, size_t rbf_size); +int fpgamgr_test_fpga_ready(void); +int fpgamgr_dclkcnt_set(unsigned long cnt); +#endif /* __ASSEMBLY__ */ #endif /* _FPGA_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h new file mode 100644 index 0000000..9cbf696 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2017 Intel Corporation <www.intel.com> + * All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _FPGA_MANAGER_ARRIA10_H_ +#define _FPGA_MANAGER_ARRIA10_H_ + +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\ + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\ + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\ + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16 + +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24) + +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0) +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16) +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24) + +#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0) +#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8) +#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000 +#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24) +#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16 + +#ifndef __ASSEMBLY__ + +struct socfpga_fpga_manager { + u32 _pad_0x0_0x7[2]; + u32 dclkcnt; + u32 dclkstat; + u32 gpo; + u32 gpi; + u32 misci; + u32 _pad_0x1c_0x2f[5]; + u32 emr_data0; + u32 emr_data1; + u32 emr_data2; + u32 emr_data3; + u32 emr_data4; + u32 emr_data5; + u32 emr_valid; + u32 emr_en; + u32 jtag_config; + u32 jtag_status; + u32 jtag_kick; + u32 _pad_0x5c_0x5f; + u32 jtag_data_w; + u32 jtag_data_r; + u32 _pad_0x68_0x6f[2]; + u32 imgcfg_ctrl_00; + u32 imgcfg_ctrl_01; + u32 imgcfg_ctrl_02; + u32 _pad_0x7c_0x7f; + u32 imgcfg_stat; + u32 intr_masked_status; + u32 intr_mask; + u32 intr_polarity; + u32 dma_config; + u32 imgcfg_fifo_status; +}; + +/* Functions */ +int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size); +int fpgamgr_program_finish(void); +int is_fpgamgr_user_mode(void); +int fpgamgr_wait_early_user_mode(void); + +#endif /* __ASSEMBLY__ */ + +#endif /* _FPGA_MANAGER_ARRIA10_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h new file mode 100644 index 0000000..2de7a11 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FPGA_MANAGER_GEN5_H_ +#define _FPGA_MANAGER_GEN5_H_ + +#define FPGAMGRREGS_STAT_MODE_MASK 0x7 +#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 +#define FPGAMGRREGS_STAT_MSEL_LSB 3 + +#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9) +#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8) +#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2) +#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1) +#define FPGAMGRREGS_CTRL_EN_MASK BIT(0) +#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 + +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3) +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2) +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1) +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0) + +/* FPGA Mode */ +#define FPGAMGRREGS_MODE_FPGAOFF 0x0 +#define FPGAMGRREGS_MODE_RESETPHASE 0x1 +#define FPGAMGRREGS_MODE_CFGPHASE 0x2 +#define FPGAMGRREGS_MODE_INITPHASE 0x3 +#define FPGAMGRREGS_MODE_USERMODE 0x4 +#define FPGAMGRREGS_MODE_UNKNOWN 0x5 + +#ifndef __ASSEMBLY__ + +struct socfpga_fpga_manager { + /* FPGA Manager Module */ + u32 stat; /* 0x00 */ + u32 ctrl; + u32 dclkcnt; + u32 dclkstat; + u32 gpo; /* 0x10 */ + u32 gpi; + u32 misci; /* 0x18 */ + u32 _pad_0x1c_0x82c[517]; + + /* Configuration Monitor (MON) Registers */ + u32 gpio_inten; /* 0x830 */ + u32 gpio_intmask; + u32 gpio_inttype_level; + u32 gpio_int_polarity; + u32 gpio_intstatus; /* 0x840 */ + u32 gpio_raw_intstatus; + u32 _pad_0x848; + u32 gpio_porta_eoi; + u32 gpio_ext_porta; /* 0x850 */ + u32 _pad_0x854_0x85c[3]; + u32 gpio_1s_sync; /* 0x860 */ + u32 _pad_0x864_0x868[2]; + u32 gpio_ver_id_code; + u32 gpio_config_reg2; /* 0x870 */ + u32 gpio_config_reg1; +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* _FPGA_MANAGER_GEN5_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h index 7922db8..b6d7f4f 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h @@ -17,7 +17,7 @@ int socfpga_reset_deassert_bridges_handoff(void); void socfpga_reset_assert_fpga_connected_peripherals(void); void socfpga_reset_deassert_osc1wd0(void); void socfpga_reset_uart(int assert); -int socfpga_bridges_reset(int enable); +int socfpga_bridges_reset(void); struct socfpga_reset_manager { u32 stat; diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c index d8c858c..66f1ec2 100644 --- a/arch/arm/mach-socfpga/reset_manager_arria10.c +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -318,13 +318,13 @@ void socfpga_per_reset_all(void) } #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) -int socfpga_bridges_reset(int enable) +int socfpga_bridges_reset(void) { /* For SoCFPGA-VT, this is NOP. */ return 0; } #else -int socfpga_bridges_reset(int enable) +int socfpga_bridges_reset(void) { int ret; diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 4838758..58085dc 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -88,6 +88,8 @@ config TEGRA124 bool "Tegra124 family" select TEGRA_ARMV7_COMMON imply ENV_IS_IN_MMC + imply REGMAP + imply SYSCON config TEGRA210 bool "Tegra210 family" diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 6b5fa7d..bd13796 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -29,7 +29,6 @@ #ifdef CONFIG_TEGRA_CLOCK_SCALING #include <asm/arch/emc.h> #endif -#include <power/as3722.h> #include "emc.h" DECLARE_GLOBAL_DATA_PTR; @@ -142,11 +141,6 @@ int board_init(void) debug("Memory controller init failed: %d\n", err); # endif # endif /* CONFIG_TEGRA_PMU */ -#ifdef CONFIG_PMIC_AS3722 - err = as3722_init(NULL); - if (err && err != -ENODEV) - return err; -#endif #endif /* CONFIG_SYS_I2C_TEGRA */ #ifdef CONFIG_USB_EHCI_TEGRA @@ -166,7 +160,7 @@ int board_init(void) pin_mux_nand(); #endif - tegra_xusb_padctl_init(gd->fdt_blob); + tegra_xusb_padctl_init(); #ifdef CONFIG_TEGRA_LP0 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 668bbd2..dc58b30 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -655,14 +655,13 @@ void clock_ll_start_uart(enum periph_id periph_id) } #if CONFIG_IS_ENABLED(OF_CONTROL) -int clock_decode_periph_id(const void *blob, int node) +int clock_decode_periph_id(struct udevice *dev) { enum periph_id id; u32 cell[2]; int err; - err = fdtdec_get_int_array(blob, node, "clocks", cell, - ARRAY_SIZE(cell)); + err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell)); if (err) return -1; id = clk_id_to_periph_id(cell[1]); diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c index 41c88cb..189b3da 100644 --- a/arch/arm/mach-tegra/spl.c +++ b/arch/arm/mach-tegra/spl.c @@ -7,6 +7,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <debug_uart.h> #include <spl.h> #include <asm/io.h> @@ -32,6 +33,9 @@ void spl_board_init(void) gpio_early_init_uart(); clock_early_init(); +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif preloader_console_init(); } diff --git a/arch/arm/mach-tegra/tegra124/Makefile b/arch/arm/mach-tegra/tegra124/Makefile index c00de61..d275daf 100644 --- a/arch/arm/mach-tegra/tegra124/Makefile +++ b/arch/arm/mach-tegra/tegra124/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_SPL_BUILD) += cpu.o obj-y += clock.o obj-y += funcmux.o obj-y += pinmux.o +obj-y += pmc.o obj-y += xusb-padctl.o obj-y += ../xusb-padctl-common.o diff --git a/arch/arm/mach-tegra/tegra124/pmc.c b/arch/arm/mach-tegra/tegra124/pmc.c new file mode 100644 index 0000000..be82acf --- /dev/null +++ b/arch/arm/mach-tegra/tegra124/pmc.c @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2017 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> + +static const struct udevice_id tegra124_syscon_ids[] = { + { .compatible = "nvidia,tegra124-pmc", .data = TEGRA_SYSCON_PMC }, +}; + +U_BOOT_DRIVER(syscon_tegra124) = { + .name = "tegra124_syscon", + .id = UCLASS_SYSCON, + .of_match = tegra124_syscon_ids, +}; diff --git a/arch/arm/mach-tegra/tegra124/xusb-padctl.c b/arch/arm/mach-tegra/tegra124/xusb-padctl.c index 76af924..d326a6a 100644 --- a/arch/arm/mach-tegra/tegra124/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c @@ -8,6 +8,8 @@ #include <common.h> #include <errno.h> +#include <dm/of_access.h> +#include <dm/ofnode.h> #include "../xusb-padctl-common.h" @@ -317,13 +319,33 @@ static const struct tegra_xusb_padctl_soc tegra124_socdata = { .num_phys = ARRAY_SIZE(tegra124_phys), }; -void tegra_xusb_padctl_init(const void *fdt) +void tegra_xusb_padctl_init(void) { - int count, nodes[1]; + ofnode nodes[1]; + int count = 0; + int ret; + + debug("%s: start\n", __func__); + if (of_live_active()) { + struct device_node *np = of_find_compatible_node(NULL, NULL, + "nvidia,tegra124-xusb-padctl"); + + debug("np=%p\n", np); + if (np) { + nodes[0] = np_to_ofnode(np); + count = 1; + } + } else { + int node_offsets[1]; + int i; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl", + COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, + node_offsets, ARRAY_SIZE(node_offsets)); + for (i = 0; i < count; i++) + nodes[i] = offset_to_ofnode(node_offsets[i]); + } - count = fdtdec_find_aliases_for_id(fdt, "padctl", - COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, - nodes, ARRAY_SIZE(nodes)); - if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra124_socdata)) - return; + ret = tegra_xusb_process_nodes(nodes, count, &tegra124_socdata); + debug("%s: done, ret=%d\n", __func__, ret); } diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c index 9ec93e7..bf85e07 100644 --- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c @@ -8,6 +8,8 @@ #include <common.h> #include <errno.h> +#include <dm/of_access.h> +#include <dm/ofnode.h> #include "../xusb-padctl-common.h" @@ -15,6 +17,8 @@ #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> +DECLARE_GLOBAL_DATA_PTR; + enum tegra210_function { TEGRA210_FUNC_SNPS, TEGRA210_FUNC_XUSB, @@ -421,17 +425,33 @@ static const struct tegra_xusb_padctl_soc tegra210_socdata = { .num_phys = ARRAY_SIZE(tegra210_phys), }; -void tegra_xusb_padctl_init(const void *fdt) +void tegra_xusb_padctl_init(void) { - int count, nodes[1]; - - debug("> %s(fdt=%p)\n", __func__, fdt); - - count = fdtdec_find_aliases_for_id(fdt, "padctl", - COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL, - nodes, ARRAY_SIZE(nodes)); - if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra210_socdata)) - return; + ofnode nodes[1]; + int count = 0; + int ret; + + debug("%s: start\n", __func__); + if (of_live_active()) { + struct device_node *np = of_find_compatible_node(NULL, NULL, + "nvidia,tegra210-xusb-padctl"); + + debug("np=%p\n", np); + if (np) { + nodes[0] = np_to_ofnode(np); + count = 1; + } + } else { + int node_offsets[1]; + int i; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl", + COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL, + node_offsets, ARRAY_SIZE(node_offsets)); + for (i = 0; i < count; i++) + nodes[i] = offset_to_ofnode(node_offsets[i]); + } - debug("< %s()\n", __func__); + ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata); + debug("%s: done, ret=%d\n", __func__, ret); } diff --git a/arch/arm/mach-tegra/xusb-padctl-common.c b/arch/arm/mach-tegra/xusb-padctl-common.c index 43f5bb7..37b5b8f 100644 --- a/arch/arm/mach-tegra/xusb-padctl-common.c +++ b/arch/arm/mach-tegra/xusb-padctl-common.c @@ -75,14 +75,14 @@ tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name) static int tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl, struct tegra_xusb_padctl_group *group, - const void *fdt, int node) + ofnode node) { unsigned int i; - int len; + int len, ret; - group->name = fdt_get_name(fdt, node, &len); + group->name = ofnode_get_name(node); - len = fdt_stringlist_count(fdt, node, "nvidia,lanes"); + len = ofnode_read_string_count(node, "nvidia,lanes"); if (len < 0) { error("failed to parse \"nvidia,lanes\" property"); return -EINVAL; @@ -91,9 +91,9 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl, group->num_pins = len; for (i = 0; i < group->num_pins; i++) { - group->pins[i] = fdt_stringlist_get(fdt, node, "nvidia,lanes", - i, NULL); - if (!group->pins[i]) { + ret = ofnode_read_string_index(node, "nvidia,lanes", i, + &group->pins[i]); + if (ret) { error("failed to read string from \"nvidia,lanes\" property"); return -EINVAL; } @@ -101,13 +101,14 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl, group->num_pins = len; - group->func = fdt_stringlist_get(fdt, node, "nvidia,function", 0, NULL); - if (!group->func) { + ret = ofnode_read_string_index(node, "nvidia,function", 0, + &group->func); + if (ret) { error("failed to parse \"nvidia,func\" property"); return -EINVAL; } - group->iddq = fdtdec_get_int(fdt, node, "nvidia,iddq", -1); + group->iddq = ofnode_read_u32_default(node, "nvidia,iddq", -1); return 0; } @@ -217,20 +218,21 @@ tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl, static int tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl, struct tegra_xusb_padctl_config *config, - const void *fdt, int node) + ofnode node) { - int subnode; + ofnode subnode; - config->name = fdt_get_name(fdt, node, NULL); + config->name = ofnode_get_name(node); - fdt_for_each_subnode(subnode, fdt, node) { + for (subnode = ofnode_first_subnode(node); + ofnode_valid(subnode); + subnode = ofnode_next_subnode(subnode)) { struct tegra_xusb_padctl_group *group; int err; group = &config->groups[config->num_groups]; - err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt, - subnode); + err = tegra_xusb_padctl_group_parse_dt(padctl, group, subnode); if (err < 0) { error("failed to parse group %s", group->name); return err; @@ -243,20 +245,24 @@ tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl, } static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, - const void *fdt, int node) + ofnode node) { - int subnode, err; + ofnode subnode; + int err; - err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs); + err = ofnode_read_resource(node, 0, &padctl->regs); if (err < 0) { error("registers not found"); return err; } - fdt_for_each_subnode(subnode, fdt, node) { + for (subnode = ofnode_first_subnode(node); + ofnode_valid(subnode); + subnode = ofnode_next_subnode(subnode)) { struct tegra_xusb_padctl_config *config = &padctl->config; - err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt, + debug("%s: subnode=%s\n", __func__, ofnode_get_name(subnode)); + err = tegra_xusb_padctl_config_parse_dt(padctl, config, subnode); if (err < 0) { error("failed to parse entry %s: %d", @@ -264,25 +270,28 @@ static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, continue; } } + debug("%s: done\n", __func__); return 0; } struct tegra_xusb_padctl padctl; -int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count, - const struct tegra_xusb_padctl_soc *socdata) +int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count, + const struct tegra_xusb_padctl_soc *socdata) { unsigned int i; int err; + debug("%s: count=%d\n", __func__, count); for (i = 0; i < count; i++) { - if (!fdtdec_get_is_enabled(fdt, nodes[i])) + debug("%s: i=%d, node=%p\n", __func__, i, nodes[i].np); + if (!ofnode_is_available(nodes[i])) continue; padctl.socdata = socdata; - err = tegra_xusb_padctl_parse_dt(&padctl, fdt, nodes[i]); + err = tegra_xusb_padctl_parse_dt(&padctl, nodes[i]); if (err < 0) { error("failed to parse DT: %d", err); continue; @@ -300,6 +309,7 @@ int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count, /* only a single instance is supported */ break; } + debug("%s: done\n", __func__); return 0; } diff --git a/arch/arm/mach-tegra/xusb-padctl-common.h b/arch/arm/mach-tegra/xusb-padctl-common.h index f44790a..6836588 100644 --- a/arch/arm/mach-tegra/xusb-padctl-common.h +++ b/arch/arm/mach-tegra/xusb-padctl-common.h @@ -9,9 +9,11 @@ #include <common.h> #include <fdtdec.h> +#include <dm/ofnode.h> #include <asm/io.h> #include <asm/arch-tegra/xusb-padctl.h> +#include <linux/ioport.h> struct tegra_xusb_padctl_lane { const char *name; @@ -77,7 +79,7 @@ struct tegra_xusb_padctl_config { struct tegra_xusb_padctl { const struct tegra_xusb_padctl_soc *socdata; struct tegra_xusb_padctl_config config; - struct fdt_resource regs; + struct resource regs; unsigned int enable; }; @@ -95,7 +97,7 @@ static inline void padctl_writel(struct tegra_xusb_padctl *padctl, writel(value, padctl->regs.start + offset); } -int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count, - const struct tegra_xusb_padctl_soc *socdata); +int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count, + const struct tegra_xusb_padctl_soc *socdata); #endif diff --git a/arch/arm/mach-tegra/xusb-padctl-dummy.c b/arch/arm/mach-tegra/xusb-padctl-dummy.c index 65f8d2e..856d712 100644 --- a/arch/arm/mach-tegra/xusb-padctl-dummy.c +++ b/arch/arm/mach-tegra/xusb-padctl-dummy.c @@ -34,6 +34,6 @@ int __weak tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy) return -ENOSYS; } -void __weak tegra_xusb_padctl_init(const void *fdt) +void __weak tegra_xusb_padctl_init(void) { } |