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-rw-r--r--arch/powerpc/cpu/mpc85xx/Makefile3
-rw-r--r--arch/powerpc/cpu/mpc85xx/cmd_errata.c16
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c12
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c19
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init_early.c149
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init_nand.c12
-rw-r--r--arch/powerpc/cpu/mpc85xx/ddr-gen2.c28
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c4
-rw-r--r--arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c9
-rw-r--r--arch/powerpc/cpu/mpc85xx/liodn.c25
-rw-r--r--arch/powerpc/cpu/mpc85xx/mp.c27
-rw-r--r--arch/powerpc/cpu/mpc85xx/p3060_ids.c113
-rw-r--r--arch/powerpc/cpu/mpc85xx/p3060_serdes.c138
-rw-r--r--arch/powerpc/cpu/mpc85xx/p5020_ids.c13
-rw-r--r--arch/powerpc/cpu/mpc85xx/portals.c7
-rw-r--r--arch/powerpc/cpu/mpc85xx/speed.c7
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S289
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds18
18 files changed, 804 insertions, 85 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 7026bca..058d609 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -67,6 +67,7 @@ COBJS-$(CONFIG_P2020) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P2040) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_P3060) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
@@ -81,6 +82,7 @@ COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o
COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
+COBJS-$(CONFIG_PPC_P3060) += p3060_ids.o
COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
@@ -114,6 +116,7 @@ COBJS-$(CONFIG_P2020) += p2020_serdes.o
COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
+COBJS-$(CONFIG_PPC_P3060) += p3060_serdes.o
COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 7b9f773..a09eb91 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -87,6 +87,22 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
puts("Work-around for Erratum DDR111 enabled\n");
puts("Work-around for Erratum DDR134 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+ puts("Work-around for Erratum IFC-A002769 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+ puts("Work-around for Erratum P1010-A003549 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+ puts("Work-around for Erratum IFC A-003399 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+ if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
+ puts("Work-around for Erratum NMG DDR120 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
+ puts("Work-around for Erratum NMG_LBC103 enabled\n");
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 22fa461..49c0551 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -64,13 +64,11 @@ int checkcpu (void)
u32 ddr_ratio = 0;
#endif /* CONFIG_FSL_CORENET */
#endif /* CONFIG_DDR_CLK_FREQ */
- int i;
+ unsigned int i, core, nr_cores = cpu_numcores();
+ u32 mask = cpu_mask();
svr = get_svr();
major = SVR_MAJ(svr);
-#ifdef CONFIG_MPC8536
- major &= 0x7; /* the msb of this nibble is a mfg code */
-#endif
minor = SVR_MIN(svr);
if (cpu_numcores() > 1) {
@@ -119,11 +117,11 @@ int checkcpu (void)
get_sys_info(&sysinfo);
puts("Clock Configuration:");
- for (i = 0; i < cpu_numcores(); i++) {
+ for_each_cpu(i, core, nr_cores, mask) {
if (!(i & 3))
printf ("\n ");
- printf("CPU%d:%-4s MHz, ",
- i,strmhz(buf1, sysinfo.freqProcessor[i]));
+ printf("CPU%d:%-4s MHz, ", core,
+ strmhz(buf1, sysinfo.freqProcessor[core]));
}
printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 6aca166..0a4ce53 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -31,6 +31,7 @@
#include <asm/processor.h>
#include <ioports.h>
#include <sata.h>
+#include <fm_eth.h>
#include <asm/io.h>
#include <asm/cache.h>
#include <asm/mmu.h>
@@ -225,7 +226,9 @@ void cpu_init_f (void)
#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
-
+#if defined(CONFIG_SECURE_BOOT)
+ struct law_entry law;
+#endif
#ifdef CONFIG_MPC8548
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
uint svr = get_svr();
@@ -243,6 +246,13 @@ void cpu_init_f (void)
disable_tlb(14);
disable_tlb(15);
+#if defined(CONFIG_SECURE_BOOT)
+ /* Disable the LAW created for NOR flash by the PBI commands */
+ law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
+ if (law.index != -1)
+ disable_law(law.index);
+#endif
+
#ifdef CONFIG_CPM2
config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
#endif
@@ -453,6 +463,9 @@ skip_l2:
clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
__raw_readl(&lbc->lcrr);
isync();
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
+ udelay(100);
+#endif
#endif
#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
@@ -472,6 +485,10 @@ skip_l2:
}
#endif
+#ifdef CONFIG_FMAN_ENET
+ fman_enet_init();
+#endif
+
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 32aa94b..4ef3c9a 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009 Freescale Semiconductor, Inc
+ * Copyright 2009-2011 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -21,59 +21,59 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
-#ifdef CONFIG_FSL_CORENET
-static void setup_ccsrbar(void)
+#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+void setup_ifc(void)
{
- u32 temp;
- volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
- volatile ccsr_local_t *ccm;
+ struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+ u32 _mas0, _mas1, _mas2, _mas3, _mas7;
+ phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
/*
- * We can't call set_law() because we haven't moved
- * CCSR yet.
+ * Adjust the TLB we were running out of to match the phys addr of the
+ * chip select we are adjusting and will return to.
*/
- ccm = (void *)ccsr_virt;
-
- out_be32(&ccm->law[0].lawbarh,
- (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32);
- out_be32(&ccm->law[0].lawbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS);
- out_be32(&ccm->law[0].lawar,
- LAW_EN | (0x1e << 20) | LAW_SIZE_4K);
-
- in_be32((u32 *)(ccsr_virt + 0));
- in_be32((u32 *)(ccsr_virt + 1));
- isync();
-
- ccm = (void *)CONFIG_SYS_CCSRBAR;
- /* Now use the temporary LAW to move CCSR */
- out_be32(&ccm->ccsrbarh, (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32);
- out_be32(&ccm->ccsrbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS);
- out_be32(&ccm->ccsrar, CCSRAR_C);
- temp = in_be32(&ccm->ccsrar);
- disable_law(0);
-}
-#else
-static void setup_ccsrbar(void)
-{
- u32 temp;
- volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
+ flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
+
+ _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
+ _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
+ MAS1_TSIZE(BOOKE_PAGESZ_4M);
+ _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
+ _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
+ _mas7 = FSL_BOOKE_MAS7(flash_phys);
+
+ mtspr(MAS0, _mas0);
+ mtspr(MAS1, _mas1);
+ mtspr(MAS2, _mas2);
+ mtspr(MAS3, _mas3);
+ mtspr(MAS7, _mas7);
- temp = in_be32(ccsr_virt);
- out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
- temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
+ asm volatile("isync;msync;tlbwe;isync");
+
+ out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
+ out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
+ out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
+
+ return ;
}
#endif
-#endif
/* We run cpu_init_early_f in AS = 1 */
void cpu_init_early_f(void)
{
u32 mas0, mas1, mas2, mas3, mas7;
int i;
+#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+ ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+ u32 *l2srbar, *dst, *src;
+ void (*setup_ifc_sram)(void);
+#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@@ -85,28 +85,77 @@ void cpu_init_early_f(void)
for (i = 0; i < sizeof(gd_t); i++)
((char *)gd)[i] = 0;
- mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0);
- mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);
+ mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
+ mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
write_tlb(mas0, mas1, mas2, mas3, mas7);
- /* set up CCSR if we want it moved */
-#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
- mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);
- /* mas1 is the same as above */
- mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G);
- mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, MAS3_SW|MAS3_SR);
- mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT);
+/*
+ * Work Around for IFC Erratum A-003549. This issue is P1010
+ * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC
+ * Hence specifically selecting CS3.
+ */
+#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
+#endif
+
+ init_laws();
+
+/*
+ * Work Around for IFC Erratum A003399, issue will hit only when execution
+ * from NOR Flash
+ */
+#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+#define SRAM_BASE_ADDR (0x00000000)
+ /* TLB for SRAM */
+ mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
+ mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS |
+ MAS1_TSIZE(BOOKE_PAGESZ_1M);
+ mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I);
+ mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR);
+ mas7 = FSL_BOOKE_MAS7(0);
write_tlb(mas0, mas1, mas2, mas3, mas7);
- setup_ccsrbar();
+ out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);
+
+ out_be32(&l2cache->l2errdis,
+ (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
+
+ out_be32(&l2cache->l2ctl,
+ (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
+
+ /*
+ * Copy the code in setup_ifc to L2SRAM. Do a word copy
+ * because NOR Flash on P1010 does not support byte
+ * access (Erratum IFC-A002769)
+ */
+ setup_ifc_sram = (void *)SRAM_BASE_ADDR;
+ dst = (u32 *) SRAM_BASE_ADDR;
+ src = (u32 *) setup_ifc;
+ for (i = 0; i < 1024; i++)
+ *l2srbar++ = *src++;
+
+ setup_ifc_sram();
+
+ /* CLEANUP */
+ clrbits_be32(&l2cache->l2ctl,
+ (MPC85xx_L2CTL_L2E |
+ MPC85xx_L2CTL_L2SRAM_ENTIRE));
+ out_be32(&l2cache->l2srbar0, 0x0);
+#endif
+
+ invalidate_tlb(1);
+
+#if defined(CONFIG_SECURE_BOOT)
+ /* Disable the TLBs created by ISBC */
+ for (i = CONFIG_SYS_ISBC_START_TLB;
+ i < CONFIG_SYS_ISBC_START_TLB + CONFIG_SYS_ISBC_NUM_TLBS; i++)
+ disable_tlb(i);
#endif
- init_laws();
- invalidate_tlb(0);
init_tlbs();
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
index 796d398..f33db02 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
@@ -21,10 +21,12 @@
*/
#include <common.h>
+#include <asm/fsl_ifc.h>
#include <asm/io.h>
void cpu_init_f(void)
{
+#ifdef CONFIG_FSL_LBC
fsl_lbc_t *lbc = LBC_BASE_ADDR;
/*
@@ -39,6 +41,16 @@ void cpu_init_f(void)
#else
#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined
#endif
+#endif
+#ifdef CONFIG_FSL_IFC
+#ifndef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
+ set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
+ set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
+ set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
+#endif
+#endif
+#endif
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
index 655f99c..49000a1 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -8,6 +8,7 @@
#include <common.h>
#include <asm/io.h>
+#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
@@ -18,13 +19,36 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num)
{
unsigned int i;
- volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+#ifdef CONFIG_MPC83xx
+ ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC83xx_DDR_ADDR;
+#else
+ ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ uint svr;
+#endif
+#endif
if (ctrl_num) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
return;
}
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+ /*
+ * Set the DDR IO receiver to an acceptable bias point.
+ * Fixed in Rev 2.1.
+ */
+ svr = get_svr();
+ if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
+ if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
+ SDRAM_CFG_SDRAM_TYPE_DDR2)
+ out_be32(&gur->ddrioovcr, 0x90000000);
+ else
+ out_be32(&gur->ddrioovcr, 0xA8000000);
+ }
+#endif
+
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (i == 0) {
out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 8f13cd8..d20c94c 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -361,6 +361,7 @@ void fdt_add_enet_stashing(void *fdt)
}
#if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
+#ifdef CONFIG_SYS_DPAA_FMAN
static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
unsigned long freq)
{
@@ -374,12 +375,14 @@ static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
"for %s: %s\n", compat, fdt_strerror(off));
}
}
+#endif
static void ft_fixup_dpaa_clks(void *blob)
{
sys_info_t sysinfo;
get_sys_info(&sysinfo);
+#ifdef CONFIG_SYS_DPAA_FMAN
ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
sysinfo.freqFMan[0]);
@@ -387,6 +390,7 @@ static void ft_fixup_dpaa_clks(void *blob)
ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
sysinfo.freqFMan[1]);
#endif
+#endif
#ifdef CONFIG_SYS_DPAA_PME
do_fixup_by_compat_u32(blob, "fsl,pme",
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 4307a4c..07e58ed 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -482,6 +482,13 @@ static void wait_for_rstdone(unsigned int bank)
printf("SERDES: timeout resetting bank %u\n", bank + 1);
}
+
+void __soc_serdes_init(void)
+{
+ /* Allow for SoC-specific initialization in <SOC>_serdes.c */
+};
+void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init")));
+
void fsl_serdes_init(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -570,6 +577,8 @@ void fsl_serdes_init(void)
}
}
+ soc_serdes_init();
+
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
/*
* Bank two uses the clock from bank three, so if bank two is enabled,
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index bd19094..e0ea502 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -120,6 +120,19 @@ static void setup_pme_liodn_base(void)
#endif
}
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+static void setup_raide_liodn_base(void)
+{
+ struct ccsr_raide *raide = (void *)CONFIG_SYS_FSL_RAID_ENGINE_ADDR;
+
+ /* setup raid engine liodn base for data/desc ; both set to 47 */
+ u32 base = (liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0] << 16) |
+ liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0];
+
+ out_be32(&raide->liodnbr, base);
+}
+#endif
+
void set_liodns(void)
{
/* setup general liodn offsets */
@@ -145,6 +158,12 @@ void set_liodns(void)
#endif
/* setup PME liodn base */
setup_pme_liodn_base();
+
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+ /* raid engine ccr addr code for liodn */
+ set_liodn(raide_liodn_tbl, raide_liodn_tbl_sz);
+ setup_raide_liodn_base();
+#endif
}
static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz)
@@ -184,4 +203,8 @@ void fdt_fixup_liodn(void *blob)
#endif
#endif
fdt_fixup_liodn_tbl(blob, sec_liodn_tbl, sec_liodn_tbl_sz);
+
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+ fdt_fixup_liodn_tbl(blob, raide_liodn_tbl, raide_liodn_tbl_sz);
+#endif
}
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 758e6d7..ffc2a9a 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -221,14 +221,14 @@ ulong get_spin_virt_addr(void)
#ifdef CONFIG_FSL_CORENET
static void plat_mp_up(unsigned long bootpg)
{
- u32 up, cpu_up_mask, whoami;
+ u32 cpu_up_mask, whoami;
u32 *table = (u32 *)get_spin_virt_addr();
volatile ccsr_gur_t *gur;
volatile ccsr_local_t *ccm;
volatile ccsr_rcpm_t *rcpm;
volatile ccsr_pic_t *pic;
int timeout = 10;
- u32 nr_cpus;
+ u32 mask = cpu_mask();
struct law_entry e;
gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -236,8 +236,6 @@ static void plat_mp_up(unsigned long bootpg)
rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
- nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1;
-
whoami = in_be32(&pic->whoami);
cpu_up_mask = 1 << whoami;
out_be32(&ccm->bstrl, bootpg);
@@ -251,19 +249,18 @@ static void plat_mp_up(unsigned long bootpg)
/* disable time base at the platform */
out_be32(&rcpm->ctbenrl, cpu_up_mask);
- /* release the hounds */
- up = ((1 << nr_cpus) - 1);
- out_be32(&gur->brrl, up);
+ out_be32(&gur->brrl, mask);
/* wait for everyone */
while (timeout) {
- int i;
- for (i = 0; i < nr_cpus; i++) {
- if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
- cpu_up_mask |= (1 << i);
- };
+ unsigned int i, cpu, nr_cpus = cpu_numcores();
- if ((cpu_up_mask & up) == up)
+ for_each_cpu(i, cpu, nr_cpus, mask) {
+ if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
+ cpu_up_mask |= (1 << cpu);
+ }
+
+ if ((cpu_up_mask & mask) == mask)
break;
udelay(100);
@@ -272,7 +269,7 @@ static void plat_mp_up(unsigned long bootpg)
if (timeout == 0)
printf("CPU up timeout. CPU up mask is %x should be %x\n",
- cpu_up_mask, up);
+ cpu_up_mask, mask);
/* enable time base at the platform */
out_be32(&rcpm->ctbenrl, 0);
@@ -283,7 +280,7 @@ static void plat_mp_up(unsigned long bootpg)
mtspr(SPRN_TBWU, 0);
mtspr(SPRN_TBWL, 0);
- out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
+ out_be32(&rcpm->ctbenrl, mask);
#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
/*
diff --git a/arch/powerpc/cpu/mpc85xx/p3060_ids.c b/arch/powerpc/cpu/mpc85xx/p3060_ids.c
new file mode 100644
index 0000000..07703d4
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p3060_ids.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+ /* dqrr liodn, frame data liodn, liodn off, sdest */
+ SET_QP_INFO( 1, 2, 1, 0),
+ SET_QP_INFO( 3, 4, 2, 1),
+ SET_QP_INFO( 5, 6, 3, 2),
+ SET_QP_INFO( 7, 8, 4, 3),
+ SET_QP_INFO( 9, 10, 5, 4),
+ SET_QP_INFO(11, 12, 6, 5),
+ SET_QP_INFO(13, 14, 7, 6),
+ SET_QP_INFO(15, 16, 8, 7),
+ SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */
+ SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */
+};
+#endif
+
+struct liodn_id_table liodn_tbl[] = {
+ SET_USB_LIODN(1, "fsl-usb2-mph", 127),
+ SET_USB_LIODN(2, "fsl-usb2-dr", 157),
+
+ SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
+ SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
+
+ SET_DMA_LIODN(1, 196),
+ SET_DMA_LIODN(2, 197),
+
+ SET_GUTS_LIODN("fsl,rapidio-delta", 198, rio1liodnr, 0),
+ SET_GUTS_LIODN(NULL, 199, rio2liodnr, 0),
+ SET_GUTS_LIODN(NULL, 200, rmuliodnr, 0),
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ SET_QMAN_LIODN(31),
+ SET_BMAN_LIODN(32),
+#endif
+ SET_PME_LIODN(128),
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+ SET_FMAN_RX_1G_LIODN(1, 0, 11),
+ SET_FMAN_RX_1G_LIODN(1, 1, 12),
+ SET_FMAN_RX_1G_LIODN(1, 2, 13),
+ SET_FMAN_RX_1G_LIODN(1, 3, 14),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+struct liodn_id_table fman2_liodn_tbl[] = {
+ SET_FMAN_RX_1G_LIODN(2, 0, 16),
+ SET_FMAN_RX_1G_LIODN(2, 1, 17),
+ SET_FMAN_RX_1G_LIODN(2, 2, 18),
+ SET_FMAN_RX_1G_LIODN(2, 3, 19),
+};
+int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
+#endif
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+ SET_SEC_JR_LIODN_ENTRY(0, 146, 154),
+ SET_SEC_JR_LIODN_ENTRY(1, 147, 155),
+ SET_SEC_JR_LIODN_ENTRY(2, 178, 186),
+ SET_SEC_JR_LIODN_ENTRY(3, 179, 187),
+ SET_SEC_RTIC_LIODN_ENTRY(a, 144),
+ SET_SEC_RTIC_LIODN_ENTRY(b, 145),
+ SET_SEC_RTIC_LIODN_ENTRY(c, 176),
+ SET_SEC_RTIC_LIODN_ENTRY(d, 177),
+ SET_SEC_DECO_LIODN_ENTRY(0, 129, 161),
+ SET_SEC_DECO_LIODN_ENTRY(1, 130, 162),
+ SET_SEC_DECO_LIODN_ENTRY(2, 131, 163),
+ SET_SEC_DECO_LIODN_ENTRY(3, 132, 164),
+ SET_SEC_DECO_LIODN_ENTRY(4, 133, 165),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+struct liodn_id_table liodn_bases[] = {
+ [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(96, 106),
+#ifdef CONFIG_SYS_DPAA_FMAN
+ [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64),
+#endif
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+ [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(116, 133),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/p3060_serdes.c b/arch/powerpc/cpu/mpc85xx/p3060_serdes.c
new file mode 100644
index 0000000..6387276
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p3060_serdes.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet_serdes.h"
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+ [0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC1,
+ SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2,
+ NONE, NONE, AURORA, AURORA},
+ [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SGMII_FM2_DTSEC3,
+ SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4,
+ SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM1_DTSEC2, NONE, NONE, AURORA, AURORA},
+ [0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1,
+ SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3,
+ SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
+ [0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, PCIE2, PCIE2, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
+ SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
+ [0x1c] = {NONE, NONE, SRIO1, SRIO2, NONE, NONE, NONE, NONE,
+ AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM1_DTSEC1,
+ SGMII_FM2_DTSEC2, SGMII_FM1_DTSEC2, SGMII_FM2_DTSEC3,
+ SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC4},
+};
+
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
+{
+ if (!serdes_lane_enabled(lane))
+ return NONE;
+
+ return serdes_cfg_tbl[cfg][lane];
+}
+
+int is_serdes_prtcl_valid(u32 prtcl)
+{
+ int i;
+
+ if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (serdes_cfg_tbl[prtcl][i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
+
+void soc_serdes_init(void)
+{
+ /*
+ * On the P3060 the devdisr2 register does not correctly reflect
+ * the state of the MACs based on the RCW fields. So disable the MACs
+ * based on the srds_prtcl and ec1, ec2, ec3 fields
+ */
+
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 devdisr2 = in_be32(&gur->devdisr2);
+ u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
+ u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+ u32 ec1_ext, ec2_ext;
+
+ /* NOTE: Leave FM1-1,FM1-2 alone for MDIO access */
+
+ if (!is_serdes_configured(SGMII_FM1_DTSEC3))
+ devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_3;
+
+ if (!is_serdes_configured(SGMII_FM1_DTSEC4))
+ devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC1_4;
+
+ if (!is_serdes_configured(SGMII_FM2_DTSEC1))
+ devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_1;
+
+ if (!is_serdes_configured(SGMII_FM2_DTSEC2))
+ devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_2;
+
+ if (!is_serdes_configured(SGMII_FM2_DTSEC3))
+ devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_3;
+
+ if (!is_serdes_configured(SGMII_FM2_DTSEC4))
+ devdisr2 |= FSL_CORENET_DEVDISR2_DTSEC2_4;
+
+ if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
+ FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) {
+ devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC1_2;
+ }
+
+ if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
+ FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1) {
+ devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_1;
+ }
+
+ ec1_ext = rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT;
+ if (ec1_ext) {
+ if ((ec1_ext == FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII) ||
+ (ec1_ext == FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII))
+ devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC1_4;
+ }
+
+ ec2_ext = rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT;
+ if (ec2_ext) {
+ if ((ec2_ext == FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII) ||
+ (ec2_ext == FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII))
+ devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_4;
+ }
+
+ if ((rcwsr13 & FSL_CORENET_RCWSR13_EC3) ==
+ FSL_CORENET_RCWSR13_EC3_FM2_DTSEC4_MII)
+ devdisr2 &= ~FSL_CORENET_DEVDISR2_DTSEC2_4;
+
+ out_be32(&gur->devdisr2, devdisr2);
+}
diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c
index 9836588..2911c13 100644
--- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c
@@ -97,6 +97,16 @@ struct liodn_id_table sec_liodn_tbl[] = {
};
int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+struct liodn_id_table raide_liodn_tbl[] = {
+ SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60),
+ SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61),
+ SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62),
+ SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63),
+};
+int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl);
+#endif
+
struct liodn_id_table liodn_bases[] = {
[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100),
#ifdef CONFIG_SYS_DPAA_FMAN
@@ -105,4 +115,7 @@ struct liodn_id_table liodn_bases[] = {
#ifdef CONFIG_SYS_DPAA_PME
[FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172),
#endif
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+ [FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(47),
+#endif
};
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
index ecaa30d..418dd9d 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -151,7 +151,7 @@ static int fdt_qportal(void *blob, int off, int id, char *name,
dev_handle = fdt_get_phandle(blob, dev_off);
if (dev_handle <= 0) {
dev_handle = fdt_alloc_phandle(blob);
- ret = fdt_create_phandle(blob, dev_off,
+ ret = fdt_set_phandle(blob, dev_off,
dev_handle);
if (ret < 0)
return ret;
@@ -198,7 +198,10 @@ void fdt_fixup_qportals(void *blob)
u32 liodns[2];
#endif
const int *ci = fdt_getprop(blob, off, "cell-index", NULL);
- int j, i = *ci;
+ int i = *ci;
+#ifdef CONFIG_SYS_DPAA_FMAN
+ int j;
+#endif
err = fdt_setprop(blob, off, "compatible", compat, compat_len);
if (err < 0)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index a83dfeb..ce47532 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -41,6 +41,7 @@ void get_sys_info (sys_info_t * sysInfo)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_CORENET
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
+ unsigned int cpu;
const u8 core_cplx_PLL[16] = {
[ 0] = 0, /* CC1 PPL / 1 */
@@ -97,11 +98,11 @@ void get_sys_info (sys_info_t * sysInfo)
freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
}
rcw_tmp = in_be32(&gur->rcwsr[3]);
- for (i = 0; i < cpu_numcores(); i++) {
- u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
+ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
+ u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
u32 cplx_pll = core_cplx_PLL[c_pll_sel];
- sysInfo->freqProcessor[i] =
+ sysInfo->freqProcessor[cpu] =
freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
}
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 878a3d6..5e0d78d 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -83,6 +83,45 @@
_start_e500:
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
+ /* ISBC uses L2 as stack.
+ * Disable L2 cache here so that u-boot can enable it later
+ * as part of it's normal flow
+ */
+
+ /* Check if L2 is enabled */
+ mfspr r3, SPRN_L2CSR0
+ lis r2, L2CSR0_L2E@h
+ ori r2, r2, L2CSR0_L2E@l
+ and. r4, r3, r2
+ beq l2_disabled
+
+ mfspr r3, SPRN_L2CSR0
+ /* Flush L2 cache */
+ lis r2,(L2CSR0_L2FL)@h
+ ori r2, r2, (L2CSR0_L2FL)@l
+ or r3, r2, r3
+ sync
+ isync
+ mtspr SPRN_L2CSR0,r3
+ isync
+1:
+ mfspr r3, SPRN_L2CSR0
+ and. r1, r3, r2
+ bne 1b
+
+ mfspr r3, SPRN_L2CSR0
+ lis r2, L2CSR0_L2E@h
+ ori r2, r2, L2CSR0_L2E@l
+ andc r4, r3, r2
+ sync
+ isync
+ mtspr SPRN_L2CSR0,r4
+ isync
+
+l2_disabled:
+#endif
+
/* clear registers/arrays not reset by hardware */
/* L1 */
@@ -279,10 +318,244 @@ _start_e500:
#endif /* CONFIG_MPC8569 */
+/*
+ * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
+ * location is not where we want it. This typically happens on a 36-bit
+ * system, where we want to move CCSR to near the top of 36-bit address space.
+ *
+ * To move CCSR, we create two temporary TLBs, one for the old location, and
+ * another for the new location. On CoreNet systems, we also need to create
+ * a special, temporary LAW.
+ *
+ * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
+ * long-term TLBs, so we use TLB0 here.
+ */
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
+
+#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
+#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
+#endif
+
+purge_old_ccsr_tlb:
+ lis r8, CONFIG_SYS_CCSRBAR@h
+ ori r8, r8, CONFIG_SYS_CCSRBAR@l
+ lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
+ ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
+
+ /*
+ * In a multi-stage boot (e.g. NAND boot), a previous stage may have
+ * created a TLB for CCSR, which will interfere with our relocation
+ * code. Since we're going to create a new TLB for CCSR anyway,
+ * it should be safe to delete this old TLB here. We have to search
+ * for it, though.
+ */
+
+ li r1, 0
+ mtspr MAS6, r1 /* Search the current address space and PID */
+ tlbsx 0, r8
+ mfspr r1, MAS1
+ andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */
+ beq 1f /* Skip if no TLB found */
+
+ rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */
+ mtspr MAS1, r1
+ tlbwe
+1:
+
+create_ccsr_new_tlb:
+ /*
+ * Create a TLB for the new location of CCSR. Register R8 is reserved
+ * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
+ */
+ lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
+ ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
+ lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
+ ori r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
+ lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
+ ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
+ lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
+ ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
+ lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
+ ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
+ mtspr MAS0, r0
+ mtspr MAS1, r1
+ mtspr MAS2, r2
+ mtspr MAS3, r3
+ mtspr MAS7, r7
+ isync
+ msync
+ tlbwe
+
+ /*
+ * Create a TLB for the old location of CCSR. Register R9 is reserved
+ * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
+ */
+create_ccsr_old_tlb:
+ lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h
+ ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
+ lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
+ ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
+ lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h
+ ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l
+ li r7, 0 /* The default CCSR address is always a 32-bit number */
+ mtspr MAS0, r0
+ /* MAS1 is the same as above */
+ mtspr MAS2, r2
+ mtspr MAS3, r3
+ mtspr MAS7, r7
+ isync
+ msync
+ tlbwe
+
+#ifdef CONFIG_FSL_CORENET
+
+#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
+#define LAW_EN 0x80000000
+#define LAW_SIZE_4K 0xb
+#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
+#define CCSRAR_C 0x80000000 /* Commit */
+
+create_temp_law:
+ /*
+ * On CoreNet systems, we create the temporary LAW using a special LAW
+ * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
+ */
+ lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
+ ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
+ lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
+ ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
+ lis r2, CCSRBAR_LAWAR@h
+ ori r2, r2, CCSRBAR_LAWAR@l
+
+ stw r0, 0xc00(r9) /* LAWBARH0 */
+ stw r1, 0xc04(r9) /* LAWBARL0 */
+ sync
+ stw r2, 0xc08(r9) /* LAWAR0 */
+
+ /*
+ * Read back from LAWAR to ensure the update is complete. e500mc
+ * cores also require an isync.
+ */
+ lwz r0, 0xc08(r9) /* LAWAR0 */
+ isync
+
+ /*
+ * Read the current CCSRBARH and CCSRBARL using load word instructions.
+ * Follow this with an isync instruction. This forces any outstanding
+ * accesses to configuration space to completion.
+ */
+read_old_ccsrbar:
+ lwz r0, 0(r9) /* CCSRBARH */
+ lwz r0, 4(r9) /* CCSRBARH */
+ isync
+
+ /*
+ * Write the new values for CCSRBARH and CCSRBARL to their old
+ * locations. The CCSRBARH has a shadow register. When the CCSRBARH
+ * has a new value written it loads a CCSRBARH shadow register. When
+ * the CCSRBARL is written, the CCSRBARH shadow register contents
+ * along with the CCSRBARL value are loaded into the CCSRBARH and
+ * CCSRBARL registers, respectively. Follow this with a sync
+ * instruction.
+ */
+write_new_ccsrbar:
+ lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
+ ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
+ lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
+ ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
+ lis r2, CCSRAR_C@h
+ ori r2, r2, CCSRAR_C@l
+
+ stw r0, 0(r9) /* Write to CCSRBARH */
+ sync /* Make sure we write to CCSRBARH first */
+ stw r1, 4(r9) /* Write to CCSRBARL */
+ sync
+
+ /*
+ * Write a 1 to the commit bit (C) of CCSRAR at the old location.
+ * Follow this with a sync instruction.
+ */
+ stw r2, 8(r9)
+ sync
+
+ /* Delete the temporary LAW */
+delete_temp_law:
+ li r1, 0
+ stw r1, 0xc08(r8)
+ sync
+ stw r1, 0xc00(r8)
+ stw r1, 0xc04(r8)
+ sync
+
+#else /* #ifdef CONFIG_FSL_CORENET */
+
+write_new_ccsrbar:
+ /*
+ * Read the current value of CCSRBAR using a load word instruction
+ * followed by an isync. This forces all accesses to configuration
+ * space to complete.
+ */
+ sync
+ lwz r0, 0(r9)
+ isync
+
+/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
+#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
+ (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
+
+ /* Write the new value to CCSRBAR. */
+ lis r0, CCSRBAR_PHYS_RS12@h
+ ori r0, r0, CCSRBAR_PHYS_RS12@l
+ stw r0, 0(r9)
+ sync
+
+ /*
+ * The manual says to perform a load of an address that does not
+ * access configuration space or the on-chip SRAM using an existing TLB,
+ * but that doesn't appear to be necessary. We will do the isync,
+ * though.
+ */
+ isync
+
+ /*
+ * Read the contents of CCSRBAR from its new location, followed by
+ * another isync.
+ */
+ lwz r0, 0(r8)
+ isync
+
+#endif /* #ifdef CONFIG_FSL_CORENET */
+
+ /* Delete the temporary TLBs */
+delete_temp_tlbs:
+ lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
+ ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
+ li r1, 0
+ lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
+ ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
+ mtspr MAS0, r0
+ mtspr MAS1, r1
+ mtspr MAS2, r2
+ isync
+ msync
+ tlbwe
+
+ lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h
+ ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
+ lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
+ ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
+ mtspr MAS0, r0
+ mtspr MAS2, r2
+ isync
+ msync
+ tlbwe
+#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
+
+create_init_ram_area:
lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
-#ifndef CONFIG_SYS_RAMBOOT
+#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
/* create a temp mapping in AS=1 to the 4M boot window */
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
@@ -293,6 +566,20 @@ _start_e500:
/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
+ /* create a temp mapping in AS = 1 for Flash mapping
+ * created by PBL for ISBC code
+ */
+ lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
+ ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
+
+ lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
+ ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
+
+ lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR))@h
+ ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR))@l
#else
/*
* create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
index 8410bd7..852f9aa 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
@@ -23,6 +23,8 @@
* MA 02111-1307 USA
*/
+#include "config.h" /* CONFIG_BOARDDIR */
+
OUTPUT_ARCH(powerpc)
SECTIONS
{
@@ -52,8 +54,18 @@ SECTIONS
. = ALIGN(8);
__init_begin = .;
__init_end = .;
-
- .resetvec ADDR(.text) + 0xffc : {
+#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
+ .bootpg ADDR(.text) + 0x1000 :
+ {
+ start.o (.bootpg)
+ }
+#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
+#elif defined(CONFIG_FSL_ELBC)
+#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
+#else
+#error unknown NAND controller
+#endif
+ .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
KEEP(*(.resetvec))
} = 0xffff
@@ -64,4 +76,4 @@ SECTIONS
}
__bss_end__ = .;
}
-ASSERT(__init_end <= 0xfff00ffc, "NAND bootstrap too big");
+ASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big");
generated by cgit v0.10.2 at 2024-07-31 20:03:37 (GMT)