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-rw-r--r--arch/powerpc/cpu/mpc83xx/pcie.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/Makefile2
-rw-r--r--arch/powerpc/cpu/mpc85xx/b4860_ids.c12
-rw-r--r--arch/powerpc/cpu/mpc85xx/c29x_serdes.c62
-rw-r--r--arch/powerpc/cpu/mpc85xx/cmd_errata.c3
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c23
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c10
-rw-r--r--arch/powerpc/cpu/mpc85xx/ddr-gen1.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/ddr-gen2.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/ddr-gen3.c36
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c6
-rw-r--r--arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h1
-rw-r--r--arch/powerpc/cpu/mpc85xx/release.S15
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S3
-rw-r--r--arch/powerpc/cpu/mpc85xx/t4240_ids.c12
-rw-r--r--arch/powerpc/cpu/mpc86xx/ddr-8641.c2
-rw-r--r--arch/powerpc/cpu/mpc8xxx/cpu.c3
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c15
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ddr.h2
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c1
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/interactive.c4
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/main.c62
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/options.c2
23 files changed, 247 insertions, 35 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index 09970b0..28c25e5 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -299,6 +299,8 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
printf("PCIE%d: ", bus);
+#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
+#define PCI_LTSSM_L0 0x16 /* L0 state */
reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
if (reg16 >= PCI_LTSSM_L0)
printf("link\n");
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 0d1e8f1..f70f0d7 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -46,6 +46,7 @@ COBJS-$(CONFIG_MPC8568) += ddr-gen2.o
COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
# supports ddr1/2/3
+COBJS-$(CONFIG_PPC_C29X) += ddr-gen3.o
COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
COBJS-$(CONFIG_MPC8569) += ddr-gen3.o
@@ -100,6 +101,7 @@ COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
# SoC specific SERDES support
+COBJS-$(CONFIG_PPC_C29X) += c29x_serdes.o
COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o
COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
index 53c6a7f..39b8e3e 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
@@ -41,8 +41,8 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
#ifdef CONFIG_SYS_SRIO
struct srio_liodn_id_table srio_liodn_tbl[] = {
- SET_SRIO_LIODN_1(1, 307),
- SET_SRIO_LIODN_1(2, 387),
+ SET_SRIO_LIODN_BASE(1, 307),
+ SET_SRIO_LIODN_BASE(2, 387),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
#endif
@@ -112,10 +112,10 @@ int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
#ifdef CONFIG_SYS_DPAA_RMAN
struct liodn_id_table rman_liodn_tbl[] = {
/* Set RMan block 0-3 liodn offset */
- SET_RMAN_LIODN(0, 678),
- SET_RMAN_LIODN(1, 679),
- SET_RMAN_LIODN(2, 680),
- SET_RMAN_LIODN(3, 681),
+ SET_RMAN_LIODN(0, 6),
+ SET_RMAN_LIODN(1, 7),
+ SET_RMAN_LIODN(2, 8),
+ SET_RMAN_LIODN(3, 9),
};
int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
new file mode 100644
index 0000000..51972cb
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES 4
+
+static u32 serdes1_prtcl_map;
+
+struct serdes_config {
+ u32 protocol;
+ u8 lanes[SRDS1_MAX_LANES];
+};
+
+static const struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {1, {PCIE1, PCIE1, PCIE1, PCIE1} },
+ {2, {PCIE1, PCIE1, PCIE1, PCIE1} },
+ {3, {PCIE1, PCIE1, NONE, NONE} },
+ {4, {PCIE1, PCIE1, NONE, NONE} },
+ {5, {PCIE1, NONE, NONE, NONE} },
+ {6, {PCIE1, NONE, NONE, NONE} },
+ {}
+};
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+ return (1 << device) & serdes1_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ const struct serdes_config *ptr;
+ int lane;
+
+ debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+ if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
+ printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+ return;
+ }
+
+ ptr = &serdes1_cfg_tbl[srds_cfg];
+ if (!ptr->protocol)
+ return;
+
+ for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = ptr->lanes[lane];
+ serdes1_prtcl_map |= (1 << lane_prtcl);
+ }
+}
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 5cd02cc..cbb443f 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -245,6 +245,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
puts("Work-around for Erratum A006593 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
+ puts("Work-around for Erratum A-005812 enabled\n");
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 91ac4ee..66bc6a2 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -44,10 +44,10 @@ int checkcpu (void)
uint major, minor;
struct cpu_type *cpu;
char buf1[32], buf2[32];
-#if (defined(CONFIG_DDR_CLK_FREQ) || \
- defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#endif /* CONFIG_FSL_CORENET */
+#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
+ ccsr_gur_t __iomem *gur =
+ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
/*
* Cornet platforms use ddr sync bit in RCW to indicate sync vs async
@@ -211,6 +211,21 @@ int checkcpu (void)
puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
+#ifdef CONFIG_FSL_CORENET
+ /* Display the RCW, so that no one gets confused as to what RCW
+ * we're actually using for this boot.
+ */
+ puts("Reset Configuration Word (RCW):");
+ for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+ u32 rcw = in_be32(&gur->rcwsr[i]);
+
+ if ((i % 4) == 0)
+ printf("\n %08x:", i * 4);
+ printf(" %08x", rcw);
+ }
+ puts("\n");
+#endif
+
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 25beda2..48b3826 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -399,6 +399,14 @@ int cpu_init_r(void)
sync();
}
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
+ /*
+ * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
+ * in write shadow mode. Checking DCWS before setting SPR 976.
+ */
+ if (mfspr(L1CSR2) & L1CSR2_DCWS)
+ mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
+#endif
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
spin = getenv("spin_table_compat");
@@ -532,8 +540,10 @@ skip_l2:
enable_cpc();
+#ifndef CONFIG_SYS_FSL_NO_SERDES
/* needs to be in ram since code uses global static vars */
fsl_serdes_init();
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
if (IS_SVR_REV(svr, 1, 0)) {
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
index 8a86819..4dd8c0b 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
@@ -15,7 +15,7 @@
#endif
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
- unsigned int ctrl_num)
+ unsigned int ctrl_num, int step)
{
unsigned int i;
volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
index a705862..542bc84 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
@@ -16,7 +16,7 @@
#endif
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
- unsigned int ctrl_num)
+ unsigned int ctrl_num, int step)
{
unsigned int i;
ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index c5b4720..1be51d3 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -15,8 +15,18 @@
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
#endif
+
+/*
+ * regs has the to-be-set values for DDR controller registers
+ * ctrl_num is the DDR controller number
+ * step: 0 goes through the initialization in one pass
+ * 1 sets registers and returns before enabling controller
+ * 2 resumes from step 1 and continues to initialize
+ * Dividing the initialization to two steps to deassert DDR reset signal
+ * to comply with JEDEC specs for RDIMMs.
+ */
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
- unsigned int ctrl_num)
+ unsigned int ctrl_num, int step)
{
unsigned int i, bus_width;
volatile ccsr_ddr_t *ddr;
@@ -54,6 +64,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
return;
}
+ if (step == 2)
+ goto step2;
+
if (regs->ddr_eor)
out_be32(&ddr->eor, regs->ddr_eor);
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
@@ -123,10 +136,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+#ifndef CONFIG_SYS_FSL_DDR_EMU
+ /*
+ * Skip these two registers if running on emulator
+ * because emulator doesn't have skew between bytes.
+ */
+
if (regs->ddr_wrlvl_cntl_2)
out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
if (regs->ddr_wrlvl_cntl_3)
out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
+#endif
out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
@@ -150,6 +170,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->debug[21], 0x24000000);
#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */
+ /*
+ * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
+ * deasserted. Clocks start when any chip select is enabled and clock
+ * control register is set. Because all DDR components are connected to
+ * one reset signal, this needs to be done in two steps. Step 1 is to
+ * get the clocks started. Step 2 resumes after reset signal is
+ * deasserted.
+ */
+ if (step == 1) {
+ udelay(200);
+ return;
+ }
+
+step2:
/* Set, but do not enable the memory */
temp_sdram_cfg = regs->ddr_sdram_cfg;
temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index cfaa2ed..84bb8fa 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -604,8 +604,12 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_add_enet_stashing(blob);
+#ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
+#define CONFIG_FSL_TBCLK_EXTRA_DIV 1
+#endif
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "timebase-frequency", get_tbclk(), 1);
+ "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
+ 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
get_sys_info(&sysinfo);
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h
index 6de572d..d515b23 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h
@@ -9,5 +9,4 @@
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
int serdes_lane_enabled(int lane);
-enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
#endif /* __FSL_CORENET2_SERDES_H */
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 15bbbc1..c15e83b 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -226,6 +226,21 @@ __secondary_start_page:
2:
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
+ /*
+ * A-005812 workaround sets bit 32 of SPR 976 for SoCs running in
+ * write shadow mode. This code should run after other code setting
+ * DCWS.
+ */
+ mfspr r3,L1CSR2
+ andis. r3,r3,(L1CSR2_DCWS)@h
+ beq 1f
+ mfspr r3, SPRN_HDBCR0
+ oris r3, r3, 0x8000
+ mtspr SPRN_HDBCR0, r3
+1:
+#endif
+
#ifdef CONFIG_BACKSIDE_L2_CACHE
/* skip L2 setup on P2040/P2040E as they have no L2 */
mfspr r3,SPRN_SVR
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index cfc3a60..ad57a9c 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -33,7 +33,8 @@
#define MINIMAL_SPL
#endif
-#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
+ !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define NOR_BOOT
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
index e173cb5..54c1cfd 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
@@ -65,8 +65,8 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
#endif
struct srio_liodn_id_table srio_liodn_tbl[] = {
- SET_SRIO_LIODN_1(1, 307),
- SET_SRIO_LIODN_1(2, 387),
+ SET_SRIO_LIODN_BASE(1, 307),
+ SET_SRIO_LIODN_BASE(2, 387),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
@@ -159,10 +159,10 @@ int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
#ifdef CONFIG_SYS_DPAA_RMAN
struct liodn_id_table rman_liodn_tbl[] = {
/* Set RMan block 0-3 liodn offset */
- SET_RMAN_LIODN(0, 678),
- SET_RMAN_LIODN(1, 679),
- SET_RMAN_LIODN(2, 680),
- SET_RMAN_LIODN(3, 681),
+ SET_RMAN_LIODN(0, 6),
+ SET_RMAN_LIODN(1, 7),
+ SET_RMAN_LIODN(2, 8),
+ SET_RMAN_LIODN(3, 9),
};
int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
#endif
diff --git a/arch/powerpc/cpu/mpc86xx/ddr-8641.c b/arch/powerpc/cpu/mpc86xx/ddr-8641.c
index 92ba26d..33a91f9 100644
--- a/arch/powerpc/cpu/mpc86xx/ddr-8641.c
+++ b/arch/powerpc/cpu/mpc86xx/ddr-8641.c
@@ -15,7 +15,7 @@
#endif
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
- unsigned int ctrl_num)
+ unsigned int ctrl_num, int step)
{
unsigned int i;
volatile ccsr_ddr_t *ddr;
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 7369582..c67be4e 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -79,6 +79,9 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(BSC9131, 9131, 1),
CPU_TYPE_ENTRY(BSC9132, 9132, 2),
CPU_TYPE_ENTRY(BSC9232, 9232, 2),
+ CPU_TYPE_ENTRY(C291, C291, 1),
+ CPU_TYPE_ENTRY(C292, C292, 1),
+ CPU_TYPE_ENTRY(C293, C293, 1),
#elif defined(CONFIG_MPC86xx)
CPU_TYPE_ENTRY(8610, 8610, 1),
CPU_TYPE_ENTRY(8641, 8641, 2),
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index ff5812d..242eb47 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -364,7 +364,7 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
ddr->timing_cfg_3 = (0
| ((ext_pretoact & 0x1) << 28)
- | ((ext_acttopre & 0x2) << 24)
+ | ((ext_acttopre & 0x3) << 24)
| ((ext_acttorw & 0x1) << 22)
| ((ext_refrec & 0x1F) << 16)
| ((ext_caslat & 0x3) << 12)
@@ -681,6 +681,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
unsigned int odt_cfg = 0; /* ODT configuration */
unsigned int num_pr; /* Number of posted refreshes */
unsigned int slow = 0; /* DDR will be run less than 1250 */
+ unsigned int x4_en = 0; /* x4 DRAM enable */
unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
unsigned int ap_en; /* Address Parity Enable */
unsigned int d_init; /* DRAM data initialization */
@@ -725,6 +726,8 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
ap_en = 0;
}
+ x4_en = popts->x4_en ? 1 : 0;
+
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* Use the DDR controller to auto initialize memory. */
d_init = popts->ECC_init_using_memctl;
@@ -747,6 +750,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
| ((odt_cfg & 0x3) << 21)
| ((num_pr & 0xf) << 12)
| ((slow & 1) << 11)
+ | (x4_en << 10)
| (qd_en << 9)
| (unq_mrs_en << 8)
| ((obc_cfg & 0x1) << 6)
@@ -1585,8 +1589,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
| ((ea & 0xFFF) << 0) /* ending address MSB */
);
} else {
- debug("FSLDDR: setting bnds to 0 for inactive CS\n");
- ddr->cs[i].bnds = 0;
+ /* setting bnds to 0xffffffff for inactive CS */
+ ddr->cs[i].bnds = 0xffffffff;
}
debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
@@ -1638,5 +1642,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_ddr_sdram_rcw(ddr, popts, common_dimm);
+#ifdef CONFIG_SYS_FSL_DDR_EMU
+ /* disble DDR training for emulator */
+ ddr->debug[2] = 0x00000400;
+ ddr->debug[4] = 0xff800000;
+#endif
return check_fsl_memctl_config_regs(ddr);
}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
index 4dd55fc..c173a5a 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@@ -96,7 +96,7 @@ unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
/* processor specific function */
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
- unsigned int ctrl_num);
+ unsigned int ctrl_num, int step);
/* board specific function */
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
index 3e7c269..b67158c 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
@@ -129,6 +129,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
pdimm->ec_sdram_width = 0;
pdimm->data_width = pdimm->primary_sdram_width
+ pdimm->ec_sdram_width;
+ pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
/* These are the types defined by the JEDEC DDR3 SPD spec */
pdimm->mirrored_dimm = 0;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
index 1ed6c77..260fce5 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
@@ -205,6 +205,7 @@ static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
DIMM_PARM(primary_sdram_width),
DIMM_PARM(ec_sdram_width),
DIMM_PARM(registered_dimm),
+ DIMM_PARM(device_width),
DIMM_PARM(n_row_addr),
DIMM_PARM(n_col_addr),
@@ -263,6 +264,7 @@ static void print_dimm_parameters(const dimm_params_t *pdimm)
DIMM_PARM(primary_sdram_width),
DIMM_PARM(ec_sdram_width),
DIMM_PARM(registered_dimm),
+ DIMM_PARM(device_width),
DIMM_PARM(n_row_addr),
DIMM_PARM(n_col_addr),
@@ -443,6 +445,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
CTRL_OPTIONS(twoT_en),
CTRL_OPTIONS(threeT_en),
CTRL_OPTIONS(ap_en),
+ CTRL_OPTIONS(x4_en),
CTRL_OPTIONS(bstopre),
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
@@ -687,6 +690,7 @@ static void print_memctl_options(const memctl_options_t *popts)
CTRL_OPTIONS(threeT_en),
CTRL_OPTIONS(registered_dimm_en),
CTRL_OPTIONS(ap_en),
+ CTRL_OPTIONS(x4_en),
CTRL_OPTIONS(bstopre),
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 7a8636d..9f4f253 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -25,10 +25,6 @@ void fsl_ddr_set_lawbar(
unsigned int ctrl_num);
void fsl_ddr_set_intl3r(const unsigned int granule_size);
-/* processor specific function */
-extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
- unsigned int ctrl_num);
-
#if defined(SPD_EEPROM_ADDRESS) || \
defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
@@ -365,9 +361,11 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
{
unsigned int i, j;
unsigned long long total_mem = 0;
+ int assert_reset;
fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
common_timing_params_t *timing_params = pinfo->common_timing_params;
+ assert_reset = board_need_mem_reset();
/* data bus width capacity adjust shift amount */
unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
@@ -462,7 +460,20 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
timing_params[i].all_DIMMs_registered,
&pinfo->memctl_opts[i],
pinfo->dimm_params[i], i);
+ /*
+ * For RDIMMs, JEDEC spec requires clocks to be stable
+ * before reset signal is deasserted. For the boards
+ * using fixed parameters, this function should be
+ * be called from board init file.
+ */
+ if (timing_params[i].all_DIMMs_registered)
+ assert_reset = 1;
}
+ if (assert_reset) {
+ debug("Asserting mem reset\n");
+ board_assert_mem_reset();
+ }
+
case STEP_ASSIGN_ADDRESSES:
/* STEP 5: Assign addresses to chip selects */
check_interleaving_options(pinfo);
@@ -504,7 +515,13 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
if (reg->cs[j].config & 0x80000000) {
unsigned int end;
- end = reg->cs[j].bnds & 0xFFF;
+ /*
+ * 0xfffffff is a special value we put
+ * for unused bnds
+ */
+ if (reg->cs[j].bnds == 0xffffffff)
+ continue;
+ end = reg->cs[j].bnds & 0xffff;
if (end > max_end) {
max_end = end;
}
@@ -531,6 +548,7 @@ phys_size_t fsl_ddr_sdram(void)
unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
unsigned long long total_memory;
fsl_ddr_info_t info;
+ int deassert_reset;
/* Reset info structure. */
memset(&info, 0, sizeof(fsl_ddr_info_t));
@@ -559,7 +577,21 @@ phys_size_t fsl_ddr_sdram(void)
}
}
- /* Program configuration registers. */
+ /*
+ * Program configuration registers.
+ * JEDEC specs requires clocks to be stable before deasserting reset
+ * for RDIMMs. Clocks start after chip select is enabled and clock
+ * control register is set. During step 1, all controllers have their
+ * registers set but not enabled. Step 2 proceeds after deasserting
+ * reset through board FPGA or GPIO.
+ * For non-registered DIMMs, initialization can go through but it is
+ * also OK to follow the same flow.
+ */
+ deassert_reset = board_need_mem_reset();
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ if (info.common_timing_params[i].all_DIMMs_registered)
+ deassert_reset = 1;
+ }
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
debug("Programming controller %u\n", i);
if (info.common_timing_params[i].ndimms_present == 0) {
@@ -567,8 +599,22 @@ phys_size_t fsl_ddr_sdram(void)
"skipping programming\n", i);
continue;
}
-
- fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
+ /*
+ * The following call with step = 1 returns before enabling
+ * the controller. It has to finish with step = 2 later.
+ */
+ fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i,
+ deassert_reset ? 1 : 0);
+ }
+ if (deassert_reset) {
+ /* Use board FPGA or GPIO to deassert reset signal */
+ debug("Deasserting mem reset\n");
+ board_deassert_mem_reset();
+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+ /* Call with step = 2 to continue initialization */
+ fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]),
+ i, 2);
+ }
}
/* program LAWs */
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
index 26369e0..30cdca4 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
@@ -700,6 +700,8 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
}
#endif
+ popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
+
/* Choose burst length. */
#if defined(CONFIG_FSL_DDR3)
#if defined(CONFIG_E500MC)