diff options
Diffstat (limited to 'arch')
106 files changed, 3111 insertions, 613 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3adafd6..b2d6e80 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -88,6 +88,12 @@ config ARM_ERRATA_833069 config ARM_ERRATA_833471 bool +config ARM_ERRATA_852421 + bool + +config ARM_ERRATA_852423 + bool + config CPU_ARM720T bool select SYS_CACHE_SHIFT_5 @@ -174,6 +180,15 @@ config SYS_CACHELINE_SIZE default 64 if SYS_CACHE_SHIFT_6 default 32 if SYS_CACHE_SHIFT_5 +config ARM_SMCCC + bool "Support for ARM SMC Calling Convention (SMCCC)" + depends on CPU_V7 || ARM64 + select ARM_PSCI_FW + help + Say Y here if you want to enable ARM SMC Calling Convention. + This should be enabled if U-Boot needs to communicate with system + firmware (for example, PSCI) according to SMCCC. + config SEMIHOSTING bool "support boot from semihosting" help @@ -254,11 +269,6 @@ config SPL_USE_ARCH_MEMSET Such implementation may be faster under some conditions but may increase the binary size. -config ARCH_OMAP2 - bool - select CPU_V7 - select SUPPORT_SPL - config ARM64_SUPPORT_AARCH32 bool "ARM64 system support AArch32 execution state" default y if ARM64 && !TARGET_THUNDERX_88XX @@ -481,72 +491,6 @@ config TARGET_VEXPRESS_CA9X4 bool "Support vexpress_ca9x4" select CPU_V7 -config TARGET_BRXRE1 - bool "Support BRXRE1" - select ARCH_OMAP2 - select BOARD_LATE_INIT - -config TARGET_BRPPT1 - bool "Support BRPPT1" - select ARCH_OMAP2 - select BOARD_LATE_INIT - -config TARGET_DRACO - bool "Support draco" - select ARCH_OMAP2 - select BOARD_LATE_INIT - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_THUBAN - bool "Support thuban" - select ARCH_OMAP2 - select BOARD_LATE_INIT - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_RASTABAN - bool "Support rastaban" - select ARCH_OMAP2 - select BOARD_LATE_INIT - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_ETAMIN - bool "Support etamin" - select ARCH_OMAP2 - select BOARD_LATE_INIT - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_PXM2 - bool "Support pxm2" - select ARCH_OMAP2 - select BOARD_LATE_INIT - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_RUT - bool "Support rut" - select ARCH_OMAP2 - select BOARD_LATE_INIT - select DM - select DM_SERIAL - select DM_GPIO - -config TARGET_TI814X_EVM - bool "Support ti814x_evm" - select ARCH_OMAP2 - -config TARGET_TI816X_EVM - bool "Support ti816x_evm" - select ARCH_OMAP2 - config TARGET_BCM23550_W1D bool "Support bcm23550_w1d" select CPU_V7 @@ -604,6 +548,13 @@ config ARCH_KEYSTONE select SUPPORT_SPL select SYS_THUMB_BUILD select CMD_POWEROFF + imply FIT + +config ARCH_OMAP2PLUS + bool "TI OMAP2+" + select CPU_V7 + select SUPPORT_SPL + imply FIT config ARCH_MESON bool "Amlogic Meson" @@ -639,126 +590,6 @@ config ARCH_MX5 select CPU_V7 select BOARD_EARLY_INIT_F -config TARGET_M53EVK - bool "Support m53evk" - select CPU_V7 - select SUPPORT_SPL - select BOARD_EARLY_INIT_F - -config TARGET_MX51EVK - bool "Support mx51evk" - select BOARD_LATE_INIT - select CPU_V7 - select BOARD_EARLY_INIT_F - -config TARGET_MX53ARD - bool "Support mx53ard" - select CPU_V7 - select BOARD_EARLY_INIT_F - -config TARGET_MX53EVK - bool "Support mx53evk" - select BOARD_LATE_INIT - select CPU_V7 - select BOARD_EARLY_INIT_F - -config TARGET_MX53LOCO - bool "Support mx53loco" - select BOARD_LATE_INIT - select CPU_V7 - select BOARD_EARLY_INIT_F - -config TARGET_MX53SMD - bool "Support mx53smd" - select CPU_V7 - select BOARD_EARLY_INIT_F - -config OMAP34XX - bool "OMAP34XX SoC" - select ARCH_OMAP2 - select ARM_ERRATA_430973 - select ARM_ERRATA_454179 - select ARM_ERRATA_621766 - select ARM_ERRATA_725233 - select USE_TINY_PRINTF - imply SPL_EXT_SUPPORT - imply SPL_FAT_SUPPORT - imply SPL_GPIO_SUPPORT - imply SPL_I2C_SUPPORT - imply SPL_LIBCOMMON_SUPPORT - imply SPL_LIBDISK_SUPPORT - imply SPL_LIBGENERIC_SUPPORT - imply SPL_MMC_SUPPORT - imply SPL_NAND_SUPPORT - imply SPL_POWER_SUPPORT - imply SPL_SERIAL_SUPPORT - imply SYS_THUMB_BUILD - -config OMAP44XX - bool "OMAP44XX SoC" - select ARCH_OMAP2 - select USE_TINY_PRINTF - imply SPL_DISPLAY_PRINT - imply SPL_EXT_SUPPORT - imply SPL_FAT_SUPPORT - imply SPL_GPIO_SUPPORT - imply SPL_I2C_SUPPORT - imply SPL_LIBCOMMON_SUPPORT - imply SPL_LIBDISK_SUPPORT - imply SPL_LIBGENERIC_SUPPORT - imply SPL_MMC_SUPPORT - imply SPL_NAND_SUPPORT - imply SPL_POWER_SUPPORT - imply SPL_SERIAL_SUPPORT - imply SYS_THUMB_BUILD - -config OMAP54XX - bool "OMAP54XX SoC" - select ARCH_OMAP2 - select ARM_ERRATA_798870 - select SYS_THUMB_BUILD - imply SPL_DISPLAY_PRINT - imply SPL_ENV_SUPPORT - imply SPL_EXT_SUPPORT - imply SPL_FAT_SUPPORT - imply SPL_GPIO_SUPPORT - imply SPL_I2C_SUPPORT - imply SPL_LIBCOMMON_SUPPORT - imply SPL_LIBDISK_SUPPORT - imply SPL_LIBGENERIC_SUPPORT - imply SPL_MMC_SUPPORT - imply SPL_NAND_SUPPORT - imply SPL_POWER_SUPPORT - imply SPL_SERIAL_SUPPORT - -config AM43XX - bool "AM43XX SoC" - select ARCH_OMAP2 - imply SPL_DM - imply SPL_DM_SEQ_ALIAS - imply SPL_OF_CONTROL - imply SPL_OF_TRANSLATE - imply SPL_SEPARATE_BSS - imply SPL_SYS_MALLOC_SIMPLE - imply SYS_THUMB_BUILD - help - Support for AM43xx SOC from Texas Instruments. - The AM43xx high performance SOC features a Cortex-A9 - ARM core, a quad core PRU-ICSS for industrial Ethernet - protocols, dual camera support, optional 3D graphics - and an optional customer programmable secure boot. - -config AM33XX - bool "AM33XX SoC" - select ARCH_OMAP2 - imply SYS_THUMB_BUILD - help - Support for AM335x SOC from Texas Instruments. - The AM335x high performance SOC features a Cortex-A8 - ARM core, a dual core PRU-ICSS for industrial Ethernet - protocols, optional 3D graphics and an optional customer - programmable secure boot. - config ARCH_RMOBILE bool "Renesas ARM SoCs" select DM @@ -796,10 +627,6 @@ config ARCH_SOCFPGA select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION select SYS_THUMB_BUILD -config TARGET_CM_T43 - bool "Support cm_t43" - select ARCH_OMAP2 - config ARCH_SUNXI bool "Support sunxi (Allwinner) SoCs" select CMD_GPIO @@ -836,11 +663,6 @@ config TARGET_TS4600 select CPU_ARM926EJS select SUPPORT_SPL -config TARGET_TS4800 - bool "Support TS4800" - select CPU_V7 - select SYS_FSL_ERRATUM_ESDHC_A001 - config ARCH_VF610 bool "Freescale Vybrid" select CPU_V7 @@ -868,6 +690,7 @@ config ARCH_ZYNQ select CLK select SPL_CLK select CLK_ZYNQ + imply CMD_CLK config ARCH_ZYNQMP bool "Support Xilinx ZynqMP Platform" @@ -1253,10 +1076,7 @@ source "arch/arm/cpu/armv8/Kconfig" source "arch/arm/imx-common/Kconfig" source "board/aries/m28evk/Kconfig" -source "board/aries/m53evk/Kconfig" source "board/bosch/shc/Kconfig" -source "board/BuR/brxre1/Kconfig" -source "board/BuR/brppt1/Kconfig" source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" source "board/Marvell/gplugd/Kconfig" @@ -1271,8 +1091,6 @@ source "board/broadcom/bcmnsp/Kconfig" source "board/broadcom/bcmns2/Kconfig" source "board/cavium/thunderx/Kconfig" source "board/cirrus/edb93xx/Kconfig" -source "board/compulab/cm_t335/Kconfig" -source "board/compulab/cm_t43/Kconfig" source "board/creative/xfi3/Kconfig" source "board/freescale/ls2080a/Kconfig" source "board/freescale/ls2080aqds/Kconfig" @@ -1293,11 +1111,6 @@ source "board/freescale/mx28evk/Kconfig" source "board/freescale/mx31ads/Kconfig" source "board/freescale/mx31pdk/Kconfig" source "board/freescale/mx35pdk/Kconfig" -source "board/freescale/mx51evk/Kconfig" -source "board/freescale/mx53ard/Kconfig" -source "board/freescale/mx53evk/Kconfig" -source "board/freescale/mx53loco/Kconfig" -source "board/freescale/mx53smd/Kconfig" source "board/freescale/s32v234evb/Kconfig" source "board/gdsys/a38x/Kconfig" source "board/grinn/chiliboard/Kconfig" @@ -1305,15 +1118,12 @@ source "board/gumstix/pepper/Kconfig" source "board/h2200/Kconfig" source "board/hisilicon/hikey/Kconfig" source "board/imx31_phycore/Kconfig" -source "board/isee/igep0033/Kconfig" +source "board/isee/igep003x/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" source "board/phytec/pcm051/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig" source "board/schulercontrol/sc_sps_1/Kconfig" -source "board/siemens/draco/Kconfig" -source "board/siemens/pxm2/Kconfig" -source "board/siemens/rut/Kconfig" source "board/silica/pengwyn/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" @@ -1323,15 +1133,10 @@ source "board/spear/x600/Kconfig" source "board/st/stv0991/Kconfig" source "board/syteco/zmx25/Kconfig" source "board/tcl/sl50/Kconfig" -source "board/ti/am335x/Kconfig" -source "board/ti/am43xx/Kconfig" source "board/birdland/bav335x/Kconfig" -source "board/ti/ti814x/Kconfig" -source "board/ti/ti816x/Kconfig" source "board/timll/devkit3250/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" source "board/technologic/ts4600/Kconfig" -source "board/technologic/ts4800/Kconfig" source "board/vscom/baltos/Kconfig" source "board/woodburn/Kconfig" source "board/work-microwave/work_92105/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 040556c..3e93fd6 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -64,7 +64,7 @@ machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X machine-$(CONFIG_ORION5X) += orion5x -machine-$(CONFIG_ARCH_OMAP2) += omap2 +machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx machine-$(CONFIG_ARCH_SUNXI) += sunxi machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 907c693..2143633 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -6,7 +6,7 @@ # ifndef CONFIG_STANDALONE_LOAD_ADDR -ifneq ($(CONFIG_ARCH_OMAP2),) +ifneq ($(CONFIG_ARCH_OMAP2PLUS),) CONFIG_STANDALONE_LOAD_ADDR = 0x80300000 else CONFIG_STANDALONE_LOAD_ADDR = 0xc100000 @@ -45,7 +45,7 @@ endif # Only test once ifeq ($(CONFIG_$(SPL_)SYS_THUMB_BUILD),y) -archprepare: checkthumb +archprepare: checkthumb checkgcc6 checkthumb: @if test "$(call cc-name)" = "gcc" -a \ @@ -55,8 +55,18 @@ checkthumb: echo '*** Your board is configured for THUMB mode.'; \ false; \ fi +else +archprepare: checkgcc6 endif +checkgcc6: + @if test "$(call cc-name)" = "gcc" -a \ + "$(call cc-version)" -lt "0600"; then \ + echo -n '*** Your GCC is older than 6.0 and will not be '; \ + echo 'supported starting in v2018.01.'; \ + fi + + # Try if EABI is supported, else fall back to old API, # i. e. for example: # - with ELDK 4.2 (EABI supported), use: diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 02e8778..5fac252 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,12 +12,13 @@ obj-y += cache_v7.o cache_v7_asm.o obj-y += cpu.o cp15.o obj-y += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_ARCH_MX7ULP)$(CONFIG_LS102XA),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_ARCH_MX7ULP)$(CONFIG_ARCH_LS1021A),) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif endif +obj-$(CONFIG_ARM_SMCCC) += smccc-call.o obj-$(CONFIG_ARMV7_NONSEC) += nonsec_virt.o virt-v7.o virt-dt.o obj-$(CONFIG_ARMV7_PSCI) += psci.o psci-common.o diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index ae5e794..d21ad39 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -94,8 +94,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) } #endif - fdt_fixup_ethernet(blob); - off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); while (off != -FDT_ERR_NOTFOUND) { val = gd->cpu_clk; diff --git a/arch/arm/cpu/armv7/mx5/Kconfig b/arch/arm/cpu/armv7/mx5/Kconfig index 7b55747..ef37c35 100644 --- a/arch/arm/cpu/armv7/mx5/Kconfig +++ b/arch/arm/cpu/armv7/mx5/Kconfig @@ -14,24 +14,63 @@ choice prompt "MX5 board select" optional -config TARGET_USBARMORY - bool "Support USB armory" - select CPU_V7 +config TARGET_M53EVK + bool "Support m53evk" + select MX53 + select SUPPORT_SPL + +config TARGET_MX51EVK + bool "Support mx51evk" + select BOARD_LATE_INIT + select MX51 + +config TARGET_MX53ARD + bool "Support mx53ard" + select MX53 config TARGET_MX53CX9020 bool "Support CX9020" select BOARD_LATE_INIT - select CPU_V7 select MX53 select DM select DM_SERIAL +config TARGET_MX53EVK + bool "Support mx53evk" + select BOARD_LATE_INIT + select MX53 + +config TARGET_MX53LOCO + bool "Support mx53loco" + select BOARD_LATE_INIT + select MX53 + +config TARGET_MX53SMD + bool "Support mx53smd" + select MX53 + +config TARGET_TS4800 + bool "Support TS4800" + select MX51 + select SYS_FSL_ERRATUM_ESDHC_A001 + +config TARGET_USBARMORY + bool "Support USB armory" + select MX53 + endchoice config SYS_SOC default "mx5" +source "board/aries/m53evk/Kconfig" source "board/beckhoff/mx53cx9020/Kconfig" +source "board/freescale/mx51evk/Kconfig" +source "board/freescale/mx53ard/Kconfig" +source "board/freescale/mx53evk/Kconfig" +source "board/freescale/mx53loco/Kconfig" +source "board/freescale/mx53smd/Kconfig" source "board/inversepath/usbarmory/Kconfig" +source "board/technologic/ts4800/Kconfig" endif diff --git a/arch/arm/cpu/armv7/smccc-call.S b/arch/arm/cpu/armv7/smccc-call.S new file mode 100644 index 0000000..c2fdbad --- /dev/null +++ b/arch/arm/cpu/armv7/smccc-call.S @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2015, Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0 + */ +#include <linux/linkage.h> + +#include <asm/opcodes-sec.h> +#include <asm/opcodes-virt.h> + +#define UNWIND(x...) + /* + * Wrap c macros in asm macros to delay expansion until after the + * SMCCC asm macro is expanded. + */ + .macro SMCCC_SMC + __SMC(0) + .endm + + .macro SMCCC_HVC + __HVC(0) + .endm + + .macro SMCCC instr +UNWIND( .fnstart) + mov r12, sp + push {r4-r7} +UNWIND( .save {r4-r7}) + ldm r12, {r4-r7} + \instr + pop {r4-r7} + ldr r12, [sp, #(4 * 4)] + stm r12, {r0-r3} + bx lr +UNWIND( .fnend) + .endm + +/* + * void smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, + * unsigned long a3, unsigned long a4, unsigned long a5, + * unsigned long a6, unsigned long a7, struct arm_smccc_res *res, + * struct arm_smccc_quirk *quirk) + */ +ENTRY(__arm_smccc_smc) + SMCCC SMCCC_SMC +ENDPROC(__arm_smccc_smc) + +/* + * void smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2, + * unsigned long a3, unsigned long a4, unsigned long a5, + * unsigned long a6, unsigned long a7, struct arm_smccc_res *res, + * struct arm_smccc_quirk *quirk) + */ +ENTRY(__arm_smccc_hvc) + SMCCC SMCCC_HVC +ENDPROC(__arm_smccc_hvc) diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 1a6aee9..f06fd28 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -283,6 +283,18 @@ skip_errata_621766: skip_errata_725233: #endif +#ifdef CONFIG_ARM_ERRATA_852421 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 24 @ set bit #24 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + +#ifdef CONFIG_ARM_ERRATA_852423 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 12 @ set bit #12 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + mov pc, r5 @ back to my caller ENDPROC(cpu_init_cp15) diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 65915ee..c447085 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -16,6 +16,8 @@ obj-y += tlb.o obj-y += transition.o obj-y += fwcall.o obj-y += cpu-dt.o +obj-$(CONFIG_ARM_SMCCC) += smccc-call.o + ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o endif diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c index 5156a15..e3c8aa2 100644 --- a/arch/arm/cpu/armv8/cpu-dt.c +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -7,25 +7,19 @@ #include <common.h> #include <asm/psci.h> #include <asm/system.h> -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT #include <asm/armv8/sec_firmware.h> -#endif +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT int psci_update_dt(void *fdt) { -#ifdef CONFIG_MP -#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) - -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT /* * If the PSCI in SEC Firmware didn't work, avoid to update the * device node of PSCI. But still return 0 instead of an error * number to support detecting PSCI dynamically and then switching * the SMP boot method between PSCI and spin-table. */ - if (sec_firmware_support_psci_version() == 0xffffffff) + if (sec_firmware_support_psci_version() == PSCI_INVALID_VER) return 0; -#endif fdt_psci(fdt); #if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_ARMV8_SECURE_BASE) @@ -34,7 +28,6 @@ int psci_update_dt(void *fdt) __secure_end - __secure_start); #endif -#endif -#endif return 0; } +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index b24462b..4c16c4c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -36,6 +36,7 @@ config ARCH_LS1046A select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008336 select SYS_FSL_ERRATUM_A008511 + select SYS_FSL_ERRATUM_A008850 select SYS_FSL_ERRATUM_A009801 select SYS_FSL_ERRATUM_A009803 select SYS_FSL_ERRATUM_A009942 @@ -63,6 +64,8 @@ config ARCH_LS2080A select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE select SYS_FSL_SRDS_2 + select FSL_TZASC_1 + select FSL_TZASC_2 select SYS_FSL_ERRATUM_A008336 select SYS_FSL_ERRATUM_A008511 select SYS_FSL_ERRATUM_A008514 @@ -171,6 +174,30 @@ config SYS_LS_PPA_FW_ADDR QSPI flash, this address is a directly memory-mapped. If it is in a serial accessed flash, such as NAND and SD card, it is a byte offset. + +config SYS_LS_PPA_ESBC_ADDR + hex "hdr address of PPA firmware loading from" + depends on FSL_LS_PPA && CHAIN_OF_TRUST + default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A + default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A + default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A + default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3 + default 0x700000 if SYS_LS_PPA_FW_IN_MMC + default 0x700000 if SYS_LS_PPA_FW_IN_NAND + help + If the PPA header firmware locate at XIP flash, such as NOR or + QSPI flash, this address is a directly memory-mapped. + If it is in a serial accessed flash, such as NAND and SD + card, it is a byte offset. + +config LS_PPA_ESBC_HDR_SIZE + hex "Length of PPA ESBC header" + depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP + default 0x2000 + help + Length (in bytes) of PPA ESBC header to be copied from MMC/SD or + NAND to memory to validate PPA image. + endmenu config SYS_FSL_ERRATUM_A010315 @@ -223,6 +250,12 @@ config SYS_FSL_SRDS_2 config SYS_HAS_SERDES bool +config FSL_TZASC_1 + bool + +config FSL_TZASC_2 + bool + endmenu menu "Layerscape clock tree configuration" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index c9ab93e..e3ce018 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -22,11 +22,11 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o endif endif -ifneq ($(CONFIG_LS2080A),) +ifneq ($(CONFIG_ARCH_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o endif -ifneq ($(CONFIG_LS1043A),) +ifneq ($(CONFIG_ARCH_LS1043A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d446527..bb02960 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -15,18 +15,14 @@ #include <asm/arch/soc.h> #include <asm/arch/cpu.h> #include <asm/arch/speed.h> -#ifdef CONFIG_MP #include <asm/arch/mp.h> -#endif #include <efi_loader.h> #include <fm_eth.h> #include <fsl-mc/fsl_mc.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT #include <asm/armv8/sec_firmware.h> -#endif #ifdef CONFIG_SYS_FSL_DDR #include <fsl_ddr.h> #endif @@ -92,7 +88,7 @@ static inline void early_mmu_setup(void) static void fix_pcie_mmu_map(void) { -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A unsigned int i; u32 svr, ver; struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -475,13 +471,19 @@ int cpu_eth_init(bd_t *bis) return error; } -int arch_early_init_r(void) +static inline int check_psci(void) { -#ifdef CONFIG_MP - int rv = 1; - u32 psci_ver = 0xffffffff; -#endif + unsigned int psci_ver; + psci_ver = sec_firmware_support_psci_version(); + if (psci_ver == PSCI_INVALID_VER) + return 1; + + return 0; +} + +int arch_early_init_r(void) +{ #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 u32 svr_dev_id; /* @@ -495,18 +497,13 @@ int arch_early_init_r(void) #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) erratum_a009942_check_cpo(); #endif -#ifdef CONFIG_MP -#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \ - defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) - /* Check the psci version to determine if the psci is supported */ - psci_ver = sec_firmware_support_psci_version(); -#endif - if (psci_ver == 0xffffffff) { - rv = fsl_layerscape_wake_seconday_cores(); - if (rv) + if (check_psci()) { + debug("PSCI: PSCI does not exist.\n"); + + /* if PSCI does not exist, boot secondary cores here */ + if (fsl_layerscape_wake_seconday_cores()) printf("Did not wake secondary cores\n"); } -#endif #ifdef CONFIG_SYS_HAS_SERDES fsl_serdes_init(); @@ -523,7 +520,7 @@ int timer_init(void) #ifdef CONFIG_FSL_LSCH3 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; #endif -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET; u32 svr_dev_id; #endif @@ -541,7 +538,7 @@ int timer_init(void) out_le32(cltbenr, 0xf); #endif -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A /* * In certain Layerscape SoCs, the clock for each core's * has an enable bit in the PMU Physical Core Time Base Enable diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 762a95b..05c4577 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -373,8 +373,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif - do_fixup_by_compat_u32(blob, "fixed-clock", - "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); + do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency", + CONFIG_SYS_CLK_FREQ, 1); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index a2185f2..f427356 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -76,7 +76,7 @@ ENTRY(lowlevel_init) #ifdef CONFIG_FSL_LSCH3 /* Set Wuo bit for RN-I 20 */ -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A ldr x0, =CCI_AUX_CONTROL_BASE(20) ldr x1, =0x00000010 bl ccn504_set_aux @@ -229,38 +229,40 @@ ENTRY(lowlevel_init) * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just * placeholders. */ +#ifdef CONFIG_FSL_TZASC_1 ldr x1, =TZASC_GATE_KEEPER(0) ldr w0, [x1] /* Filter 0 Gate Keeper Register */ orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */ str w0, [x1] - ldr x1, =TZASC_GATE_KEEPER(1) - ldr w0, [x1] /* Filter 0 Gate Keeper Register */ - orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */ - str w0, [x1] - ldr x1, =TZASC_REGION_ATTRIBUTES_0(0) ldr w0, [x1] /* Region-0 Attributes Register */ orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */ orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */ str w0, [x1] + ldr x1, =TZASC_REGION_ID_ACCESS_0(0) + ldr w0, [x1] /* Region-0 Access Register */ + mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ + str w0, [x1] +#endif +#ifdef CONFIG_FSL_TZASC_2 + ldr x1, =TZASC_GATE_KEEPER(1) + ldr w0, [x1] /* Filter 0 Gate Keeper Register */ + orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */ + str w0, [x1] + ldr x1, =TZASC_REGION_ATTRIBUTES_0(1) ldr w0, [x1] /* Region-1 Attributes Register */ orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */ orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */ str w0, [x1] - ldr x1, =TZASC_REGION_ID_ACCESS_0(0) - ldr w0, [x1] /* Region-0 Access Register */ - mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ - str w0, [x1] - ldr x1, =TZASC_REGION_ID_ACCESS_0(1) ldr w0, [x1] /* Region-1 Attributes Register */ mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ str w0, [x1] - +#endif isb dsb sy #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c index ab83e85..4db3c76 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c @@ -70,6 +70,7 @@ static struct serdes_config serdes2_cfg_tbl[] = { SATA2 } }, {0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 } }, + {0x51, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, {0x57, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII15, SGMII16 } }, {} }; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c index b35ad5f..26c47a1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c @@ -37,13 +37,20 @@ int ppa_init(void) int ret; #ifdef CONFIG_CHAIN_OF_TRUST - uintptr_t ppa_esbc_hdr = CONFIG_SYS_LS_PPA_ESBC_ADDR; + uintptr_t ppa_esbc_hdr = 0; uintptr_t ppa_img_addr = 0; +#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \ + defined(CONFIG_SYS_LS_PPA_FW_IN_NAND) + void *ppa_hdr_ddr; +#endif #endif #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR; debug("%s: PPA image load from XIP\n", __func__); +#ifdef CONFIG_CHAIN_OF_TRUST + ppa_esbc_hdr = CONFIG_SYS_LS_PPA_ESBC_ADDR; +#endif #else /* !CONFIG_SYS_LS_PPA_FW_IN_XIP */ size_t fw_length, fdt_header_len = sizeof(struct fdt_header); @@ -53,7 +60,7 @@ int ppa_init(void) int dev = CONFIG_SYS_MMC_ENV_DEV; struct fdt_header *fitp; u32 cnt; - u32 blk = CONFIG_SYS_LS_PPA_FW_ADDR / 512; + u32 blk; debug("%s: PPA image load from eMMC/SD\n", __func__); @@ -81,6 +88,7 @@ int ppa_init(void) return -ENOMEM; } + blk = CONFIG_SYS_LS_PPA_FW_ADDR / 512; cnt = DIV_ROUND_UP(fdt_header_len, 512); debug("%s: MMC read PPA FIT header: dev # %u, block # %u, count %u\n", __func__, dev, blk, cnt); @@ -102,6 +110,29 @@ int ppa_init(void) return ret; } +#ifdef CONFIG_CHAIN_OF_TRUST + ppa_hdr_ddr = malloc(CONFIG_LS_PPA_ESBC_HDR_SIZE); + if (!ppa_hdr_ddr) { + printf("PPA: malloc failed for PPA header\n"); + return -ENOMEM; + } + + blk = CONFIG_SYS_LS_PPA_ESBC_ADDR >> 9; + cnt = DIV_ROUND_UP(CONFIG_LS_PPA_ESBC_HDR_SIZE, 512); + ret = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, ppa_hdr_ddr); + if (ret != cnt) { + free(ppa_hdr_ddr); + printf("MMC/SD read of PPA header failed\n"); + return -EIO; + } + debug("Read PPA header to 0x%p\n", ppa_hdr_ddr); + + /* flush cache after read */ + flush_cache((ulong)ppa_hdr_ddr, cnt * 512); + + ppa_esbc_hdr = (uintptr_t)ppa_hdr_ddr; +#endif + fw_length = fdt_totalsize(fitp); free(fitp); @@ -113,6 +144,7 @@ int ppa_init(void) return -ENOMEM; } + blk = CONFIG_SYS_LS_PPA_FW_ADDR / 512; cnt = DIV_ROUND_UP(fw_length, 512); debug("%s: MMC read PPA FIT image: dev # %u, block # %u, count %u\n", __func__, dev, blk, cnt); @@ -148,6 +180,31 @@ int ppa_init(void) return ret; } +#ifdef CONFIG_CHAIN_OF_TRUST + ppa_hdr_ddr = malloc(CONFIG_LS_PPA_ESBC_HDR_SIZE); + if (!ppa_hdr_ddr) { + printf("PPA: malloc failed for PPA header\n"); + return -ENOMEM; + } + + fw_length = CONFIG_LS_PPA_ESBC_HDR_SIZE; + + ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_ESBC_ADDR, + &fw_length, (u_char *)ppa_hdr_ddr); + if (ret == -EUCLEAN) { + free(ppa_hdr_ddr); + printf("NAND read of PPA firmware at offset 0x%x failed\n", + CONFIG_SYS_LS_PPA_FW_ADDR); + return -EIO; + } + debug("Read PPA header to 0x%p\n", ppa_hdr_ddr); + + /* flush cache after read */ + flush_cache((ulong)ppa_hdr_ddr, fw_length); + + ppa_esbc_hdr = (uintptr_t)ppa_hdr_ddr; +#endif + fw_length = fdt_totalsize(&fit); ppa_fit_addr = malloc(fw_length); @@ -177,14 +234,25 @@ int ppa_init(void) #ifdef CONFIG_CHAIN_OF_TRUST ppa_img_addr = (uintptr_t)ppa_fit_addr; if (fsl_check_boot_mode_secure() != 0) { + /* + * In case of failure in validation, fsl_secboot_validate + * would not return back in case of Production environment + * with ITS=1. In Development environment (ITS=0 and + * SB_EN=1), the function may return back in case of + * non-fatal failures. + */ ret = fsl_secboot_validate(ppa_esbc_hdr, - CONFIG_PPA_KEY_HASH, + PPA_KEY_HASH, &ppa_img_addr); if (ret != 0) printf("PPA validation failed\n"); else printf("PPA validation Successful\n"); } +#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \ + defined(CONFIG_SYS_LS_PPA_FW_IN_NAND) + free(ppa_hdr_ddr); +#endif #endif #ifdef CONFIG_FSL_LSCH3 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 73a8680..eb730e8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -41,13 +41,31 @@ u32 spl_boot_mode(const u32 boot_device) } #ifdef CONFIG_SPL_BUILD + +void spl_board_init(void) +{ +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_LSCH2) + /* + * In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + u32 val; + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +#endif +} + void board_init_f(ulong dummy) { /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); board_early_init_f(); timer_init(); -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A env_init(); #endif get_clocks(); diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index ec9cf40..4afa3ad 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -227,7 +227,7 @@ unsigned int sec_firmware_support_psci_version(void) if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) return _sec_firmware_support_psci_version(); - return 0xffffffff; + return PSCI_INVALID_VER; } #endif diff --git a/arch/arm/cpu/armv8/smccc-call.S b/arch/arm/cpu/armv8/smccc-call.S new file mode 100644 index 0000000..bbb6cba --- /dev/null +++ b/arch/arm/cpu/armv8/smccc-call.S @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2015, Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0 + */ +#include <linux/linkage.h> +#include <linux/arm-smccc.h> +#include <generated/asm-offsets.h> + + .macro SMCCC instr + .cfi_startproc + \instr #0 + ldr x4, [sp] + stp x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS] + stp x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS] + ldr x4, [sp, #8] + cbz x4, 1f /* no quirk structure */ + ldr x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS] + cmp x9, #ARM_SMCCC_QUIRK_QCOM_A6 + b.ne 1f + str x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS] +1: ret + .cfi_endproc + .endm + +/* + * void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, + * unsigned long a3, unsigned long a4, unsigned long a5, + * unsigned long a6, unsigned long a7, struct arm_smccc_res *res, + * struct arm_smccc_quirk *quirk) + */ +ENTRY(__arm_smccc_smc) + SMCCC smc +ENDPROC(__arm_smccc_smc) + +/* + * void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2, + * unsigned long a3, unsigned long a4, unsigned long a5, + * unsigned long a6, unsigned long a7, struct arm_smccc_res *res, + * struct arm_smccc_quirk *quirk) + */ +ENTRY(__arm_smccc_hvc) + SMCCC hvc +ENDPROC(__arm_smccc_hvc) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 959e23d..4d656ce 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -153,6 +153,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_de0_nano_soc.dtb \ socfpga_cyclone5_de1_soc.dtb \ + socfpga_cyclone5_de10_nano.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sr1500.dtb \ @@ -166,7 +167,7 @@ dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ am571x-idk.dtb dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb -dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \ +dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ ls1021a-qds-lpuart.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ ls1021a-iot-duart.dtb @@ -184,7 +185,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb -dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb +dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \ + stm32f769-disco.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts index dc13952..723941a 100644 --- a/arch/arm/dts/ast2500-evb.dts +++ b/arch/arm/dts/ast2500-evb.dts @@ -21,3 +21,18 @@ &sdrammc { clock-frequency = <400000000>; }; + +&wdt1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&wdt2 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&wdt3 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi index c95a7ba..7f80bad 100644 --- a/arch/arm/dts/ast2500-u-boot.dtsi +++ b/arch/arm/dts/ast2500-u-boot.dtsi @@ -1,4 +1,5 @@ #include <dt-bindings/clock/ast2500-scu.h> +#include <dt-bindings/reset/ast2500-reset.h> #include "ast2500.dtsi" @@ -11,12 +12,21 @@ #reset-cells = <1>; }; + rst: reset-controller { + u-boot,dm-pre-reloc; + compatible = "aspeed,ast2500-reset"; + aspeed,wdt = <&wdt1>; + #reset-cells = <1>; + }; + sdrammc: sdrammc@1e6e0000 { u-boot,dm-pre-reloc; compatible = "aspeed,ast2500-sdrammc"; reg = <0x1e6e0000 0x174 0x1e6e0200 0x1d4 >; + #reset-cells = <1>; clocks = <&scu PLL_MPLL>; + resets = <&rst AST_RESET_SDRAM>; }; ahb { @@ -24,30 +34,39 @@ apb { u-boot,dm-pre-reloc; + }; + + }; +}; + +&uart1 { + clocks = <&scu PCLK_UART1>; +}; - timer: timer@1e782000 { - u-boot,dm-pre-reloc; - }; +&uart2 { + clocks = <&scu PCLK_UART2>; +}; - uart1: serial@1e783000 { - clocks = <&scu PCLK_UART1>; - }; +&uart3 { + clocks = <&scu PCLK_UART3>; +}; + +&uart4 { + clocks = <&scu PCLK_UART4>; +}; - uart2: serial@1e78d000 { - clocks = <&scu PCLK_UART2>; - }; +&uart5 { + clocks = <&scu PCLK_UART5>; +}; - uart3: serial@1e78e000 { - clocks = <&scu PCLK_UART3>; - }; +&timer { + u-boot,dm-pre-reloc; +}; - uart4: serial@1e78f000 { - clocks = <&scu PCLK_UART4>; - }; +&mac0 { + clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>; +}; - uart5: serial@1e784000 { - clocks = <&scu PCLK_UART5>; - }; - }; - }; +&mac1 { + clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>; }; diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi index 97fac69..7e0ad3a 100644 --- a/arch/arm/dts/ast2500.dtsi +++ b/arch/arm/dts/ast2500.dtsi @@ -1,6 +1,6 @@ /* * This device tree is copied from - * https://raw.githubusercontent.com/torvalds/linux/02440622/arch/arm/boot/dts/ + * https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi */ #include "skeleton.dtsi" @@ -36,6 +36,22 @@ reg = <0x1e6c0080 0x80>; }; + mac0: ethernet@1e660000 { + compatible = "faraday,ftgmac100"; + reg = <0x1e660000 0x180>; + interrupts = <2>; + no-hw-checksum; + status = "disabled"; + }; + + mac1: ethernet@1e680000 { + compatible = "faraday,ftgmac100"; + reg = <0x1e680000 0x180>; + interrupts = <3>; + no-hw-checksum; + status = "disabled"; + }; + apb { compatible = "simple-bus"; #address-cells = <1>; @@ -48,6 +64,822 @@ reg = <0x1e6e2070 0x04>; }; + syscon: syscon@1e6e2000 { + compatible = "aspeed,g5-scu", "syscon", "simple-mfd"; + reg = <0x1e6e2000 0x1a8>; + + pinctrl: pinctrl { + compatible = "aspeed,g5-pinctrl"; + aspeed,external-nodes = <&gfx &lhc>; + + pinctrl_acpi_default: acpi_default { + function = "ACPI"; + groups = "ACPI"; + }; + + pinctrl_adc0_default: adc0_default { + function = "ADC0"; + groups = "ADC0"; + }; + + pinctrl_adc1_default: adc1_default { + function = "ADC1"; + groups = "ADC1"; + }; + + pinctrl_adc10_default: adc10_default { + function = "ADC10"; + groups = "ADC10"; + }; + + pinctrl_adc11_default: adc11_default { + function = "ADC11"; + groups = "ADC11"; + }; + + pinctrl_adc12_default: adc12_default { + function = "ADC12"; + groups = "ADC12"; + }; + + pinctrl_adc13_default: adc13_default { + function = "ADC13"; + groups = "ADC13"; + }; + + pinctrl_adc14_default: adc14_default { + function = "ADC14"; + groups = "ADC14"; + }; + + pinctrl_adc15_default: adc15_default { + function = "ADC15"; + groups = "ADC15"; + }; + + pinctrl_adc2_default: adc2_default { + function = "ADC2"; + groups = "ADC2"; + }; + + pinctrl_adc3_default: adc3_default { + function = "ADC3"; + groups = "ADC3"; + }; + + pinctrl_adc4_default: adc4_default { + function = "ADC4"; + groups = "ADC4"; + }; + + pinctrl_adc5_default: adc5_default { + function = "ADC5"; + groups = "ADC5"; + }; + + pinctrl_adc6_default: adc6_default { + function = "ADC6"; + groups = "ADC6"; + }; + + pinctrl_adc7_default: adc7_default { + function = "ADC7"; + groups = "ADC7"; + }; + + pinctrl_adc8_default: adc8_default { + function = "ADC8"; + groups = "ADC8"; + }; + + pinctrl_adc9_default: adc9_default { + function = "ADC9"; + groups = "ADC9"; + }; + + pinctrl_bmcint_default: bmcint_default { + function = "BMCINT"; + groups = "BMCINT"; + }; + + pinctrl_ddcclk_default: ddcclk_default { + function = "DDCCLK"; + groups = "DDCCLK"; + }; + + pinctrl_ddcdat_default: ddcdat_default { + function = "DDCDAT"; + groups = "DDCDAT"; + }; + + pinctrl_espi_default: espi_default { + function = "ESPI"; + groups = "ESPI"; + }; + + pinctrl_fwspics1_default: fwspics1_default { + function = "FWSPICS1"; + groups = "FWSPICS1"; + }; + + pinctrl_fwspics2_default: fwspics2_default { + function = "FWSPICS2"; + groups = "FWSPICS2"; + }; + + pinctrl_gpid0_default: gpid0_default { + function = "GPID0"; + groups = "GPID0"; + }; + + pinctrl_gpid2_default: gpid2_default { + function = "GPID2"; + groups = "GPID2"; + }; + + pinctrl_gpid4_default: gpid4_default { + function = "GPID4"; + groups = "GPID4"; + }; + + pinctrl_gpid6_default: gpid6_default { + function = "GPID6"; + groups = "GPID6"; + }; + + pinctrl_gpie0_default: gpie0_default { + function = "GPIE0"; + groups = "GPIE0"; + }; + + pinctrl_gpie2_default: gpie2_default { + function = "GPIE2"; + groups = "GPIE2"; + }; + + pinctrl_gpie4_default: gpie4_default { + function = "GPIE4"; + groups = "GPIE4"; + }; + + pinctrl_gpie6_default: gpie6_default { + function = "GPIE6"; + groups = "GPIE6"; + }; + + pinctrl_i2c10_default: i2c10_default { + function = "I2C10"; + groups = "I2C10"; + }; + + pinctrl_i2c11_default: i2c11_default { + function = "I2C11"; + groups = "I2C11"; + }; + + pinctrl_i2c12_default: i2c12_default { + function = "I2C12"; + groups = "I2C12"; + }; + + pinctrl_i2c13_default: i2c13_default { + function = "I2C13"; + groups = "I2C13"; + }; + + pinctrl_i2c14_default: i2c14_default { + function = "I2C14"; + groups = "I2C14"; + }; + + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; + + pinctrl_i2c4_default: i2c4_default { + function = "I2C4"; + groups = "I2C4"; + }; + + pinctrl_i2c5_default: i2c5_default { + function = "I2C5"; + groups = "I2C5"; + }; + + pinctrl_i2c6_default: i2c6_default { + function = "I2C6"; + groups = "I2C6"; + }; + + pinctrl_i2c7_default: i2c7_default { + function = "I2C7"; + groups = "I2C7"; + }; + + pinctrl_i2c8_default: i2c8_default { + function = "I2C8"; + groups = "I2C8"; + }; + + pinctrl_i2c9_default: i2c9_default { + function = "I2C9"; + groups = "I2C9"; + }; + + pinctrl_lad0_default: lad0_default { + function = "LAD0"; + groups = "LAD0"; + }; + + pinctrl_lad1_default: lad1_default { + function = "LAD1"; + groups = "LAD1"; + }; + + pinctrl_lad2_default: lad2_default { + function = "LAD2"; + groups = "LAD2"; + }; + + pinctrl_lad3_default: lad3_default { + function = "LAD3"; + groups = "LAD3"; + }; + + pinctrl_lclk_default: lclk_default { + function = "LCLK"; + groups = "LCLK"; + }; + + pinctrl_lframe_default: lframe_default { + function = "LFRAME"; + groups = "LFRAME"; + }; + + pinctrl_lpchc_default: lpchc_default { + function = "LPCHC"; + groups = "LPCHC"; + }; + + pinctrl_lpcpd_default: lpcpd_default { + function = "LPCPD"; + groups = "LPCPD"; + }; + + pinctrl_lpcplus_default: lpcplus_default { + function = "LPCPLUS"; + groups = "LPCPLUS"; + }; + + pinctrl_lpcpme_default: lpcpme_default { + function = "LPCPME"; + groups = "LPCPME"; + }; + + pinctrl_lpcrst_default: lpcrst_default { + function = "LPCRST"; + groups = "LPCRST"; + }; + + pinctrl_lpcsmi_default: lpcsmi_default { + function = "LPCSMI"; + groups = "LPCSMI"; + }; + + pinctrl_lsirq_default: lsirq_default { + function = "LSIRQ"; + groups = "LSIRQ"; + }; + + pinctrl_mac1link_default: mac1link_default { + function = "MAC1LINK"; + groups = "MAC1LINK"; + }; + + pinctrl_mac2link_default: mac2link_default { + function = "MAC2LINK"; + groups = "MAC2LINK"; + }; + + pinctrl_mdio1_default: mdio1_default { + function = "MDIO1"; + groups = "MDIO1"; + }; + + pinctrl_mdio2_default: mdio2_default { + function = "MDIO2"; + groups = "MDIO2"; + }; + + pinctrl_ncts1_default: ncts1_default { + function = "NCTS1"; + groups = "NCTS1"; + }; + + pinctrl_ncts2_default: ncts2_default { + function = "NCTS2"; + groups = "NCTS2"; + }; + + pinctrl_ncts3_default: ncts3_default { + function = "NCTS3"; + groups = "NCTS3"; + }; + + pinctrl_ncts4_default: ncts4_default { + function = "NCTS4"; + groups = "NCTS4"; + }; + + pinctrl_ndcd1_default: ndcd1_default { + function = "NDCD1"; + groups = "NDCD1"; + }; + + pinctrl_ndcd2_default: ndcd2_default { + function = "NDCD2"; + groups = "NDCD2"; + }; + + pinctrl_ndcd3_default: ndcd3_default { + function = "NDCD3"; + groups = "NDCD3"; + }; + + pinctrl_ndcd4_default: ndcd4_default { + function = "NDCD4"; + groups = "NDCD4"; + }; + + pinctrl_ndsr1_default: ndsr1_default { + function = "NDSR1"; + groups = "NDSR1"; + }; + + pinctrl_ndsr2_default: ndsr2_default { + function = "NDSR2"; + groups = "NDSR2"; + }; + + pinctrl_ndsr3_default: ndsr3_default { + function = "NDSR3"; + groups = "NDSR3"; + }; + + pinctrl_ndsr4_default: ndsr4_default { + function = "NDSR4"; + groups = "NDSR4"; + }; + + pinctrl_ndtr1_default: ndtr1_default { + function = "NDTR1"; + groups = "NDTR1"; + }; + + pinctrl_ndtr2_default: ndtr2_default { + function = "NDTR2"; + groups = "NDTR2"; + }; + + pinctrl_ndtr3_default: ndtr3_default { + function = "NDTR3"; + groups = "NDTR3"; + }; + + pinctrl_ndtr4_default: ndtr4_default { + function = "NDTR4"; + groups = "NDTR4"; + }; + + pinctrl_nri1_default: nri1_default { + function = "NRI1"; + groups = "NRI1"; + }; + + pinctrl_nri2_default: nri2_default { + function = "NRI2"; + groups = "NRI2"; + }; + + pinctrl_nri3_default: nri3_default { + function = "NRI3"; + groups = "NRI3"; + }; + + pinctrl_nri4_default: nri4_default { + function = "NRI4"; + groups = "NRI4"; + }; + + pinctrl_nrts1_default: nrts1_default { + function = "NRTS1"; + groups = "NRTS1"; + }; + + pinctrl_nrts2_default: nrts2_default { + function = "NRTS2"; + groups = "NRTS2"; + }; + + pinctrl_nrts3_default: nrts3_default { + function = "NRTS3"; + groups = "NRTS3"; + }; + + pinctrl_nrts4_default: nrts4_default { + function = "NRTS4"; + groups = "NRTS4"; + }; + + pinctrl_oscclk_default: oscclk_default { + function = "OSCCLK"; + groups = "OSCCLK"; + }; + + pinctrl_pewake_default: pewake_default { + function = "PEWAKE"; + groups = "PEWAKE"; + }; + + pinctrl_pnor_default: pnor_default { + function = "PNOR"; + groups = "PNOR"; + }; + + pinctrl_pwm0_default: pwm0_default { + function = "PWM0"; + groups = "PWM0"; + }; + + pinctrl_pwm1_default: pwm1_default { + function = "PWM1"; + groups = "PWM1"; + }; + + pinctrl_pwm2_default: pwm2_default { + function = "PWM2"; + groups = "PWM2"; + }; + + pinctrl_pwm3_default: pwm3_default { + function = "PWM3"; + groups = "PWM3"; + }; + + pinctrl_pwm4_default: pwm4_default { + function = "PWM4"; + groups = "PWM4"; + }; + + pinctrl_pwm5_default: pwm5_default { + function = "PWM5"; + groups = "PWM5"; + }; + + pinctrl_pwm6_default: pwm6_default { + function = "PWM6"; + groups = "PWM6"; + }; + + pinctrl_pwm7_default: pwm7_default { + function = "PWM7"; + groups = "PWM7"; + }; + + pinctrl_rgmii1_default: rgmii1_default { + function = "RGMII1"; + groups = "RGMII1"; + }; + + pinctrl_rgmii2_default: rgmii2_default { + function = "RGMII2"; + groups = "RGMII2"; + }; + + pinctrl_rmii1_default: rmii1_default { + function = "RMII1"; + groups = "RMII1"; + }; + + pinctrl_rmii2_default: rmii2_default { + function = "RMII2"; + groups = "RMII2"; + }; + + pinctrl_rxd1_default: rxd1_default { + function = "RXD1"; + groups = "RXD1"; + }; + + pinctrl_rxd2_default: rxd2_default { + function = "RXD2"; + groups = "RXD2"; + }; + + pinctrl_rxd3_default: rxd3_default { + function = "RXD3"; + groups = "RXD3"; + }; + + pinctrl_rxd4_default: rxd4_default { + function = "RXD4"; + groups = "RXD4"; + }; + + pinctrl_salt1_default: salt1_default { + function = "SALT1"; + groups = "SALT1"; + }; + + pinctrl_salt10_default: salt10_default { + function = "SALT10"; + groups = "SALT10"; + }; + + pinctrl_salt11_default: salt11_default { + function = "SALT11"; + groups = "SALT11"; + }; + + pinctrl_salt12_default: salt12_default { + function = "SALT12"; + groups = "SALT12"; + }; + + pinctrl_salt13_default: salt13_default { + function = "SALT13"; + groups = "SALT13"; + }; + + pinctrl_salt14_default: salt14_default { + function = "SALT14"; + groups = "SALT14"; + }; + + pinctrl_salt2_default: salt2_default { + function = "SALT2"; + groups = "SALT2"; + }; + + pinctrl_salt3_default: salt3_default { + function = "SALT3"; + groups = "SALT3"; + }; + + pinctrl_salt4_default: salt4_default { + function = "SALT4"; + groups = "SALT4"; + }; + + pinctrl_salt5_default: salt5_default { + function = "SALT5"; + groups = "SALT5"; + }; + + pinctrl_salt6_default: salt6_default { + function = "SALT6"; + groups = "SALT6"; + }; + + pinctrl_salt7_default: salt7_default { + function = "SALT7"; + groups = "SALT7"; + }; + + pinctrl_salt8_default: salt8_default { + function = "SALT8"; + groups = "SALT8"; + }; + + pinctrl_salt9_default: salt9_default { + function = "SALT9"; + groups = "SALT9"; + }; + + pinctrl_scl1_default: scl1_default { + function = "SCL1"; + groups = "SCL1"; + }; + + pinctrl_scl2_default: scl2_default { + function = "SCL2"; + groups = "SCL2"; + }; + + pinctrl_sd1_default: sd1_default { + function = "SD1"; + groups = "SD1"; + }; + + pinctrl_sd2_default: sd2_default { + function = "SD2"; + groups = "SD2"; + }; + + pinctrl_sda1_default: sda1_default { + function = "SDA1"; + groups = "SDA1"; + }; + + pinctrl_sda2_default: sda2_default { + function = "SDA2"; + groups = "SDA2"; + }; + + pinctrl_sgps1_default: sgps1_default { + function = "SGPS1"; + groups = "SGPS1"; + }; + + pinctrl_sgps2_default: sgps2_default { + function = "SGPS2"; + groups = "SGPS2"; + }; + + pinctrl_sioonctrl_default: sioonctrl_default { + function = "SIOONCTRL"; + groups = "SIOONCTRL"; + }; + + pinctrl_siopbi_default: siopbi_default { + function = "SIOPBI"; + groups = "SIOPBI"; + }; + + pinctrl_siopbo_default: siopbo_default { + function = "SIOPBO"; + groups = "SIOPBO"; + }; + + pinctrl_siopwreq_default: siopwreq_default { + function = "SIOPWREQ"; + groups = "SIOPWREQ"; + }; + + pinctrl_siopwrgd_default: siopwrgd_default { + function = "SIOPWRGD"; + groups = "SIOPWRGD"; + }; + + pinctrl_sios3_default: sios3_default { + function = "SIOS3"; + groups = "SIOS3"; + }; + + pinctrl_sios5_default: sios5_default { + function = "SIOS5"; + groups = "SIOS5"; + }; + + pinctrl_siosci_default: siosci_default { + function = "SIOSCI"; + groups = "SIOSCI"; + }; + + pinctrl_spi1_default: spi1_default { + function = "SPI1"; + groups = "SPI1"; + }; + + pinctrl_spi1cs1_default: spi1cs1_default { + function = "SPI1CS1"; + groups = "SPI1CS1"; + }; + + pinctrl_spi1debug_default: spi1debug_default { + function = "SPI1DEBUG"; + groups = "SPI1DEBUG"; + }; + + pinctrl_spi1passthru_default: spi1passthru_default { + function = "SPI1PASSTHRU"; + groups = "SPI1PASSTHRU"; + }; + + pinctrl_spi2ck_default: spi2ck_default { + function = "SPI2CK"; + groups = "SPI2CK"; + }; + + pinctrl_spi2cs0_default: spi2cs0_default { + function = "SPI2CS0"; + groups = "SPI2CS0"; + }; + + pinctrl_spi2cs1_default: spi2cs1_default { + function = "SPI2CS1"; + groups = "SPI2CS1"; + }; + + pinctrl_spi2miso_default: spi2miso_default { + function = "SPI2MISO"; + groups = "SPI2MISO"; + }; + + pinctrl_spi2mosi_default: spi2mosi_default { + function = "SPI2MOSI"; + groups = "SPI2MOSI"; + }; + + pinctrl_timer3_default: timer3_default { + function = "TIMER3"; + groups = "TIMER3"; + }; + + pinctrl_timer4_default: timer4_default { + function = "TIMER4"; + groups = "TIMER4"; + }; + + pinctrl_timer5_default: timer5_default { + function = "TIMER5"; + groups = "TIMER5"; + }; + + pinctrl_timer6_default: timer6_default { + function = "TIMER6"; + groups = "TIMER6"; + }; + + pinctrl_timer7_default: timer7_default { + function = "TIMER7"; + groups = "TIMER7"; + }; + + pinctrl_timer8_default: timer8_default { + function = "TIMER8"; + groups = "TIMER8"; + }; + + pinctrl_txd1_default: txd1_default { + function = "TXD1"; + groups = "TXD1"; + }; + + pinctrl_txd2_default: txd2_default { + function = "TXD2"; + groups = "TXD2"; + }; + + pinctrl_txd3_default: txd3_default { + function = "TXD3"; + groups = "TXD3"; + }; + + pinctrl_txd4_default: txd4_default { + function = "TXD4"; + groups = "TXD4"; + }; + + pinctrl_uart6_default: uart6_default { + function = "UART6"; + groups = "UART6"; + }; + + pinctrl_usbcki_default: usbcki_default { + function = "USBCKI"; + groups = "USBCKI"; + }; + + pinctrl_vgabiosrom_default: vgabiosrom_default { + function = "VGABIOSROM"; + groups = "VGABIOSROM"; + }; + + pinctrl_vgahs_default: vgahs_default { + function = "VGAHS"; + groups = "VGAHS"; + }; + + pinctrl_vgavs_default: vgavs_default { + function = "VGAVS"; + groups = "VGAVS"; + }; + + pinctrl_vpi24_default: vpi24_default { + function = "VPI24"; + groups = "VPI24"; + }; + + pinctrl_vpo_default: vpo_default { + function = "VPO"; + groups = "VPO"; + }; + + pinctrl_wdtrst1_default: wdtrst1_default { + function = "WDTRST1"; + groups = "WDTRST1"; + }; + + pinctrl_wdtrst2_default: wdtrst2_default { + function = "WDTRST2"; + groups = "WDTRST2"; + }; + + }; + }; + clk_hpll: clk_hpll@1e6e2024 { #clock-cells = <0>; compatible = "aspeed,g5-hpll-clock"; @@ -75,11 +907,27 @@ reg = <0x1e6e202c 0x4>; }; + gfx: display@1e6e6000 { + compatible = "aspeed,ast2500-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + reg-io-width = <4>; + }; + sram@1e720000 { compatible = "mmio-sram"; reg = <0x1e720000 0x9000>; // 36K }; + gpio: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2500-gpio"; + reg = <0x1e780000 0x1000>; + interrupts = <20>; + gpio-ranges = <&pinctrl 0 0 220>; + interrupt-controller; + }; + timer: timer@1e782000 { compatible = "aspeed,ast2400-timer"; reg = <0x1e782000 0x90>; @@ -90,6 +938,7 @@ clocks = <&clk_apb>; }; + wdt1: wdt@1e785000 { compatible = "aspeed,wdt"; reg = <0x1e785000 0x1c>; @@ -119,6 +968,36 @@ status = "disabled"; }; + lpc: lpc@1e789000 { + compatible = "aspeed,ast2500-lpc", "simple-mfd"; + reg = <0x1e789000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e789000 0x1000>; + + lpc_bmc: lpc-bmc@0 { + compatible = "aspeed,ast2500-lpc-bmc"; + reg = <0x0 0x80>; + }; + + lpc_host: lpc-host@80 { + compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; + reg = <0x80 0x1e0>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x80 0x1e0>; + + reg-io-width = <4>; + + lhc: lhc@20 { + compatible = "aspeed,ast2500-lhc"; + reg = <0x20 0x24 0x48 0x8>; + }; + }; + }; + uart2: serial@1e78d000 { compatible = "ns16550a"; reg = <0x1e78d000 0x1000>; diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts new file mode 100644 index 0000000..ee62a50 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2017, Intel Corporation + * + * based on socfpga_cyclone5_de0_nano_soc.dts + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "Terasic DE10-Nano"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + aliases { + ethernet0 = &gmac1; + udc0 = &usb1; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + txen-skew-ps = <0>; + txc-skew-ps = <1860>; + rxdv-skew-ps = <420>; + rxc-skew-ps = <1680>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&mmc0 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi new file mode 100644 index 0000000..5f77f57 --- /dev/null +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -0,0 +1,24 @@ +&pinctrl { + usart1_pins_a: usart1@0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; + }; + fmc_pins: fmc@0 { + u-boot,dm-pre-reloc; + pins + { + u-boot,dm-pre-reloc; + }; + }; +}; + +&fmc { + bank1: bank@0 { + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index 07e0ca7..2c7fa79 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -1,5 +1,6 @@ /* * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com> + * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com> * * Based on: * stm32f469-disco.dts from Linux @@ -46,6 +47,7 @@ /dts-v1/; #include "stm32f746.dtsi" +#include <dt-bindings/memory/stm32-sdram.h> / { model = "STMicroelectronics STM32F746-DISCO board"; @@ -63,6 +65,28 @@ aliases { serial0 = &usart1; spi0 = &qspi; + /* Aliases for gpios so as to use sequence */ + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + }; + + led1 { + compatible = "st,led1"; + led-gpio = <&gpioi 1 0>; + }; + + button1 { + compatible = "st,button1"; + button-gpio = <&gpioi 11 0>; }; }; @@ -70,12 +94,120 @@ clock-frequency = <25000000>; }; +&pinctrl { + usart1_pins_a: usart1@0 { + pins1 { + pinmux = <STM32F746_PA9_FUNC_USART1_TX>; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32F746_PB7_FUNC_USART1_RX>; + bias-disable; + }; + }; + + ethernet_mii: mii@0 { + pins { + pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, + <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, + <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, + <STM32F746_PA2_FUNC_ETH_MDIO>, + <STM32F746_PC1_FUNC_ETH_MDC>, + <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, + <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, + <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, + <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>; + slew-rate = <2>; + }; + }; + + qspi_pins: qspi@0 { + pins { + pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>, + <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>, + <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>, + <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>, + <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>, + <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>; + slew-rate = <2>; + }; + }; + + fmc_pins: fmc@0 { + pins { + pinmux = <STM32F746_PD10_FUNC_FMC_D15>, + <STM32F746_PD9_FUNC_FMC_D14>, + <STM32F746_PD8_FUNC_FMC_D13>, + <STM32F746_PE15_FUNC_FMC_D12>, + <STM32F746_PE14_FUNC_FMC_D11>, + <STM32F746_PE13_FUNC_FMC_D10>, + <STM32F746_PE12_FUNC_FMC_D9>, + <STM32F746_PE11_FUNC_FMC_D8>, + <STM32F746_PE10_FUNC_FMC_D7>, + <STM32F746_PE9_FUNC_FMC_D6>, + <STM32F746_PE8_FUNC_FMC_D5>, + <STM32F746_PE7_FUNC_FMC_D4>, + <STM32F746_PD1_FUNC_FMC_D3>, + <STM32F746_PD0_FUNC_FMC_D2>, + <STM32F746_PD15_FUNC_FMC_D1>, + <STM32F746_PD14_FUNC_FMC_D0>, + + <STM32F746_PE1_FUNC_FMC_NBL1>, + <STM32F746_PE0_FUNC_FMC_NBL0>, + + <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, + <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, + + <STM32F746_PG1_FUNC_FMC_A11>, + <STM32F746_PG0_FUNC_FMC_A10>, + <STM32F746_PF15_FUNC_FMC_A9>, + <STM32F746_PF14_FUNC_FMC_A8>, + <STM32F746_PF13_FUNC_FMC_A7>, + <STM32F746_PF12_FUNC_FMC_A6>, + <STM32F746_PF5_FUNC_FMC_A5>, + <STM32F746_PF4_FUNC_FMC_A4>, + <STM32F746_PF3_FUNC_FMC_A3>, + <STM32F746_PF2_FUNC_FMC_A2>, + <STM32F746_PF1_FUNC_FMC_A1>, + <STM32F746_PF0_FUNC_FMC_A0>, + + <STM32F746_PH3_FUNC_FMC_SDNE0>, + <STM32F746_PH5_FUNC_FMC_SDNWE>, + <STM32F746_PF11_FUNC_FMC_SDNRAS>, + <STM32F746_PG15_FUNC_FMC_SDNCAS>, + <STM32F746_PC3_FUNC_FMC_SDCKE0>, + <STM32F746_PG8_FUNC_FMC_SDCLK>; + slew-rate = <2>; + }; + }; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; status = "okay"; }; +&fmc { + pinctrl-0 = <&fmc_pins>; + pinctrl-names = "default"; + status = "okay"; + + mr-nbanks = <1>; + /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ + bank1: bank@0 { + st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_4 + CAS_3 SDCLK_2 RD_BURST_EN + RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2 + TRP_2 TRCD_2>; + /* refcount = (64msec/total_row_sdram)*freq - 20 */ + st,sdram-refcount = < 1542 >; + }; +}; + &mac { status = "okay"; pinctrl-0 = <ðernet_mii>; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index b2b0b5f..ac24d98 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -1,5 +1,6 @@ /* * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com> + * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com> * * Based on: * stm32f429.dtsi from Linux @@ -70,6 +71,13 @@ status = "disabled"; }; + fmc: fmc@A0000000 { + compatible = "st,stm32-fmc"; + reg = <0xA0000000 0x1000>; + clocks = <&rcc 0 64>; + u-boot,dm-pre-reloc; + }; + qspi: quadspi@A0001000 { compatible = "st,stm32-qspi"; #address-cells = <1>; @@ -78,6 +86,7 @@ reg-names = "QuadSPI", "QuadSPI-memory"; interrupts = <92>; spi-max-frequency = <108000000>; + clocks = <&rcc 0 65>; status = "disabled"; }; usart1: serial@40011000 { @@ -105,43 +114,117 @@ u-boot,dm-pre-reloc; pins-are-numbered; - usart1_pins_a: usart1@0 { - pins1 { - pinmux = <STM32F746_PA9_FUNC_USART1_TX>; - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = <STM32F746_PB7_FUNC_USART1_RX>; - bias-disable; - }; + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x0 0x400>; + clocks = <&rcc 0 0>; + st,bank-name = "GPIOA"; + u-boot,dm-pre-reloc; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x400 0x400>; + clocks = <&rcc 0 1>; + st,bank-name = "GPIOB"; + u-boot,dm-pre-reloc; + }; + + + gpioc: gpio@40020800 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x800 0x400>; + clocks = <&rcc 0 2>; + st,bank-name = "GPIOC"; + u-boot,dm-pre-reloc; + }; + + gpiod: gpio@40020c00 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0xc00 0x400>; + clocks = <&rcc 0 3>; + st,bank-name = "GPIOD"; + u-boot,dm-pre-reloc; }; - ethernet_mii: mii@0 { - pins { - pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, - <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, - <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, - <STM32F746_PA2_FUNC_ETH_MDIO>, - <STM32F746_PC1_FUNC_ETH_MDC>, - <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, - <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, - <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, - <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>; - slew-rate = <2>; - }; + + gpioe: gpio@40021000 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x1000 0x400>; + clocks = <&rcc 0 4>; + st,bank-name = "GPIOE"; + u-boot,dm-pre-reloc; }; - qspi_pins: qspi@0{ - pins { - pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>, - <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>, - <STM32F746_PD11_FUNC_QUADSPI_BK1_IO0>, - <STM32F746_PD12_FUNC_QUADSPI_BK1_IO1>, - <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>, - <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>; - slew-rate = <2>; - }; + + gpiof: gpio@40021400 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x1400 0x400>; + clocks = <&rcc 0 5>; + st,bank-name = "GPIOF"; + u-boot,dm-pre-reloc; }; + + gpiog: gpio@40021800 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x1800 0x400>; + clocks = <&rcc 0 6>; + st,bank-name = "GPIOG"; + u-boot,dm-pre-reloc; + }; + + gpioh: gpio@40021c00 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x1c00 0x400>; + clocks = <&rcc 0 7>; + st,bank-name = "GPIOH"; + u-boot,dm-pre-reloc; + }; + + gpioi: gpio@40022000 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x2000 0x400>; + clocks = <&rcc 0 8>; + st,bank-name = "GPIOI"; + u-boot,dm-pre-reloc; + }; + + gpioj: gpio@40022400 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x2400 0x400>; + clocks = <&rcc 0 9>; + st,bank-name = "GPIOJ"; + u-boot,dm-pre-reloc; + }; + + gpiok: gpio@40022800 { + gpio-controller; + #gpio-cells = <2>; + compatible = "st,stm32-gpio"; + reg = <0x2800 0x400>; + clocks = <&rcc 0 10>; + st,bank-name = "GPIOK"; + u-boot,dm-pre-reloc; + }; + }; }; }; diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts new file mode 100644 index 0000000..6591cc8 --- /dev/null +++ b/arch/arm/dts/stm32f769-disco.dts @@ -0,0 +1,255 @@ +/* + * Copyright 2016 - Vikas Manocha <vikas.manocha@st.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "stm32f746.dtsi" +#include <dt-bindings/memory/stm32-sdram.h> + +/ { + model = "STMicroelectronics STM32F769-DISCO board"; + compatible = "st,stm32f769-disco", "st,stm32f7"; + + chosen { + bootargs = "root=/dev/ram rdinit=/linuxrc"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0xC0000000 0x1000000>; + }; + + aliases { + serial0 = &usart1; + spi0 = &qspi; + /* Aliases for gpios so as to use sequence */ + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + }; + + led1 { + compatible = "st,led1"; + led-gpio = <&gpioj 5 0>; + }; + + button1 { + compatible = "st,button1"; + button-gpio = <&gpioa 0 0>; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&pinctrl { + usart1_pins_a: usart1@0 { + pins1 { + pinmux = <STM32F746_PA9_FUNC_USART1_TX>; + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32F746_PA10_FUNC_USART1_RX>; + bias-disable; + }; + }; + + ethernet_mii: mii@0 { + pins { + pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, + <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, + <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, + <STM32F746_PA2_FUNC_ETH_MDIO>, + <STM32F746_PC1_FUNC_ETH_MDC>, + <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, + <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, + <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, + <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>; + slew-rate = <2>; + }; + }; + + qspi_pins: qspi@0 { + pins { + pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>, + <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>, + <STM32F746_PC9_FUNC_QUADSPI_BK1_IO0>, + <STM32F746_PC10_FUNC_QUADSPI_BK1_IO1>, + <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>, + <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>; + slew-rate = <2>; + }; + }; + + fmc_pins: fmc@0 { + pins { + pinmux = <STM32F746_PI10_FUNC_FMC_D31>, + <STM32F746_PI9_FUNC_FMC_D30>, + <STM32F746_PI7_FUNC_FMC_D29>, + <STM32F746_PI6_FUNC_FMC_D28>, + <STM32F746_PI3_FUNC_FMC_D27>, + <STM32F746_PI2_FUNC_FMC_D26>, + <STM32F746_PI1_FUNC_FMC_D25>, + <STM32F746_PI0_FUNC_FMC_D24>, + <STM32F746_PH15_FUNC_FMC_D23>, + <STM32F746_PH14_FUNC_FMC_D22>, + <STM32F746_PH13_FUNC_FMC_D21>, + <STM32F746_PH12_FUNC_FMC_D20>, + <STM32F746_PH11_FUNC_FMC_D19>, + <STM32F746_PH10_FUNC_FMC_D18>, + <STM32F746_PH9_FUNC_FMC_D17>, + <STM32F746_PH8_FUNC_FMC_D16>, + + <STM32F746_PD10_FUNC_FMC_D15>, + <STM32F746_PD9_FUNC_FMC_D14>, + <STM32F746_PD8_FUNC_FMC_D13>, + <STM32F746_PE15_FUNC_FMC_D12>, + <STM32F746_PE14_FUNC_FMC_D11>, + <STM32F746_PE13_FUNC_FMC_D10>, + <STM32F746_PE12_FUNC_FMC_D9>, + <STM32F746_PE11_FUNC_FMC_D8>, + <STM32F746_PE10_FUNC_FMC_D7>, + <STM32F746_PE9_FUNC_FMC_D6>, + <STM32F746_PE8_FUNC_FMC_D5>, + <STM32F746_PE7_FUNC_FMC_D4>, + <STM32F746_PD1_FUNC_FMC_D3>, + <STM32F746_PD0_FUNC_FMC_D2>, + <STM32F746_PD15_FUNC_FMC_D1>, + <STM32F746_PD14_FUNC_FMC_D0>, + + <STM32F746_PI5_FUNC_FMC_NBL3>, + <STM32F746_PI4_FUNC_FMC_NBL2>, + <STM32F746_PE1_FUNC_FMC_NBL1>, + <STM32F746_PE0_FUNC_FMC_NBL0>, + + <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, + <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, + + <STM32F746_PG1_FUNC_FMC_A11>, + <STM32F746_PG0_FUNC_FMC_A10>, + <STM32F746_PF15_FUNC_FMC_A9>, + <STM32F746_PF14_FUNC_FMC_A8>, + <STM32F746_PF13_FUNC_FMC_A7>, + <STM32F746_PF12_FUNC_FMC_A6>, + <STM32F746_PF5_FUNC_FMC_A5>, + <STM32F746_PF4_FUNC_FMC_A4>, + <STM32F746_PF3_FUNC_FMC_A3>, + <STM32F746_PF2_FUNC_FMC_A2>, + <STM32F746_PF1_FUNC_FMC_A1>, + <STM32F746_PF0_FUNC_FMC_A0>, + + <STM32F746_PH3_FUNC_FMC_SDNE0>, + <STM32F746_PH5_FUNC_FMC_SDNWE>, + <STM32F746_PF11_FUNC_FMC_SDNRAS>, + <STM32F746_PG15_FUNC_FMC_SDNCAS>, + <STM32F746_PH2_FUNC_FMC_SDCKE0>, + <STM32F746_PG8_FUNC_FMC_SDCLK>; + slew-rate = <2>; + }; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&fmc { + pinctrl-0 = <&fmc_pins>; + pinctrl-names = "default"; + status = "okay"; + + mr-nbanks = <1>; + /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ + bank1: bank@0 { + st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_32 BANKS_4 + CAS_3 SDCLK_2 RD_BURST_EN + RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2 + TRP_2 TRCD_2>; + /* refcount = (64msec/total_row_sdram)*freq - 20 */ + st,sdram-refcount = < 1542 >; + }; +}; + +&mac { + status = "okay"; + pinctrl-0 = <ðernet_mii>; + phy-mode = "rmii"; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + status = "okay"; + + qflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a13", "spi-flash"; + spi-max-frequency = <108000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + memory-map = <0x90000000 0x1000000>; + reg = <0>; + }; +}; diff --git a/arch/arm/dts/uniphier-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi index 2843adb..5294a90 100644 --- a/arch/arm/dts/uniphier-ld11.dtsi +++ b/arch/arm/dts/uniphier-ld11.dtsi @@ -4,7 +4,43 @@ * Copyright (C) 2016 Socionext Inc. * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * - * SPDX-License-Identifier: GPL-2.0+ X11 + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /memreserve/ 0x80000000 0x00080000; @@ -53,31 +89,31 @@ compatible = "operating-points-v2"; opp-shared; - opp@245000000 { + opp-245000000 { opp-hz = /bits/ 64 <245000000>; clock-latency-ns = <300>; }; - opp@250000000 { + opp-250000000 { opp-hz = /bits/ 64 <250000000>; clock-latency-ns = <300>; }; - opp@490000000 { + opp-490000000 { opp-hz = /bits/ 64 <490000000>; clock-latency-ns = <300>; }; - opp@500000000 { + opp-500000000 { opp-hz = /bits/ 64 <500000000>; clock-latency-ns = <300>; }; - opp@653334000 { + opp-653334000 { opp-hz = /bits/ 64 <653334000>; clock-latency-ns = <300>; }; - opp@666667000 { + opp-666667000 { opp-hz = /bits/ 64 <666667000>; clock-latency-ns = <300>; }; - opp@980000000 { + opp-980000000 { opp-hz = /bits/ 64 <980000000>; clock-latency-ns = <300>; }; @@ -279,6 +315,11 @@ bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + cdns,phy-input-delay-legacy = <4>; + cdns,phy-input-delay-mmc-highspeed = <2>; + cdns,phy-input-delay-mmc-ddr = <3>; + cdns,phy-dll-delay-sdclk = <21>; + cdns,phy-dll-delay-sdclk-hsmmc = <21>; }; usb0: usb@5a800100 { @@ -377,7 +418,7 @@ }; nand: nand@68000000 { - compatible = "socionext,denali-nand-v5b"; + compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index d853526..2906471 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -4,7 +4,43 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * - * SPDX-License-Identifier: GPL-2.0+ X11 + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /memreserve/ 0x80000000 0x00080000; @@ -80,35 +116,35 @@ compatible = "operating-points-v2"; opp-shared; - opp@250000000 { + opp-250000000 { opp-hz = /bits/ 64 <250000000>; clock-latency-ns = <300>; }; - opp@275000000 { + opp-275000000 { opp-hz = /bits/ 64 <275000000>; clock-latency-ns = <300>; }; - opp@500000000 { + opp-500000000 { opp-hz = /bits/ 64 <500000000>; clock-latency-ns = <300>; }; - opp@550000000 { + opp-550000000 { opp-hz = /bits/ 64 <550000000>; clock-latency-ns = <300>; }; - opp@666667000 { + opp-666667000 { opp-hz = /bits/ 64 <666667000>; clock-latency-ns = <300>; }; - opp@733334000 { + opp-733334000 { opp-hz = /bits/ 64 <733334000>; clock-latency-ns = <300>; }; - opp@1000000000 { + opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; clock-latency-ns = <300>; }; - opp@1100000000 { + opp-1100000000 { opp-hz = /bits/ 64 <1100000000>; clock-latency-ns = <300>; }; @@ -118,35 +154,35 @@ compatible = "operating-points-v2"; opp-shared; - opp@250000000 { + opp-250000000 { opp-hz = /bits/ 64 <250000000>; clock-latency-ns = <300>; }; - opp@275000000 { + opp-275000000 { opp-hz = /bits/ 64 <275000000>; clock-latency-ns = <300>; }; - opp@500000000 { + opp-500000000 { opp-hz = /bits/ 64 <500000000>; clock-latency-ns = <300>; }; - opp@550000000 { + opp-550000000 { opp-hz = /bits/ 64 <550000000>; clock-latency-ns = <300>; }; - opp@666667000 { + opp-666667000 { opp-hz = /bits/ 64 <666667000>; clock-latency-ns = <300>; }; - opp@733334000 { + opp-733334000 { opp-hz = /bits/ 64 <733334000>; clock-latency-ns = <300>; }; - opp@1000000000 { + opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; clock-latency-ns = <300>; }; - opp@1100000000 { + opp-1100000000 { opp-hz = /bits/ 64 <1100000000>; clock-latency-ns = <300>; }; @@ -353,6 +389,11 @@ bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + cdns,phy-input-delay-legacy = <4>; + cdns,phy-input-delay-mmc-highspeed = <2>; + cdns,phy-input-delay-mmc-ddr = <3>; + cdns,phy-dll-delay-sdclk = <21>; + cdns,phy-dll-delay-sdclk-hsmmc = <21>; }; sd: sdhc@5a400000 { @@ -429,7 +470,7 @@ }; nand: nand@68000000 { - compatible = "socionext,denali-nand-v5b"; + compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi index de98697..2c8558c 100644 --- a/arch/arm/dts/uniphier-pro5.dtsi +++ b/arch/arm/dts/uniphier-pro5.dtsi @@ -4,7 +4,43 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * - * SPDX-License-Identifier: GPL-2.0+ X11 + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ / { @@ -41,67 +77,67 @@ compatible = "operating-points-v2"; opp-shared; - opp@100000000 { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; clock-latency-ns = <300>; }; - opp@116667000 { + opp-116667000 { opp-hz = /bits/ 64 <116667000>; clock-latency-ns = <300>; }; - opp@150000000 { + opp-150000000 { opp-hz = /bits/ 64 <150000000>; clock-latency-ns = <300>; }; - opp@175000000 { + opp-175000000 { opp-hz = /bits/ 64 <175000000>; clock-latency-ns = <300>; }; - opp@200000000 { + opp-200000000 { opp-hz = /bits/ 64 <200000000>; clock-latency-ns = <300>; }; - opp@233334000 { + opp-233334000 { opp-hz = /bits/ 64 <233334000>; clock-latency-ns = <300>; }; - opp@300000000 { + opp-300000000 { opp-hz = /bits/ 64 <300000000>; clock-latency-ns = <300>; }; - opp@350000000 { + opp-350000000 { opp-hz = /bits/ 64 <350000000>; clock-latency-ns = <300>; }; - opp@400000000 { + opp-400000000 { opp-hz = /bits/ 64 <400000000>; clock-latency-ns = <300>; }; - opp@466667000 { + opp-466667000 { opp-hz = /bits/ 64 <466667000>; clock-latency-ns = <300>; }; - opp@600000000 { + opp-600000000 { opp-hz = /bits/ 64 <600000000>; clock-latency-ns = <300>; }; - opp@700000000 { + opp-700000000 { opp-hz = /bits/ 64 <700000000>; clock-latency-ns = <300>; }; - opp@800000000 { + opp-800000000 { opp-hz = /bits/ 64 <800000000>; clock-latency-ns = <300>; }; - opp@933334000 { + opp-933334000 { opp-hz = /bits/ 64 <933334000>; clock-latency-ns = <300>; }; - opp@1200000000 { + opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; clock-latency-ns = <300>; }; - opp@1400000000 { + opp-1400000000 { opp-hz = /bits/ 64 <1400000000>; clock-latency-ns = <300>; }; @@ -620,7 +656,7 @@ }; nand: nand@68000000 { - compatible = "socionext,denali-nand-v5b"; + compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index b0f6f94..6cd3a93 100644 --- a/arch/arm/dts/uniphier-pxs2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -4,7 +4,43 @@ * Copyright (C) 2015-2016 Socionext Inc. * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * - * SPDX-License-Identifier: GPL-2.0+ X11 + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ / { @@ -61,35 +97,35 @@ compatible = "operating-points-v2"; opp-shared; - opp@100000000 { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; clock-latency-ns = <300>; }; - opp@150000000 { + opp-150000000 { opp-hz = /bits/ 64 <150000000>; clock-latency-ns = <300>; }; - opp@200000000 { + opp-200000000 { opp-hz = /bits/ 64 <200000000>; clock-latency-ns = <300>; }; - opp@300000000 { + opp-300000000 { opp-hz = /bits/ 64 <300000000>; clock-latency-ns = <300>; }; - opp@400000000 { + opp-400000000 { opp-hz = /bits/ 64 <400000000>; clock-latency-ns = <300>; }; - opp@600000000 { + opp-600000000 { opp-hz = /bits/ 64 <600000000>; clock-latency-ns = <300>; }; - opp@800000000 { + opp-800000000 { opp-hz = /bits/ 64 <800000000>; clock-latency-ns = <300>; }; - opp@1200000000 { + opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; clock-latency-ns = <300>; }; @@ -632,7 +668,7 @@ }; nand: nand@68000000 { - compatible = "socionext,denali-nand-v5b"; + compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled"; reg-names = "nand_data", "denali_reg"; reg = <0x68000000 0x20>, <0x68100000 0x1000>; diff --git a/arch/arm/dts/zynq-topic-miami.dts b/arch/arm/dts/zynq-topic-miami.dts index aa05c4d..79a3671 100644 --- a/arch/arm/dts/zynq-topic-miami.dts +++ b/arch/arm/dts/zynq-topic-miami.dts @@ -19,6 +19,7 @@ i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; + usbotg0 = &usb0; }; memory@0 { diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig index 7ee74d5..25cbd12 100644 --- a/arch/arm/imx-common/Kconfig +++ b/arch/arm/imx-common/Kconfig @@ -29,6 +29,29 @@ config SECURE_BOOT bool "Support i.MX HAB features" depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 select FSL_CAAM + imply CMD_DEKBLOB help This option enables the support for secure boot (HAB). See doc/README.mxc_hab for more details. + +config CMD_BMODE + bool "Support the 'bmode' command" + default y + depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 + help + This enables the 'bmode' (bootmode) command for forcing + a boot from specific media. + + This is useful for forcing the ROM's usb downloader to + activate upon a watchdog reset which is nice when iterating + on U-Boot. Using the reset button or running bmode normal + will set it back to normal. This command currently + supports i.MX53 and i.MX6. + +config CMD_DEKBLOB + bool "Support the 'dek_blob' command" + help + This enables the 'dek_blob' command which is used with the + Freescale secure boot mechanism. This command encapsulates and + creates a blob of data. See also CMD_BLOB and doc/README.mxc_hab for + more information. diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index f744ab0..4b5a48e 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -28,7 +28,7 @@ #define BOOT_DEVICE_XIP 0x01 #define BOOT_DEVICE_XIPWAIT 0x02 #define BOOT_DEVICE_NAND 0x03 -#define BOOT_DEVICE_ONENAD 0x04 +#define BOOT_DEVICE_ONENAND 0x04 #define BOOT_DEVICE_MMC2 0x05 /* ROM only supports 2nd instance. */ #define BOOT_DEVICE_MMC1 0x06 #define BOOT_DEVICE_UART 0x43 @@ -47,6 +47,7 @@ #define BOOT_DEVICE_UART 0x41 #define BOOT_DEVICE_USBETH 0x44 #define BOOT_DEVICE_CPGMAC 0x46 +#define BOOT_DEVICE_ONENAND 0xFF /* ROM does not support OneNAND. */ #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 diff --git a/arch/arm/include/asm/arch-aspeed/pinctrl.h b/arch/arm/include/asm/arch-aspeed/pinctrl.h new file mode 100644 index 0000000..365dc21 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/pinctrl.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2017 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_PERIPH_H +#define _ASM_ARCH_PERIPH_H + +/* + * Peripherals supported by the hardware. + * These are used to specify pinctrl settings. + */ + +enum periph_id { + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + PERIPH_ID_UART4, + PERIPH_ID_LPC, + PERIPH_ID_PWM0, + PERIPH_ID_PWM1, + PERIPH_ID_PWM2, + PERIPH_ID_PWM3, + PERIPH_ID_PWM4, + PERIPH_ID_PWM5, + PERIPH_ID_PWM6, + PERIPH_ID_PWM7, + PERIPH_ID_PWM8, + PERIPH_ID_MAC1, + PERIPH_ID_MAC2, + PERIPH_ID_VIDEO, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, + PERIPH_ID_I2C8, + PERIPH_ID_I2C9, + PERIPH_ID_I2C10, + PERIPH_ID_I2C11, + PERIPH_ID_I2C12, + PERIPH_ID_I2C13, + PERIPH_ID_I2C14, + PERIPH_ID_SD1, + PERIPH_ID_SD2, +}; + +#endif /* _ASM_ARCH_SCU_AST2500_H */ diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h index fc0c01a..590aed2 100644 --- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h @@ -8,28 +8,134 @@ #define SCU_UNLOCK_VALUE 0x1688a8a8 -#define SCU_HWSTRAP_VGAMEM_MASK 3 #define SCU_HWSTRAP_VGAMEM_SHIFT 2 +#define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT) +#define SCU_HWSTRAP_MAC1_RGMII (1 << 6) +#define SCU_HWSTRAP_MAC2_RGMII (1 << 7) #define SCU_HWSTRAP_DDR4 (1 << 24) #define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23) #define SCU_MPLL_DENUM_SHIFT 0 #define SCU_MPLL_DENUM_MASK 0x1f #define SCU_MPLL_NUM_SHIFT 5 -#define SCU_MPLL_NUM_MASK 0xff +#define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT) #define SCU_MPLL_POST_SHIFT 13 -#define SCU_MPLL_POST_MASK 0x3f - +#define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT) +#define SCU_PCLK_DIV_SHIFT 23 +#define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT) #define SCU_HPLL_DENUM_SHIFT 0 #define SCU_HPLL_DENUM_MASK 0x1f #define SCU_HPLL_NUM_SHIFT 5 -#define SCU_HPLL_NUM_MASK 0xff +#define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT) #define SCU_HPLL_POST_SHIFT 13 -#define SCU_HPLL_POST_MASK 0x3f +#define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT) + +#define SCU_MACCLK_SHIFT 16 +#define SCU_MACCLK_MASK (7 << SCU_MACCLK_SHIFT) +#define SCU_MISC2_RGMII_HPLL (1 << 23) +#define SCU_MISC2_RGMII_CLKDIV_SHIFT 20 +#define SCU_MISC2_RGMII_CLKDIV_MASK (3 << SCU_MISC2_RGMII_CLKDIV_SHIFT) +#define SCU_MISC2_RMII_MPLL (1 << 19) +#define SCU_MISC2_RMII_CLKDIV_SHIFT 16 +#define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT) #define SCU_MISC2_UARTCLK_SHIFT 24 +#define SCU_MISC_D2PLL_OFF (1 << 4) #define SCU_MISC_UARTCLK_DIV13 (1 << 12) +#define SCU_MISC_GCRT_USB20CLK (1 << 21) + +#define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT 0 +#define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\ + << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT) +#define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT 6 +#define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\ + << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT) +#define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12 +#define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT) +#define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18 +#define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT) +#define SCU_MICDS_MAC1RMII_TXFALL (1 << 24) +#define SCU_MICDS_MAC2RMII_TXFALL (1 << 25) +#define SCU_MICDS_RMII1_RCLKEN (1 << 29) +#define SCU_MICDS_RMII2_RCLKEN (1 << 30) +#define SCU_MICDS_RGMIIPLL (1 << 31) + +/* + * SYSRESET is actually more like a Power register, + * except that corresponding bit set to 1 means that + * the peripheral is off. + */ +#define SCU_SYSRESET_XDMA (1 << 25) +#define SCU_SYSRESET_MCTP (1 << 24) +#define SCU_SYSRESET_ADC (1 << 23) +#define SCU_SYSRESET_JTAG (1 << 22) +#define SCU_SYSRESET_MIC (1 << 18) +#define SCU_SYSRESET_SDIO (1 << 16) +#define SCU_SYSRESET_USB11HOST (1 << 15) +#define SCU_SYSRESET_USBHUB (1 << 14) +#define SCU_SYSRESET_CRT (1 << 13) +#define SCU_SYSRESET_MAC2 (1 << 12) +#define SCU_SYSRESET_MAC1 (1 << 11) +#define SCU_SYSRESET_PECI (1 << 10) +#define SCU_SYSRESET_PWM (1 << 9) +#define SCU_SYSRESET_PCI_VGA (1 << 8) +#define SCU_SYSRESET_2D (1 << 7) +#define SCU_SYSRESET_VIDEO (1 << 6) +#define SCU_SYSRESET_LPC (1 << 5) +#define SCU_SYSRESET_HAC (1 << 4) +#define SCU_SYSRESET_USBHID (1 << 3) +#define SCU_SYSRESET_I2C (1 << 2) +#define SCU_SYSRESET_AHB (1 << 1) +#define SCU_SYSRESET_SDRAM_WDT (1 << 0) + +/* Bits 16-27 in the register control pin functions for I2C devices 3-14 */ +#define SCU_PINMUX_CTRL5_I2C (1 << 16) + +/* + * The values are grouped by function, not by register. + * They are actually scattered across multiple loosely related registers. + */ +#define SCU_PIN_FUN_MAC1_MDC (1 << 30) +#define SCU_PIN_FUN_MAC1_MDIO (1 << 31) +#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0) +#define SCU_PIN_FUN_MAC2_MDIO (1 << 2) +#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1) +#define SCU_PIN_FUN_SCL1 (1 << 12) +#define SCU_PIN_FUN_SCL2 (1 << 14) +#define SCU_PIN_FUN_SDA1 (1 << 13) +#define SCU_PIN_FUN_SDA2 (1 << 15) + +#define SCU_CLKSTOP_MAC1 (1 << 20) +#define SCU_CLKSTOP_MAC2 (1 << 21) + +#define SCU_D2PLL_EXT1_OFF (1 << 0) +#define SCU_D2PLL_EXT1_BYPASS (1 << 1) +#define SCU_D2PLL_EXT1_RESET (1 << 2) +#define SCU_D2PLL_EXT1_MODE_SHIFT 3 +#define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT) +#define SCU_D2PLL_EXT1_PARAM_SHIFT 5 +#define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT) + +#define SCU_D2PLL_NUM_SHIFT 0 +#define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT) +#define SCU_D2PLL_DENUM_SHIFT 8 +#define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT) +#define SCU_D2PLL_POST_SHIFT 13 +#define SCU_D2PLL_POST_MASK (0x3f << SCU_D2PLL_POST_SHIFT) +#define SCU_D2PLL_ODIV_SHIFT 19 +#define SCU_D2PLL_ODIV_MASK (7 << SCU_D2PLL_ODIV_SHIFT) +#define SCU_D2PLL_SIC_SHIFT 22 +#define SCU_D2PLL_SIC_MASK (0x1f << SCU_D2PLL_SIC_SHIFT) +#define SCU_D2PLL_SIP_SHIFT 27 +#define SCU_D2PLL_SIP_MASK (0x1f << SCU_D2PLL_SIP_SHIFT) + +#define SCU_CLKDUTY_DCLK_SHIFT 0 +#define SCU_CLKDUTY_DCLK_MASK (0x3f << SCU_CLKDUTY_DCLK_SHIFT) +#define SCU_CLKDUTY_RGMII1TXCK_SHIFT 8 +#define SCU_CLKDUTY_RGMII1TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII1TXCK_SHIFT) +#define SCU_CLKDUTY_RGMII2TXCK_SHIFT 16 +#define SCU_CLKDUTY_RGMII2TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT) #ifndef __ASSEMBLY__ @@ -120,6 +226,20 @@ int ast_get_clk(struct udevice **devp); */ void *ast_get_scu(void); +/** + * ast_scu_unlock() - unlock protected registers + * + * @scu, pointer to ast2500_scu + */ +void ast_scu_unlock(struct ast2500_scu *scu); + +/** + * ast_scu_lock() - lock protected registers + * + * @scu, pointer to ast2500_scu + */ +void ast_scu_lock(struct ast2500_scu *scu); + #endif /* __ASSEMBLY__ */ #endif /* _ASM_ARCH_SCU_AST2500_H */ diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h b/arch/arm/include/asm/arch-aspeed/wdt.h index b292a0e..db8ecbc 100644 --- a/arch/arm/include/asm/arch-aspeed/wdt.h +++ b/arch/arm/include/asm/arch-aspeed/wdt.h @@ -67,33 +67,39 @@ struct ast_wdt { u32 timeout_status; u32 clr_timeout_status; u32 reset_width; -#ifdef CONFIG_ASPEED_AST2500 + /* On pre-ast2500 SoCs this register is reserved. */ u32 reset_mask; -#else - u32 reserved0; -#endif }; -void wdt_stop(struct ast_wdt *wdt); -void wdt_start(struct ast_wdt *wdt, u32 timeout); - /** - * Reset peripherals specified by mask + * Given flags parameter passed to wdt_reset or wdt_start uclass functions, + * gets Reset Mode value from it. * - * Note, that this is only supported by ast2500 SoC + * @flags: flags parameter passed into wdt_reset or wdt_start + * @return Reset Mode value + */ +u32 ast_reset_mode_from_flags(ulong flags); + +/** + * Given flags parameter passed to wdt_reset or wdt_start uclass functions, + * gets Reset Mask value from it. Reset Mask is only supported on ast2500 * - * @wdt: watchdog to use for this reset - * @mask: reset mask. + * @flags: flags parameter passed into wdt_reset or wdt_start + * @return Reset Mask value */ -int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask); +u32 ast_reset_mask_from_flags(ulong flags); /** - * ast_get_wdt() - get a pointer to watchdog registers + * Given Reset Mask and Reset Mode values, converts them to flags, + * suitable for passing into wdt_start or wdt_reset uclass functions. + * + * On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they + * can both be packed into single 32 bits wide value. * - * @wdt_number: 0-based WDT peripheral number - * @return pointer to registers or -ve error on error + * @reset_mode: Reset Mode + * @reset_mask: Reset Mask */ -struct ast_wdt *ast_get_wdt(u8 wdt_number); +ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask); #endif /* __ASSEMBLY__ */ #endif /* _ASM_ARCH_WDT_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index b5b08aa..93e6597 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -18,7 +18,7 @@ */ #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 #define CONFIG_SYS_PAGE_SIZE 0x10000 @@ -132,7 +132,7 @@ #define CONFIG_SYS_FSL_PEX_LUT_BE /* SoC related */ -#ifdef CONFIG_LS1043A +#ifdef CONFIG_ARCH_LS1043A #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 7 @@ -185,7 +185,12 @@ #elif defined(CONFIG_ARCH_LS1012A) #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 - +#define CONFIG_SYS_FSL_SFP_VER_3_2 +#define CONFIG_SYS_FSL_SEC_MON_BE +#define CONFIG_SYS_FSL_SFP_BE +#define CONFIG_SYS_FSL_SRK_LE +#define CONFIG_KEY_REVOCATION +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE @@ -199,7 +204,7 @@ #define CONFIG_SYS_FSL_IFC_BE #define CONFIG_SYS_FSL_SFP_VER_3_2 -#define CONFIG_SYS_FSL_SNVS_LE +#define CONFIG_SYS_FSL_SEC_MON_BE #define CONFIG_SYS_FSL_SFP_BE #define CONFIG_SYS_FSL_SRK_LE #define CONFIG_KEY_REVOCATION diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index bcf3e38..95c3e2f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -249,7 +249,7 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 70181c5..a8f9a50 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -9,7 +9,7 @@ #include <config.h> -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A enum srds_prtcl { /* * Nobody will check whether the device 'NONE' has been configured, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index d0832b5..fd3f851 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -31,7 +31,11 @@ extern u64 __spin_table[]; extern u64 __real_cntfrq; extern u64 *secondary_boot_code; extern size_t __secondary_boot_code_size; +#ifdef CONFIG_MP int fsl_layerscape_wake_seconday_cores(void); +#else +static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; } +#endif void *get_spin_tbl_addr(void); phys_addr_t determine_mp_bootpg(void); void secondary_boot_func(void); diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 2f7233f..5c4da0f 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -108,7 +108,7 @@ #define DCU_LAYER_MAX_NUM 16 -#ifdef CONFIG_LS102XA +#ifdef CONFIG_ARCH_LS1021A #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else diff --git a/arch/arm/include/asm/arch-omap3/i2c.h b/arch/arm/include/asm/arch-omap3/i2c.h index b370290..6b3a3da 100644 --- a/arch/arm/include/asm/arch-omap3/i2c.h +++ b/arch/arm/include/asm/arch-omap3/i2c.h @@ -17,7 +17,7 @@ struct i2c { unsigned short res2; unsigned short stat; /* 0x08 */ unsigned short res3; - unsigned short iv; /* 0x0C */ + unsigned short we; /* 0x0C */ unsigned short res4; unsigned short syss; /* 0x10 */ unsigned short res4a; @@ -43,6 +43,18 @@ struct i2c { unsigned short res14; unsigned short systest; /* 0x3c */ unsigned short res15; + unsigned short bufstat; /* 0x40 */ + unsigned short res16; + unsigned short oa1; /* 0x44 */ + unsigned short res17; + unsigned short oa2; /* 0x48 */ + unsigned short res18; + unsigned short oa3; /* 0x4c */ + unsigned short res19; + unsigned short actoa; /* 0x50 */ + unsigned short res20; + unsigned short sblock; /* 0x54 */ + unsigned short res21; }; #endif /* _OMAP3_I2C_H_ */ diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h index 79fb1a0..92eb878 100644 --- a/arch/arm/include/asm/arch-rockchip/bootrom.h +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -13,10 +13,15 @@ */ extern u32 SAVE_SP_ADDR; -/* +/** * Hand control back to the bootrom to load another * boot stage. */ -extern void back_to_bootrom(void); +void back_to_bootrom(void); + +/** + * Assembler component for the above (do not call this directly) + */ +void _back_to_bootrom_s(void); #endif diff --git a/arch/arm/include/asm/arch-stm32f7/gpio.h b/arch/arm/include/asm/arch-stm32f7/gpio.h index 2942cd9..56e469e 100644 --- a/arch/arm/include/asm/arch-stm32f7/gpio.h +++ b/arch/arm/include/asm/arch-stm32f7/gpio.h @@ -7,6 +7,7 @@ #ifndef _STM32_GPIO_H_ #define _STM32_GPIO_H_ +#include <asm/gpio.h> enum stm32_gpio_port { STM32_GPIO_PORT_A = 0, @@ -96,6 +97,22 @@ struct stm32_gpio_ctl { enum stm32_gpio_af af; }; +struct stm32_gpio_regs { + u32 moder; /* GPIO port mode */ + u32 otyper; /* GPIO port output type */ + u32 ospeedr; /* GPIO port output speed */ + u32 pupdr; /* GPIO port pull-up/pull-down */ + u32 idr; /* GPIO port input data */ + u32 odr; /* GPIO port output data */ + u32 bsrr; /* GPIO port bit set/reset */ + u32 lckr; /* GPIO port configuration lock */ + u32 afr[2]; /* GPIO alternate function */ +}; + +struct stm32_gpio_priv { + struct stm32_gpio_regs *regs; +}; + static inline unsigned stm32_gpio_to_port(unsigned gpio) { return gpio / 16; @@ -106,8 +123,4 @@ static inline unsigned stm32_gpio_to_pin(unsigned gpio) return gpio % 16; } -int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc, - const struct stm32_gpio_ctl *gpio_ctl); -int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state); - #endif /* _STM32_GPIO_H_ */ diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h index bcdb1b0..bc1d97d 100644 --- a/arch/arm/include/asm/armv8/sec_firmware.h +++ b/arch/arm/include/asm/armv8/sec_firmware.h @@ -7,12 +7,19 @@ #ifndef __SEC_FIRMWARE_H_ #define __SEC_FIRMWARE_H_ +#define PSCI_INVALID_VER 0xffffffff + int sec_firmware_init(const void *, u32 *, u32 *); int _sec_firmware_entry(const void *, u32 *, u32 *); bool sec_firmware_is_valid(const void *); #ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI unsigned int sec_firmware_support_psci_version(void); unsigned int _sec_firmware_support_psci_version(void); +#else +static inline unsigned int sec_firmware_support_psci_version(void) +{ + return PSCI_INVALID_VER; +} #endif #endif /* __SEC_FIRMWARE_H_ */ diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index 1ad221a..5674d37 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -14,7 +14,7 @@ #define CONFIG_STATIC_RELA #endif -#if defined(CONFIG_LS102XA) || \ +#if defined(CONFIG_ARCH_LS1021A) || \ defined(CONFIG_CPU_PXA27X) || \ defined(CONFIG_CPU_MONAHANS) || \ defined(CONFIG_CPU_PXA25X) || \ diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index d98a1e8..b0ca4bc 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -27,10 +27,10 @@ #define CONFIG_SPL_UBOOT_KEY_HASH NULL #endif /* ifdef CONFIG_SPL_BUILD */ +#define CONFIG_KEY_REVOCATION + #ifndef CONFIG_SPL_BUILD -#define CONFIG_CMD_BLOB #define CONFIG_CMD_HASH -#define CONFIG_KEY_REVOCATION #ifndef CONFIG_SYS_RAMBOOT /* The key used for verification of next level images * is picked up from an Extension Table which has @@ -46,14 +46,15 @@ #endif -#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) -/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit - * Similiarly for LS2080 +#if defined(CONFIG_FSL_LAYERSCAPE) +/* + * For fsl layerscape based platforms, ESBC image Address in Header + * is 64 bit. */ #define CONFIG_ESBC_ADDR_64BIT #endif -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xa0000000;" \ "setenv initrd_high 0xcfffffff;" \ @@ -68,7 +69,7 @@ /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD)*/ #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \ - defined(CONFIG_SD_BOOT) + defined(CONFIG_SD_BOOT) || defined(CONFIG_NAND_BOOT) #define CONFIG_BOOTSCRIPT_COPY_RAM #endif /* The address needs to be modified according to NOR, NAND, SD and @@ -86,16 +87,37 @@ /* For SD boot address and size are assigned in terms of sector * offset and no. of sectors respectively. */ -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900 +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) +#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000920 +#else +#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900 +#endif #define CONFIG_BS_ADDR_DEVICE 0x00000940 #define CONFIG_BS_HDR_SIZE 0x00000010 #define CONFIG_BS_SIZE 0x00000008 +#elif defined(CONFIG_NAND_BOOT) +#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000 +#define CONFIG_BS_ADDR_DEVICE 0x00802000 +#define CONFIG_BS_HDR_SIZE 0x00002000 +#define CONFIG_BS_SIZE 0x00001000 +#elif defined(CONFIG_QSPI_BOOT) +#ifdef CONFIG_ARCH_LS1046A +#define CONFIG_BS_HDR_ADDR_DEVICE 0x40780000 +#define CONFIG_BS_ADDR_DEVICE 0x40800000 +#elif defined(CONFIG_ARCH_LS1012A) +#define CONFIG_BS_HDR_ADDR_DEVICE 0x400c0000 +#define CONFIG_BS_ADDR_DEVICE 0x40060000 #else +#error "Platform not supported" +#endif +#define CONFIG_BS_HDR_SIZE 0x00002000 +#define CONFIG_BS_SIZE 0x00001000 +#else /* Default NOR Boot */ #define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000 #define CONFIG_BS_ADDR_DEVICE 0x60060000 #define CONFIG_BS_HDR_SIZE 0x00002000 #define CONFIG_BS_SIZE 0x00001000 -#endif /* #ifdef CONFIG_SD_BOOT */ +#endif #define CONFIG_BS_HDR_ADDR_RAM 0x81000000 #define CONFIG_BS_ADDR_RAM 0x81020000 #endif @@ -109,23 +131,13 @@ #endif #ifdef CONFIG_FSL_LS_PPA -#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP -#ifdef CONFIG_LS1043A -#define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x600c0000 -#elif defined(CONFIG_FSL_LSCH3) -#define CONFIG_SYS_LS_PPA_ESBC_ADDR 0x580c40000 -#endif -#else -#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined" -#endif /* ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP */ - /* Define the key hash here if SRK used for signing PPA image is * different from SRK hash put in SFP used for U-Boot. * Example - * #define CONFIG_PPA_KEY_HASH \ + * #define PPA_KEY_HASH \ * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" */ -#define CONFIG_PPA_KEY_HASH NULL +#define PPA_KEY_HASH NULL #endif /* ifdef CONFIG_FSL_LS_PPA */ #include <config_fsl_chain_trust.h> diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index dfcbcce..1aab629 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -67,7 +67,7 @@ struct arch_global_data { phys_addr_t resv_ram; #endif -#ifdef CONFIG_ARCH_OMAP2 +#ifdef CONFIG_ARCH_OMAP2PLUS u32 omap_boot_device; u32 omap_boot_mode; u8 omap_ch_flags; diff --git a/arch/arm/include/asm/opcodes-sec.h b/arch/arm/include/asm/opcodes-sec.h new file mode 100644 index 0000000..16dee8f --- /dev/null +++ b/arch/arm/include/asm/opcodes-sec.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2012 ARM Limited + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ARM_OPCODES_SEC_H +#define __ASM_ARM_OPCODES_SEC_H + +#include <asm/opcodes.h> + +#define __SMC(imm4) __inst_arm_thumb32( \ + 0xE1600070 | (((imm4) & 0xF) << 0), \ + 0xF7F08000 | (((imm4) & 0xF) << 16) \ +) + +#endif /* __ASM_ARM_OPCODES_SEC_H */ diff --git a/arch/arm/include/asm/opcodes-virt.h b/arch/arm/include/asm/opcodes-virt.h new file mode 100644 index 0000000..9272997 --- /dev/null +++ b/arch/arm/include/asm/opcodes-virt.h @@ -0,0 +1,27 @@ +/* + * opcodes-virt.h: Opcode definitions for the ARM virtualization extensions + * Copyright (C) 2012 Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_ARM_OPCODES_VIRT_H +#define __ASM_ARM_OPCODES_VIRT_H + +#include <asm/opcodes.h> + +#define __HVC(imm16) __inst_arm_thumb32( \ + 0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F), \ + 0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF) \ +) + +#define __ERET __inst_arm_thumb32( \ + 0xE160006E, \ + 0xF3DE8F00 \ +) + +#define __MSR_ELR_HYP(regnum) __inst_arm_thumb32( \ + 0xE12EF300 | regnum, \ + 0xF3808E30 | (regnum << 16) \ +) + +#endif /* ! __ASM_ARM_OPCODES_VIRT_H */ diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h new file mode 100644 index 0000000..199f0ba --- /dev/null +++ b/arch/arm/include/asm/opcodes.h @@ -0,0 +1,229 @@ +/* + * arch/arm/include/asm/opcodes.h + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ARM_OPCODES_H +#define __ASM_ARM_OPCODES_H + +#ifndef __ASSEMBLY__ +#include <linux/linkage.h> +extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr); +#endif + +#define ARM_OPCODE_CONDTEST_FAIL 0 +#define ARM_OPCODE_CONDTEST_PASS 1 +#define ARM_OPCODE_CONDTEST_UNCOND 2 + + +/* + * Assembler opcode byteswap helpers. + * These are only intended for use by this header: don't use them directly, + * because they will be suboptimal in most cases. + */ +#define ___asm_opcode_swab32(x) ( \ + (((x) << 24) & 0xFF000000) \ + | (((x) << 8) & 0x00FF0000) \ + | (((x) >> 8) & 0x0000FF00) \ + | (((x) >> 24) & 0x000000FF) \ +) +#define ___asm_opcode_swab16(x) ( \ + (((x) << 8) & 0xFF00) \ + | (((x) >> 8) & 0x00FF) \ +) +#define ___asm_opcode_swahb32(x) ( \ + (((x) << 8) & 0xFF00FF00) \ + | (((x) >> 8) & 0x00FF00FF) \ +) +#define ___asm_opcode_swahw32(x) ( \ + (((x) << 16) & 0xFFFF0000) \ + | (((x) >> 16) & 0x0000FFFF) \ +) +#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF) +#define ___asm_opcode_identity16(x) ((x) & 0xFFFF) + + +/* + * Opcode byteswap helpers + * + * These macros help with converting instructions between a canonical integer + * format and in-memory representation, in an endianness-agnostic manner. + * + * __mem_to_opcode_*() convert from in-memory representation to canonical form. + * __opcode_to_mem_*() convert from canonical form to in-memory representation. + * + * + * Canonical instruction representation: + * + * ARM: 0xKKLLMMNN + * Thumb 16-bit: 0x0000KKLL, where KK < 0xE8 + * Thumb 32-bit: 0xKKLLMMNN, where KK >= 0xE8 + * + * There is no way to distinguish an ARM instruction in canonical representation + * from a Thumb instruction (just as these cannot be distinguished in memory). + * Where this distinction is important, it needs to be tracked separately. + * + * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not + * represent any valid Thumb-2 instruction. For this range, + * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false. + * + * The ___asm variants are intended only for use by this header, in situations + * involving inline assembler. For .S files, the normal __opcode_*() macros + * should do the right thing. + */ +#ifdef __ASSEMBLY__ + +#define ___opcode_swab32(x) ___asm_opcode_swab32(x) +#define ___opcode_swab16(x) ___asm_opcode_swab16(x) +#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x) +#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x) +#define ___opcode_identity32(x) ___asm_opcode_identity32(x) +#define ___opcode_identity16(x) ___asm_opcode_identity16(x) + +#else /* ! __ASSEMBLY__ */ + +#include <linux/types.h> +#include <linux/swab.h> + +#define ___opcode_swab32(x) swab32(x) +#define ___opcode_swab16(x) swab16(x) +#define ___opcode_swahb32(x) swahb32(x) +#define ___opcode_swahw32(x) swahw32(x) +#define ___opcode_identity32(x) ((u32)(x)) +#define ___opcode_identity16(x) ((u16)(x)) + +#endif /* ! __ASSEMBLY__ */ + + +#ifdef CONFIG_CPU_ENDIAN_BE8 + +#define __opcode_to_mem_arm(x) ___opcode_swab32(x) +#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x) +#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x) +#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x) +#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x) +#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x) + +#else /* ! CONFIG_CPU_ENDIAN_BE8 */ + +#define __opcode_to_mem_arm(x) ___opcode_identity32(x) +#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x) +#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x) +#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x) +#ifndef CONFIG_CPU_ENDIAN_BE32 +/* + * On BE32 systems, using 32-bit accesses to store Thumb instructions will not + * work in all cases, due to alignment constraints. For now, a correct + * version is not provided for BE32. + */ +#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x) +#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x) +#endif + +#endif /* ! CONFIG_CPU_ENDIAN_BE8 */ + +#define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x) +#define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x) +#ifndef CONFIG_CPU_ENDIAN_BE32 +#define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x) +#endif + +/* Operations specific to Thumb opcodes */ + +/* Instruction size checks: */ +#define __opcode_is_thumb32(x) ( \ + ((x) & 0xF8000000) == 0xE8000000 \ + || ((x) & 0xF0000000) == 0xF0000000 \ +) +#define __opcode_is_thumb16(x) ( \ + ((x) & 0xFFFF0000) == 0 \ + && !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000) \ +) + +/* Operations to construct or split 32-bit Thumb instructions: */ +#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16)) +#define __opcode_thumb32_second(x) (___opcode_identity16(x)) +#define __opcode_thumb32_compose(first, second) ( \ + (___opcode_identity32(___opcode_identity16(first)) << 16) \ + | ___opcode_identity32(___opcode_identity16(second)) \ +) +#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16)) +#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x)) +#define ___asm_opcode_thumb32_compose(first, second) ( \ + (___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \ + | ___asm_opcode_identity32(___asm_opcode_identity16(second)) \ +) + +/* + * Opcode injection helpers + * + * In rare cases it is necessary to assemble an opcode which the + * assembler does not support directly, or which would normally be + * rejected because of the CFLAGS or AFLAGS used to build the affected + * file. + * + * Before using these macros, consider carefully whether it is feasible + * instead to change the build flags for your file, or whether it really + * makes sense to support old assembler versions when building that + * particular kernel feature. + * + * The macros defined here should only be used where there is no viable + * alternative. + * + * + * __inst_arm(x): emit the specified ARM opcode + * __inst_thumb16(x): emit the specified 16-bit Thumb opcode + * __inst_thumb32(x): emit the specified 32-bit Thumb opcode + * + * __inst_arm_thumb16(arm, thumb): emit either the specified arm or + * 16-bit Thumb opcode, depending on whether an ARM or Thumb-2 + * kernel is being built + * + * __inst_arm_thumb32(arm, thumb): emit either the specified arm or + * 32-bit Thumb opcode, depending on whether an ARM or Thumb-2 + * kernel is being built + * + * + * Note that using these macros directly is poor practice. Instead, you + * should use them to define human-readable wrapper macros to encode the + * instructions that you care about. In code which might run on ARMv7 or + * above, you can usually use the __inst_arm_thumb{16,32} macros to + * specify the ARM and Thumb alternatives at the same time. This ensures + * that the correct opcode gets emitted depending on the instruction set + * used for the kernel build. + * + * Look at opcodes-virt.h for an example of how to use these macros. + */ +#include <linux/stringify.h> + +#define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x)) +#define __inst_thumb32(x) ___inst_thumb32( \ + ___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_first(x)), \ + ___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_second(x)) \ +) +#define __inst_thumb16(x) ___inst_thumb16(___asm_opcode_to_mem_thumb16(x)) + +#ifdef CONFIG_THUMB2_KERNEL +#define __inst_arm_thumb16(arm_opcode, thumb_opcode) \ + __inst_thumb16(thumb_opcode) +#define __inst_arm_thumb32(arm_opcode, thumb_opcode) \ + __inst_thumb32(thumb_opcode) +#else +#define __inst_arm_thumb16(arm_opcode, thumb_opcode) __inst_arm(arm_opcode) +#define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode) +#endif + +/* Helpers for the helpers. Don't use these directly. */ +#ifdef __ASSEMBLY__ +#define ___inst_arm(x) .long x +#define ___inst_thumb16(x) .short x +#define ___inst_thumb32(first, second) .short first, second +#else +#define ___inst_arm(x) ".long " __stringify(x) "\n\t" +#define ___inst_thumb16(x) ".short " __stringify(x) "\n\t" +#define ___inst_thumb32(first, second) \ + ".short " __stringify(first) ", " __stringify(second) "\n\t" +#endif + +#endif /* __ASM_ARM_OPCODES_H */ diff --git a/arch/arm/include/asm/ti-common/sys_proto.h b/arch/arm/include/asm/ti-common/sys_proto.h index 60d1160..a047501 100644 --- a/arch/arm/include/asm/ti-common/sys_proto.h +++ b/arch/arm/include/asm/ti-common/sys_proto.h @@ -9,7 +9,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_ARCH_OMAP2 +#ifdef CONFIG_ARCH_OMAP2PLUS #define TI_ARMV7_DRAM_ADDR_SPACE_START 0x80000000 #define TI_ARMV7_DRAM_ADDR_SPACE_END 0xFFFFFFFF diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c index e5bcaea..d620dc0 100644 --- a/arch/arm/lib/asm-offsets.c +++ b/arch/arm/lib/asm-offsets.c @@ -14,6 +14,7 @@ #include <common.h> #include <linux/kbuild.h> +#include <linux/arm-smccc.h> #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \ || defined(CONFIG_MX51) || defined(CONFIG_MX53) @@ -198,5 +199,12 @@ int main(void) DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn)); #endif +#ifdef CONFIG_ARM_SMCCC + DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0)); + DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2)); + DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id)); + DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state)); +#endif + return 0; } diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 426bee6..4dbe6a5 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -356,7 +356,10 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) int fake = (flag & BOOTM_STATE_OS_FAKE_GO); kernel_entry = (void (*)(int, int, uint))images->ep; - +#ifdef CONFIG_CPU_V7M + ulong addr = (ulong)kernel_entry | 1; + kernel_entry = (void *)addr; +#endif s = getenv("machid"); if (s) { if (strict_strtoul(s, 16, &machid) < 0) { diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index e606d47..8ff2c50 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -44,22 +44,21 @@ void __weak board_init_f(ulong dummy) /* * This function jumps to an image with argument. Normally an FDT or ATAGS * image. - * arg: Pointer to paramter image in RAM */ #ifdef CONFIG_SPL_OS_BOOT -void __noreturn jump_to_image_linux(struct spl_image_info *spl_image, void *arg) +void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) { unsigned long machid = 0xffffffff; #ifdef CONFIG_MACH_TYPE machid = CONFIG_MACH_TYPE; #endif - debug("Entering kernel arg pointer: 0x%p\n", arg); + debug("Entering kernel arg pointer: 0x%p\n", spl_image->arg); typedef void (*image_entry_arg_t)(int, int, void *) __attribute__ ((noreturn)); image_entry_arg_t image_entry = (image_entry_arg_t)(uintptr_t) spl_image->entry_point; cleanup_before_linux(); - image_entry(0, machid, arg); + image_entry(0, machid, spl_image->arg); } #endif diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index c5b90bd..4f021ba 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -11,19 +11,13 @@ config SYS_TEXT_BASE config ASPEED_AST2500 bool "Support Aspeed AST2500 SoC" + depends on DM_RESET select CPU_ARM1176 help The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU. It is used as Board Management Controller on many server boards, which is enabled by support of LPC and eSPI peripherals. -config WDT_NUM - int "Number of Watchdog Timers" - default 3 if ASPEED_AST2500 - help - The number of Watchdot Timers on a SoC. - AST2500 has three WDTsk earlier versions have two or fewer. - source "arch/arm/mach-aspeed/ast2500/Kconfig" endif diff --git a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c index 079909f..30cfac1 100644 --- a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c +++ b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c @@ -6,6 +6,7 @@ #include <common.h> #include <dm.h> +#include <asm/io.h> #include <asm/arch/scu_ast2500.h> int ast_get_clk(struct udevice **devp) @@ -28,3 +29,17 @@ void *ast_get_scu(void) return priv->scu; } + +void ast_scu_unlock(struct ast2500_scu *scu) +{ + writel(SCU_UNLOCK_VALUE, &scu->protection_key); + while (!readl(&scu->protection_key)) + ; +} + +void ast_scu_lock(struct ast2500_scu *scu) +{ + writel(~SCU_UNLOCK_VALUE, &scu->protection_key); + while (readl(&scu->protection_key)) + ; +} diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c index cb6e03f..6383f72 100644 --- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c +++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c @@ -12,6 +12,7 @@ #include <errno.h> #include <ram.h> #include <regmap.h> +#include <reset.h> #include <asm/io.h> #include <asm/arch/scu_ast2500.h> #include <asm/arch/sdram_ast2500.h> @@ -182,9 +183,8 @@ static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info) static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info) { size_t vga_mem_size_base = 8 * 1024 * 1024; - u32 vga_hwconf = (readl(&info->scu->hwstrap) - >> SCU_HWSTRAP_VGAMEM_SHIFT) - & SCU_HWSTRAP_VGAMEM_MASK; + u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK) + >> SCU_HWSTRAP_VGAMEM_SHIFT; return vga_mem_size_base << vga_hwconf; } @@ -328,6 +328,7 @@ static void ast2500_sdrammc_lock(struct dram_info *info) static int ast2500_sdrammc_probe(struct udevice *dev) { + struct reset_ctl reset_ctl; struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); struct ast2500_sdrammc_regs *regs = priv->regs; int i; @@ -345,9 +346,15 @@ static int ast2500_sdrammc_probe(struct udevice *dev) } clk_set_rate(&priv->ddr_clk, priv->clock_rate); - ret = ast_wdt_reset_masked(ast_get_wdt(0), WDT_RESET_SDRAM); + ret = reset_get_by_index(dev, 0, &reset_ctl); if (ret) { - debug("%s(): SDRAM reset failed\n", __func__); + debug("%s(): Failed to get reset signal\n", __func__); + return ret; + } + + ret = reset_assert(&reset_ctl); + if (ret) { + debug("%s(): SDRAM reset failed: %u\n", __func__, ret); return ret; } diff --git a/arch/arm/mach-aspeed/ast_wdt.c b/arch/arm/mach-aspeed/ast_wdt.c index 22481ab..1a858b1 100644 --- a/arch/arm/mach-aspeed/ast_wdt.c +++ b/arch/arm/mach-aspeed/ast_wdt.c @@ -9,51 +9,22 @@ #include <asm/arch/wdt.h> #include <linux/err.h> -void wdt_stop(struct ast_wdt *wdt) +u32 ast_reset_mode_from_flags(ulong flags) { - clrbits_le32(&wdt->ctrl, WDT_CTRL_EN); + return flags & WDT_CTRL_RESET_MASK; } -void wdt_start(struct ast_wdt *wdt, u32 timeout) +u32 ast_reset_mask_from_flags(ulong flags) { - writel(timeout, &wdt->counter_reload_val); - writel(WDT_COUNTER_RESTART_VAL, &wdt->counter_restart); - /* - * Setting CLK1MHZ bit is just for compatibility with ast2400 part. - * On ast2500 watchdog timer clock is fixed at 1MHz and the bit is - * read-only - */ - setbits_le32(&wdt->ctrl, - WDT_CTRL_EN | WDT_CTRL_RESET | WDT_CTRL_CLK1MHZ); + return flags >> 2; } -struct ast_wdt *ast_get_wdt(u8 wdt_number) +ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask) { - if (wdt_number > CONFIG_WDT_NUM - 1) - return ERR_PTR(-EINVAL); + ulong ret = reset_mode & WDT_CTRL_RESET_MASK; - return (struct ast_wdt *)(WDT_BASE + - sizeof(struct ast_wdt) * wdt_number); -} - -int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask) -{ -#ifdef CONFIG_ASPEED_AST2500 - if (!mask) - return -EINVAL; - - writel(mask, &wdt->reset_mask); - clrbits_le32(&wdt->ctrl, - WDT_CTRL_RESET_MASK << WDT_CTRL_RESET_MODE_SHIFT); - wdt_start(wdt, 1); - - /* Wait for WDT to reset */ - while (readl(&wdt->ctrl) & WDT_CTRL_EN) - ; - wdt_stop(wdt); + if (ret == WDT_CTRL_RESET_SOC) + ret |= (reset_mask << 2); - return 0; -#else - return -EINVAL; -#endif + return ret; } diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index 68f8980..645bd96 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -284,7 +284,7 @@ static unsigned long pll_freq_get(int pll) u32 tmp, reg; if (pll == MAIN_PLL) { - ret = external_clk[sys_clk]; + ret = get_external_clk(sys_clk); if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) { /* PLL mode */ tmp = __raw_readl(KS2_MAINPLLCTL0); @@ -302,23 +302,23 @@ static unsigned long pll_freq_get(int pll) } else { switch (pll) { case PASS_PLL: - ret = external_clk[pa_clk]; + ret = get_external_clk(pa_clk); reg = KS2_PASSPLLCTL0; break; case TETRIS_PLL: - ret = external_clk[tetris_clk]; + ret = get_external_clk(tetris_clk); reg = KS2_ARMPLLCTL0; break; case DDR3A_PLL: - ret = external_clk[ddr3a_clk]; + ret = get_external_clk(ddr3a_clk); reg = KS2_DDR3APLLCTL0; break; case DDR3B_PLL: - ret = external_clk[ddr3b_clk]; + ret = get_external_clk(ddr3b_clk); reg = KS2_DDR3BPLLCTL0; break; case UART_PLL: - ret = external_clk[uart_clk]; + ret = get_external_clk(uart_clk); reg = KS2_UARTPLLCTL0; break; default: diff --git a/arch/arm/mach-keystone/include/mach/clock-k2g.h b/arch/arm/mach-keystone/include/mach/clock-k2g.h index 74de620..374f0d9 100644 --- a/arch/arm/mach-keystone/include/mach/clock-k2g.h +++ b/arch/arm/mach-keystone/include/mach/clock-k2g.h @@ -12,8 +12,8 @@ #define PLLSET_CMD_LIST "<pa|arm|ddr3>" -#define DEV_SUPPORTED_SPEEDS 0x1ff -#define ARM_SUPPORTED_SPEEDS 0xff +#define DEV_SUPPORTED_SPEEDS 0xff +#define ARM_SUPPORTED_SPEEDS 0x3ff #define KS2_CLK1_6 sys_clk0_6_clk diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h index 0d8a944..006d074 100644 --- a/arch/arm/mach-keystone/include/mach/clock.h +++ b/arch/arm/mach-keystone/include/mach/clock.h @@ -117,7 +117,6 @@ struct pll_init_data { int pll_od; /* PLL output divider */ }; -extern unsigned int external_clk[ext_clk_count]; extern const struct keystone_pll_regs keystone_pll_regs[]; extern s16 divn_val[]; extern int speeds[]; @@ -129,6 +128,7 @@ unsigned long ks_clk_get_rate(unsigned int clk); int get_max_dev_speed(int *spds); int get_max_arm_speed(int *spds); void pll_pa_clk_sel(void); +unsigned int get_external_clk(u32 clk); #endif #endif diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h index 0f6bf61..90ca120 100644 --- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h @@ -86,4 +86,25 @@ #define RSTMUX_OMODE8_INT 0x3 #define RSTMUX_OMODE8_INT_AND_DEV_RESET 0x4 +/* DEVSTAT register definition */ +#define KS2_DEVSTAT_REFCLK_SHIFT 7 +#define KS2_DEVSTAT_REFCLK_MASK (0x7 << 7) + +/* GPMC */ +#define KS2_GPMC_BASE 0x21818000 + +/* SYSCLK indexes */ +#define SYSCLK_19MHz 0 +#define SYSCLK_24MHz 1 +#define SYSCLK_25MHz 2 +#define SYSCLK_26MHz 3 +#define MAX_SYSCLK 4 + +#ifndef __ASSEMBLY__ +static inline u8 get_sysclk_index(void) +{ + u32 dev_stat = __raw_readl(KS2_DEVSTAT); + return (dev_stat & KS2_DEVSTAT_REFCLK_MASK) >> KS2_DEVSTAT_REFCLK_SHIFT; +} +#endif #endif /* __ASM_ARCH_HARDWARE_K2G_H */ diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index ddfae8c..2dd107a 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -34,6 +34,9 @@ config TARGET_ICONNECT config TARGET_KM_KIRKWOOD bool "KM_KIRKWOOD Board" select BOARD_LATE_INIT + imply CMD_CRAMFS + imply CMD_DIAG + imply FS_CRAMFS config TARGET_NET2BIG_V2 bool "LaCie 2Big Network v2 NAS Board" diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index 1c0477a..2ef5726 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -94,7 +94,7 @@ int dram_init_banksize(void) ac = fdt_address_cells(fdt, 0); sc = fdt_size_cells(fdt, 0); - if (ac < 1 || sc > 2 || sc < 1 || sc > 2) { + if (ac < 1 || ac > 2 || sc < 1 || sc > 2) { printf("invalid address/size cells\n"); return -ENXIO; } diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index d74b068..93fb320 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -1,3 +1,152 @@ +if ARCH_OMAP2PLUS + +choice + prompt "OMAP2+ platform select" + default TARGET_BRXRE1 + +config TARGET_BRXRE1 + bool "Support BRXRE1" + select BOARD_LATE_INIT + +config TARGET_BRPPT1 + bool "Support BRPPT1" + select BOARD_LATE_INIT + +config TARGET_DRACO + bool "Support draco" + select BOARD_LATE_INIT + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_THUBAN + bool "Support thuban" + select BOARD_LATE_INIT + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_RASTABAN + bool "Support rastaban" + select BOARD_LATE_INIT + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_ETAMIN + bool "Support etamin" + select BOARD_LATE_INIT + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_PXM2 + bool "Support pxm2" + select BOARD_LATE_INIT + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_RUT + bool "Support rut" + select BOARD_LATE_INIT + select DM + select DM_SERIAL + select DM_GPIO + +config TARGET_TI814X_EVM + bool "Support ti814x_evm" + +config TARGET_TI816X_EVM + bool "Support ti816x_evm" + +config OMAP34XX + bool "OMAP34XX SoC" + select ARM_ERRATA_430973 + select ARM_ERRATA_454179 + select ARM_ERRATA_621766 + select ARM_ERRATA_725233 + select USE_TINY_PRINTF + imply SPL_EXT_SUPPORT + imply SPL_FAT_SUPPORT + imply SPL_GPIO_SUPPORT + imply SPL_I2C_SUPPORT + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBDISK_SUPPORT + imply SPL_LIBGENERIC_SUPPORT + imply SPL_MMC_SUPPORT + imply SPL_NAND_SUPPORT + imply SPL_POWER_SUPPORT + imply SPL_SERIAL_SUPPORT + imply SYS_THUMB_BUILD + +config OMAP44XX + bool "OMAP44XX SoC" + select USE_TINY_PRINTF + imply SPL_DISPLAY_PRINT + imply SPL_EXT_SUPPORT + imply SPL_FAT_SUPPORT + imply SPL_GPIO_SUPPORT + imply SPL_I2C_SUPPORT + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBDISK_SUPPORT + imply SPL_LIBGENERIC_SUPPORT + imply SPL_MMC_SUPPORT + imply SPL_NAND_SUPPORT + imply SPL_POWER_SUPPORT + imply SPL_SERIAL_SUPPORT + imply SYS_THUMB_BUILD + +config OMAP54XX + bool "OMAP54XX SoC" + select ARM_ERRATA_798870 + select SYS_THUMB_BUILD + imply SPL_DISPLAY_PRINT + imply SPL_ENV_SUPPORT + imply SPL_EXT_SUPPORT + imply SPL_FAT_SUPPORT + imply SPL_GPIO_SUPPORT + imply SPL_I2C_SUPPORT + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBDISK_SUPPORT + imply SPL_LIBGENERIC_SUPPORT + imply SPL_MMC_SUPPORT + imply SPL_NAND_SUPPORT + imply SPL_POWER_SUPPORT + imply SPL_SERIAL_SUPPORT + +config AM43XX + bool "AM43XX SoC" + imply SPL_DM + imply SPL_DM_SEQ_ALIAS + imply SPL_OF_CONTROL + imply SPL_OF_TRANSLATE + imply SPL_SEPARATE_BSS + imply SPL_SYS_MALLOC_SIMPLE + imply SYS_THUMB_BUILD + help + Support for AM43xx SOC from Texas Instruments. + The AM43xx high performance SOC features a Cortex-A9 + ARM core, a quad core PRU-ICSS for industrial Ethernet + protocols, dual camera support, optional 3D graphics + and an optional customer programmable secure boot. + +config AM33XX + bool "AM33XX SoC" + imply SYS_THUMB_BUILD + help + Support for AM335x SOC from Texas Instruments. + The AM335x high performance SOC features a Cortex-A8 + ARM core, a dual core PRU-ICSS for industrial Ethernet + protocols, optional 3D graphics and an optional customer + programmable secure boot. + +config TARGET_CM_T43 + bool "Support cm_t43" + +endchoice + + config TI_SECURE_DEVICE bool "HS Device Type Support" depends on OMAP54XX || AM43XX || AM33XX || ARCH_KEYSTONE @@ -15,3 +164,17 @@ source "arch/arm/mach-omap2/omap4/Kconfig" source "arch/arm/mach-omap2/omap5/Kconfig" source "arch/arm/mach-omap2/am33xx/Kconfig" + +source "board/BuR/brxre1/Kconfig" +source "board/BuR/brppt1/Kconfig" +source "board/siemens/draco/Kconfig" +source "board/siemens/pxm2/Kconfig" +source "board/siemens/rut/Kconfig" +source "board/ti/ti814x/Kconfig" +source "board/ti/ti816x/Kconfig" +source "board/ti/am43xx/Kconfig" +source "board/ti/am335x/Kconfig" +source "board/compulab/cm_t335/Kconfig" +source "board/compulab/cm_t43/Kconfig" + +endif diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index cf5d95a..db3c70f 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -44,8 +44,9 @@ config TARGET_AM335X_BALTOS select DM_SERIAL select DM_GPIO -config TARGET_AM335X_IGEP0033 - bool "Support am335x_igep0033" +config TARGET_AM335X_IGEP003X + bool "Support am335x_igep003x" + select BOARD_LATE_INIT select DM select DM_SERIAL select DM_GPIO diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index f1436fb..01df579 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -46,7 +46,7 @@ static const struct omap_gpio_platdata omap34xx_gpio[] = { { 5, OMAP34XX_GPIO6_BASE }, }; -U_BOOT_DEVICES(am33xx_gpios) = { +U_BOOT_DEVICES(omap34xx_gpios) = { { "gpio_omap", &omap34xx_gpio[0] }, { "gpio_omap", &omap34xx_gpio[1] }, { "gpio_omap", &omap34xx_gpio[2] }, diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig index 4041adc..c89c438 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig +++ b/arch/arm/mach-omap2/omap5/Kconfig @@ -1,11 +1,17 @@ if OMAP54XX +config DRA7XX + bool + help + DRA7xx is an OMAP based SOC with Dual Core A-15s. + choice prompt "OMAP5 board select" optional config TARGET_CL_SOM_AM57X bool "CompuLab CL-SOM-AM57x" + select DRA7XX config TARGET_CM_T54 bool "CompuLab CM-T54" @@ -16,12 +22,14 @@ config TARGET_OMAP5_UEVM config TARGET_DRA7XX_EVM bool "TI DRA7XX" select BOARD_LATE_INIT + select DRA7XX select TI_I2C_BOARD_DETECT select PHYS_64BIT config TARGET_AM57XX_EVM bool "AM57XX" select BOARD_LATE_INIT + select DRA7XX select TI_I2C_BOARD_DETECT endchoice diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 0fa8db0..ec1ffa5 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -39,8 +39,10 @@ u32 secure_rom_call(u32 service, u32 proc_id, u32 flag, ...) num_args = va_arg(ap, u32); - if (num_args > 4) + if (num_args > 4) { + va_end(ap); return 1; + } /* Copy args to aligned args structure */ for (i = 0; i < num_args; i++) diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 6b251c7..327b267 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -4,6 +4,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o + ifdef CONFIG_TPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c new file mode 100644 index 0000000..da36f92 --- /dev/null +++ b/arch/arm/mach-rockchip/bootrom.c @@ -0,0 +1,16 @@ +/** + * Copyright (c) 2017 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/bootrom.h> + +void back_to_bootrom(void) +{ +#if defined(CONFIG_SPL_LIBGENERIC_SUPPORT) && !defined(CONFIG_TPL_BUILD) + printf("Returning to boot ROM..."); +#endif + _back_to_bootrom_s(); +} diff --git a/arch/arm/mach-rockchip/save_boot_param.S b/arch/arm/mach-rockchip/save_boot_param.S index 85b407b..5e6c8db 100644 --- a/arch/arm/mach-rockchip/save_boot_param.S +++ b/arch/arm/mach-rockchip/save_boot_param.S @@ -23,10 +23,10 @@ ENTRY(save_boot_params) ENDPROC(save_boot_params) -.globl back_to_bootrom -ENTRY(back_to_bootrom) +.globl _back_to_bootrom_s +ENTRY(_back_to_bootrom_s) ldr r0, =SAVE_SP_ADDR ldr sp, [r0] mov r0, #0 pop {r1-r12, pc} -ENDPROC(back_to_bootrom) +ENDPROC(_back_to_bootrom_s) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 9bfee04..f6e5773 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -82,6 +82,10 @@ config TARGET_SOCFPGA_TERASIC_DE0_NANO bool "Terasic DE0-Nano-Atlas (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_TERASIC_DE10_NANO + bool "Terasic DE10-Nano (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + config TARGET_SOCFPGA_TERASIC_DE1_SOC bool "Terasic DE1-SoC (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -97,6 +101,7 @@ config SYS_BOARD default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC + default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "is1" if TARGET_SOCFPGA_IS1 default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT @@ -112,6 +117,7 @@ config SYS_VENDOR default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC + default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT config SYS_SOC @@ -122,6 +128,7 @@ config SYS_CONFIG_NAME default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC + default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "socfpga_is1" if TARGET_SOCFPGA_IS1 default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index b73cd63..84f1ee5 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -148,7 +148,7 @@ int board_init(void) debug("Memory controller init failed: %d\n", err); # endif # endif /* CONFIG_TEGRA_PMU */ -#ifdef CONFIG_AS3722_POWER +#ifdef CONFIG_PMIC_AS3722 err = as3722_init(NULL); if (err && err != -ENODEV) return err; diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 124a1c6..7a0b25a 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -16,7 +16,9 @@ obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o obj-y += dram_init.o obj-y += board_init.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o +ifndef CONFIG_SYSRESET obj-y += reset.o +endif obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/ micro-support-card.o obj-y += pinctrl-glue.o diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 92dd610..4bfa10b 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -64,27 +64,33 @@ int board_late_init(void) switch (uniphier_boot_device_raw()) { case BOOT_DEVICE_MMC1: - printf("eMMC Boot\n"); + printf("eMMC Boot"); setenv("bootmode", "emmcboot"); break; case BOOT_DEVICE_NAND: - printf("NAND Boot\n"); + printf("NAND Boot"); setenv("bootmode", "nandboot"); nand_denali_wp_disable(); break; case BOOT_DEVICE_NOR: - printf("NOR Boot\n"); + printf("NOR Boot"); setenv("bootmode", "norboot"); break; case BOOT_DEVICE_USB: - printf("USB Boot\n"); + printf("USB Boot"); setenv("bootmode", "usbboot"); break; default: - printf("Unknown\n"); + printf("Unknown"); break; } + if (uniphier_have_internal_stm()) + printf(" (STM: %s)", + uniphier_boot_from_backend() ? "OFF" : "ON"); + + printf("\n"); + if (uniphier_set_fdt_file()) printf("fdt_file environment was not set correctly\n"); diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c index 5ec0b5b..0080977 100644 --- a/arch/arm/mach-uniphier/boot-device/boot-device.c +++ b/arch/arm/mach-uniphier/boot-device/boot-device.c @@ -22,6 +22,7 @@ struct uniphier_boot_device_info { const unsigned int *boot_device_count; int (*boot_device_is_usb)(u32 pinmon); unsigned int (*boot_device_fixup)(unsigned int mode); + int have_internal_stm; }; static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { @@ -31,6 +32,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_sel_shift = 0, .boot_device_table = uniphier_sld3_boot_device_table, .boot_device_count = &uniphier_sld3_boot_device_count, + .have_internal_stm = 0, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) @@ -39,6 +41,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_sel_shift = 1, .boot_device_table = uniphier_ld4_boot_device_table, .boot_device_count = &uniphier_ld4_boot_device_count, + .have_internal_stm = 1, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO4) @@ -47,6 +50,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_sel_shift = 1, .boot_device_table = uniphier_ld4_boot_device_table, .boot_device_count = &uniphier_ld4_boot_device_count, + .have_internal_stm = 0, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_SLD8) @@ -55,6 +59,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_sel_shift = 1, .boot_device_table = uniphier_ld4_boot_device_table, .boot_device_count = &uniphier_ld4_boot_device_count, + .have_internal_stm = 1, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO5) @@ -63,6 +68,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_sel_shift = 1, .boot_device_table = uniphier_pro5_boot_device_table, .boot_device_count = &uniphier_pro5_boot_device_count, + .have_internal_stm = 0, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PXS2) @@ -73,6 +79,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_count = &uniphier_pxs2_boot_device_count, .boot_device_is_usb = uniphier_pxs2_boot_device_is_usb, .boot_device_fixup = uniphier_pxs2_boot_device_fixup, + .have_internal_stm = 0, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD6B) @@ -83,6 +90,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_count = &uniphier_pxs2_boot_device_count, .boot_device_is_usb = uniphier_pxs2_boot_device_is_usb, .boot_device_fixup = uniphier_pxs2_boot_device_fixup, + .have_internal_stm = 1, /* STM on A-chip */ }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD11) @@ -93,6 +101,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_count = &uniphier_ld11_boot_device_count, .boot_device_is_usb = uniphier_ld11_boot_device_is_usb, .boot_device_fixup = uniphier_ld11_boot_device_fixup, + .have_internal_stm = 1, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) @@ -103,6 +112,7 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = { .boot_device_count = &uniphier_ld11_boot_device_count, .boot_device_is_usb = uniphier_ld20_boot_device_is_usb, .boot_device_fixup = uniphier_ld11_boot_device_fixup, + .have_internal_stm = 1, }, #endif }; @@ -161,6 +171,24 @@ u32 spl_boot_device(void) info->boot_device_fixup(raw_mode) : raw_mode; } +int uniphier_have_internal_stm(void) +{ + const struct uniphier_boot_device_info *info; + + info = uniphier_get_boot_device_info(); + if (!info) { + pr_err("unsupported SoC\n"); + return -ENOTSUPP; + } + + return info->have_internal_stm; +} + +int uniphier_boot_from_backend(void) +{ + return !!(readl(SG_PINMON0) & BIT(27)); +} + #ifndef CONFIG_SPL_BUILD static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -176,12 +204,16 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return CMD_RET_FAILURE; } - printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF"); + if (uniphier_have_internal_stm()) + printf("STB Micon: %s\n", + uniphier_boot_from_backend() ? "OFF" : "ON"); + + printf("Boot Swap: %s\n", boot_is_swapped() ? "ON" : "OFF"); pinmon = readl(SG_PINMON0); if (info->boot_device_is_usb) - printf("USB Boot: %s\n\n", + printf("USB Boot: %s\n", info->boot_device_is_usb(pinmon) ? "ON" : "OFF"); boot_device_count = *info->boot_device_count; @@ -189,7 +221,7 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) boot_sel = pinmon >> info->boot_device_sel_shift; boot_sel &= boot_device_count - 1; - printf("Boot Mode Sel:\n"); + printf("\nBoot Mode Sel:\n"); for (i = 0; i < boot_device_count; i++) printf(" %c %02x %s\n", i == boot_sel ? '*' : ' ', i, info->boot_device_table[i].desc); diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c index a4dcde7..36aa787 100644 --- a/arch/arm/mach-uniphier/clk/clk-ld11.c +++ b/arch/arm/mach-uniphier/clk/clk-ld11.c @@ -37,9 +37,18 @@ void uniphier_ld11_clk_init(void) { /* FIXME: the current clk driver can not handle parents */ u32 tmp; + int ch; + tmp = readl(SC_CLKCTRL4); tmp |= SC_CLKCTRL4_MIO | SC_CLKCTRL4_STDMAC; writel(tmp, SC_CLKCTRL4); + + for (ch = 0; ch < 3; ch++) { + void __iomem *phyctrl = (void __iomem *)SG_USBPHYCTRL; + + writel(0x82280600, phyctrl + 8 * ch); + writel(0x00000106, phyctrl + 8 * ch + 4); + } } #endif } diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index 5c45f2d..4803d08 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -121,6 +121,8 @@ void uniphier_ld11_clk_init(void); void uniphier_ld20_clk_init(void); unsigned int uniphier_boot_device_raw(void); +int uniphier_have_internal_stm(void); +int uniphier_boot_from_backend(void); int uniphier_pin_init(const char *pinconfig_name); void uniphier_smp_kick_all_cpus(void); void cci500_init(int nr_slaves); diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index 4d7e6f7..dc94084 100644 --- a/arch/arm/mach-uniphier/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h @@ -55,6 +55,7 @@ #define SG_MEMCONF_SPARSEMEM (0x1 << 4) +#define SG_USBPHYCTRL (SG_CTRL_BASE | 0x500) #define SG_ETPHYPSHUT (SG_CTRL_BASE | 0x554) #define SG_ETPHYCNT (SG_CTRL_BASE | 0x550) diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c index 8e6d926..3d57a5a 100644 --- a/arch/microblaze/cpu/spl.c +++ b/arch/microblaze/cpu/spl.c @@ -29,15 +29,15 @@ void spl_board_init(void) } #ifdef CONFIG_SPL_OS_BOOT -void __noreturn jump_to_image_linux(struct spl_image_info *spl_image, void *arg) +void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) { - debug("Entering kernel arg pointer: 0x%p\n", arg); + debug("Entering kernel arg pointer: 0x%p\n", spl_image->arg); typedef void (*image_entry_arg_t)(char *, ulong, ulong) __attribute__ ((noreturn)); image_entry_arg_t image_entry = (image_entry_arg_t)spl_image->entry_point; - image_entry(NULL, 0, (ulong)arg); + image_entry(NULL, 0, (ulong)spl_image->arg); } #endif /* CONFIG_SPL_OS_BOOT */ diff --git a/arch/nios2/cpu/Makefile b/arch/nios2/cpu/Makefile index 185ca3c..c859b46 100644 --- a/arch/nios2/cpu/Makefile +++ b/arch/nios2/cpu/Makefile @@ -8,4 +8,3 @@ extra-y = start.o obj-y = exceptions.o obj-y += cpu.o interrupts.o traps.o -obj-y += fdt.o diff --git a/arch/nios2/cpu/fdt.c b/arch/nios2/cpu/fdt.c deleted file mode 100644 index a44f51a..0000000 --- a/arch/nios2/cpu/fdt.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2011, Missing Link Electronics - * Joachim Foerster <joachim@missinglinkelectronics.com> - * - * Taken from arch/powerpc/cpu/ppc4xx/fdt.c: - * - * (C) Copyright 2007-2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#ifdef CONFIG_OF_BOARD_SETUP -#include <libfdt.h> -#include <fdt_support.h> - -DECLARE_GLOBAL_DATA_PTR; - -int __ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - return 0; -} -int ft_board_setup(void *blob, bd_t *bd) - __attribute__((weak, alias("__ft_board_setup"))); - -void ft_cpu_setup(void *blob, bd_t *bd) -{ - /* - * Fixup all ethernet nodes - * Note: aliases in the dts are required for this - */ - fdt_fixup_ethernet(blob); -} -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/arch/powerpc/cpu/mpc512x/cpu.c b/arch/powerpc/cpu/mpc512x/cpu.c index 4ee91e1..ce524fc 100644 --- a/arch/powerpc/cpu/mpc512x/cpu.c +++ b/arch/powerpc/cpu/mpc512x/cpu.c @@ -176,9 +176,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) old_ft_cpu_setup(blob, bd); #endif ft_clock_setup(blob, bd); -#ifdef CONFIG_HAS_ETH0 - fdt_fixup_ethernet(blob); -#endif fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); } #endif diff --git a/arch/powerpc/cpu/mpc8260/Kconfig b/arch/powerpc/cpu/mpc8260/Kconfig index e93732d..47bae55 100644 --- a/arch/powerpc/cpu/mpc8260/Kconfig +++ b/arch/powerpc/cpu/mpc8260/Kconfig @@ -10,6 +10,8 @@ choice config TARGET_KM82XX bool "Support km82xx" + imply CMD_CRAMFS + imply FS_CRAMFS endchoice diff --git a/arch/powerpc/cpu/mpc8260/cpu.c b/arch/powerpc/cpu/mpc8260/cpu.c index 58d1c02..7302b37 100644 --- a/arch/powerpc/cpu/mpc8260/cpu.c +++ b/arch/powerpc/cpu/mpc8260/cpu.c @@ -294,11 +294,6 @@ void watchdog_reset (void) #ifdef CONFIG_OF_BOARD_SETUP void ft_cpu_setup (void *blob, bd_t *bd) { -#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ - defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) - fdt_fixup_ethernet(blob); -#endif - do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", "clock-frequency", bd->bi_brgfreq, 1); diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index bf3be50..02e43bc 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -64,12 +64,19 @@ config TARGET_IDS8313 config TARGET_KM8360 bool "Support km8360" + imply CMD_CRAMFS + imply CMD_DIAG + imply FS_CRAMFS config TARGET_SUVD3 bool "Support suvd3" + imply CMD_CRAMFS + imply FS_CRAMFS config TARGET_TUXX1 bool "Support tuxx1" + imply CMD_CRAMFS + imply FS_CRAMFS config TARGET_TQM834X bool "Support TQM834x" diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index f249a58..3ac4eb1 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -53,7 +53,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\ defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5) - fdt_fixup_ethernet(blob); #ifdef CONFIG_MPC8313 /* * mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1 diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 592b581..31c0964 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -321,6 +321,8 @@ config TARGET_KMP204X bool "Support kmp204x" select ARCH_P2041 select PHYS_64BIT + imply CMD_CRAMFS + imply FS_CRAMFS config TARGET_XPEDITE520X bool "Support xpedite520x" diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 67140ba..a9ea947 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -612,8 +612,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) } #endif - fdt_fixup_ethernet(blob); - fdt_add_enet_stashing(blob); #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index eb817f1..63fdffd 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1145,8 +1145,9 @@ switch_as: li r0,0 1: dcbz r0,r3 -#ifdef CONFIG_E6500 /* Lock/unlock L2 cache instead of L1 */ +#ifdef CONFIG_E6500 /* Lock/unlock L2 cache long with L1 */ dcbtls 2, r0, r3 + dcbtls 0, r0, r3 #else dcbtls 0, r0, r3 #endif @@ -1790,8 +1791,9 @@ unlock_ram_in_cache: slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) mtctr r4 1: dcbi r0,r3 -#ifdef CONFIG_E6500 /* lock/unlock L2 cache instead of L1 */ +#ifdef CONFIG_E6500 /* lock/unlock L2 cache long with L1 */ dcblc 2, r0, r3 + dcblc 0, r0, r3 #else dcblc r0,r3 #endif diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index 5f9ad6b..30fbf14 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c @@ -32,11 +32,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); -#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) \ - || defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) - fdt_fixup_ethernet(blob); -#endif - #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c index 97830e3..34d3647 100644 --- a/arch/powerpc/cpu/mpc8xx/fdt.c +++ b/arch/powerpc/cpu/mpc8xx/fdt.c @@ -23,8 +23,5 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency", gd->arch.brg_clk, 1); - /* Fixup ethernet MAC addresses */ - fdt_fixup_ethernet(blob); - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); } diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index a6066ef..38121c1 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -129,6 +129,14 @@ config TARGET_XILINX_PPC440_GENERIC endchoice +config CMD_CHIP_CONFIG + bool "Enable the 'chip_config' command" + help + This command programs the I2C bootstrap EEPROM or shows a list of + possible configurations. The configurations are board-specific + and control the CPU and peripehrals clocks. The programmed + configuration is then used when the board boots. + source "board/amcc/acadia/Kconfig" source "board/amcc/bamboo/Kconfig" source "board/amcc/bubinga/Kconfig" diff --git a/arch/powerpc/cpu/ppc4xx/fdt.c b/arch/powerpc/cpu/ppc4xx/fdt.c index c73509b..2808058 100644 --- a/arch/powerpc/cpu/ppc4xx/fdt.c +++ b/arch/powerpc/cpu/ppc4xx/fdt.c @@ -150,12 +150,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) } /* - * Fixup all ethernet nodes - * Note: aliases in the dts are required for this - */ - fdt_fixup_ethernet(blob); - - /* * Fixup all available PCIe nodes by setting the device_type property */ fdt_pcie_setup(blob); diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 1b7cf09..62ce816 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -100,7 +100,6 @@ #endif /* ifdef CONFIG_SPL_BUILD */ #define CONFIG_CMD_ESBC_VALIDATE -#define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON #define CONFIG_SHA_PROG_HW_ACCEL diff --git a/arch/powerpc/lib/spl.c b/arch/powerpc/lib/spl.c index 080b978..b931970 100644 --- a/arch/powerpc/lib/spl.c +++ b/arch/powerpc/lib/spl.c @@ -14,18 +14,18 @@ DECLARE_GLOBAL_DATA_PTR; /* * This function jumps to an image with argument. Normally an FDT or ATAGS * image. - * arg: Pointer to paramter image in RAM */ #ifdef CONFIG_SPL_OS_BOOT -void __noreturn jump_to_image_linux(struct spl_image_info *spl_image, void *arg) +void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) { - debug("Entering kernel arg pointer: 0x%p\n", arg); + debug("Entering kernel arg pointer: 0x%p\n", spl_image->arg); typedef void (*image_entry_arg_t)(void *, ulong r4, ulong r5, ulong r6, ulong r7, ulong r8, ulong r9) __attribute__ ((noreturn)); image_entry_arg_t image_entry = (image_entry_arg_t)spl_image->entry_point; - image_entry(arg, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ, 0, 0); + image_entry(spl_image->arg, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ, + 0, 0); } #endif /* CONFIG_SPL_OS_BOOT */ diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index fff175d..094c5aa 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -272,6 +272,14 @@ power-domains = <&pwrdom 2>; }; + pwm { + compatible = "sandbox,pwm"; + }; + + pwm2 { + compatible = "sandbox,pwm"; + }; + ram { compatible = "sandbox,ram"; }; @@ -418,6 +426,10 @@ }; }; }; + + wdt0: wdt@0 { + compatible = "sandbox,wdt"; + }; }; #include "sandbox_pmic.dtsi" diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index 149f28d..987cc7b 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -39,6 +39,12 @@ struct sandbox_spi_info { struct udevice *emul; }; +struct sandbox_wdt_info { + unsigned long long counter; + uint reset_count; + bool running; +}; + /* The complete state of the test system */ struct sandbox_state { const char *cmd; /* Command to execute */ @@ -69,6 +75,9 @@ struct sandbox_state { /* Pointer to information for each SPI bus/cs */ struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS] [CONFIG_SANDBOX_SPI_MAX_CS]; + + /* Information about Watchdog */ + struct sandbox_wdt_info wdt; }; /* Minimum space we guarantee in the state FDT when calling read/write*/ diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index 4b3601f..9820651 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -3,6 +3,8 @@ if TARGET_COREBOOT config SYS_COREBOOT bool default y + imply CMD_CBFS + imply FS_CBFS config CBMEM_CONSOLE bool diff --git a/arch/x86/cpu/cpu_x86.c b/arch/x86/cpu/cpu_x86.c index 8be14b5..b465b14 100644 --- a/arch/x86/cpu/cpu_x86.c +++ b/arch/x86/cpu/cpu_x86.c @@ -41,10 +41,14 @@ int cpu_x86_get_vendor(struct udevice *dev, char *buf, int size) int cpu_x86_get_desc(struct udevice *dev, char *buf, int size) { + char *ptr; + if (size < CPU_MAX_NAME_LEN) return -ENOSPC; - cpu_get_name(buf); + ptr = cpu_get_name(buf); + if (ptr != buf) + strcpy(buf, ptr); return 0; } diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 2b1b450..832a5d7 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -37,8 +37,6 @@ static int x86_spl_init(void) debug("%s: spl_init() failed\n", __func__); return ret; } - preloader_console_init(); - ret = arch_cpu_init(); if (ret) { debug("%s: arch_cpu_init() failed\n", __func__); @@ -49,6 +47,7 @@ static int x86_spl_init(void) debug("%s: arch_cpu_init_dm() failed\n", __func__); return ret; } + preloader_console_init(); ret = print_cpuinfo(); if (ret) { debug("%s: print_cpuinfo() failed\n", __func__); |