diff options
Diffstat (limited to 'board/cadence')
| -rw-r--r-- | board/cadence/xtfpga/Kconfig | 39 | ||||
| -rw-r--r-- | board/cadence/xtfpga/MAINTAINERS | 7 | ||||
| -rw-r--r-- | board/cadence/xtfpga/Makefile | 7 | ||||
| -rw-r--r-- | board/cadence/xtfpga/README | 125 | ||||
| -rw-r--r-- | board/cadence/xtfpga/xtfpga.c | 115 |
5 files changed, 293 insertions, 0 deletions
diff --git a/board/cadence/xtfpga/Kconfig b/board/cadence/xtfpga/Kconfig new file mode 100644 index 0000000..69296be --- /dev/null +++ b/board/cadence/xtfpga/Kconfig @@ -0,0 +1,39 @@ +if TARGET_XTFPGA + +choice + prompt "XTFPGA board type select" + +config XTFPGA_LX60 + bool "Support Avnet LX60" +config XTFPGA_LX110 + bool "Support Avnet LX110" +config XTFPGA_LX200 + bool "Support Avnet LX200" +config XTFPGA_ML605 + bool "Support Xilinx ML605" +config XTFPGA_KC705 + bool "Support Xilinx KC705" + +endchoice + +config SYS_BOARD + string + default "xtfpga" + +config SYS_VENDOR + string + default "cadence" + +config SYS_CONFIG_NAME + string + default "xtfpga" + +config BOARD_SDRAM_SIZE + hex + default 0x04000000 if XTFPGA_LX60 + default 0x03000000 if XTFPGA_LX110 + default 0x06000000 if XTFPGA_LX200 + default 0x18000000 if XTFPGA_ML605 + default 0x38000000 if XTFPGA_KC705 + +endif diff --git a/board/cadence/xtfpga/MAINTAINERS b/board/cadence/xtfpga/MAINTAINERS new file mode 100644 index 0000000..f4a2b94 --- /dev/null +++ b/board/cadence/xtfpga/MAINTAINERS @@ -0,0 +1,7 @@ +XTFPGA BOARD +M: Max Filippov <jcmvbkbc@gmail.com> +S: Maintained +F: board/cadence/xtfpga/ +F: include/configs/xtfpga.h +F: configs/xtfpga_defconfig +F: drivers/sysreset/sysreset_xtfpga.c diff --git a/board/cadence/xtfpga/Makefile b/board/cadence/xtfpga/Makefile new file mode 100644 index 0000000..fd8f720 --- /dev/null +++ b/board/cadence/xtfpga/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2007 - 2013, Tensilica Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ${BOARD}.o diff --git a/board/cadence/xtfpga/README b/board/cadence/xtfpga/README new file mode 100644 index 0000000..5f29e25 --- /dev/null +++ b/board/cadence/xtfpga/README @@ -0,0 +1,125 @@ + Tensilica 'xtfpga' Evaluation Boards + ==================================== + +Tensilica's 'xtfpga' evaluation boards are actually a set of different +boards that share configurations. The following is a list of supported +hardware by this board type: + +- XT-AV60 / LX60 +- XT-AV110 / LX110 +- XT-AV200 / LX200 +- ML605 +- KC705 + +All boards provide the following common configurations: + +- An Xtensa or Diamond processor core. +- An on-chip-debug (OCD) JTAG interface. +- A 16550 compatible UART and serial port. +- An OpenCores Wishbone 10/100-base-T ethernet interface. +- A 32 char two line LCD display. (except for the LX200) + +LX60/LX110/LX200: + +- Virtex-4 (XC4VLX60 / XCV4LX200) / Virtext-5 (XC5VLX110) +- 128MB / 64MB (LX60) memory +- 16MB / 4MB (LX60) Linear Flash + +ML605 + +- Virtex-6 (XC6VLX240T) +- 512MB DDR3 memory +- 16MB Linear BPI Flash + +KC705 (Xilinx) + +- Kintex-7 XC7K325T FPGA +- 1GB DDR3 memory +- 128MB Linear BPI Flash + + +Setting up the Board +-------------------- + +The serial port defaults to 115200 baud, no parity and 1 stop bit. +A terminal emulator must be set accordingly to see the U-Boot prompt. + + +Board Configurations LX60/LX110/LX200/ML605/KC705 +------------------------------------------------- + +The LX60/LX110/LX200/ML605 contain an 8-way DIP switch that controls +the boot mapping and selects from a range of default ethernet MAC +addresses. + +Boot Mapping (DIP switch 8): + + DIP switch 8 maps the system ROM address space (in which the + reset vector resides) to either SRAM (off, 0, down) or Flash + (on, 1, up). This mapping is implemented in the FPGA bitstream + and cannot be disabled by software, therefore DIP switch 8 is no + available for application use. Note DIP switch 7 is reserved by + Tensilica for future possible hardware use. + + Mapping to SRAM allows U-Boot to be debugged with an OCD/JTAG + tool such as the Xtensa OCD Daemon connected via a suppored probe. + See the tools documentation for supported probes and how to + connect them. Be aware that the board has only 128 KB of SRAM, + therefore U-Boot must fit within this space to debug an image + intended for the Flash. This issues is discussed in a separate + section toward the end. + + Mapping to flash allows U-Boot to start on reset, provided it + has been programmed into the first two 64 KB sectors of the Flash. + + The Flash is always mapped at a device (memory mapped I/O) address + (the address is board specific and is expressed as CFG_FLASH_BASE). + The device address is used by U-Boot to program the flash, and may + be used to specify an application to run or U-Boot image to boot. + +Default MAC Address (DIP switches 1-6): + + When the board is first powered on, or after the environment has + been reinitialized, the ethernet MAC address receives a default + value whose least significant 6 bits come from DIP switches 1-6. + The default is 00:50:C2:13:6F:xx where xx ranges from 0..3F + according to the DIP switches, where "on"==1 and "off"==0, and + switch 1 is the least-significant bit. + + After initial startup, the MAC address is stored in the U-Boot + environment variable 'ethaddr'. The user may change this to any + other address with the "setenv" comamnd. After the environment + has been saved to Flash by the "saveenv" command, this will be + used and the DIP switches no longer consulted. DIP swithes 1-6 + may then be used for application purposes. + +The KC705 board contains 4-way DIP switch, way 1 is the boot mapping +switch and ways 2-4 control the low three bits of the MAC address. + + +Limitation of SDRAM Size for OCD Debugging on the LX60 +------------------------------------------------------ + +The XT-AV60 board has only 128 KB of SDRAM that can be mapped +to the system ROM address space for debugging a ROM image under +OCD/JTAG. This limits the useful size of U-Boot to 128 KB (0x20000) +or the first 2 sectors of the flash. + +This can pose a problem if all the sources are compiled with -O0 +for debugging. The code size is then too large, in which case it +would be necessary to temporarily alter the linker script to place +the load addresses (LMA) in the RAM (VMA) so that OCD loads U-Boot +directly there and does not unpack. In practice this is not really +necessary as long as only a limited set of sources need to be +debugged, because the image can still fit into the 128 KB SRAM. + +The recommended procedure for debugging is to first build U-Boot +with the default optimization level (-Os), and then touch and +rebuild incrementally with -O0 so that only the touched sources +are recompiled with -O0. To build with -O0, pass it in the KCFLAGS +variable to make. + +Because this problem is easy to fall into and difficult to debug +if one doesn't expect it, the linker script provides a link-time +check and fatal error message if the image size exceeds 128 KB. + diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c new file mode 100644 index 0000000..5899aa6 --- /dev/null +++ b/board/cadence/xtfpga/xtfpga.c @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2007 - 2013 Tensilica Inc. + * (C) Copyright 2014 - 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <dm/platdata.h> +#include <dm/platform_data/net_ethoc.h> +#include <linux/ctype.h> +#include <linux/string.h> +#include <linux/stringify.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Check board idendity. + * (Print information about the board to stdout.) + */ + + +#if defined(CONFIG_XTFPGA_LX60) +const char *board = "XT_AV60"; +const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / "; +#elif defined(CONFIG_XTFPGA_LX110) +const char *board = "XT_AV110"; +const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / "; +#elif defined(CONFIG_XTFPGA_LX200) +const char *board = "XT_AV200"; +const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / "; +#elif defined(CONFIG_XTFPGA_ML605) +const char *board = "XT_ML605"; +const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / "; +#elif defined(CONFIG_XTFPGA_KC705) +const char *board = "XT_KC705"; +const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / "; +#else +const char *board = "<unknown>"; +const char *description = ""; +#endif + +int checkboard(void) +{ + printf("Board: %s: %sTensilica bitstream\n", board, description); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE); + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; +} + +int board_postclk_init(void) +{ + /* + * Obtain CPU clock frequency from board and cache in global + * data structure (Hz). Return 0 on success (OK to continue), + * else non-zero (hang). + */ + +#ifdef CONFIG_SYS_FPGAREG_FREQ + gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ); +#else + /* early Tensilica bitstreams lack this reg, but most run at 50 MHz */ + gd->cpu_clk = 50000000UL; +#endif + return 0; +} + +/* + * Miscellaneous late initializations. + * The environment has been set up, so we can set the Ethernet address. + */ + +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_NET + /* + * Initialize ethernet environment variables and board info. + * Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6. + */ + + char *s = getenv("ethaddr"); + if (s == 0) { + unsigned int x; + char s[] = __stringify(CONFIG_ETHBASE); + x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW) + & FPGAREG_MAC_MASK; + sprintf(&s[15], "%02x", x); + setenv("ethaddr", s); + } +#endif /* CONFIG_CMD_NET */ + + return 0; +} + +U_BOOT_DEVICE(sysreset) = { + .name = "xtfpga_sysreset", +}; + +static struct ethoc_eth_pdata ethoc_pdata = { + .eth_pdata = { + .iobase = CONFIG_SYS_ETHOC_BASE, + }, + .packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR, +}; + +U_BOOT_DEVICE(ethoc) = { + .name = "ethoc", + .platdata = ðoc_pdata, +}; |