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-rw-r--r--board/freescale/b4860qds/b4860qds.c95
-rw-r--r--board/freescale/b4860qds/eth_b4860qds.c127
-rw-r--r--board/freescale/b4860qds/law.c3
3 files changed, 191 insertions, 34 deletions
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index bed8f56..6a8fca6 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -19,6 +19,7 @@
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
+#include <hwconfig.h>
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
@@ -333,6 +334,8 @@ int configure_vsc3316_3308(void)
unsigned int num_vsc16_con, num_vsc08_con;
u32 serdes1_prtcl, serdes2_prtcl;
int ret;
+ char buffer[HWCONFIG_BUFFER_SIZE];
+ char *buf = NULL;
serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@@ -385,15 +388,18 @@ int configure_vsc3316_3308(void)
}
break;
+ case 0x01:
case 0x02:
case 0x04:
case 0x05:
case 0x06:
+ case 0x07:
case 0x08:
case 0x09:
case 0x0A:
case 0x0B:
case 0x0C:
+ case 0x2F:
case 0x30:
case 0x32:
case 0x33:
@@ -487,6 +493,9 @@ int configure_vsc3316_3308(void)
return -1;
}
+ num_vsc08_con = NUM_CON_VSC3308;
+ /* Configure VSC3308 crossbar switch */
+ ret = select_i2c_ch_pca(I2C_CH_VSC3308);
switch (serdes2_prtcl) {
#ifdef CONFIG_PPC_B4420
case 0x9d:
@@ -494,14 +503,11 @@ int configure_vsc3316_3308(void)
case 0x9E:
case 0x9A:
case 0x98:
- case 0xb2:
+ case 0x48:
case 0x49:
case 0x4E:
- case 0x8D:
+ case 0x79:
case 0x7A:
- num_vsc08_con = NUM_CON_VSC3308;
- /* Configure VSC3308 crossbar switch */
- ret = select_i2c_ch_pca(I2C_CH_VSC3308);
if (!ret) {
ret = vsc3308_config(VSC3308_TX_ADDRESS,
vsc08_tx_amc, num_vsc08_con);
@@ -515,6 +521,71 @@ int configure_vsc3316_3308(void)
return ret;
}
break;
+ case 0x80:
+ case 0x81:
+ case 0x82:
+ case 0x83:
+ case 0x84:
+ case 0x85:
+ case 0x86:
+ case 0x87:
+ case 0x88:
+ case 0x89:
+ case 0x8a:
+ case 0x8b:
+ case 0x8c:
+ case 0x8d:
+ case 0x8e:
+ case 0xb1:
+ case 0xb2:
+ if (!ret) {
+ /*
+ * Extract hwconfig from environment since environment
+ * is not setup properly yet
+ */
+ getenv_f("hwconfig", buffer, sizeof(buffer));
+ buf = buffer;
+
+ if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
+ "sfp_amc", "sfp", buf)) {
+#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
+ /* change default VSC3308 for XFI erratum */
+ ret = vsc3308_config_adjust(VSC3308_TX_ADDRESS,
+ vsc08_tx_sfp, num_vsc08_con);
+ if (ret)
+ return ret;
+
+ ret = vsc3308_config_adjust(VSC3308_RX_ADDRESS,
+ vsc08_rx_sfp, num_vsc08_con);
+ if (ret)
+ return ret;
+#else
+ ret = vsc3308_config(VSC3308_TX_ADDRESS,
+ vsc08_tx_sfp, num_vsc08_con);
+ if (ret)
+ return ret;
+
+ ret = vsc3308_config(VSC3308_RX_ADDRESS,
+ vsc08_rx_sfp, num_vsc08_con);
+ if (ret)
+ return ret;
+#endif
+ } else {
+ ret = vsc3308_config(VSC3308_TX_ADDRESS,
+ vsc08_tx_amc, num_vsc08_con);
+ if (ret)
+ return ret;
+
+ ret = vsc3308_config(VSC3308_RX_ADDRESS,
+ vsc08_rx_amc, num_vsc08_con);
+ if (ret)
+ return ret;
+ }
+
+ } else {
+ return ret;
+ }
+ break;
default:
printf("WARNING:VSC crossbars programming not supported for: %x"
" SerDes2 Protocol.\n", serdes2_prtcl);
@@ -730,19 +801,23 @@ int config_serdes1_refclks(void)
* to 122.88MHz
*/
switch (serdes1_prtcl) {
+ case 0x29:
case 0x2A:
case 0x2C:
case 0x2D:
case 0x2E:
+ case 0x01:
case 0x02:
case 0x04:
case 0x05:
case 0x06:
+ case 0x07:
case 0x08:
case 0x09:
case 0x0A:
case 0x0B:
case 0x0C:
+ case 0x2F:
case 0x30:
case 0x32:
case 0x33:
@@ -860,6 +935,8 @@ int config_serdes2_refclks(void)
#endif
case 0x9E:
case 0x9A:
+ /* fallthrough */
+ case 0xb1:
case 0xb2:
debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
serdes2_prtcl);
@@ -915,6 +992,14 @@ int board_early_init_r(void)
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
int ret;
+ u32 svr = SVR_SOC_VER(get_svr());
+
+ /* Create law for MAPLE only for personalities having MAPLE */
+ if ((svr == SVR_B4860) || (svr == SVR_B4440) ||
+ (svr == SVR_B4420) || (svr == SVR_B4220)) {
+ set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M,
+ LAW_TRGT_IF_MAPLE);
+ }
/*
* Remap Boot flash + PROMJET region to caching-inhibited
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index 12df9a8..501d4b3 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -112,7 +112,10 @@ static void initialize_lane_to_slot(void)
* Lanes: A,B,C,D: PCI
* Lanes: E,F,G,H: XAUI2
*/
+ case 0xb1:
case 0xb2:
+ case 0x8c:
+ case 0x8d:
/*
* Configuration:
* SERDES: 2
@@ -195,34 +198,34 @@ int board_eth_init(bd_t *bis)
* all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
* 6 to on board SGMII phys
*/
- fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
switch (serdes1_prtcl) {
case 0x29:
case 0x2a:
/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
- debug("Setting phy addresses for FM1_DTSEC5: %x and"
- "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
fm_info_set_phy_address(FM1_DTSEC5,
- CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC6,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#ifdef CONFIG_PPC_B4420
case 0x17:
case 0x18:
/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
- debug("Setting phy addresses for FM1_DTSEC3: %x and"
- "FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
/* Fixing Serdes clock by programming FPGA register */
QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#endif
default:
@@ -233,8 +236,8 @@ int board_eth_init(bd_t *bis)
switch (serdes2_prtcl) {
case 0x17:
case 0x18:
- debug("Setting phy addresses on SGMII Riser card for"
- "FM1_DTSEC ports: \n");
+ debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
@@ -246,8 +249,8 @@ int board_eth_init(bd_t *bis)
break;
case 0x48:
case 0x49:
- debug("Setting phy addresses on SGMII Riser card for"
- "FM1_DTSEC ports: \n");
+ debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
@@ -255,29 +258,37 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
break;
- case 0x8d:
+ case 0xb1:
case 0xb2:
- debug("Setting phy addresses on SGMII Riser card for"
- "FM1_DTSEC ports: \n");
+ case 0x8c:
+ case 0x8d:
+ debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n",
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
+ /*
+ * XFI does not need a PHY to work, but to make U-boot
+ * happy, assign a fake PHY address for a XFI port.
+ */
+ fm_info_set_phy_address(FM1_10GEC1, 0);
+ fm_info_set_phy_address(FM1_10GEC2, 1);
break;
case 0x98:
/* XAUI in Slot1 and Slot2 */
- debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC1: %x\n",
+ debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n",
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC1,
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
- debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
+ debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2,
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
break;
case 0x9E:
/* XAUI in Slot2 */
- debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
+ debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2,
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
@@ -329,17 +340,20 @@ int board_eth_init(bd_t *bis)
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
fm_info_set_mdio(i,
- miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
+ miiphy_get_dev_by_name
+ (DEFAULT_FM_TGEC_MDIO_NAME));
+ break;
+ case PHY_INTERFACE_MODE_NONE:
+ fm_info_set_phy_address(i, 0);
break;
default:
- printf("Fman1: 10GSEC%u set to unknown interface %i\n",
+ printf("Fman1: TGEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
}
-
cpu_eth_init(bis);
#endif
@@ -351,21 +365,82 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
{
int phy;
char alias[32];
+ struct fixed_link f_link;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+ prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
phy = fm_info_get_phy_address(port);
sprintf(alias, "phy_sgmii_%x", phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, alias);
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
+ /* check if it's XFI interface for 10g */
+ switch (prtcl2) {
+ case 0x80:
+ case 0x81:
+ case 0x82:
+ case 0x83:
+ case 0x84:
+ case 0x85:
+ case 0x86:
+ case 0x87:
+ case 0x88:
+ case 0x89:
+ case 0x8a:
+ case 0x8b:
+ case 0x8c:
+ case 0x8d:
+ case 0x8e:
+ case 0xb1:
+ case 0xb2:
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 10000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link,
+ sizeof(f_link));
+ break;
+ case 0x98: /* XAUI interface */
+ sprintf(alias, "phy_xaui_slot1");
+ fdt_status_okay_by_alias(fdt, alias);
+
+ sprintf(alias, "phy_xaui_slot2");
+ fdt_status_okay_by_alias(fdt, alias);
+ break;
+ case 0x9e: /* XAUI interface */
+ case 0x9a:
+ case 0x93:
+ case 0x91:
+ sprintf(alias, "phy_xaui_slot1");
+ fdt_status_okay_by_alias(fdt, alias);
+ break;
+ case 0x97: /* XAUI interface */
+ case 0xc3:
+ sprintf(alias, "phy_xaui_slot2");
+ fdt_status_okay_by_alias(fdt, alias);
+ break;
+ default:
+ break;
+ }
}
}
+/*
+ * Set status to disabled for unused ethernet node
+ */
void fdt_fixup_board_enet(void *fdt)
{
int i;
char alias[32];
- for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_NONE:
sprintf(alias, "ethernet%u", i);
diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c
index 5b327cc..047c3cb 100644
--- a/board/freescale/b4860qds/law.c
+++ b/board/freescale/b4860qds/law.c
@@ -17,9 +17,6 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_MAPLE_MEM_PHYS
- SET_LAW(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_MAPLE),
-#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
generated by cgit v0.10.2 at 2024-11-07 00:36:23 (GMT)