diff options
Diffstat (limited to 'board/freescale/common')
| -rw-r--r-- | board/freescale/common/Kconfig | 20 | ||||
| -rw-r--r-- | board/freescale/common/Makefile | 31 | ||||
| -rw-r--r-- | board/freescale/common/arm_sleep.c | 6 | ||||
| -rw-r--r-- | board/freescale/common/fsl_chain_of_trust.c | 11 | ||||
| -rw-r--r-- | board/freescale/common/fsl_validate.c | 148 | ||||
| -rw-r--r-- | board/freescale/common/mc34vr500.c | 95 | ||||
| -rw-r--r-- | board/freescale/common/ns_access.c | 25 | ||||
| -rw-r--r-- | board/freescale/common/pixis.h | 10 | ||||
| -rw-r--r-- | board/freescale/common/pq-mds-pib.c | 2 | ||||
| -rw-r--r-- | board/freescale/common/spl.h | 13 | ||||
| -rw-r--r-- | board/freescale/common/vid.c | 174 | ||||
| -rw-r--r-- | board/freescale/common/zm7300.c | 4 |
12 files changed, 431 insertions, 108 deletions
diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig new file mode 100644 index 0000000..8a5c456 --- /dev/null +++ b/board/freescale/common/Kconfig @@ -0,0 +1,20 @@ +config CHAIN_OF_TRUST + depends on !FIT_SIGNATURE && SECURE_BOOT + imply CMD_BLOB + imply CMD_HASH if ARM + select FSL_CAAM + select SPL_BOARD_INIT if (ARM && SPL) + select SHA_HW_ACCEL + select SHA_PROG_HW_ACCEL + select ENV_IS_NOWHERE + bool + default y + +config CMD_ESBC_VALIDATE + bool "Enable the 'esbc_validate' and 'esbc_halt' commands" + default y if CHAIN_OF_TRUST + help + This option enables two commands used for secure booting: + + esbc_validate - validate signature using RSA verification + esbc_halt - put the core in spin loop (Secure Boot Only) diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index be114ce..1c53fb6 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -45,31 +45,32 @@ endif obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o -obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o -obj-$(CONFIG_MPC8548CDS) += cds_pci_ft.o -obj-$(CONFIG_MPC8555CDS) += cds_pci_ft.o +obj-$(CONFIG_TARGET_MPC8541CDS) += cds_pci_ft.o +obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o +obj-$(CONFIG_TARGET_MPC8555CDS) += cds_pci_ft.o -obj-$(CONFIG_MPC8536DS) += ics307_clk.o -obj-$(CONFIG_MPC8572DS) += ics307_clk.o -obj-$(CONFIG_P1022DS) += ics307_clk.o +obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o +obj-$(CONFIG_TARGET_MPC8572DS) += ics307_clk.o +obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o obj-$(CONFIG_P2020DS) += ics307_clk.o -obj-$(CONFIG_P3041DS) += ics307_clk.o -obj-$(CONFIG_P4080DS) += ics307_clk.o -obj-$(CONFIG_P5020DS) += ics307_clk.o -obj-$(CONFIG_P5040DS) += ics307_clk.o +obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o +obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o +obj-$(CONFIG_TARGET_P5020DS) += ics307_clk.o +obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o obj-$(CONFIG_ZM7300) += zm7300.o obj-$(CONFIG_POWER_PFUZE100) += pfuze.o +obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o # deal with common files for P-series corenet based devices -obj-$(CONFIG_P2041RDB) += p_corenet/ -obj-$(CONFIG_P3041DS) += p_corenet/ -obj-$(CONFIG_P4080DS) += p_corenet/ -obj-$(CONFIG_P5020DS) += p_corenet/ -obj-$(CONFIG_P5040DS) += p_corenet/ +obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/ +obj-$(CONFIG_TARGET_P3041DS) += p_corenet/ +obj-$(CONFIG_TARGET_P4080DS) += p_corenet/ +obj-$(CONFIG_TARGET_P5020DS) += p_corenet/ +obj-$(CONFIG_TARGET_P5040DS) += p_corenet/ obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c index 16fd445..6ed5d9e 100644 --- a/board/freescale/common/arm_sleep.c +++ b/board/freescale/common/arm_sleep.c @@ -13,7 +13,7 @@ #endif #include <asm/armv7.h> -#if defined(CONFIG_LS102XA) +#if defined(CONFIG_ARCH_LS1021A) #include <asm/arch/immap_ls102xa.h> #endif @@ -66,7 +66,7 @@ static void dp_ddr_restore(void) *dst++ = *src++; } -#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_LS102XA) +#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A) void ls1_psci_resume_fixup(void) { u32 tmp; @@ -104,7 +104,7 @@ static void dp_resume_prepare(void) #ifdef CONFIG_U_QE u_qe_resume(); #endif -#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_LS102XA) +#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A) ls1_psci_resume_fixup(); #endif } diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index dea231b..dfe5d20 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <dm.h> #include <fsl_validate.h> #include <fsl_secboot_err.h> #include <fsl_sfp.h> @@ -22,7 +23,7 @@ #include <asm/fsl_pamu.h> #endif -#ifdef CONFIG_LS102XA +#ifdef CONFIG_ARCH_LS1021A #include <asm/arch/immap_ls102xa.h> #endif @@ -80,7 +81,13 @@ int fsl_setenv_chain_of_trust(void) * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) */ setenv("bootdelay", "0"); + +#ifdef CONFIG_ARM + setenv("secureboot", "y"); +#else setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD); +#endif + return 0; } #endif @@ -151,7 +158,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) * may return back in case of non-fatal failures. */ - debug("image entry point: 0x%X\n", spl_image->entry_point); + debug("image entry point: 0x%lX\n", spl_image->entry_point); image_entry(); } #endif /* ifdef CONFIG_SPL_FRAMEWORK */ diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 8c171b1..ef93407 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -5,17 +5,17 @@ */ #include <common.h> +#include <dm.h> #include <fsl_validate.h> #include <fsl_secboot_err.h> #include <fsl_sfp.h> #include <fsl_sec.h> #include <command.h> #include <malloc.h> -#include <dm/uclass.h> #include <u-boot/rsa-mod-exp.h> #include <hash.h> #include <fsl_secboot_err.h> -#ifdef CONFIG_LS102XA +#ifdef CONFIG_ARCH_LS1021A #include <asm/arch/immap_ls102xa.h> #endif @@ -27,6 +27,10 @@ #define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \ ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \ ((key_len) == 2 * KEY_SIZE_BYTES)) +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +/* Global data structure */ +static struct fsl_secboot_glb glb; +#endif /* This array contains DER value for SHA-256 */ static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, @@ -60,7 +64,7 @@ self: #if defined(CONFIG_FSL_ISBC_KEY_EXT) static u32 check_ie(struct fsl_secboot_img_priv *img) { - if (img->hdr.ie_flag) + if (img->hdr.ie_flag & IE_FLAG_MASK) return 1; return 0; @@ -119,7 +123,21 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) } #endif -static int get_ie_info_addr(u32 *ie_addr) +#if defined(CONFIG_ESBC_HDR_LS) +static int get_ie_info_addr(uintptr_t *ie_addr) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + /* For LS-CH3, the address of IE Table is + * stated in Scratch13 and scratch14 of DCFG. + * Bootrom validates this table while validating uboot. + * DCFG is LE*/ + *ie_addr = in_le32(&gur->scratchrw[SCRATCH_IE_HIGH_ADR - 1]); + *ie_addr = *ie_addr << 32; + *ie_addr |= in_le32(&gur->scratchrw[SCRATCH_IE_LOW_ADR - 1]); + return 0; +} +#else /* CONFIG_ESBC_HDR_LS */ +static int get_ie_info_addr(uintptr_t *ie_addr) { struct fsl_secboot_img_hdr *hdr; struct fsl_secboot_sg_table *sg_tbl; @@ -147,16 +165,17 @@ static int get_ie_info_addr(u32 *ie_addr) /* IE Key Table is the first entry in the SG Table */ #if defined(CONFIG_MPC85xx) - *ie_addr = (sg_tbl->src_addr & ~(CONFIG_SYS_PBI_FLASH_BASE)) + - flash_base_addr; + *ie_addr = (uintptr_t)((sg_tbl->src_addr & + ~(CONFIG_SYS_PBI_FLASH_BASE)) + + flash_base_addr); #else - *ie_addr = sg_tbl->src_addr; + *ie_addr = (uintptr_t)sg_tbl->src_addr; #endif - debug("IE Table address is %x\n", *ie_addr); + debug("IE Table address is %lx\n", *ie_addr); return 0; } - +#endif /* CONFIG_ESBC_HDR_LS */ #endif #ifdef CONFIG_KEY_REVOCATION @@ -164,7 +183,10 @@ static int get_ie_info_addr(u32 *ie_addr) static u32 check_srk(struct fsl_secboot_img_priv *img) { #ifdef CONFIG_ESBC_HDR_LS - /* In LS, No SRK Flag as SRK is always present*/ + /* In LS, No SRK Flag as SRK is always present if IE not present*/ +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + return !check_ie(img); +#endif return 1; #else if (img->hdr.len_kr.srk_table_flag & SRK_FLAG) @@ -253,14 +275,29 @@ static u32 read_validate_single_key(struct fsl_secboot_img_priv *img) #endif /* CONFIG_ESBC_HDR_LS */ #if defined(CONFIG_FSL_ISBC_KEY_EXT) + +static void install_ie_tbl(uintptr_t ie_tbl_addr, + struct fsl_secboot_img_priv *img) +{ + /* Copy IE tbl to Global Data */ + memcpy(&glb.ie_tbl, (u8 *)ie_tbl_addr, sizeof(struct ie_key_info)); + img->ie_addr = (uintptr_t)&glb.ie_tbl; + glb.ie_addr = img->ie_addr; +} + static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img) { struct fsl_secboot_img_hdr *hdr = &img->hdr; u32 ie_key_len, ie_revoc_flag, ie_num; struct ie_key_info *ie_info; - if (get_ie_info_addr(&img->ie_addr)) - return ERROR_IE_TABLE_NOT_FOUND; + if (!img->ie_addr) { + if (get_ie_info_addr(&img->ie_addr)) + return ERROR_IE_TABLE_NOT_FOUND; + else + install_ie_tbl(img->ie_addr, img); + } + ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr; if (ie_info->num_keys == 0 || ie_info->num_keys > 32) return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; @@ -301,27 +338,15 @@ static inline u32 get_key_len(struct fsl_secboot_img_priv *img) */ static void fsl_secboot_header_verification_failure(void) { - struct ccsr_sec_mon_regs *sec_mon_regs = (void *) - (CONFIG_SYS_SEC_MON_ADDR); struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); - u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat); /* 29th bit of OSPR is ITS */ u32 its = sfp_in32(&sfp_regs->ospr) >> 2; - /* - * Read the SEC_MON status register - * Read SSM_ST field - */ - sts = sec_mon_in32(&sec_mon_regs->hp_stat); - if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) { - if (its == 1) - change_sec_mon_state(HPSR_SSM_ST_TRUST, - HPSR_SSM_ST_SOFT_FAIL); - else - change_sec_mon_state(HPSR_SSM_ST_TRUST, - HPSR_SSM_ST_NON_SECURE); - } + if (its == 1) + set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL); + else + set_sec_mon_state(HPSR_SSM_ST_NON_SECURE); printf("Generating reset request\n"); do_reset(NULL, 0, 0, NULL); @@ -338,32 +363,20 @@ static void fsl_secboot_header_verification_failure(void) */ static void fsl_secboot_image_verification_failure(void) { - struct ccsr_sec_mon_regs *sec_mon_regs = (void *) - (CONFIG_SYS_SEC_MON_ADDR); struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); - u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat); u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT; - /* - * Read the SEC_MON status register - * Read SSM_ST field - */ - sts = sec_mon_in32(&sec_mon_regs->hp_stat); - if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) { - if (its == 1) { - change_sec_mon_state(HPSR_SSM_ST_TRUST, - HPSR_SSM_ST_SOFT_FAIL); - - printf("Generating reset request\n"); - do_reset(NULL, 0, 0, NULL); - /* If reset doesn't coocur, halt execution */ - do_esbc_halt(NULL, 0, 0, NULL); - - } else { - change_sec_mon_state(HPSR_SSM_ST_TRUST, - HPSR_SSM_ST_NON_SECURE); - } + if (its == 1) { + set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL); + + printf("Generating reset request\n"); + do_reset(NULL, 0, 0, NULL); + /* If reset doesn't coocur, halt execution */ + do_esbc_halt(NULL, 0, 0, NULL); + + } else { + set_sec_mon_state(HPSR_SSM_ST_NON_SECURE); } } @@ -380,6 +393,7 @@ static void fsl_secboot_bootscript_parse_failure(void) */ void fsl_secboot_handle_error(int error) { +#ifndef CONFIG_SPL_BUILD const struct fsl_secboot_errcode *e; for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX; @@ -387,6 +401,9 @@ void fsl_secboot_handle_error(int error) if (e->errcode == error) printf("ERROR :: %x :: %s\n", error, e->name); } +#else + printf("ERROR :: %x\n", error); +#endif /* If Boot Mode is secure, transition the SNVS state and issue * reset based on type of failure and ITS setting. @@ -810,6 +827,26 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img) return 0; } +/* Function to initialize img priv and global data structure + */ +static int secboot_init(struct fsl_secboot_img_priv **img_ptr) +{ + *img_ptr = malloc(sizeof(struct fsl_secboot_img_priv)); + + struct fsl_secboot_img_priv *img = *img_ptr; + + if (!img) + return -ENOMEM; + memset(img, 0, sizeof(struct fsl_secboot_img_priv)); + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + if (glb.ie_addr) + img->ie_addr = glb.ie_addr; +#endif + return 0; +} + + /* haddr - Address of the header of image to be validated. * arg_hash_str - Option hash string. If provided, this * overrides the key hash in the SFP fuses. @@ -863,12 +900,9 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, hash_cmd = 1; } - img = malloc(sizeof(struct fsl_secboot_img_priv)); - - if (!img) - return -1; - - memset(img, 0, sizeof(struct fsl_secboot_img_priv)); + ret = secboot_init(&img); + if (ret) + goto exit; /* Update the information in Private Struct */ hdr = &img->hdr; @@ -923,5 +957,7 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, } exit: + /* Free Img as it was malloc'ed*/ + free(img); return ret; } diff --git a/board/freescale/common/mc34vr500.c b/board/freescale/common/mc34vr500.c new file mode 100644 index 0000000..9c57569 --- /dev/null +++ b/board/freescale/common/mc34vr500.c @@ -0,0 +1,95 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Hou Zhiqiang <Zhiqiang.Hou@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/mc34vr500_pmic.h> + +static uint8_t swxvolt_addr[4] = { MC34VR500_SW1VOLT, + MC34VR500_SW2VOLT, + MC34VR500_SW3VOLT, + MC34VR500_SW4VOLT }; + +static uint8_t swx_set_point_base[4] = { 13, 9, 9, 9 }; + +int mc34vr500_get_sw_volt(uint8_t sw) +{ + struct pmic *p; + u32 swxvolt; + uint8_t spb; + int sw_volt; + int ret; + + debug("%s: Get SW%u volt from swxvolt_addr = 0x%x\n", + __func__, sw + 1, swxvolt_addr[sw]); + if (sw > SW4) { + printf("%s: Unsupported SW(sw%d)\n", __func__, sw + 1); + return -EINVAL; + } + + p = pmic_get("MC34VR500"); + if (!p) { + printf("%s: Did NOT find PMIC MC34VR500\n", __func__); + return -ENODEV; + } + + ret = pmic_probe(p); + if (ret) + return ret; + + ret = pmic_reg_read(p, swxvolt_addr[sw], &swxvolt); + if (ret) { + printf("%s: Failed to get SW%u volt\n", __func__, sw + 1); + return ret; + } + + debug("%s: SW%d step point swxvolt = %u\n", __func__, sw + 1, swxvolt); + spb = swx_set_point_base[sw]; + /* The base of SW volt is 625mV and increase by step 25mV */ + sw_volt = 625 + (swxvolt - spb) * 25; + + debug("%s: SW%u volt = %dmV\n", __func__, sw + 1, sw_volt); + return sw_volt; +} + +int mc34vr500_set_sw_volt(uint8_t sw, int sw_volt) +{ + struct pmic *p; + u32 swxvolt; + uint8_t spb; + int ret; + + debug("%s: Set SW%u volt to %dmV\n", __func__, sw + 1, sw_volt); + /* The least SW volt is 625mV, and only 4 SW outputs */ + if (sw > SW4 || sw_volt < 625) + return -EINVAL; + + p = pmic_get("MC34VR500"); + if (!p) { + printf("%s: Did NOT find PMIC MC34VR500\n", __func__); + return -ENODEV; + } + + ret = pmic_probe(p); + if (ret) + return ret; + + spb = swx_set_point_base[sw]; + /* The base of SW volt is 625mV and increase by step 25mV */ + swxvolt = (sw_volt - 625) / 25 + spb; + debug("%s: SW%d step point swxvolt = %u\n", __func__, sw + 1, swxvolt); + if (swxvolt > 63) + return -EINVAL; + + ret = pmic_reg_write(p, swxvolt_addr[sw], swxvolt); + if (ret) + return ret; + + return 0; +} diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index 81c9211..0c3a54c 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -10,15 +10,15 @@ #include <asm/arch/ns_access.h> #include <asm/arch/fsl_serdes.h> -void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val) +void set_devices_ns_access(unsigned long index, u16 val) { u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR; u32 *reg; uint32_t tmp; - reg = base + ns_dev->ind / 2; + reg = base + index / 2; tmp = in_be32(reg); - if (ns_dev->ind % 2 == 0) { + if (index % 2 == 0) { tmp &= 0x0000ffff; tmp |= val << 16; } else { @@ -34,12 +34,15 @@ static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) int i; for (i = 0; i < num; i++) - set_devices_ns_access(ns_dev + i, ns_dev[i].val); + set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val); } void enable_layerscape_ns_access(void) { - enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#ifdef CONFIG_ARM64 + if (current_el() == 3) +#endif + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); } void set_pcie_ns_access(int pcie, u16 val) @@ -47,20 +50,20 @@ void set_pcie_ns_access(int pcie, u16 val) switch (pcie) { #ifdef CONFIG_PCIE1 case PCIE1: - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val); - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val); + set_devices_ns_access(CSU_CSLX_PCIE1, val); + set_devices_ns_access(CSU_CSLX_PCIE1_IO, val); return; #endif #ifdef CONFIG_PCIE2 case PCIE2: - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val); - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val); + set_devices_ns_access(CSU_CSLX_PCIE2, val); + set_devices_ns_access(CSU_CSLX_PCIE2_IO, val); return; #endif #ifdef CONFIG_PCIE3 case PCIE3: - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val); - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val); + set_devices_ns_access(CSU_CSLX_PCIE3, val); + set_devices_ns_access(CSU_CSLX_PCIE3_IO, val); return; #endif default: diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h index 9328404..e6e0f66 100644 --- a/board/freescale/common/pixis.h +++ b/board/freescale/common/pixis.h @@ -7,7 +7,7 @@ #define __PIXIS_H_ 1 /* PIXIS register set. */ -#if defined(CONFIG_MPC8536DS) +#if defined(CONFIG_TARGET_MPC8536DS) typedef struct pixis { u8 id; u8 ver; @@ -46,7 +46,7 @@ typedef struct pixis { u8 res2[4]; } __attribute__ ((packed)) pixis_t; -#elif defined(CONFIG_MPC8544DS) +#elif defined(CONFIG_TARGET_MPC8544DS) typedef struct pixis { u8 id; u8 ver; @@ -73,7 +73,7 @@ typedef struct pixis { u8 res2[34]; } __attribute__ ((packed)) pixis_t; -#elif defined(CONFIG_MPC8572DS) +#elif defined(CONFIG_TARGET_MPC8572DS) typedef struct pixis { u8 id; u8 ver; @@ -102,7 +102,7 @@ typedef struct pixis { u8 res4[25]; } __attribute__ ((packed)) pixis_t; -#elif defined(CONFIG_MPC8610HPCD) +#elif defined(CONFIG_TARGET_MPC8610HPCD) typedef struct pixis { u8 id; u8 ver; /* also called arch */ @@ -132,7 +132,7 @@ typedef struct pixis { u8 res4[33]; } __attribute__ ((packed)) pixis_t; -#elif defined(CONFIG_MPC8641HPCN) +#elif defined(CONFIG_TARGET_MPC8641HPCN) typedef struct pixis { u8 id; u8 ver; diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c index 1eb3786..d152a78 100644 --- a/board/freescale/common/pq-mds-pib.c +++ b/board/freescale/common/pq-mds-pib.c @@ -63,7 +63,7 @@ int pib_init(void) #endif #if defined(CONFIG_PQ_MDS_PIB_ATM) -#if defined(CONFIG_MPC8569MDS) +#if defined(CONFIG_TARGET_MPC8569MDS) val8 = 0; i2c_write(0x20, 0x6, 1, &val8, 1); i2c_write(0x20, 0x7, 1, &val8, 1); diff --git a/board/freescale/common/spl.h b/board/freescale/common/spl.h new file mode 100644 index 0000000..88c987e --- /dev/null +++ b/board/freescale/common/spl.h @@ -0,0 +1,13 @@ +/* + * Copyright 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FREESCALE_BOARD_SPL_H +#define __FREESCALE_BOARD_SPL_H + +void fsl_spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst); +void fsl_spi_boot(void) __noreturn; + +#endif diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 1a50304..9b65c13 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -284,10 +284,170 @@ static int set_voltage(int i2caddress, int vdd) return vdd_last; } +#ifdef CONFIG_FSL_LSCH3 int adjust_vdd(ulong vdd_override) { int re_enable = disable_interrupts(); -#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 fusesr; + u8 vid, buf; + int vdd_target, vdd_current, vdd_last; + int ret, i2caddress; + unsigned long vdd_string_override; + char *vdd_string; + static const uint16_t vdd[32] = { + 10500, + 0, /* reserved */ + 9750, + 0, /* reserved */ + 9500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 10000, /* 1.0000V */ + 0, /* reserved */ + 10250, + 0, /* reserved */ + 10500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + }; + struct vdd_drive { + u8 vid; + unsigned voltage; + }; + + ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); + if (ret) { + debug("VID: I2C failed to switch channel\n"); + ret = -1; + goto exit; + } + ret = find_ir_chip_on_i2c(); + if (ret < 0) { + printf("VID: Could not find voltage regulator on I2C.\n"); + ret = -1; + goto exit; + } else { + i2caddress = ret; + debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); + } + + /* check IR chip work on Intel mode*/ + ret = i2c_read(i2caddress, + IR36021_INTEL_MODE_OOFSET, + 1, (void *)&buf, 1); + if (ret) { + printf("VID: failed to read IR chip mode.\n"); + ret = -1; + goto exit; + } + if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) { + printf("VID: IR Chip is not used in Intel mode.\n"); + ret = -1; + goto exit; + } + + /* get the voltage ID from fuse status register */ + fusesr = in_le32(&gur->dcfg_fusesr); + vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; + if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { + vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & + FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; + } + vdd_target = vdd[vid]; + + /* check override variable for overriding VDD */ + vdd_string = getenv(CONFIG_VID_FLS_ENV); + if (vdd_override == 0 && vdd_string && + !strict_strtoul(vdd_string, 10, &vdd_string_override)) + vdd_override = vdd_string_override; + + if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) { + vdd_target = vdd_override * 10; /* convert to 1/10 mV */ + debug("VDD override is %lu\n", vdd_override); + } else if (vdd_override != 0) { + printf("Invalid value.\n"); + } + + /* divide and round up by 10 to get a value in mV */ + vdd_target = DIV_ROUND_UP(vdd_target, 10); + if (vdd_target == 0) { + debug("VID: VID not used\n"); + ret = 0; + goto exit; + } else if (vdd_target < VDD_MV_MIN || vdd_target > VDD_MV_MAX) { + /* Check vdd_target is in valid range */ + printf("VID: Target VID %d mV is not in range.\n", + vdd_target); + ret = -1; + goto exit; + } else { + debug("VID: vid = %d mV\n", vdd_target); + } + + /* + * Read voltage monitor to check real voltage. + */ + vdd_last = read_voltage(i2caddress); + if (vdd_last < 0) { + printf("VID: Couldn't read sensor abort VID adjustment\n"); + ret = -1; + goto exit; + } + vdd_current = vdd_last; + debug("VID: Core voltage is currently at %d mV\n", vdd_last); + /* + * Adjust voltage to at or one step above target. + * As measurements are less precise than setting the values + * we may run through dummy steps that cancel each other + * when stepping up and then down. + */ + while (vdd_last > 0 && + vdd_last < vdd_target) { + vdd_current += IR_VDD_STEP_UP; + vdd_last = set_voltage(i2caddress, vdd_current); + } + while (vdd_last > 0 && + vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) { + vdd_current -= IR_VDD_STEP_DOWN; + vdd_last = set_voltage(i2caddress, vdd_current); + } + + if (vdd_last > 0) + printf("VID: Core voltage after adjustment is at %d mV\n", + vdd_last); + else + ret = -1; +exit: + if (re_enable) + enable_interrupts(); + i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); + return ret; +} +#else /* !CONFIG_FSL_LSCH3 */ +int adjust_vdd(ulong vdd_override) +{ + int re_enable = disable_interrupts(); +#if defined(CONFIG_FSL_LSCH2) struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); #else ccsr_gur_t __iomem *gur = @@ -364,11 +524,7 @@ int adjust_vdd(ulong vdd_override) } /* get the voltage ID from fuse status register */ -#ifdef CONFIG_FSL_LSCH3 - fusesr = in_le32(&gur->dcfg_fusesr); -#else fusesr = in_be32(&gur->dcfg_fusesr); -#endif /* * VID is used according to the table below * --------------------------------------- @@ -393,13 +549,6 @@ int adjust_vdd(ulong vdd_override) vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; } -#elif defined(CONFIG_FSL_LSCH3) - vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & - FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; - if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { - vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & - FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; - } #else vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; @@ -472,6 +621,7 @@ exit: return ret; } +#endif static int print_vdd(void) { diff --git a/board/freescale/common/zm7300.c b/board/freescale/common/zm7300.c index be5953a..a6c3e69 100644 --- a/board/freescale/common/zm7300.c +++ b/board/freescale/common/zm7300.c @@ -140,9 +140,7 @@ int dpm_wrp(u8 r, u8 d) /* Uses the DPM command RRP */ u8 zm_read(uchar reg) { - u8 d; - d = dpm_rrp(reg); - return d; + return dpm_rrp(reg); } /* ZM_write -- |