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-rw-r--r--board/ns9750dev/Makefile47
-rw-r--r--board/ns9750dev/config.mk16
-rw-r--r--board/ns9750dev/flash.c477
-rw-r--r--board/ns9750dev/led.c46
-rw-r--r--board/ns9750dev/ns9750dev.c127
-rw-r--r--board/ns9750dev/platform.S298
-rw-r--r--board/ns9750dev/u-boot.lds58
7 files changed, 1069 insertions, 0 deletions
diff --git a/board/ns9750dev/Makefile b/board/ns9750dev/Makefile
new file mode 100644
index 0000000..d2718cc
--- /dev/null
+++ b/board/ns9750dev/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := ns9750dev.o flash.o led.o
+SOBJS := platform.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/ns9750dev/config.mk b/board/ns9750dev/config.mk
new file mode 100644
index 0000000..6a22cee
--- /dev/null
+++ b/board/ns9750dev/config.mk
@@ -0,0 +1,16 @@
+#######################################################################
+#
+# Copyright (C) 2004 by FS Forth-Systeme GmbH.
+# Markus Pietrek <mpietrek@fsforth.de>
+#
+# @TODO
+# Linux-Kernel is expected to be at 0000'8000, entry 0000'8000
+# optionally with a ramdisk at 0080'0000
+#
+# we load ourself to 0078'0000
+#
+# download area is 0060'0000
+#
+
+
+TEXT_BASE = 0x00780000
diff --git a/board/ns9750dev/flash.c b/board/ns9750dev/flash.c
new file mode 100644
index 0000000..e7d6515
--- /dev/null
+++ b/board/ns9750dev/flash.c
@@ -0,0 +1,477 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH ushort
+#define FLASH_PORT_WIDTHV vu_short
+#define SWAP(x) __swab16(x)
+#else
+#define FLASH_PORT_WIDTH ulong
+#define FLASH_PORT_WIDTHV vu_long
+#define SWAP(x) __swab32(x)
+#endif
+
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+
+/* Flash Organization Structure */
+typedef struct OrgDef {
+ unsigned int sector_number;
+ unsigned int sector_size;
+} OrgDef;
+
+
+/* Flash Organizations */
+OrgDef OrgIntel_28F256L18T[] = {
+ {4, 32 * 1024}, /* 4 * 32kBytes sectors */
+ {255, 128 * 1024}, /* 255 * 128kBytes sectors */
+};
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+unsigned long flash_init (void);
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+void flash_print_info (flash_info_t * info);
+void flash_unprotect_sectors (FPWV * addr);
+int flash_erase (flash_info_t * info, int s_first, int s_last);
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ int i;
+ ulong size = 0;
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ switch (i) {
+ case 0:
+ flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+ flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+ break;
+ default:
+ panic ("configured too many flash banks!\n");
+ break;
+ }
+ size += flash_info[i].size;
+ }
+
+ /* Protect monitor and environment sectors
+ */
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+ int i;
+ OrgDef *pOrgDef;
+
+ pOrgDef = OrgIntel_28F256L18T;
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+ for (i = 0; i < info->sector_count; i++) {
+ if (i > 255) {
+ info->start[i] = base + (i * 0x8000);
+ info->protect[i] = 0;
+ } else {
+ info->start[i] = base +
+ (i * PHYS_FLASH_SECT_SIZE);
+ info->protect[i] = 0;
+ }
+ }
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL:
+ printf ("INTEL ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F256L18T:
+ printf ("FLASH 28F256L18T\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i], info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+ return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+ volatile FPW value;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr[0x5555] = (FPW) 0x00AA00AA;
+ addr[0x2AAA] = (FPW) 0x00550055;
+ addr[0x5555] = (FPW) 0x00900090;
+
+ mb ();
+ value = addr[0];
+
+ switch (value) {
+
+ case (FPW) INTEL_MANUFACT:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
+ return (0); /* no or unknown flash */
+ }
+
+ mb ();
+ value = addr[1]; /* device ID */
+ switch (value) {
+
+ case (FPW) (INTEL_ID_28F256L18T):
+ info->flash_id += FLASH_28F256L18T;
+ info->sector_count = 259;
+ info->size = 0x02000000;
+ break; /* => 32 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ break;
+ }
+
+ if (info->sector_count > CFG_MAX_FLASH_SECT) {
+ printf ("** ERROR: sector count %d > max (%d) **\n",
+ info->sector_count, CFG_MAX_FLASH_SECT);
+ info->sector_count = CFG_MAX_FLASH_SECT;
+ }
+
+ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
+
+ return (info->size);
+}
+
+
+/* unprotects a sector for write and erase
+ * on some intel parts, this unprotects the entire chip, but it
+ * wont hurt to call this additional times per sector...
+ */
+void flash_unprotect_sectors (FPWV * addr)
+{
+#define PD_FINTEL_WSMS_READY_MASK 0x0080
+
+ *addr = (FPW) 0x00500050; /* clear status register */
+
+ /* this sends the clear lock bit command */
+ *addr = (FPW) 0x00600060;
+ *addr = (FPW) 0x00D000D0;
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong type, start, last;
+ int rcode = 0;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ type = (info->flash_id & FLASH_VENDMASK);
+ if ((type != FLASH_MAN_INTEL)) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+
+ start = get_timer (0);
+ last = start;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ FPWV *addr = (FPWV *) (info->start[sect]);
+ FPW status;
+
+ printf ("Erasing sector %2d ... ", sect);
+
+ flash_unprotect_sectors (addr);
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ *addr = (FPW) 0x00500050;/* clear status register */
+ *addr = (FPW) 0x00200020;/* erase setup */
+ *addr = (FPW) 0x00D000D0;/* erase confirm */
+
+ while (((status =
+ *addr) & (FPW) 0x00800080) !=
+ (FPW) 0x00800080) {
+ if (get_timer_masked () >
+ CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ /* suspend erase */
+ *addr = (FPW) 0x00B000B0;
+ /* reset to read mode */
+ *addr = (FPW) 0x00FF00FF;
+ rcode = 1;
+ break;
+ }
+ }
+
+ /* clear status register cmd. */
+ *addr = (FPW) 0x00500050;
+ *addr = (FPW) 0x00FF00FF;/* resest to read mode */
+ printf (" done\n");
+ }
+ }
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ FPW data;
+ int count, i, l, rc, port_width;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return 4;
+ }
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+ wp = (addr & ~1);
+ port_width = 2;
+#else
+ wp = (addr & ~3);
+ port_width = 4;
+#endif
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < port_width && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ count = 0;
+ while (cnt >= port_width) {
+ data = 0;
+ for (i = 0; i < port_width; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ cnt -= port_width;
+ if (count++ > 0x800) {
+ spin_wheel ();
+ count = 0;
+ }
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+ FPWV *addr = (FPWV *) dest;
+ ulong status;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+ return (2);
+ }
+ flash_unprotect_sectors (addr);
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+ *addr = (FPW) 0x00400040; /* write setup */
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ /* wait while polling the status register */
+ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+ if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+ *addr = (FPW) 0x00FF00FF; /* restore read mode */
+ return (1);
+ }
+ }
+ *addr = (FPW) 0x00FF00FF; /* restore read mode */
+ return (0);
+}
+
+void inline spin_wheel (void)
+{
+ static int p = 0;
+ static char w[] = "\\/-";
+
+ printf ("\010%c", w[p]);
+ (++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/ns9750dev/led.c b/board/ns9750dev/led.c
new file mode 100644
index 0000000..ab27f7b
--- /dev/null
+++ b/board/ns9750dev/led.c
@@ -0,0 +1,46 @@
+/***********************************************************************
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ *
+ * $Id: led.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
+ * @Author: Markus Pietrek
+ * @Descr: Defines helper functions for toggeling LEDs
+ * @Usage:
+ * @References: [1]
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ***********************************************************************/
+
+#ifdef CONFIG_STATUS_LED
+
+#include <ns9750_bbus.h>
+
+static inline void __led_init( led_id_t mask, int state )
+{
+ XXXX;
+}
+
+static inline void __led_toggle( led_id_t mask )
+{
+}
+
+static inline void __led_set( led_id_t mask, int state )
+{
+}
+
+#endif /* CONFIG_STATUS_LED */
diff --git a/board/ns9750dev/ns9750dev.c b/board/ns9750dev/ns9750dev.c
new file mode 100644
index 0000000..0ea89a5
--- /dev/null
+++ b/board/ns9750dev/ns9750dev.c
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ * Markus Pietrek <mpietrek@fsforth.de>
+ * derived from omap1610innovator.c
+ * @References: [1] NS9750 Hardware Reference/December 2003
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_NS9750DEV)
+# include <./configs/ns9750dev.h>
+# include <./ns9750_bbus.h>
+#endif
+
+void flash__init( void );
+void ether__init( void );
+
+static inline void delay( unsigned long loops )
+{
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+}
+
+
+/***********************************************************************
+ * @Function: board_init
+ * @Return: 0
+ * @Descr: Enables BBUS modules and other devices
+ ***********************************************************************/
+
+int board_init( void )
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* Active BBUS modules */
+ *get_bbus_reg_addr( NS9750_BBUS_MASTER_RESET ) = 0;
+
+#warning TODO check numbers
+ /* arch number of OMAP 1510-Board */
+ /* to be changed for OMAP 1610 Board */
+ gd->bd->bi_arch_number = 234;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x10000100;
+
+
+/* this speeds up your boot a quite a bit. However to make it
+ * work, you need make sure your kernel startup flush bug is fixed.
+ * ... rkw ...
+ */
+ icache_enable();
+
+ flash__init();
+ ether__init();
+ return 0;
+}
+
+
+int misc_init_r (void)
+{
+ /* currently empty */
+ return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+void flash__init (void)
+{
+}
+/*************************************************************
+ Routine:ether__init
+ Description: take the Ethernet controller out of reset and wait
+ for the EEPROM load to complete.
+*************************************************************/
+void ether__init (void)
+{
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+#if CONFIG_NR_DRAM_BANKS > 1
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+ return 0;
+}
diff --git a/board/ns9750dev/platform.S b/board/ns9750dev/platform.S
new file mode 100644
index 0000000..11f9aef
--- /dev/null
+++ b/board/ns9750dev/platform.S
@@ -0,0 +1,298 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for the NS9750 DevBoard by
+ * (C) Copyright 2004 by FS Forth-Systeme GmbH.
+ * Markus Pietrek <mpietrek@fsforth.de>
+ * @References: [1] NS9750 Hardware Reference/December 2003
+ * [2] ns9750_a.cmd from MAJIC configuration
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#if defined(CONFIG_NS9750DEV)
+# ifdef CONFIG_INIT_CRITICAL
+# include <./ns9750_sys.h>
+# include <./ns9750_mem.h>
+# endif
+#endif
+
+/***********************************************************************
+ * @Function: write_register_block
+ * @Return: nothing
+ * @Descr: Copies the register block of register_offset:register value to
+ * the registers at base r0. The block is assumed to start in RAM at r1
+ * and end at r2. The linked RAM base address of U-Boot is assumed to be
+ * in r5 while the ROM base address we are running from is r6
+ * Uses r3 and r4 as tempory registers
+ ***********************************************************************/
+
+.macro write_register_block
+ @@ map the addresses to high memory
+ sub r1, r1, r5
+ add r1, r1, r6
+ sub r2, r2, r5
+ add r2, r2, r6
+
+ @@ copy all
+1:
+ @@ Write register/value pair starting at [r1] to register base r0
+ ldr r3, [r1], #4
+ ldr r4, [r1], #4
+ str r4, [r0,r3]
+ cmp r1, r2
+ blt 1b
+.endm
+
+_TEXT_BASE:
+ .word TEXT_BASE @ sdram load addr from config.mk
+_PHYS_FLASH:
+ .word PHYS_FLASH_1 @ real flash address (without mirroring)
+_CAS_LATENCY:
+ .word 0x00022000 @ for CAS2 latency
+
+#ifdef CONFIG_INIT_CRITICAL
+.globl platformsetup
+platformsetup:
+
+ /* U-Boot may be linked to RAM at 0x780000. But this code will run in
+ flash from 0x0. But in order to enable RAM we have to disable the
+ mirror bit, therefore we have to jump to our real flash address
+ beginning at PHYS_FLASH_1 (CS4 Base). Therefore,
+ _run_at_real_flash_address may be 0x500003b0 while be linked to
+ 0x7803b0. So we must modify our linked addresses */
+
+ @@ branch to high memory address, away from 0x0
+ ldr r5, _TEXT_BASE
+ ldr r6, _PHYS_FLASH
+ ldr r0, =_run_at_real_flash_address
+ sub r0, r0, r5
+ add r0, r0, r6
+ mov pc, r0
+ nop @ for pipelining
+
+_run_at_real_flash_address:
+ @@ now we are running > PHYS_FLASH_1, safe to enable memory controller
+
+ @@ Write Memory Configuration Registers
+
+ ldr r0, _NS9750_MEM_MODULE_BASE
+ ldr r1, =_MEM_CONFIG_START
+ ldr r2, =_MEM_CONFIG_END
+
+ write_register_block
+
+ @@ Give SDRAM some time to settle
+ @@ @TODO. According to [2] it should be 2 AHB cycles. Check
+
+ ldr r1, =0x50
+_sdram_settle:
+ subs r1, r1, #1
+ bne _sdram_settle
+
+_enable_mappings:
+ @@ Enable SDRAM Mode
+
+ ldr r1, =_MEM_MODE_START
+ ldr r2, =_MEM_MODE_END
+
+ write_register_block
+
+ ldr r3, _CAS_LATENCY @ perform one read from SDRAM
+ ldr r3, [r3]
+
+ @@ Enable SDRAM and memory mappings
+
+ ldr r1, =_MEM_ENABLE_START
+ ldr r2, =_MEM_ENABLE_END
+
+ write_register_block
+
+ @@ Activate AHB monitor
+
+ ldr r0, =NS9750_SYS_MODULE_BASE
+ ldr r1, =_AHB_MONITOR_START
+ ldr r2, =_AHB_MONITOR_END
+
+ write_register_block
+_relocate_lr:
+ /* lr and ip (from cpu_init_crit) are still based on 0x0, relocate it to
+ PHYS_FLASH. */
+ mov r1, ip
+ add r1, r1, r6
+ mov ip, r1
+
+ mov r1, lr
+ add r1, r1, r6
+ mov lr, r1
+
+ @@ back to arch calling code
+ mov pc, lr
+
+ .ltorg
+
+_NS9750_MEM_MODULE_BASE:
+ .word NS9750_MEM_MODULE_BASE
+
+_MEM_CONFIG_START:
+ /* Table of 2 32bit entries. First word is register address offset
+ relative to NS9750_MEM_MODULE_BASE, second one is value. They are
+ written in order of appearance */
+
+ @@ Register values taken from [2]
+ .word NS9750_MEM_CTRL
+ .word NS9750_MEM_CTRL_E
+
+ .word NS9750_MEM_DYN_REFRESH
+ .word (0x6 & NS9750_MEM_DYN_REFRESH_MA)
+
+ .word NS9750_MEM_DYN_READ_CFG
+ .word (0x1 & NS9750_MEM_DYN_READ_CFG_MA)
+
+ .word NS9750_MEM_DYN_TRP
+ .word (0x1 & NS9750_MEM_DYN_TRP_MA)
+
+ .word NS9750_MEM_DYN_TRAS
+ .word (0x4 & NS9750_MEM_DYN_TRAS_MA)
+
+ .word NS9750_MEM_DYN_TAPR
+ .word (0x1 & NS9750_MEM_DYN_TRAS_MA)
+
+ .word NS9750_MEM_DYN_TDAL
+ .word (0x5 & NS9750_MEM_DYN_TDAL_MA)
+
+ .word NS9750_MEM_DYN_TWR
+ .word (0x1 & NS9750_MEM_DYN_TWR_MA)
+
+ .word NS9750_MEM_DYN_TRC
+ .word (0x6 & NS9750_MEM_DYN_TRC_MA)
+
+ .word NS9750_MEM_DYN_TRFC
+ .word (0x6 & NS9750_MEM_DYN_TRFC_MA)
+
+ .word NS9750_MEM_DYN_TRRD
+ .word (0x1 & NS9750_MEM_DYN_TRRD_MA)
+
+ .word NS9750_MEM_DYN_TMRD
+ .word (0x1 & NS9750_MEM_DYN_TMRD_MA)
+
+ @@ CS 4
+ .word NS9750_MEM_DYN_CFG(0)
+ .word (NS9750_MEM_DYN_CFG_AM | \
+ (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+ .word NS9750_MEM_DYN_RAS_CAS(0)
+ .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
+ (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
+
+ @@ CS 5
+ .word NS9750_MEM_DYN_CFG(1)
+ .word (NS9750_MEM_DYN_CFG_AM | \
+ (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+ .word NS9750_MEM_DYN_RAS_CAS(1)
+ .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
+ (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
+
+ @@ CS 6
+ .word NS9750_MEM_DYN_CFG(2)
+ .word (NS9750_MEM_DYN_CFG_AM | \
+ (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+ .word NS9750_MEM_DYN_RAS_CAS(2)
+ .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
+ (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
+
+ @@ CS 7
+ .word NS9750_MEM_DYN_CFG(3)
+ .word (NS9750_MEM_DYN_CFG_AM | \
+ (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+ .word NS9750_MEM_DYN_RAS_CAS(3)
+ .word ((0x200 & NS9750_MEM_DYN_RAS_CAS_CAS_MA) | \
+ (0x03 & NS9750_MEM_DYN_RAS_CAS_RAS_MA))
+
+ .word NS9750_MEM_DYN_CTRL
+ .word (NS9750_MEM_DYN_CTRL_I_PALL | \
+ NS9750_MEM_DYN_CTRL_SR | \
+ NS9750_MEM_DYN_CTRL_CE )
+
+ .word NS9750_MEM_DYN_REFRESH
+ .word (0x1 & NS9750_MEM_DYN_REFRESH_MA)
+ @@ No further register settings after refresh
+_MEM_CONFIG_END:
+
+_MEM_MODE_START:
+ .word NS9750_MEM_DYN_REFRESH
+ .word (0x30 & NS9750_MEM_DYN_REFRESH_MA)
+
+ .word NS9750_MEM_DYN_CTRL
+ .word (NS9750_MEM_DYN_CTRL_I_MODE | \
+ NS9750_MEM_DYN_CTRL_SR | \
+ NS9750_MEM_DYN_CTRL_CE )
+_MEM_MODE_END:
+
+_MEM_ENABLE_START:
+ .word NS9750_MEM_DYN_CTRL
+ .word (NS9750_MEM_DYN_CTRL_I_NORMAL | \
+ NS9750_MEM_DYN_CTRL_SR | \
+ NS9750_MEM_DYN_CTRL_CE )
+
+ @@ CS 4
+ .word NS9750_MEM_DYN_CFG(0)
+ .word (NS9750_MEM_DYN_CFG_BDMC | \
+ NS9750_MEM_DYN_CFG_AM | \
+ (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+ @@ CS 5
+ .word NS9750_MEM_DYN_CFG(1)
+ .word (NS9750_MEM_DYN_CFG_BDMC | \
+ NS9750_MEM_DYN_CFG_AM | \
+ (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+ @@ CS 6
+ .word NS9750_MEM_DYN_CFG(2)
+ .word (NS9750_MEM_DYN_CFG_BDMC | \
+ NS9750_MEM_DYN_CFG_AM | \
+ (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+
+ @@ CS 7
+ .word NS9750_MEM_DYN_CFG(3)
+ .word (NS9750_MEM_DYN_CFG_BDMC | \
+ NS9750_MEM_DYN_CFG_AM | \
+ (0x280 & NS9750_MEM_DYN_CFG_AM_MA))
+_MEM_ENABLE_END:
+
+_AHB_MONITOR_START:
+ .word NS9750_SYS_AHB_TIMEOUT
+ .word 0x01000100 @ @TODO not calculated yet
+
+ .word NS9750_SYS_AHB_MON
+ .word (NS9750_SYS_AHB_MON_BMTC_GEN_IRQ | \
+ NS9750_SYS_AHB_MON_BATC_GEN_IRQ)
+_AHB_MONITOR_END:
+
+#endif /* CONFIG_INIT_CRITICAL */
diff --git a/board/ns9750dev/u-boot.lds b/board/ns9750dev/u-boot.lds
new file mode 100644
index 0000000..8a05892
--- /dev/null
+++ b/board/ns9750dev/u-boot.lds
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm926ejs/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = . ;
+
+}