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Diffstat (limited to 'board/scalys/simc-t10xx/ddr.c')
-rw-r--r--board/scalys/simc-t10xx/ddr.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/board/scalys/simc-t10xx/ddr.c b/board/scalys/simc-t10xx/ddr.c
index f6d04ac..7fed0d2 100644
--- a/board/scalys/simc-t10xx/ddr.c
+++ b/board/scalys/simc-t10xx/ddr.c
@@ -1,24 +1,19 @@
/*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
* opensource@scalys.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <asm/mmu.h>
-//#include <asm/gpio.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
-//#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
/* MT41K512M8RH-125 */
dimm_params_t ddr_raw_timing = {
@@ -45,7 +40,7 @@ dimm_params_t ddr_raw_timing = {
.tfaw_ps = 30000,
.twr_ps = 15000,
.trfc_ps = 260000,
- .trrd_ps = 6000,
+ .trrd_ps = 5000, //1Kb page size!
.twtr_ps = 7500,
.trtp_ps = 7500,
.refresh_rate_ps = 70200000,
@@ -90,6 +85,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
/* Clock is launched 1/2 applied cycle after address/command */
popts->clk_adjust = 8;
+
+ /* Optimized cpo */
+ popts->cpo_sample = 0x46;
}
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
@@ -108,7 +106,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
return 0;
}
-phys_size_t initdram(int board_type)
+int dram_init(void)
{
phys_size_t dram_size;
@@ -142,5 +140,7 @@ phys_size_t initdram(int board_type)
dram_size = fsl_ddr_sdram_size();
#endif
- return dram_size;
+ gd->ram_size = dram_size;
+
+ return 0;
}