diff options
Diffstat (limited to 'board/scalys/simc-t10xx/ddr.c')
| -rw-r--r-- | board/scalys/simc-t10xx/ddr.c | 39 |
1 files changed, 25 insertions, 14 deletions
diff --git a/board/scalys/simc-t10xx/ddr.c b/board/scalys/simc-t10xx/ddr.c index ca5407e..f6d04ac 100644 --- a/board/scalys/simc-t10xx/ddr.c +++ b/board/scalys/simc-t10xx/ddr.c @@ -7,7 +7,7 @@ #include <common.h> #include <asm/mmu.h> -#include <asm/gpio.h> +//#include <asm/gpio.h> #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> @@ -18,10 +18,7 @@ #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> #include <asm/fsl_law.h> -#include <asm/mpc8xxx_gpio.h> - -/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */ -#define DDR_RST_N MPC8XXX_GPIO_NR(2, 12) +//#include <asm/gpio.h> /* MT41K512M8RH-125 */ dimm_params_t ddr_raw_timing = { @@ -91,8 +88,8 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->ddr_cdr1 = 0x800c0000; popts->ddr_cdr2 = 0x00000001; - /* Clock is launched 1/4 applied cycle after address/command */ - popts->clk_adjust = 4; + /* Clock is launched 1/2 applied cycle after address/command */ + popts->clk_adjust = 8; } int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, @@ -114,15 +111,29 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, phys_size_t initdram(int board_type) { phys_size_t dram_size; - + #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + uint32_t regval; + + /* Remove reset of DDR using GPIO pin. We do this manually since + * we have not yet access to the DM gpio at this time */ + /* DDR_RST_N => IFC_CS3_B => GPIO2_12 */ + +#define CONFIG_SYS_MPC85XX_GPIO2_ADDR (CONFIG_SYS_IMMR + 0x131000) +#define DDR_RST_N (12) +/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */ +/* #define DDR_RST_N MPC85XX_GPIO_NR(2, 12) */ -#ifdef GPIO_IN_SPL_WORKING - gpio_request(DDR_RST_N, "DDR_RST_N"); - gpio_direction_output(DDR_RST_N, 1); -#else - mpc8xxx_gpio_set(DDR_RST_N,1); -#endif + /* Set output */ + regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8); + regval |= (0x80000000 >> 12); + out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8, regval); + + /* Set direction to acivate gpio pin */ + regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR); + regval |= (0x80000000 >> 12); + out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR, regval); + dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; |