diff options
Diffstat (limited to 'board/scalys/simc-t10xx/ddr_QT1040-1GB.c')
| -rw-r--r-- | board/scalys/simc-t10xx/ddr_QT1040-1GB.c | 173 |
1 files changed, 173 insertions, 0 deletions
diff --git a/board/scalys/simc-t10xx/ddr_QT1040-1GB.c b/board/scalys/simc-t10xx/ddr_QT1040-1GB.c new file mode 100644 index 0000000..e4fdcf6 --- /dev/null +++ b/board/scalys/simc-t10xx/ddr_QT1040-1GB.c @@ -0,0 +1,173 @@ +/* + * Copyright 2017 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <hwconfig.h> +#include <asm/mmu.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> +#include <asm/fsl_law.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Values for QT1040 */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .device_width = 16, + .primary_sdram_width = 64, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 14, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 2, + .burst_lengths_bitmask = 0x0c, + .tckmin_x_ps = 1250, + .caslat_x = (0x7fe << 4), + .taa_ps = 13750, + .twr_ps = 15000, + .trcd_ps = 13750, + .trrd_ps = 7500, + .trp_ps = 13750, + .tras_ps = 37500, + .trc_ps = 50600, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 3900000, + .tfaw_ps = 50000, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + int i; + + if (ctrl_num != 0) { + printf("Only 1 memory controller supported, but %i requested\n", + ctrl_num); + return; + } + + if (pdimm == NULL ) { + printf("Error, no valid dimm pararmeter supplied\n"); + return; + } + + if (!pdimm->n_ranks) { + printf("No ranks in dimm parameters. Configuration error?\n"); + return; + } + + /* DDR speed is fixed in the RCW */ + + /* set odt_rd_cfg and odt_wr_cfg. */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_wr_cfg = 4; + } + + popts->half_strength_driver_enable = 0; /* */ + + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 5; + popts->wrlvl_ctl_2 = 0x05050506; + popts->wrlvl_ctl_3 = 0x06060605; /* 1333MT/s */ + + popts->ddr_cdr1 = 0x800c0000; + popts->ddr_cdr2 = 0x00000001; + + /* + * rtt and rtt_wr override + */ + popts->rtt_override = 0; /* */ + + /* Enable ZQ calibration */ + popts->zq_en = 1; /* */ + + /* Clock is launched 1/2 applied cycle after address/command */ + popts->clk_adjust = 4; + + /* Optimized cpo */ + popts->cpo_sample = 0x33; +} + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Soldered-down discrete DDR3"; + + if (((controller_number == 0) && (dimm_number == 0)) || + ((controller_number == 1) && (dimm_number == 0))) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +int test123(void){ + { + volatile int waitforme = 0; + + while (waitforme) { + asm volatile ("nop"); + } + } + return 0; +} + + +int dram_init(void) +{ + phys_size_t dram_size; + +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) + uint32_t regval; + + /* Remove reset of DDR using GPIO pin. We do this manually since + * we have not yet access to the DM gpio at this time */ + /* DDR_RST_N => IFC_CS3_B => GPIO2_12 */ + +#define CONFIG_SYS_MPC85XX_GPIO2_ADDR (CONFIG_SYS_IMMR + 0x131000) +#define DDR_RST_N (12) +/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */ +/* #define DDR_RST_N MPC85XX_GPIO_NR(2, 12) */ + + /* Set output */ + regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8); + regval |= (0x80000000 >> 12); + out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8, regval); + + /* Set direction to acivate gpio pin */ + regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR); + regval |= (0x80000000 >> 12); + out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR, regval); + + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; +#else + /* DDR has been initialised by SPL loader */ + dram_size = fsl_ddr_sdram_size(); +#endif + + test123(); + + gd->ram_size = dram_size; + + return 0; +} + |