diff options
Diffstat (limited to 'board/scalys/simc-t10xx/ddr_QT1040-1GB.c')
| -rw-r--r-- | board/scalys/simc-t10xx/ddr_QT1040-1GB.c | 43 |
1 files changed, 4 insertions, 39 deletions
diff --git a/board/scalys/simc-t10xx/ddr_QT1040-1GB.c b/board/scalys/simc-t10xx/ddr_QT1040-1GB.c index e4fdcf6..8a4ebbe 100644 --- a/board/scalys/simc-t10xx/ddr_QT1040-1GB.c +++ b/board/scalys/simc-t10xx/ddr_QT1040-1GB.c @@ -1,5 +1,5 @@ /* - * Copyright 2017 Scalys B.V. + * Copyright 2020 Scalys B.V. * opensource@scalys.com * * SPDX-License-Identifier: GPL-2.0+ @@ -106,56 +106,23 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, unsigned int controller_number, unsigned int dimm_number) { - const char dimm_model[] = "Soldered-down discrete DDR3"; + const char dimm_model[] = "Soldered DDR3L"; if (((controller_number == 0) && (dimm_number == 0)) || ((controller_number == 1) && (dimm_number == 0))) { memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + memcpy(pdimm->mpart, dimm_model, sizeof(pdimm->mpart) - 1); } return 0; } -int test123(void){ - { - volatile int waitforme = 0; - - while (waitforme) { - asm volatile ("nop"); - } - } - return 0; -} - - int dram_init(void) { phys_size_t dram_size; #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) - uint32_t regval; - - /* Remove reset of DDR using GPIO pin. We do this manually since - * we have not yet access to the DM gpio at this time */ - /* DDR_RST_N => IFC_CS3_B => GPIO2_12 */ - -#define CONFIG_SYS_MPC85XX_GPIO2_ADDR (CONFIG_SYS_IMMR + 0x131000) -#define DDR_RST_N (12) -/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */ -/* #define DDR_RST_N MPC85XX_GPIO_NR(2, 12) */ - - /* Set output */ - regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8); - regval |= (0x80000000 >> 12); - out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8, regval); - - /* Set direction to acivate gpio pin */ - regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR); - regval |= (0x80000000 >> 12); - out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR, regval); - dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; @@ -163,9 +130,7 @@ int dram_init(void) /* DDR has been initialised by SPL loader */ dram_size = fsl_ddr_sdram_size(); #endif - - test123(); - + gd->ram_size = dram_size; return 0; |