diff options
Diffstat (limited to 'board/scalys/simc-t10xx/pci.c')
| -rw-r--r-- | board/scalys/simc-t10xx/pci.c | 55 |
1 files changed, 50 insertions, 5 deletions
diff --git a/board/scalys/simc-t10xx/pci.c b/board/scalys/simc-t10xx/pci.c index ab9edbb..9a02f90 100644 --- a/board/scalys/simc-t10xx/pci.c +++ b/board/scalys/simc-t10xx/pci.c @@ -1,5 +1,5 @@ /* - * Copyright 2016 Scalys B.V. + * Copyright 2017 Scalys B.V. * opensource@scalys.com * * Copyright 2013 Freescale Semiconductor, Inc. @@ -22,11 +22,16 @@ void pci_init_board(void) uint32_t *gpio1_gpdat = (uint32_t *) 0xffe130008; uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000; uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008; - uint32_t regval; - - debug("%s\n", __FUNCTION__); + uint32_t regval; + + /*debug("%s\n", __FUNCTION__);*/ - //TODO, when present pins are available on the board, use them to enable only active slots + /*TODO, when present pins are available on the board, use them to enable only active slots*/ + +#if 0 + /* Dragonfruit Carrier board 1.x */ + + /* * IRQ[0-3] : PCIe present detect signals * IRQ[0] : SLOT1_PRSNT2_N : XXX @@ -51,7 +56,47 @@ void pci_init_board(void) regval |= ( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) ); out_be32(gpio1_gpdir, regval); +#else + /* Dragonfruit Carrier board 2.x */ + /* + * PCIe present detect signals: + * IRQ[3] : GPIO1_23 : SLOT1_PRSNT2_N + * IRQ[4] : GPIO1_24 : SLOT2_PRSNT2_N + * IRQ[5] : GPIO1_25 : SLOT3_PRSNT2_N + * IRQ[10] : GPIO1_30 : SLOT4_PRSNT2_N + * + * Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7 + * IFC_CS_N7 : GPIO1_IO12 : PCIe SLOT4_REFCLK_OE_N (used for all 4 slots) + * IFC_PAR1 : GPIO2_14 : PEX_REFCLK_SEL + */ + + /* Set output to 0 to enable reference clocks */ + regval = in_be32(gpio1_gpdat); + regval &= ~( 0x80000000 >> 12 ); + out_be32(gpio1_gpdat, regval); + /* Set Enable outputs */ + regval = in_be32(gpio1_gpdir); + regval |= ( 0x80000000 >> 12 ); + out_be32(gpio1_gpdir, regval); + + /* Set PEX_REFCLK_SEL to 0 to select CLK0 */ + + /* Set IFC_PAR1 to output mode */ + regval = in_be32(gpio2_gpdir); + regval |= ( 0x80000000 >> 14 ); + out_be32(gpio2_gpdir, regval); + + /* Set output to 0 to select clock source 0 */ + regval = in_be32(gpio2_gpdat); + regval &= ~( 0x80000000 >> 14 ); + out_be32(gpio2_gpdat, regval); + +#endif + + /* + * IFC_PAR0 : GPIO2_13 : PEX_PERST_N + */ /* Remove reset from PCIe devices */ |