diff options
Diffstat (limited to 'board/scalys/simc-t10xx/tlb.c')
| -rw-r--r-- | board/scalys/simc-t10xx/tlb.c | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/board/scalys/simc-t10xx/tlb.c b/board/scalys/simc-t10xx/tlb.c index fa2dccb..e6edf51 100644 --- a/board/scalys/simc-t10xx/tlb.c +++ b/board/scalys/simc-t10xx/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2016 Scalys B.V. + * Copyright 2017 Scalys B.V. * opensource@scalys.com * * Copyright 2013 Freescale Semiconductor, Inc. @@ -40,14 +40,12 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_256K, 1), - #elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD) /* * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot * the physical address of the SRAM is at 0xbffc0000, * and virtual address is 0xfffc0000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -66,8 +64,8 @@ struct fsl_e_tlb_entry tlb_table[] = { /* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_64M, 1), #ifndef CONFIG_SPL_BUILD #ifdef CONFIG_PCI @@ -116,21 +114,20 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), #endif -#ifdef CONFIG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 11, BOOKE_PAGESZ_256K, 1), -#endif #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 12, BOOKE_PAGESZ_1G, 1), +#if defined(CONFIG_SYS_SDRAM_SIZE) +#if (CONFIG_SYS_SDRAM_SIZE >= 2048) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 13, BOOKE_PAGESZ_1G, 1) #endif +#endif +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); |