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-rw-r--r--board/scalys/simc-t10xx/Kconfig2
-rw-r--r--board/scalys/simc-t10xx/ddr.c39
-rw-r--r--board/scalys/simc-t10xx/dragonfruit.c10
-rw-r--r--board/scalys/simc-t10xx/simc-t10xx.c36
4 files changed, 46 insertions, 41 deletions
diff --git a/board/scalys/simc-t10xx/Kconfig b/board/scalys/simc-t10xx/Kconfig
index d43dc85..2b18913 100644
--- a/board/scalys/simc-t10xx/Kconfig
+++ b/board/scalys/simc-t10xx/Kconfig
@@ -57,7 +57,7 @@ config PPC_T1020
config PPC_T1022
bool
- prompt "T1040"
+ prompt "T1022"
config PPC_T1040
bool
diff --git a/board/scalys/simc-t10xx/ddr.c b/board/scalys/simc-t10xx/ddr.c
index ca5407e..f6d04ac 100644
--- a/board/scalys/simc-t10xx/ddr.c
+++ b/board/scalys/simc-t10xx/ddr.c
@@ -7,7 +7,7 @@
#include <common.h>
#include <asm/mmu.h>
-#include <asm/gpio.h>
+//#include <asm/gpio.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
@@ -18,10 +18,7 @@
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
-#include <asm/mpc8xxx_gpio.h>
-
-/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */
-#define DDR_RST_N MPC8XXX_GPIO_NR(2, 12)
+//#include <asm/gpio.h>
/* MT41K512M8RH-125 */
dimm_params_t ddr_raw_timing = {
@@ -91,8 +88,8 @@ void fsl_ddr_board_options(memctl_options_t *popts,
popts->ddr_cdr1 = 0x800c0000;
popts->ddr_cdr2 = 0x00000001;
- /* Clock is launched 1/4 applied cycle after address/command */
- popts->clk_adjust = 4;
+ /* Clock is launched 1/2 applied cycle after address/command */
+ popts->clk_adjust = 8;
}
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
@@ -114,15 +111,29 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
-
+
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+ uint32_t regval;
+
+ /* Remove reset of DDR using GPIO pin. We do this manually since
+ * we have not yet access to the DM gpio at this time */
+ /* DDR_RST_N => IFC_CS3_B => GPIO2_12 */
+
+#define CONFIG_SYS_MPC85XX_GPIO2_ADDR (CONFIG_SYS_IMMR + 0x131000)
+#define DDR_RST_N (12)
+/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */
+/* #define DDR_RST_N MPC85XX_GPIO_NR(2, 12) */
-#ifdef GPIO_IN_SPL_WORKING
- gpio_request(DDR_RST_N, "DDR_RST_N");
- gpio_direction_output(DDR_RST_N, 1);
-#else
- mpc8xxx_gpio_set(DDR_RST_N,1);
-#endif
+ /* Set output */
+ regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8);
+ regval |= (0x80000000 >> 12);
+ out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8, regval);
+
+ /* Set direction to acivate gpio pin */
+ regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR);
+ regval |= (0x80000000 >> 12);
+ out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR, regval);
+
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
diff --git a/board/scalys/simc-t10xx/dragonfruit.c b/board/scalys/simc-t10xx/dragonfruit.c
index 1656054..0ae849c 100644
--- a/board/scalys/simc-t10xx/dragonfruit.c
+++ b/board/scalys/simc-t10xx/dragonfruit.c
@@ -7,8 +7,6 @@
#include <common.h>
#include <asm-generic/gpio.h>
-#include <dm/platform_data/gpio_mpc8xxx.h>
-#include <asm/mpc8xxx_gpio.h>
#include "dragonfruit.h"
@@ -42,10 +40,10 @@
* SERDES H => Slot 4, lane 3
*/
-#define MUX_SER0_1_SEL MPC8XXX_GPIO_NR(2, 25)
-#define MUX_SER2_3_SEL MPC8XXX_GPIO_NR(2, 26)
-#define MUX_SER5_6_SEL MPC8XXX_GPIO_NR(2, 27)
-#define SERDES_CLK_OE MPC8XXX_GPIO_NR(2, 29)
+#define MUX_SER0_1_SEL MPC85XX_GPIO_NR(2, 25)
+#define MUX_SER2_3_SEL MPC85XX_GPIO_NR(2, 26)
+#define MUX_SER5_6_SEL MPC85XX_GPIO_NR(2, 27)
+#define SERDES_CLK_OE MPC85XX_GPIO_NR(2, 29)
int scalys_carrier_setup_muxing(int serdes_config)
{
diff --git a/board/scalys/simc-t10xx/simc-t10xx.c b/board/scalys/simc-t10xx/simc-t10xx.c
index f5b8a2c..46c5677 100644
--- a/board/scalys/simc-t10xx/simc-t10xx.c
+++ b/board/scalys/simc-t10xx/simc-t10xx.c
@@ -21,8 +21,6 @@
#include <fm_eth.h>
#include <asm/processor.h>
#include <asm/gpio.h>
-#include <asm/mpc8xxx_gpio.h>
-#include <dm/platform_data/gpio_mpc8xxx.h>
#include <fsl_esdhc.h>
#include <dm.h>
#include "dragonfruit.h"
@@ -43,13 +41,15 @@ int misc_init_r(void)
int serdes_config;
ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int ret;
+
+ debug("t10xx: misc_init_r\n");
/*
* Initialize and set the LED's on the module to indicate u-boot is alive
* IFC_A30 : led green : GPIO2_30
* IFC_A31 : led red : GPIO2_31
*/
- #define MODULE_LED_RED MPC8XXX_GPIO_NR(2, 31)
- #define MODULE_LED_GREEN MPC8XXX_GPIO_NR(2, 30)
+ #define MODULE_LED_RED MPC85XX_GPIO_NR(2, 31)
+ #define MODULE_LED_GREEN MPC85XX_GPIO_NR(2, 30)
gpio_request(MODULE_LED_RED, "module_led_red");
gpio_request(MODULE_LED_GREEN, "module_led_green");
@@ -74,22 +74,18 @@ int misc_init_r(void)
}
/* Platform data for the GPIOs */
-static const struct mpc8xxx_gpio_platdata gpio_platdata[] = {
- { .regs = (ccsr_gpio_t*) CONFIG_SYS_MPC8XXX_GPIO1_ADDR,
- .bank_name = "GPIO1_" },
- { .regs = (ccsr_gpio_t*) CONFIG_SYS_MPC8XXX_GPIO2_ADDR,
- .bank_name = "GPIO2_" },
- { .regs = (ccsr_gpio_t*) CONFIG_SYS_MPC8XXX_GPIO3_ADDR,
- .bank_name = "GPIO3_" },
- { .regs = (ccsr_gpio_t*) CONFIG_SYS_MPC8XXX_GPIO4_ADDR,
- .bank_name = "GPIO4_" },
+static const struct mpc85xx_gpio_plat gpio_platdata[] = {
+ { .addr = 0x130000, .ngpios = 32 },
+ { .addr = 0x131000, .ngpios = 32 },
+ { .addr = 0x132000, .ngpios = 32 },
+ { .addr = 0x133000, .ngpios = 32,},
};
-U_BOOT_DEVICES(mpc8xxx_gpios) = {
- { "gpio-mpc8xxx", &gpio_platdata[0] },
- { "gpio-mpc8xxx", &gpio_platdata[1] },
- { "gpio-mpc8xxx", &gpio_platdata[2] },
- { "gpio-mpc8xxx", &gpio_platdata[3] },
+U_BOOT_DEVICES(mpc85xx_gpios) = {
+ { "gpio_mpc85xx", &gpio_platdata[0] },
+ { "gpio_mpc85xx", &gpio_platdata[1] },
+ { "gpio_mpc85xx", &gpio_platdata[2] },
+ { "gpio_mpc85xx", &gpio_platdata[3] },
};
int ft_board_setup(void *blob, bd_t *bd)
@@ -97,7 +93,7 @@ int ft_board_setup(void *blob, bd_t *bd)
phys_addr_t base;
phys_size_t size;
- debug( "ft_board_setup\n" );
+ debug( "t10xx: ft_board_setup\n" );
ft_cpu_setup(blob, bd);
base = getenv_bootm_low();
@@ -144,4 +140,4 @@ void board_detail(void)
{
do_bcdinfo();
}
-#endif \ No newline at end of file
+#endif
generated by cgit v0.10.2 at 2024-06-14 06:22:23 (GMT)