diff options
Diffstat (limited to 'board/scalys/simc-t2081/eth.c')
| -rw-r--r-- | board/scalys/simc-t2081/eth.c | 206 |
1 files changed, 206 insertions, 0 deletions
diff --git a/board/scalys/simc-t2081/eth.c b/board/scalys/simc-t2081/eth.c new file mode 100644 index 0000000..c25a81c --- /dev/null +++ b/board/scalys/simc-t2081/eth.c @@ -0,0 +1,206 @@ +/* + * Copyright 2017 Scalys B.V. + * opensource@scalys.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <netdev.h> +#include <asm/fsl_serdes.h> +#include <asm/immap_85xx.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <malloc.h> +#include <fsl_dtsec.h> +#include <vsc9953.h> +#include <i2c.h> + +#include "../../freescale/common/fman.h" + +uint8_t sfp_phy_config[][2] = { + { 0x1b, 0x90 }, + { 0x1b, 0x84 }, + { 0x09, 0x0F }, + { 0x09, 0x00 }, + { 0x00, 0x81 }, + { 0x00, 0x40 }, +}; + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info memac_mdio_info; + unsigned int i; + uint8_t i2c_data; + int ret; + int phy_addr = 0; + + uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000; + uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008; + uint32_t *gpio4_gpdir = (uint32_t *) 0xffe133000; + uint32_t *gpio4_gpdat = (uint32_t *) 0xffe133008; + uint32_t regval; + + /* Try to read a byte from te carrier eeprom te determine if were on the correct carrier */ + ret = i2c_read(0x54, 0, 2, &i2c_data, 1 ); + if (ret != 0) { + printf("No dragonfruit carrier detected\n"); + return 0; + } + + printf("Initializing Fman\n"); + + memac_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fm_memac_mdio_init(bis, &memac_mdio_info); + + /* Marvell 88E1111 Setup + * + * Remove reset from Ethernet PHY's + * + * Carrier board v1.x: + * IFC_PERR_B : GPIO2_15 : eth1_reset + * IFC_CS_N2 : GPIO2_11 : eth2_reset + * + * Carrier board v2.x: + * IFC_PERR_B : GPIO2_15 : eth1_reset + * IFC_CS_N2 : GPIO4_09 : eth2_reset + * + * Note: make sure gpio pins are configured as gpio in RCW! + */ + +#if 0 + /* TODO: use EEPROM data to chose carrier board version */ + /* Carrier board v1.x */ + /* Clear outputs to activate reset */ + regval = in_be32(gpio2_gpdat); + regval &= ~((0x80000000 >> 11 ) | (0x80000000 >> 15)); + out_be32(gpio2_gpdat, regval); + + /* Set outputs to output mode */ + regval = in_be32(gpio2_gpdir); + regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15)); + out_be32(gpio2_gpdir, regval); + + /* Wait for 10 ms to to meet reset timing */ + mdelay(10); + + /* Set outputs to de-activate reset */ + regval = in_be32(gpio2_gpdat); + regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15)); + out_be32(gpio2_gpdat, regval); +#else + /* Carrier board v2.x */ + /* Clear outputs to activate reset */ + regval = in_be32(gpio2_gpdat); + regval &= ~(0x80000000 >> 15); + out_be32(gpio2_gpdat, regval); + regval = in_be32(gpio4_gpdat); + regval &= ~(0x80000000 >> 9); + out_be32(gpio4_gpdat, regval); + + /* Set outputs to output mode */ + regval = in_be32(gpio2_gpdir); + regval |= (0x80000000 >> 15); + out_be32(gpio2_gpdir, regval); + regval = in_be32(gpio4_gpdir); + regval |= (0x80000000 >> 9); + out_be32(gpio4_gpdir, regval); + + /* Wait for 10 ms to to meet reset timing */ + mdelay(10); + + /* Set outputs to de-activate reset */ + regval = in_be32(gpio2_gpdat); + regval |= (0x80000000 >> 15); + out_be32(gpio2_gpdat, regval); + regval = in_be32(gpio4_gpdat); + regval |= (0x80000000 >> 9); + out_be32(gpio4_gpdat, regval); +#endif + + /* Write 0x4111 to reg 0x18 on both PHYs to change LEDs usage */ + miiphy_write("FSL_MDIO0",0,0x18,0x4111); + miiphy_write("FSL_MDIO0",1,0x18,0x4111); + + /* Remove SFP TX_disable */ + i2c_set_bus_num(0); + ret = i2c_read(0x22, 0x0E, 1, &i2c_data, 1); + i2c_data &= ~0x04; + ret = i2c_write(0x22, 0x0E, 1, &i2c_data, 1); + + mdelay(100); + + i2c_set_bus_num(3); + + for (phy_addr=0; phy_addr<4; phy_addr++) { + i2c_data = (1 << phy_addr); + ret = i2c_write(0x70, 0, 1, &i2c_data, 1); + if (ret) { + printf("Error Setting SFP i2c MUX\n"); + break; + } + + for ( i = 0; i < 6; i++) { + ret = i2c_write(0x56, sfp_phy_config[i][0], 1, &(sfp_phy_config[i][1]), 1); + if (ret) { + printf("Error sfp phy(%i:%i):%02x to address %02x\n", phy_addr, i, sfp_phy_config[i][1],sfp_phy_config[i][0]); + break; + } + } + } + + /* Two external pin interfaces + * MAC1|MAC2|MAC3 SGMII interface + * MAC3|MAC4|MAC10 EC1|EC2 RGMII interface + */ + + /* + * Program on board RGMII, SGMII PHY addresses. + */ + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_RGMII: + if (FM1_DTSEC3 == i) + phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; + if (FM1_DTSEC4 == i) + phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR; + /*if (FM1_DTSEC10 == i) + phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;*/ + fm_info_set_phy_address(i, phy_addr); + break; + case PHY_INTERFACE_MODE_QSGMII: + /* TODO, get fixed phy here */ + fm_info_set_phy_address(i, i+2); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); + break; + case PHY_INTERFACE_MODE_SGMII: + printf("TODO, add phy interface to SGMII\n"); + fm_info_set_phy_address(i, PHY_INTERFACE_MODE_NONE); + break; + default: + printf("Fman1: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + //fm_info_set_phy_address(i, 0); + break; + } + fm_info_set_mdio(i, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + } + + cpu_eth_init(bis); +#endif + return pci_eth_init(bis); +} + +/*void fdt_fixup_board_enet(void *fdt) +{ + return; +}*/ |