diff options
Diffstat (limited to 'board/scalys/simc-t2081/eth.c')
| -rw-r--r-- | board/scalys/simc-t2081/eth.c | 89 |
1 files changed, 72 insertions, 17 deletions
diff --git a/board/scalys/simc-t2081/eth.c b/board/scalys/simc-t2081/eth.c index 10c59f8..82703d4 100644 --- a/board/scalys/simc-t2081/eth.c +++ b/board/scalys/simc-t2081/eth.c @@ -15,9 +15,13 @@ #include <fsl_dtsec.h> #include <vsc9953.h> #include <i2c.h> +#include <phy.h> +#include <cortina.h> #include "../../freescale/common/fman.h" +#define VILLA_EEPROM_LOADER_STATUS 0xc01 + uint8_t sfp_phy_config[][2] = { { 0x1b, 0x90 }, { 0x1b, 0x84 }, @@ -32,18 +36,21 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_FMAN_ENET struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; + /*struct phy_driver *cortina_10G_phy;*/ unsigned int i; uint8_t i2c_data; int ret; int phy_addr = 0; + /*uint32_t *gpio1_gpdir = (uint32_t *) 0xffe130000; + uint32_t *gpio1_gpdat = (uint32_t *) 0xffe130008;*/ uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000; uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008; uint32_t *gpio4_gpdir = (uint32_t *) 0xffe133000; uint32_t *gpio4_gpdat = (uint32_t *) 0xffe133008; uint32_t regval; - /* Try to read a byte from te carrier eeprom te determine if were on the correct carrier */ + /* Try to read a byte from the carrier eeprom the determine if were on the correct carrier */ ret = i2c_read(0x54, 0, 2, &i2c_data, 1 ); if (ret != 0) { printf("No dragonfruit carrier detected\n"); @@ -71,27 +78,30 @@ int board_eth_init(bd_t *bis) * Remove reset from Ethernet PHY's * * Carrier board v1.x: - * IFC_PERR_B : GPIO2_15 : eth1_reset - * IFC_CS_N2 : GPIO2_11 : eth2_reset + * IFC_PERR_B : GPIO2_15 : eth1_reset_n + * IFC_CS_N2 : GPIO2_11 : eth2_reset_n * * Carrier board v2.x: - * IFC_PERR_B : GPIO2_15 : eth1_reset - * IFC_CS_N2 : GPIO4_09 : eth2_reset + * IFC_PERR_B : GPIO2_15 : eth1_reset_n + * N_DMA2_DDONE0_B : GPIO4_09 : eth2_reset_n * * Note: make sure gpio pins are configured as gpio in RCW! */ #if 0 + +#define ETH1_RESET_N (0x80000000 >> 15) +#define ETH2_RESET_N (0x80000000 >> 11) /* TODO: use EEPROM data to chose carrier board version */ /* Carrier board v1.x */ /* Clear outputs to activate reset */ regval = in_be32(gpio2_gpdat); - regval &= ~((0x80000000 >> 11 ) | (0x80000000 >> 15)); + regval &= ~(ETH1_RESET_N | ETH2_RESET_N); out_be32(gpio2_gpdat, regval); /* Set outputs to output mode */ regval = in_be32(gpio2_gpdir); - regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15)); + regval |= (ETH1_RESET_N | ETH2_RESET_N); out_be32(gpio2_gpdir, regval); /* Wait for 10 ms to to meet reset timing */ @@ -99,24 +109,27 @@ int board_eth_init(bd_t *bis) /* Set outputs to de-activate reset */ regval = in_be32(gpio2_gpdat); - regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15)); + regval |= (ETH1_RESET_N | ETH2_RESET_N); out_be32(gpio2_gpdat, regval); #else + +#define ETH1_RESET_N (0x80000000 >> 15) +#define ETH2_RESET_N (0x80000000 >> 9) /* Carrier board v2.x */ /* Clear outputs to activate reset */ regval = in_be32(gpio2_gpdat); - regval &= ~(0x80000000 >> 15); + regval &= ~(ETH1_RESET_N); out_be32(gpio2_gpdat, regval); regval = in_be32(gpio4_gpdat); - regval &= ~(0x80000000 >> 9); + regval &= ~(ETH2_RESET_N); out_be32(gpio4_gpdat, regval); /* Set outputs to output mode */ regval = in_be32(gpio2_gpdir); - regval |= (0x80000000 >> 15); + regval |= (ETH1_RESET_N); out_be32(gpio2_gpdir, regval); regval = in_be32(gpio4_gpdir); - regval |= (0x80000000 >> 9); + regval |= (ETH2_RESET_N); out_be32(gpio4_gpdir, regval); /* Wait for 10 ms to to meet reset timing */ @@ -124,10 +137,10 @@ int board_eth_init(bd_t *bis) /* Set outputs to de-activate reset */ regval = in_be32(gpio2_gpdat); - regval |= (0x80000000 >> 15); + regval |= (ETH1_RESET_N); out_be32(gpio2_gpdat, regval); regval = in_be32(gpio4_gpdat); - regval |= (0x80000000 >> 9); + regval |= (ETH2_RESET_N); out_be32(gpio4_gpdat, regval); #endif @@ -199,13 +212,55 @@ int board_eth_init(bd_t *bis) } fm_info_set_mdio(i, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); } - + + /* 10G XFI interface initialization (TODO)*/ +#if 0 + /* Reset phy */ + /* N_DMA2_DDONE0_B : GPIO1_09 : EDC_RST_N */ +#define EDC_RST_N (0x80000000 >> 9) + /* Clear outputs to activate reset */ + regval = in_be32(gpio1_gpdat); + regval &= ~(EDC_RST_N); + out_be32(gpio1_gpdat, regval); + + /* Set outputs to output mode */ + regval = in_be32(gpio1_gpdir); + regval |= (EDC_RST_N); + out_be32(gpio1_gpdir, regval); + + /* Wait for 10 ms to to meet reset timing */ + mdelay(10); + + /* Set outputs to de-activate reset */ + regval = in_be32(gpio1_gpdat); + regval |= (EDC_RST_N); + out_be32(gpio1_gpdat, regval); + + /* Wait 10ms to let phy set the load_failed bit */ + mdelay(10); + + /* get cs4315 phy */ + cortina_10G_phy = phy_find_by_mask(tgec_mdio_info, 0xfffffff0, PHY_INTERFACE_MODE_XGMII); + + /* Check load_failed == 1 (else skip initialization) */ + mii_data = miiphy_read("FM_TGEC_MDIO",0,VILLA_EEPROM_LOADER_STATUS); + + if ((mii_data & 0x02) != 0) { + /* TODO: upload microcode */ + cortina_10G_phy->config(); + } + + /* TODO: insert additional configuration */ + + /* Start phy */ + cortina_10G_phy->startup(); +#endif for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1); + fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2); break; case PHY_INTERFACE_MODE_NONE: fm_info_set_phy_address(i, 0); |