diff options
Diffstat (limited to 'board/scalys/simc-t2081/pci.c')
| -rw-r--r-- | board/scalys/simc-t2081/pci.c | 122 |
1 files changed, 122 insertions, 0 deletions
diff --git a/board/scalys/simc-t2081/pci.c b/board/scalys/simc-t2081/pci.c new file mode 100644 index 0000000..9a02f90 --- /dev/null +++ b/board/scalys/simc-t2081/pci.c @@ -0,0 +1,122 @@ +/* + * Copyright 2017 Scalys B.V. + * opensource@scalys.com + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/fsl_pci.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/fsl_serdes.h> + +void pci_init_board(void) +{ + + uint32_t *gpio1_gpdir = (uint32_t *) 0xffe130000; + uint32_t *gpio1_gpdat = (uint32_t *) 0xffe130008; + uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000; + uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008; + uint32_t regval; + + /*debug("%s\n", __FUNCTION__);*/ + + /*TODO, when present pins are available on the board, use them to enable only active slots*/ + +#if 0 + /* Dragonfruit Carrier board 1.x */ + + + /* + * IRQ[0-3] : PCIe present detect signals + * IRQ[0] : SLOT1_PRSNT2_N : XXX + * IRQ[1] : SLOT2_PRSNT2_N : XXX + * IRQ[2] : SLOT3_PRSNT2_N : XXX + * IRQ[3] : SLOT4_PRSNT2_N : XXX + * + * Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7 + * IFC_CS_N4 : GPIO1_IO09 : PCIe SLOT1_REFCLK_OE_N + * IFC_CS_N5 : GPIO1_IO10 : PCIe SLOT2_REFCLK_OE_N + * IFC_CS_N6 : GPIO1_IO11 : PCIe SLOT3_REFCLK_OE_N + * IFC_CS_N7 : GPIO1_IO12 : PCIe SLOT4_REFCLK_OE_N + */ + + /* Set output to 0 to enable reference clocks */ + regval = in_be32(gpio1_gpdat); + regval &= ~( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) ); + out_be32(gpio1_gpdat, regval); + + /* Set Enable outputs*/ + regval = in_be32(gpio1_gpdir); + regval |= ( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) ); + out_be32(gpio1_gpdir, regval); + +#else + /* Dragonfruit Carrier board 2.x */ + /* + * PCIe present detect signals: + * IRQ[3] : GPIO1_23 : SLOT1_PRSNT2_N + * IRQ[4] : GPIO1_24 : SLOT2_PRSNT2_N + * IRQ[5] : GPIO1_25 : SLOT3_PRSNT2_N + * IRQ[10] : GPIO1_30 : SLOT4_PRSNT2_N + * + * Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7 + * IFC_CS_N7 : GPIO1_IO12 : PCIe SLOT4_REFCLK_OE_N (used for all 4 slots) + * IFC_PAR1 : GPIO2_14 : PEX_REFCLK_SEL + */ + + /* Set output to 0 to enable reference clocks */ + regval = in_be32(gpio1_gpdat); + regval &= ~( 0x80000000 >> 12 ); + out_be32(gpio1_gpdat, regval); + + /* Set Enable outputs */ + regval = in_be32(gpio1_gpdir); + regval |= ( 0x80000000 >> 12 ); + out_be32(gpio1_gpdir, regval); + + /* Set PEX_REFCLK_SEL to 0 to select CLK0 */ + + /* Set IFC_PAR1 to output mode */ + regval = in_be32(gpio2_gpdir); + regval |= ( 0x80000000 >> 14 ); + out_be32(gpio2_gpdir, regval); + + /* Set output to 0 to select clock source 0 */ + regval = in_be32(gpio2_gpdat); + regval &= ~( 0x80000000 >> 14 ); + out_be32(gpio2_gpdat, regval); + +#endif + + /* + * IFC_PAR0 : GPIO2_13 : PEX_PERST_N + */ + + /* Remove reset from PCIe devices */ + + /* Set IFC_PAR0 to output mode */ + regval = in_be32(gpio2_gpdir); + regval |= ( 0x80000000 >> 13 ); + out_be32(gpio2_gpdir, regval); + + /* Set output to 1 to clear reset */ + regval = in_be32(gpio2_gpdat); + regval |= ( 0x80000000 >> 13 ); + out_be32(gpio2_gpdat, regval); + + /* Wait for 100 ms to allow the PCIe device to become ready */ + mdelay(100); + + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} |