diff options
Diffstat (limited to 'board/scalys/simc-t2081/pci.c')
| -rw-r--r-- | board/scalys/simc-t2081/pci.c | 79 |
1 files changed, 36 insertions, 43 deletions
diff --git a/board/scalys/simc-t2081/pci.c b/board/scalys/simc-t2081/pci.c index 9a02f90..f3473f8 100644 --- a/board/scalys/simc-t2081/pci.c +++ b/board/scalys/simc-t2081/pci.c @@ -14,30 +14,49 @@ #include <libfdt.h> #include <fdt_support.h> #include <asm/fsl_serdes.h> +#include <asm-generic/gpio.h> +#include "dragonfruit.h" + +#define SLOT1_REFCLK_OE_N MPC85XX_GPIO_NR(1, 9) +#define SLOT2_REFCLK_OE_N MPC85XX_GPIO_NR(1, 10) +#define SLOT3_REFCLK_OE_N MPC85XX_GPIO_NR(1, 11) +#define SLOT4_REFCLK_OE_N MPC85XX_GPIO_NR(1, 12) + +#define SLOT1_PRSNT2_N MPC85XX_GPIO_NR(1, 23) +#define SLOT2_PRSNT2_N MPC85XX_GPIO_NR(1, 24) +#define SLOT3_PRSNT2_N MPC85XX_GPIO_NR(1, 25) +#define SLOT4_PRSNT2_N MPC85XX_GPIO_NR(1, 30) + +#define PEX_REFCLK_SEL MPC85XX_GPIO_NR(2, 14) +#define PEX_PERST_N MPC85XX_GPIO_NR(2, 13) + void pci_init_board(void) { + int ret = 0; + int serdes_config; + ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint32_t *gpio1_gpdir = (uint32_t *) 0xffe130000; - uint32_t *gpio1_gpdat = (uint32_t *) 0xffe130008; - uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000; - uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008; - uint32_t regval; - - /*debug("%s\n", __FUNCTION__);*/ + /* SERDES configuration is determined boot time through the RCW config. + * It is located in the fourth RCW word (bit 128-135 of the RCW). */ + serdes_config = ( in_be32(&gur->rcwsr[4]) >> 24); + scalys_carrier_setup_muxing(serdes_config); - /*TODO, when present pins are available on the board, use them to enable only active slots*/ + ret += gpio_request(SLOT4_REFCLK_OE_N, "c19"); + ret += gpio_request(PEX_REFCLK_SEL, "c14"); + ret += gpio_request(PEX_PERST_N, "c15"); + if (ret != 0) + printf("A gpio request failed(%i)\n", ret); #if 0 /* Dragonfruit Carrier board 1.x */ - /* * IRQ[0-3] : PCIe present detect signals - * IRQ[0] : SLOT1_PRSNT2_N : XXX - * IRQ[1] : SLOT2_PRSNT2_N : XXX - * IRQ[2] : SLOT3_PRSNT2_N : XXX - * IRQ[3] : SLOT4_PRSNT2_N : XXX + * IRQ[3] : GPIO1_23 : SLOT1_PRSNT2_N + * IRQ[4] : GPIO1_24 : SLOT2_PRSNT2_N + * IRQ[5] : GPIO1_25 : SLOT3_PRSNT2_N + * IRQ[10] : GPIO1_30 : SLOT4_PRSNT2_N * * Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7 * IFC_CS_N4 : GPIO1_IO09 : PCIe SLOT1_REFCLK_OE_N @@ -71,44 +90,18 @@ void pci_init_board(void) */ /* Set output to 0 to enable reference clocks */ - regval = in_be32(gpio1_gpdat); - regval &= ~( 0x80000000 >> 12 ); - out_be32(gpio1_gpdat, regval); - - /* Set Enable outputs */ - regval = in_be32(gpio1_gpdir); - regval |= ( 0x80000000 >> 12 ); - out_be32(gpio1_gpdir, regval); + gpio_direction_output(SLOT4_REFCLK_OE_N, 0); /* Set PEX_REFCLK_SEL to 0 to select CLK0 */ - - /* Set IFC_PAR1 to output mode */ - regval = in_be32(gpio2_gpdir); - regval |= ( 0x80000000 >> 14 ); - out_be32(gpio2_gpdir, regval); - - /* Set output to 0 to select clock source 0 */ - regval = in_be32(gpio2_gpdat); - regval &= ~( 0x80000000 >> 14 ); - out_be32(gpio2_gpdat, regval); - -#endif + gpio_direction_output(PEX_REFCLK_SEL, 0); +#endif /* * IFC_PAR0 : GPIO2_13 : PEX_PERST_N */ /* Remove reset from PCIe devices */ - - /* Set IFC_PAR0 to output mode */ - regval = in_be32(gpio2_gpdir); - regval |= ( 0x80000000 >> 13 ); - out_be32(gpio2_gpdir, regval); - - /* Set output to 1 to clear reset */ - regval = in_be32(gpio2_gpdat); - regval |= ( 0x80000000 >> 13 ); - out_be32(gpio2_gpdat, regval); + gpio_direction_output(PEX_PERST_N, 1); /* Wait for 100 ms to allow the PCIe device to become ready */ mdelay(100); |