diff options
Diffstat (limited to 'board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg')
| -rw-r--r-- | board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg b/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg new file mode 100644 index 0000000..e3ed70b --- /dev/null +++ b/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg @@ -0,0 +1,44 @@ +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#512KB SRAM +09010100 00000000 +09010104 fffc0009 +09010f00 08000000 +#enable CPC1 +09010000 80000000 +#Configure LAW for CPC1 (LAW 13) +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Errata for slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure IFC controller +# (IFC_CSPR1) +09124010 ff8000c3 +# IFC_CSOR_NAND +09124130 85084101 +# IFC_FTIM0_CS0_NAND to IFC_FTIM0_CS0_NAND +091241c0 181c080c +091241c4 3850141a +091241c8 03008028 +091241cc 28000000 +# Set IFC_CCR clkdiv to 2 (=/3) to get: +# (platform clock/2/3=83.3MHz) +0912444c 02008000 +#Flush PBL data (Wait 0xFFFFF cycles ) +091380c0 000fffff |