diff options
Diffstat (limited to 'board/scalys/simc-t2081/spl.c')
| -rw-r--r-- | board/scalys/simc-t2081/spl.c | 179 |
1 files changed, 179 insertions, 0 deletions
diff --git a/board/scalys/simc-t2081/spl.c b/board/scalys/simc-t2081/spl.c new file mode 100644 index 0000000..f0fb9dd --- /dev/null +++ b/board/scalys/simc-t2081/spl.c @@ -0,0 +1,179 @@ +/* + * Copyright 2017 Scalys B.V. + * opensource@scalys.com + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <ns16550.h> +#include <console.h> +#include <nand.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <i2c.h> +#include <spi_flash.h> + +DECLARE_GLOBAL_DATA_PTR; + +phys_size_t get_effective_memsize(void) +{ + return CONFIG_SYS_L3_SIZE; +} + +unsigned long get_board_sys_clk(void) +{ + return CONFIG_SYS_CLK_FREQ; +} + +unsigned long get_board_ddr_clk(void) +{ + return CONFIG_DDR_CLK_FREQ; +} + +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 +void board_init_f(ulong bootflag) +{ + u32 plat_ratio, sys_clk, uart_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); + + /* Update GD pointer */ + gd = (gd_t *)(CONFIG_SPL_GD_ADDR); + + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("" : : : "memory"); + + console_init_f(); + + /* initialize selected port with appropriate baud rate */ + sys_clk = get_board_sys_clk(); + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; + uart_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + uart_clk / 16 / CONFIG_BAUDRATE); + + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); +} + +void setup_ifc_nand(enum ifc_chip_sel cs) +{ + set_ifc_cspr_ext(cs, CONFIG_SYS_NAND_CSPR_EXT); + set_ifc_csor (cs, CONFIG_SYS_NAND_CSOR); + set_ifc_amask (cs, CONFIG_SYS_NAND_AMASK); + set_ifc_cspr (cs, CONFIG_SYS_NAND_CSPR); + set_ifc_ftim (cs, IFC_FTIM0, CONFIG_SYS_NAND_FTIM0); + set_ifc_ftim (cs, IFC_FTIM1, CONFIG_SYS_NAND_FTIM1); + set_ifc_ftim (cs, IFC_FTIM2, CONFIG_SYS_NAND_FTIM2); + set_ifc_ftim (cs, IFC_FTIM3, CONFIG_SYS_NAND_FTIM3); + set_ifc_csor_ext(cs, 0); + +} + +void setup_ifc_nor(enum ifc_chip_sel cs) +{ + set_ifc_cspr_ext(cs, CONFIG_SYS_NOR_CSPR_EXT); + set_ifc_csor (cs, CONFIG_SYS_NOR_CSOR); + set_ifc_amask (cs, CONFIG_SYS_NOR_AMASK); + set_ifc_cspr (cs, CONFIG_SYS_NOR_CSPR); + set_ifc_ftim (cs, IFC_FTIM0, CONFIG_SYS_NOR_FTIM0); + set_ifc_ftim (cs, IFC_FTIM1, CONFIG_SYS_NOR_FTIM1); + set_ifc_ftim (cs, IFC_FTIM2, CONFIG_SYS_NOR_FTIM2); + set_ifc_ftim (cs, IFC_FTIM3, CONFIG_SYS_NOR_FTIM3); + set_ifc_csor_ext(cs, 0); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + bd_t *bd; + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + uint32_t boot_source; + + __attribute__((noreturn)) void (*boot)(void) = hang; + + bd = (bd_t *)(gd + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; + bd->bi_memsize = CONFIG_SYS_L3_SIZE; + + arch_cpu_init(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; + + gd->ram_size = dram_init(); + + /* Get the boot source from the Power On Status Register (set by QSC) */ + boot_source = (in_be32(&gur->porsr1) >> 23); + + switch (boot_source) { + case 0x23: + /* NOR boot */ + setup_ifc_nor(IFC_CS0); + setup_ifc_nand(IFC_CS1); + + memcpy((void*)CONFIG_SYS_NAND_U_BOOT_DST, (void*) CONFIG_SYS_FLASH_BASE + CONFIG_SPL_PAD_TO, CONFIG_SYS_NAND_U_BOOT_SIZE); + + flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE); + boot = (void*) CONFIG_SYS_NAND_U_BOOT_START; + break; + + case 0x45: +#if 0 + /*SPI nor flash */ + setup_ifc_nand(IFC_CS0); + setup_ifc_nor(IFC_CS1); + //fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, (uchar *)CONFIG_ENV_ADDR); + { + struct spi_flash *flash; + + flash = spi_flash_probe(0, 0, + CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE); + if (flash == NULL) { + puts("\nspi_flash_probe failed"); + hang(); + } + + spi_flash_read(flash, CONFIG_SPL_PAD_TO, CONFIG_SYS_NAND_U_BOOT_SIZE, (void*) CONFIG_SYS_NAND_U_BOOT_DST); + } +#endif + printf("TODO, load u-boot from SPI....\n"); + hang(); + break; + case 0x40: + /* SD/MMC (eSDHC) boot */ + #ifdef CONFIG_SPL_MMC_BOOT + setup_ifc_nand(IFC_CS0); + setup_ifc_nor(IFC_CS1); + + mmc_initialize(bd); + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + boot = mmc_boot; + #endif + break; + case 0x105: + /* NAND boot */ + setup_ifc_nand(IFC_CS0); + setup_ifc_nor(IFC_CS1); + + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + boot = nand_boot; + break; + default: + printf("Unknown boot source (%3x\n", boot_source); + break; + } + boot(); +} |