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-rw-r--r--board/scalys/simc-t2081/Kconfig9
-rw-r--r--board/scalys/simc-t2081/Makefile19
-rw-r--r--board/scalys/simc-t2081/ddr.c146
-rw-r--r--board/scalys/simc-t2081/dragonfruit.c169
-rw-r--r--board/scalys/simc-t2081/dragonfruit.h13
-rw-r--r--board/scalys/simc-t2081/eth.c206
-rw-r--r--board/scalys/simc-t2081/law.c32
-rw-r--r--board/scalys/simc-t2081/pci.c122
-rw-r--r--board/scalys/simc-t2081/simc-t2081.c143
-rw-r--r--board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg44
-rw-r--r--board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg20
-rw-r--r--board/scalys/simc-t2081/simc-t2081_nor_pbi.cfg31
-rw-r--r--board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg8
-rw-r--r--board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg31
-rw-r--r--board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg18
-rw-r--r--board/scalys/simc-t2081/spl.c179
-rw-r--r--board/scalys/simc-t2081/tlb.c131
17 files changed, 1321 insertions, 0 deletions
diff --git a/board/scalys/simc-t2081/Kconfig b/board/scalys/simc-t2081/Kconfig
new file mode 100644
index 0000000..323ae5b
--- /dev/null
+++ b/board/scalys/simc-t2081/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_SIMC_TXXXX && ARCH_T2081
+
+config SYS_BOARD
+ default "simc-t2081"
+
+config SYS_CONFIG_NAME
+ default "simc-t2081"
+
+endif
diff --git a/board/scalys/simc-t2081/Makefile b/board/scalys/simc-t2081/Makefile
new file mode 100644
index 0000000..730b5ad
--- /dev/null
+++ b/board/scalys/simc-t2081/Makefile
@@ -0,0 +1,19 @@
+# Copyright 2016 Scalys B.V.
+# opensource@scalys.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+UBOOTINCLUDE += -I$(srctree)/board/$(VENDOR)/common/
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += simc-t2081.o
+obj-y += eth.o
+obj-$(CONFIG_PCI) += pci.o
+endif
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
+obj-y += dragonfruit.o
diff --git a/board/scalys/simc-t2081/ddr.c b/board/scalys/simc-t2081/ddr.c
new file mode 100644
index 0000000..3d8821c
--- /dev/null
+++ b/board/scalys/simc-t2081/ddr.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* MT41K512M8RH-125 */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 2,
+ .rank_density = 0x100000000ULL,
+ .capacity = 0x200000000ULL,
+ .primary_sdram_width = 64,
+ .ec_sdram_width = 8,
+ .registered_dimm = 0,
+ .mirrored_dimm = 1,
+ .n_row_addr = 16,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = EDC_ECC,
+ .burst_lengths_bitmask = 0x0c,
+ .tckmin_x_ps = 1250,
+ .tckmax_ps = 1499,
+ .caslat_x = (1 << 11),
+ .taa_ps = 13750,
+ .trcd_ps = 13750,
+ .trp_ps = 13750,
+ .tras_ps = 35000,
+ .trc_ps = 48750,
+ .tfaw_ps = 30000,
+ .twr_ps = 15000,
+ .trfc_ps = 260000,
+ .trrd_ps = 5000, //1Kb page size!
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 70200000,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ int i;
+
+ if (ctrl_num != 0) {
+ printf("Only 1 memory controller supported, but %i requested\n",
+ ctrl_num);
+ return;
+ }
+
+ if (pdimm == NULL ) {
+ printf("Error, no valid dimm pararmeter supplied\n");
+ return;
+ }
+
+ if (!pdimm->n_ranks) {
+ printf("No ranks in dimm parameters. Configuration error?\n");
+ return;
+ }
+
+ /* set odt_rd_cfg and odt_wr_cfg. */
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ popts->cs_local_opts[i].odt_wr_cfg = 4;
+ }
+
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 13;
+ popts->wrlvl_start = 7; /* 7/8 clock delay */
+ popts->wrlvl_ctl_2 = 0x06070809;
+ popts->wrlvl_ctl_3 = 0x0d0f0a09;
+
+ popts->ddr_cdr1 = 0x800c0000;
+ popts->ddr_cdr2 = 0x00000001;
+
+ /* Clock is launched 1/2 applied cycle after address/command */
+ popts->clk_adjust = 8;
+
+ /* cpo optimization */
+ popts->cpo_sample = 0x46;
+}
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Soldered-down discrete DDR3";
+
+ if (((controller_number == 0) && (dimm_number == 0)) ||
+ ((controller_number == 1) && (dimm_number == 0))) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+ uint32_t regval;
+
+ /* Remove reset of DDR using GPIO pin. We do this manually since
+ * we have not yet access to the DM gpio at this time */
+ /* DDR_RST_N => IFC_CS3_B => GPIO2_12 */
+
+#define CONFIG_SYS_MPC85XX_GPIO2_ADDR (CONFIG_SYS_IMMR + 0x131000)
+#define DDR_RST_N (12)
+/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */
+/* #define DDR_RST_N MPC85XX_GPIO_NR(2, 12) */
+
+ /* Set output */
+ regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8);
+ regval |= (0x80000000 >> 12);
+ out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8, regval);
+
+ /* Set direction to acivate gpio pin */
+ regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR);
+ regval |= (0x80000000 >> 12);
+ out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR, regval);
+
+ dram_size = fsl_ddr_sdram();
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+#else
+ /* DDR has been initialised by SPL loader */
+ dram_size = fsl_ddr_sdram_size();
+#endif
+
+ gd->ram_size = dram_size;
+
+ return 0;
+}
diff --git a/board/scalys/simc-t2081/dragonfruit.c b/board/scalys/simc-t2081/dragonfruit.c
new file mode 100644
index 0000000..286b2c2
--- /dev/null
+++ b/board/scalys/simc-t2081/dragonfruit.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include "dragonfruit.h"
+
+/*
+ * SERDER MUX Configuration pins:
+ * IFC_A25 : GPIO2_25 : SERDES_CLK_ MUX_SER0_1_SEL
+ * IFC_A26 : GPIO2_26 : SERDES_CLK_ MUX_SER2_3_SEL
+ * IFC_A27 : GPIO2_27 : SERDES_CLK_ MUX_SER5_6_SEL
+ */
+#define MUX_SER0_1_SEL MPC85XX_GPIO_NR(2, 25)
+#define MUX_SER2_3_SEL MPC85XX_GPIO_NR(2, 26)
+#define MUX_SER5_6_SEL MPC85XX_GPIO_NR(2, 27)
+#define SERDES_CLK_OE MPC85XX_GPIO_NR(2, 29)
+
+/*
+ * MUX_SER0_1_SEL
+ * 0: SERDES A => Slot1, lane 0
+ * SERDES B => Slot1, lane 1
+ * 1: SERDES A => CS4315 retimer => SFP+ 0
+ * SERDES B => CS4315 retimer => SFP+ 1
+ */
+#define SER_0_1_SLOT1 0
+#define SER_0_1_SFP01 1
+
+/*
+ * MUX_SER2_3_SEL
+ * 0: SERDES C => Slot1, lane 2
+ * SERDES D => Slot1, lane 3
+ * 1: SERDES C => QSFP+ 2
+ * SERDES D => QSFP+ 3
+ */
+#define SER_2_3_SLOT1 0
+#define SER_2_3_SFP23 2
+
+/*
+ * SERDES E => Slot 4, lane 0
+ */
+
+/* MUX_SER5_6_SEL
+ * 0: SERDES F => SLOT4, lane 1
+ * SERDES G => SLOT4, lane 2
+ * 1: SERDES F => SLOT2
+ * SERDES G => SLOT3
+ */
+#define SER_5_6_SLOT4 0
+#define SER_5_6_SLOT23 4
+
+
+/*
+ * SERDES H => Slot 4, lane 3
+ */
+
+int scalys_carrier_setup_muxing(int serdes_config)
+{
+ int ret = 0;
+ int mux_config = 0;
+
+ ret = gpio_request(MUX_SER0_1_SEL, "mux_ser0_1_sel");
+ if (ret != 0) {
+ printf("gpio request failed(%i)\n", ret);
+ }
+ gpio_request(MUX_SER2_3_SEL, "mux_ser2_3_sel");
+ gpio_request(MUX_SER5_6_SEL, "mux_ser5_6_sel");
+ gpio_request(SERDES_CLK_OE, "serdes_clk_oe");
+
+
+ /*
+ * SERDES options for each target as supported by the dragonfruit
+ * carrier board. Refer to the QorIQ reference manual for the SERDES options table
+ * and all relevant information.
+ *
+ * Note: The SERDES lanes A&B, C&D, and F&G can only be switched
+ * as pairs using the multiplexers. Which means some SERDES options are only partly usable.
+ *
+ * Note 2/TODO: SERDES PLL2 must be powered down using SRDS_PLL_PD_S1 when
+ * SRDS_PRTCL_S1 is any of the following values: 0x00, 0x40, 0x60, 0x67,
+ * 0x85, 0x87, 0x8D, 0x45.
+ *
+ * T2081 has 8 SERDES lanes at up to 10GHz (ie. SERDES 2 configurations are DNC)
+ *
+ */
+ switch(serdes_config){
+#if defined(CONFIG_PPC_T2081)
+ /* TODO: test all major cases */
+ case 0x6E:
+ case 0xC8:
+ case 0xD6:
+ case 0x6C:
+ mux_config = SER_5_6_SLOT4 | SER_2_3_SFP23 | SER_0_1_SFP01;
+ break;
+ case 0xAA: /* Note 2 */
+ mux_config = SER_5_6_SLOT4 | SER_2_3_SLOT1 | SER_0_1_SLOT1;
+ break;
+ case 0xBC: /* Note 2 */
+ mux_config = SER_5_6_SLOT4 | SER_2_3_SFP23 | SER_0_1_SLOT1;
+ break;
+ case 0xCA:
+ case 0xF2: /* Note 2 */
+ case 0xF8:
+ case 0xFA:
+ case 0x70:
+ mux_config = SER_5_6_SLOT23 | SER_2_3_SFP23 | SER_0_1_SFP01;
+ break;
+ case 0xDE: /* Note 2 */
+ case 0xE0: /* Note 2 */
+ mux_config = SER_5_6_SLOT23 | SER_2_3_SLOT1 | SER_0_1_SLOT1;
+ break;
+#else
+#error "Invalid or unspecified target cpu for dragonfruit carrier board!"
+#endif
+ default:
+ printf("Unsupported SERDES configuration (%02x) detected for dragonfruit carrier board (Warning: Using default multiplexer settings)!\n", serdes_config);
+ }
+
+
+
+
+
+
+ printf("-----------------------------------------------------\n");
+ printf("Serdes lane configuration:\n");
+ if ((mux_config & 1) > 0) {
+ gpio_direction_output(MUX_SER0_1_SEL, 1);
+ printf("A: SFP slot 0 (T2081 only)\n");
+ printf("B: SFP slot 1\n");
+ } else {
+ gpio_direction_output(MUX_SER0_1_SEL, 0);
+ printf("A: PCIe slot 1 on lane 0\n");
+ printf("B: PCIe slot 1 on lane 1\n");
+ }
+
+ if ((mux_config & 2) > 0) {
+ gpio_direction_output(MUX_SER2_3_SEL, 1);
+ printf("C: SFP slot 2\n");
+ printf("D: SFP slot 3\n");
+ } else {
+ gpio_direction_output(MUX_SER2_3_SEL, 0);
+ printf("C: PCIe slot 1 on lane 2\n");
+ printf("D: PCIe slot 1 on lane 3\n");
+ }
+
+ printf("E: PCIe slot 4 on lane 0\n");
+
+ if ((mux_config & 4) > 0) {
+ gpio_direction_output(MUX_SER5_6_SEL, 1);
+ printf("F: PCIe slot 2 on lane 0\n");
+ printf("G: PCIe slot 3 on lane 0\n");
+ } else {
+ gpio_direction_output(MUX_SER5_6_SEL, 0);
+ printf("F: PCIe slot 4 on lane 1\n");
+ printf("G: PCIe slot 4 on lane 2\n");
+ }
+
+ printf("H: PCIe slot 4 on lane 3\n");
+ printf("-----------------------------------------------------\n");
+
+ /* Enable serdes clock */
+ gpio_direction_output(SERDES_CLK_OE, 1);
+
+ return ret;
+}
diff --git a/board/scalys/simc-t2081/dragonfruit.h b/board/scalys/simc-t2081/dragonfruit.h
new file mode 100644
index 0000000..554b2bf
--- /dev/null
+++ b/board/scalys/simc-t2081/dragonfruit.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DRAGON_FRUIT_H
+#define _DRAGON_FRUIT_H
+
+int scalys_carrier_setup_muxing(int serdes_config);
+
+#endif /* _DRAGON_FRUIT_H */
diff --git a/board/scalys/simc-t2081/eth.c b/board/scalys/simc-t2081/eth.c
new file mode 100644
index 0000000..c25a81c
--- /dev/null
+++ b/board/scalys/simc-t2081/eth.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <asm/immap_85xx.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fsl_dtsec.h>
+#include <vsc9953.h>
+#include <i2c.h>
+
+#include "../../freescale/common/fman.h"
+
+uint8_t sfp_phy_config[][2] = {
+ { 0x1b, 0x90 },
+ { 0x1b, 0x84 },
+ { 0x09, 0x0F },
+ { 0x09, 0x00 },
+ { 0x00, 0x81 },
+ { 0x00, 0x40 },
+};
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ struct memac_mdio_info memac_mdio_info;
+ unsigned int i;
+ uint8_t i2c_data;
+ int ret;
+ int phy_addr = 0;
+
+ uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
+ uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
+ uint32_t *gpio4_gpdir = (uint32_t *) 0xffe133000;
+ uint32_t *gpio4_gpdat = (uint32_t *) 0xffe133008;
+ uint32_t regval;
+
+ /* Try to read a byte from te carrier eeprom te determine if were on the correct carrier */
+ ret = i2c_read(0x54, 0, 2, &i2c_data, 1 );
+ if (ret != 0) {
+ printf("No dragonfruit carrier detected\n");
+ return 0;
+ }
+
+ printf("Initializing Fman\n");
+
+ memac_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+ memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the real 1G MDIO bus */
+ fm_memac_mdio_init(bis, &memac_mdio_info);
+
+ /* Marvell 88E1111 Setup
+ *
+ * Remove reset from Ethernet PHY's
+ *
+ * Carrier board v1.x:
+ * IFC_PERR_B : GPIO2_15 : eth1_reset
+ * IFC_CS_N2 : GPIO2_11 : eth2_reset
+ *
+ * Carrier board v2.x:
+ * IFC_PERR_B : GPIO2_15 : eth1_reset
+ * IFC_CS_N2 : GPIO4_09 : eth2_reset
+ *
+ * Note: make sure gpio pins are configured as gpio in RCW!
+ */
+
+#if 0
+ /* TODO: use EEPROM data to chose carrier board version */
+ /* Carrier board v1.x */
+ /* Clear outputs to activate reset */
+ regval = in_be32(gpio2_gpdat);
+ regval &= ~((0x80000000 >> 11 ) | (0x80000000 >> 15));
+ out_be32(gpio2_gpdat, regval);
+
+ /* Set outputs to output mode */
+ regval = in_be32(gpio2_gpdir);
+ regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15));
+ out_be32(gpio2_gpdir, regval);
+
+ /* Wait for 10 ms to to meet reset timing */
+ mdelay(10);
+
+ /* Set outputs to de-activate reset */
+ regval = in_be32(gpio2_gpdat);
+ regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15));
+ out_be32(gpio2_gpdat, regval);
+#else
+ /* Carrier board v2.x */
+ /* Clear outputs to activate reset */
+ regval = in_be32(gpio2_gpdat);
+ regval &= ~(0x80000000 >> 15);
+ out_be32(gpio2_gpdat, regval);
+ regval = in_be32(gpio4_gpdat);
+ regval &= ~(0x80000000 >> 9);
+ out_be32(gpio4_gpdat, regval);
+
+ /* Set outputs to output mode */
+ regval = in_be32(gpio2_gpdir);
+ regval |= (0x80000000 >> 15);
+ out_be32(gpio2_gpdir, regval);
+ regval = in_be32(gpio4_gpdir);
+ regval |= (0x80000000 >> 9);
+ out_be32(gpio4_gpdir, regval);
+
+ /* Wait for 10 ms to to meet reset timing */
+ mdelay(10);
+
+ /* Set outputs to de-activate reset */
+ regval = in_be32(gpio2_gpdat);
+ regval |= (0x80000000 >> 15);
+ out_be32(gpio2_gpdat, regval);
+ regval = in_be32(gpio4_gpdat);
+ regval |= (0x80000000 >> 9);
+ out_be32(gpio4_gpdat, regval);
+#endif
+
+ /* Write 0x4111 to reg 0x18 on both PHYs to change LEDs usage */
+ miiphy_write("FSL_MDIO0",0,0x18,0x4111);
+ miiphy_write("FSL_MDIO0",1,0x18,0x4111);
+
+ /* Remove SFP TX_disable */
+ i2c_set_bus_num(0);
+ ret = i2c_read(0x22, 0x0E, 1, &i2c_data, 1);
+ i2c_data &= ~0x04;
+ ret = i2c_write(0x22, 0x0E, 1, &i2c_data, 1);
+
+ mdelay(100);
+
+ i2c_set_bus_num(3);
+
+ for (phy_addr=0; phy_addr<4; phy_addr++) {
+ i2c_data = (1 << phy_addr);
+ ret = i2c_write(0x70, 0, 1, &i2c_data, 1);
+ if (ret) {
+ printf("Error Setting SFP i2c MUX\n");
+ break;
+ }
+
+ for ( i = 0; i < 6; i++) {
+ ret = i2c_write(0x56, sfp_phy_config[i][0], 1, &(sfp_phy_config[i][1]), 1);
+ if (ret) {
+ printf("Error sfp phy(%i:%i):%02x to address %02x\n", phy_addr, i, sfp_phy_config[i][1],sfp_phy_config[i][0]);
+ break;
+ }
+ }
+ }
+
+ /* Two external pin interfaces
+ * MAC1|MAC2|MAC3 SGMII interface
+ * MAC3|MAC4|MAC10 EC1|EC2 RGMII interface
+ */
+
+ /*
+ * Program on board RGMII, SGMII PHY addresses.
+ */
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ int idx = i - FM1_DTSEC1;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_RGMII:
+ if (FM1_DTSEC3 == i)
+ phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
+ if (FM1_DTSEC4 == i)
+ phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
+ /*if (FM1_DTSEC10 == i)
+ phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;*/
+ fm_info_set_phy_address(i, phy_addr);
+ break;
+ case PHY_INTERFACE_MODE_QSGMII:
+ /* TODO, get fixed phy here */
+ fm_info_set_phy_address(i, i+2);
+ break;
+ case PHY_INTERFACE_MODE_NONE:
+ fm_info_set_phy_address(i, 0);
+ break;
+ case PHY_INTERFACE_MODE_SGMII:
+ printf("TODO, add phy interface to SGMII\n");
+ fm_info_set_phy_address(i, PHY_INTERFACE_MODE_NONE);
+ break;
+ default:
+ printf("Fman1: DTSEC%u set to unknown interface %i\n",
+ idx + 1, fm_info_get_enet_if(i));
+ //fm_info_set_phy_address(i, 0);
+ break;
+ }
+ fm_info_set_mdio(i,
+ miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+ }
+
+ cpu_eth_init(bis);
+#endif
+ return pci_eth_init(bis);
+}
+
+/*void fdt_fixup_board_enet(void *fdt)
+{
+ return;
+}*/
diff --git a/board/scalys/simc-t2081/law.c b/board/scalys/simc-t2081/law.c
new file mode 100644
index 0000000..cc03808a
--- /dev/null
+++ b/board/scalys/simc-t2081/law.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SYS_NO_FLASH
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/scalys/simc-t2081/pci.c b/board/scalys/simc-t2081/pci.c
new file mode 100644
index 0000000..9a02f90
--- /dev/null
+++ b/board/scalys/simc-t2081/pci.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+
+ uint32_t *gpio1_gpdir = (uint32_t *) 0xffe130000;
+ uint32_t *gpio1_gpdat = (uint32_t *) 0xffe130008;
+ uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
+ uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
+ uint32_t regval;
+
+ /*debug("%s\n", __FUNCTION__);*/
+
+ /*TODO, when present pins are available on the board, use them to enable only active slots*/
+
+#if 0
+ /* Dragonfruit Carrier board 1.x */
+
+
+ /*
+ * IRQ[0-3] : PCIe present detect signals
+ * IRQ[0] : SLOT1_PRSNT2_N : XXX
+ * IRQ[1] : SLOT2_PRSNT2_N : XXX
+ * IRQ[2] : SLOT3_PRSNT2_N : XXX
+ * IRQ[3] : SLOT4_PRSNT2_N : XXX
+ *
+ * Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7
+ * IFC_CS_N4 : GPIO1_IO09 : PCIe SLOT1_REFCLK_OE_N
+ * IFC_CS_N5 : GPIO1_IO10 : PCIe SLOT2_REFCLK_OE_N
+ * IFC_CS_N6 : GPIO1_IO11 : PCIe SLOT3_REFCLK_OE_N
+ * IFC_CS_N7 : GPIO1_IO12 : PCIe SLOT4_REFCLK_OE_N
+ */
+
+ /* Set output to 0 to enable reference clocks */
+ regval = in_be32(gpio1_gpdat);
+ regval &= ~( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) );
+ out_be32(gpio1_gpdat, regval);
+
+ /* Set Enable outputs*/
+ regval = in_be32(gpio1_gpdir);
+ regval |= ( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) );
+ out_be32(gpio1_gpdir, regval);
+
+#else
+ /* Dragonfruit Carrier board 2.x */
+ /*
+ * PCIe present detect signals:
+ * IRQ[3] : GPIO1_23 : SLOT1_PRSNT2_N
+ * IRQ[4] : GPIO1_24 : SLOT2_PRSNT2_N
+ * IRQ[5] : GPIO1_25 : SLOT3_PRSNT2_N
+ * IRQ[10] : GPIO1_30 : SLOT4_PRSNT2_N
+ *
+ * Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7
+ * IFC_CS_N7 : GPIO1_IO12 : PCIe SLOT4_REFCLK_OE_N (used for all 4 slots)
+ * IFC_PAR1 : GPIO2_14 : PEX_REFCLK_SEL
+ */
+
+ /* Set output to 0 to enable reference clocks */
+ regval = in_be32(gpio1_gpdat);
+ regval &= ~( 0x80000000 >> 12 );
+ out_be32(gpio1_gpdat, regval);
+
+ /* Set Enable outputs */
+ regval = in_be32(gpio1_gpdir);
+ regval |= ( 0x80000000 >> 12 );
+ out_be32(gpio1_gpdir, regval);
+
+ /* Set PEX_REFCLK_SEL to 0 to select CLK0 */
+
+ /* Set IFC_PAR1 to output mode */
+ regval = in_be32(gpio2_gpdir);
+ regval |= ( 0x80000000 >> 14 );
+ out_be32(gpio2_gpdir, regval);
+
+ /* Set output to 0 to select clock source 0 */
+ regval = in_be32(gpio2_gpdat);
+ regval &= ~( 0x80000000 >> 14 );
+ out_be32(gpio2_gpdat, regval);
+
+#endif
+
+ /*
+ * IFC_PAR0 : GPIO2_13 : PEX_PERST_N
+ */
+
+ /* Remove reset from PCIe devices */
+
+ /* Set IFC_PAR0 to output mode */
+ regval = in_be32(gpio2_gpdir);
+ regval |= ( 0x80000000 >> 13 );
+ out_be32(gpio2_gpdir, regval);
+
+ /* Set output to 1 to clear reset */
+ regval = in_be32(gpio2_gpdat);
+ regval |= ( 0x80000000 >> 13 );
+ out_be32(gpio2_gpdat, regval);
+
+ /* Wait for 100 ms to allow the PCIe device to become ready */
+ mdelay(100);
+
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/scalys/simc-t2081/simc-t2081.c b/board/scalys/simc-t2081/simc-t2081.c
new file mode 100644
index 0000000..f07a36f
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <asm/fsl_pci.h>
+#include <fm_eth.h>
+#include <asm/processor.h>
+#include <asm/gpio.h>
+#include <fsl_esdhc.h>
+#include <dm.h>
+#include "dragonfruit.h"
+#include <board_configuration_data.h>
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ printf("Board: simc-t2081\n" );
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ const void* bcd_dtc_blob;
+ int serdes_config;
+ ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int ret;
+
+ debug("t2081: misc_init_r\n");
+ /*
+ * Initialize and set the LED's on the module to indicate u-boot is alive
+ * IFC_A30 : led green : GPIO2_30
+ * IFC_A31 : led red : GPIO2_31
+ */
+ #define MODULE_LED_RED MPC85XX_GPIO_NR(2, 31)
+ #define MODULE_LED_GREEN MPC85XX_GPIO_NR(2, 30)
+ gpio_request(MODULE_LED_RED, "module_led_red");
+ gpio_request(MODULE_LED_GREEN, "module_led_green");
+
+ gpio_direction_output(MODULE_LED_RED, 0);
+ gpio_direction_output(MODULE_LED_GREEN, 1);
+
+ /* SERDES configuration is determined boot time through the RCW config.
+ * It is located in the fourth RCW word (bit 128-135 of the RCW). */
+ serdes_config = ( in_be32(&gur->rcwsr[4]) >> 24);
+ scalys_carrier_setup_muxing(serdes_config);
+
+ bcd_dtc_blob = get_boardinfo_eeprom();
+ if (bcd_dtc_blob != NULL) {
+ /* Board Configuration Data is intact, ready for parsing */
+ ret = add_mac_addressess_to_env(bcd_dtc_blob);
+ if (ret != 0) {
+ printf("Error adding BCD data to environement\n");
+ }
+ }
+
+ return 0;
+}
+
+/* Platform data for the GPIOs */
+static const struct mpc85xx_gpio_plat gpio_platdata[] = {
+ { .addr = 0x130000, .ngpios = 32 },
+ { .addr = 0x131000, .ngpios = 32 },
+ { .addr = 0x132000, .ngpios = 32 },
+ { .addr = 0x133000, .ngpios = 32,},
+};
+
+U_BOOT_DEVICES(mpc85xx_gpios) = {
+ { "gpio_mpc85xx", &gpio_platdata[0] },
+ { "gpio_mpc85xx", &gpio_platdata[1] },
+ { "gpio_mpc85xx", &gpio_platdata[2] },
+ { "gpio_mpc85xx", &gpio_platdata[3] },
+};
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ debug( "t2081: ft_board_setup\n" );
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ debug( "fdt_fixup_memory\n" );
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ debug( "pci_of_setup\n" );
+ FT_FSL_PCI_SETUP;
+#endif
+ debug( "fdt_fixup_liodn\n" );
+ fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ debug( "fsl_fdt_fixup_dr_usb\n" );
+ fsl_fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ debug( "fdt_fixup_fman_ethernet\n" );
+ fdt_fixup_fman_ethernet(blob);
+#endif
+
+ return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ struct fsl_esdhc_cfg *cfg;
+
+ cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
+ cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+ cfg->sdhc_clk = gd->arch.sdhc_clk;
+ cfg->max_bus_width = 4;
+ return fsl_esdhc_initialize(bis, cfg);
+
+ return 0;
+}
+
+#if 0
+void board_detail(void)
+{
+ do_bcdinfo();
+}
+#endif
diff --git a/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg b/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg
new file mode 100644
index 0000000..e3ed70b
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg
@@ -0,0 +1,44 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fffc0009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1 (LAW 13)
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure IFC controller
+# (IFC_CSPR1)
+09124010 ff8000c3
+# IFC_CSOR_NAND
+09124130 85084101
+# IFC_FTIM0_CS0_NAND to IFC_FTIM0_CS0_NAND
+091241c0 181c080c
+091241c4 3850141a
+091241c8 03008028
+091241cc 28000000
+# Set IFC_CCR clkdiv to 2 (=/3) to get:
+# (platform clock/2/3=83.3MHz)
+0912444c 02008000
+#Flush PBL data (Wait 0xFFFFF cycles )
+091380c0 000fffff
diff --git a/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg b/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
new file mode 100644
index 0000000..2746cf4
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
@@ -0,0 +1,20 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+#0a06000c 0c000000 00000000 00000000
+#aa000002 00004000 e8105000 21000000
+#00000000 cafebabe 00000000 00030ffc
+#00000314 0000000c 00000000 00000001
+#
+
+# #SerDes=0xaa, Core:1200MHz, DDR:1600MT/s
+# 0a06000c 0c000000 00000000 00000000
+# 66000002 00404000 e8105000 21000000
+# 00000000 cafebabe 00000000 00030ffc
+# 00000314 00000008 00000000 00000001
+
+
+0c06000c 0c000000 00000000 00000000
+aa000002 40404000 e8105000 21000000
+00000000 cafebabe 00000000 00030ffc
+00000314 80000009 00000000 00000001
diff --git a/board/scalys/simc-t2081/simc-t2081_nor_pbi.cfg b/board/scalys/simc-t2081/simc-t2081_nor_pbi.cfg
new file mode 100644
index 0000000..fd38b58
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_nor_pbi.cfg
@@ -0,0 +1,31 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fffc0009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1 (LAW 13)
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data (Wait 0xFFFFF cycles )
+091380c0 000fffff
diff --git a/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg b/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg
new file mode 100644
index 0000000..d8ac2bd
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+0c06000c 0c000000 00000000 00000000
+aa000002 40404000 e8023000 21000000
+00000000 cafebabe 00000000 00030ffc
+00000314 80000009 00000000 00000001
+
diff --git a/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg b/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg
new file mode 100644
index 0000000..fd38b58
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg
@@ -0,0 +1,31 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fffc0009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1 (LAW 13)
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data (Wait 0xFFFFF cycles )
+091380c0 000fffff
diff --git a/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg b/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg
new file mode 100644
index 0000000..f06629c
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg
@@ -0,0 +1,18 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+
+#SerDes=0xaa, Core:1200MHz, DDR:1600MT/s
+# 0a06000c 0c000000 00000000 00000000
+# 66000002 00404000 68105000 21000000
+# 00000000 cafebabe 00000000 00030ffc
+# 00000314 00000008 00000000 00000001
+
+# 0c06000c 0c000000 00000000 00000000
+# 66000002 40404000 68105000 21000000
+# 00000000 cafebabe 00000000 00030ffc
+# 00000314 80000008 00000000 00000001
+
+0c06000c 0c000000 00000000 00000000
+aa000002 40404000 68105000 21000000
+00000000 cafebabe 00000000 00030ffc
+00000314 80000009 00000000 00000001
diff --git a/board/scalys/simc-t2081/spl.c b/board/scalys/simc-t2081/spl.c
new file mode 100644
index 0000000..f0fb9dd
--- /dev/null
+++ b/board/scalys/simc-t2081/spl.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <console.h>
+#include <nand.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+ return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ return CONFIG_DDR_CLK_FREQ;
+}
+
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio, sys_clk, uart_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+ /* Update GD pointer */
+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+ /* compiler optimization barrier needed for GCC >= 3.4 */
+ __asm__ __volatile__("" : : : "memory");
+
+ console_init_f();
+
+ /* initialize selected port with appropriate baud rate */
+ sys_clk = get_board_sys_clk();
+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+ uart_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ uart_clk / 16 / CONFIG_BAUDRATE);
+
+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void setup_ifc_nand(enum ifc_chip_sel cs)
+{
+ set_ifc_cspr_ext(cs, CONFIG_SYS_NAND_CSPR_EXT);
+ set_ifc_csor (cs, CONFIG_SYS_NAND_CSOR);
+ set_ifc_amask (cs, CONFIG_SYS_NAND_AMASK);
+ set_ifc_cspr (cs, CONFIG_SYS_NAND_CSPR);
+ set_ifc_ftim (cs, IFC_FTIM0, CONFIG_SYS_NAND_FTIM0);
+ set_ifc_ftim (cs, IFC_FTIM1, CONFIG_SYS_NAND_FTIM1);
+ set_ifc_ftim (cs, IFC_FTIM2, CONFIG_SYS_NAND_FTIM2);
+ set_ifc_ftim (cs, IFC_FTIM3, CONFIG_SYS_NAND_FTIM3);
+ set_ifc_csor_ext(cs, 0);
+
+}
+
+void setup_ifc_nor(enum ifc_chip_sel cs)
+{
+ set_ifc_cspr_ext(cs, CONFIG_SYS_NOR_CSPR_EXT);
+ set_ifc_csor (cs, CONFIG_SYS_NOR_CSOR);
+ set_ifc_amask (cs, CONFIG_SYS_NOR_AMASK);
+ set_ifc_cspr (cs, CONFIG_SYS_NOR_CSPR);
+ set_ifc_ftim (cs, IFC_FTIM0, CONFIG_SYS_NOR_FTIM0);
+ set_ifc_ftim (cs, IFC_FTIM1, CONFIG_SYS_NOR_FTIM1);
+ set_ifc_ftim (cs, IFC_FTIM2, CONFIG_SYS_NOR_FTIM2);
+ set_ifc_ftim (cs, IFC_FTIM3, CONFIG_SYS_NOR_FTIM3);
+ set_ifc_csor_ext(cs, 0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ bd_t *bd;
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ uint32_t boot_source;
+
+ __attribute__((noreturn)) void (*boot)(void) = hang;
+
+ bd = (bd_t *)(gd + sizeof(gd_t));
+ memset(bd, 0, sizeof(bd_t));
+ gd->bd = bd;
+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+ arch_cpu_init();
+ get_clocks();
+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+ CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd->env_valid = 1;
+
+ gd->ram_size = dram_init();
+
+ /* Get the boot source from the Power On Status Register (set by QSC) */
+ boot_source = (in_be32(&gur->porsr1) >> 23);
+
+ switch (boot_source) {
+ case 0x23:
+ /* NOR boot */
+ setup_ifc_nor(IFC_CS0);
+ setup_ifc_nand(IFC_CS1);
+
+ memcpy((void*)CONFIG_SYS_NAND_U_BOOT_DST, (void*) CONFIG_SYS_FLASH_BASE + CONFIG_SPL_PAD_TO, CONFIG_SYS_NAND_U_BOOT_SIZE);
+
+ flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+ boot = (void*) CONFIG_SYS_NAND_U_BOOT_START;
+ break;
+
+ case 0x45:
+#if 0
+ /*SPI nor flash */
+ setup_ifc_nand(IFC_CS0);
+ setup_ifc_nor(IFC_CS1);
+ //fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, (uchar *)CONFIG_ENV_ADDR);
+ {
+ struct spi_flash *flash;
+
+ flash = spi_flash_probe(0, 0,
+ CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
+ if (flash == NULL) {
+ puts("\nspi_flash_probe failed");
+ hang();
+ }
+
+ spi_flash_read(flash, CONFIG_SPL_PAD_TO, CONFIG_SYS_NAND_U_BOOT_SIZE, (void*) CONFIG_SYS_NAND_U_BOOT_DST);
+ }
+#endif
+ printf("TODO, load u-boot from SPI....\n");
+ hang();
+ break;
+ case 0x40:
+ /* SD/MMC (eSDHC) boot */
+ #ifdef CONFIG_SPL_MMC_BOOT
+ setup_ifc_nand(IFC_CS0);
+ setup_ifc_nor(IFC_CS1);
+
+ mmc_initialize(bd);
+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ boot = mmc_boot;
+ #endif
+ break;
+ case 0x105:
+ /* NAND boot */
+ setup_ifc_nand(IFC_CS0);
+ setup_ifc_nor(IFC_CS1);
+
+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ boot = nand_boot;
+ break;
+ default:
+ printf("Unknown boot source (%3x\n", boot_source);
+ break;
+ }
+ boot();
+}
diff --git a/board/scalys/simc-t2081/tlb.c b/board/scalys/simc-t2081/tlb.c
new file mode 100644
index 0000000..c03282e
--- /dev/null
+++ b/board/scalys/simc-t2081/tlb.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
+ !defined(CONFIG_SECURE_BOOT)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 512K SRAM, the address of the
+ * SRAM is at 0xfffc0000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_512K, 1),
+#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 512K SRAM, in case of Secure Boot
+ * the physical address of the SRAM is at 0xbffc0000,
+ * and virtual address is 0xfffc0000
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR,
+ CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_512K, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_64M, 1), /* modified to simc-t1040 equivalent */
+
+#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_PCI
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256K, 1),
+#endif
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 5, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 12, BOOKE_PAGESZ_1G, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 13, BOOKE_PAGESZ_1G, 1)
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
generated by cgit v0.10.2 at 2024-06-01 08:59:00 (GMT)