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-rw-r--r--board/scalys/simc-t10xx/Kconfig2
-rw-r--r--board/scalys/simc-t10xx/dragonfruit.c45
-rw-r--r--board/scalys/simc-t10xx/qt1040-1gb_nand_rcw.cfg2
-rw-r--r--board/scalys/simc-t10xx/qt1040-1gb_nor_rcw.cfg2
-rw-r--r--board/scalys/simc-t10xx/qt1040-1gb_sdhc_rcw.cfg2
-rw-r--r--board/scalys/simc-t10xx/qt1040-1gb_spi_rcw.cfg2
-rw-r--r--board/scalys/simc-t10xx/spl.c4
-rw-r--r--board/scalys/simc-t2081/dragonfruit.c53
-rw-r--r--board/scalys/simc-t2081/eth.c44
-rw-r--r--board/scalys/simc-t2081/law.c9
-rw-r--r--board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg4
-rw-r--r--board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg33
-rw-r--r--board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg9
-rw-r--r--board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg2
-rw-r--r--board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg21
-rw-r--r--board/scalys/simc-t2081/spl.c4
-rw-r--r--board/scalys/simc-t2081/tlb.c47
17 files changed, 184 insertions, 101 deletions
diff --git a/board/scalys/simc-t10xx/Kconfig b/board/scalys/simc-t10xx/Kconfig
index 4ac5c59..a82d91d 100644
--- a/board/scalys/simc-t10xx/Kconfig
+++ b/board/scalys/simc-t10xx/Kconfig
@@ -1,4 +1,4 @@
-if (TARGET_SIMC_TXXXX || TARGET_QT1040_1GB) && !ARCH_T2081
+if ((TARGET_SIMC_TXXXX && !ARCH_T2081) || TARGET_QT1040_1GB)
config SYS_BOARD
string
diff --git a/board/scalys/simc-t10xx/dragonfruit.c b/board/scalys/simc-t10xx/dragonfruit.c
index c8e5a13..80235fe 100644
--- a/board/scalys/simc-t10xx/dragonfruit.c
+++ b/board/scalys/simc-t10xx/dragonfruit.c
@@ -11,16 +11,20 @@
#include "dragonfruit.h"
+uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
+uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
+uint32_t regval;
+
/*
* SERDER MUX Configuration pins:
* IFC_A25 : GPIO2_25 : SERDES_CLK_ MUX_SER0_1_SEL
* IFC_A26 : GPIO2_26 : SERDES_CLK_ MUX_SER2_3_SEL
* IFC_A27 : GPIO2_27 : SERDES_CLK_ MUX_SER5_6_SEL
*/
-#define MUX_SER0_1_SEL MPC85XX_GPIO_NR(2, 25)
-#define MUX_SER2_3_SEL MPC85XX_GPIO_NR(2, 26)
-#define MUX_SER5_6_SEL MPC85XX_GPIO_NR(2, 27)
-#define SERDES_CLK_OE MPC85XX_GPIO_NR(2, 29)
+#define MUX_SER0_1_SEL (0x80000000 >> 25)
+#define MUX_SER2_3_SEL (0x80000000 >> 26)
+#define MUX_SER5_6_SEL (0x80000000 >> 27)
+#define SERDES_CLK_OE (0x80000000 >> 29)
/*
* MUX_SER0_1_SEL
@@ -150,21 +154,29 @@ int scalys_carrier_setup_muxing(int serdes_config)
printf("-----------------------------------------------------\n");
printf("Serdes lane configuration:\n");
if ((mux_config & 1) > 0) {
- gpio_direction_output(MUX_SER0_1_SEL, 1);
+ regval = in_be32(gpio2_gpdat);
+ regval |= MUX_SER0_1_SEL;
+ out_be32(gpio2_gpdat, regval);
printf("A: SFP slot 0 (T2081 only)\n");
printf("B: SFP slot 1\n");
} else {
- gpio_direction_output(MUX_SER0_1_SEL, 0);
+ regval = in_be32(gpio2_gpdat);
+ regval &= ~MUX_SER0_1_SEL;
+ out_be32(gpio2_gpdat, regval);
printf("A: PCIe slot 1 on lane 0\n");
printf("B: PCIe slot 1 on lane 1\n");
}
if ((mux_config & 2) > 0) {
- gpio_direction_output(MUX_SER2_3_SEL, 1);
+ regval = in_be32(gpio2_gpdat);
+ regval |= MUX_SER2_3_SEL;
+ out_be32(gpio2_gpdat, regval);
printf("C: SFP slot 2\n");
printf("D: SFP slot 3\n");
} else {
- gpio_direction_output(MUX_SER2_3_SEL, 0);
+ regval = in_be32(gpio2_gpdat);
+ regval &= ~MUX_SER2_3_SEL;
+ out_be32(gpio2_gpdat, regval);
printf("C: PCIe slot 1 on lane 2\n");
printf("D: PCIe slot 1 on lane 3\n");
}
@@ -172,11 +184,15 @@ int scalys_carrier_setup_muxing(int serdes_config)
printf("E: PCIe slot 4 on lane 0\n");
if ((mux_config & 4) > 0) {
- gpio_direction_output(MUX_SER5_6_SEL, 1);
+ regval = in_be32(gpio2_gpdat);
+ regval |= MUX_SER5_6_SEL;
+ out_be32(gpio2_gpdat, regval);
printf("F: PCIe slot 2 on lane 0\n");
printf("G: PCIe slot 3 on lane 0\n");
} else {
- gpio_direction_output(MUX_SER5_6_SEL, 0);
+ regval = in_be32(gpio2_gpdat);
+ regval &= ~MUX_SER5_6_SEL;
+ out_be32(gpio2_gpdat, regval);
printf("F: PCIe slot 4 on lane 1\n");
printf("G: PCIe slot 4 on lane 2\n");
}
@@ -185,7 +201,14 @@ int scalys_carrier_setup_muxing(int serdes_config)
printf("-----------------------------------------------------\n");
/* Enable serdes clock */
- gpio_direction_output(SERDES_CLK_OE, 1);
+ regval = in_be32(gpio2_gpdat);
+ regval |= SERDES_CLK_OE;
+ out_be32(gpio2_gpdat, regval);
+
+ /* Set outputs to output mode */
+ regval = in_be32(gpio2_gpdir);
+ regval |= (MUX_SER0_1_SEL | MUX_SER2_3_SEL | MUX_SER5_6_SEL | SERDES_CLK_OE);
+ out_be32(gpio2_gpdir, regval);
return ret;
}
diff --git a/board/scalys/simc-t10xx/qt1040-1gb_nand_rcw.cfg b/board/scalys/simc-t10xx/qt1040-1gb_nand_rcw.cfg
index 48b9f68..87ec66f 100644
--- a/board/scalys/simc-t10xx/qt1040-1gb_nand_rcw.cfg
+++ b/board/scalys/simc-t10xx/qt1040-1gb_nand_rcw.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
AA55AA55 010E0100
-0c0a000c 0c000000 00000000 00000000
+0a0a000c 0c000000 00000000 00000000
81000002 40000002 e8105000 21000000
00000000 cafebabe 00000000 00030ffc
00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/qt1040-1gb_nor_rcw.cfg b/board/scalys/simc-t10xx/qt1040-1gb_nor_rcw.cfg
index 5cf027e..9fd7e93 100644
--- a/board/scalys/simc-t10xx/qt1040-1gb_nor_rcw.cfg
+++ b/board/scalys/simc-t10xx/qt1040-1gb_nor_rcw.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
AA55AA55 010E0100
#
-0c0a000c 0c000000 00000000 00000000
+0a0a000c 0c000000 00000000 00000000
81000002 40000002 e8023000 21000000
00000000 cafebabe 00000000 00030ffc
00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/qt1040-1gb_sdhc_rcw.cfg b/board/scalys/simc-t10xx/qt1040-1gb_sdhc_rcw.cfg
index b5cc904..43b7304 100644
--- a/board/scalys/simc-t10xx/qt1040-1gb_sdhc_rcw.cfg
+++ b/board/scalys/simc-t10xx/qt1040-1gb_sdhc_rcw.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
AA55AA55 010E0100
#
-0c0a000c 0c000000 00000000 00000000
+0a0a000c 0c000000 00000000 00000000
81000002 40000002 68105000 21000000
00000000 cafebabe 00000000 00030ffc
00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/qt1040-1gb_spi_rcw.cfg b/board/scalys/simc-t10xx/qt1040-1gb_spi_rcw.cfg
index dfc4250..6cede86 100644
--- a/board/scalys/simc-t10xx/qt1040-1gb_spi_rcw.cfg
+++ b/board/scalys/simc-t10xx/qt1040-1gb_spi_rcw.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
AA55AA55 010E0100
#
-0c0a000c 0c000000 00000000 00000000
+0a0a000c 0c000000 00000000 00000000
81000002 40000002 58105000 21000000
00000000 cafebabe 00000000 00030ffc
00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/spl.c b/board/scalys/simc-t10xx/spl.c
index c861284..cfb6e04 100644
--- a/board/scalys/simc-t10xx/spl.c
+++ b/board/scalys/simc-t10xx/spl.c
@@ -152,7 +152,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
break;
case 0x40:
/* SD/MMC (eSDHC) boot */
- #ifdef CONFIG_SPL_MMC_BOOT
+#if defined(CONFIG_SPL_MMC_BOOT) || defined(CONFIG_SDHC_FLASH_BOOT)
setup_ifc_nand(IFC_CS0);
setup_ifc_nor(IFC_CS1);
@@ -160,7 +160,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
boot = mmc_boot;
- #endif
+#endif
break;
case 0x105:
/* NAND boot */
diff --git a/board/scalys/simc-t2081/dragonfruit.c b/board/scalys/simc-t2081/dragonfruit.c
index 286b2c2..a2d6653 100644
--- a/board/scalys/simc-t2081/dragonfruit.c
+++ b/board/scalys/simc-t2081/dragonfruit.c
@@ -9,16 +9,20 @@
#include <asm/gpio.h>
#include "dragonfruit.h"
+uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
+uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
+uint32_t regval;
+
/*
* SERDER MUX Configuration pins:
* IFC_A25 : GPIO2_25 : SERDES_CLK_ MUX_SER0_1_SEL
* IFC_A26 : GPIO2_26 : SERDES_CLK_ MUX_SER2_3_SEL
* IFC_A27 : GPIO2_27 : SERDES_CLK_ MUX_SER5_6_SEL
*/
-#define MUX_SER0_1_SEL MPC85XX_GPIO_NR(2, 25)
-#define MUX_SER2_3_SEL MPC85XX_GPIO_NR(2, 26)
-#define MUX_SER5_6_SEL MPC85XX_GPIO_NR(2, 27)
-#define SERDES_CLK_OE MPC85XX_GPIO_NR(2, 29)
+#define MUX_SER0_1_SEL (0x80000000 >> 25)
+#define MUX_SER2_3_SEL (0x80000000 >> 26)
+#define MUX_SER5_6_SEL (0x80000000 >> 27)
+#define SERDES_CLK_OE (0x80000000 >> 29)
/*
* MUX_SER0_1_SEL
@@ -80,9 +84,6 @@ int scalys_carrier_setup_muxing(int serdes_config)
* Note: The SERDES lanes A&B, C&D, and F&G can only be switched
* as pairs using the multiplexers. Which means some SERDES options are only partly usable.
*
- * Note 2/TODO: SERDES PLL2 must be powered down using SRDS_PLL_PD_S1 when
- * SRDS_PRTCL_S1 is any of the following values: 0x00, 0x40, 0x60, 0x67,
- * 0x85, 0x87, 0x8D, 0x45.
*
* T2081 has 8 SERDES lanes at up to 10GHz (ie. SERDES 2 configurations are DNC)
*
@@ -120,29 +121,32 @@ int scalys_carrier_setup_muxing(int serdes_config)
printf("Unsupported SERDES configuration (%02x) detected for dragonfruit carrier board (Warning: Using default multiplexer settings)!\n", serdes_config);
}
-
-
-
-
-
printf("-----------------------------------------------------\n");
printf("Serdes lane configuration:\n");
if ((mux_config & 1) > 0) {
- gpio_direction_output(MUX_SER0_1_SEL, 1);
+ regval = in_be32(gpio2_gpdat);
+ regval |= MUX_SER0_1_SEL;
+ out_be32(gpio2_gpdat, regval);
printf("A: SFP slot 0 (T2081 only)\n");
printf("B: SFP slot 1\n");
} else {
- gpio_direction_output(MUX_SER0_1_SEL, 0);
+ regval = in_be32(gpio2_gpdat);
+ regval &= ~MUX_SER0_1_SEL;
+ out_be32(gpio2_gpdat, regval);
printf("A: PCIe slot 1 on lane 0\n");
printf("B: PCIe slot 1 on lane 1\n");
}
if ((mux_config & 2) > 0) {
- gpio_direction_output(MUX_SER2_3_SEL, 1);
+ regval = in_be32(gpio2_gpdat);
+ regval |= MUX_SER2_3_SEL;
+ out_be32(gpio2_gpdat, regval);
printf("C: SFP slot 2\n");
printf("D: SFP slot 3\n");
} else {
- gpio_direction_output(MUX_SER2_3_SEL, 0);
+ regval = in_be32(gpio2_gpdat);
+ regval &= ~MUX_SER2_3_SEL;
+ out_be32(gpio2_gpdat, regval);
printf("C: PCIe slot 1 on lane 2\n");
printf("D: PCIe slot 1 on lane 3\n");
}
@@ -150,11 +154,15 @@ int scalys_carrier_setup_muxing(int serdes_config)
printf("E: PCIe slot 4 on lane 0\n");
if ((mux_config & 4) > 0) {
- gpio_direction_output(MUX_SER5_6_SEL, 1);
+ regval = in_be32(gpio2_gpdat);
+ regval |= MUX_SER5_6_SEL;
+ out_be32(gpio2_gpdat, regval);
printf("F: PCIe slot 2 on lane 0\n");
printf("G: PCIe slot 3 on lane 0\n");
} else {
- gpio_direction_output(MUX_SER5_6_SEL, 0);
+ regval = in_be32(gpio2_gpdat);
+ regval &= ~MUX_SER5_6_SEL;
+ out_be32(gpio2_gpdat, regval);
printf("F: PCIe slot 4 on lane 1\n");
printf("G: PCIe slot 4 on lane 2\n");
}
@@ -163,7 +171,14 @@ int scalys_carrier_setup_muxing(int serdes_config)
printf("-----------------------------------------------------\n");
/* Enable serdes clock */
- gpio_direction_output(SERDES_CLK_OE, 1);
+ regval = in_be32(gpio2_gpdat);
+ regval |= SERDES_CLK_OE;
+ out_be32(gpio2_gpdat, regval);
+
+ /* Set outputs to output mode */
+ regval = in_be32(gpio2_gpdir);
+ regval |= (MUX_SER0_1_SEL | MUX_SER2_3_SEL | MUX_SER5_6_SEL | SERDES_CLK_OE);
+ out_be32(gpio2_gpdir, regval);
return ret;
}
diff --git a/board/scalys/simc-t2081/eth.c b/board/scalys/simc-t2081/eth.c
index c25a81c..10c59f8 100644
--- a/board/scalys/simc-t2081/eth.c
+++ b/board/scalys/simc-t2081/eth.c
@@ -30,7 +30,8 @@ uint8_t sfp_phy_config[][2] = {
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
- struct memac_mdio_info memac_mdio_info;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
unsigned int i;
uint8_t i2c_data;
int ret;
@@ -51,12 +52,19 @@ int board_eth_init(bd_t *bis)
printf("Initializing Fman\n");
- memac_mdio_info.regs =
+ dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
- memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the real 1G MDIO bus */
- fm_memac_mdio_init(bis, &memac_mdio_info);
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Marvell 88E1111 Setup
*
@@ -155,7 +163,6 @@ int board_eth_init(bd_t *bis)
}
/* Two external pin interfaces
- * MAC1|MAC2|MAC3 SGMII interface
* MAC3|MAC4|MAC10 EC1|EC2 RGMII interface
*/
@@ -174,10 +181,9 @@ int board_eth_init(bd_t *bis)
phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;*/
fm_info_set_phy_address(i, phy_addr);
break;
- case PHY_INTERFACE_MODE_QSGMII:
- /* TODO, get fixed phy here */
+/* case PHY_INTERFACE_MODE_QSGMII:
fm_info_set_phy_address(i, i+2);
- break;
+ break;*/
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
break;
@@ -191,8 +197,22 @@ int board_eth_init(bd_t *bis)
//fm_info_set_phy_address(i, 0);
break;
}
- fm_info_set_mdio(i,
- miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+ fm_info_set_mdio(i, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+ }
+
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
+ break;
+ case PHY_INTERFACE_MODE_NONE:
+ fm_info_set_phy_address(i, 0);
+ default:
+ break;
+ }
+ fm_info_set_mdio(i, miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
}
cpu_eth_init(bis);
@@ -200,7 +220,7 @@ int board_eth_init(bd_t *bis)
return pci_eth_init(bis);
}
-/*void fdt_fixup_board_enet(void *fdt)
+void fdt_fixup_board_enet(void *fdt)
{
return;
-}*/
+}
diff --git a/board/scalys/simc-t2081/law.c b/board/scalys/simc-t2081/law.c
index cc03808a..ec8ed07 100644
--- a/board/scalys/simc-t2081/law.c
+++ b/board/scalys/simc-t2081/law.c
@@ -12,17 +12,19 @@
#include <asm/mmu.h>
struct law_entry law_table[] = {
-#ifndef CONFIG_SYS_NO_FLASH
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
-#endif
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
#endif
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
+/*#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+ SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif*/
#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
@@ -30,3 +32,4 @@ struct law_entry law_table[] = {
};
int num_law_entries = ARRAY_SIZE(law_table);
+
diff --git a/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg b/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg
index e3ed70b..9b0a4d6 100644
--- a/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg
+++ b/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg
@@ -38,7 +38,9 @@
091241c8 03008028
091241cc 28000000
# Set IFC_CCR clkdiv to 2 (=/3) to get:
-# (platform clock/2/3=83.3MHz)
+# (platform clock/2/3
0912444c 02008000
+#Write clk_out reg (platform clock/2)
+#090E1A00 0001D800
#Flush PBL data (Wait 0xFFFFF cycles )
091380c0 000fffff
diff --git a/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg b/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
index 2746cf4..88dc8ab 100644
--- a/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
+++ b/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
@@ -1,20 +1,29 @@
#PBL preamble and RCW header
AA55AA55 010E0100
#
-#0a06000c 0c000000 00000000 00000000
-#aa000002 00004000 e8105000 21000000
-#00000000 cafebabe 00000000 00030ffc
-#00000314 0000000c 00000000 00000001
-#
+## SYS_CLK: 100MHz PLAT:600MHz Core:1800MHz FMAN:700MHz (1800MHz speedgrade)
+## DDR:1600MT/s
+# 0c06000e 12000000 00000000 40000000
+# 6c000002 40004000 e8105000 41000000
+# 00000000 cafebabe 00000000 00030ffc
+# 00000314 80000009 00000000 00000004
-# #SerDes=0xaa, Core:1200MHz, DDR:1600MT/s
-# 0a06000c 0c000000 00000000 00000000
-# 66000002 00404000 e8105000 21000000
+## SYS_CLK: 100MHz PLAT:600MHz Core:1500MHz FMAN: 700MHz (1533MHz speedgrade)
+## DDR:1600MT/s
+# 0c06000e 0f000000 00000000 40000000
+# bc000002 40004000 e8105000 41000000
# 00000000 cafebabe 00000000 00030ffc
-# 00000314 00000008 00000000 00000001
+# 00000314 80000009 00000000 00000004
-0c06000c 0c000000 00000000 00000000
-aa000002 40404000 e8105000 21000000
+### lowest valid clock & pll settings
+# 0806000a 0a000000 00000000 20000000
+# bc000002 40004000 e8105000 61000000
+# 00000000 cafebabe 00000000 00030ffc
+# 00000314 80000009 00000000 00000004
+
+## PCI SATA + Virtualization demo
+0c06000e 12000000 00000000 40000000
+aa000002 40004000 e8105000 41000000
00000000 cafebabe 00000000 00030ffc
-00000314 80000009 00000000 00000001
+00000314 80000009 00000000 00000004
diff --git a/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg b/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg
index d8ac2bd..08c3b2a 100644
--- a/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg
+++ b/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg
@@ -1,8 +1,9 @@
#PBL preamble and RCW header
AA55AA55 010E0100
#
-0c06000c 0c000000 00000000 00000000
-aa000002 40404000 e8023000 21000000
+## SYS_CLK: 100MHz PLAT:600MHz Core:1800MHz FMAN:700MHz (Max speedgrade)
+## DDR:1600MT/s SERDES:0x6c
+0c06000e 12000000 00000000 40000000
+6c000002 40004000 e8023000 41000000
00000000 cafebabe 00000000 00030ffc
-00000314 80000009 00000000 00000001
-
+00000314 80000009 00000000 00000004
diff --git a/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg b/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg
index fd38b58..849721a 100644
--- a/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg
+++ b/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg
@@ -27,5 +27,7 @@
09000010 00000000
09000014 ff000000
09000018 81000000
+#Write clk_out reg (platform clock/2)
+#090E1A00 0000EC00
#Flush PBL data (Wait 0xFFFFF cycles )
091380c0 000fffff
diff --git a/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg b/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg
index f06629c..e7c9aad 100644
--- a/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg
+++ b/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg
@@ -1,18 +1,11 @@
#PBL preamble and RCW header
AA55AA55 010E0100
+#
+## SYS_CLK: 100MHz PLAT:600MHz Core:1800MHz FMAN:700MHz (Max speedgrade)
+## DDR:1600MT/s SERDES:0x6c
+0c06000e 12000000 00000000 40000000
+6c000002 40004000 68105000 41000000
+00000000 cafebabe 00000000 00030ffc
+00000314 80000009 00000000 00000004
-#SerDes=0xaa, Core:1200MHz, DDR:1600MT/s
-# 0a06000c 0c000000 00000000 00000000
-# 66000002 00404000 68105000 21000000
-# 00000000 cafebabe 00000000 00030ffc
-# 00000314 00000008 00000000 00000001
-
-# 0c06000c 0c000000 00000000 00000000
-# 66000002 40404000 68105000 21000000
-# 00000000 cafebabe 00000000 00030ffc
-# 00000314 80000008 00000000 00000001
-0c06000c 0c000000 00000000 00000000
-aa000002 40404000 68105000 21000000
-00000000 cafebabe 00000000 00030ffc
-00000314 80000009 00000000 00000001
diff --git a/board/scalys/simc-t2081/spl.c b/board/scalys/simc-t2081/spl.c
index f0fb9dd..d36e9f4 100644
--- a/board/scalys/simc-t2081/spl.c
+++ b/board/scalys/simc-t2081/spl.c
@@ -152,7 +152,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
break;
case 0x40:
/* SD/MMC (eSDHC) boot */
- #ifdef CONFIG_SPL_MMC_BOOT
+#if defined(CONFIG_SPL_MMC_BOOT) || defined(CONFIG_SDHC_FLASH_BOOT)
setup_ifc_nand(IFC_CS0);
setup_ifc_nor(IFC_CS1);
@@ -160,7 +160,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
boot = mmc_boot;
- #endif
+#endif
break;
case 0x105:
/* NAND boot */
diff --git a/board/scalys/simc-t2081/tlb.c b/board/scalys/simc-t2081/tlb.c
index c03282e..ddaa10e 100644
--- a/board/scalys/simc-t2081/tlb.c
+++ b/board/scalys/simc-t2081/tlb.c
@@ -39,7 +39,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
*/
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_512K, 1),
+ 0, 0, BOOKE_PAGESZ_1M, 1),
#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD)
/*
* *I*G - L3SRAM. When L3 is used as 512K SRAM, in case of Secure Boot
@@ -65,45 +65,60 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_64M, 1), /* modified to simc-t1040 equivalent */
+ 0, 2, BOOKE_PAGESZ_64M, 1),
#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_PCI
- /* *I*G* - PCI */
+ /* *I*G* - PCIe 1, 0x80000000 */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
+ 0, 3, BOOKE_PAGESZ_512M, 1),
+
+ /* *I*G* - PCIe 2, 0xa0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCIe 3, 0xb0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCIe 4, 0xc0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI I/O */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256K, 1),
-#endif
+ 0, 7, BOOKE_PAGESZ_256K, 1),
- /* Bman/Qman */
+
+ /* Bman/Qman
+ */
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 5, BOOKE_PAGESZ_16M, 1),
+ 0, 9, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_16M, 1),
+ 0, 10, BOOKE_PAGESZ_16M, 1),
#endif
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_16M, 1),
+ 0, 11, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_16M, 1),
+ 0, 12, BOOKE_PAGESZ_16M, 1),
#endif
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_4M, 1),
+ 0, 13, BOOKE_PAGESZ_32M, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE
/*
@@ -113,17 +128,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
*/
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_64K, 1),
+ 0, 16, BOOKE_PAGESZ_64K, 1),
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 12, BOOKE_PAGESZ_1G, 1),
+ 0, 19, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 13, BOOKE_PAGESZ_1G, 1)
+ 0, 20, BOOKE_PAGESZ_1G, 1)
#endif
};
generated by cgit v0.10.2 at 2024-06-01 07:01:51 (GMT)