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-rw-r--r--board/scalys/simc-t10xx/dragonfruit.c54
-rw-r--r--board/scalys/simc-t2081/dragonfruit.c71
-rw-r--r--board/scalys/simc-t2081/eth.c89
-rw-r--r--board/scalys/simc-t2081/pci.c79
-rw-r--r--board/scalys/simc-t2081/simc-t2081.c8
-rw-r--r--board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg8
-rw-r--r--board/scalys/simc-t2081/tlb.c4
7 files changed, 158 insertions, 155 deletions
diff --git a/board/scalys/simc-t10xx/dragonfruit.c b/board/scalys/simc-t10xx/dragonfruit.c
index 80235fe..12accc0 100644
--- a/board/scalys/simc-t10xx/dragonfruit.c
+++ b/board/scalys/simc-t10xx/dragonfruit.c
@@ -8,23 +8,18 @@
#include <common.h>
#include <asm-generic/gpio.h>
-
#include "dragonfruit.h"
-uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
-uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
-uint32_t regval;
-
/*
* SERDER MUX Configuration pins:
* IFC_A25 : GPIO2_25 : SERDES_CLK_ MUX_SER0_1_SEL
* IFC_A26 : GPIO2_26 : SERDES_CLK_ MUX_SER2_3_SEL
* IFC_A27 : GPIO2_27 : SERDES_CLK_ MUX_SER5_6_SEL
*/
-#define MUX_SER0_1_SEL (0x80000000 >> 25)
-#define MUX_SER2_3_SEL (0x80000000 >> 26)
-#define MUX_SER5_6_SEL (0x80000000 >> 27)
-#define SERDES_CLK_OE (0x80000000 >> 29)
+#define MUX_SER0_1_SEL MPC85XX_GPIO_NR(2, 25)
+#define MUX_SER2_3_SEL MPC85XX_GPIO_NR(2, 26)
+#define MUX_SER5_6_SEL MPC85XX_GPIO_NR(2, 27)
+#define SERDES_CLK_OE MPC85XX_GPIO_NR(2, 29)
/*
* MUX_SER0_1_SEL
@@ -153,46 +148,34 @@ int scalys_carrier_setup_muxing(int serdes_config)
printf("-----------------------------------------------------\n");
printf("Serdes lane configuration:\n");
- if ((mux_config & 1) > 0) {
- regval = in_be32(gpio2_gpdat);
- regval |= MUX_SER0_1_SEL;
- out_be32(gpio2_gpdat, regval);
+ if ((mux_config & 1) != 0) {
+ gpio_direction_output(MUX_SER0_1_SEL, 1);
printf("A: SFP slot 0 (T2081 only)\n");
- printf("B: SFP slot 1\n");
+ printf("B: SFP slot 1 (T2081 only)\n");
} else {
- regval = in_be32(gpio2_gpdat);
- regval &= ~MUX_SER0_1_SEL;
- out_be32(gpio2_gpdat, regval);
+ gpio_direction_output(MUX_SER0_1_SEL, 0);
printf("A: PCIe slot 1 on lane 0\n");
printf("B: PCIe slot 1 on lane 1\n");
}
- if ((mux_config & 2) > 0) {
- regval = in_be32(gpio2_gpdat);
- regval |= MUX_SER2_3_SEL;
- out_be32(gpio2_gpdat, regval);
+ if ((mux_config & 2) != 0) {
+ gpio_direction_output(MUX_SER2_3_SEL, 1);
printf("C: SFP slot 2\n");
printf("D: SFP slot 3\n");
} else {
- regval = in_be32(gpio2_gpdat);
- regval &= ~MUX_SER2_3_SEL;
- out_be32(gpio2_gpdat, regval);
+ gpio_direction_output(MUX_SER2_3_SEL, 0);
printf("C: PCIe slot 1 on lane 2\n");
printf("D: PCIe slot 1 on lane 3\n");
}
printf("E: PCIe slot 4 on lane 0\n");
- if ((mux_config & 4) > 0) {
- regval = in_be32(gpio2_gpdat);
- regval |= MUX_SER5_6_SEL;
- out_be32(gpio2_gpdat, regval);
+ if ((mux_config & 4) != 0) {
+ gpio_direction_output(MUX_SER5_6_SEL, 1);
printf("F: PCIe slot 2 on lane 0\n");
printf("G: PCIe slot 3 on lane 0\n");
} else {
- regval = in_be32(gpio2_gpdat);
- regval &= ~MUX_SER5_6_SEL;
- out_be32(gpio2_gpdat, regval);
+ gpio_direction_output(MUX_SER5_6_SEL, 0);
printf("F: PCIe slot 4 on lane 1\n");
printf("G: PCIe slot 4 on lane 2\n");
}
@@ -201,14 +184,7 @@ int scalys_carrier_setup_muxing(int serdes_config)
printf("-----------------------------------------------------\n");
/* Enable serdes clock */
- regval = in_be32(gpio2_gpdat);
- regval |= SERDES_CLK_OE;
- out_be32(gpio2_gpdat, regval);
+ gpio_direction_output(SERDES_CLK_OE, 1);
- /* Set outputs to output mode */
- regval = in_be32(gpio2_gpdir);
- regval |= (MUX_SER0_1_SEL | MUX_SER2_3_SEL | MUX_SER5_6_SEL | SERDES_CLK_OE);
- out_be32(gpio2_gpdir, regval);
-
return ret;
}
diff --git a/board/scalys/simc-t2081/dragonfruit.c b/board/scalys/simc-t2081/dragonfruit.c
index a2d6653..e3f1641 100644
--- a/board/scalys/simc-t2081/dragonfruit.c
+++ b/board/scalys/simc-t2081/dragonfruit.c
@@ -6,23 +6,19 @@
*/
#include <common.h>
-#include <asm/gpio.h>
+#include <asm-generic/gpio.h>
#include "dragonfruit.h"
-uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
-uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
-uint32_t regval;
-
/*
* SERDER MUX Configuration pins:
* IFC_A25 : GPIO2_25 : SERDES_CLK_ MUX_SER0_1_SEL
* IFC_A26 : GPIO2_26 : SERDES_CLK_ MUX_SER2_3_SEL
* IFC_A27 : GPIO2_27 : SERDES_CLK_ MUX_SER5_6_SEL
*/
-#define MUX_SER0_1_SEL (0x80000000 >> 25)
-#define MUX_SER2_3_SEL (0x80000000 >> 26)
-#define MUX_SER5_6_SEL (0x80000000 >> 27)
-#define SERDES_CLK_OE (0x80000000 >> 29)
+#define MUX_SER0_1_SEL MPC85XX_GPIO_NR(2, 25)
+#define MUX_SER2_3_SEL MPC85XX_GPIO_NR(2, 26)
+#define MUX_SER5_6_SEL MPC85XX_GPIO_NR(2, 27)
+#define SERDES_CLK_OE MPC85XX_GPIO_NR(2, 29)
/*
* MUX_SER0_1_SEL
@@ -57,8 +53,7 @@ uint32_t regval;
#define SER_5_6_SLOT4 0
#define SER_5_6_SLOT23 4
-
-/*
+/*
* SERDES H => Slot 4, lane 3
*/
@@ -66,14 +61,17 @@ int scalys_carrier_setup_muxing(int serdes_config)
{
int ret = 0;
int mux_config = 0;
+
+
+ mdelay(100);
- ret = gpio_request(MUX_SER0_1_SEL, "mux_ser0_1_sel");
+ ret += gpio_request(MUX_SER0_1_SEL, "mux_ser0_1_sel");
+ ret += gpio_request(MUX_SER2_3_SEL, "mux_ser2_3_sel");
+ ret += gpio_request(MUX_SER5_6_SEL, "mux_ser5_6_sel");
+ ret += gpio_request(SERDES_CLK_OE, "serdes_clk_oe");
if (ret != 0) {
printf("gpio request failed(%i)\n", ret);
}
- gpio_request(MUX_SER2_3_SEL, "mux_ser2_3_sel");
- gpio_request(MUX_SER5_6_SEL, "mux_ser5_6_sel");
- gpio_request(SERDES_CLK_OE, "serdes_clk_oe");
/*
@@ -123,46 +121,34 @@ int scalys_carrier_setup_muxing(int serdes_config)
printf("-----------------------------------------------------\n");
printf("Serdes lane configuration:\n");
- if ((mux_config & 1) > 0) {
- regval = in_be32(gpio2_gpdat);
- regval |= MUX_SER0_1_SEL;
- out_be32(gpio2_gpdat, regval);
+ if ((mux_config & 1) != 0) {
+ gpio_direction_output(MUX_SER0_1_SEL, 1);
printf("A: SFP slot 0 (T2081 only)\n");
- printf("B: SFP slot 1\n");
+ printf("B: SFP slot 1 (T2081 only)\n");
} else {
- regval = in_be32(gpio2_gpdat);
- regval &= ~MUX_SER0_1_SEL;
- out_be32(gpio2_gpdat, regval);
+ gpio_direction_output(MUX_SER0_1_SEL, 0);
printf("A: PCIe slot 1 on lane 0\n");
printf("B: PCIe slot 1 on lane 1\n");
}
- if ((mux_config & 2) > 0) {
- regval = in_be32(gpio2_gpdat);
- regval |= MUX_SER2_3_SEL;
- out_be32(gpio2_gpdat, regval);
+ if ((mux_config & 2) != 0) {
+ gpio_direction_output(MUX_SER2_3_SEL, 1);
printf("C: SFP slot 2\n");
printf("D: SFP slot 3\n");
} else {
- regval = in_be32(gpio2_gpdat);
- regval &= ~MUX_SER2_3_SEL;
- out_be32(gpio2_gpdat, regval);
+ gpio_direction_output(MUX_SER2_3_SEL, 0);
printf("C: PCIe slot 1 on lane 2\n");
printf("D: PCIe slot 1 on lane 3\n");
}
printf("E: PCIe slot 4 on lane 0\n");
- if ((mux_config & 4) > 0) {
- regval = in_be32(gpio2_gpdat);
- regval |= MUX_SER5_6_SEL;
- out_be32(gpio2_gpdat, regval);
+ if ((mux_config & 4) != 0) {
+ gpio_direction_output(MUX_SER5_6_SEL, 1);
printf("F: PCIe slot 2 on lane 0\n");
printf("G: PCIe slot 3 on lane 0\n");
} else {
- regval = in_be32(gpio2_gpdat);
- regval &= ~MUX_SER5_6_SEL;
- out_be32(gpio2_gpdat, regval);
+ gpio_direction_output(MUX_SER5_6_SEL, 0);
printf("F: PCIe slot 4 on lane 1\n");
printf("G: PCIe slot 4 on lane 2\n");
}
@@ -171,14 +157,9 @@ int scalys_carrier_setup_muxing(int serdes_config)
printf("-----------------------------------------------------\n");
/* Enable serdes clock */
- regval = in_be32(gpio2_gpdat);
- regval |= SERDES_CLK_OE;
- out_be32(gpio2_gpdat, regval);
+ gpio_direction_output(SERDES_CLK_OE, 1);
+
+ mdelay(100);
- /* Set outputs to output mode */
- regval = in_be32(gpio2_gpdir);
- regval |= (MUX_SER0_1_SEL | MUX_SER2_3_SEL | MUX_SER5_6_SEL | SERDES_CLK_OE);
- out_be32(gpio2_gpdir, regval);
-
return ret;
}
diff --git a/board/scalys/simc-t2081/eth.c b/board/scalys/simc-t2081/eth.c
index 10c59f8..82703d4 100644
--- a/board/scalys/simc-t2081/eth.c
+++ b/board/scalys/simc-t2081/eth.c
@@ -15,9 +15,13 @@
#include <fsl_dtsec.h>
#include <vsc9953.h>
#include <i2c.h>
+#include <phy.h>
+#include <cortina.h>
#include "../../freescale/common/fman.h"
+#define VILLA_EEPROM_LOADER_STATUS 0xc01
+
uint8_t sfp_phy_config[][2] = {
{ 0x1b, 0x90 },
{ 0x1b, 0x84 },
@@ -32,18 +36,21 @@ int board_eth_init(bd_t *bis)
#ifdef CONFIG_FMAN_ENET
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
+ /*struct phy_driver *cortina_10G_phy;*/
unsigned int i;
uint8_t i2c_data;
int ret;
int phy_addr = 0;
+ /*uint32_t *gpio1_gpdir = (uint32_t *) 0xffe130000;
+ uint32_t *gpio1_gpdat = (uint32_t *) 0xffe130008;*/
uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
uint32_t *gpio4_gpdir = (uint32_t *) 0xffe133000;
uint32_t *gpio4_gpdat = (uint32_t *) 0xffe133008;
uint32_t regval;
- /* Try to read a byte from te carrier eeprom te determine if were on the correct carrier */
+ /* Try to read a byte from the carrier eeprom the determine if were on the correct carrier */
ret = i2c_read(0x54, 0, 2, &i2c_data, 1 );
if (ret != 0) {
printf("No dragonfruit carrier detected\n");
@@ -71,27 +78,30 @@ int board_eth_init(bd_t *bis)
* Remove reset from Ethernet PHY's
*
* Carrier board v1.x:
- * IFC_PERR_B : GPIO2_15 : eth1_reset
- * IFC_CS_N2 : GPIO2_11 : eth2_reset
+ * IFC_PERR_B : GPIO2_15 : eth1_reset_n
+ * IFC_CS_N2 : GPIO2_11 : eth2_reset_n
*
* Carrier board v2.x:
- * IFC_PERR_B : GPIO2_15 : eth1_reset
- * IFC_CS_N2 : GPIO4_09 : eth2_reset
+ * IFC_PERR_B : GPIO2_15 : eth1_reset_n
+ * N_DMA2_DDONE0_B : GPIO4_09 : eth2_reset_n
*
* Note: make sure gpio pins are configured as gpio in RCW!
*/
#if 0
+
+#define ETH1_RESET_N (0x80000000 >> 15)
+#define ETH2_RESET_N (0x80000000 >> 11)
/* TODO: use EEPROM data to chose carrier board version */
/* Carrier board v1.x */
/* Clear outputs to activate reset */
regval = in_be32(gpio2_gpdat);
- regval &= ~((0x80000000 >> 11 ) | (0x80000000 >> 15));
+ regval &= ~(ETH1_RESET_N | ETH2_RESET_N);
out_be32(gpio2_gpdat, regval);
/* Set outputs to output mode */
regval = in_be32(gpio2_gpdir);
- regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15));
+ regval |= (ETH1_RESET_N | ETH2_RESET_N);
out_be32(gpio2_gpdir, regval);
/* Wait for 10 ms to to meet reset timing */
@@ -99,24 +109,27 @@ int board_eth_init(bd_t *bis)
/* Set outputs to de-activate reset */
regval = in_be32(gpio2_gpdat);
- regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15));
+ regval |= (ETH1_RESET_N | ETH2_RESET_N);
out_be32(gpio2_gpdat, regval);
#else
+
+#define ETH1_RESET_N (0x80000000 >> 15)
+#define ETH2_RESET_N (0x80000000 >> 9)
/* Carrier board v2.x */
/* Clear outputs to activate reset */
regval = in_be32(gpio2_gpdat);
- regval &= ~(0x80000000 >> 15);
+ regval &= ~(ETH1_RESET_N);
out_be32(gpio2_gpdat, regval);
regval = in_be32(gpio4_gpdat);
- regval &= ~(0x80000000 >> 9);
+ regval &= ~(ETH2_RESET_N);
out_be32(gpio4_gpdat, regval);
/* Set outputs to output mode */
regval = in_be32(gpio2_gpdir);
- regval |= (0x80000000 >> 15);
+ regval |= (ETH1_RESET_N);
out_be32(gpio2_gpdir, regval);
regval = in_be32(gpio4_gpdir);
- regval |= (0x80000000 >> 9);
+ regval |= (ETH2_RESET_N);
out_be32(gpio4_gpdir, regval);
/* Wait for 10 ms to to meet reset timing */
@@ -124,10 +137,10 @@ int board_eth_init(bd_t *bis)
/* Set outputs to de-activate reset */
regval = in_be32(gpio2_gpdat);
- regval |= (0x80000000 >> 15);
+ regval |= (ETH1_RESET_N);
out_be32(gpio2_gpdat, regval);
regval = in_be32(gpio4_gpdat);
- regval |= (0x80000000 >> 9);
+ regval |= (ETH2_RESET_N);
out_be32(gpio4_gpdat, regval);
#endif
@@ -199,13 +212,55 @@ int board_eth_init(bd_t *bis)
}
fm_info_set_mdio(i, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
}
-
+
+ /* 10G XFI interface initialization (TODO)*/
+#if 0
+ /* Reset phy */
+ /* N_DMA2_DDONE0_B : GPIO1_09 : EDC_RST_N */
+#define EDC_RST_N (0x80000000 >> 9)
+ /* Clear outputs to activate reset */
+ regval = in_be32(gpio1_gpdat);
+ regval &= ~(EDC_RST_N);
+ out_be32(gpio1_gpdat, regval);
+
+ /* Set outputs to output mode */
+ regval = in_be32(gpio1_gpdir);
+ regval |= (EDC_RST_N);
+ out_be32(gpio1_gpdir, regval);
+
+ /* Wait for 10 ms to to meet reset timing */
+ mdelay(10);
+
+ /* Set outputs to de-activate reset */
+ regval = in_be32(gpio1_gpdat);
+ regval |= (EDC_RST_N);
+ out_be32(gpio1_gpdat, regval);
+
+ /* Wait 10ms to let phy set the load_failed bit */
+ mdelay(10);
+
+ /* get cs4315 phy */
+ cortina_10G_phy = phy_find_by_mask(tgec_mdio_info, 0xfffffff0, PHY_INTERFACE_MODE_XGMII);
+
+ /* Check load_failed == 1 (else skip initialization) */
+ mii_data = miiphy_read("FM_TGEC_MDIO",0,VILLA_EEPROM_LOADER_STATUS);
+
+ if ((mii_data & 0x02) != 0) {
+ /* TODO: upload microcode */
+ cortina_10G_phy->config();
+ }
+
+ /* TODO: insert additional configuration */
+
+ /* Start phy */
+ cortina_10G_phy->startup();
+#endif
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
- fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
+ fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
break;
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
diff --git a/board/scalys/simc-t2081/pci.c b/board/scalys/simc-t2081/pci.c
index 9a02f90..f3473f8 100644
--- a/board/scalys/simc-t2081/pci.c
+++ b/board/scalys/simc-t2081/pci.c
@@ -14,30 +14,49 @@
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
+#include <asm-generic/gpio.h>
+#include "dragonfruit.h"
+
+#define SLOT1_REFCLK_OE_N MPC85XX_GPIO_NR(1, 9)
+#define SLOT2_REFCLK_OE_N MPC85XX_GPIO_NR(1, 10)
+#define SLOT3_REFCLK_OE_N MPC85XX_GPIO_NR(1, 11)
+#define SLOT4_REFCLK_OE_N MPC85XX_GPIO_NR(1, 12)
+
+#define SLOT1_PRSNT2_N MPC85XX_GPIO_NR(1, 23)
+#define SLOT2_PRSNT2_N MPC85XX_GPIO_NR(1, 24)
+#define SLOT3_PRSNT2_N MPC85XX_GPIO_NR(1, 25)
+#define SLOT4_PRSNT2_N MPC85XX_GPIO_NR(1, 30)
+
+#define PEX_REFCLK_SEL MPC85XX_GPIO_NR(2, 14)
+#define PEX_PERST_N MPC85XX_GPIO_NR(2, 13)
+
void pci_init_board(void)
{
+ int ret = 0;
+ int serdes_config;
+ ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint32_t *gpio1_gpdir = (uint32_t *) 0xffe130000;
- uint32_t *gpio1_gpdat = (uint32_t *) 0xffe130008;
- uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
- uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
- uint32_t regval;
-
- /*debug("%s\n", __FUNCTION__);*/
+ /* SERDES configuration is determined boot time through the RCW config.
+ * It is located in the fourth RCW word (bit 128-135 of the RCW). */
+ serdes_config = ( in_be32(&gur->rcwsr[4]) >> 24);
+ scalys_carrier_setup_muxing(serdes_config);
- /*TODO, when present pins are available on the board, use them to enable only active slots*/
+ ret += gpio_request(SLOT4_REFCLK_OE_N, "c19");
+ ret += gpio_request(PEX_REFCLK_SEL, "c14");
+ ret += gpio_request(PEX_PERST_N, "c15");
+ if (ret != 0)
+ printf("A gpio request failed(%i)\n", ret);
#if 0
/* Dragonfruit Carrier board 1.x */
-
/*
* IRQ[0-3] : PCIe present detect signals
- * IRQ[0] : SLOT1_PRSNT2_N : XXX
- * IRQ[1] : SLOT2_PRSNT2_N : XXX
- * IRQ[2] : SLOT3_PRSNT2_N : XXX
- * IRQ[3] : SLOT4_PRSNT2_N : XXX
+ * IRQ[3] : GPIO1_23 : SLOT1_PRSNT2_N
+ * IRQ[4] : GPIO1_24 : SLOT2_PRSNT2_N
+ * IRQ[5] : GPIO1_25 : SLOT3_PRSNT2_N
+ * IRQ[10] : GPIO1_30 : SLOT4_PRSNT2_N
*
* Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7
* IFC_CS_N4 : GPIO1_IO09 : PCIe SLOT1_REFCLK_OE_N
@@ -71,44 +90,18 @@ void pci_init_board(void)
*/
/* Set output to 0 to enable reference clocks */
- regval = in_be32(gpio1_gpdat);
- regval &= ~( 0x80000000 >> 12 );
- out_be32(gpio1_gpdat, regval);
-
- /* Set Enable outputs */
- regval = in_be32(gpio1_gpdir);
- regval |= ( 0x80000000 >> 12 );
- out_be32(gpio1_gpdir, regval);
+ gpio_direction_output(SLOT4_REFCLK_OE_N, 0);
/* Set PEX_REFCLK_SEL to 0 to select CLK0 */
-
- /* Set IFC_PAR1 to output mode */
- regval = in_be32(gpio2_gpdir);
- regval |= ( 0x80000000 >> 14 );
- out_be32(gpio2_gpdir, regval);
-
- /* Set output to 0 to select clock source 0 */
- regval = in_be32(gpio2_gpdat);
- regval &= ~( 0x80000000 >> 14 );
- out_be32(gpio2_gpdat, regval);
-
-#endif
+ gpio_direction_output(PEX_REFCLK_SEL, 0);
+#endif
/*
* IFC_PAR0 : GPIO2_13 : PEX_PERST_N
*/
/* Remove reset from PCIe devices */
-
- /* Set IFC_PAR0 to output mode */
- regval = in_be32(gpio2_gpdir);
- regval |= ( 0x80000000 >> 13 );
- out_be32(gpio2_gpdir, regval);
-
- /* Set output to 1 to clear reset */
- regval = in_be32(gpio2_gpdat);
- regval |= ( 0x80000000 >> 13 );
- out_be32(gpio2_gpdat, regval);
+ gpio_direction_output(PEX_PERST_N, 1);
/* Wait for 100 ms to allow the PCIe device to become ready */
mdelay(100);
diff --git a/board/scalys/simc-t2081/simc-t2081.c b/board/scalys/simc-t2081/simc-t2081.c
index f07a36f..0569d88 100644
--- a/board/scalys/simc-t2081/simc-t2081.c
+++ b/board/scalys/simc-t2081/simc-t2081.c
@@ -23,7 +23,6 @@
#include <asm/gpio.h>
#include <fsl_esdhc.h>
#include <dm.h>
-#include "dragonfruit.h"
#include <board_configuration_data.h>
@@ -38,8 +37,6 @@ int checkboard(void)
int misc_init_r(void)
{
const void* bcd_dtc_blob;
- int serdes_config;
- ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int ret;
debug("t2081: misc_init_r\n");
@@ -56,11 +53,6 @@ int misc_init_r(void)
gpio_direction_output(MODULE_LED_RED, 0);
gpio_direction_output(MODULE_LED_GREEN, 1);
- /* SERDES configuration is determined boot time through the RCW config.
- * It is located in the fourth RCW word (bit 128-135 of the RCW). */
- serdes_config = ( in_be32(&gur->rcwsr[4]) >> 24);
- scalys_carrier_setup_muxing(serdes_config);
-
bcd_dtc_blob = get_boardinfo_eeprom();
if (bcd_dtc_blob != NULL) {
/* Board Configuration Data is intact, ready for parsing */
diff --git a/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg b/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
index 88dc8ab..afef4e0 100644
--- a/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
+++ b/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
@@ -23,7 +23,13 @@ AA55AA55 010E0100
# 00000314 80000009 00000000 00000004
## PCI SATA + Virtualization demo
+# 0c06000e 12000000 00000000 40000000
+# aa000002 40004000 e8105000 41000000
+# 00000000 cafebabe 00000000 00030ffc
+# 00000314 80000009 00000000 00000004
+
+## SERDES PLL2 disabled
0c06000e 12000000 00000000 40000000
-aa000002 40004000 e8105000 41000000
+aa000002 00404000 e8105000 41000000
00000000 cafebabe 00000000 00030ffc
00000314 80000009 00000000 00000004
diff --git a/board/scalys/simc-t2081/tlb.c b/board/scalys/simc-t2081/tlb.c
index ddaa10e..b16b682 100644
--- a/board/scalys/simc-t2081/tlb.c
+++ b/board/scalys/simc-t2081/tlb.c
@@ -134,11 +134,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 19, BOOKE_PAGESZ_1G, 1),
+ 0, 17, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 20, BOOKE_PAGESZ_1G, 1)
+ 0, 18, BOOKE_PAGESZ_1G, 1)
#endif
};
generated by cgit v0.10.2 at 2024-06-01 08:07:49 (GMT)