diff options
Diffstat (limited to 'board/spd8xx/spd8xx.c')
| -rw-r--r-- | board/spd8xx/spd8xx.c | 200 |
1 files changed, 85 insertions, 115 deletions
diff --git a/board/spd8xx/spd8xx.c b/board/spd8xx/spd8xx.c index 239cf26..9f52e33 100644 --- a/board/spd8xx/spd8xx.c +++ b/board/spd8xx/spd8xx.c @@ -34,14 +34,13 @@ static long int dram_size (long int, long int *, long int); #define _NOT_USED_ 0xFFFFFFFF -const uint sharc_table[] = -{ +const uint sharc_table[] = { /* * Single Read. (Offset 0 in UPM RAM) */ 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04, - 0xFFFFEC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0xFFFFEC05, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Burst Read. (Offset 8 in UPM RAM) */ @@ -54,8 +53,8 @@ const uint sharc_table[] = * Single Write. (Offset 18 in UPM RAM) */ 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04, - 0xFFFFEC05, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0xFFFFEC05, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Burst Write. (Offset 20 in UPM RAM) */ @@ -74,18 +73,17 @@ const uint sharc_table[] = /* * Exception. (Offset 3c in UPM RAM) */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, }; -const uint sdram_table[] = -{ +const uint sdram_table[] = { /* * Single Read. (Offset 0 in UPM RAM) */ 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ + 0x1FF77C47, /* last */ /* * SDRAM Initialization (offset 5 in UPM RAM) * @@ -94,39 +92,39 @@ const uint sdram_table[] = * sequence, which is executed by a RUN command. * */ - 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ + 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ /* * Burst Read. (Offset 8 in UPM RAM) */ 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Single Write. (Offset 18 in UPM RAM) */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ + 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Burst Write. (Offset 20 in UPM RAM) */ 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, + 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Refresh (Offset 30 in UPM RAM) */ 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Exception. (Offset 3c in UPM RAM) */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, }; /* ------------------------------------------------------------------------- */ @@ -145,71 +143,74 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -long int -initdram (int board_type) +long int initdram (int board_type) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size_b0; #if 0 - /* - * Map controller bank 2 to the SRAM bank at preliminary address. - */ - memctl->memc_or2 = CFG_OR2; - memctl->memc_br2 = CFG_BR2; + /* + * Map controller bank 2 to the SRAM bank at preliminary address. + */ + memctl->memc_or2 = CFG_OR2; + memctl->memc_br2 = CFG_BR2; #endif - /* - * Map controller bank 4 to the PER8 bank. - */ - memctl->memc_or4 = CFG_OR4; - memctl->memc_br4 = CFG_BR4; + /* + * Map controller bank 4 to the PER8 bank. + */ + memctl->memc_or4 = CFG_OR4; + memctl->memc_br4 = CFG_BR4; #if 0 - /* Configure SHARC at UMA */ - upmconfig(UPMA, (uint *)sharc_table, sizeof(sharc_table)/sizeof(uint)); - /* Map controller bank 5 to the SHARC */ - memctl->memc_or5 = CFG_OR5; - memctl->memc_br5 = CFG_BR5; + /* Configure SHARC at UMA */ + upmconfig (UPMA, (uint *) sharc_table, + sizeof (sharc_table) / sizeof (uint)); + /* Map controller bank 5 to the SHARC */ + memctl->memc_or5 = CFG_OR5; + memctl->memc_br5 = CFG_BR5; #endif - memctl->memc_mamr = 0x00001000; + memctl->memc_mamr = 0x00001000; - /* Configure SDRAM at UMB */ - upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); + /* Configure SDRAM at UMB */ + upmconfig (UPMB, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); - memctl->memc_mptpr = CFG_MPTPR_1BK_8K; + memctl->memc_mptpr = CFG_MPTPR_1BK_8K; - memctl->memc_mar = 0x00000088; + memctl->memc_mar = 0x00000088; - /* - * Map controller bank 3 to the SDRAM bank at preliminary address. - */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; + /* + * Map controller bank 3 to the SDRAM bank at preliminary address. + */ + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; - memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */ + memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */ - udelay(200); - memctl->memc_mcr = 0x80806105; - udelay(1); - memctl->memc_mcr = 0x80806130; - udelay(1); - memctl->memc_mcr = 0x80806130; - udelay(1); - memctl->memc_mcr = 0x80806106; + udelay (200); + memctl->memc_mcr = 0x80806105; + udelay (1); + memctl->memc_mcr = 0x80806130; + udelay (1); + memctl->memc_mcr = 0x80806130; + udelay (1); + memctl->memc_mcr = 0x80806106; - memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */ + memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */ - /* - * Check Bank 0 Memory Size for re-configuration - */ - size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); + /* + * Check Bank 0 Memory Size for re-configuration + */ + size_b0 = + dram_size (CFG_MBMR_8COL, (ulong *) SDRAM_BASE3_PRELIM, + SDRAM_MAX_SIZE); - memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE; + memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE; - return (size_b0); + return (size_b0); } /* ------------------------------------------------------------------------- */ @@ -222,60 +223,29 @@ initdram (int board_type) * - short between data lines */ -static long int dram_size (long int mamr_value, long int *base, long int maxsize) +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile long int *addr; - ulong cnt, val; - ulong save[32]; /* to make test non-destructive */ - unsigned char i = 0; - - memctl->memc_mbmr = mamr_value; - - for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) { - addr = base + cnt; /* pointer arith! */ - - save[i++] = *addr; - *addr = ~cnt; - } - - /* write 0 to base address */ - addr = base; - save[i] = *addr; - *addr = 0; - - /* check at base address */ - if ((val = *addr) != 0) { - *addr = save[i]; - return (0); - } - - for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; - val = *addr; - *addr = save[--i]; + memctl->memc_mbmr = mamr_value; - if (val != (~cnt)) { - return (cnt * sizeof(long)); - } - } - return (maxsize); + return (get_ram_size (base, maxsize)); } /* ------------------------------------------------------------------------- */ -void reset_phy(void) +void reset_phy (void) { - immap_t *immr = (immap_t *)CFG_IMMR; + immap_t *immr = (immap_t *) CFG_IMMR; ushort sreg; /* Configure extra port pins for NS DP83843 PHY */ immr->im_ioport.iop_papar &= ~(PA_ENET_MDC | PA_ENET_MDIO); - sreg = immr->im_ioport.iop_padir; - sreg |= PA_ENET_MDC; /* Mgmt. Data Clock is Output */ + sreg = immr->im_ioport.iop_padir; + sreg |= PA_ENET_MDC; /* Mgmt. Data Clock is Output */ sreg &= ~(PA_ENET_MDIO); /* Mgmt. Data I/O is bidirect. => Input */ immr->im_ioport.iop_padir = sreg; @@ -288,23 +258,23 @@ void reset_phy(void) * Configure RESET pins for NS DP83843 PHY, and RESET chip. * * Note: The RESET pin is high active, but there is an - * inverter on the SPD823TS board... + * inverter on the SPD823TS board... */ immr->im_ioport.iop_pcpar &= ~(PC_ENET_RESET); - immr->im_ioport.iop_pcdir |= PC_ENET_RESET; + immr->im_ioport.iop_pcdir |= PC_ENET_RESET; /* assert RESET signal of PHY */ immr->im_ioport.iop_pcdat &= ~(PC_ENET_RESET); udelay (10); /* de-assert RESET signal of PHY */ - immr->im_ioport.iop_pcdat |= PC_ENET_RESET; + immr->im_ioport.iop_pcdat |= PC_ENET_RESET; udelay (10); } /* ------------------------------------------------------------------------- */ -void ide_set_reset(int on) +void ide_set_reset (int on) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *) CFG_IMMR; /* * Configure PC for IDE Reset Pin @@ -312,13 +282,13 @@ void ide_set_reset(int on) if (on) { /* assert RESET */ immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET); } else { /* release RESET */ - immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET; + immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET; } /* program port pin as GPIO output */ immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET); - immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET); - immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET; + immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET); + immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET; } /* ------------------------------------------------------------------------- */ |