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-rw-r--r--board/theadorable/theadorable.c54
1 files changed, 54 insertions, 0 deletions
diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c
index c1db289..9b56620 100644
--- a/board/theadorable/theadorable.c
+++ b/board/theadorable/theadorable.c
@@ -115,6 +115,13 @@ MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
},
};
+/*
+ * Define a board-specific detection pulse-width array for the SerDes PCIe
+ * interfaces. If not defined in the board code, the default of currently 2
+ * is used. Values from 0...3 are possible (2 bits).
+ */
+u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
+
MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
{
/* Only one mode supported for this board */
@@ -126,6 +133,12 @@ MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
return &theadorable_serdes_cfg[0];
}
+u8 board_sat_r_get(u8 dev_num, u8 reg)
+{
+ /* Bit 0 enables PCI 2.0 link capabilities instead of PCI 1.x */
+ return 0x01;
+}
+
int board_early_init_f(void)
{
/* Configure MPP */
@@ -281,3 +294,44 @@ int board_late_init(void)
return 0;
}
#endif
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI)
+int do_pcie_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ pci_dev_t bdf;
+ u16 ven_id, dev_id;
+
+ if (argc != 3)
+ return cmd_usage(cmdtp);
+
+ ven_id = simple_strtoul(argv[1], NULL, 16);
+ dev_id = simple_strtoul(argv[2], NULL, 16);
+
+ printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n",
+ ven_id, dev_id);
+
+ /*
+ * Check if the PCIe device is detected (somtimes its not available
+ * on the PCIe bus)
+ */
+ bdf = pci_find_device(ven_id, dev_id, 0);
+ if (bdf == -1) {
+ /* PCIe device not found! */
+ printf("Failed to find PCIe device\n");
+ } else {
+ /* PCIe device found! */
+ printf("PCIe device found, resetting board...\n");
+
+ /* default handling: SOFT reset */
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ pcie, 3, 0, do_pcie_test,
+ "Test for presence of a PCIe device",
+ "<VendorID> <DeviceID>"
+);
+#endif