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-rw-r--r--board/tqc/tqma6/Kconfig7
-rw-r--r--board/tqc/tqma6/README3
-rw-r--r--board/tqc/tqma6/tqma6.c37
-rw-r--r--board/tqc/tqma6/tqma6_mba6.c51
-rw-r--r--board/tqc/tqma6/tqma6_wru4.c6
-rw-r--r--board/tqc/tqma6/tqma6dl.cfg125
6 files changed, 179 insertions, 50 deletions
diff --git a/board/tqc/tqma6/Kconfig b/board/tqc/tqma6/Kconfig
index 5dafa38..6df4134 100644
--- a/board/tqc/tqma6/Kconfig
+++ b/board/tqc/tqma6/Kconfig
@@ -22,6 +22,12 @@ config TQMA6Q
help
select TQMa6Q / TQMa6D with i.MX6Q/D and 1GiB DRAM
+config TQMA6DL
+ bool "TQMa6DL"
+ select MX6DL
+ help
+ select TQMa6DL with i.MX6DL and 1GiB DRAM
+
config TQMA6S
bool "TQMa6S"
select MX6S
@@ -70,6 +76,7 @@ endchoice
config IMX_CONFIG
default "board/tqc/tqma6/tqma6q.cfg" if TQMA6Q
+ default "board/tqc/tqma6/tqma6dl.cfg" if TQMA6DL
default "board/tqc/tqma6/tqma6s.cfg" if TQMA6S
endif
diff --git a/board/tqc/tqma6/README b/board/tqc/tqma6/README
index 2c012e7..c47cb21 100644
--- a/board/tqc/tqma6/README
+++ b/board/tqc/tqma6/README
@@ -21,6 +21,7 @@ To build U-Boot for the TQ Systems TQMa6 modules:
x is a placeholder for the CPU variant
q - means i.MX6Q/D: TQMa6Q (i.MX6Q) and TQMa6D (i.MX6D)
+dl - means i.MX6DL: TQMa6DL (i.MX6DL)
s - means i.MX6S: TQMa6S (i.MX6S)
baseboard is a placeholder for the boot device
@@ -31,5 +32,7 @@ This gives the following configurations:
tqma6q_mba6_mmc_config
tqma6q_mba6_spi_config
+tqma6dl_mba6_mmc_config
+tqma6dl_mba6_spi_config
tqma6s_mba6_mmc_config
tqma6s_mba6_spi_config
diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c
index 7fc57da..fcdea34 100644
--- a/board/tqc/tqma6/tqma6.c
+++ b/board/tqc/tqma6/tqma6.c
@@ -13,11 +13,11 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/spi.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <libfdt.h>
@@ -47,7 +47,7 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
int dram_init(void)
@@ -232,25 +232,27 @@ static const char *tqma6_get_boardname(void)
};
}
-int board_late_init(void)
+/* setup board specific PMIC */
+int power_init_board(void)
{
struct pmic *p;
- u32 reg;
-
- setenv("board_name", tqma6_get_boardname());
+ u32 reg, rev;
- /*
- * configure PFUZE100 PMIC:
- * TODO: should go to power_init_board if bus switching is
- * fixed in generic power code
- */
power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
p = pmic_get("PFUZE100");
if (p && !pmic_probe(p)) {
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
- printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+ pmic_reg_read(p, PFUZE100_REVID, &rev);
+ printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev);
}
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setenv("board_name", tqma6_get_boardname());
+
tqma6_bb_board_late_init();
return 0;
@@ -267,8 +269,15 @@ int checkboard(void)
* Device Tree Support
*/
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#define MODELSTRLEN 32u
int ft_board_setup(void *blob, bd_t *bd)
{
+ char modelstr[MODELSTRLEN];
+
+ snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(),
+ tqma6_bb_get_boardname());
+ do_fixup_by_path_string(blob, "/", "model", modelstr);
+ fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size);
/* bring in eMMC dsr settings */
do_fixup_by_path_u32(blob,
"/soc/aips-bus@02100000/usdhc@02198000",
diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c
index e58b714..1188215 100644
--- a/board/tqc/tqma6/tqma6_mba6.c
+++ b/board/tqc/tqma6/tqma6_mba6.c
@@ -14,9 +14,9 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <common.h>
#include <fsl_esdhc.h>
@@ -51,22 +51,22 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-#if defined(CONFIG_MX6Q)
+#if defined(CONFIG_TQMA6Q)
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790
#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac
-#elif defined(CONFIG_MX6S)
+#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768
#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788
#else
-#error "need to define target CPU"
+#error "need to select module"
#endif
@@ -114,6 +114,11 @@ static iomux_v3_cfg_t const mba6_enet_pads[] = {
static void mba6_setup_iomuxc_enet(void)
{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* clear gpr1[ENET_CLK_SEL] for externel clock */
+ clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
__raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
(void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
__raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
@@ -125,7 +130,7 @@ static void mba6_setup_iomuxc_enet(void)
/* Reset PHY */
gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
/* Need delay 10ms after power on according to KSZ9031 spec */
- udelay(1000 * 10);
+ mdelay(10);
gpio_set_value(ENET_PHY_RESET_GPIO, 1);
/*
* KSZ9031 manual: 100 usec wait time after reset before communication
@@ -133,7 +138,7 @@ static void mba6_setup_iomuxc_enet(void)
* BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on
* reset before the phy sees a high level
*/
- udelay(200);
+ mdelay(15);
}
static iomux_v3_cfg_t const mba6_uart2_pads[] = {
@@ -234,39 +239,20 @@ static void mba6_setup_i2c(void)
printf("setup I2C1 failed: %d\n", ret);
}
-
-static iomux_v3_cfg_t const mba6_ecspi1_pads[] = {
- NEW_PAD_CTRL(MX6_PAD_EIM_D24__GPIO3_IO24, SPI_PAD_CTRL),
- NEW_PAD_CTRL(MX6_PAD_EIM_D25__GPIO3_IO25, SPI_PAD_CTRL),
-};
-
-static unsigned const mba6_ecspi1_cs[] = {
- IMX_GPIO_NR(3, 24),
- IMX_GPIO_NR(3, 25),
-};
-
-static void mba6_setup_iomuxc_spi(void)
-{
- unsigned i;
-
- for (i = 0; i < ARRAY_SIZE(mba6_ecspi1_cs); ++i)
- gpio_direction_output(mba6_ecspi1_cs[i], 1);
- imx_iomux_v3_setup_multiple_pads(mba6_ecspi1_pads,
- ARRAY_SIZE(mba6_ecspi1_pads));
-}
-
int board_phy_config(struct phy_device *phydev)
{
/*
* optimized pad skew values depends on CPU variant on the TQMa6x module:
- * i.MX6Q/D or i.MX6DL/S
+ * CONFIG_TQMA6Q: i.MX6Q/D
+ * CONFIG_TQMA6S: i.MX6S
+ * CONFIG_TQMA6DL: i.MX6DL
*/
-#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q)
+#if defined(CONFIG_TQMA6Q)
#define MBA6X_KSZ9031_CTRL_SKEW 0x0032
#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
#define MBA6X_KSZ9031_RX_SKEW 0x3333
#define MBA6X_KSZ9031_TX_SKEW 0x2036
-#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
#define MBA6X_KSZ9031_CTRL_SKEW 0x0030
#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
#define MBA6X_KSZ9031_RX_SKEW 0x3333
@@ -341,7 +327,6 @@ int tqma6_bb_board_early_init_f(void)
int tqma6_bb_board_init(void)
{
mba6_setup_i2c();
- mba6_setup_iomuxc_spi();
/* do it here - to have reset completed */
mba6_setup_iomuxc_enet();
diff --git a/board/tqc/tqma6/tqma6_wru4.c b/board/tqc/tqma6/tqma6_wru4.c
index c9a7ab7..2360cff 100644
--- a/board/tqc/tqma6/tqma6_wru4.c
+++ b/board/tqc/tqma6/tqma6_wru4.c
@@ -16,10 +16,10 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
#include <common.h>
#include <fsl_esdhc.h>
diff --git a/board/tqc/tqma6/tqma6dl.cfg b/board/tqc/tqma6/tqma6dl.cfg
new file mode 100644
index 0000000..716033f
--- /dev/null
+++ b/board/tqc/tqma6/tqma6dl.cfg
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2014 - 2015 Markus Niebel <Markus.Niebel@tq-group.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+#if defined(CONFIG_TQMA6X_MMC_BOOT)
+BOOT_FROM sd
+#elif defined(CONFIG_TQMA6X_SPI_BOOT)
+BOOT_FROM spi
+#endif
+
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* TQMa6DL DDR config Rev. 0100E */
+/* IOMUX configuration */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
+DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
+
+/* memory interface calibration values */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00440048
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x003D003F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0029002D
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x002B0043
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x424C0250
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02300234
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4234023C
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0224022C
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x48484C4C
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4C4E4E4C
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36382C36
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x34343630
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+
+/* configure memory interface */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00408032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
+#include "clocks.cfg"
generated by cgit v0.10.2 at 2024-09-30 15:38:45 (GMT)