summaryrefslogtreecommitdiff
path: root/board
diff options
context:
space:
mode:
Diffstat (limited to 'board')
-rw-r--r--board/LaCie/net2big_v2/kwbimage.cfg2
-rw-r--r--board/LaCie/netspace_v2/kwbimage-is2.cfg2
-rw-r--r--board/LaCie/netspace_v2/kwbimage-ns2l.cfg2
-rw-r--r--board/LaCie/netspace_v2/kwbimage.cfg2
-rw-r--r--board/LaCie/wireless_space/kwbimage.cfg2
-rw-r--r--board/Marvell/dreamplug/kwbimage.cfg2
-rw-r--r--board/Marvell/guruplug/kwbimage.cfg2
-rw-r--r--board/Marvell/mv88f6281gtw_ge/kwbimage.cfg2
-rw-r--r--board/Marvell/openrd/kwbimage.cfg2
-rw-r--r--board/Marvell/rd6281a/kwbimage.cfg2
-rw-r--r--board/Seagate/dockstar/kwbimage.cfg2
-rw-r--r--board/alaska/Makefile44
-rw-r--r--board/alaska/README482
-rw-r--r--board/alaska/alaska.c153
-rw-r--r--board/alaska/flash.c945
-rw-r--r--board/bf609-ezkit/soft_switch.c171
-rw-r--r--board/bf609-ezkit/soft_switch.h80
-rw-r--r--board/boundary/nitrogen6x/nitrogen6dl.cfg2
-rw-r--r--board/boundary/nitrogen6x/nitrogen6dl2g.cfg2
-rw-r--r--board/boundary/nitrogen6x/nitrogen6q.cfg2
-rw-r--r--board/boundary/nitrogen6x/nitrogen6q2g.cfg2
-rw-r--r--board/boundary/nitrogen6x/nitrogen6s.cfg2
-rw-r--r--board/boundary/nitrogen6x/nitrogen6s1g.cfg2
-rw-r--r--board/buffalo/lsxl/kwbimage-lschl.cfg2
-rw-r--r--board/buffalo/lsxl/kwbimage-lsxhl.cfg2
-rw-r--r--board/cloudengines/pogo_e02/kwbimage.cfg2
-rw-r--r--board/d-link/dns325/kwbimage.cfg2
-rw-r--r--board/esg/ima3-mx53/imximage.cfg2
-rw-r--r--board/freescale/b4860qds/b4860qds.c6
-rw-r--r--board/freescale/b4860qds/b4860qds_crossbar_con.h31
-rw-r--r--board/freescale/b4860qds/ddr.c72
-rw-r--r--board/freescale/b4860qds/eth_b4860qds.c35
-rw-r--r--board/freescale/b4860qds/law.c6
-rw-r--r--board/freescale/b4860qds/tlb.c2
-rw-r--r--board/freescale/common/qixis.h6
-rw-r--r--board/freescale/corenet_ds/eth_superhydra.c8
-rw-r--r--board/freescale/corenet_ds/pbi.cfg2
-rw-r--r--board/freescale/corenet_ds/rcw_p5040ds.cfg11
-rw-r--r--board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg2
-rw-r--r--board/freescale/mx25pdk/imximage.cfg2
-rw-r--r--board/freescale/mx51evk/imximage.cfg2
-rw-r--r--board/freescale/mx53ard/imximage_dd3.cfg2
-rw-r--r--board/freescale/mx53evk/imximage.cfg2
-rw-r--r--board/freescale/mx53loco/imximage.cfg2
-rw-r--r--board/freescale/mx53smd/imximage.cfg2
-rw-r--r--board/freescale/mx6qarm2/imximage.cfg2
-rw-r--r--board/freescale/mx6qsabreauto/imximage.cfg2
-rw-r--r--board/freescale/p2041rdb/p2041rdb.c11
-rw-r--r--board/freescale/t4qds/ddr.c56
-rw-r--r--board/freescale/t4qds/eth.c371
-rw-r--r--board/freescale/t4qds/law.c3
-rw-r--r--board/freescale/t4qds/t4240qds_qixis.h2
-rw-r--r--board/freescale/t4qds/t4_pbi.cfg36
-rw-r--r--board/freescale/t4qds/t4_rcw.cfg7
-rw-r--r--board/freescale/t4qds/t4qds.c405
-rw-r--r--board/freescale/t4qds/tlb.c2
-rw-r--r--board/genesi/mx51_efikamx/imximage_mx.cfg2
-rw-r--r--board/genesi/mx51_efikamx/imximage_sb.cfg2
-rw-r--r--board/iomega/iconnect/kwbimage.cfg2
-rw-r--r--board/karo/tk71/kwbimage.cfg2
-rw-r--r--board/keymile/km_arm/kwbimage-memphis.cfg2
-rw-r--r--board/keymile/km_arm/kwbimage.cfg2
-rw-r--r--board/keymile/km_arm/kwbimage_128M16_1.cfg2
-rw-r--r--board/keymile/km_arm/kwbimage_256M8_1.cfg2
-rw-r--r--board/openrisc/openrisc-generic/u-boot.lds77
-rw-r--r--board/raidsonic/ib62x0/kwbimage.cfg2
-rw-r--r--board/sorcery/Makefile44
-rw-r--r--board/sorcery/sorcery.c68
-rw-r--r--board/ttcontrol/vision2/imximage_hynix.cfg2
-rw-r--r--board/xilinx/microblaze-generic/microblaze-generic.c17
70 files changed, 1255 insertions, 1980 deletions
diff --git a/board/LaCie/net2big_v2/kwbimage.cfg b/board/LaCie/net2big_v2/kwbimage.cfg
index 8d9f153..d3904d3 100644
--- a/board/LaCie/net2big_v2/kwbimage.cfg
+++ b/board/LaCie/net2big_v2/kwbimage.cfg
@@ -19,7 +19,7 @@
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/LaCie/netspace_v2/kwbimage-is2.cfg b/board/LaCie/netspace_v2/kwbimage-is2.cfg
index 590720a..93b803c 100644
--- a/board/LaCie/netspace_v2/kwbimage-is2.cfg
+++ b/board/LaCie/netspace_v2/kwbimage-is2.cfg
@@ -19,7 +19,7 @@
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg b/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
index d008eb0..0a8a514 100644
--- a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
+++ b/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
@@ -19,7 +19,7 @@
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/LaCie/netspace_v2/kwbimage.cfg b/board/LaCie/netspace_v2/kwbimage.cfg
index 7e53649..0cf4682 100644
--- a/board/LaCie/netspace_v2/kwbimage.cfg
+++ b/board/LaCie/netspace_v2/kwbimage.cfg
@@ -19,7 +19,7 @@
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/LaCie/wireless_space/kwbimage.cfg b/board/LaCie/wireless_space/kwbimage.cfg
index 0daf5b5..aeddc0c 100644
--- a/board/LaCie/wireless_space/kwbimage.cfg
+++ b/board/LaCie/wireless_space/kwbimage.cfg
@@ -22,7 +22,7 @@
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/Marvell/dreamplug/kwbimage.cfg b/board/Marvell/dreamplug/kwbimage.cfg
index ca9cd74..e662b2d 100644
--- a/board/Marvell/dreamplug/kwbimage.cfg
+++ b/board/Marvell/dreamplug/kwbimage.cfg
@@ -24,7 +24,7 @@
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/Marvell/guruplug/kwbimage.cfg b/board/Marvell/guruplug/kwbimage.cfg
index 2afd927..9baf6bc 100644
--- a/board/Marvell/guruplug/kwbimage.cfg
+++ b/board/Marvell/guruplug/kwbimage.cfg
@@ -21,7 +21,7 @@
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg b/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg
index ec2513f..f74d443 100644
--- a/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg
+++ b/board/Marvell/mv88f6281gtw_ge/kwbimage.cfg
@@ -21,7 +21,7 @@
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/Marvell/openrd/kwbimage.cfg b/board/Marvell/openrd/kwbimage.cfg
index 757eb28..19d0bac 100644
--- a/board/Marvell/openrd/kwbimage.cfg
+++ b/board/Marvell/openrd/kwbimage.cfg
@@ -21,7 +21,7 @@
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/Marvell/rd6281a/kwbimage.cfg b/board/Marvell/rd6281a/kwbimage.cfg
index 0d12dd9..c8b5d74 100644
--- a/board/Marvell/rd6281a/kwbimage.cfg
+++ b/board/Marvell/rd6281a/kwbimage.cfg
@@ -21,7 +21,7 @@
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/Seagate/dockstar/kwbimage.cfg b/board/Seagate/dockstar/kwbimage.cfg
index 98b514d..4b0351d 100644
--- a/board/Seagate/dockstar/kwbimage.cfg
+++ b/board/Seagate/dockstar/kwbimage.cfg
@@ -24,7 +24,7 @@
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/alaska/Makefile b/board/alaska/Makefile
deleted file mode 100644
index a21f851..0000000
--- a/board/alaska/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS := $(BOARD).o flash.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/alaska/README b/board/alaska/README
deleted file mode 100644
index 3345073..0000000
--- a/board/alaska/README
+++ /dev/null
@@ -1,482 +0,0 @@
-Freescale Alaska MPC8220 board
-==============================
-
-TsiChung Liew(Tsi-Chung.Liew@freescale.com)
-Created 9/21/04
-===========================================
-
-
-Changed files:
-==============
-
-- Makefile added MPC8220 and Alaska8220_config
-- MAKEALL added MPC8220 and Alaska8220
-- README added CONFIG_MPC8220, Alaska8220_config
-
-- common/cmd_bdinfo.c added board information members for MPC8220
-- common/cmd_bootm.c added clocks for MPC8220 in do_bootm_linux()
-
-- include/common.h added CONFIG_MPC8220
-
-- include/asm-ppc/u-boot.h added board information members for MPC8220
-- include/asm-ppc/global_data.h added global variables - inp_clk, pci_clk,
- vco_clk, pev_clk, flb_clk, and bExtUart
-
-- arch/powerpc/lib/board.c added CONFIG_MPC8220 support
-
-- net/eth.c added FEC support for MPC8220
-
-Added files:
-============
-- board/alaska directory for Alaska MPC8220
-- board/alaska/alaska.c Alaska dram and BATs setup
-- board/alaska/extserial.c external serial (debug card serial) support
-- board/alaska/flash.c Socket (AMD) and Onboard (INTEL) flash support
-- board/alaska/serial.c to determine which int/ext serial to use
-- board/alaska/Makefile Makefile
-- board/alaska/config.mk config make
-- board/alaska/u-boot.lds Linker description
-
-- arch/powerpc/cpu/mpc8220/dma.h multi-channel dma header file
-- arch/powerpc/cpu/mpc8220/dramSetup.h dram setup header file
-- arch/powerpc/cpu/mpc8220/fec.h MPC8220 FEC header file
-- arch/powerpc/cpu/mpc8220/cpu.c cpu specific code
-- arch/powerpc/cpu/mpc8220/cpu_init.c Flexbus ChipSelect and Mux pins setup
-- arch/powerpc/cpu/mpc8220/dramSetup.c MPC8220 DDR SDRAM setup
-- arch/powerpc/cpu/mpc8220/fec.c MPC8220 FEC driver
-- arch/powerpc/cpu/mpc8220/i2c.c MPC8220 I2C driver
-- arch/powerpc/cpu/mpc8220/interrupts.c interrupt support (not enable)
-- arch/powerpc/cpu/mpc8220/loadtask.c load dma
-- arch/powerpc/cpu/mpc8220/speed.c system, pci, flexbus, pev, and cpu clock
-- arch/powerpc/cpu/mpc8220/traps.c exception
-- arch/powerpc/cpu/mpc8220/uart.c MPC8220 UART driver
-- arch/powerpc/cpu/mpc8220/Makefile Makefile
-- arch/powerpc/cpu/mpc8220/config.mk config make
-- arch/powerpc/cpu/mpc8220/fec_dma_task.S MPC8220 FEC multi-channel dma program
-- arch/powerpc/cpu/mpc8220/io.S io functions
-- arch/powerpc/cpu/mpc8220/start.S start up
-
-- include/mpc8220.h
-
-- include/asm-ppc/immap_8220.h
-
-- include/configs/Alaska8220.h
-
-
-1. SWITCH SETTINGS
-==================
-1.1 SW1: 0 - Boot from Socket Flash (AMD) or 1 - Onboard Flash (INTEL)
- SW2: 0 - Select MPC8220 UART or 1 - Debug Card UART
- SW3: unsed
- SW4: 0 - 1284 or 1 - FEC1
- SW5: 0 - PEV or 1 - FEC2
-
-
-2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
-===========================================
-2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and
- linux kernel, you can customize it based on your system requirements:
- DDR: 0x00000000-0x1fffffff (max 512MB)
- MBAR: 0xf0000000-0xf0027fff (128KB)
- CPLD: 0xf1000000-0xf103ffff (256KB)
- FPGA: 0xf2000000-0xf203ffff (256KB)
- Flash: 0xfe000000-0xffffffff (max 32MB)
-
-3. DEFINITIONS AND COMPILATION
-==============================
-3.1 Explanation on NEW definitions in include/configs/alaska8220.h
- CONFIG_MPC8220 MPC8220 specific
- CONFIG_ALASKA8220 Alaska board specific
- CONFIG_SYS_MPC8220_CLKIN Define Alaska Input Clock
- CONFIG_PSC_CONSOLE Enable MPC8220 UART
- CONFIG_EXTUART_CONSOLE Enable External 16552 UART
- CONFIG_SYS_AMD_BOOT To determine the u-boot is booted from AMD or Intel
- CONFIG_SYS_MBAR MBAR base address
- CONFIG_SYS_DEFAULT_MBAR Reset MBAR base address
-
-3.2 Compilation
- export CROSS_COMPILE=cross-compile-prefix
- cd u-boot-1-1-x
- make distclean
- make Alaska8220_config
- make
-
-
-4. SCREEN DUMP
-==============
-4.1 Alaska MPC8220 board
- Boot from AMD (NOTE: May not show exactly the same)
-
-U-Boot 1.1.1 (Sep 22 2004 - 22:14:41)
-
-CPU: MPC8220 (JTAG ID 1640301d) at 300 MHz
- Bus 120 MHz, CPU 300 MHz, PCI 30 MHz, VCO 480 MHz
-Board: Alaska MPC8220 Evaluation Board
-I2C: 93 kHz, ready
-DRAM: 256 MB
-Reserving 167k for U-Boot at: 0ffd6000
-FLASH: 16.5 MB
-*** Warning - bad CRC, using default environment
-
-In: serial
-Out: serial
-Err: serial
-Net: FEC ETHERNET
-=> flinfo
-
-Bank # 1: INTEL 28F128J3A
- Size: 8 MB in 64 Sectors
- Sector Start Addresses:
- FE000000 FE020000 FE040000 FE060000 FE080000
- FE0A0000 FE0C0000 FE0E0000 FE100000 FE120000
- FE140000 FE160000 FE180000 FE1A0000 FE1C0000
- FE1E0000 FE200000 FE220000 FE240000 FE260000
- FE280000 FE2A0000 FE2C0000 FE2E0000 FE300000
- FE320000 FE340000 FE360000 FE380000 FE3A0000
- FE3C0000 FE3E0000 FE400000 FE420000 FE440000
- FE460000 FE480000 FE4A0000 FE4C0000 FE4E0000
- FE500000 FE520000 FE540000 FE560000 FE580000
- FE5A0000 FE5C0000 FE5E0000 FE600000 FE620000
- FE640000 FE660000 FE680000 FE6A0000 FE6C0000
- FE6E0000 FE700000 FE720000 FE740000 FE760000
- FE780000 FE7A0000 FE7C0000 FE7E0000
-
-Bank # 2: INTEL 28F128J3A
- Size: 8 MB in 64 Sectors
- Sector Start Addresses:
- FE800000 FE820000 FE840000 FE860000 FE880000
- FE8A0000 FE8C0000 FE8E0000 FE900000 FE920000
- FE940000 FE960000 FE980000 FE9A0000 FE9C0000
- FE9E0000 FEA00000 FEA20000 FEA40000 FEA60000
- FEA80000 FEAA0000 FEAC0000 FEAE0000 FEB00000
- FEB20000 FEB40000 FEB60000 FEB80000 FEBA0000
- FEBC0000 FEBE0000 FEC00000 FEC20000 FEC40000
- FEC60000 FEC80000 FECA0000 FECC0000 FECE0000
- FED00000 FED20000 FED40000 FED60000 FED80000
- FEDA0000 FEDC0000 FEDE0000 FEE00000 FEE20000
- FEE40000 FEE60000 FEE80000 FEEA0000 FEEC0000
- FEEE0000 FEF00000 (RO) FEF20000 (RO) FEF40000 FEF60000
- FEF80000 FEFA0000 FEFC0000 FEFE0000 (RO)
-
-Bank # 3: AMD AMD29F040B
- Size: 0 MB in 7 Sectors
- Sector Start Addresses:
- FFF00000 (RO) FFF10000 (RO) FFF20000 (RO) FFF30000 FFF40000
- FFF50000 FFF60000
-
-Bank # 4: AMD AMD29F040B
- Size: 0 MB in 1 Sectors
- Sector Start Addresses:
- FFF70000 (RO)
-=> bdinfo
-
-memstart = 0xF0009800
-memsize = 0x10000000
-flashstart = 0xFFF00000
-flashsize = 0x01080000
-flashoffset = 0x00025000
-sramstart = 0xF0020000
-sramsize = 0x00008000
-bootflags = 0x00000001
-intfreq = 300 MHz
-busfreq = 120 MHz
-inpfreq = 30 MHz
-flbfreq = 30 MHz
-pcifreq = 30 MHz
-vcofreq = 480 MHz
-pevfreq = 81 MHz
-ethaddr = 00:E0:0C:BC:E0:60
-eth1addr = 00:E0:0C:BC:E0:61
-IP addr = 192.162.1.2
-baudrate = 115200 bps
-=> printenv
-bootargs=root=/dev/ram rw
-bootdelay=5
-baudrate=115200
-ethaddr=00:e0:0c:bc:e0:60
-eth1addr=00:e0:0c:bc:e0:61
-ipaddr=192.162.1.2
-serverip=192.162.1.1
-gatewayip=192.162.1.1
-netmask=255.255.255.0
-hostname=Alaska
-stdin=serial
-stdout=serial
-stderr=serial
-ethact=FEC ETHERNET
-
-Environment size: 268/65532 bytes
-=> setenv ipaddr 192.160.1.2
-=> setenv serverip 192.160.1.1
-=> setenv gatewayip 192.160.1.1
-=> saveenv
-Saving Environment to Flash...
-
-.
-Un-Protected 1 sectors
-Erasing Flash...
-Erasing sector 0 ... done
-Erased 1 sectors
-Writing to Flash... done
-
-.
-Protected 1 sectors
-=> tftp 0x10000 linux.elf
-Using FEC ETHERNET device
-TFTP from server 192.160.1.1; our IP address is 192.160.1.2; sending through gateway 192.160.1.1
-Filename 'linux.elf'.
-Load address: 0x10000
-Loading: invalid RARP header
-#################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- #################################################################
- ##################################################
-done
-Bytes transferred = 2917494 (2c8476 hex)
-=> bootelf
-Loading .text @ 0x00a00000 (23820 bytes)
-Loading .data @ 0x00a06000 (2752512 bytes)
-Clearing .bss @ 0x00ca6000 (12764 bytes)
-## Starting application at 0x00a00000 ...
-
-Collect some entropy from RAM........done
-loaded at: 00A00000 00CA91DC
-zimage at: 00A06A93 00AD7756
-initrd at: 00AD8000 00CA5565
-avail ram: 00CAA000 014AA000
-
-Linux/PPC load: ip=off console=ttyS0,115200
-Uncompressing Linux...done.
-Now booting the kernel
-Total memory in system: 256 MB
-Memory BAT mapping: BAT2=256Mb, BAT3=0Mb, residual: 0Mb
-Linux version 2.4.21-rc1 (r61688@bluesocks.sps.mot.com) (gcc version 3.3.1) #17 Wed Sep 8 11:49:16 CDT 2004
-Motorola Alaska port (C) 2003 Motorola, Inc.
-CPLD rev 3
-CPLD switches 0x1b
-Set Pin Mux for FEC1
-Set Pin Mux for FEC2
-Alaska Pin Multiplexing:
-Port Configuration Register 0 = 0
-Port Configuration Register 1 = 0
-Port Configuration Register 2 = 0
-Port Configuration Register 3 = 50000000
-Port Configuration Register 3 - PCI = 51400180
-Setup Alaska FPGA PIC:
-Interrupt Enable Register *(u32) = 0
-Interrupt Status Register = 2f0000
-Interrupt Enable Register in_be32 = 0
-Interrupt Status Register = 2f0000
-Interrupt Enable Register in_le32 = 0
-Interrupt Status Register = 2f00
-Interrupt Enable Register readl = 0
-Interrupt Status Register = 2f00
-Interrupt Enable Register = 0
-Interrupt Status Register = 2f0000
-Setup Alaska PCI Controller:
-On node 0 totalpages: 65536
-zone(0): 65536 pages.
-zone(1): 0 pages.
-zone(2): 0 pages.
-Kernel command line: ip=off console=ttyS0,115200
-Using XLB clock (120.00 MHz) to set up decrementer
-Calibrating delay loop... 199.88 BogoMIPS
-Memory: 254792k available (1476k kernel code, 708k data, 228k init, 0k highmem)
-Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
-Inode cache hash table entries: 16384 (order: 5, 131072 bytes)
-Mount cache hash table entries: 512 (order: 0, 4096 bytes)
-Buffer-cache hash table entries: 16384 (order: 4, 65536 bytes)
-Page-cache hash table entries: 65536 (order: 6, 262144 bytes)
-POSIX conformance testing by UNIFIX
-PCI: Probing PCI hardware
-PCI: (pcibios_init) Global-Hose = 0xc029d000
-Scanning bus 00
-Fixups for bus 00
-Bus scan for 00 returning with max=00
-PCI: (pcibios_init) finished pci_scan_bus(hose->first_busno = 0, hose->ops = c01a1a74, hose = c029d000)
-PCI: (pcibios_init) PCI Bus Count = 0 =?= Next Bus# = 1
-PCI: (pcibios_init@pci_fixup_irqs) finished machine dependent PCI interrupt routing!
-PCI: bridge rsrc 81000000..81ffffff (100), parent c01a7f88
-PCI: bridge rsrc 84000000..87ffffff (200), parent c01a7fa4
-PCI: (pcibios_init) finished allocating and assigning resources!
-initDma!
-Using 90 DMA buffer descriptors
-descUsed f0023600, descriptors f002360c freeSram f0024140
-unmask SDMA tasks: 0xf0008018 = 0x6f000000
-Linux NET4.0 for Linux 2.4
-Based upon Swansea University Computer Society NET3.039
-Initializing RT netlink socket
-Starting kswapd
-Journalled Block Device driver loaded
-JFFS version 1.0, (C) 1999, 2000 Axis Communications AB
-JFFS2 version 2.1. (C) 2001 Red Hat, Inc., designed by Axis Communications AB.
-pty: 256 Unix98 ptys configured
-tracek: Copyright (C) Motorola, 2003.
-Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
-ttyS00 at 0xf1001008 (irq = 73) is a ST16650
-ttyS01 at 0xf1001010 (irq = 74) is a ST16650
-elp-fpanel: Copyright (C) Motorola, 2003.
-fpanel: fpanelWait timeout
-elp-engine: Copyright (C) Motorola, 2003.
-Video disabled due to configuration switch 4
-Alpine 1284 driver: Copyright (C) Motorola, 2003.
-1284 disabled due to configuration switch 5
-Alpine USB driver: Copyright (C) Motorola, 2003.
-OK
-USB: Descriptor download completed OK
-enable_irq(41) unbalanced
-enable_irq(75) unbalanced
-elp-dmaram: Copyright (C) Motorola, 2003.
-Total memory in system: 256 MB
-elp_dmaram: offset is 0x10000000, size is 0
-Xicor NVRAM driver: Copyright (C) Motorola, 2003.
-elp-video: Copyright (C) Motorola, 2003.
-Video disabled due to configuration switch 4
-elp-pfm: Copyright (C) Motorola, 2003.
-paddle: Copyright (C) Motorola, 2001, present.
-RAMDISK driver initialized: 16 RAM disks of 12288K size 1024 blocksize
-loop: loaded (max 8 devices)
-PPP generic driver version 2.4.2
-PPP Deflate Compression module registered
-Uniform Multi-Platform E-IDE driver Revision: 7.00beta-2.4
-ide: Assuming 50MHz system bus speed for PIO modes; override with idebus=xx
-init_alaska_mtd: chip probing count 0
-cfi_cmdset_0001: Erase suspend on write enabled
-Using buffer write method
-init_alaska_mtd: bank1, name:ALASKA0, size:16777216bytes
-ALASKA flash0: Using Static image partition definition
-Creating 3 MTD partitions on "ALASKA0":
-0x00000000-0x00280000 : "kernel"
-0x00280000-0x00fe0000 : "user"
-0x00fe0000-0x01000000 : "signature"
-mgt_fec_module_init
-mgt_fec_init()
-mgt_fec_init
-mgt_init_fec_dev(0xc05f6000,0)
-dev c05f6000 fec_priv c05f6160 fec f0009000
-mgt_init_fec_dev(0xc05f6800,1)
-dev c05f6800 fec_priv c05f6960 fec f0009800
-NET4: Linux TCP/IP 1.0 for NET4.0
-IP Protocols: ICMP, UDP, TCP, IGMP
-IP: routing cache hash table of 2048 buckets, 16Kbytes
-TCP: Hash tables configured (established 16384 bind 32768)
-NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
-RAMDISK: Compressed image found at block 0
-Freeing initrd memory: 1845k freed
-JFFS: Trying to mount a non-mtd device.
-VFS: Mounted root (romfs filesystem) readonly.
-Freeing unused kernel memory: 228k init
-INIT: version 2.78 booting
-INIT: Entering runlevel: 1
-"Space, a great big place of unknown stuff." -Dexter, for our MotD.
-[01/Jan/1970:00:00:01 +0000] boa: server version Boa/0.94.8.3
-[01/Jan/1970:00:00:01 +0000] boa: server built Sep 7 2004 at 17:40:55.
-[01/Jan/1970:00:00:01 +0000] boa: starting server pid=28, port 80
-Mounting flash filesystem, will take a minute...
-/etc/rc: line 30: /dev/lp0: No such devish-2.05b#
-sh-2.05b# ifup eth0
-client (v0.9.9-pre) started
-adapter index 2
-adapter hardware address 00:e0:0c:bc:e0:60
-execle'ing /usr/share/udhcpc/default.script
-/sbin/ifconfig eth0
-eth0 Link encap:Ethernet HWaddr 00:E0:0C:BC:E0:60
- BROADCAST MULTICAST MTU:1500 Metric:1
- mgt_fec_open
- Rfec request irq
-X fec_open: rcv_ring_size 8, xmt_ring_size 8
-packmgt_fec_open(): call netif_start_queue()
-ets:0 errors:0 dropped:0 overruns:0 frame:0
- TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
- collisions:0 txqueuelen:100
- RX bytes:0 (0.0 b) TX bytes:0 (0.0 b)
- Base address:0x9000
-
-/sbin/ifconfig eth0 up
-entering raw listen mode
-Opening raw socket on ifindex 2
-adding option 0x35
-adding option 0x3d
-adding option 0x3c
-Sending discover...
-Waiting on select...
-unrelated/bogus packet
-Waiting on select...
-oooooh!!! got some!
-adding option 0x35
-adding option 0x3d
-adding option 0x3c
-adding option 0x32
-adding option 0x36
-Sending select for 163.12.48.146...
-Waiting on select...
-oooooh!!! got some!
-Waiting on select...
-oooooh!!! got some!
-Lease of 163.12.48.146 obtained, lease time 345600
-execle'ing /usr/share/udhcpc/default.script
-/sbin/ifconfig eth0 163.12.48.146 netmask 255.255.254.0
-/sbin/ifconfig eth0 up
-deleting routers
-/sbin/route del default
-/sbin/route add default gw 163.12.49.254 dev eth0
-adding dns 163.12.252.230
-adding dns 192.55.22.4
-adding dns 192.5.249.4
-entering none listen mode
-sh-2.05b#
-
-5. REPROGRAM U-BOOT
-===================
-5.1 Reprogram u-boot (boot from AMD)
- 1. Unprotect the boot sector
- => protect off bank 3
- 2. Download new u-boot binary file
- => tftp 0x10000 u-boot.bin
- 3. Erase bootsector (max 7 sectors)
- => erase 0xfff00000 0xfff6ffff
- 4. Program the u-boot to flash
- => cp.b 0x10000 0xfff00000
- 5. Reset for the new u-boot to take place
- => reset
-
-5.2 Reprogram u-boot (boot from AMD program at INTEL)
- 1. Unprotect the boot sector
- => protect off bank 2
- 2. Download new u-boot binary file
- => tftp 0x10000 u-boot.bin
- 3. Erase bootsector (max 7 sectors)
- => erase 0xfef00000 0xfefdffff
- 4. Program the u-boot to flash
- => cp.b 0x10000 0xfef00000
- 5. Reset for the new u-boot to take place
- => reset
-
-5.3 Reprogram u-boot (boot from INTEL)
- 1. Unprotect the boot sector
- => protect off bank 4
- 2. Download new u-boot binary file
- => tftp 0x10000 u-boot.bin
- 3. Erase bootsector (max 7 sectors)
- => erase 0xfff00000 0xfffdffff
- 4. Program the u-boot to flash
- => cp.b 0x10000 0xfff00000
- 5. Reset for the new u-boot to take place
- => reset
-
-5.4 Reprogram u-boot (boot from INTEL program at AMD)
- 1. Unprotect the boot sector
- => protect off bank 1
- 2. Download new u-boot binary file
- => tftp 0x10000 u-boot.bin
- 3. Erase bootsector (max 7 sectors)
- => erase 0xfe080000 0xfe0effff
- 4. Program the u-boot to flash
- => cp.b 0x10000 0xfe080000
- 5. Reset for the new u-boot to take place
- => reset
diff --git a/board/alaska/alaska.c b/board/alaska/alaska.c
deleted file mode 100644
index 89c1abd..0000000
--- a/board/alaska/alaska.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * (C) Copyright 2004, Freescale Inc.
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8220.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-
-void setupBat (ulong size)
-{
- ulong batu, batl;
- int blocksize = 0;
-
- /* Flash 0 */
-#if defined (CONFIG_SYS_AMD_BOOT)
- batu = CONFIG_SYS_FLASH0_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
-#else
- batu = CONFIG_SYS_FLASH0_BASE | BATU_BL_16M | BPP_RW | BPP_RX;
-#endif
- batl = CONFIG_SYS_FLASH0_BASE | 0x22;
- write_bat (IBAT0, batu, batl);
- write_bat (DBAT0, batu, batl);
-
- /* Flash 1 */
-#if defined (CONFIG_SYS_AMD_BOOT)
- batu = CONFIG_SYS_FLASH1_BASE | BATU_BL_16M | BPP_RW | BPP_RX;
-#else
- batu = CONFIG_SYS_FLASH1_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
-#endif
- batl = CONFIG_SYS_FLASH1_BASE | 0x22;
- write_bat (IBAT1, batu, batl);
- write_bat (DBAT1, batu, batl);
-
- /* CPLD */
- batu = CONFIG_SYS_CPLD_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
- batl = CONFIG_SYS_CPLD_BASE | 0x22;
- write_bat (IBAT2, 0, 0);
- write_bat (DBAT2, batu, batl);
-
- /* FPGA */
- batu = CONFIG_SYS_FPGA_BASE | BATU_BL_512K | BPP_RW | BPP_RX;
- batl = CONFIG_SYS_FPGA_BASE | 0x22;
- write_bat (IBAT3, 0, 0);
- write_bat (DBAT3, batu, batl);
-
- /* MBAR - Data only */
- batu = CONFIG_SYS_MBAR | BPP_RW | BPP_RX;
- batl = CONFIG_SYS_MBAR | 0x22;
- mtspr (IBAT4L, 0);
- mtspr (IBAT4U, 0);
- mtspr (DBAT4L, batl);
- mtspr (DBAT4U, batu);
-
- /* MBAR - SRAM */
- batu = CONFIG_SYS_SRAM_BASE | BPP_RW | BPP_RX;
- batl = CONFIG_SYS_SRAM_BASE | 0x42;
- mtspr (IBAT5L, batl);
- mtspr (IBAT5U, batu);
- mtspr (DBAT5L, batl);
- mtspr (DBAT5U, batu);
-
- if (size <= 0x800000) /* 8MB */
- blocksize = BATU_BL_8M;
- else if (size <= 0x1000000) /* 16MB */
- blocksize = BATU_BL_16M;
- else if (size <= 0x2000000) /* 32MB */
- blocksize = BATU_BL_32M;
- else if (size <= 0x4000000) /* 64MB */
- blocksize = BATU_BL_64M;
- else if (size <= 0x8000000) /* 128MB */
- blocksize = BATU_BL_128M;
- else if (size <= 0x10000000) /* 256MB */
- blocksize = BATU_BL_256M;
-
- /* Memory */
- batu = CONFIG_SYS_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
- batl = CONFIG_SYS_SDRAM_BASE | 0x42;
- mtspr (IBAT6L, batl);
- mtspr (IBAT6U, batu);
- mtspr (DBAT6L, batl);
- mtspr (DBAT6U, batu);
-
- /* memory size is less than 256MB */
- if (size <= 0x10000000) {
- /* Nothing */
- batu = 0;
- batl = 0;
- } else {
- size -= 0x10000000;
- if (size <= 0x800000) /* 8MB */
- blocksize = BATU_BL_8M;
- else if (size <= 0x1000000) /* 16MB */
- blocksize = BATU_BL_16M;
- else if (size <= 0x2000000) /* 32MB */
- blocksize = BATU_BL_32M;
- else if (size <= 0x4000000) /* 64MB */
- blocksize = BATU_BL_64M;
- else if (size <= 0x8000000) /* 128MB */
- blocksize = BATU_BL_128M;
- else if (size <= 0x10000000) /* 256MB */
- blocksize = BATU_BL_256M;
-
- batu = (CONFIG_SYS_SDRAM_BASE +
- 0x10000000) | blocksize | BPP_RW | BPP_RX;
- batl = (CONFIG_SYS_SDRAM_BASE + 0x10000000) | 0x42;
- }
-
- mtspr (IBAT7L, batl);
- mtspr (IBAT7U, batu);
- mtspr (DBAT7L, batl);
- mtspr (DBAT7U, batu);
-}
-
-phys_size_t initdram (int board_type)
-{
- ulong size;
-
- size = dramSetup ();
-
-/* if iCache ad dCache is defined */
-#if defined(CONFIG_CMD_CACHE)
-/* setupBat(size);*/
-#endif
-
- return size;
-}
-
-int checkboard (void)
-{
- puts ("Board: Alaska MPC8220 Evaluation Board\n");
-
- return 0;
-}
diff --git a/board/alaska/flash.c b/board/alaska/flash.c
deleted file mode 100644
index 977822a..0000000
--- a/board/alaska/flash.c
+++ /dev/null
@@ -1,945 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* Board support for 1 or 2 flash devices */
-#define FLASH_PORT_WIDTH8
-
-typedef unsigned char FLASH_PORT_WIDTH;
-typedef volatile unsigned char FLASH_PORT_WIDTHV;
-
-#define SWAP(x) (x)
-
-/* Intel-compatible flash ID */
-#define INTEL_COMPAT 0x89
-#define INTEL_ALT 0xB0
-
-/* Intel-compatible flash commands */
-#define INTEL_PROGRAM 0x10
-#define INTEL_ERASE 0x20
-#define INTEL_CLEAR 0x50
-#define INTEL_LOCKBIT 0x60
-#define INTEL_PROTECT 0x01
-#define INTEL_STATUS 0x70
-#define INTEL_READID 0x90
-#define INTEL_CONFIRM 0xD0
-#define INTEL_RESET 0xFF
-
-/* Intel-compatible flash status bits */
-#define INTEL_FINISHED 0x80
-#define INTEL_OK 0x80
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define FLASH_CYCLE1 0x0555
-#define FLASH_CYCLE2 0x02aa
-
-#define WR_BLOCK 0x20
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static int write_data_block (flash_info_t * info, ulong src, ulong dest);
-static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-static void flash_sync_real_protect (flash_info_t * info);
-static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
-static unsigned char same_chip_banks (int bank1, int bank2);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- int i;
- ulong size = 0;
- ulong fsize = 0;
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- memset (&flash_info[i], 0, sizeof (flash_info_t));
-
- switch (i) {
- case 0:
- flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE,
- &flash_info[i]);
- flash_get_offsets (CONFIG_SYS_FLASH1_BASE, &flash_info[i]);
- break;
- case 1:
- flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE,
- &flash_info[i]);
- fsize = CONFIG_SYS_FLASH1_BASE + flash_info[i - 1].size;
- flash_get_offsets (fsize, &flash_info[i]);
- break;
- case 2:
- flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE,
- &flash_info[i]);
- flash_get_offsets (CONFIG_SYS_FLASH0_BASE, &flash_info[i]);
- break;
- case 3:
- flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE,
- &flash_info[i]);
- fsize = CONFIG_SYS_FLASH0_BASE + flash_info[i - 1].size;
- flash_get_offsets (fsize, &flash_info[i]);
- break;
- default:
- panic ("configured to many flash banks!\n");
- break;
- }
- size += flash_info[i].size;
-
- /* get the h/w and s/w protection status in sync */
- flash_sync_real_protect(&flash_info[i]);
- }
-
- /* Protect monitor and environment sectors
- */
-#if defined (CONFIG_SYS_AMD_BOOT)
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[2]);
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_INTEL_BASE,
- CONFIG_SYS_INTEL_BASE + monitor_flash_len - 1,
- &flash_info[1]);
-#else
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[3]);
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_AMD_BASE,
- CONFIG_SYS_AMD_BASE + monitor_flash_len - 1, &flash_info[0]);
-#endif
-
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV1_ADDR,
- CONFIG_ENV1_ADDR + CONFIG_ENV1_SIZE - 1, &flash_info[1]);
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[3]);
-
- return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN)
- return;
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * PHYS_AMD_SECT_SIZE);
- info->protect[i] = 0;
- }
- }
-
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base + (i * PHYS_INTEL_SECT_SIZE);
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("INTEL ");
- break;
- case FLASH_MAN_AMD:
- printf ("AMD ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F128J3A:
- printf ("28F128J3A\n");
- break;
-
- case FLASH_AM040:
- printf ("AMD29F040B\n");
- break;
-
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info)
-{
- FPWV value;
- static int amd = 0;
-
- /* Write auto select command: read Manufacturer ID */
- /* Write auto select command sequence and test FLASH answer */
- addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */
- __asm__ ("sync");
- addr[FLASH_CYCLE2] = (FPW) 0x00550055; /* for AMD, Intel ignores this */
- __asm__ ("sync");
- addr[FLASH_CYCLE1] = (FPW) 0x00900090; /* selects Intel or AMD */
- __asm__ ("sync");
-
- udelay (100);
-
- switch (addr[0] & 0xff) {
-
- case (uchar) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- value = addr[1];
- break;
-
- case (uchar) INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- value = addr[2];
- break;
-
- default:
- printf ("unknown\n");
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
- return (0); /* no or unknown flash */
- }
-
- switch (value) {
-
- case (FPW) INTEL_ID_28F128J3A:
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 64;
- info->size = 0x00800000; /* => 16 MB */
- break;
-
- case (FPW) AMD_ID_LV040B:
- info->flash_id += FLASH_AM040;
- if (amd == 0) {
- info->sector_count = 7;
- info->size = 0x00070000; /* => 448 KB */
- amd = 1;
- } else {
- /* for Environment settings */
- info->sector_count = 1;
- info->size = PHYS_AMD_SECT_SIZE; /* => 64 KB */
- amd = 0;
- }
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- break;
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
-
- if (value == (FPW) INTEL_ID_28F128J3A)
- addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
- else
- addr[0] = (FPW) 0x00F000F0; /* restore read mode */
-
- return (info->size);
-}
-
-
-/*
- * This function gets the u-boot flash sector protection status
- * (flash_info_t.protect[]) in sync with the sector protection
- * status stored in hardware.
- */
-static void flash_sync_real_protect (flash_info_t * info)
-{
- int i;
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F128J3A:
- for (i = 0; i < info->sector_count; ++i) {
- info->protect[i] = intel_sector_protected(info, i);
- }
- break;
- case FLASH_AM040:
- default:
- /* no h/w protect support */
- break;
- }
-}
-
-
-/*
- * checks if "sector" in bank "info" is protected. Should work on intel
- * strata flash chips 28FxxxJ3x in 8-bit mode.
- * Returns 1 if sector is protected (or timed-out while trying to read
- * protection status), 0 if it is not.
- */
-static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
-{
- FPWV *addr;
- FPWV *lock_conf_addr;
- ulong start;
- unsigned char ret;
-
- /*
- * first, wait for the WSM to be finished. The rationale for
- * waiting for the WSM to become idle for at most
- * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy
- * because of: (1) erase, (2) program or (3) lock bit
- * configuration. So we just wait for the longest timeout of
- * the (1)-(3), i.e. the erase timeout.
- */
-
- /* wait at least 35ns (W12) before issuing Read Status Register */
- udelay(1);
- addr = (FPWV *) info->start[sector];
- *addr = (FPW) INTEL_STATUS;
-
- start = get_timer (0);
- while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
- if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- *addr = (FPW) INTEL_RESET; /* restore read mode */
- printf("WSM busy too long, can't get prot status\n");
- return 1;
- }
- }
-
- /* issue the Read Identifier Codes command */
- *addr = (FPW) INTEL_READID;
-
- /* wait at least 35ns (W12) before reading */
- udelay(1);
-
- /* Intel example code uses offset of 4 for 8-bit flash */
- lock_conf_addr = (FPWV *) info->start[sector] + 4;
- ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
-
- /* put flash back in read mode */
- *addr = (FPW) INTEL_RESET;
-
- return ret;
-}
-
-
-/*
- * Checks if "bank1" and "bank2" are on the same chip. Returns 1 if they
- * are and 0 otherwise.
- */
-static unsigned char same_chip_banks (int bank1, int bank2)
-{
- unsigned char same_chip[CONFIG_SYS_MAX_FLASH_BANKS][CONFIG_SYS_MAX_FLASH_BANKS] = {
- {1, 1, 0, 0},
- {1, 1, 0, 0},
- {0, 0, 1, 1},
- {0, 0, 1, 1}
- };
- return same_chip[bank1][bank2];
-}
-
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong type, start;
- int rcode = 0, intel = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN)
- printf ("- missing\n");
- else
- printf ("- no sectors to erase\n");
- return 1;
- }
-
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_INTEL)) {
- type = (info->flash_id & FLASH_VENDMASK);
- if ((type != FLASH_MAN_AMD)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
- }
-
- if (type == FLASH_MAN_INTEL)
- intel = 1;
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- FPWV *addr = (FPWV *) (info->start[sect]);
- FPW status;
-
- printf ("Erasing sector %2d ... ", sect);
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer (0);
-
- if (intel) {
- *addr = (FPW) 0x00500050; /* clear status register */
- *addr = (FPW) 0x00200020; /* erase setup */
- *addr = (FPW) 0x00D000D0; /* erase confirm */
- } else {
- FPWV *base; /* first address in bank */
-
- base = (FPWV *) (CONFIG_SYS_AMD_BASE);
- base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */
- base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
- *addr = (FPW) 0x00300030; /* erase sector */
- }
-
- while (((status =
- *addr) & (FPW) 0x00800080) !=
- (FPW) 0x00800080) {
- if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- if (intel) {
- *addr = (FPW) 0x00B000B0; /* suspend erase */
- *addr = (FPW) 0x00FF00FF; /* reset to read mode */
- } else
- *addr = (FPW) 0x00F000F0; /* reset to read mode */
-
- rcode = 1;
- break;
- }
- }
-
- if (intel) {
- *addr = (FPW) 0x00500050; /* clear status register cmd. */
- *addr = (FPW) 0x00FF00FF; /* resest to read mode */
- } else
- *addr = (FPW) 0x00F000F0; /* reset to read mode */
-
- printf (" done\n");
- }
- }
- if (flag)
- enable_interrupts();
-
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- if (info->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- {
- FPW data = 0; /* 16 or 32 bit word, matches flash bus width */
- int bytes; /* number of bytes to program in current word */
- int left; /* number of bytes left to program */
- int i, res;
-
- for (left = cnt, res = 0;
- left > 0 && res == 0;
- addr += sizeof (data), left -=
- sizeof (data) - bytes) {
-
- bytes = addr & (sizeof (data) - 1);
- addr &= ~(sizeof (data) - 1);
-
- /* combine source and destination data so can program
- * an entire word of 16 or 32 bits
- */
- for (i = 0; i < sizeof (data); i++) {
- data <<= 8;
- if (i < bytes || i - bytes >= left)
- data += *((uchar *) addr + i);
- else
- data += *src++;
- }
-
- res = write_word_amd (info, (FPWV *) addr,
- data);
- }
- return res;
- } /* case FLASH_MAN_AMD */
-
- case FLASH_MAN_INTEL:
- {
- ulong cp, wp;
- FPW data;
- int count, i, l, rc, port_width;
-
- /* get lower word aligned address */
- wp = addr;
- port_width = 1;
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- for (; i < port_width && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
-
- for (; cnt == 0 && i < port_width; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- if ((rc =
- write_data (info, wp, SWAP (data))) != 0)
- return (rc);
- wp += port_width;
- }
-
- if (cnt > WR_BLOCK) {
- /*
- * handle word aligned part
- */
- count = 0;
- while (cnt >= WR_BLOCK) {
-
- if ((rc =
- write_data_block (info,
- (ulong) src,
- wp)) != 0)
- return (rc);
-
- wp += WR_BLOCK;
- src += WR_BLOCK;
- cnt -= WR_BLOCK;
-
- if (count++ > 0x800) {
- spin_wheel ();
- count = 0;
- }
- }
- }
-
- if (cnt < WR_BLOCK) {
- /*
- * handle word aligned part
- */
- count = 0;
- while (cnt >= port_width) {
- data = 0;
- for (i = 0; i < port_width; ++i)
- data = (data << 8) | *src++;
-
- if ((rc =
- write_data (info, wp,
- SWAP (data))) != 0)
- return (rc);
-
- wp += port_width;
- cnt -= port_width;
- if (count++ > 0x800) {
- spin_wheel ();
- count = 0;
- }
- }
- }
-
- if (cnt == 0)
- return (0);
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < port_width && cnt > 0;
- ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
-
- for (; i < port_width; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- return (write_data (info, wp, SWAP (data)));
- } /* case FLASH_MAN_INTEL */
-
- } /* switch */
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
- FPWV *addr = (FPWV *) dest;
- ulong start;
- int flag, rc = 0;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- printf ("not erased at %08lx (%lx)\n", (ulong)addr, (ulong)*addr);
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- *addr = (FPW) 0x00400040; /* write setup */
- *addr = data;
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer (0);
-
- /* wait while polling the status register */
- while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- rc = 1;
- goto OUT;
- }
- }
-
-OUT:
- *addr = (FPW)0x00FF00FF; /* restore read mode */
-
- if (flag)
- enable_interrupts();
-
- return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data_block (flash_info_t * info, ulong src, ulong dest)
-{
- FPWV *srcaddr = (FPWV *) src;
- FPWV *dstaddr = (FPWV *) dest;
- ulong start;
- int flag, i, rc = 0;
-
- /* Check if Flash is (sufficiently) erased */
- for (i = 0; i < WR_BLOCK; i++)
- if ((*dstaddr++ & 0xff) != 0xff) {
- printf ("not erased at %08lx (%lx)\n",
- (ulong)dstaddr, (ulong)*dstaddr);
- return (2);
- }
-
- dstaddr = (FPWV *) dest;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- *dstaddr = (FPW) 0x00e800e8; /* write block setup */
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer (0);
-
- /* wait while polling the status register */
- while ((*dstaddr & (FPW)0x00800080) != (FPW)0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- rc = 1;
- goto OUT;
- }
- }
-
- *dstaddr = (FPW) 0x001f001f; /* write 32 to buffer */
- for (i = 0; i < WR_BLOCK; i++)
- *dstaddr++ = *srcaddr++;
-
- dstaddr -= 1;
- *dstaddr = (FPW) 0x00d000d0; /* write 32 to buffer */
-
- /* arm simple, non interrupt dependent timer */
- start = get_timer (0);
-
- /* wait while polling the status register */
- while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */
- return (1);
- }
- }
-
-OUT:
- *dstaddr = (FPW)0x00FF00FF; /* restore read mode */
- if (flag)
- enable_interrupts();
-
- return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data)
-{
- ulong start;
- int flag;
- int res = 0; /* result, assume success */
- FPWV *base; /* first address in flash bank */
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest & data) != data) {
- return (2);
- }
-
- base = (FPWV *) (CONFIG_SYS_AMD_BASE);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (FPW) 0x00A000A0; /* selects program mode */
-
- *dest = data; /* start programming the data */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- start = get_timer (0);
-
- /* data polling for D7 */
- while (res == 0
- && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *dest = (FPW) 0x00F000F0; /* reset bank */
- res = 1;
- }
- }
-
- return (res);
-}
-
-void inline spin_wheel (void)
-{
- static int p = 0;
- static char w[] = "\\/-";
-
- printf ("\010%c", w[p]);
- (++p == 3) ? (p = 0) : 0;
-}
-
-/*-----------------------------------------------------------------------
- * Set/Clear sector's lock bit, returns:
- * 0 - OK
- * 1 - Error (timeout, voltage problems, etc.)
- */
-int flash_real_protect (flash_info_t * info, long sector, int prot)
-{
- ulong start;
- int i, j;
- int curr_bank;
- int bank;
- int rc = 0;
- FPWV *addr = (FPWV *) (info->start[sector]);
- int flag = disable_interrupts ();
-
- /*
- * 29F040B AMD flash does not support software protection/unprotection,
- * the only way to protect the AMD flash is marked it as prot bit.
- * This flash only support hardware protection, by supply or not supply
- * 12vpp to the flash
- */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
- info->protect[sector] = prot;
-
- return 0;
- }
-
- *addr = INTEL_CLEAR; /* Clear status register */
- if (prot) { /* Set sector lock bit */
- *addr = INTEL_LOCKBIT; /* Sector lock bit */
- *addr = INTEL_PROTECT; /* set */
- } else { /* Clear sector lock bit */
- *addr = INTEL_LOCKBIT; /* All sectors lock bits */
- *addr = INTEL_CONFIRM; /* clear */
- }
-
- start = get_timer (0);
-
- while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if (get_timer (start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
- printf ("Flash lock bit operation timed out\n");
- rc = 1;
- break;
- }
- }
-
- if (*addr != INTEL_OK) {
- printf ("Flash lock bit operation failed at %08X, CSR=%08X\n",
- (uint) addr, (uint) * addr);
- rc = 1;
- }
-
- if (!rc)
- info->protect[sector] = prot;
-
- /*
- * Clear lock bit command clears all sectors lock bits, so
- * we have to restore lock bits of protected sectors.
- */
- if (!prot) {
- /*
- * re-locking must be done for all banks that belong on one
- * FLASH chip, as all the sectors on the chip were unlocked
- * by INTEL_LOCKBIT/INTEL_CONFIRM commands. (let's hope
- * that banks never span chips, in particular chips which
- * support h/w protection differently).
- */
-
- /* find the current bank number */
- curr_bank = CONFIG_SYS_MAX_FLASH_BANKS + 1;
- for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; ++j) {
- if (&flash_info[j] == info) {
- curr_bank = j;
- }
- }
- if (curr_bank == CONFIG_SYS_MAX_FLASH_BANKS + 1) {
- printf("Error: can't determine bank number!\n");
- }
-
- for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
- if (!same_chip_banks(curr_bank, bank)) {
- continue;
- }
- info = &flash_info[bank];
- for (i = 0; i < info->sector_count; i++) {
- if (info->protect[i]) {
- start = get_timer (0);
- addr = (FPWV *) (info->start[i]);
- *addr = INTEL_LOCKBIT; /* Sector lock bit */
- *addr = INTEL_PROTECT; /* set */
- while ((*addr & INTEL_FINISHED) !=
- INTEL_FINISHED) {
- if (get_timer (start) >
- CONFIG_SYS_FLASH_UNLOCK_TOUT) {
- printf ("Flash lock bit operation timed out\n");
- rc = 1;
- break;
- }
- }
- }
- }
- }
-
- /*
- * get the s/w sector protection status in sync with the h/w,
- * in case something went wrong during the re-locking.
- */
- flash_sync_real_protect(info); /* resets flash to read mode */
- }
-
- if (flag)
- enable_interrupts ();
-
- *addr = INTEL_RESET; /* Reset to read array mode */
-
- return rc;
-}
diff --git a/board/bf609-ezkit/soft_switch.c b/board/bf609-ezkit/soft_switch.c
new file mode 100644
index 0000000..e0c8d93
--- /dev/null
+++ b/board/bf609-ezkit/soft_switch.c
@@ -0,0 +1,171 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "soft_switch.h"
+
+struct switch_config {
+ uchar dir0; /* IODIRA */
+ uchar dir1; /* IODIRB */
+ uchar value0; /* OLATA */
+ uchar value1; /* OLATB */
+};
+
+static struct switch_config switch_config_array[NUM_SWITCH] = {
+ {
+/*
+ U45 Port A U45 Port B
+
+ 7--------------- RMII_CLK_EN | 7--------------- ~TEMP_THERM_EN
+ | 6------------- ~CNT0ZM_EN | | 6------------- ~TEMP_IRQ_EN
+ | | 5----------- ~CNT0DG_EN | | | 5----------- ~UART0CTS_146_EN
+ | | | 4--------- ~CNT0UD_EN | | | | 4--------- ~UART0CTS_RST_EN
+ | | | | 3------- ~CAN0RX_EN | | | | | 3------- ~UART0CTS_RTS_LPBK
+ | | | | | 2----- ~CAN0_ERR_EN | | | | | | 2----- ~UART0CTS_EN
+ | | | | | | 1--- ~CAN_STB | | | | | | | 1--- ~UART0RX_EN
+ | | | | | | | 0- CAN_EN | | | | | | | | 0- ~UART0RTS_EN
+ | | | | | | | | | | | | | | | | |
+ O O O O O O O O | O O O O O O O O (I/O direction)
+ 1 0 0 0 0 0 1 1 | 1 1 1 1 1 0 0 0 (value being set)
+*/
+ .dir0 = 0x0, /* all output */
+ .dir1 = 0x0, /* all output */
+ .value0 = RMII_CLK_EN | CAN_STB | CAN_EN,
+ .value1 = TEMP_THERM_EN | TEMP_IRQ_EN | UART0CTS_146_EN
+ | UART0CTS_RST_EN | UART0CTS_RTS_LPBK,
+ },
+ {
+/*
+ U46 Port A U46 Port B
+
+ 7--------------- ~LED4_GPIO_EN | 7--------------- EMPTY
+ | 6------------- ~LED3_GPIO_EN | | 6------------- ~SPI0D3_EN
+ | | 5----------- ~LED2_GPIO_EN | | | 5----------- ~SPI0D2_EN
+ | | | 4--------- ~LED1_GPIO_EN | | | | 4--------- ~SPIFLASH_CS_EN
+ | | | | 3------- SMC0_LP0_EN | | | | | 3------- ~SD_WP_EN
+ | | | | | 2----- EMPTY | | | | | | 2----- ~SD_CD_EN
+ | | | | | | 1--- SMC0_EPPI2 | | | | | | | 1--- ~PUSHBUTTON2_EN
+ _LP1_SWITCH
+ | | | | | | | 0- OVERRIDE_SMC0 | | | | | | | | 0- ~PUSHBUTTON1_EN
+ _LP0_BOOT
+ | | | | | | | | | | | | | | | | |
+ O O O O O O O O | O O O O O O O O (I/O direction)
+ 0 0 0 0 0 X 0 1 | X 0 0 0 0 0 0 0 (value being set)
+*/
+ .dir0 = 0x0, /* all output */
+ .dir1 = 0x0, /* all output */
+#ifdef CONFIG_BFIN_LINKPORT
+ .value0 = OVERRIDE_SMC0_LP0_BOOT,
+#else
+ .value0 = SMC0_EPPI2_LP1_SWITCH,
+#endif
+ .value1 = 0x0,
+ },
+ {
+/*
+ U47 Port A U47 Port B
+
+ 7--------------- ~PD2_SPI0MISO | 7--------------- EMPTY
+ _EI3_EN
+ | 6------------- ~PD1_SPI0D3 | | 6------------- EMPTY
+ _EPPI1D17
+ _SPI0SEL2
+ _EI3_EN
+ | | 5----------- ~PD0_SPI0D2 | | | 5----------- EMPTY
+ _EPPI1D16
+ _SPI0SEL3
+ _EI3_EN
+ | | | 4--------- ~WAKE_PUSH | | | | 4--------- EMPTY
+ BUTTON_EN
+ | | | | 3------- ~ETHERNET_EN | | | | | 3------- EMPTY
+ | | | | | 2----- PHYAD0 | | | | | | 2----- EMPTY
+ | | | | | | 1--- PHY_PWR | | | | | | | 1--- ~PD4_SPI0CK_EI3_EN
+ _DWN_INT
+ | | | | | | | 0- ~PHYINT_EN | | | | | | | | 0- ~PD3_SPI0MOSI_EI3_EN
+ | | | | | | | | | | | | | | | | |
+ O O O O O I I O | O O O O O O O O (I/O direction)
+ 1 1 1 0 0 0 0 0 | X X X X X X 1 1 (value being set)
+*/
+ .dir0 = 0x6, /* bits 1 and 2 input, all others output */
+ .dir1 = 0x0, /* all output */
+ .value0 = PD1_SPI0D3_EN | PD0_SPI0D2_EN,
+ .value1 = 0,
+ },
+};
+
+static int setup_soft_switch(int addr, struct switch_config *config)
+{
+ int ret = 0;
+
+ ret = i2c_write(addr, OLATA, 1, &config->value0, 1);
+ if (ret)
+ return ret;
+ ret = i2c_write(addr, OLATB, 1, &config->value1, 1);
+ if (ret)
+ return ret;
+
+ ret = i2c_write(addr, IODIRA, 1, &config->dir0, 1);
+ if (ret)
+ return ret;
+ return i2c_write(addr, IODIRB, 1, &config->dir1, 1);
+}
+
+int config_switch_bit(int addr, int port, int bit, int dir, uchar value)
+{
+ int ret, data_reg, dir_reg;
+ uchar tmp;
+
+ if (port == IO_PORT_A) {
+ data_reg = OLATA;
+ dir_reg = IODIRA;
+ } else {
+ data_reg = OLATB;
+ dir_reg = IODIRB;
+ }
+
+ if (dir == IO_PORT_INPUT) {
+ ret = i2c_read(addr, dir_reg, 1, &tmp, 1);
+ if (ret)
+ return ret;
+ tmp |= bit;
+ return i2c_write(addr, dir_reg, 1, &tmp, 1);
+ } else {
+ ret = i2c_read(addr, data_reg, 1, &tmp, 1);
+ if (ret)
+ return ret;
+ if (value)
+ tmp |= bit;
+ else
+ tmp &= ~bit;
+ ret = i2c_write(addr, data_reg, 1, &tmp, 1);
+ if (ret)
+ return ret;
+ ret = i2c_read(addr, dir_reg, 1, &tmp, 1);
+ if (ret)
+ return ret;
+ tmp &= ~bit;
+ return i2c_write(addr, dir_reg, 1, &tmp, 1);
+ }
+}
+
+int setup_board_switches(void)
+{
+ int ret;
+ int i;
+
+ for (i = 0; i < NUM_SWITCH; i++) {
+ ret = setup_soft_switch(SWITCH_ADDR + i,
+ &switch_config_array[i]);
+ if (ret)
+ return ret;
+ }
+ return 0;
+}
diff --git a/board/bf609-ezkit/soft_switch.h b/board/bf609-ezkit/soft_switch.h
new file mode 100644
index 0000000..d147fe1
--- /dev/null
+++ b/board/bf609-ezkit/soft_switch.h
@@ -0,0 +1,80 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BOARD_SOFT_SWITCH_H__
+#define __BOARD_SOFT_SWITCH_H__
+
+#include <asm/soft_switch.h>
+
+/* switch 0 port A */
+#define CAN_EN 0x1
+#define CAN_STB 0x2
+#define CAN0_ERR_EN 0x4
+#define CAN0RX_EN 0x8
+#define CNT0UD_EN 0x10
+#define CNT0DG_EN 0x20
+#define CNT0ZM_EN 0x40
+#define RMII_CLK_EN 0x80
+
+/* switch 0 port B */
+#define UART0RTS_EN 0x1
+#define UART0RX_EN 0x2
+#define UART0CTS_EN 0x4
+#define UART0CTS_RTS_LPBK 0x8
+#define UART0CTS_RST_EN 0x10
+#define UART0CTS_146_EN 0x20
+#define TEMP_IRQ_EN 0x40
+#define TEMP_THERM_EN 0x80
+
+/* switch 1 port A */
+#define OVERRIDE_SMC0_LP0_BOOT 0x1
+#define SMC0_EPPI2_LP1_SWITCH 0x2
+#define SMC0_LP0_EN 0x8
+#define LED1_GPIO_EN 0x10
+#define LED2_GPIO_EN 0x20
+#define LED3_GPIO_EN 0x40
+#define LED4_GPIO_EN 0x80
+
+/* switch 1 port B */
+#define PUSHBUTTON1_EN 0x1
+#define PUSHBUTTON2_EN 0x2
+#define SD_CD_EN 0x4
+#define SD_WP_EN 0x8
+#define SPIFLASH_CS_EN 0x10
+#define SPI0D2_EN 0x20
+#define SPI0D3_EN 0x40
+
+/* switch 2 port A */
+#define PHYINT_EN 0x1
+#define PHY_PWR_DWN_INT 0x2
+#define PHYAD0 0x4
+#define ETHERNET_EN 0x8
+#define WAKE_PUSHBUTTON_EN 0x10
+#define PD0_SPI0D2_EN 0x20
+#define PD1_SPI0D3_EN 0x40
+#define PD2_SPI0MISO_EN 0x80
+
+/* switch 2 port B */
+#define PD3_SPI0MOSI_EN 0x1
+#define PD4_SPI0CK_EN 0x2
+
+#ifdef CONFIG_BFIN_BOARD_VERSION_1_0
+#define SWITCH_ADDR 0x21
+#else
+#define SWITCH_ADDR 0x20
+#endif
+
+#define NUM_SWITCH 3
+#define IODIRA 0x0
+#define IODIRB 0x1
+#define OLATA 0x14
+#define OLATB 0x15
+
+int setup_board_switches(void);
+
+#endif /* __BOARD_SOFT_SWITCH_H__ */
diff --git a/board/boundary/nitrogen6x/nitrogen6dl.cfg b/board/boundary/nitrogen6x/nitrogen6dl.cfg
index d6da96c..6625790 100644
--- a/board/boundary/nitrogen6x/nitrogen6dl.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6dl.cfg
@@ -19,7 +19,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
index 0b1c35c..dccd497 100644
--- a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
@@ -19,7 +19,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/boundary/nitrogen6x/nitrogen6q.cfg b/board/boundary/nitrogen6x/nitrogen6q.cfg
index 680a853..e317374 100644
--- a/board/boundary/nitrogen6x/nitrogen6q.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6q.cfg
@@ -19,7 +19,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
index f57ab0e..5a06220 100644
--- a/board/boundary/nitrogen6x/nitrogen6q2g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
@@ -19,7 +19,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/boundary/nitrogen6x/nitrogen6s.cfg b/board/boundary/nitrogen6x/nitrogen6s.cfg
index b5af5cc..d7d5f29 100644
--- a/board/boundary/nitrogen6x/nitrogen6s.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6s.cfg
@@ -19,7 +19,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
index 5aeefc8..cf2690a 100644
--- a/board/boundary/nitrogen6x/nitrogen6s1g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
@@ -19,7 +19,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/buffalo/lsxl/kwbimage-lschl.cfg b/board/buffalo/lsxl/kwbimage-lschl.cfg
index 2b9b3cd..4ac381e 100644
--- a/board/buffalo/lsxl/kwbimage-lschl.cfg
+++ b/board/buffalo/lsxl/kwbimage-lschl.cfg
@@ -20,7 +20,7 @@
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/buffalo/lsxl/kwbimage-lsxhl.cfg b/board/buffalo/lsxl/kwbimage-lsxhl.cfg
index 8a94b6c..c62f22c 100644
--- a/board/buffalo/lsxl/kwbimage-lsxhl.cfg
+++ b/board/buffalo/lsxl/kwbimage-lsxhl.cfg
@@ -20,7 +20,7 @@
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/cloudengines/pogo_e02/kwbimage.cfg b/board/cloudengines/pogo_e02/kwbimage.cfg
index a02e88d..32c0cd5 100644
--- a/board/cloudengines/pogo_e02/kwbimage.cfg
+++ b/board/cloudengines/pogo_e02/kwbimage.cfg
@@ -23,7 +23,7 @@
# You should have received a copy of the GNU General Public License
# along with this program; If not, see <http://www.gnu.org/licenses/>.
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/d-link/dns325/kwbimage.cfg b/board/d-link/dns325/kwbimage.cfg
index 97cb090..6df7939 100644
--- a/board/d-link/dns325/kwbimage.cfg
+++ b/board/d-link/dns325/kwbimage.cfg
@@ -25,7 +25,7 @@
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/esg/ima3-mx53/imximage.cfg b/board/esg/ima3-mx53/imximage.cfg
index fce7492..ab22385 100644
--- a/board/esg/ima3-mx53/imximage.cfg
+++ b/board/esg/ima3-mx53/imximage.cfg
@@ -20,7 +20,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index 41887c2..a39c17a 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -166,11 +166,13 @@ int configure_vsc3316_3308(void)
ret = select_i2c_ch_pca(I2C_CH_VSC3316);
if (!ret) {
ret = vsc3316_config(VSC3316_TX_ADDRESS,
- vsc16_tx_sgmii_lane_ab, num_vsc16_con);
+ vsc16_tx_4sfp_sgmii_12_56,
+ num_vsc16_con);
if (ret)
return ret;
ret = vsc3316_config(VSC3316_RX_ADDRESS,
- vsc16_rx_sgmii_lane_ab, num_vsc16_con);
+ vsc16_rx_4sfp_sgmii_12_56,
+ num_vsc16_con);
if (ret)
return ret;
} else {
diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h
index 994dec5..c2b6c44 100644
--- a/board/freescale/b4860qds/b4860qds_crossbar_con.h
+++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h
@@ -26,42 +26,53 @@
static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
{5, 11}, {4, 5}, {2, 6}, {12, 9} };
-static const int8_t vsc16_tx_sfp[8][2] = { {15, 8}, {0, 0}, {7, 7}, {9, 1},
- {5, 15}, {4, 14}, {2, 12}, {12, 13} };
+static const int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-static const int8_t vsc16_tx_sgmii_lane_ab[8][2] = { {2, 14}, {12, 15},
- {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+static const int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
+ {7, 8}, {9, 0}, {2, 14}, {12, 15},
+ {-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
+ {7, 8}, {9, 0}, {5, 14}, {4, 15},
+ {-1, -1}, {-1, -1} };
#ifdef CONFIG_PPC_B4420
static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
#endif
+
static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
{11, 11}, {5, 10}, {6, 3}, {9, 12} };
-static const int8_t vsc16_rx_sfp[8][2] = { {0, 15}, {8, 1}, {1, 8}, {7, 9},
+static const int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
-static const int8_t vsc16_rx_sgmii_lane_ab[8][2] = { {14, 3}, {15, 12},
- {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+static const int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
+ {7, 8}, {1, 9}, {14, 3}, {15, 12},
+ {-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
+ {7, 8}, {1, 9}, {14, 11}, {15, 10},
+ {-1, -1}, {-1, -1} };
#ifdef CONFIG_PPC_B4420
static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
#endif
-static const int8_t vsc16_rx_aurora[8][2] = { {12, 3}, {13, 12}, {-1, -1},
+static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };
-static const int8_t vsc08_tx_sfp[4][2] = { {2, 6}, {3, 7}, {7, 1}, {1, 0} };
+static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} };
static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };
-static const int8_t vsc08_rx_sfp[4][2] = { {6, 3}, {7, 4}, {1, 7}, {0, 1} };
+static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} };
#endif
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index dd4c0f6..b82b3d4 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -13,6 +13,7 @@
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
+#include <../arch/powerpc/cpu/mpc8xxx/ddr/ddr.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -188,3 +189,74 @@ phys_size_t initdram(int board_type)
puts(" DDR: ");
return dram_size;
}
+
+unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
+ unsigned int dbw_cap_adj[])
+{
+ int i, j;
+ unsigned long long total_mem, current_mem_base, total_ctlr_mem;
+ unsigned long long rank_density, ctlr_density = 0;
+
+ current_mem_base = 0ull;
+ total_mem = 0;
+ /*
+ * This board has soldered DDR chips. DDRC1 has two rank.
+ * DDRC2 has only one rank.
+ * Assigning DDRC2 to lower address and DDRC1 to higher address.
+ */
+ if (pinfo->memctl_opts[0].memctl_interleaving) {
+ rank_density = pinfo->dimm_params[0][0].rank_density >>
+ dbw_cap_adj[0];
+ ctlr_density = rank_density;
+
+ debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
+ rank_density, ctlr_density);
+ for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
+ switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
+ case FSL_DDR_CACHE_LINE_INTERLEAVING:
+ case FSL_DDR_PAGE_INTERLEAVING:
+ case FSL_DDR_BANK_INTERLEAVING:
+ case FSL_DDR_SUPERBANK_INTERLEAVING:
+ total_ctlr_mem = 2 * ctlr_density;
+ break;
+ default:
+ panic("Unknown interleaving mode");
+ }
+ pinfo->common_timing_params[i].base_address =
+ current_mem_base;
+ pinfo->common_timing_params[i].total_mem =
+ total_ctlr_mem;
+ total_mem = current_mem_base + total_ctlr_mem;
+ debug("ctrl %d base 0x%llx\n", i, current_mem_base);
+ debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
+ }
+ } else {
+ /*
+ * Simple linear assignment if memory
+ * controllers are not interleaved.
+ */
+ for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
+ total_ctlr_mem = 0;
+ pinfo->common_timing_params[i].base_address =
+ current_mem_base;
+ for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+ /* Compute DIMM base addresses. */
+ unsigned long long cap =
+ pinfo->dimm_params[i][j].capacity;
+ pinfo->dimm_params[i][j].base_address =
+ current_mem_base;
+ debug("ctrl %d dimm %d base 0x%llx\n",
+ i, j, current_mem_base);
+ current_mem_base += cap;
+ total_ctlr_mem += cap;
+ }
+ debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
+ pinfo->common_timing_params[i].total_mem =
+ total_ctlr_mem;
+ total_mem += total_ctlr_mem;
+ }
+ }
+ debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
+
+ return total_mem;
+}
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index 68e2725..3bcda6d 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -275,6 +275,24 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
break;
+ case 0x98:
+ /* XAUI in Slot1 and Slot2 */
+ debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC1: %x\n",
+ CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC1,
+ CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+ debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
+ CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC2,
+ CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
+ break;
+ case 0x9E:
+ /* XAUI in Slot2 */
+ debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
+ CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC2,
+ CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
+ break;
default:
printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
serdes2_prtcl);
@@ -300,6 +318,23 @@ int board_eth_init(bd_t *bis)
}
}
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ int idx = i - FM1_10GEC1;
+
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ fm_info_set_mdio(i,
+ miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
+ break;
+ default:
+ printf("Fman1: 10GSEC%u set to unknown interface %i\n",
+ idx + 1, fm_info_get_enet_if(i));
+ fm_info_set_phy_address(i, 0);
+ break;
+ }
+ }
+
+
cpu_eth_init(bis);
#endif
diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c
index 4142e01..b26725b 100644
--- a/board/freescale/b4860qds/law.c
+++ b/board/freescale/b4860qds/law.c
@@ -33,8 +33,12 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_MAPLE_MEM_PHYS
+ SET_LAW(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_MAPLE),
+#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
index 6d634bf..29cc41b 100644
--- a/board/freescale/b4860qds/tlb.c
+++ b/board/freescale/b4860qds/tlb.c
@@ -106,7 +106,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_4M, 1),
+ 0, 10, BOOKE_PAGESZ_32M, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE
/*
diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h
index 8d914d5..2cf8738 100644
--- a/board/freescale/common/qixis.h
+++ b/board/freescale/common/qixis.h
@@ -78,7 +78,11 @@ struct qixis {
u8 trig_stat;
u8 res12[3];
u8 trig_ctr[4];
- u8 res13[48];
+ u8 res13[16];
+ u8 clk_freq[6]; /* Clock Measurement Registers */
+ u8 res_c6[8];
+ u8 clk_base[2]; /* Clock Frequency Base Reg */
+ u8 res_d0[16];
u8 aux2[4]; /* Auxiliary Registers,0xE0 */
u8 res14[10];
u8 aux_ad;
diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c
index ef9de25..ae07073 100644
--- a/board/freescale/corenet_ds/eth_superhydra.c
+++ b/board/freescale/corenet_ds/eth_superhydra.c
@@ -605,8 +605,8 @@ int board_eth_init(bd_t *bis)
lane = serdes_get_first_lane(XAUI_FM1);
if (lane >= 0) {
debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
- mdio_mux[FM1_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK;
- mdio_mux[FM1_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT2;
+ mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
+ mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2;
super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
}
@@ -704,8 +704,8 @@ int board_eth_init(bd_t *bis)
lane = serdes_get_first_lane(XAUI_FM2);
if (lane >= 0) {
debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
- mdio_mux[FM2_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK;
- mdio_mux[FM2_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT1;
+ mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK;
+ mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1;
super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
}
diff --git a/board/freescale/corenet_ds/pbi.cfg b/board/freescale/corenet_ds/pbi.cfg
index 50806ca..af1ebd6 100644
--- a/board/freescale/corenet_ds/pbi.cfg
+++ b/board/freescale/corenet_ds/pbi.cfg
@@ -19,7 +19,7 @@
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
-# Refer docs/README.pblimage for more details about how-to configure
+# Refer doc/README.pblimage for more details about how-to configure
# and create PBL boot image
#
diff --git a/board/freescale/corenet_ds/rcw_p5040ds.cfg b/board/freescale/corenet_ds/rcw_p5040ds.cfg
new file mode 100644
index 0000000..82fa741
--- /dev/null
+++ b/board/freescale/corenet_ds/rcw_p5040ds.cfg
@@ -0,0 +1,11 @@
+#
+# Default RCW for P5040DS.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+0c580000 00000000 22121200 00000000
+089c4400 00283000 58000000 61000000
+00000000 00000000 00000000 10070000
+00000000 00000000 00000000 00000000
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index 996d788..bae5c23 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -20,7 +20,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx25pdk/imximage.cfg b/board/freescale/mx25pdk/imximage.cfg
index c42a283..8cc8bde 100644
--- a/board/freescale/mx25pdk/imximage.cfg
+++ b/board/freescale/mx25pdk/imximage.cfg
@@ -15,7 +15,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx51evk/imximage.cfg b/board/freescale/mx51evk/imximage.cfg
index 3e141ee..aaa490a 100644
--- a/board/freescale/mx51evk/imximage.cfg
+++ b/board/freescale/mx51evk/imximage.cfg
@@ -20,7 +20,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx53ard/imximage_dd3.cfg b/board/freescale/mx53ard/imximage_dd3.cfg
index 4633e4d..a103d95 100644
--- a/board/freescale/mx53ard/imximage_dd3.cfg
+++ b/board/freescale/mx53ard/imximage_dd3.cfg
@@ -20,7 +20,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx53evk/imximage.cfg b/board/freescale/mx53evk/imximage.cfg
index 1cd61d5..c1cfdda 100644
--- a/board/freescale/mx53evk/imximage.cfg
+++ b/board/freescale/mx53evk/imximage.cfg
@@ -20,7 +20,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg
index e6b90c1..2f75ad0 100644
--- a/board/freescale/mx53loco/imximage.cfg
+++ b/board/freescale/mx53loco/imximage.cfg
@@ -20,7 +20,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx53smd/imximage.cfg b/board/freescale/mx53smd/imximage.cfg
index 4633e4d..a103d95 100644
--- a/board/freescale/mx53smd/imximage.cfg
+++ b/board/freescale/mx53smd/imximage.cfg
@@ -20,7 +20,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg
index 4ed211e..6f18b37 100644
--- a/board/freescale/mx6qarm2/imximage.cfg
+++ b/board/freescale/mx6qarm2/imximage.cfg
@@ -20,7 +20,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx6qsabreauto/imximage.cfg b/board/freescale/mx6qsabreauto/imximage.cfg
index bbff813..e720c6b 100644
--- a/board/freescale/mx6qsabreauto/imximage.cfg
+++ b/board/freescale/mx6qsabreauto/imximage.cfg
@@ -19,7 +19,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index a706a6d..44d3e0c 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -227,6 +227,17 @@ int misc_init_r(void)
"'00' is unsupported\n");
else
actual[i] = freq[i][clock];
+
+ /*
+ * PC board uses a different CPLD with PB board, this CPLD
+ * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
+ * board has cpld_ver_sub = 0, and pcba_ver = 4.
+ */
+ if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
+ (CPLD_READ(pcba_ver) == 5)) {
+ /* PC board bank2 frequency */
+ actual[i] = freq[i-1][clock];
+ }
}
for (i = 0; i < NUM_SRDS_BANKS; i++) {
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 692616a..058d625 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -19,6 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
+ u32 rank_gb;
u32 clk_adjust;
u32 wrlvl_start;
u32 wrlvl_ctl_2;
@@ -36,16 +37,19 @@ struct board_specific_parameters {
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
- * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
- {2, 1350, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0},
- {2, 1666, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {2, 2140, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
- {1, 1350, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {1, 1700, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {1, 1900, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
- {1, 2140, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
+ {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
+ {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
+ {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
+ {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
+ {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
+ {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
+ {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
+ {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
{}
};
@@ -61,19 +65,19 @@ static const struct board_specific_parameters *udimms[] = {
static const struct board_specific_parameters rdimm0[] = {
/*
* memory controller 0
- * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
- {4, 1350, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0},
- {4, 1666, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0},
- {4, 2140, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0},
- {2, 1350, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0},
- {2, 1666, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {2, 2140, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
- {1, 1350, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {1, 1700, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {1, 1900, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
- {1, 2140, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
+ {4, 1350, 0, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0},
+ {4, 1666, 0, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0},
+ {4, 2140, 0, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0},
+ {2, 1350, 0, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0},
+ {2, 1666, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
+ {2, 2140, 0, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
+ {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
+ {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
+ {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
{}
};
@@ -113,7 +117,8 @@ void fsl_ddr_board_options(memctl_options_t *popts,
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->cpo_override = pbsp->cpo;
popts->write_data_delay =
@@ -146,6 +151,13 @@ void fsl_ddr_board_options(memctl_options_t *popts,
panic("DIMM is not supported by this board");
}
found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+ "wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index a49c7d4..7103a0d 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -52,7 +52,7 @@
#define EMI1_SLOT4 4
#define EMI1_SLOT5 5
#define EMI1_SLOT7 7
-#define EMI2 8 /* tmp, FIXME */
+#define EMI2 8
/* Slot6 and Slot8 do not have EMI connections */
static int mdio_mux[NUM_FM_PORTS];
@@ -71,6 +71,14 @@ static const char *mdio_names[] = {
static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
+static u8 slot_qsgmii_phyaddr[5][4] = {
+ {0, 0, 0, 0},/* not used, to make index match slot No. */
+ {0, 1, 2, 3},
+ {4, 5, 6, 7},
+ {8, 9, 0xa, 0xb},
+ {0xc, 0xd, 0xe, 0xf},
+};
+static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
{
@@ -180,21 +188,228 @@ static int t4240qds_mdio_init(char *realbusname, u8 muxval)
void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
enum fm_port port, int offset)
{
- if (mdio_mux[port] == EMI1_RGMII)
- fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
-
- /* TODO: will do with dts */
+ if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+ switch (port) {
+ case FM1_DTSEC1:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy21");
+ break;
+ case FM1_DTSEC2:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy22");
+ break;
+ case FM1_DTSEC3:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy23");
+ break;
+ case FM1_DTSEC4:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy24");
+ break;
+ case FM1_DTSEC6:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy12");
+ break;
+ case FM1_DTSEC9:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy14");
+ else
+ fdt_set_phy_handle(blob, prop, pa,
+ "phy_sgmii4");
+ break;
+ case FM1_DTSEC10:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy13");
+ else
+ fdt_set_phy_handle(blob, prop, pa,
+ "phy_sgmii3");
+ break;
+ case FM2_DTSEC1:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy41");
+ break;
+ case FM2_DTSEC2:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy42");
+ break;
+ case FM2_DTSEC3:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy43");
+ break;
+ case FM2_DTSEC4:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy44");
+ break;
+ case FM2_DTSEC6:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy32");
+ break;
+ case FM2_DTSEC9:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy34");
+ else
+ fdt_set_phy_handle(blob, prop, pa,
+ "phy_sgmii12");
+ break;
+ case FM2_DTSEC10:
+ if (qsgmiiphy_fix[port])
+ fdt_set_phy_handle(blob, prop, pa,
+ "sgmii_phy33");
+ else
+ fdt_set_phy_handle(blob, prop, pa,
+ "phy_sgmii11");
+ break;
+ default:
+ break;
+ }
+ }
}
void fdt_fixup_board_enet(void *fdt)
{
- /* TODO: will do with dts */
+ int i;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+ prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ switch (mdio_mux[i]) {
+ case EMI1_SLOT1:
+ fdt_status_okay_by_alias(fdt, "emi1_slot1");
+ break;
+ case EMI1_SLOT2:
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ break;
+ case EMI1_SLOT3:
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ break;
+ case EMI1_SLOT4:
+ fdt_status_okay_by_alias(fdt, "emi1_slot4");
+ break;
+ default:
+ break;
+ }
+ break;
+ case PHY_INTERFACE_MODE_XGMII:
+ /* check if it's XFI interface for 10g */
+ if ((prtcl2 == 56) || (prtcl2 == 57)) {
+ fdt_status_okay_by_alias(fdt, "emi2_xfislot3");
+ break;
+ }
+ switch (i) {
+ case FM1_10GEC1:
+ fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
+ break;
+ case FM1_10GEC2:
+ fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
+ break;
+ case FM2_10GEC1:
+ fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
+ break;
+ case FM2_10GEC2:
+ fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+static void initialize_qsgmiiphy_fix(void)
+{
+ int i;
+ unsigned short reg;
+
+ for (i = 1; i <= 4; i++) {
+ /*
+ * Try to read if a SGMII card is used, we do it slot by slot.
+ * if a SGMII PHY address is valid on a slot, then we mark
+ * all ports on the slot, then fix the PHY address for the
+ * marked port when doing dtb fixup.
+ */
+ if (miiphy_read(mdio_names[i],
+ SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, &reg) != 0) {
+ debug("Slot%d PHY ID register 2 read failed\n", i);
+ continue;
+ }
+
+ debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
+
+ if (reg == 0xFFFF) {
+ /* No physical device present at this address */
+ continue;
+ }
+
+ switch (i) {
+ case 1:
+ qsgmiiphy_fix[FM1_DTSEC5] = 1;
+ qsgmiiphy_fix[FM1_DTSEC6] = 1;
+ qsgmiiphy_fix[FM1_DTSEC9] = 1;
+ qsgmiiphy_fix[FM1_DTSEC10] = 1;
+ slot_qsgmii_phyaddr[1][0] = SGMII_CARD_PORT1_PHY_ADDR;
+ slot_qsgmii_phyaddr[1][1] = SGMII_CARD_PORT2_PHY_ADDR;
+ slot_qsgmii_phyaddr[1][2] = SGMII_CARD_PORT3_PHY_ADDR;
+ slot_qsgmii_phyaddr[1][3] = SGMII_CARD_PORT4_PHY_ADDR;
+ break;
+ case 2:
+ qsgmiiphy_fix[FM1_DTSEC1] = 1;
+ qsgmiiphy_fix[FM1_DTSEC2] = 1;
+ qsgmiiphy_fix[FM1_DTSEC3] = 1;
+ qsgmiiphy_fix[FM1_DTSEC4] = 1;
+ slot_qsgmii_phyaddr[2][0] = SGMII_CARD_PORT1_PHY_ADDR;
+ slot_qsgmii_phyaddr[2][1] = SGMII_CARD_PORT2_PHY_ADDR;
+ slot_qsgmii_phyaddr[2][2] = SGMII_CARD_PORT3_PHY_ADDR;
+ slot_qsgmii_phyaddr[2][3] = SGMII_CARD_PORT4_PHY_ADDR;
+ break;
+ case 3:
+ qsgmiiphy_fix[FM2_DTSEC5] = 1;
+ qsgmiiphy_fix[FM2_DTSEC6] = 1;
+ qsgmiiphy_fix[FM2_DTSEC9] = 1;
+ qsgmiiphy_fix[FM2_DTSEC10] = 1;
+ slot_qsgmii_phyaddr[3][0] = SGMII_CARD_PORT1_PHY_ADDR;
+ slot_qsgmii_phyaddr[3][1] = SGMII_CARD_PORT2_PHY_ADDR;
+ slot_qsgmii_phyaddr[3][2] = SGMII_CARD_PORT3_PHY_ADDR;
+ slot_qsgmii_phyaddr[3][3] = SGMII_CARD_PORT4_PHY_ADDR;
+ break;
+ case 4:
+ qsgmiiphy_fix[FM2_DTSEC1] = 1;
+ qsgmiiphy_fix[FM2_DTSEC2] = 1;
+ qsgmiiphy_fix[FM2_DTSEC3] = 1;
+ qsgmiiphy_fix[FM2_DTSEC4] = 1;
+ slot_qsgmii_phyaddr[4][0] = SGMII_CARD_PORT1_PHY_ADDR;
+ slot_qsgmii_phyaddr[4][1] = SGMII_CARD_PORT2_PHY_ADDR;
+ slot_qsgmii_phyaddr[4][2] = SGMII_CARD_PORT3_PHY_ADDR;
+ slot_qsgmii_phyaddr[4][3] = SGMII_CARD_PORT4_PHY_ADDR;
+ break;
+ default:
+ break;
+ }
+ }
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FMAN_ENET)
- int i;
+ int i, idx, lane, slot;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -236,6 +451,7 @@ int board_eth_init(bd_t *bis)
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+ initialize_qsgmiiphy_fix();
switch (srds_prtcl_s1) {
case 1:
@@ -248,44 +464,48 @@ int board_eth_init(bd_t *bis)
case 28:
case 36:
/* SGMII in Slot1 and Slot2 */
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
+ fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
+ fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
+ fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
+ fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
+ fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC9,
- SGMII_CARD_PORT4_PHY_ADDR);
+ slot_qsgmii_phyaddr[1][3]);
fm_info_set_phy_address(FM1_DTSEC10,
- SGMII_CARD_PORT3_PHY_ADDR);
+ slot_qsgmii_phyaddr[1][2]);
}
break;
case 38:
- fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
+ fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
+ fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
+ fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
+ fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
+ fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC9,
- QSGMII_CARD_PHY_ADDR);
+ slot_qsgmii_phyaddr[1][3]);
fm_info_set_phy_address(FM1_DTSEC10,
- QSGMII_CARD_PHY_ADDR);
+ slot_qsgmii_phyaddr[1][2]);
}
break;
case 40:
case 46:
case 48:
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
+ fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC10,
- SGMII_CARD_PORT3_PHY_ADDR);
+ slot_qsgmii_phyaddr[1][3]);
fm_info_set_phy_address(FM1_DTSEC9,
- SGMII_CARD_PORT4_PHY_ADDR);
+ slot_qsgmii_phyaddr[1][2]);
}
- fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
+ fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
+ fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
+ fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
break;
default:
puts("Invalid SerDes1 protocol for T4240QDS\n");
@@ -293,7 +513,7 @@ int board_eth_init(bd_t *bis)
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
- int idx = i - FM1_DTSEC1, lane, slot;
+ idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(FSL_SRDS_1,
@@ -334,8 +554,16 @@ int board_eth_init(bd_t *bis)
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ idx = i - FM1_10GEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ XAUI_FM1_MAC9 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot_fsm1[lane];
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
mdio_mux[i] = EMI2;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
@@ -344,7 +572,6 @@ int board_eth_init(bd_t *bis)
}
}
-
#if (CONFIG_SYS_NUM_FMAN == 2)
switch (srds_prtcl_s2) {
case 1:
@@ -364,68 +591,64 @@ int board_eth_init(bd_t *bis)
case 26:
/* XAUI/HiGig in Slot3, SGMII in Slot4 */
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
case 28:
case 36:
/* SGMII in Slot3 and Slot4 */
- fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
+ fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
+ fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
+ fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
+ fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
break;
case 38:
/* QSGMII in Slot3 and Slot4 */
- fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC5, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC6, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC9, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC10, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
+ fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
+ fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
+ fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
+ fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
break;
case 40:
case 46:
case 48:
/* SGMII in Slot3 */
- fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
+ fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
+ fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
+ fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
/* QSGMII in Slot4 */
- fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
case 50:
case 52:
case 54:
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
case 56:
case 57:
/* XFI in Slot3, SGMII in Slot4 */
- fm_info_set_phy_address(FM1_10GEC1, XFI_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_10GEC2, XFI_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM2_10GEC2, XFI_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM2_10GEC1, XFI_CARD_PORT4_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
default:
puts("Invalid SerDes2 protocol for T4240QDS\n");
@@ -433,7 +656,7 @@ int board_eth_init(bd_t *bis)
}
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
- int idx = i - FM2_DTSEC1, lane, slot;
+ idx = i - FM2_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(FSL_SRDS_2,
@@ -477,8 +700,16 @@ int board_eth_init(bd_t *bis)
}
for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
+ idx = i - FM2_10GEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
+ lane = serdes_get_first_lane(FSL_SRDS_2,
+ XAUI_FM2_MAC9 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot_fsm2[lane];
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
mdio_mux[i] = EMI2;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c
index 6f2c5c8..f3848f3 100644
--- a/board/freescale/t4qds/law.c
+++ b/board/freescale/t4qds/law.c
@@ -37,7 +37,8 @@ struct law_entry law_table[] = {
#endif
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
#ifdef CONFIG_SYS_DCSRBAR_PHYS
- SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
diff --git a/board/freescale/t4qds/t4240qds_qixis.h b/board/freescale/t4qds/t4240qds_qixis.h
index efb718d..485353d 100644
--- a/board/freescale/t4qds/t4240qds_qixis.h
+++ b/board/freescale/t4qds/t4240qds_qixis.h
@@ -42,7 +42,7 @@
#define QIXIS_DDRCLK_125 0x2
#define QIXIS_DDRCLK_133 0x3
-#define BRDCFG5_RESET 0x00
+#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
#define BRDCFG12_SD3EN_MASK 0x20
#define BRDCFG12_SD3MX_MASK 0x08
diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/freescale/t4qds/t4_pbi.cfg
new file mode 100644
index 0000000..c598fb5
--- /dev/null
+++ b/board/freescale/t4qds/t4_pbi.cfg
@@ -0,0 +1,36 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#workaround for IFC bus speed
+091241c0 f03f3f3f
+091241c4 ff003f3f
+09124010 00000101
+09124130 0000000c
+#workaround for SERDES A-006031
+090ea000 064740e6
+090ea020 064740e6
+090eb000 064740e6
+090eb020 064740e6
+090ec000 064740e6
+090ec020 064740e6
+090ed000 064740e6
+090ed020 064740e6
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
new file mode 100644
index 0000000..6ac95ff
--- /dev/null
+++ b/board/freescale/t4qds/t4_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#serdes protocol 1_28_6_12
+14180019 0c101916 00000000 00000000
+04383060 30548c00 6c020000 19000000
+00000000 ee0000ee 00000000 000187fc
+00000000 00000000 00000000 00000018
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index 3c95f3f..f0f280b 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4qds.c
@@ -110,7 +110,7 @@ int checkboard(void)
for (i = 0; i < MAX_SERDES; i++) {
static const char *freq[] = {
"100", "125", "156.25", "161.1328125"};
- unsigned int clock = (sw >> (2 * i)) & 3;
+ unsigned int clock = (sw >> (6 - 2 * i)) & 3;
printf("SERDES%u=%sMHz ", i+1, freq[clock]);
}
@@ -132,6 +132,243 @@ int select_i2c_ch_pca9547(u8 ch)
return 0;
}
+/*
+ * read_voltage from sensor on I2C bus
+ * We use average of 4 readings, waiting for 532us befor another reading
+ */
+#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
+#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
+
+static inline int read_voltage(void)
+{
+ int i, ret, voltage_read = 0;
+ u16 vol_mon;
+
+ for (i = 0; i < NUM_READINGS; i++) {
+ ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+ I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
+ if (ret) {
+ printf("VID: failed to read core voltage\n");
+ return ret;
+ }
+ if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
+ printf("VID: Core voltage sensor error\n");
+ return -1;
+ }
+ debug("VID: bus voltage reads 0x%04x\n", vol_mon);
+ /* LSB = 4mv */
+ voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
+ udelay(WAIT_FOR_ADC);
+ }
+ /* calculate the average */
+ voltage_read /= NUM_READINGS;
+
+ return voltage_read;
+}
+
+/*
+ * We need to calculate how long before the voltage starts to drop or increase
+ * It returns with the loop count. Each loop takes several readings (532us)
+ */
+static inline int wait_for_voltage_change(int vdd_last)
+{
+ int timeout, vdd_current;
+
+ vdd_current = read_voltage();
+ /* wait until voltage starts to drop */
+ for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
+ timeout < 100; timeout++) {
+ vdd_current = read_voltage();
+ }
+ if (timeout >= 100) {
+ printf("VID: Voltage adjustment timeout\n");
+ return -1;
+ }
+ return timeout;
+}
+
+/*
+ * argument 'wait' is the time we know the voltage difference can be measured
+ * this function keeps reading the voltage until it is stable
+ */
+static inline int wait_for_voltage_stable(int wait)
+{
+ int timeout, vdd_current, vdd_last;
+
+ vdd_last = read_voltage();
+ udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
+ /* wait until voltage is stable */
+ vdd_current = read_voltage();
+ for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
+ timeout < 100; timeout++) {
+ vdd_last = vdd_current;
+ udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
+ vdd_current = read_voltage();
+ }
+ if (timeout >= 100) {
+ printf("VID: Voltage adjustment timeout\n");
+ return -1;
+ }
+
+ return vdd_current;
+}
+
+static inline int set_voltage(u8 vid)
+{
+ int wait, vdd_last;
+
+ vdd_last = read_voltage();
+ QIXIS_WRITE(brdcfg[6], vid);
+ wait = wait_for_voltage_change(vdd_last);
+ if (wait < 0)
+ return -1;
+ debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
+ wait = wait ? wait : 1;
+
+ vdd_last = wait_for_voltage_stable(wait);
+ if (vdd_last < 0)
+ return -1;
+ debug("VID: Current voltage is %d mV\n", vdd_last);
+
+ return vdd_last;
+}
+
+
+static int adjust_vdd(ulong vdd_override)
+{
+ int re_enable = disable_interrupts();
+ ccsr_gur_t __iomem *gur =
+ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 fusesr;
+ u8 vid, vid_current;
+ int vdd_target, vdd_current, vdd_last;
+ int ret;
+ unsigned long vdd_string_override;
+ char *vdd_string;
+ static const uint16_t vdd[32] = {
+ 0, /* unused */
+ 9875, /* 0.9875V */
+ 9750,
+ 9625,
+ 9500,
+ 9375,
+ 9250,
+ 9125,
+ 9000,
+ 8875,
+ 8750,
+ 8625,
+ 8500,
+ 8375,
+ 8250,
+ 8125,
+ 10000, /* 1.0000V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 0, /* reserved */
+ };
+ struct vdd_drive {
+ u8 vid;
+ unsigned voltage;
+ };
+
+ ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ debug("VID: I2c failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+
+ /* get the voltage ID from fuse status register */
+ fusesr = in_be32(&gur->dcfg_fusesr);
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_VID_MASK;
+ if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
+ }
+ vdd_target = vdd[vid];
+
+ /* check override variable for overriding VDD */
+ vdd_string = getenv("t4240qds_vdd_mv");
+ if (vdd_override == 0 && vdd_string &&
+ !strict_strtoul(vdd_string, 10, &vdd_string_override))
+ vdd_override = vdd_string_override;
+ if (vdd_override >= 819 && vdd_override <= 1212) {
+ vdd_target = vdd_override * 10; /* convert to 1/10 mV */
+ debug("VDD override is %lu\n", vdd_override);
+ } else if (vdd_override != 0) {
+ printf("Invalid value.\n");
+ }
+
+ if (vdd_target == 0) {
+ debug("VID: VID not used\n");
+ ret = 0;
+ goto exit;
+ } else {
+ /* round up and divice by 10 to get a value in mV */
+ vdd_target = DIV_ROUND_UP(vdd_target, 10);
+ debug("VID: vid = %d mV\n", vdd_target);
+ }
+
+ /*
+ * Check current board VID setting
+ * Voltage regulator support output to 6.250mv step
+ * The highes voltage allowed for this board is (vid=0x40) 1.21250V
+ * the lowest is (vid=0x7f) 0.81875V
+ */
+ vid_current = QIXIS_READ(brdcfg[6]);
+ vdd_current = 121250 - (vid_current - 0x40) * 625;
+ debug("VID: Current vid setting is (0x%x) %d mV\n",
+ vid_current, vdd_current/100);
+
+ /*
+ * Read voltage monitor to check real voltage.
+ * Voltage monitor LSB is 4mv.
+ */
+ vdd_last = read_voltage();
+ if (vdd_last < 0) {
+ printf("VID: Could not read voltage sensor abort VID adjustment\n");
+ ret = -1;
+ goto exit;
+ }
+ debug("VID: Core voltage is at %d mV\n", vdd_last);
+ /*
+ * Adjust voltage to at or 8mV above target.
+ * Each step of adjustment is 6.25mV.
+ * Stepping down too fast may cause over current.
+ */
+ while (vdd_last > 0 && vid_current < 0x80 &&
+ vdd_last > (vdd_target + 8)) {
+ vid_current++;
+ vdd_last = set_voltage(vid_current);
+ }
+ /*
+ * Check if we need to step up
+ * This happens when board voltage switch was set too low
+ */
+ while (vdd_last > 0 && vid_current >= 0x40 &&
+ vdd_last < vdd_target + 2) {
+ vid_current--;
+ vdd_last = set_voltage(vid_current);
+ }
+ if (vdd_last > 0)
+ printf("VID: Core voltage %d mV\n", vdd_last);
+ else
+ ret = -1;
+
+exit:
+ if (re_enable)
+ enable_interrupts();
+ return ret;
+}
+
/* Configure Crossbar switches for Front-Side SerDes Ports */
int config_frontside_crossbar_vsc3316(void)
{
@@ -282,8 +519,15 @@ int board_early_init_r(void)
setup_portals();
#endif
- /* Disable remote I2C connectoin */
- QIXIS_WRITE(brdcfg[5], BRDCFG5_RESET);
+ /* Disable remote I2C connection to qixis fpga */
+ QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
+
+ /*
+ * Adjust core voltage according to voltage ID
+ * This function changes I2C mux to channel 2.
+ */
+ if (adjust_vdd(0))
+ printf("Warning: Adjusting core voltage failed.\n");
/* Configure board SERDES ports crossbar */
config_frontside_crossbar_vsc3316();
@@ -296,6 +540,20 @@ int board_early_init_r(void)
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+ /* use accurate clock measurement */
+ int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
+ int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+ u32 val;
+
+ val = freq * base;
+ if (val) {
+ debug("SYS Clock measurement is: %d\n", val);
+ return val;
+ } else {
+ printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
+ }
+#endif
switch (sysclk_conf & 0x0F) {
case QIXIS_SYSCLK_83:
@@ -319,6 +577,20 @@ unsigned long get_board_sys_clk(void)
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+ /* use accurate clock measurement */
+ int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
+ int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+ u32 val;
+
+ val = freq * base;
+ if (val) {
+ debug("DDR Clock measurement is: %d\n", val);
+ return val;
+ } else {
+ printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
+ }
+#endif
switch ((ddrclk_conf & 0x30) >> 4) {
case QIXIS_DDRCLK_100:
@@ -357,7 +629,7 @@ int misc_init_r(void)
sw = QIXIS_READ(brdcfg[2]);
for (i = 0; i < MAX_SERDES; i++) {
- unsigned int clock = (sw >> (2 * i)) & 3;
+ unsigned int clock = (sw >> (6 - 2 * i)) & 3;
switch (clock) {
case 0:
actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
@@ -414,6 +686,106 @@ void ft_board_setup(void *blob, bd_t *bd)
}
/*
+ * This function is called by bdinfo to print detail board information.
+ * As an exmaple for future board, we organize the messages into
+ * several sections. If applicable, the message is in the format of
+ * <name> = <value>
+ * It should aligned with normal output of bdinfo command.
+ *
+ * Voltage: Core, DDR and another configurable voltages
+ * Clock : Critical clocks which are not printed already
+ * RCW : RCW source if not printed already
+ * Misc : Other important information not in above catagories
+ */
+void board_detail(void)
+{
+ int i;
+ u8 brdcfg[16], dutcfg[16], rst_ctl;
+ int vdd, rcwsrc;
+ static const char * const clk[] = {"66.67", "100", "125", "133.33"};
+
+ for (i = 0; i < 16; i++) {
+ brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
+ dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
+ }
+
+ /* Voltage secion */
+ if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) {
+ vdd = read_voltage();
+ if (vdd > 0)
+ printf("Core voltage= %d mV\n", vdd);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+ }
+
+ printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
+
+ /* clock section */
+ printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n",
+ clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
+
+ /* RCW section */
+ rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
+ puts("RCW source = ");
+ switch (rcwsrc) {
+ case 0x017:
+ case 0x01f:
+ puts("8-bit NOR\n");
+ break;
+ case 0x027:
+ case 0x02F:
+ puts("16-bit NOR\n");
+ break;
+ case 0x040:
+ puts("SDHC/eMMC\n");
+ break;
+ case 0x044:
+ puts("SPI 16-bit addressing\n");
+ break;
+ case 0x045:
+ puts("SPI 24-bit addressing\n");
+ break;
+ case 0x048:
+ puts("I2C normal addressing\n");
+ break;
+ case 0x049:
+ puts("I2C extended addressing\n");
+ break;
+ case 0x108:
+ case 0x109:
+ case 0x10a:
+ case 0x10b:
+ puts("8-bit NAND, 2KB\n");
+ break;
+ default:
+ if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
+ puts("Hard-coded RCW\n");
+ else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
+ puts("8-bit NAND, 4KB\n");
+ else
+ puts("unknown\n");
+ break;
+ }
+
+ /* Misc section */
+ rst_ctl = QIXIS_READ(rst_ctl);
+ puts("HRESET_REQ = ");
+ switch (rst_ctl & 0x30) {
+ case 0x00:
+ puts("Ignored\n");
+ break;
+ case 0x10:
+ puts("Assert HRESET\n");
+ break;
+ case 0x30:
+ puts("Reset system\n");
+ break;
+ default:
+ puts("N/A\n");
+ break;
+ }
+}
+
+/*
* Reverse engineering switch settings.
* Some bits cannot be figured out. They will be displayed as
* underscore in binary format. mask[] has those bits.
@@ -429,7 +801,7 @@ void qixis_dump_switch(void)
* Any bit with 1 means that bit cannot be reverse engineered.
* It will be displayed as _ in binary format.
*/
- static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xdf, 0x3f, 0x1f};
+ static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
char buf[10];
u8 brdcfg[16], dutcfg[16];
@@ -460,7 +832,8 @@ void qixis_dump_switch(void)
sw[5] = ((brdcfg[0] & 0x0f) << 4) | \
((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \
((brdcfg[0] & 0x40) >> 5);
- sw[6] = (brdcfg[11] & 0x20);
+ sw[6] = (brdcfg[11] & 0x20) |
+ ((brdcfg[5] & 0x02) << 3);
sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \
((brdcfg[5] & 0x10) << 2);
sw[8] = ((brdcfg[12] & 0x08) << 4) | \
@@ -472,3 +845,23 @@ void qixis_dump_switch(void)
i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
}
}
+
+static int do_vdd_adjust(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ulong override;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+ if (!strict_strtoul(argv[1], 10, &override))
+ adjust_vdd(override); /* the value is checked by callee */
+ else
+ return CMD_RET_USAGE;
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ vdd_override, 2, 0, do_vdd_adjust,
+ "Override VDD",
+ "- override with the voltage specified in mV, eg. 1050"
+);
diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c
index 80eb511..92c01cf 100644
--- a/board/freescale/t4qds/tlb.c
+++ b/board/freescale/t4qds/tlb.c
@@ -115,7 +115,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 13, BOOKE_PAGESZ_4M, 1),
+ 0, 13, BOOKE_PAGESZ_32M, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE
/*
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg
index 21ff6d6..0173535 100644
--- a/board/genesi/mx51_efikamx/imximage_mx.cfg
+++ b/board/genesi/mx51_efikamx/imximage_mx.cfg
@@ -26,7 +26,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/genesi/mx51_efikamx/imximage_sb.cfg b/board/genesi/mx51_efikamx/imximage_sb.cfg
index 7ddd0b1..5c46769 100644
--- a/board/genesi/mx51_efikamx/imximage_sb.cfg
+++ b/board/genesi/mx51_efikamx/imximage_sb.cfg
@@ -26,7 +26,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/iomega/iconnect/kwbimage.cfg b/board/iomega/iconnect/kwbimage.cfg
index 4b64dab..1b66207 100644
--- a/board/iomega/iconnect/kwbimage.cfg
+++ b/board/iomega/iconnect/kwbimage.cfg
@@ -19,7 +19,7 @@
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/karo/tk71/kwbimage.cfg b/board/karo/tk71/kwbimage.cfg
index 0166826..9a9cf9d 100644
--- a/board/karo/tk71/kwbimage.cfg
+++ b/board/karo/tk71/kwbimage.cfg
@@ -24,7 +24,7 @@
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/keymile/km_arm/kwbimage-memphis.cfg b/board/keymile/km_arm/kwbimage-memphis.cfg
index 5aa0de2..63822a5 100644
--- a/board/keymile/km_arm/kwbimage-memphis.cfg
+++ b/board/keymile/km_arm/kwbimage-memphis.cfg
@@ -23,7 +23,7 @@
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg
index e5e9942..d941d7e 100644
--- a/board/keymile/km_arm/kwbimage.cfg
+++ b/board/keymile/km_arm/kwbimage.cfg
@@ -20,7 +20,7 @@
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/keymile/km_arm/kwbimage_128M16_1.cfg b/board/keymile/km_arm/kwbimage_128M16_1.cfg
index 5de8df7..4c31a0d 100644
--- a/board/keymile/km_arm/kwbimage_128M16_1.cfg
+++ b/board/keymile/km_arm/kwbimage_128M16_1.cfg
@@ -25,7 +25,7 @@
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/keymile/km_arm/kwbimage_256M8_1.cfg b/board/keymile/km_arm/kwbimage_256M8_1.cfg
index d0a09f6..31b9203 100644
--- a/board/keymile/km_arm/kwbimage_256M8_1.cfg
+++ b/board/keymile/km_arm/kwbimage_256M8_1.cfg
@@ -22,7 +22,7 @@
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
# This configuration applies to COGE5 design (ARM-part)
diff --git a/board/openrisc/openrisc-generic/u-boot.lds b/board/openrisc/openrisc-generic/u-boot.lds
deleted file mode 100644
index 9024f30..0000000
--- a/board/openrisc/openrisc-generic/u-boot.lds
+++ /dev/null
@@ -1,77 +0,0 @@
-#include <config.h>
-OUTPUT_ARCH(or32)
-__DYNAMIC = 0;
-
-MEMORY
-{
- vectors : ORIGIN = 0, LENGTH = 0x2000
- ram : ORIGIN = CONFIG_SYS_MONITOR_BASE,
- LENGTH = CONFIG_SYS_MONITOR_LEN
-}
-
-SECTIONS
-{
- .vectors :
- {
- *(.vectors)
- } > vectors
-
- __start = .;
- .text : AT (__start) {
- _stext = .;
- *(.text)
- _etext = .;
- *(.lit)
- *(.shdata)
- _endtext = .;
- } > ram
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- .rodata : {
- *(.rodata);
- *(.rodata.*)
- } > ram
-
- .shbss :
- {
- *(.shbss)
- } > ram
-
- .talias :
- {
- } > ram
-
- .data : {
- sdata = .;
- _sdata = .;
- *(.data)
- edata = .;
- _edata = .;
- } > ram
-
- .bss :
- {
- _bss_start = .;
- *(.bss)
- *(COMMON)
- _bss_end = .;
- } > ram
- __end = .;
-
- /* No stack specification - done manually */
-
- .stab 0 (NOLOAD) :
- {
- [ .stab ]
- }
-
- .stabstr 0 (NOLOAD) :
- {
- [ .stabstr ]
- }
-}
diff --git a/board/raidsonic/ib62x0/kwbimage.cfg b/board/raidsonic/ib62x0/kwbimage.cfg
index bade627..27a5e31 100644
--- a/board/raidsonic/ib62x0/kwbimage.cfg
+++ b/board/raidsonic/ib62x0/kwbimage.cfg
@@ -20,7 +20,7 @@
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
-# Refer docs/README.kwimage for more details about how-to configure
+# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
diff --git a/board/sorcery/Makefile b/board/sorcery/Makefile
deleted file mode 100644
index e1752e3..0000000
--- a/board/sorcery/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-#
-# (C) Copyright 2005-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS := $(BOARD).o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/sorcery/sorcery.c b/board/sorcery/sorcery.c
deleted file mode 100644
index 90d4298..0000000
--- a/board/sorcery/sorcery.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2004, Freescale Inc.
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc8220.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <pci.h>
-#include <netdev.h>
-
-phys_size_t initdram (int board_type)
-{
- ulong size;
-
- size = dramSetup ();
-
- return get_ram_size(CONFIG_SYS_SDRAM_BASE, size);
-}
-
-int checkboard (void)
-{
- puts ("Board: Sorcery-C MPC8220\n");
-
- return 0;
-}
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI devices, report devices found.
- */
-static struct pci_controller hose;
-
-#endif /* CONFIG_PCI */
-
-void pci_init_board (void)
-{
-#ifdef CONFIG_PCI
- extern void pci_mpc8220_init (struct pci_controller *hose);
- pci_mpc8220_init (&hose);
-#endif /* CONFIG_PCI */
-}
-
-int board_eth_init(bd_t *bis)
-{
- /* Initialize built-in FEC first */
- cpu_eth_init(bis);
- return pci_eth_init(bis);
-}
diff --git a/board/ttcontrol/vision2/imximage_hynix.cfg b/board/ttcontrol/vision2/imximage_hynix.cfg
index c1de94f..64bddbb 100644
--- a/board/ttcontrol/vision2/imximage_hynix.cfg
+++ b/board/ttcontrol/vision2/imximage_hynix.cfg
@@ -23,7 +23,7 @@
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
index befbb3a..2f5f20e 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -31,12 +31,17 @@
#include <asm/processor.h>
#include <asm/microblaze_intc.h>
#include <asm/asm.h>
+#include <asm/gpio.h>
+
+#ifdef CONFIG_XILINX_GPIO
+static int reset_pin = -1;
+#endif
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
-#ifdef CONFIG_SYS_GPIO_0
- *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) =
- ++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)));
+#ifdef CONFIG_XILINX_GPIO
+ if (reset_pin != -1)
+ gpio_direction_output(reset_pin, 1);
#endif
#ifdef CONFIG_XILINX_TB_WATCHDOG
@@ -52,8 +57,10 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
int gpio_init (void)
{
-#ifdef CONFIG_SYS_GPIO_0
- *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0xFFFFFFFF;
+#ifdef CONFIG_XILINX_GPIO
+ reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1);
+ if (reset_pin != -1)
+ gpio_request(reset_pin, "reset_pin");
#endif
return 0;
}