1826 files changed, 42119 insertions, 74448 deletions

diff --git a/board/AndesTech/adp-ae3xx/Kconfig b/board/AndesTech/adp-ae3xx/Kconfig
new file mode 100644
index 0000000..8ec69d6
--- /dev/null
+++ b/board/AndesTech/adp-ae3xx/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_ADP_AE3XX
+
+config SYS_CPU
+	default "n1213"
+
+config SYS_BOARD
+	default "adp-ae3xx"
+
+config SYS_VENDOR
+	default "AndesTech"
+
+config SYS_SOC
+	default "ae3xx"
+
+config SYS_CONFIG_NAME
+	default "adp-ae3xx"
+
+endif
diff --git a/board/AndesTech/adp-ae3xx/MAINTAINERS b/board/AndesTech/adp-ae3xx/MAINTAINERS
new file mode 100644
index 0000000..02e5a19
--- /dev/null
+++ b/board/AndesTech/adp-ae3xx/MAINTAINERS
@@ -0,0 +1,6 @@
+ADP-AG101P BOARD
+M:	Andes <uboot@andestech.com>
+S:	Maintained
+F:	board/AndesTech/adp-ae3xx/
+F:	include/configs/adp-ae3xx.h
+F:	configs/adp-ae3xx_defconfig
diff --git a/board/AndesTech/adp-ae3xx/Makefile b/board/AndesTech/adp-ae3xx/Makefile
new file mode 100644
index 0000000..842dfb4
--- /dev/null
+++ b/board/AndesTech/adp-ae3xx/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2016 Andes Technology Corporation
+# Rick Chen, Andes Technology Corporation <rick@andestech.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= adp-ae3xx.o
diff --git a/board/AndesTech/adp-ae3xx/adp-ae3xx.c b/board/AndesTech/adp-ae3xx/adp-ae3xx.c
new file mode 100644
index 0000000..98ed4d9
--- /dev/null
+++ b/board/AndesTech/adp-ae3xx/adp-ae3xx.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+#include <netdev.h>
+#endif
+#include <linux/io.h>
+#include <faraday/ftsdc010.h>
+#include <faraday/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+int board_init(void)
+{
+	/*
+	 * refer to BOOT_PARAMETER_PA_BASE within
+	 * "linux/arch/nds32/include/asm/misc_spec.h"
+	 */
+	printf("Board: %s\n" , CONFIG_SYS_BOARD);
+	gd->bd->bi_arch_number = MACH_TYPE_ADPAE3XX;
+	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned long sdram_base = PHYS_SDRAM_0;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
+	unsigned long actual_size;
+	actual_size = get_ram_size((void *)sdram_base, expected_size);
+	gd->ram_size = actual_size;
+	if (expected_size != actual_size) {
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+	}
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
+	gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
+int board_eth_init(bd_t *bd)
+{
+	return ftmac100_initialize(bd);
+}
+#endif
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+	if (banknum == 0) {	/* non-CFI boot flash */
+		info->portwidth = FLASH_CFI_8BIT;
+		info->chipwidth = FLASH_CFI_BY8;
+		info->interface = FLASH_CFI_X8;
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifndef CONFIG_DM_MMC
+#ifdef CONFIG_FTSDC010
+	ftsdc010_mmc_init(0);
+#endif
+#endif
+	return 0;
+}
diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c b/board/AndesTech/adp-ag101p/adp-ag101p.c
index 84c77f7..79608f4 100644
--- a/board/AndesTech/adp-ag101p/adp-ag101p.c
+++ b/board/AndesTech/adp-ag101p/adp-ag101p.c
@@ -7,8 +7,12 @@
  */
 
 #include <common.h>
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
 #include <netdev.h>
+#endif
+#include <linux/io.h>
 #include <asm/io.h>
+#include <asm/mach-types.h>
 
 #include <faraday/ftsdc010.h>
 #include <faraday/ftsmc020.h>
@@ -25,6 +29,7 @@ int board_init(void)
 	 * refer to BOOT_PARAMETER_PA_BASE within
 	 * "linux/arch/nds32/include/asm/misc_spec.h"
 	 */
+	printf("Board: %s\n" , CONFIG_SYS_BOARD);
 	gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P;
 	gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
 
@@ -49,18 +54,22 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
 	gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
+
+	return 0;
 }
 
+#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
 int board_eth_init(bd_t *bd)
 {
 	return ftmac100_initialize(bd);
 }
+#endif
 
 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
 {
@@ -76,6 +85,8 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
 
 int board_mmc_init(bd_t *bis)
 {
+#ifdef CONFIG_FTSDC010
 	ftsdc010_mmc_init(0);
+#endif
 	return 0;
 }
diff --git a/board/Arcturus/ucp1020/spl.c b/board/Arcturus/ucp1020/spl.c
index 9315bb7..cd484fc 100644
--- a/board/Arcturus/ucp1020/spl.c
+++ b/board/Arcturus/ucp1020/spl.c
@@ -83,7 +83,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
 	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
 
-	probecpu();
+	arch_cpu_init();
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
@@ -110,7 +110,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-	gd->ram_size = initdram(0);
+	dram_init();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("Tertiary program loader running in sram...");
 #else
@@ -119,8 +119,6 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
-#elif defined(CONFIG_SPL_SPI_BOOT)
-	spi_boot();
 #elif defined(CONFIG_SPL_NAND_BOOT)
 	nand_boot();
 #endif
diff --git a/board/Arcturus/ucp1020/ucp1020.c b/board/Arcturus/ucp1020/ucp1020.c
index 0fc2bac..0d086e8 100644
--- a/board/Arcturus/ucp1020/ucp1020.c
+++ b/board/Arcturus/ucp1020/ucp1020.c
@@ -315,7 +315,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	FT_FSL_PCI_SETUP;
 
 #if defined(CONFIG_HAS_FSL_DR_USB)
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
diff --git a/board/Barix/ipam390/ipam390.c b/board/Barix/ipam390/ipam390.c
index 6ce8960..3a58402 100644
--- a/board/Barix/ipam390/ipam390.c
+++ b/board/Barix/ipam390/ipam390.c
@@ -25,10 +25,11 @@
 #include <asm/arch/pinmux_defs.h>
 #include <asm/io.h>
 #include <asm/arch/davinci_misc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
 #include <hwconfig.h>
 #include <bootstage.h>
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -188,9 +189,7 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-#ifndef CONFIG_USE_IRQ
 	irq_init();
-#endif
 
 	/* arch number of the board */
 	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index e947e54..c3a56db 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -259,18 +259,19 @@ static int load_devicetree(void)
 	}
 #ifdef CONFIG_NAND
 	dtbsize = 0x20000;
-	rc = nand_read_skip_bad(nand_info[0], 0x40000, (size_t *)&dtbsize,
+	rc = nand_read_skip_bad(get_nand_dev_by_index(0), 0x40000,
+				(size_t *)&dtbsize,
 				NULL, 0x20000, (u_char *)dtbaddr);
 #else
 	char *dtbname = getenv("dtb");
 	char *dtbdev = getenv("dtbdev");
-	char *dtppart = getenv("dtbpart");
-	if (!dtbdev || !dtbdev || !dtbname) {
+	char *dtbpart = getenv("dtbpart");
+	if (!dtbdev || !dtbpart || !dtbname) {
 		printf("%s: <dtbdev>/<dtbpart>/<dtb> missing.\n", __func__);
 		return -1;
 	}
 
-	if (fs_set_blk_dev(dtbdev, dtppart, FS_TYPE_EXT)) {
+	if (fs_set_blk_dev(dtbdev, dtbpart, FS_TYPE_EXT)) {
 		puts("load_devicetree: set_blk_dev failed.\n");
 		return -1;
 	}
@@ -684,10 +685,15 @@ int board_eth_init(bd_t *bis)
 	return rv;
 }
 #endif /* defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD) */
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
-	return omap_mmc_init(1, 0, 0, -1, -1);
+	int rc = 0;
+
+	rc |= omap_mmc_init(0, 0, 0, -1, -1);
+	rc |= omap_mmc_init(1, 0, 0, -1, -1);
+
+	return rc;
 }
 #endif
 int overwrite_console(void)
diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c
index 2164b52..a00a83a 100644
--- a/board/BuS/eb_cpu5282/eb_cpu5282.c
+++ b/board/BuS/eb_cpu5282/eb_cpu5282.c
@@ -35,7 +35,7 @@ int checkboard (void)
 	return 0;
 }
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	int size, i;
 
@@ -92,7 +92,9 @@ phys_size_t initdram (int board_type)
 	*(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
 	size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
 #endif
-	return size;
+	gd->ram_size = size;
+
+	return 0;
 }
 
 #if defined(CONFIG_SYS_DRAM_TEST)
@@ -174,7 +176,7 @@ void __led_init(led_id_t mask, int state)
 
 void __led_set(led_id_t mask, int state)
 {
-	if (state == STATUS_LED_ON)
+	if (state == CONFIG_LED_STATUS_ON)
 		MCFGPTA_GPTPORT |= (1 << 3);
 	else
 		MCFGPTA_GPTPORT &= ~(1 << 3);
diff --git a/board/CZ.NIC/turris_omnia/Makefile b/board/CZ.NIC/turris_omnia/Makefile
new file mode 100644
index 0000000..f2ae506
--- /dev/null
+++ b/board/CZ.NIC/turris_omnia/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= turris_omnia.o
diff --git a/board/CZ.NIC/turris_omnia/kwbimage.cfg b/board/CZ.NIC/turris_omnia/kwbimage.cfg
new file mode 100644
index 0000000..cc05792
--- /dev/null
+++ b/board/CZ.NIC/turris_omnia/kwbimage.cfg
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl.bin 0000005b 00000068
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
new file mode 100644
index 0000000..a427509
--- /dev/null
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -0,0 +1,535 @@
+/*
+ * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
+ * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
+ *
+ * Derived from the code for
+ *   Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <dm/uclass.h>
+#include <fdt_support.h>
+#include <time.h>
+
+#ifdef CONFIG_ATSHA204A
+# include <atsha204a-i2c.h>
+#endif
+
+#ifdef CONFIG_WDT_ORION
+# include <wdt.h>
+#endif
+
+#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OMNIA_I2C_EEPROM_DM_NAME	"i2c@0"
+#define OMNIA_I2C_EEPROM		0x54
+#define OMNIA_I2C_EEPROM_CONFIG_ADDR	0x0
+#define OMNIA_I2C_EEPROM_ADDRLEN	2
+#define OMNIA_I2C_EEPROM_MAGIC		0x0341a034
+
+#define OMNIA_I2C_MCU_DM_NAME		"i2c@0"
+#define OMNIA_I2C_MCU_ADDR_STATUS	0x1
+#define OMNIA_I2C_MCU_SATA		0x20
+#define OMNIA_I2C_MCU_CARDDET		0x10
+#define OMNIA_I2C_MCU			0x2a
+#define OMNIA_I2C_MCU_WDT_ADDR		0x0b
+
+#define OMNIA_ATSHA204_OTP_VERSION	0
+#define OMNIA_ATSHA204_OTP_SERIAL	1
+#define OMNIA_ATSHA204_OTP_MAC0		3
+#define OMNIA_ATSHA204_OTP_MAC1		4
+
+#define MVTWSI_ARMADA_DEBUG_REG		0x8c
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2014_T3.0"
+ */
+#define OMNIA_GPP_OUT_ENA_LOW					\
+	(~(BIT(1)  | BIT(4)  | BIT(6)  | BIT(7)  | BIT(8)  | BIT(9)  |	\
+	   BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) |	\
+	   BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
+#define OMNIA_GPP_OUT_ENA_MID					\
+	(~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) |	\
+	   BIT(16) | BIT(17) | BIT(18)))
+
+#define OMNIA_GPP_OUT_VAL_LOW	0x0
+#define OMNIA_GPP_OUT_VAL_MID	0x0
+#define OMNIA_GPP_POL_LOW	0x0
+#define OMNIA_GPP_POL_MID	0x0
+
+static struct serdes_map board_serdes_map_pex[] = {
+	{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
+};
+
+static struct serdes_map board_serdes_map_sata[] = {
+	{SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
+};
+
+static bool omnia_detect_sata(void)
+{
+	struct udevice *bus, *dev;
+	int ret, retry = 3;
+	u16 mode;
+
+	puts("SERDES0 card detect: ");
+
+	if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) {
+		puts("Cannot find MCU bus!\n");
+		return false;
+	}
+
+	ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev);
+	if (ret) {
+		puts("Cannot get MCU chip!\n");
+		return false;
+	}
+
+	for (; retry > 0; --retry) {
+		ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2);
+		if (!ret)
+			break;
+	}
+
+	if (!retry) {
+		puts("I2C read failed! Default PEX\n");
+		return false;
+	}
+
+	if (!(mode & OMNIA_I2C_MCU_CARDDET)) {
+		puts("NONE\n");
+		return false;
+	}
+
+	if (mode & OMNIA_I2C_MCU_SATA) {
+		puts("SATA\n");
+		return true;
+	} else {
+		puts("PEX\n");
+		return false;
+	}
+}
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+	if (omnia_detect_sata()) {
+		*serdes_map_array = board_serdes_map_sata;
+		*count = ARRAY_SIZE(board_serdes_map_sata);
+	} else {
+		*serdes_map_array = board_serdes_map_pex;
+		*count = ARRAY_SIZE(board_serdes_map_pex);
+	}
+
+	return 0;
+}
+
+struct omnia_eeprom {
+	u32 magic;
+	u32 ramsize;
+	char region[4];
+	u32 crc;
+};
+
+static bool omnia_read_eeprom(struct omnia_eeprom *oep)
+{
+	struct udevice *bus, *dev;
+	int ret, crc, retry = 3;
+
+	if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_EEPROM_DM_NAME, &bus)) {
+		puts("Cannot find EEPROM bus\n");
+		return false;
+	}
+
+	ret = i2c_get_chip(bus, OMNIA_I2C_EEPROM, OMNIA_I2C_EEPROM_ADDRLEN, &dev);
+	if (ret) {
+		puts("Cannot get EEPROM chip\n");
+		return false;
+	}
+
+	for (; retry > 0; --retry) {
+		ret = dm_i2c_read(dev, OMNIA_I2C_EEPROM_CONFIG_ADDR, (uchar *) oep, sizeof(struct omnia_eeprom));
+		if (ret)
+			continue;
+
+		if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
+			puts("I2C EEPROM missing magic number!\n");
+			continue;
+		}
+
+		crc = crc32(0, (unsigned char *) oep,
+			    sizeof(struct omnia_eeprom) - 4);
+		if (crc == oep->crc) {
+			break;
+		} else {
+			printf("CRC of EEPROM memory config failed! "
+			       "calc=0x%04x saved=0x%04x\n", crc, oep->crc);
+		}
+	}
+
+	if (!retry) {
+		puts("I2C EEPROM read failed!\n");
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct hws_topology_map board_topology_map_1g = {
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+	{ { { {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0} },
+	    SPEED_BIN_DDR_1600K,	/* speed_bin */
+	    BUS_WIDTH_16,		/* memory_width */
+	    MEM_4G,			/* mem_size */
+	    DDR_FREQ_800,		/* frequency */
+	    0, 0,			/* cas_l cas_wl */
+	    HWS_TEMP_NORMAL,		/* temperature */
+	    HWS_TIM_2T} },		/* timing (force 2t) */
+	5,				/* Num Of Bus Per Interface*/
+	BUS_MASK_32BIT			/* Busses mask */
+};
+
+static struct hws_topology_map board_topology_map_2g = {
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+	{ { { {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0} },
+	    SPEED_BIN_DDR_1600K,	/* speed_bin */
+	    BUS_WIDTH_16,		/* memory_width */
+	    MEM_8G,			/* mem_size */
+	    DDR_FREQ_800,		/* frequency */
+	    0, 0,			/* cas_l cas_wl */
+	    HWS_TEMP_NORMAL,		/* temperature */
+	    HWS_TIM_2T} },		/* timing (force 2t) */
+	5,				/* Num Of Bus Per Interface*/
+	BUS_MASK_32BIT			/* Busses mask */
+};
+
+struct hws_topology_map *ddr3_get_topology_map(void)
+{
+	static int mem = 0;
+	struct omnia_eeprom oep;
+
+	/* Get the board config from EEPROM */
+	if (mem == 0) {
+		if(!omnia_read_eeprom(&oep))
+			goto out;
+
+		printf("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
+
+		if (oep.ramsize == 0x2)
+			mem = 2;
+		else
+			mem = 1;
+	}
+
+out:
+	/* Hardcoded fallback */
+	if (mem == 0) {
+		puts("WARNING: Memory config from EEPROM read failed.\n");
+		puts("Falling back to default 1GiB map.\n");
+		mem = 1;
+	}
+
+	/* Return the board topology as defined in the board code */
+	if (mem == 1)
+		return &board_topology_map_1g;
+	if (mem == 2)
+		return &board_topology_map_2g;
+
+	return &board_topology_map_1g;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static int set_regdomain(void)
+{
+	struct omnia_eeprom oep;
+	char rd[3] = {' ', ' ', 0};
+
+	if (omnia_read_eeprom(&oep))
+		memcpy(rd, &oep.region, 2);
+	else
+		puts("EEPROM regdomain read failed.\n");
+
+	printf("Regdomain set to %s\n", rd);
+	return setenv("regdomain", rd);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	u32 i2c_debug_reg;
+
+	/* Configure MPP */
+	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+	writel(0x11244011, MVEBU_MPP_BASE + 0x08);
+	writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
+	writel(0x22200002, MVEBU_MPP_BASE + 0x10);
+	writel(0x30042022, MVEBU_MPP_BASE + 0x14);
+	writel(0x55550555, MVEBU_MPP_BASE + 0x18);
+	writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
+
+	/* Set GPP Out value */
+	writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+	/* Disable I2C debug mode blocking 0x64 I2C address */
+	i2c_debug_reg = readl(MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG);
+	i2c_debug_reg &= ~(1<<18);
+	writel(i2c_debug_reg, MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG);
+
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+static bool disable_mcu_watchdog(void)
+{
+	struct udevice *bus, *dev;
+	int ret, retry = 3;
+	uchar buf[1] = {0x0};
+
+	if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) {
+		puts("Cannot find MCU bus! Can not disable MCU WDT.\n");
+		return false;
+	}
+
+	ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev);
+	if (ret) {
+		puts("Cannot get MCU chip! Can not disable MCU WDT.\n");
+		return false;
+	}
+
+	for (; retry > 0; --retry)
+		if (!dm_i2c_write(dev, OMNIA_I2C_MCU_WDT_ADDR, (uchar *) buf, 1))
+			break;
+
+	if (retry <= 0) {
+		puts("I2C MCU watchdog failed to disable!\n");
+		return false;
+	}
+
+	return true;
+}
+#endif
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION)
+static struct udevice *watchdog_dev = NULL;
+#endif
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+#ifndef CONFIG_SPL_BUILD
+# ifdef CONFIG_WDT_ORION
+	if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
+		puts("Cannot find Armada 385 watchdog!\n");
+	} else {
+		puts("Enabling Armada 385 watchdog.\n");
+		wdt_start(watchdog_dev, (u32) 25000000 * 120, 0);
+	}
+# endif
+
+	if (disable_mcu_watchdog())
+		puts("Disabled MCU startup watchdog.\n");
+
+	set_regdomain();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_WATCHDOG
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+# if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION)
+	static ulong next_reset = 0;
+	ulong now;
+
+	if (!watchdog_dev)
+		return;
+
+	now = timer_get_us();
+
+	/* Do not reset the watchdog too often */
+	if (now > next_reset) {
+		wdt_reset(watchdog_dev);
+		next_reset = now + 1000;
+	}
+# endif
+}
+#endif
+
+int board_late_init(void)
+{
+#ifndef CONFIG_SPL_BUILD
+	set_regdomain();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_ATSHA204A
+static struct udevice *get_atsha204a_dev(void)
+{
+	static struct udevice *dev = NULL;
+
+	if (dev != NULL)
+		return dev;
+
+	if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
+		puts("Cannot find ATSHA204A on I2C bus!\n");
+		dev = NULL;
+	}
+
+	return dev;
+}
+#endif
+
+int checkboard(void)
+{
+	u32 version_num, serial_num;
+	int err = 1;
+
+#ifdef CONFIG_ATSHA204A
+	struct udevice *dev = get_atsha204a_dev();
+
+	if (dev) {
+		err = atsha204a_wakeup(dev);
+		if (err)
+			goto out;
+
+		err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+				     OMNIA_ATSHA204_OTP_VERSION,
+				     (u8 *) &version_num);
+		if (err)
+			goto out;
+
+		err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+				     OMNIA_ATSHA204_OTP_SERIAL,
+				     (u8 *) &serial_num);
+		if (err)
+			goto out;
+
+		atsha204a_sleep(dev);
+	}
+
+out:
+#endif
+
+	if (err)
+		printf("Board: Turris Omnia (ver N/A). SN: N/A\n");
+	else
+		printf("Board: Turris Omnia SNL %08X%08X\n",
+		       be32_to_cpu(version_num), be32_to_cpu(serial_num));
+
+	return 0;
+}
+
+static void increment_mac(u8 *mac)
+{
+	int i;
+
+	for (i = 5; i >= 3; i--) {
+		mac[i] += 1;
+		if (mac[i])
+			break;
+	}
+}
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_ATSHA204A
+	int err;
+	struct udevice *dev = get_atsha204a_dev();
+	u8 mac0[4], mac1[4], mac[6];
+
+	if (!dev)
+		goto out;
+
+	err = atsha204a_wakeup(dev);
+	if (err)
+		goto out;
+
+	err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+			     OMNIA_ATSHA204_OTP_MAC0, mac0);
+	if (err)
+		goto out;
+
+	err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
+			     OMNIA_ATSHA204_OTP_MAC1, mac1);
+	if (err)
+		goto out;
+
+	atsha204a_sleep(dev);
+
+	mac[0] = mac0[1];
+	mac[1] = mac0[2];
+	mac[2] = mac0[3];
+	mac[3] = mac1[1];
+	mac[4] = mac1[2];
+	mac[5] = mac1[3];
+
+	if (is_valid_ethaddr(mac))
+		eth_setenv_enetaddr("ethaddr", mac);
+
+	increment_mac(mac);
+
+	if (is_valid_ethaddr(mac))
+		eth_setenv_enetaddr("eth1addr", mac);
+
+	increment_mac(mac);
+
+	if (is_valid_ethaddr(mac))
+		eth_setenv_enetaddr("eth2addr", mac);
+
+out:
+#endif
+
+	return 0;
+}
+
diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c
index 7f5cfc8..3cd4dc9 100644
--- a/board/CarMediaLab/flea3/flea3.c
+++ b/board/CarMediaLab/flea3/flea3.c
@@ -10,7 +10,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/iomux-mx35.h>
@@ -19,6 +19,9 @@
 #include <asm/gpio.h>
 #include <asm/arch/sys_proto.h>
 #include <netdev.h>
+#include <fdt_support.h>
+#include <mtd_node.h>
+#include <jffs2/load_kernel.h>
 
 #ifndef CONFIG_BOARD_EARLY_INIT_F
 #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
@@ -27,18 +30,6 @@
 #define CCM_CCMR_CONFIG		0x003F4208
 
 #define ESDCTL_DDR2_CONFIG	0x007FFC3F
-#define ESDCTL_0x92220000	0x92220000
-#define ESDCTL_0xA2220000	0xA2220000
-#define ESDCTL_0xB2220000	0xB2220000
-#define ESDCTL_0x82228080	0x82228080
-#define ESDCTL_DDR2_EMR2	0x04000000
-#define ESDCTL_DDR2_EMR3	0x06000000
-#define ESDCTL_PRECHARGE	0x00000400
-#define ESDCTL_DDR2_EN_DLL	0x02000400
-#define ESDCTL_DDR2_RESET_DLL	0x00000333
-#define ESDCTL_DDR2_MR		0x00000233
-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
-#define ESDCTL_DELAY_LINE5	0x00F49F00
 
 static inline void dram_wait(unsigned int count)
 {
@@ -58,83 +49,6 @@ int dram_init(void)
 	return 0;
 }
 
-static void board_setup_sdram_bank(u32 start_address)
-
-{
-	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
-	u32 *cfg_reg, *ctl_reg;
-	u32 val;
-
-	switch (start_address) {
-	case CSD0_BASE_ADDR:
-		cfg_reg = &esdc->esdcfg0;
-		ctl_reg = &esdc->esdctl0;
-		break;
-	case CSD1_BASE_ADDR:
-		cfg_reg = &esdc->esdcfg1;
-		ctl_reg = &esdc->esdctl1;
-		break;
-	default:
-		return;
-	}
-
-	/* Initialize MISC register for DDR2 */
-	val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
-		ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
-	writel(val, &esdc->esdmisc);
-	val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
-	writel(val, &esdc->esdmisc);
-
-	/*
-	 * according to DDR2 specs, wait a while before
-	 * the PRECHARGE_ALL command
-	 */
-	dram_wait(0x20000);
-
-	/* Load DDR2 config and timing */
-	writel(ESDCTL_DDR2_CONFIG, cfg_reg);
-
-	/* Precharge ALL */
-	writel(ESDCTL_0x92220000,
-		ctl_reg);
-	writel(0xda, start_address + ESDCTL_PRECHARGE);
-
-	/* Load mode */
-	writel(ESDCTL_0xB2220000,
-		ctl_reg);
-	writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
-	writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
-	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
-	writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
-
-	/* Precharge ALL */
-	writel(ESDCTL_0x92220000,
-		ctl_reg);
-	writel(0xda, start_address + ESDCTL_PRECHARGE);
-
-	/* Set mode auto refresh : at least two refresh are required */
-	writel(ESDCTL_0xA2220000,
-		ctl_reg);
-	writel(0xda, start_address);
-	writel(0xda, start_address);
-
-	writel(ESDCTL_0xB2220000,
-		ctl_reg);
-	writeb(0xda, start_address + ESDCTL_DDR2_MR);
-	writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
-
-	/* OCD mode exit */
-	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
-
-	/* Set normal mode */
-	writel(ESDCTL_0x82228080,
-		ctl_reg);
-
-	dram_wait(0x20000);
-
-	/* Do not set delay lines, only for MDDR */
-}
-
 static void board_setup_sdram(void)
 {
 	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
@@ -143,7 +57,9 @@ static void board_setup_sdram(void)
 	writel(0x2000, &esdc->esdctl0);
 	writel(0x2000, &esdc->esdctl1);
 
-	board_setup_sdram_bank(CSD0_BASE_ADDR);
+
+	mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
+			     13, 10, 2, 0x8080);
 }
 
 static void setup_iomux_uart3(void)
@@ -206,6 +122,8 @@ static void setup_iomux_fec(void)
 		MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
 		MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
 		MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+		/* GPIO used to power off ethernet */
+		MX35_PAD_STXFS4__GPIO2_31,
 	};
 
 	/* setup pins for FEC */
@@ -267,6 +185,11 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
+	/* Enable power for ethernet */
+	gpio_direction_output(63, 0);
+
+	udelay(2000);
+
 	return 0;
 }
 
@@ -276,3 +199,24 @@ u32 get_board_rev(void)
 
 	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
 }
+
+/*
+ * called prior to booting kernel or by 'fdt boardsetup' command
+ *
+ */
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	struct node_info nodes[] = {
+		{ "physmap-flash.0", MTD_DEV_TYPE_NOR, },  /* NOR flash */
+		{ "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
+	};
+
+	if (getenv("fdt_noauto")) {
+		puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
+		return 0;
+	}
+
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
+	return 0;
+}
diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c
index edf6281..736d65c 100644
--- a/board/LaCie/edminiv2/edminiv2.c
+++ b/board/LaCie/edminiv2/edminiv2.c
@@ -14,6 +14,7 @@
 #include "../common/common.h"
 #include <spl.h>
 #include <ns16550.h>
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c
index 263bb54..2e6e9ef 100644
--- a/board/LaCie/net2big_v2/net2big_v2.c
+++ b/board/LaCie/net2big_v2/net2big_v2.c
@@ -12,6 +12,7 @@
 #include <common.h>
 #include <command.h>
 #include <i2c.h>
+#include <asm/mach-types.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c
index 17e6296..16d6947 100644
--- a/board/LaCie/netspace_v2/netspace_v2.c
+++ b/board/LaCie/netspace_v2/netspace_v2.c
@@ -11,6 +11,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <asm/mach-types.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
diff --git a/board/Marvell/aspenite/aspenite.c b/board/Marvell/aspenite/aspenite.c
index 24ee679..0ef63b7 100644
--- a/board/Marvell/aspenite/aspenite.c
+++ b/board/Marvell/aspenite/aspenite.c
@@ -9,6 +9,7 @@
 
 #include <common.h>
 #include <mvmfp.h>
+#include <asm/mach-types.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/mfp.h>
 #include <asm/arch/armada100.h>
diff --git a/board/Marvell/db-88f6820-amc/MAINTAINERS b/board/Marvell/db-88f6820-amc/MAINTAINERS
new file mode 100644
index 0000000..abf5b7e
--- /dev/null
+++ b/board/Marvell/db-88f6820-amc/MAINTAINERS
@@ -0,0 +1,6 @@
+DB_88F6820_AMC BOARD
+M:	Chris Packham <chris.packham@alliedtelesis.co.nz>
+S:	Maintained
+F:	board/Marvell/db-88f6820-amc/
+F:	include/configs/db-88f6820-amc.h
+F:	configs/db-88f6820-amc_defconfig
diff --git a/board/Marvell/db-88f6820-amc/Makefile b/board/Marvell/db-88f6820-amc/Makefile
new file mode 100644
index 0000000..79e1a75
--- /dev/null
+++ b/board/Marvell/db-88f6820-amc/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= db-88f6820-amc.o
diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
new file mode 100644
index 0000000..40fa599
--- /dev/null
+++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ETH_PHY_CTRL_REG		0
+#define ETH_PHY_CTRL_POWER_DOWN_BIT	11
+#define ETH_PHY_CTRL_POWER_DOWN_MASK	(1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2016_T1.0.eng_drop_v10"
+ */
+#define DB_AMC_88F68XX_GPP_OUT_ENA_LOW					\
+	(~(BIT(29)))
+#define DB_AMC_88F68XX_GPP_OUT_ENA_MID					\
+	(~(BIT(12) | BIT(17) | BIT(18) | BIT(20) | BIT(21)))
+#define DB_AMC_88F68XX_GPP_OUT_VAL_LOW	(BIT(29))
+#define DB_AMC_88F68XX_GPP_OUT_VAL_MID	0x0
+#define DB_AMC_88F68XX_GPP_OUT_VAL_HIGH	0x0
+#define DB_AMC_88F68XX_GPP_POL_LOW	0x0
+#define DB_AMC_88F68XX_GPP_POL_MID	0x0
+
+static struct serdes_map board_serdes_map[] = {
+	{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+	{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+	*serdes_map_array = board_serdes_map;
+	*count = ARRAY_SIZE(board_serdes_map);
+	return 0;
+}
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct hws_topology_map board_topology_map = {
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+	{ { { {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0} },
+	    SPEED_BIN_DDR_1866L,	/* speed_bin */
+	    BUS_WIDTH_8,		/* memory_width */
+	    MEM_4G,			/* mem_size */
+	    DDR_FREQ_800,		/* frequency */
+	    0, 0,			/* cas_l cas_wl */
+	    HWS_TEMP_LOW,		/* temperature */
+	    HWS_TIM_DEFAULT} },		/* timing */
+	5,				/* Num Of Bus Per Interface*/
+	BUS_MASK_32BIT			/* Busses mask */
+};
+
+struct hws_topology_map *ddr3_get_topology_map(void)
+{
+	/* Return the board topology as defined in the board code */
+	return &board_topology_map;
+}
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+	writel(0x55066011, MVEBU_MPP_BASE + 0x08);
+	writel(0x05055550, MVEBU_MPP_BASE + 0x0c);
+	writel(0x05055555, MVEBU_MPP_BASE + 0x10);
+	writel(0x01106565, MVEBU_MPP_BASE + 0x14);
+	writel(0x40000000, MVEBU_MPP_BASE + 0x18);
+	writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
+
+	/* Set GPP Out value */
+	writel(DB_AMC_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(DB_AMC_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(DB_AMC_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(DB_AMC_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(DB_AMC_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(DB_AMC_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Marvell DB-88F6820-AMC\n");
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis); /* Built in controller(s) come first */
+	return pci_eth_init(bis);
+}
diff --git a/board/Marvell/db-88f6820-amc/kwbimage.cfg b/board/Marvell/db-88f6820-amc/kwbimage.cfg
new file mode 100644
index 0000000..1f748db
--- /dev/null
+++ b/board/Marvell/db-88f6820-amc/kwbimage.cfg
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
index e700781..a1974cb 100644
--- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
+++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -90,7 +90,8 @@ static struct hws_topology_map board_topology_map = {
 	    MEM_4G,			/* mem_size */
 	    DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_l cas_wl */
-	    HWS_TEMP_LOW} },		/* temperature */
+	    HWS_TEMP_LOW,		/* temperature */
+	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per Interface*/
 	BUS_MASK_32BIT			/* Busses mask */
 };
diff --git a/board/Marvell/gplugd/MAINTAINERS b/board/Marvell/gplugd/MAINTAINERS
index 320bc09..197c6a0 100644
--- a/board/Marvell/gplugd/MAINTAINERS
+++ b/board/Marvell/gplugd/MAINTAINERS
@@ -1,5 +1,5 @@
 GPLUGD BOARD
-M:	Ajay Bhargav <ajay.bhargav@einfochips.com>
+M:	Ajay Bhargav <contact@8051projects.net>
 S:	Maintained
 F:	board/Marvell/gplugd/
 F:	include/configs/gplugd.h
diff --git a/board/Marvell/gplugd/Makefile b/board/Marvell/gplugd/Makefile
index b384578..8929da5 100644
--- a/board/Marvell/gplugd/Makefile
+++ b/board/Marvell/gplugd/Makefile
@@ -1,7 +1,7 @@
 #
 # (C) Copyright 2011
 # eInfochips Ltd. <www.einfochips.com>
-# Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+# Written-by: Ajay Bhargav <contact@8051projects.net>
 #
 # Based on Aspenite:
 # (C) Copyright 2010
diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
index 0e8ebcc..05ce98b 100644
--- a/board/Marvell/gplugd/gplugd.c
+++ b/board/Marvell/gplugd/gplugd.c
@@ -1,7 +1,7 @@
 /*
  * (C) Copyright 2011
  * eInfochips Ltd. <www.einfochips.com>
- * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
  *
  * Based on Aspenite:
  * (C) Copyright 2010
@@ -19,6 +19,7 @@
 #include <asm/arch/armada100.h>
 #include <asm/gpio.h>
 #include <miiphy.h>
+#include <asm/mach-types.h>
 
 #ifdef CONFIG_ARMADA100_FEC
 #include <net.h>
@@ -76,7 +77,7 @@ int board_init(void)
 		(struct armd1apb2_registers *)ARMD1_APBC2_BASE;
 
 	/* arch number of Board */
-	gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
+	gd->bd->bi_arch_number = MACH_TYPE_GPLUGD;
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
 	/* Assert PHY_RST# */
diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c
index b0d5f1e..af0c491 100644
--- a/board/Marvell/guruplug/guruplug.c
+++ b/board/Marvell/guruplug/guruplug.c
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <miiphy.h>
+#include <asm/mach-types.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
diff --git a/board/Marvell/mvebu_armada-37xx/MAINTAINERS b/board/Marvell/mvebu_armada-37xx/MAINTAINERS
new file mode 100644
index 0000000..52a3869
--- /dev/null
+++ b/board/Marvell/mvebu_armada-37xx/MAINTAINERS
@@ -0,0 +1,6 @@
+MVEBU_DB_88F3720 BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/Marvell/mvebu_armada-37xx/
+F:	include/configs/mvebu_armada-37xx.h
+F:	configs/mvebu_db-88f3720_defconfig
diff --git a/board/Marvell/mvebu_armada-37xx/Makefile b/board/Marvell/mvebu_armada-37xx/Makefile
new file mode 100644
index 0000000..ed39738
--- /dev/null
+++ b/board/Marvell/mvebu_armada-37xx/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= board.o
diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c
new file mode 100644
index 0000000..8dc1f46
--- /dev/null
+++ b/board/Marvell/mvebu_armada-37xx/board.c
@@ -0,0 +1,258 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <phy.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* IO expander I2C device */
+#define I2C_IO_EXP_ADDR		0x22
+#define I2C_IO_CFG_REG_0	0x6
+#define I2C_IO_DATA_OUT_REG_0	0x2
+#define I2C_IO_REG_0_SATA_OFF	2
+#define I2C_IO_REG_0_USB_H_OFF	1
+
+/* The pin control values are the same for DB and Espressobin */
+#define PINCTRL_NB_REG_VALUE	0x000173fa
+#define PINCTRL_SB_REG_VALUE	0x00007a23
+
+/* Ethernet switch registers */
+/* SMI addresses for multi-chip mode */
+#define MVEBU_PORT_CTRL_SMI_ADDR(p)	(16 + (p))
+#define MVEBU_SW_G2_SMI_ADDR		(28)
+
+/* Multi-chip mode */
+#define MVEBU_SW_SMI_DATA_REG		(1)
+#define MVEBU_SW_SMI_CMD_REG		(0)
+ #define SW_SMI_CMD_REG_ADDR_OFF	0
+ #define SW_SMI_CMD_DEV_ADDR_OFF	5
+ #define SW_SMI_CMD_SMI_OP_OFF		10
+ #define SW_SMI_CMD_SMI_MODE_OFF	12
+ #define SW_SMI_CMD_SMI_BUSY_OFF	15
+
+/* Single-chip mode */
+/* Switch Port Registers */
+#define MVEBU_SW_LINK_CTRL_REG		(1)
+#define MVEBU_SW_PORT_CTRL_REG		(4)
+
+/* Global 2 Registers */
+#define MVEBU_G2_SMI_PHY_CMD_REG	(24)
+#define MVEBU_G2_SMI_PHY_DATA_REG	(25)
+
+int board_early_init_f(void)
+{
+	const void *blob = gd->fdt_blob;
+	const char *bank_name;
+	const char *compat = "marvell,armada-3700-pinctl";
+	int off, len;
+	void __iomem *addr;
+
+	/* FIXME
+	 * Temporary WA for setting correct pin control values
+	 * until the real pin control driver is awailable.
+	 */
+	off = fdt_node_offset_by_compatible(blob, -1, compat);
+	while (off != -FDT_ERR_NOTFOUND) {
+		bank_name = fdt_getprop(blob, off, "bank-name", &len);
+		addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(
+				blob, off, "reg", 0, NULL, true);
+		if (!strncmp(bank_name, "armada-3700-nb", len))
+			writel(PINCTRL_NB_REG_VALUE, addr);
+		else if (!strncmp(bank_name, "armada-3700-sb", len))
+			writel(PINCTRL_SB_REG_VALUE, addr);
+
+		off = fdt_node_offset_by_compatible(blob, off, compat);
+	}
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+/* Board specific AHCI / SATA enable code */
+int board_ahci_enable(void)
+{
+	struct udevice *dev;
+	int ret;
+	u8 buf[8];
+
+	/* Only DB requres this configuration */
+	if (!of_machine_is_compatible("marvell,armada-3720-db"))
+		return 0;
+
+	/* Configure IO exander PCA9555: 7bit address 0x22 */
+	ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
+	if (ret) {
+		printf("Cannot find PCA9555: %d\n", ret);
+		return 0;
+	}
+
+	ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to read IO expander value via I2C\n");
+		return -EIO;
+	}
+
+	/*
+	 * Enable SATA power via IO expander connected via I2C by setting
+	 * the corresponding bit to output mode to enable power for SATA
+	 */
+	buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
+	ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to set IO expander via I2C\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/* Board specific xHCI enable code */
+int board_xhci_enable(void)
+{
+	struct udevice *dev;
+	int ret;
+	u8 buf[8];
+
+	/* Only DB requres this configuration */
+	if (!of_machine_is_compatible("marvell,armada-3720-db"))
+		return 0;
+
+	/* Configure IO exander PCA9555: 7bit address 0x22 */
+	ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
+	if (ret) {
+		printf("Cannot find PCA9555: %d\n", ret);
+		return 0;
+	}
+
+	printf("Enable USB VBUS\n");
+
+	/*
+	 * Read configuration (direction) and set VBUS pin as output
+	 * (reset pin = output)
+	 */
+	ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to read IO expander value via I2C\n");
+		return -EIO;
+	}
+	buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
+	ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to set IO expander via I2C\n");
+		return -EIO;
+	}
+
+	/* Read VBUS output value and disable it */
+	ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to read IO expander value via I2C\n");
+		return -EIO;
+	}
+	buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
+	ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to set IO expander via I2C\n");
+		return -EIO;
+	}
+
+	/*
+	 * Required delay for configuration to settle - must wait for
+	 * power on port is disabled in case VBUS signal was high,
+	 * required 3 seconds delay to let VBUS signal fully settle down
+	 */
+	mdelay(3000);
+
+	/* Enable VBUS power: Set output value of VBUS pin as enabled */
+	buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
+	ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+	if (ret) {
+		printf("Failed to set IO expander via I2C\n");
+		return -EIO;
+	}
+
+	mdelay(500); /* required delay to let output value settle */
+
+	return 0;
+}
+
+/* Helper function for accessing switch devices in multi-chip connection mode */
+static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr,
+				     int smi_addr, int reg, u16 value)
+{
+	u16 smi_cmd = 0;
+
+	if (bus->write(bus, dev_smi_addr, 0,
+		       MVEBU_SW_SMI_DATA_REG, value) != 0) {
+		printf("Error writing to the PHY addr=%02x reg=%02x\n",
+		       smi_addr, reg);
+		return -EFAULT;
+	}
+
+	smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) |
+		  (1 << SW_SMI_CMD_SMI_MODE_OFF) |
+		  (1 << SW_SMI_CMD_SMI_OP_OFF) |
+		  (smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) |
+		  (reg << SW_SMI_CMD_REG_ADDR_OFF);
+	if (bus->write(bus, dev_smi_addr, 0,
+		       MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) {
+		printf("Error writing to the PHY addr=%02x reg=%02x\n",
+		       smi_addr, reg);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+/* Bring-up board-specific network stuff */
+int board_network_enable(struct mii_dev *bus)
+{
+	if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
+		return 0;
+
+	/*
+	 * FIXME: remove this code once Topaz driver gets available
+	 * A3720 Community Board Only
+	 * Configure Topaz switch (88E6341)
+	 * Set port 0,1,2,3 to forwarding Mode (through Switch Port registers)
+	 */
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
+				  MVEBU_SW_PORT_CTRL_REG, 0x7f);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
+				  MVEBU_SW_PORT_CTRL_REG, 0x7f);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
+				  MVEBU_SW_PORT_CTRL_REG, 0x7f);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
+				  MVEBU_SW_PORT_CTRL_REG, 0x7f);
+
+	/* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */
+	mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
+				  MVEBU_SW_LINK_CTRL_REG, 0xe002);
+
+	/* Power up PHY 1, 2, 3 (through Global 2 registers) */
+	mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
+				  MVEBU_G2_SMI_PHY_DATA_REG, 0x1140);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
+				  MVEBU_G2_SMI_PHY_CMD_REG, 0x9620);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
+				  MVEBU_G2_SMI_PHY_CMD_REG, 0x9640);
+	mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
+				  MVEBU_G2_SMI_PHY_CMD_REG, 0x9660);
+
+	return 0;
+}
diff --git a/board/Marvell/mvebu_armada-8k/MAINTAINERS b/board/Marvell/mvebu_armada-8k/MAINTAINERS
new file mode 100644
index 0000000..e0b965d
--- /dev/null
+++ b/board/Marvell/mvebu_armada-8k/MAINTAINERS
@@ -0,0 +1,7 @@
+MVEBU_ARMADA_8K BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/Marvell/mvebu_armada-8k/
+F:	include/configs/mvebu_armada-8k.h
+F:	configs/mvebu_db-88f7040_defconfig
+F:	configs/mvebu_db-88f8040_defconfig
diff --git a/board/Marvell/mvebu_armada-8k/Makefile b/board/Marvell/mvebu_armada-8k/Makefile
new file mode 100644
index 0000000..ed39738
--- /dev/null
+++ b/board/Marvell/mvebu_armada-8k/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= board.o
diff --git a/board/Marvell/mvebu_armada-8k/board.c b/board/Marvell/mvebu_armada-8k/board.c
new file mode 100644
index 0000000..7d1b5d9
--- /dev/null
+++ b/board/Marvell/mvebu_armada-8k/board.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Information specific to the DB-88F7040 eval board. We strive to use
+ * DT for such platform specfic configurations. At some point, this
+ * might be removed here and implemented via DT.
+ */
+/* IO expander I2C device */
+#define I2C_IO_EXP_ADDR		0x21
+#define I2C_IO_CFG_REG_0	0x6
+#define I2C_IO_DATA_OUT_REG_0	0x2
+/* VBus enable */
+#define I2C_IO_REG_0_USB_H0_OFF	0
+#define I2C_IO_REG_0_USB_H1_OFF	1
+#define I2C_IO_REG_VBUS		((1 << I2C_IO_REG_0_USB_H0_OFF) | \
+				 (1 << I2C_IO_REG_0_USB_H1_OFF))
+/* Current limit */
+#define I2C_IO_REG_0_USB_H0_CL	4
+#define I2C_IO_REG_0_USB_H1_CL	5
+#define I2C_IO_REG_CL		((1 << I2C_IO_REG_0_USB_H0_CL) | \
+				 (1 << I2C_IO_REG_0_USB_H1_CL))
+
+static int usb_enabled = 0;
+
+/* Board specific xHCI dis-/enable code */
+
+/*
+ * Set USB VBUS signals (via I2C IO expander/GPIO) as output and set
+ * output value as disabled
+ *
+ * Set USB Current Limit signals (via I2C IO expander/GPIO) as output
+ * and set output value as enabled
+ */
+int board_xhci_config(void)
+{
+	struct udevice *dev;
+	int ret;
+	u8 buf[8];
+
+	if (of_machine_is_compatible("marvell,armada7040-db")) {
+		/* Configure IO exander PCA9555: 7bit address 0x21 */
+		ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
+		if (ret) {
+			printf("Cannot find PCA9555: %d\n", ret);
+			return 0;
+		}
+
+		/*
+		 * Read configuration (direction) and set VBUS pin as output
+		 * (reset pin = output)
+		 */
+		ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
+		if (ret) {
+			printf("Failed to read IO expander value via I2C\n");
+			return -EIO;
+		}
+		buf[0] &= ~I2C_IO_REG_VBUS;
+		buf[0] &= ~I2C_IO_REG_CL;
+		ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
+		if (ret) {
+			printf("Failed to set IO expander via I2C\n");
+			return -EIO;
+		}
+
+		/* Read output value and configure it */
+		ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+		if (ret) {
+			printf("Failed to read IO expander value via I2C\n");
+			return -EIO;
+		}
+		buf[0] &= ~I2C_IO_REG_VBUS;
+		buf[0] |= I2C_IO_REG_CL;
+		ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+		if (ret) {
+			printf("Failed to set IO expander via I2C\n");
+			return -EIO;
+		}
+
+		mdelay(500); /* required delay to let output value settle */
+	}
+
+	return 0;
+}
+
+int board_xhci_enable(void)
+{
+	struct udevice *dev;
+	int ret;
+	u8 buf[8];
+
+	if (of_machine_is_compatible("marvell,armada7040-db")) {
+		/*
+		 * This function enables all USB ports simultaniously,
+		 * it only needs to get called once
+		 */
+		if (usb_enabled)
+			return 0;
+
+		/* Configure IO exander PCA9555: 7bit address 0x21 */
+		ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
+		if (ret) {
+			printf("Cannot find PCA9555: %d\n", ret);
+			return 0;
+		}
+
+		/* Read VBUS output value */
+		ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+		if (ret) {
+			printf("Failed to read IO expander value via I2C\n");
+			return -EIO;
+		}
+
+		/* Enable VBUS power: Set output value of VBUS pin as enabled */
+		buf[0] |= I2C_IO_REG_VBUS;
+		ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
+		if (ret) {
+			printf("Failed to set IO expander via I2C\n");
+			return -EIO;
+		}
+
+		mdelay(500); /* required delay to let output value settle */
+		usb_enabled = 1;
+	}
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	/* Nothing to do (yet), perhaps later some pin-muxing etc */
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	/* Pre-configure the USB ports (overcurrent, VBus) */
+	board_xhci_config();
+
+	return 0;
+}
diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c
index 17a6560..f6cffc8 100644
--- a/board/Marvell/openrd/openrd.c
+++ b/board/Marvell/openrd/openrd.c
@@ -13,6 +13,7 @@
 
 #include <common.h>
 #include <miiphy.h>
+#include <asm/mach-types.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c
index 8907fb5..c7dfaa2 100644
--- a/board/Marvell/sheevaplug/sheevaplug.c
+++ b/board/Marvell/sheevaplug/sheevaplug.c
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <miiphy.h>
+#include <asm/mach-types.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c
index 83ab1bc..f444c16 100644
--- a/board/Seagate/dockstar/dockstar.c
+++ b/board/Seagate/dockstar/dockstar.c
@@ -15,6 +15,7 @@
 #include <asm/arch/mpp.h>
 #include <asm/arch/cpu.h>
 #include <asm/io.h>
+#include <asm/mach-types.h>
 #include "dockstar.h"
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c
index 1f4fb92..5d0a424 100644
--- a/board/Seagate/goflexhome/goflexhome.c
+++ b/board/Seagate/goflexhome/goflexhome.c
@@ -14,6 +14,7 @@
 
 #include <common.h>
 #include <miiphy.h>
+#include <asm/mach-types.h>
 #include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include <asm/arch/cpu.h>
diff --git a/board/Seagate/nas220/nas220.c b/board/Seagate/nas220/nas220.c
index d9a0627..18c2895 100644
--- a/board/Seagate/nas220/nas220.c
+++ b/board/Seagate/nas220/nas220.c
@@ -11,6 +11,7 @@
 
 #include <common.h>
 #include <miiphy.h>
+#include <asm/mach-types.h>
 #include <asm/arch/soc.h>
 #include <asm/arch/mpp.h>
 #include <asm/arch/cpu.h>
@@ -75,7 +76,7 @@ int board_init(void)
 	/*
 	 * arch number of board
 	 */
-	gd->bd->bi_arch_number = MACH_TYPE_NAS220;
+	gd->bd->bi_arch_number = MACH_TYPE_RD88F6192_NAS;
 
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
diff --git a/board/Synology/ds109/Kconfig b/board/Synology/ds109/Kconfig
new file mode 100644
index 0000000..a7c75ae
--- /dev/null
+++ b/board/Synology/ds109/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DS109
+
+config SYS_BOARD
+	default "ds109"
+
+config SYS_VENDOR
+	default "Synology"
+
+config SYS_CONFIG_NAME
+	default "ds109"
+
+endif
diff --git a/board/Synology/ds109/MAINTAINERS b/board/Synology/ds109/MAINTAINERS
new file mode 100644
index 0000000..8783fdb
--- /dev/null
+++ b/board/Synology/ds109/MAINTAINERS
@@ -0,0 +1,6 @@
+DS109 BOARD
+M:	Walter Schweizer <swwa@users.sourceforge.net>
+S:	Maintained
+F:	board/Synology/ds109
+F:	configs/ds109_defconfig
+F:	include/configs/ds109.h
diff --git a/board/Synology/ds109/Makefile b/board/Synology/ds109/Makefile
new file mode 100644
index 0000000..eeeb64d
--- /dev/null
+++ b/board/Synology/ds109/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= ds109.o
diff --git a/board/Synology/ds109/ds109.c b/board/Synology/ds109/ds109.c
new file mode 100644
index 0000000..0c2f525
--- /dev/null
+++ b/board/Synology/ds109/ds109.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/setup.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include "ds109.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the below configuration configures mainly initial LED status
+	 */
+	mvebu_config_gpio(DS109_OE_VAL_LOW,
+			  DS109_OE_VAL_HIGH,
+			  DS109_OE_LOW, DS109_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	static const u32 kwmpp_config[] = {
+		MPP0_SPI_SCn,		/* SPI Flash */
+		MPP1_SPI_MOSI,
+		MPP2_SPI_SCK,
+		MPP3_SPI_MISO,
+		MPP4_GPIO,
+		MPP5_GPO,
+		MPP6_SYSRST_OUTn,	/* Reset signal */
+		MPP7_GPO,
+		MPP8_TW_SDA,		/* I2C */
+		MPP9_TW_SCK,		/* I2C */
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_GPO,
+		MPP13_UART1_TXD,
+		MPP14_UART1_RXD,
+		MPP15_GPIO,
+		MPP16_GPIO,
+		MPP17_GPIO,
+		MPP18_GPO,
+		MPP19_GPO,
+		MPP20_SATA1_ACTn,
+		MPP21_SATA0_ACTn,
+		MPP22_GPIO,		/* HDD2 FAIL LED */
+		MPP23_GPIO,		/* HDD1 FAIL LED */
+		MPP24_GPIO,
+		MPP25_GPIO,
+		MPP26_GPIO,
+		MPP27_GPIO,
+		MPP28_GPIO,
+		MPP29_GPIO,
+		MPP30_GPIO,
+		MPP31_GPIO,		/* HDD2 */
+		MPP32_GPIO,		/* FAN A */
+		MPP33_GPIO,		/* FAN B */
+		MPP34_GPIO,		/* FAN C */
+		MPP35_GPIO,		/* FAN SENSE */
+		MPP36_GPIO,
+		MPP37_GPIO,
+		MPP38_GPIO,
+		MPP39_GPIO,
+		MPP40_GPIO,
+		MPP41_GPIO,
+		MPP42_GPIO,
+		MPP43_GPIO,
+		MPP44_GPIO,
+		MPP45_GPIO,
+		MPP46_GPIO,
+		MPP47_GPIO,
+		MPP48_GPIO,
+		MPP49_GPIO,
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+/* Synology reset uses UART */
+#include <ns16550.h>
+#define SOFTWARE_SHUTDOWN   0x31
+#define SOFTWARE_REBOOT     0x43
+#define CONFIG_SYS_NS16550_COM2		KW_UART1_BASE
+void reset_misc(void)
+{
+	int b_d;
+	printf("Synology reset...");
+	udelay(50000);
+
+	b_d = ns16550_calc_divisor((NS16550_t)CONFIG_SYS_NS16550_COM2,
+		CONFIG_SYS_NS16550_CLK, 9600);
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM2, b_d);
+	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, SOFTWARE_REBOOT);
+}
+
+/* Support old kernels */
+void setup_board_tags(struct tag **in_params)
+{
+	unsigned int boardId;
+	struct tag *params;
+	struct tag_mv_uboot *t;
+	int i;
+
+	printf("Synology board tags...");
+	params = *in_params;
+	t = (struct tag_mv_uboot *)&params->u;
+
+	t->uboot_version = VER_NUM;
+
+	boardId = SYNO_DS109_ID;
+	t->uboot_version |= boardId;
+
+	t->tclk = CONFIG_SYS_TCLK;
+	t->sysclk = CONFIG_SYS_TCLK*2;
+
+	t->isusbhost = 1;
+	for (i = 0; i < 4; i++)	{
+		memset(t->macaddr[i], 0, sizeof(t->macaddr[i]));
+		t->mtu[i] = 0;
+	}
+
+	params->hdr.tag = ATAG_MV_UBOOT;
+	params->hdr.size = tag_size(tag_mv_uboot);
+	params = tag_next(params);
+	*in_params = params;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+	u16 reg;
+	u16 devadr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
+		printf("Error: 88E1116 could not read PHY dev address\n");
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Synology/ds109/ds109.h b/board/Synology/ds109/ds109.h
new file mode 100644
index 0000000..a57cda7
--- /dev/null
+++ b/board/Synology/ds109/ds109.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DS109_H
+#define __DS109_H
+
+#define DS109_OE_LOW			(0)
+#define DS109_OE_HIGH			(0)
+#define DS109_OE_VAL_LOW		((1 << 22)|(1 << 23))
+#define DS109_OE_VAL_HIGH		((1 << 1)|1)
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_MAC_CTRL2_REG		21
+
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+/* Marvell uboot parameters */
+#define ATAG_MV_UBOOT 0x41000403
+#define VER_NUM       0x03040400 /* 3.4.4 */
+#define BOARD_ID_BASE 0x0
+#define SYNO_DS109_ID (BOARD_ID_BASE+0x15)
+
+struct tag_mv_uboot {
+	u32 uboot_version;
+	u32 tclk;
+	u32 sysclk;
+	u32 isusbhost;
+	char macaddr[4][6];
+	u16 mtu[4];
+	u32 fw_image_base;
+	u32 fw_image_size;
+};
+
+#endif /* __DS109_H */
diff --git a/board/Synology/ds109/kwbimage.cfg b/board/Synology/ds109/kwbimage.cfg
new file mode 100644
index 0000000..d544af5
--- /dev/null
+++ b/board/Synology/ds109/kwbimage.cfg
@@ -0,0 +1,152 @@
+#
+# (C) Copyright 2011
+# Jason Cooper <u-boot@lakedaemon.net>
+#
+# Based on work by:
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Siddarth Gore <gores@marvell.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0/1 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+DATA 0xFFD20134 0xbbbbbbbb
+DATA 0xFFD20138 0x00bbbbbb
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x39543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000833	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000d	#  DDR Address Control
+# bit1-0:   01, Cs0width=x8
+# bit3-2:   10, Cs0size=1Gb
+# bit5-4:   01, Cs1width=x8
+# bit7-6:   10, Cs1size=1Gb
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000042	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    0,  DDR drive strenght normal
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F1FF	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+
+DATA 0xFFD01510 0x20000000	# CS[2]n Base address to 256Mb
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD01518 0x30000000	# CS[3]n Base address to 256Mb
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x003C0000	#  DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000F80F	# CPU ODT Control
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/Synology/ds109/openocd.cfg b/board/Synology/ds109/openocd.cfg
new file mode 100644
index 0000000..baa512a
--- /dev/null
+++ b/board/Synology/ds109/openocd.cfg
@@ -0,0 +1,115 @@
+# Synology DS109
+
+interface ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x000b
+ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
+ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040
+
+adapter_khz 2000
+
+# length of reset signal: [ms]
+adapter_nsrst_assert_width 1000
+
+# don't talk to JTAG after reset for: [ms]
+adapter_nsrst_delay 200
+
+source [find target/feroceon.cfg]
+
+reset_config trst_and_srst srst_nogate
+
+proc ds109_init { } {
+
+	# We need to assert DBGRQ while holding nSRST down.
+	# However DBGACK will be set only when nSRST is released.
+	# Furthermore, the JTAG interface doesn't respond at all when
+	# the CPU is in the WFI (wait for interrupts) state, so it is
+	# possible that initial tap examination failed.  So let's
+	# re-examine the target again here when nSRST is asserted which
+	# should then succeed.
+	jtag_reset 0 1
+	feroceon.cpu arp_examine
+	halt 0
+	jtag_reset 0 0
+	wait_halt
+	#reset run
+	#soft_reset_halt
+
+	arm mcr 15 0 0 1 0 0x00052078
+
+	mww 0xD00100e0 0x1b1b1b9b ;#
+	mww 0xD0020134 0xbbbbbbbb ;#
+	mww 0xD0020138 0x00bbbbbb ;#
+	mww 0xD0001400 0x43000C30 ;#  DDR SDRAM Configuration Register
+	mww 0xD0001404 0x39743000 ;#  Dunit Control Low Register
+	mww 0xD0001408 0x22125551 ;#  DDR SDRAM Timing (Low) Register
+	mww 0xD000140C 0x00000833 ;#  DDR SDRAM Timing (High) Register
+	mww 0xD0001410 0x0000000d ;#  DDR SDRAM Address Control Register
+	mww 0xD0001414 0x00000000 ;#  DDR SDRAM Open Pages Control Register
+	mww 0xD0001418 0x00000000 ;#  DDR SDRAM Operation Register
+	mww 0xD000141C 0x00000C62 ;#  DDR SDRAM Mode Register
+	mww 0xD0001420 0x00000042 ;#  DDR SDRAM Extended Mode Register
+	mww 0xD0001424 0x0000F1FF ;#  Dunit Control High Register
+	mww 0xD0001428 0x00085520 ;#  Dunit Control High Register
+	mww 0xD000147c 0x00008552 ;#  Dunit Control High Register
+	mww 0xD0001500 0x00000000 ;#
+	mww 0xD0001504 0x07FFFFF1 ;#  CS0n Size Register
+	mww 0xD0001508 0x10000000 ;#  CS1n Base Register
+	mww 0xD000150C 0x00000000 ;#  CS1n Size Register
+	mww 0xD0001510 0x20000000 ;#
+	mww 0xD0001514 0x00000000 ;#  CS2n Size Register
+	mww 0xD000151C 0x00000000 ;#  CS3n Size Register
+	mww 0xD0001494 0x003C0000 ;#  DDR2 SDRAM ODT Control (Low) Register
+	mww 0xD0001498 0x00000000 ;#  DDR2 SDRAM ODT Control (High) REgister
+	mww 0xD000149C 0x0000F80F ;#  DDR2 Dunit ODT Control Register
+	mww 0xD0001480 0x00000001 ;#  DDR SDRAM Initialization Control Register
+	mww 0xD0020204 0x00000000 ;#  Main IRQ Interrupt Mask Register
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+	mww 0xD0020204 0x00000000 ;#              "
+
+	mww 0xD0010000 0x01111111 ;#  MPP  0 to 7
+	mww 0xD0010004 0x11113322 ;#  MPP  8 to 15
+	mww 0xD0010008 0x00001111 ;#  MPP 16 to 23
+}
+
+proc ds109_load { } {
+	# load u-Boot into RAM and execute it
+	ds109_init
+	load_image u-boot.bin 0x00600000 bin
+	resume 0x00600000
+}
diff --git a/board/a3m071/Kconfig b/board/a3m071/Kconfig
deleted file mode 100644
index 444c450..0000000
--- a/board/a3m071/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_A3M071
-
-config SYS_BOARD
-	default "a3m071"
-
-config SYS_CONFIG_NAME
-	default "a3m071"
-
-endif
diff --git a/board/a3m071/MAINTAINERS b/board/a3m071/MAINTAINERS
deleted file mode 100644
index 975107d..0000000
--- a/board/a3m071/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-A3M071 BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/a3m071/
-F:	include/configs/a3m071.h
-F:	configs/a3m071_defconfig
-F:	configs/a4m2k_defconfig
diff --git a/board/a3m071/Makefile b/board/a3m071/Makefile
deleted file mode 100644
index 4e31e33..0000000
--- a/board/a3m071/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= a3m071.o
diff --git a/board/a3m071/README b/board/a3m071/README
deleted file mode 100644
index 112c47b..0000000
--- a/board/a3m071/README
+++ /dev/null
@@ -1,80 +0,0 @@
-------------------------------------------------------------------------
-A3M071 board support
-------------------------------------------------------------------------
-
-
-SPL NOR flash support:
-----------------------
-To boot fast into the OS (Linux), this board port integrates the SPL
-framework. This means, that a special, stripped-down version of
-U-Boot runs in the beginning. In the case of the A3M071 board, this
-SPL U-Boot version is less than 16 KiB big. This SPL U-Boot can either
-boot the OS (Linux) or a "real", full-blown U-Boot. This detection
-on whether to boot Linux or U-Boot is done by using the "boot_os"
-environment variable. If "boot_os" is set to "yes", Linux will be
-loaded and booted from the SPL U-Boot version. Otherwise, the
-full-blown U-Boot version will be loaded and run.
-
-Enabling Linux booting:
------------------------
-From U-Boot:
-=> setenv boot_os yes
-=> saveenv
-
-From Linux:
-$ fw_setenv boot_os yes
-
-Enabling U-Boot booting:
-------------------------
-From U-Boot:
-=> setenv boot_os no
-=> saveenv
-
-From Linux:
-$ fw_setenv boot_os no
-
-
-Preparing Linux image(s) for booting from SPL U-Boot:
------------------------------------------------------
-To boot the Linux kernel from the SPL, the DT blob (fdt) needs to get
-prepard/patched first. U-Boot usually inserts some dynamic values into
-the DT binary (blob), e.g. autodetected memory size, MAC addresses,
-clocks speeds etc. To generate this patched DT blob, you can use
-the following command:
-
-1. Load fdt blob to SDRAM:
-=> tftp 1800000 a3m071/a3m071.dtb
-
-2. Set bootargs as desired for Linux booting (e.g. flash_mtd):
-=> run mtdargs addip2 addtty
-
-3. Use "fdt" commands to patch the DT blob:
-=> fdt addr 1800000
-=> fdt boardsetup
-=> fdt chosen
-
-4. Display patched DT blob (optional):
-=> fdt print
-
-5. Save fdt to NOR flash:
-=> erase fc180000 fc07ffff
-=> cp.b 1800000 fc180000 10000
-
-All this can be integrated into an environment command:
-=> setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip addtty; \
-	fdt addr 1800000;fdt boardsetup;fdt chosen;erase fc180000 fc07ffff; \
-	cp.b 1800000 fc180000 10000'
-=> saveenv
-
-After this, only "run upd_fdt" needs to get called to load, patch
-and save the DT blob into NOR flash.
-
-Additionally, the Linux kernel image has to be saved uncompressed in
-its uImage file (and not gzip compressed). This can be done with this
-command:
-
-$ mkimage -A ppc -O linux -T kernel -C none -a 0 -e 0 \
-	-n "Linux Kernel Image" -d vmlinux.bin uImage.uncompressed
-
-------------------------------------------------------------------------
-Stefan Roese, 2012-08-23
diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c
deleted file mode 100644
index 55d0bc8..0000000
--- a/board/a3m071/a3m071.c
+++ /dev/null
@@ -1,477 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2006
- * MicroSys GmbH
- *
- * Copyright 2012-2013 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <miiphy.h>
-#include <linux/compiler.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_A4M2K
-#include "is46r16320d.h"
-#else
-#include "mt46v16m16-75.h"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if !defined(CONFIG_SYS_RAMBOOT) && \
-	(defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
-static void sdram_start(int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-	long control = SDRAM_CONTROL | hi_addr_bit;
-
-	/* unlock mode register */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
-
-	/* precharge all banks */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
-
-#ifdef SDRAM_DDR
-	/* set mode register: extended mode */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
-
-	/* set mode register: reset DLL */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
-#endif
-
-	/* precharge all banks */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
-
-	/* auto refresh */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
-
-	/* set mode register */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
-
-	/*
-	 * Wait a short while for the DLL to lock before accessing
-	 * the SDRAM
-	 */
-	udelay(100);
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
- * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
- */
-phys_size_t initdram(int board_type)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-#if !defined(CONFIG_SYS_RAMBOOT) && \
-	(defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);	/* 2GB at 0x0 */
-	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000);	/* disabled */
-
-	/* setup config registers */
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
-
-#ifdef SDRAM_DDR
-	/* set tap delay */
-	out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
-			 0x13 + __builtin_ffs(dramsize >> 20) - 1);
-	} else {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0);	/* disabled */
-	}
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
-	if (dramsize2 >= 0x13)
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	else
-		dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
-		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
-
-	return dramsize + dramsize2;
-}
-
-static void get_revisions(int *failsavelevel, int *digiboardversion,
-	int *fpgaversion)
-{
-	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-	u8 val;
-
-	/* read digitalboard-version from TMR[2..4] */
-	val = 0;
-	val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0;
-	val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
-	val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
-	*digiboardversion = val;
-
-	/*
-	 * A4M2K only supports digiboardversion. No failsavelevel and
-	 * fpgaversion here.
-	 */
-#if !defined(CONFIG_A4M2K)
-	/*
-	 * Figure out failsavelevel
-	 * see ticket dsvk#59
-	 */
-	*failsavelevel = 0;	/* 0=failsave, 1=board ok, 2=fpga ok */
-
-	if (*digiboardversion == 0) {
-		*failsavelevel = 1;	/* digiboard-version ok */
-
-		/* read fpga-version from TMR[5..7] */
-		val = 0;
-		val |= (gpt->gpt5.sr & (1 << (31 - 23))) ? (1) : 0;
-		val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
-		val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
-		*fpgaversion = val;
-
-		if (*fpgaversion == 1)
-			*failsavelevel = 2;	/* fpga-version ok */
-	}
-#endif
-}
-
-/*
- * This function is called from the SPL U-Boot version for
- * early init stuff, that needs to be done for OS (e.g. Linux)
- * booting. Doing it later in the real U-Boot would not work
- * in case that the SPL U-Boot boots Linux directly.
- */
-void spl_board_init(void)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_mmap_ctl *mm =
-		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
-
-#if defined(CONFIG_A4M2K)
-	/* enable CS3 and CS5 (FPGA) */
-	setbits_be32(&mm->ipbi_ws_ctrl, (1 << 19) | (1 << 21));
-#else
-	int digiboardversion;
-	int failsavelevel;
-	int fpgaversion;
-	u32 val;
-
-	get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
-
-	val = in_be32(&mm->ipbi_ws_ctrl);
-
-	/* first clear bits 19..21 (CS3...5) */
-	val &= ~((1 << 19) | (1 << 20) | (1 << 21));
-	if (failsavelevel == 2) {
-		/* FPGA ok */
-		val |= (1 << 19) | (1 << 21);
-	}
-
-	if (failsavelevel >= 1) {
-		/* at least digiboard-version ok */
-		val |= (1 << 20);
-	}
-
-	/* And write new value back to register */
-	out_be32(&mm->ipbi_ws_ctrl, val);
-
-
-	/* Setup pin multiplexing */
-	if (failsavelevel == 2) {
-		/* fpga-version ok */
-#if defined(CONFIG_SYS_GPS_PORT_CONFIG_2)
-		out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_2);
-#endif
-	} else if (failsavelevel == 1) {
-		/* digiboard-version ok - fpga not */
-#if defined(CONFIG_SYS_GPS_PORT_CONFIG_1)
-		out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_1);
-#endif
-	} else {
-		/* full failsave-mode */
-#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
-		out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
-#endif
-	}
-#endif
-
-	/*
-	 * Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see
-	 * ticket #60
-	 *
-	 * MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT)
-	 * set bit 0(msb) to 1
-	 */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_WDOG_GPIO_PIN);
-
-#if defined(CONFIG_A4M2K)
-	/* Setup USB[x] as MPCDiag[0..3] GPIO outputs */
-
-	/* set USB0,6,7,8 (MPCDiag[0..3]) direction to output */
-	gpio->simple_ddr |= 1 << (31 - 15);
-	gpio->simple_ddr |= 1 << (31 - 14);
-	gpio->simple_ddr |= 1 << (31 - 13);
-	gpio->simple_ddr |= 1 << (31 - 12);
-
-	/* enable USB0,6,7,8 (MPCDiag[0..3]) as GPIO */
-	gpio->simple_gpioe |= 1 << (31 - 15);
-	gpio->simple_gpioe |= 1 << (31 - 14);
-	gpio->simple_gpioe |= 1 << (31 - 13);
-	gpio->simple_gpioe |= 1 << (31 - 12);
-
-	/* Setup PSC2[0..2] as STSLED[0..2] GPIO outputs */
-
-	/* set PSC2[0..2] (STSLED[0..2]) direction to output */
-	gpio->simple_ddr |= 1 << (31 - 27);
-	gpio->simple_ddr |= 1 << (31 - 26);
-	gpio->simple_ddr |= 1 << (31 - 25);
-
-	/* enable PSC2[0..2] (STSLED[0..2]) as GPIO */
-	gpio->simple_gpioe |= 1 << (31 - 27);
-	gpio->simple_gpioe |= 1 << (31 - 26);
-	gpio->simple_gpioe |= 1 << (31 - 25);
-
-	/* Setup PSC6[2] as MRST2 self reset GPIO output */
-
-	/* set PSC6[2]/IRDA_TX (MRST2) direction to output */
-	gpio->simple_ddr |= 1 << (31 - 3);
-
-	/* set PSC6[2]/IRDA_TX (MRST2) output as open drain */
-	gpio->simple_ode |= 1 << (31 - 3);
-
-	/* set PSC6[2]/IRDA_TX (MRST2) output as default high */
-	gpio->simple_dvo |= 1 << (31 - 3);
-
-	/* enable PSC6[2]/IRDA_TX (MRST2) as GPIO */
-	gpio->simple_gpioe |= 1 << (31 - 3);
-
-	/* Setup PSC6[3] as HARNSSCD harness code GPIO input */
-
-	/* set PSC6[3]/IR_USB_CLK (HARNSSCD) direction to input */
-	gpio->simple_ddr |= 0 << (31 - 2);
-
-	/* enable PSC6[3]/IR_USB_CLK (HARNSSCD) as GPIO */
-	gpio->simple_gpioe |= 1 << (31 - 2);
-#else
-	/* setup GPIOs for status-leds if needed - see ticket #57 */
-	if (failsavelevel > 0) {
-		/* digiboard-version is OK */
-		/* LED is LOW ACTIVE - so deactivate by set output to 1 */
-		gpio->simple_dvo |= 1 << (31 - 12);
-		gpio->simple_dvo |= 1 << (31 - 13);
-		/* set GPIO direction to output */
-		gpio->simple_ddr |= 1 << (31 - 12);
-		gpio->simple_ddr |= 1 << (31 - 13);
-		/* open drain config is set to "normal output" at reset */
-		/* gpio->simple_ode &=~ ( 1 << (31-12) ); */
-		/* gpio->simple_ode &=~ ( 1 << (31-13) ); */
-		/* enable as GPIO */
-		gpio->simple_gpioe |= 1 << (31 - 12);
-		gpio->simple_gpioe |= 1 << (31 - 13);
-	}
-
-	/* setup fpga irq - see ticket #65 */
-	if (failsavelevel > 1) {
-		/*
-		 * The main irq initialisation is done in interrupts.c
-		 * mpc5xxx_init_irq
-		 */
-		struct mpc5xxx_intr *intr =
-		    (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
-
-		setbits_be32(&intr->ctrl, 0x08C01801);
-
-		/*
-		 * The MBAR+0x0524 Bit 21:23 CSe are ignored here due to the
-		 * already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above
-		 */
-	}
-#endif
-}
-
-int checkboard(void)
-{
-	int digiboardversion;
-	int failsavelevel;
-	int fpgaversion;
-
-	get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
-
-#ifdef CONFIG_A4M2K
-	puts("Board: A4M2K\n");
-	printf("       digiboard IO version %u\n", digiboardversion);
-#else
-	puts("Board: A3M071\n");
-	printf("Rev:   failsave level       %u\n", failsavelevel);
-	printf("       digiboard IO version %u\n", digiboardversion);
-	if (failsavelevel > 0)	/* only if fpga-version red */
-		printf("       fpga IO version      %u\n", fpgaversion);
-#endif
-
-	return 0;
-}
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
-	/* adjust flash start and offset to detected values */
-	gd->bd->bi_flashstart = flash_info[0].start[0];
-	gd->bd->bi_flashoffset = 0;
-
-	/* adjust mapping */
-	out_be32((void *)MPC5XXX_BOOTCS_START,
-		 START_REG(gd->bd->bi_flashstart));
-	out_be32((void *)MPC5XXX_CS0_START, START_REG(gd->bd->bi_flashstart));
-	out_be32((void *)MPC5XXX_BOOTCS_STOP,
-		 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
-	out_be32((void *)MPC5XXX_CS0_STOP,
-		 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-#ifdef CONFIG_SPL_OS_BOOT
-/*
- * A3M071 specific implementation of spl_start_uboot()
- *
- * RETURN
- * 0 if booting into OS is selected (default)
- * 1 if booting into U-Boot is selected
- */
-int spl_start_uboot(void)
-{
-	char s[8];
-
-	env_init();
-	getenv_f("boot_os", s, sizeof(s));
-	if ((s != NULL) && (*s == '1' || *s == 'y' || *s == 'Y' ||
-			    *s == 't' || *s == 'T'))
-		return 0;
-
-	return 1;
-}
-#endif
-
-#if defined(CONFIG_HW_WATCHDOG)
-static int watchdog_toggle;
-
-void hw_watchdog_reset(void)
-{
-	int val;
-
-	/*
-	 * Check if watchdog is enabled via user command
-	 */
-	if ((gd->flags & GD_FLG_RELOC) && watchdog_toggle) {
-		/* Set direction to output */
-		setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_WDOG_GPIO_PIN);
-
-		/*
-		 * Toggle watchdog output
-		 */
-		val = (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
-		       CONFIG_WDOG_GPIO_PIN);
-		if (val) {
-			clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
-				     CONFIG_WDOG_GPIO_PIN);
-		} else {
-			setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
-				     CONFIG_WDOG_GPIO_PIN);
-		}
-	}
-}
-
-int do_wdog_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	if (argc != 2)
-		goto usage;
-
-	if (strncmp(argv[1], "on", 2) == 0)
-		watchdog_toggle = 1;
-	else if (strncmp(argv[1], "off", 3) == 0)
-		watchdog_toggle = 0;
-	else
-		goto usage;
-
-	return 0;
-usage:
-	printf("Usage: wdogtoggle %s\n", cmdtp->usage);
-	return 1;
-}
-
-U_BOOT_CMD(
-	wdogtoggle, CONFIG_SYS_MAXARGS, 2, do_wdog_toggle,
-	"toggle GPIO pin to service watchdog",
-	"[on/off] - Switch watchdog toggling via GPIO pin on/off"
-);
-#endif
diff --git a/board/a3m071/is46r16320d.h b/board/a3m071/is46r16320d.h
deleted file mode 100644
index 981359f..0000000
--- a/board/a3m071/is46r16320d.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR		/* is DDR */
-
-#if defined(CONFIG_MPC5200)
-/* Settings for XLB = 132 MHz */
-/* see is46r16320d datasheet and MPC5200UM chap. 8.6.1. */
-
-/* SDRAM Config Standard timing */
-#define SDRAM_MODE	0x008d0000
-#define SDRAM_EMODE	0x40010000
-#define SDRAM_CONTROL	0x70430f00
-#define SDRAM_CONFIG1	0x33622930
-#define SDRAM_CONFIG2	0x46670000
-#define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/a3m071/mt46v16m16-75.h b/board/a3m071/mt46v16m16-75.h
deleted file mode 100644
index 8f42830..0000000
--- a/board/a3m071/mt46v16m16-75.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR		/* is DDR */
-
-#if defined(CONFIG_MPC5200)
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x704f0f00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-#define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/a4m072/Kconfig b/board/a4m072/Kconfig
deleted file mode 100644
index ba5447f..0000000
--- a/board/a4m072/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_A4M072
-
-config SYS_BOARD
-	default "a4m072"
-
-config SYS_CONFIG_NAME
-	default "a4m072"
-
-endif
diff --git a/board/a4m072/MAINTAINERS b/board/a4m072/MAINTAINERS
deleted file mode 100644
index 83dc59e..0000000
--- a/board/a4m072/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-A4M072 BOARD
-M:	Sergei Poselenov <sposelenov@emcraft.com>
-S:	Maintained
-F:	board/a4m072/
-F:	include/configs/a4m072.h
-F:	configs/a4m072_defconfig
diff --git a/board/a4m072/Makefile b/board/a4m072/Makefile
deleted file mode 100644
index 2a40e57..0000000
--- a/board/a4m072/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= a4m072.o
diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c
deleted file mode 100644
index 20d8b80..0000000
--- a/board/a4m072/a4m072.c
+++ /dev/null
@@ -1,475 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2010
- * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <libfdt.h>
-#include <netdev.h>
-#include <led-display.h>
-#include <linux/err.h>
-
-#include "mt46v32m16.h"
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-	long control = SDRAM_CONTROL | hi_addr_bit;
-
-	/* unlock mode register */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
-	__asm__ volatile ("sync");
-#endif
-
-	/* precharge all banks */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
-	__asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *            is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-	uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
-	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set tap delay */
-	out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
-	__asm__ volatile ("sync");
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
-				 0x13 + __builtin_ffs(dramsize >> 20) - 1);
-	} else {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
-		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
-		__asm__ volatile ("sync");
-	}
-
-	return dramsize;
-}
-
-int checkboard (void)
-{
-	puts ("Board: A4M072\n");
-	return 0;
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-int board_eth_init(bd_t *bis)
-{
-	int rv, num_if = 0;
-
-	/* Initialize TSECs first */
-	if ((rv = cpu_eth_init(bis)) >= 0)
-		num_if += rv;
-	else
-		printf("ERROR: failed to initialize FEC.\n");
-
-	if ((rv = pci_eth_init(bis)) >= 0)
-		num_if += rv;
-	else
-		printf("ERROR: failed to initialize PCI Ethernet.\n");
-
-	return num_if;
-}
-/*
- * Miscellaneous late-boot configurations
- *
- * Initialize EEPROM write-protect GPIO pin.
- */
-int misc_init_r(void)
-{
-#if defined(CONFIG_SYS_EEPROM_WREN)
-	/* Enable GPIO pin */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
-	/* Set direction, output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
-	/* De-assert write enable */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
-#endif
-	return 0;
-}
-#if defined(CONFIG_SYS_EEPROM_WREN)
-/* Input: <dev_addr>  I2C address of EEPROM device to enable.
- *         <state>     -1: deliver current state
- *	               0: disable write
- *		       1: enable write
- *  Returns:           -1: wrong device address
- *                      0: dis-/en- able done
- *		     0/1: current state if <state> was -1.
- */
-int eeprom_write_enable (unsigned dev_addr, int state)
-{
-	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
-		return -1;
-	} else {
-		switch (state) {
-		case 1:
-			/* Enable write access */
-			clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
-			state = 0;
-			break;
-		case 0:
-			/* Disable write access */
-			setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
-			state = 0;
-			break;
-		default:
-			/* Read current status back. */
-			state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
-						   CONFIG_SYS_EEPROM_WP));
-			break;
-		}
-	}
-	return state;
-}
-#endif
-
-#ifdef CONFIG_CMD_DISPLAY
-#define DISPLAY_BUF_SIZE	2
-static u8 display_buf[DISPLAY_BUF_SIZE];
-static u8 display_putc_pos;
-static u8 display_out_pos;
-
-void display_set(int cmd) {
-
-	if (cmd & DISPLAY_CLEAR) {
-		display_buf[0] = display_buf[1] = 0;
-	}
-
-	if (cmd & DISPLAY_HOME) {
-		display_putc_pos = 0;
-	}
-}
-
-#define SEG_A    (1<<0)
-#define SEG_B    (1<<1)
-#define SEG_C    (1<<2)
-#define SEG_D    (1<<3)
-#define SEG_E    (1<<4)
-#define SEG_F    (1<<5)
-#define SEG_G    (1<<6)
-#define SEG_P    (1<<7)
-#define SEG__    0
-
-/*
- * +- A -+
- * |     |
- * F     B
- * |     |
- * +- G -+
- * |     |
- * E     C
- * |     |
- * +- D -+  P
- *
- * 0..9		index 0..9
- * A..Z		index 10..35
- * -		index 36
- * _		index 37
- * .		index 38
- */
-
-#define SYMBOL_DASH		(36)
-#define SYMBOL_UNDERLINE	(37)
-#define SYMBOL_DOT		(38)
-
-static u8 display_char2seg7_tbl[]=
-{
-	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,		/* 0 */
-	SEG_B | SEG_C,						/* 1 */
-	SEG_A | SEG_B | SEG_D | SEG_E | SEG_G,			/* 2 */
-	SEG_A | SEG_B | SEG_C | SEG_D | SEG_G,			/* 3 */
-	SEG_B | SEG_C | SEG_F | SEG_G,				/* 4 */
-	SEG_A | SEG_C | SEG_D | SEG_F | SEG_G,			/* 5 */
-	SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,		/* 6 */
-	SEG_A | SEG_B | SEG_C,					/* 7 */
-	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,	/* 8 */
-	SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G,		/* 9 */
-	SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G,		/* A */
-	SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,			/* b */
-	SEG_A | SEG_D | SEG_E | SEG_F,				/* C */
-	SEG_B | SEG_C | SEG_D | SEG_E | SEG_G,			/* d */
-	SEG_A | SEG_D | SEG_E | SEG_F | SEG_G,			/* E */
-	SEG_A | SEG_E | SEG_F | SEG_G,				/* F */
-	0,					/* g - not displayed */
-	SEG_B | SEG_C | SEG_E | SEG_F | SEG_G,			/* H */
-	SEG_B | SEG_C,						/* I */
-	0,					/* J - not displayed */
-	0,					/* K - not displayed */
-	SEG_D | SEG_E | SEG_F,					/* L */
-	0,					/* m - not displayed */
-	0,					/* n - not displayed */
-	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,		/* O */
-	SEG_A | SEG_B | SEG_E | SEG_F | SEG_G,			/* P */
-	0,					/* q - not displayed */
-	0,					/* r - not displayed */
-	SEG_A | SEG_C | SEG_D | SEG_F | SEG_G,			/* S */
-	SEG_D | SEG_E | SEG_F | SEG_G,				/* t */
-	SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,			/* U */
-	0,					/* V - not displayed */
-	0,					/* w - not displayed */
-	0,					/* X - not displayed */
-	SEG_B | SEG_C | SEG_D | SEG_F | SEG_G,			/* Y */
-	0,					/* Z - not displayed */
-	SEG_G,							/* - */
-	SEG_D,							/* _ */
-	SEG_P							/* . */
-};
-
-/* Convert char to the LED segments representation */
-static u8 display_char2seg7(char c)
-{
-	u8 val = 0;
-
-	if (c >= '0' && c <= '9')
-		c -= '0';
-	else if (c >= 'a' && c <= 'z')
-		c -= 'a' - 10;
-	else if (c >= 'A' && c <= 'Z')
-		c -= 'A' - 10;
-	else if (c == '-')
-		c = SYMBOL_DASH;
-	else if (c == '_')
-		c = SYMBOL_UNDERLINE;
-	else if (c == '.')
-		c = SYMBOL_DOT;
-	else
-		c = ' ';	/* display unsupported symbols as space */
-
-	if (c != ' ')
-		val = display_char2seg7_tbl[(int)c];
-
-	return val;
-}
-
-int display_putc(char c)
-{
-	if (display_putc_pos >= DISPLAY_BUF_SIZE)
-		return -1;
-
-	display_buf[display_putc_pos++] = display_char2seg7(c);
-	/* one-symbol message should be steady */
-	if (display_putc_pos == 1)
-		display_buf[display_putc_pos] = display_char2seg7(c);
-
-	return c;
-}
-
-/*
- * Flush current symbol to the LED display hardware
- */
-static inline void display_flush(void)
-{
-	u32 val = display_buf[display_out_pos];
-
-	val |= (val << 8) | (val << 16) | (val << 24);
-	out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val);
-}
-
-/*
- * Output contents of the software display buffer to the LED display every 0.5s
- */
-void board_show_activity(ulong timestamp)
-{
-	static ulong last;
-	static u8 once;
-
-	if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) {
-		display_flush();
-		display_out_pos ^= 1;
-		last = timestamp;
-		once = 1;
-	}
-}
-
-/*
- * Empty fake function
- */
-void show_activity(int arg)
-{
-}
-#endif
-#if defined (CONFIG_SHOW_BOOT_PROGRESS)
-static int a4m072_status2code(int status, char *buf)
-{
-	char c = 0;
-
-	if (((status > 0) && (status <= 8)) ||
-				((status >= 100) && (status <= 108)) ||
-				((status < 0) && (status >= -9)) ||
-				(status == -100) || (status == -101) ||
-				((status <= -103) && (status >= -113))) {
-		c = '5';
-	} else if (((status >= 9) && (status <= 14)) ||
-			((status >= 120) && (status <= 123)) ||
-			((status >= 125) && (status <= 129)) ||
-			((status >= -13) && (status <= -10)) ||
-			(status == -120) || (status == -122) ||
-			((status <= -124) && (status >= -127)) ||
-			(status == -129)) {
-		c = '8';
-	} else if (status == 15) {
-		c = '9';
-	} else if ((status <= -30) && (status >= -32)) {
-		c = 'A';
-	} else if (((status <= -35) && (status >= -40)) ||
-			((status <= -42) && (status >= -51)) ||
-			((status <= -53) && (status >= -58)) ||
-			(status == -64) ||
-			((status <= -80) && (status >= -83)) ||
-			(status == -130) || (status == -140) ||
-			(status == -150)) {
-		c = 'B';
-	}
-
-	if (c == 0)
-		return -EINVAL;
-
-	buf[0] = (status < 0) ? '-' : c;
-	buf[1] = c;
-
-	return 0;
-}
-
-void show_boot_progress(int status)
-{
-	char buf[2];
-
-	if (a4m072_status2code(status, buf) < 0)
-		return;
-
-	display_putc(buf[0]);
-	display_putc(buf[1]);
-	display_set(DISPLAY_HOME);
-	display_out_pos = 0;	/* reset output position */
-
-	/* we want to flush status 15 now */
-	if (status == BOOTSTAGE_ID_RUN_OS)
-		display_flush();
-}
-#endif
diff --git a/board/a4m072/mt46v32m16.h b/board/a4m072/mt46v32m16.h
deleted file mode 100644
index c0a08a8..0000000
--- a/board/a4m072/mt46v32m16.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-#if defined(CONFIG_MPC5200)
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40010000
-#define SDRAM_CONTROL	0x704f0f00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-#define SDRAM_TAPDELAY	0x10000000
-
-#else
-#error CONFIG_MPC5200 not defined
-#endif
diff --git a/board/advantech/dms-ba16/dms-ba16.c b/board/advantech/dms-ba16/dms-ba16.c
index f0f1976..c728943 100644
--- a/board/advantech/dms-ba16/dms-ba16.c
+++ b/board/advantech/dms-ba16/dms-ba16.c
@@ -10,12 +10,12 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
@@ -103,8 +103,9 @@ static void setup_iomux_enet(void)
 
 	/* Reset AR8033 PHY */
 	gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
-	udelay(500);
+	mdelay(10);
 	gpio_set_value(IMX_GPIO_NR(1, 28), 1);
+	mdelay(1);
 }
 
 static iomux_v3_cfg_t const usdhc2_pads[] = {
@@ -303,7 +304,8 @@ static int mx6_rgmii_rework(struct phy_device *phydev)
 	/* set debug port address: SerDes Test and System Mode Control */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 	/* enable rgmii tx clock delay */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+	/* set the reserved bits to avoid board specific voltage peak issue*/
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 
 	return 0;
 }
@@ -534,11 +536,61 @@ static const struct boot_mode board_boot_modes[] = {
 };
 #endif
 
+void pmic_init(void)
+{
+
+#define DA9063_ADDR 0x58
+#define BCORE2_CONF 0x9D
+#define BCORE1_CONF 0x9E
+#define BPRO_CONF 0x9F
+#define BIO_CONF 0xA0
+#define BMEM_CONF 0xA1
+#define BPERI_CONF 0xA2
+#define MODE_BIT_H 7
+#define MODE_BIT_L 6
+
+        uchar val;
+        i2c_set_bus_num(2);
+
+        i2c_read(DA9063_ADDR, BCORE2_CONF, 1, &val, 1);
+        val |= (1 << MODE_BIT_H);
+        val &= ~(1 << MODE_BIT_L);
+        i2c_write(DA9063_ADDR, BCORE2_CONF , 1, &val, 1);
+
+        i2c_read(DA9063_ADDR, BCORE1_CONF, 1, &val, 1);
+        val |= (1 << MODE_BIT_H);
+        val &= ~(1 << MODE_BIT_L);
+        i2c_write(DA9063_ADDR, BCORE1_CONF , 1, &val, 1);
+
+        i2c_read(DA9063_ADDR, BPRO_CONF, 1, &val, 1);
+        val |= (1 << MODE_BIT_H);
+        val &= ~(1 << MODE_BIT_L);
+        i2c_write(DA9063_ADDR, BPRO_CONF , 1, &val, 1);
+
+        i2c_read(DA9063_ADDR, BIO_CONF, 1, &val, 1);
+        val |= (1 << MODE_BIT_H);
+        val &= ~(1 << MODE_BIT_L);
+        i2c_write(DA9063_ADDR, BIO_CONF , 1, &val, 1);
+
+        i2c_read(DA9063_ADDR, BMEM_CONF, 1, &val, 1);
+        val |= (1 << MODE_BIT_H);
+        val &= ~(1 << MODE_BIT_L);
+        i2c_write(DA9063_ADDR, BMEM_CONF , 1, &val, 1);
+
+        i2c_read(DA9063_ADDR, BPERI_CONF, 1, &val, 1);
+        val |= (1 << MODE_BIT_H);
+        val &= ~(1 << MODE_BIT_L);
+        i2c_write(DA9063_ADDR, BPERI_CONF , 1, &val, 1);
+
+}
+
 int board_late_init(void)
 {
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
 #endif
+
+#if defined(CONFIG_VIDEO_IPUV3)
 	/*
 	 * We need at least 200ms between power on and backlight on
 	 * as per specifications from CHI MEI
@@ -555,11 +607,15 @@ int board_late_init(void)
 	gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 
 	pwm_enable(0);
+#endif
 
-#ifdef CONFIG_CMD_SATA
+#ifdef CONFIG_SATA
 	setup_ba16_sata();
 #endif
 
+        /* board specific pmic init */
+        pmic_init();
+
 	return 0;
 }
 
diff --git a/board/advantech/som-db5800-som-6867/Kconfig b/board/advantech/som-db5800-som-6867/Kconfig
index f6f3748..fac562a 100644
--- a/board/advantech/som-db5800-som-6867/Kconfig
+++ b/board/advantech/som-db5800-som-6867/Kconfig
@@ -21,6 +21,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR if !EFI_STUB
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select BOARD_EARLY_INIT_F
+	select SPI_FLASH_MACRONIX
 
 config PCIE_ECAM_BASE
 	default 0xe0000000
diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
index 5bed2c1..6158795 100644
--- a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
+++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c
@@ -17,8 +17,3 @@ int board_early_init_f(void)
 
 	return 0;
 }
-
-int arch_early_init_r(void)
-{
-	return 0;
-}
diff --git a/board/alphaproject/ap_sh4a_4a/Makefile b/board/alphaproject/ap_sh4a_4a/Makefile
index 486d0ac..df76466 100644
--- a/board/alphaproject/ap_sh4a_4a/Makefile
+++ b/board/alphaproject/ap_sh4a_4a/Makefile
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y	:= ap_sh4a_4a.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c b/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c
index e65befc..9205c22 100644
--- a/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c
+++ b/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c
@@ -11,8 +11,6 @@
 #include <netdev.h>
 #include <i2c.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #define MODEMR			(0xFFCC0020)
 #define MODEMR_MASK		(0x6)
 #define MODEMR_533MHZ	(0x2)
@@ -158,26 +156,7 @@ int board_init(void)
 
 int board_late_init(void)
 {
-	u8 mac[6];
-
-	/* Read Mac Address and set*/
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-	i2c_set_bus_num(CONFIG_SYS_I2C_MODULE);
-
-	/* Read MAC address */
-	i2c_read(0x50, 0x0, 0, mac, 6);
-
-	if (is_valid_ethaddr(mac))
-		eth_setenv_enetaddr("ethaddr", mac);
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	printf("Cannot use I2C to get MAC address\n");
 
 	return 0;
 }
diff --git a/board/altera/arria10-socdk/Kconfig b/board/altera/arria10-socdk/Kconfig
new file mode 100644
index 0000000..b80cc6d
--- /dev/null
+++ b/board/altera/arria10-socdk/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SOCFPGA_ARRIA10
+
+config SYS_CPU
+	default "armv7"
+
+config SYS_BOARD
+	default "socfpga_arria10"
+
+config SYS_VENDOR
+	default "altera"
+
+config SYS_SOC
+	default "socfpga_arria10"
+
+config SYS_CONFIG_NAME
+	default "socfpga_arria10"
+
+endif
diff --git a/board/altera/arria10-socdk/Makefile b/board/altera/arria10-socdk/Makefile
new file mode 100644
index 0000000..1d885ce
--- /dev/null
+++ b/board/altera/arria10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Altera Corporation <www.altera.com>
+#
+# SPDX-License-Identifier:	GPL-2.0
+#
+
+obj-y	:= socfpga.o
diff --git a/board/altera/arria10-socdk/socfpga.c b/board/altera/arria10-socdk/socfpga.c
new file mode 100644
index 0000000..8516633
--- /dev/null
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2015 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
diff --git a/board/altera/arria5-socdk/MAINTAINERS b/board/altera/arria5-socdk/MAINTAINERS
index ba35b36..873ec2b 100644
--- a/board/altera/arria5-socdk/MAINTAINERS
+++ b/board/altera/arria5-socdk/MAINTAINERS
@@ -1,5 +1,5 @@
 SOCFPGA BOARD
-M:	Dinh Nguyen <dinguyen@opensource.altera.com>
+M:	Dinh Nguyen <dinguyen@kernel.org>
 M:	Chin-Liang See <clsee@altera.com>
 S:	Maintained
 F:	board/altera/arria5-socdk/
diff --git a/board/altera/arria5-socdk/qts/sdram_config.h b/board/altera/arria5-socdk/qts/sdram_config.h
index e9fe60f..2589f3f 100644
--- a/board/altera/arria5-socdk/qts/sdram_config.h
+++ b/board/altera/arria5-socdk/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0
diff --git a/board/altera/cyclone5-socdk/MAINTAINERS b/board/altera/cyclone5-socdk/MAINTAINERS
index 6374d59..ecf1d04 100644
--- a/board/altera/cyclone5-socdk/MAINTAINERS
+++ b/board/altera/cyclone5-socdk/MAINTAINERS
@@ -1,5 +1,5 @@
 SOCFPGA BOARD
-M:	Dinh Nguyen <dinguyen@opensource.altera.com>
+M:	Dinh Nguyen <dinguyen@kernel.org>
 M:	Chin-Liang See <clsee@altera.com>
 S:	Maintained
 F:	board/altera/cyclone5-socdk/
diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h b/board/altera/cyclone5-socdk/qts/sdram_config.h
index 37c1476..8f3ddce 100644
--- a/board/altera/cyclone5-socdk/qts/sdram_config.h
+++ b/board/altera/cyclone5-socdk/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0
diff --git a/board/amazon/kc1/kc1.c b/board/amazon/kc1/kc1.c
index 469a83e..13a9c6a 100644
--- a/board/amazon/kc1/kc1.c
+++ b/board/amazon/kc1/kc1.c
@@ -17,6 +17,7 @@
 #include <asm/emif.h>
 #include <twl6030.h>
 #include "kc1.h"
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -166,12 +167,10 @@ int fb_set_reboot_flag(void)
 	return omap_reboot_mode_store("b");
 }
 
-#ifndef CONFIG_SPL_BUILD
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(1, 0, 0, -1, -1);
 }
-#endif
 
 void board_mmc_power_init(void)
 {
diff --git a/board/amcc/acadia/Kconfig b/board/amcc/acadia/Kconfig
deleted file mode 100644
index 7c0ef53..0000000
--- a/board/amcc/acadia/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TARGET_ACADIA
-
-config SYS_BOARD
-	default "acadia"
-
-config SYS_VENDOR
-	default "amcc"
-
-config SYS_CONFIG_NAME
-	default "acadia"
-
-config DISPLAY_BOARDINFO
-	bool
-	default y
-
-endif
diff --git a/board/amcc/acadia/MAINTAINERS b/board/amcc/acadia/MAINTAINERS
deleted file mode 100644
index c16961f..0000000
--- a/board/amcc/acadia/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ACADIA BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/amcc/acadia/
-F:	include/configs/acadia.h
-F:	configs/acadia_defconfig
diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile
deleted file mode 100644
index 035f407..0000000
--- a/board/amcc/acadia/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= acadia.o cmd_acadia.o memory.o pll.o
diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
deleted file mode 100644
index 2eb18df..0000000
--- a/board/amcc/acadia/acadia.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-extern void board_pll_init_f(void);
-
-static void acadia_gpio_init(void)
-{
-	/*
-	 * GPIO0 setup (select GPIO or alternate function)
-	 */
-	out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
-	out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH);	/* output select */
-	out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
-	out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H);	/* input select */
-	out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
-	out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH);	/* three-state select */
-	out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR);  /* enable output driver for outputs */
-
-	/*
-	 * Ultra (405EZ) was nice enough to add another GPIO controller
-	 */
-	out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH);	/* output select */
-	out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL);
-	out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H);	/* input select */
-	out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L);
-	out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH);	/* three-state select */
-	out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL);
-	out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR);  /* enable output driver for outputs */
-}
-
-int board_early_init_f(void)
-{
-	unsigned int reg;
-
-	/* don't reinit PLL when booting via I2C bootstrap option */
-	mfsdr(SDR0_PINSTP, reg);
-	if (reg != 0xf0000000)
-		board_pll_init_f();
-
-	acadia_gpio_init();
-
-	/* Configure 405EZ for NAND usage */
-	mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
-	mfsdr(SDR0_ULTRA0, reg);
-	reg &= ~SDR_ULTRA0_CSN_MASK;
-	reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) |
-		SDR_ULTRA0_NDGPIOBP |
-		SDR_ULTRA0_EBCRDYEN |
-		SDR_ULTRA0_NFSRSTEN;
-	mtsdr(SDR0_ULTRA0, reg);
-
-	/* USB Host core needs this bit set */
-	mfsdr(SDR0_ULTRA1, reg);
-	mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
-
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
-	mtdcr(UIC0CR, 0x00000010);
-	mtdcr(UIC0PR, 0xFE7FFFF0);	/* set int polarities */
-	mtdcr(UIC0TR, 0x00000010);	/* set int trigger levels */
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-
-	return 0;
-}
-
-int misc_init_f(void)
-{
-	/* Set EPLD to take PHY out of reset */
-	out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00);
-	udelay(100000);
-
-	return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-	u8 rev;
-
-	rev = in8(CONFIG_SYS_CPLD_BASE + 0);
-	printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev);
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return (0);
-}
diff --git a/board/amcc/acadia/cmd_acadia.c b/board/amcc/acadia/cmd_acadia.c
deleted file mode 100644
index e9df61b..0000000
--- a/board/amcc/acadia/cmd_acadia.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-
-static u8 boot_267_nor[] = {
-	0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x00,
-	0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00
-};
-
-static u8 boot_267_nand[] = {
-	0xd0, 0x38, 0xc3, 0x50, 0x13, 0x88, 0x8e, 0x00,
-	0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00
-};
-
-static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	u8 chip;
-	u8 *buf;
-	int cpu_freq;
-
-	if (argc < 3)
-		return cmd_usage(cmdtp);
-
-	cpu_freq = simple_strtol(argv[1], NULL, 10);
-	if (cpu_freq != 267) {
-		printf("Unsupported cpu-frequency - only 267 supported\n");
-		return 1;
-	}
-
-	/* use 0x50 as I2C EEPROM address for now */
-	chip = 0x50;
-
-	if ((strcmp(argv[2], "nor") != 0) &&
-	    (strcmp(argv[2], "nand") != 0)) {
-		printf("Unsupported boot-device - only nor|nand support\n");
-		return 1;
-	}
-
-	if (strcmp(argv[2], "nand") == 0) {
-		switch (cpu_freq) {
-		case 267:
-			buf = boot_267_nand;
-			break;
-		default:
-			break;
-		}
-	} else {
-		switch (cpu_freq) {
-		case 267:
-			buf = boot_267_nor;
-			break;
-		default:
-			break;
-		}
-	}
-
-	if (i2c_write(chip, 0, 1, buf, 16) != 0)
-		printf("Error writing to EEPROM at address 0x%x\n", chip);
-	udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
-	if (i2c_write(chip, 0x10, 1, buf+16, 4) != 0)
-		printf("Error2 writing to EEPROM at address 0x%x\n", chip);
-
-	printf("Done\n");
-	printf("Please power-cycle the board for the changes to take effect\n");
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	bootstrap,	3,	0,	do_bootstrap,
-	"program the I2C bootstrap EEPROM",
-	"<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM"
-);
diff --git a/board/amcc/acadia/config.mk b/board/amcc/acadia/config.mk
deleted file mode 100644
index 5350ec0..0000000
--- a/board/amcc/acadia/config.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2007-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-#
-# AMCC 405EZ Reference Platform (Acadia) board
-#
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
deleted file mode 100644
index 9673118..0000000
--- a/board/amcc/acadia/memory.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-extern void board_pll_init_f(void);
-
-static void cram_bcr_write(u32 wr_val)
-{
-	wr_val <<= 2;
-
-	/* set CRAM_CRE to 1 */
-	gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1);
-
-	/* Write BCR to CRAM on CS1 */
-	out32(wr_val + 0x00200000, 0);
-	debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
-
-	/* Write BCR to CRAM on CS2 */
-	out32(wr_val + 0x02200000, 0);
-	debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
-
-	sync();
-	eieio();
-
-	/* set CRAM_CRE back to 0 (normal operation) */
-	gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0);
-
-	return;
-}
-
-phys_size_t initdram(int board_type)
-{
-	int i;
-	u32 val;
-
-	/* 1. EBC need to program READY, CLK, ADV for ASync mode */
-	gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
-	gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
-	gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
-	gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
-
-	/* 2. EBC in Async mode */
-	mtebc(PB1AP, 0x078F1EC0);
-	mtebc(PB2AP, 0x078F1EC0);
-	mtebc(PB1CR, 0x000BC000);
-	mtebc(PB2CR, 0x020BC000);
-
-	/* 3. Set CRAM in Sync mode */
-	cram_bcr_write(0x7012);		/* CRAM burst setting */
-
-	/* 4. EBC in Sync mode */
-	mtebc(PB1AP, 0x9C0201C0);
-	mtebc(PB2AP, 0x9C0201C0);
-
-	/* Set GPIO pins back to alternate function */
-	gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
-	gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
-
-	/* Config EBC to use RDY */
-	mfsdr(SDR0_ULTRA0, val);
-	mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN);
-
-	/* Wait a short while, since for NAND booting this is too fast */
-	for (i=0; i<200000; i++)
-		;
-
-	return (CONFIG_SYS_MBYTES_RAM << 20);
-}
diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c
deleted file mode 100644
index d868582..0000000
--- a/board/amcc/acadia/pll.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/ppc405.h>
-
-/* test-only: move into cpu directory!!! */
-
-#if defined(PLLMR0_200_133_66)
-void board_pll_init_f(void)
-{
-	/*
-	 * set PLL clocks based on input sysclk is 33M
-	 *
-	 * ----------------------------------
-	 * | CLK   | FREQ (MHz) | DIV RATIO |
-	 * ----------------------------------
-	 * | CPU   |  200.0     |   4 (0x02)|
-	 * | PLB   |  133.3     |   6 (0x06)|
-	 * | OPB   |   66.6     |  12 (0x0C)|
-	 * | EBC   |   66.6     |  12 (0x0C)|
-	 * | SPI   |   66.6     |  12 (0x0C)|
-	 * | UART0 |   10.0     |  40 (0x28)|
-	 * | UART1 |   10.0     |  40 (0x28)|
-	 * | DAC   |    2.0     | 200 (0xC8)|
-	 * | ADC   |    2.0     | 200 (0xC8)|
-	 * | PWM   |  100.0     |   4 (0x04)|
-	 * | EMAC  |   25.0     |  16 (0x10)|
-	 * -----------------------------------
-	 */
-
-	/* Initialize PLL */
-	mtcpr(CPR0_PLLC, 0x0000033c);
-	mtcpr(CPR0_PLLD, 0x0c010200);
-	mtcpr(CPR0_PRIMAD, 0x04060c0c);
-	mtcpr(CPR0_PERD0, 0x000c0000);	/* SPI clk div. eq. OPB clk div. */
-	mtcpr(CPR0_CLKUPD, 0x40000000);
-}
-
-#elif defined(PLLMR0_266_160_80)
-
-void board_pll_init_f(void)
-{
-	/*
-	 * set PLL clocks based on input sysclk is 33M
-	 *
-	 * ----------------------------------
-	 * | CLK   | FREQ (MHz) | DIV RATIO |
-	 * ----------------------------------
-	 * | CPU   |  266.64    |   3       |
-	 * | PLB   |  159.98    |   5 (0x05)|
-	 * | OPB   |   79.99    |  10 (0x0A)|
-	 * | EBC   |   79.99    |  10 (0x0A)|
-	 * | SPI   |   79.99    |  10 (0x0A)|
-	 * | UART0 |   28.57    |   7 (0x07)|
-	 * | UART1 |   28.57    |   7 (0x07)|
-	 * | DAC   |   28.57    |   7 (0xA7)|
-	 * | ADC   |    4       |  50 (0x32)|
-	 * | PWM   |   28.57    |   7 (0x07)|
-	 * | EMAC  |    4       |  50 (0x32)|
-	 * -----------------------------------
-	 */
-
-	/* Initialize PLL */
-	mtcpr(CPR0_PLLC, 0x20000238);
-	mtcpr(CPR0_PLLD, 0x03010400);
-	mtcpr(CPR0_PRIMAD, 0x03050a0a);
-	mtcpr(CPR0_PERC0, 0x00000000);
-	mtcpr(CPR0_PERD0, 0x070a0707);	/* SPI clk div. eq. OPB clk div. */
-	mtcpr(CPR0_PERD1, 0x07323200);
-	mtcpr(CPR0_CLKUP, 0x40000000);
-}
-
-#elif defined(PLLMR0_333_166_83)
-
-void board_pll_init_f(void)
-{
-	/*
-	 * set PLL clocks based on input sysclk is 33M
-	 *
-	 * ----------------------------------
-	 * | CLK   | FREQ (MHz) | DIV RATIO |
-	 * ----------------------------------
-	 * | CPU   |  333.33    |   2       |
-	 * | PLB   |  166.66    |   4 (0x04)|
-	 * | OPB   |   83.33    |   8 (0x08)|
-	 * | EBC   |   83.33    |   8 (0x08)|
-	 * | SPI   |   83.33    |   8 (0x08)|
-	 * | UART0 |   16.66    |   5 (0x05)|
-	 * | UART1 |   16.66    |   5 (0x05)|
-	 * | DAC   |   ????     | 166 (0xA6)|
-	 * | ADC   |   ????     | 166 (0xA6)|
-	 * | PWM   |   41.66    |   3 (0x03)|
-	 * | EMAC  |   ????     |   3 (0x03)|
-	 * -----------------------------------
-	 */
-
-	/* Initialize PLL */
-	mtcpr(CPR0_PLLC, 0x0000033C);
-	mtcpr(CPR0_PLLD, 0x0a010000);
-	mtcpr(CPR0_PRIMAD, 0x02040808);
-	mtcpr(CPR0_PERD0, 0x02080505);	/* SPI clk div. eq. OPB clk div. */
-	mtcpr(CPR0_PERD1, 0xA6A60300);
-	mtcpr(CPR0_CLKUP, 0x40000000);
-}
-
-#elif defined(PLLMR0_100_100_12)
-
-void board_pll_init_f(void)
-{
-	/*
-	 * set PLL clocks based on input sysclk is 33M
-	 *
-	 * ----------------------
-	 * | CLK   | FREQ (MHz) |
-	 * ----------------------
-	 * | CPU   |  100.00    |
-	 * | PLB   |  100.00    |
-	 * | OPB   |   12.00    |
-	 * | EBC   |   49.00    |
-	 * ----------------------
-	 */
-
-	/* Initialize PLL */
-	mtcpr(CPR0_PLLC, 0x000003BC);
-	mtcpr(CPR0_PLLD, 0x06060600);
-	mtcpr(CPR0_PRIMAD, 0x02020004);
-	mtcpr(CPR0_PERD0, 0x04002828);	/* SPI clk div. eq. OPB clk div. */
-	mtcpr(CPR0_PERD1, 0xC8C81600);
-	mtcpr(CPR0_CLKUP, 0x40000000);
-}
-#endif				/* CPU_<speed>_405EZ */
diff --git a/board/amcc/bamboo/Kconfig b/board/amcc/bamboo/Kconfig
deleted file mode 100644
index d44a36a..0000000
--- a/board/amcc/bamboo/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TARGET_BAMBOO
-
-config SYS_BOARD
-	default "bamboo"
-
-config SYS_VENDOR
-	default "amcc"
-
-config SYS_CONFIG_NAME
-	default "bamboo"
-
-config DISPLAY_BOARDINFO
-	bool
-	default y
-
-endif
diff --git a/board/amcc/bamboo/MAINTAINERS b/board/amcc/bamboo/MAINTAINERS
deleted file mode 100644
index 4c8929e..0000000
--- a/board/amcc/bamboo/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BAMBOO BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/amcc/bamboo/
-F:	include/configs/bamboo.h
-F:	configs/bamboo_defconfig
diff --git a/board/amcc/bamboo/Makefile b/board/amcc/bamboo/Makefile
deleted file mode 100644
index 4c0a125..0000000
--- a/board/amcc/bamboo/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= bamboo.o flash.o
-extra-y	+= init.o
diff --git a/board/amcc/bamboo/README b/board/amcc/bamboo/README
deleted file mode 100644
index e139c6d..0000000
--- a/board/amcc/bamboo/README
+++ /dev/null
@@ -1,77 +0,0 @@
-The 2 important dipswitches are configured as shown below:
-
-SW1 (for 33MHz SysClk)
-----------------------
-S1   S2   S3   S4   S5   S6   S7   S8
-OFF  OFF  OFF  OFF  OFF  OFF  OFF  ON
-
-SW7 (for Op-Code Flash and Boot Option H)
------------------------------------------
-S1   S2   S3   S4   S5   S6   S7   S8
-OFF  OFF  OFF  ON   OFF  OFF  OFF  OFF
-
-The EEPROM at location 0x52 is loaded with these 16 bytes:
-C47042A6 05D7A190 40082350 0d050000
-
-SDR0_SDSTP0[ENG]:	1		: PLL's VCO is the source for PLL forward divisors
-SDR0_SDSTP0[SRC]:	1		: Feedback originates from PLLOUTB
-SDR0_SDSTP0[SEL]:	0		: Feedback selection is PLL output
-SDR0_SDSTP0[TUNE]:	1000111000	: 10 <= M <= 22, 600MHz < VCO <= 900MHz
-SDR0_SDSTP0[FBDV]:	4		: PLL feedback divisor
-SDR0_SDSTP0[FBDVA]:	2		: PLL forward divisor A
-SDR0_SDSTP0[FBDVB]:	5		: PLL forward divisor B
-SDR0_SDSTP0[PRBDV0]:	1		: PLL primary divisor B
-SDR0_SDSTP0[OPBDV0]:	2		: OPB clock divisor
-SDR0_SDSTP0[LFBDV]:	1		: PLL local feedback divisor
-SDR0_SDSTP0[PERDV0]:	3		: Peripheral clock divisor 0
-SDR0_SDSTP0[MALDV0]:	2		: MAL clock divisor 0
-SDR0_SDSTP0[PCIDV0]:	2		: Sync PCI clock divisor 0
-SDR0_SDSTP0[PLLTIMER]:	7		: PLL locking timer
-SDR0_SDSTP0[RW]:	1		: EBC ROM width: 16-bit
-SDR0_SDSTP0[RL]:	0		: EBC ROM location: EBC
-SDR0_SDSTP0[PAE]:	0		: PCI internal arbiter: disabled
-SDR0_SDSTP0[PHCE]:	0		: PCI host configuration: disabled
-SDR0_SDSTP0[ZM]:	3		: ZMII mode: RMII mode 100
-SDR0_SDSTP0[CTE]:	0		: CPU trace: disabled
-SDR0_SDSTP0[Nto1]:	0		: CPU/PLB ratio N/P: not N to 1
-SDR0_SDSTP0[PAME]:	1		: PCI asynchronous mode: enabled
-SDR0_SDSTP0[MEM]:	1		: Multiplex: EMAC
-SDR0_SDSTP0[NE]:	0		: NDFC: disabled
-SDR0_SDSTP0[NBW]:	0		: NDFC boot width: 8-bit
-SDR0_SDSTP0[NBW]:	0		: NDFC boot page selection
-SDR0_SDSTP0[NBAC]:	0		: NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size)
-SDR0_SDSTP0[NARE]:	0		: NDFC auto read : disabled
-SDR0_SDSTP0[NRB]:	0		: NDFC Ready/Busy : Ready
-SDR0_SDSTP0[NDRSC]:	33333		: NDFC device reset counter
-SDR0_SDSTP0[NCG0]:	0		: NDFC/EBC chip select gating CS0 : EBC
-SDR0_SDSTP0[NCG1]:	0		: NDFC/EBC chip select gating CS1 : EBC
-SDR0_SDSTP0[NCG2]:	0		: NDFC/EBC chip select gating CS2 : EBC
-SDR0_SDSTP0[NCG3]:	0		: NDFC/EBC chip select gating CS3 : EBC
-SDR0_SDSTP0[NCRDC]:	3333		: NDFC device read count
-
-PPC440EP Clocking Configuration
-
-SysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHz
-OPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHz
-
-The above information is reported by Eugene O'Brien
-<Eugene.O'Brien@advantechamt.com>. Thanks a lot.
-
-2007-08-06, Stefan Roese <sr@denx.de>
----------------------------------------------------------------------
-
-The configuration for the AMCC 440EP eval board "Bamboo" was changed
-to only use 384 kbytes of FLASH for the U-Boot image. This way the
-redundant environment can be saved in the remaining 2 sectors of the
-same flash chip.
-
-Caution: With an upgrade from an earlier U-Boot version the current
-environment will be erased since the environment is now saved in
-different sectors. By using the following command the environment can
-be saved after upgrading the U-Boot image and *before* resetting the
-board:
-
-setenv recover_env 'prot off FFF80000 FFF9FFFF;era FFF80000 FFF9FFFF;' \
-	'cp.b FFF60000 FFF80000 20000'
-
-2006-07-27, Stefan Roese <sr@denx.de>
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
deleted file mode 100644
index c8d0963..0000000
--- a/board/amcc/bamboo/bamboo.c
+++ /dev/null
@@ -1,1896 +0,0 @@
-/*
- * (C) Copyright 2005-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-gpio.h>
-#include <spd_sdram.h>
-#include <asm/ppc440.h>
-#include "bamboo.h"
-
-void ext_bus_cntlr_init(void);
-void configure_ppc440ep_pins(void);
-int is_nand_selected(void);
-
-/*************************************************************************
- *
- * Bamboo has one bank onboard sdram (plus DIMM)
- *
- * Fixed memory is composed of :
- *	MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
- *	13 row add bits, 10 column add bits (but 12 row used only).
- *	ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
- *	12 row add bits, 10 column add bits.
- *	Prepare a subset (only the used ones) of SPD data
- *
- *	Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
- *	the corresponding bank is divided by 2 due to number of Row addresses
- *	12 in the ECC module
- *
- *  Assumes:	64 MB, ECC, non-registered
- *		PLB @ 133 MHz
- *
- ************************************************************************/
-const unsigned char cfg_simulate_spd_eeprom[128] = {
-	0x80,    /* number of SPD bytes used: 128 */
-	0x08,    /*  total number bytes in SPD device = 256 */
-	0x07,    /* DDR ram */
-#ifdef CONFIG_DDR_ECC
-	0x0C,    /* num Row Addr: 12 */
-#else
-	0x0D,    /* num Row Addr: 13 */
-#endif
-	0x09,    /* numColAddr: 9  */
-	0x01,    /* numBanks: 1 */
-	0x20,    /* Module data width: 32 bits */
-	0x00,    /* Module data width continued: +0 */
-	0x04,    /* 2.5 Volt */
-	0x75,    /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
-	0x00,    /* SDRAM Access from clock */
-#ifdef CONFIG_DDR_ECC
-	0x02,    /* ECC ON : 02 OFF : 00 */
-#else
-	0x00,    /* ECC ON : 02 OFF : 00 */
-#endif
-	0x82,    /* refresh Rate Type: Normal (7.8us) + Self refresh */
-	0,
-	0,
-	0x01,    /* wcsbc = 1 */
-	0,
-	0,
-	0x0C,    /* casBit (2,2.5) */
-	0,
-	0,
-	0x00,    /* not registered: 0  registered : 0x02*/
-	0,
-	0xA0,    /* SDRAM Cycle Time (cas latency 2) = 10 ns */
-	0,
-	0x00,    /* SDRAM Cycle Time (cas latency 1.5) = N.A */
-	0,
-	0x50,    /* tRpNs = 20 ns  */
-	0,
-	0x50,    /* tRcdNs = 20 ns */
-	45,      /* tRasNs */
-#ifdef CONFIG_DDR_ECC
-	0x08,    /* bankSizeID: 32MB */
-#else
-	0x10,    /* bankSizeID: 64MB */
-#endif
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0
-};
-
-#if 0
-{	   /* GPIO   Alternate1	      Alternate2	Alternate3 */
-    {
-	/* GPIO Core 0 */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0	-> EBC_ADDR(7)	    DMA_REQ(2) */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1	-> EBC_ADDR(6)	    DMA_ACK(2) */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2	-> EBC_ADDR(5)	    DMA_EOT/TC(2) */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3	-> EBC_ADDR(4)	    DMA_REQ(3) */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4	-> EBC_ADDR(3)	    DMA_ACK(3) */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6	-> EBC_CS_N(1) */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7	-> EBC_CS_N(2) */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8	-> EBC_CS_N(3) */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9	 -> EBC_CS_N(4) */
-	{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 ->		    USB2D_RXVALID */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ	    USB2D_RXERROR */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 ->		    USB2D_TXVALID */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA	    USB2D_PAD_SUSPNDM */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK	    USB2D_XCVRSELECT */
-	{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ   USB2D_TERMSELECT */
-    },
-    {
-	/* GPIO Core 1 */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0	-> USB2D_OPMODE0 */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1	-> USB2D_OPMODE1 */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2	-> UART0_DCD_N	    UART1_DSR_CTS_N   UART2_SOUT */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3	-> UART0_8PIN_DSR_N UART1_RTS_DTR_N   UART2_SIN */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4	-> UART0_8PIN_CTS_N		      UART3_SIN */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5	-> UART0_RTS_N */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6	-> UART0_DTR_N	    UART1_SOUT */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7	-> UART0_RI_N	    UART1_SIN */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8	-> UIC_IRQ(0) */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9	-> UIC_IRQ(1) */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4)	    DMA_ACK(1) */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6)	    DMA_EOT/TC(1) */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7)	    DMA_REQ(0) */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8)	    DMA_ACK(0) */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9)	    DMA_EOT/TC(0) */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 ->  | */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 ->  | */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 ->  | */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 ->  | */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 ->  | */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 ->   \	   Can be unselected thru TraceSelect Bit */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 ->   /	      in PowerPC440EP Chip */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 ->  | */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 ->  | */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 ->  | */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 ->  | */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 ->  | */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 ->  | */
-	{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
-    }
-};
-#endif
-
-/*----------------------------------------------------------------------------+
-  | EBC Devices Characteristics
-  |   Peripheral Bank Access Parameters	      -	  EBC0_BnAP
-  |   Peripheral Bank Configuration Register  -	  EBC0_BnCR
-  +----------------------------------------------------------------------------*/
-/* Small Flash */
-#define EBC0_BNAP_SMALL_FLASH				\
-	EBC0_BNAP_BME_DISABLED			|	\
-	EBC0_BNAP_TWT_ENCODE(6)			|	\
-	EBC0_BNAP_CSN_ENCODE(0)			|	\
-	EBC0_BNAP_OEN_ENCODE(1)			|	\
-	EBC0_BNAP_WBN_ENCODE(1)			|	\
-	EBC0_BNAP_WBF_ENCODE(3)			|	\
-	EBC0_BNAP_TH_ENCODE(1)			|	\
-	EBC0_BNAP_RE_ENABLED			|	\
-	EBC0_BNAP_SOR_DELAYED			|	\
-	EBC0_BNAP_BEM_WRITEONLY			|	\
-	EBC0_BNAP_PEN_DISABLED
-
-#define EBC0_BNCR_SMALL_FLASH_CS0			\
-	EBC0_BNCR_BAS_ENCODE(0xFFF00000)	|	\
-	EBC0_BNCR_BS_1MB			|	\
-	EBC0_BNCR_BU_RW				|	\
-	EBC0_BNCR_BW_8BIT
-
-#define EBC0_BNCR_SMALL_FLASH_CS4			\
-	EBC0_BNCR_BAS_ENCODE(0x87F00000)	|	\
-	EBC0_BNCR_BS_1MB			|	\
-	EBC0_BNCR_BU_RW				|	\
-	EBC0_BNCR_BW_8BIT
-
-/* Large Flash or SRAM */
-#define EBC0_BNAP_LARGE_FLASH_OR_SRAM			\
-	EBC0_BNAP_BME_DISABLED			|	\
-	EBC0_BNAP_TWT_ENCODE(8)			|	\
-	EBC0_BNAP_CSN_ENCODE(0)			|	\
-	EBC0_BNAP_OEN_ENCODE(1)			|	\
-	EBC0_BNAP_WBN_ENCODE(1)			|	\
-	EBC0_BNAP_WBF_ENCODE(1)			|	\
-	EBC0_BNAP_TH_ENCODE(2)			|	\
-	EBC0_BNAP_SOR_DELAYED			|	\
-	EBC0_BNAP_BEM_RW			|	\
-	EBC0_BNAP_PEN_DISABLED
-
-#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0		\
-	EBC0_BNCR_BAS_ENCODE(0xFF800000)	|	\
-	EBC0_BNCR_BS_8MB			|	\
-	EBC0_BNCR_BU_RW				|	\
-	EBC0_BNCR_BW_16BIT
-
-
-#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4		\
-	EBC0_BNCR_BAS_ENCODE(0x87800000)	|	\
-	EBC0_BNCR_BS_8MB			|	\
-	EBC0_BNCR_BU_RW				|	\
-	EBC0_BNCR_BW_16BIT
-
-/* NVRAM - FPGA */
-#define EBC0_BNAP_NVRAM_FPGA				\
-	EBC0_BNAP_BME_DISABLED			|	\
-	EBC0_BNAP_TWT_ENCODE(9)			|	\
-	EBC0_BNAP_CSN_ENCODE(0)			|	\
-	EBC0_BNAP_OEN_ENCODE(1)			|	\
-	EBC0_BNAP_WBN_ENCODE(1)			|	\
-	EBC0_BNAP_WBF_ENCODE(0)			|	\
-	EBC0_BNAP_TH_ENCODE(2)			|	\
-	EBC0_BNAP_RE_ENABLED			|	\
-	EBC0_BNAP_SOR_DELAYED			|	\
-	EBC0_BNAP_BEM_WRITEONLY			|	\
-	EBC0_BNAP_PEN_DISABLED
-
-#define EBC0_BNCR_NVRAM_FPGA_CS5			\
-	EBC0_BNCR_BAS_ENCODE(0x80000000)	|	\
-	EBC0_BNCR_BS_1MB			|	\
-	EBC0_BNCR_BU_RW				|	\
-	EBC0_BNCR_BW_8BIT
-
-/* Nand Flash */
-#define EBC0_BNAP_NAND_FLASH				\
-	EBC0_BNAP_BME_DISABLED			|	\
-	EBC0_BNAP_TWT_ENCODE(3)			|	\
-	EBC0_BNAP_CSN_ENCODE(0)			|	\
-	EBC0_BNAP_OEN_ENCODE(0)			|	\
-	EBC0_BNAP_WBN_ENCODE(0)			|	\
-	EBC0_BNAP_WBF_ENCODE(0)			|	\
-	EBC0_BNAP_TH_ENCODE(1)			|	\
-	EBC0_BNAP_RE_ENABLED			|	\
-	EBC0_BNAP_SOR_NOT_DELAYED		|	\
-	EBC0_BNAP_BEM_RW			|	\
-	EBC0_BNAP_PEN_DISABLED
-
-
-#define EBC0_BNCR_NAND_FLASH_CS0	0xB8400000
-
-/* NAND0 */
-#define EBC0_BNCR_NAND_FLASH_CS1			\
-	EBC0_BNCR_BAS_ENCODE(0x90000000)	|	\
-	EBC0_BNCR_BS_1MB			|	\
-	EBC0_BNCR_BU_RW				|	\
-	EBC0_BNCR_BW_32BIT
-/* NAND1 - Bank2 */
-#define EBC0_BNCR_NAND_FLASH_CS2			\
-	EBC0_BNCR_BAS_ENCODE(0x94000000)	|	\
-	EBC0_BNCR_BS_1MB			|	\
-	EBC0_BNCR_BU_RW				|	\
-	EBC0_BNCR_BW_32BIT
-
-/* NAND1 - Bank3 */
-#define EBC0_BNCR_NAND_FLASH_CS3			\
-	EBC0_BNCR_BAS_ENCODE(0x94000000)	|	\
-	EBC0_BNCR_BS_1MB			|	\
-	EBC0_BNCR_BU_RW				|	\
-	EBC0_BNCR_BW_32BIT
-
-int board_early_init_f(void)
-{
-	ext_bus_cntlr_init();
-
-	/*--------------------------------------------------------------------
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 *-------------------------------------------------------------------*/
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all */
-	mtdcr(UIC0CR, 0x00000009);	/* ATI & UIC1 crit are critical */
-	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
-	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
-	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC1ER, 0x00000000);	/* disable all */
-	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
-	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-
-	/*--------------------------------------------------------------------
-	 * Setup the GPIO pins
-	 *-------------------------------------------------------------------*/
-	out32(GPIO0_OSRL,  0x00000400);
-	out32(GPIO0_OSRH,  0x00000000);
-	out32(GPIO0_TSRL,  0x00000400);
-	out32(GPIO0_TSRH,  0x00000000);
-	out32(GPIO0_ISR1L, 0x00000000);
-	out32(GPIO0_ISR1H, 0x00000000);
-	out32(GPIO0_ISR2L, 0x00000000);
-	out32(GPIO0_ISR2H, 0x00000000);
-	out32(GPIO0_ISR3L, 0x00000000);
-	out32(GPIO0_ISR3H, 0x00000000);
-
-	out32(GPIO1_OSRL,  0x0C380000);
-	out32(GPIO1_OSRH,  0x00000000);
-	out32(GPIO1_TSRL,  0x0C380000);
-	out32(GPIO1_TSRH,  0x00000000);
-	out32(GPIO1_ISR1L, 0x0FC30000);
-	out32(GPIO1_ISR1H, 0x00000000);
-	out32(GPIO1_ISR2L, 0x0C010000);
-	out32(GPIO1_ISR2H, 0x00000000);
-	out32(GPIO1_ISR3L, 0x01400000);
-	out32(GPIO1_ISR3H, 0x00000000);
-
-	configure_ppc440ep_pins();
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return (0);
-}
-
-
-phys_size_t initdram (int board_type)
-{
-	long dram_size;
-
-	dram_size = spd_sdram();
-
-	return dram_size;
-}
-
-/*----------------------------------------------------------------------------+
-  | is_powerpc440ep_pass1.
-  +----------------------------------------------------------------------------*/
-int is_powerpc440ep_pass1(void)
-{
-	unsigned long pvr;
-
-	pvr = get_pvr();
-
-	if (pvr == PVR_POWERPC_440EP_PASS1)
-		return true;
-	else if (pvr == PVR_POWERPC_440EP_PASS2)
-		return false;
-	else {
-		printf("brdutil error 3\n");
-		for (;;)
-			;
-	}
-
-	return false;
-}
-
-/*----------------------------------------------------------------------------+
-  | is_nand_selected.
-  +----------------------------------------------------------------------------*/
-int is_nand_selected(void)
-{
-#ifdef CONFIG_BAMBOO_NAND
-	return true;
-#else
-	return false;
-#endif
-}
-
-/*----------------------------------------------------------------------------+
-  | config_on_ebc_cs4_is_small_flash => from EPLD
-  +----------------------------------------------------------------------------*/
-unsigned char config_on_ebc_cs4_is_small_flash(void)
-{
-	/* Not implemented yet => returns constant value */
-	return true;
-}
-
-/*----------------------------------------------------------------------------+
-  | Ext_bus_cntlr_init.
-  | Initialize the external bus controller
-  +----------------------------------------------------------------------------*/
-void ext_bus_cntlr_init(void)
-{
-	unsigned long sdr0_pstrp0, sdr0_sdstp1;
-	unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
-	int	      computed_boot_device = BOOT_DEVICE_UNKNOWN;
-	unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
-	unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
-	unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
-	unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
-	unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
-
-
-	/*-------------------------------------------------------------------------+
-	  |
-	  |  PART 1 : Initialize EBC Bank 5
-	  |  ==============================
-	  | Bank5 is always associated to the NVRAM/EPLD.
-	  | It has to be initialized prior to other banks settings computation since
-	  | some board registers values may be needed
-	  |
-	  +-------------------------------------------------------------------------*/
-	/* NVRAM - FPGA */
-	mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA);
-	mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5);
-
-	/*-------------------------------------------------------------------------+
-	  |
-	  |  PART 2 : Determine which boot device was selected
-	  |  =========================================
-	  |
-	  |  Read Pin Strap Register in PPC440EP
-	  |  In case of boot from IIC, read Serial Device Strap Register1
-	  |
-	  |  Result can either be :
-	  |   - Boot from EBC 8bits    => SMALL FLASH
-	  |   - Boot from EBC 16bits   => Large Flash or SRAM
-	  |   - Boot from NAND Flash
-	  |   - Boot from PCI
-	  |
-	  +-------------------------------------------------------------------------*/
-	/* Read Pin Strap Register in PPC440EP */
-	mfsdr(SDR0_PINSTP, sdr0_pstrp0);
-	bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
-
-	/*-------------------------------------------------------------------------+
-	  |  PPC440EP Pass1
-	  +-------------------------------------------------------------------------*/
-	if (is_powerpc440ep_pass1() == true) {
-		switch(bootstrap_settings) {
-		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
-			/* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
-			/* Boot from Small Flash */
-			computed_boot_device = BOOT_FROM_SMALL_FLASH;
-			break;
-		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
-			/* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
-			/* Boot from PCI */
-			computed_boot_device = BOOT_FROM_PCI;
-			break;
-
-		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
-			/* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
-			/* Boot from Nand Flash */
-			computed_boot_device = BOOT_FROM_NAND_FLASH0;
-			break;
-
-		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
-			/* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
-			/* Boot from Small Flash */
-			computed_boot_device = BOOT_FROM_SMALL_FLASH;
-			break;
-
-		case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
-		case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
-			/* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
-			/* Read Serial Device Strap Register1 in PPC440EP */
-			mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
-			boot_selection	= sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
-			ebc_boot_size	= sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
-
-			switch(boot_selection) {
-			case SDR0_SDSTP1_BOOT_SEL_EBC:
-				switch(ebc_boot_size) {
-				case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
-					computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
-					break;
-				case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
-					computed_boot_device = BOOT_FROM_SMALL_FLASH;
-					break;
-				}
-				break;
-
-			case SDR0_SDSTP1_BOOT_SEL_PCI:
-				computed_boot_device = BOOT_FROM_PCI;
-				break;
-
-			case SDR0_SDSTP1_BOOT_SEL_NDFC:
-				computed_boot_device = BOOT_FROM_NAND_FLASH0;
-				break;
-			}
-			break;
-		}
-	}
-
-	/*-------------------------------------------------------------------------+
-	  |  PPC440EP Pass2
-	  +-------------------------------------------------------------------------*/
-	else {
-		switch(bootstrap_settings) {
-		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
-			/* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
-			/* Boot from Small Flash */
-			computed_boot_device = BOOT_FROM_SMALL_FLASH;
-			break;
-		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
-			/* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
-			/* Boot from PCI */
-			computed_boot_device = BOOT_FROM_PCI;
-			break;
-
-		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
-			/* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
-			/* Boot from Nand Flash */
-			computed_boot_device = BOOT_FROM_NAND_FLASH0;
-			break;
-
-		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
-			/* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
-			/* Boot from Large Flash or SRAM */
-			computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
-			break;
-
-		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
-			/* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
-			/* Boot from Large Flash or SRAM */
-			computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
-			break;
-
-		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
-			/* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
-			/* Boot from PCI */
-			computed_boot_device = BOOT_FROM_PCI;
-			break;
-
-		case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
-		case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
-			/* Default Strap Settings 5-7 */
-			/* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
-			/* Read Serial Device Strap Register1 in PPC440EP */
-			mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
-			boot_selection	= sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
-			ebc_boot_size	= sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
-
-			switch(boot_selection) {
-			case SDR0_SDSTP1_BOOT_SEL_EBC:
-				switch(ebc_boot_size) {
-				case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
-					computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
-					break;
-				case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
-					computed_boot_device = BOOT_FROM_SMALL_FLASH;
-					break;
-				}
-				break;
-
-			case SDR0_SDSTP1_BOOT_SEL_PCI:
-				computed_boot_device = BOOT_FROM_PCI;
-				break;
-
-			case SDR0_SDSTP1_BOOT_SEL_NDFC:
-				computed_boot_device = BOOT_FROM_NAND_FLASH0;
-				break;
-			}
-			break;
-		}
-	}
-
-	/*-------------------------------------------------------------------------+
-	  |
-	  |  PART 3 : Compute EBC settings depending on selected boot device
-	  |  ======   ======================================================
-	  |
-	  | Resulting EBC init will be among following configurations :
-	  |
-	  |  - Boot from EBC 8bits => boot from SMALL FLASH selected
-	  |	       EBC-CS0	   = Small Flash
-	  |	       EBC-CS1,2,3 = NAND Flash or
-	  |			    Exp.Slot depending on Soft Config
-	  |	       EBC-CS4	   = SRAM/Large Flash or
-	  |			    Large Flash/SRAM depending on jumpers
-	  |	       EBC-CS5	   = NVRAM / EPLD
-	  |
-	  |  - Boot from EBC 16bits => boot from Large Flash or SRAM selected
-	  |	       EBC-CS0	   = SRAM/Large Flash or
-	  |			     Large Flash/SRAM depending on jumpers
-	  |	       EBC-CS1,2,3 = NAND Flash or
-	  |			     Exp.Slot depending on Software Configuration
-	  |	       EBC-CS4	   = Small Flash
-	  |	       EBC-CS5	   = NVRAM / EPLD
-	  |
-	  |  - Boot from NAND Flash
-	  |	       EBC-CS0	   = NAND Flash0
-	  |	       EBC-CS1,2,3 = NAND Flash1
-	  |	       EBC-CS4	   = SRAM/Large Flash or
-	  |			     Large Flash/SRAM depending on jumpers
-	  |	       EBC-CS5	   = NVRAM / EPLD
-	  |
-	  |    - Boot from PCI
-	  |	       EBC-CS0	   = ...
-	  |	       EBC-CS1,2,3 = NAND Flash or
-	  |			     Exp.Slot depending on Software Configuration
-	  |	       EBC-CS4	   = SRAM/Large Flash or
-	  |			     Large Flash/SRAM or
-	  |			     Small Flash depending on jumpers
-	  |	       EBC-CS5	   = NVRAM / EPLD
-	  |
-	  +-------------------------------------------------------------------------*/
-
-	switch(computed_boot_device) {
-		/*------------------------------------------------------------------------- */
-	case BOOT_FROM_SMALL_FLASH:
-		/*------------------------------------------------------------------------- */
-		ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
-		ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
-		if ((is_nand_selected()) == true) {
-			/* NAND Flash */
-			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
-			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
-			ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
-			ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
-			ebc0_cs3_bnap_value = 0;
-			ebc0_cs3_bncr_value = 0;
-		} else {
-			/* Expansion Slot */
-			ebc0_cs1_bnap_value = 0;
-			ebc0_cs1_bncr_value = 0;
-			ebc0_cs2_bnap_value = 0;
-			ebc0_cs2_bncr_value = 0;
-			ebc0_cs3_bnap_value = 0;
-			ebc0_cs3_bncr_value = 0;
-		}
-		ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
-		ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
-
-		break;
-
-		/*------------------------------------------------------------------------- */
-	case BOOT_FROM_LARGE_FLASH_OR_SRAM:
-		/*------------------------------------------------------------------------- */
-		ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
-		ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
-		if ((is_nand_selected()) == true) {
-			/* NAND Flash */
-			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
-			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
-			ebc0_cs2_bnap_value = 0;
-			ebc0_cs2_bncr_value = 0;
-			ebc0_cs3_bnap_value = 0;
-			ebc0_cs3_bncr_value = 0;
-		} else {
-			/* Expansion Slot */
-			ebc0_cs1_bnap_value = 0;
-			ebc0_cs1_bncr_value = 0;
-			ebc0_cs2_bnap_value = 0;
-			ebc0_cs2_bncr_value = 0;
-			ebc0_cs3_bnap_value = 0;
-			ebc0_cs3_bncr_value = 0;
-		}
-		ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
-		ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
-
-		break;
-
-		/*------------------------------------------------------------------------- */
-	case BOOT_FROM_NAND_FLASH0:
-		/*------------------------------------------------------------------------- */
-		ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
-		ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
-
-		ebc0_cs1_bnap_value = 0;
-		ebc0_cs1_bncr_value = 0;
-		ebc0_cs2_bnap_value = 0;
-		ebc0_cs2_bncr_value = 0;
-		ebc0_cs3_bnap_value = 0;
-		ebc0_cs3_bncr_value = 0;
-
-		/* Large Flash or SRAM */
-		ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
-		ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
-
-		break;
-
-		/*------------------------------------------------------------------------- */
-	case BOOT_FROM_PCI:
-		/*------------------------------------------------------------------------- */
-		ebc0_cs0_bnap_value = 0;
-		ebc0_cs0_bncr_value = 0;
-
-		if ((is_nand_selected()) == true) {
-			/* NAND Flash */
-			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
-			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
-			ebc0_cs2_bnap_value = 0;
-			ebc0_cs2_bncr_value = 0;
-			ebc0_cs3_bnap_value = 0;
-			ebc0_cs3_bncr_value = 0;
-		} else {
-			/* Expansion Slot */
-			ebc0_cs1_bnap_value = 0;
-			ebc0_cs1_bncr_value = 0;
-			ebc0_cs2_bnap_value = 0;
-			ebc0_cs2_bncr_value = 0;
-			ebc0_cs3_bnap_value = 0;
-			ebc0_cs3_bncr_value = 0;
-		}
-
-		if ((config_on_ebc_cs4_is_small_flash()) == true) {
-			/* Small Flash */
-			ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
-			ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
-		} else {
-			/* Large Flash or SRAM */
-			ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
-			ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
-		}
-
-		break;
-
-		/*------------------------------------------------------------------------- */
-	case BOOT_DEVICE_UNKNOWN:
-		/*------------------------------------------------------------------------- */
-		/* Error */
-		break;
-
-	}
-
-
-	/*-------------------------------------------------------------------------+
-	  | Initialize EBC CONFIG
-	  +-------------------------------------------------------------------------*/
-	mtdcr(EBC0_CFGADDR, EBC0_CFG);
-	mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN	   |
-	      EBC0_CFG_PTD_ENABLED	  |
-	      EBC0_CFG_RTC_2048PERCLK	  |
-	      EBC0_CFG_EMPL_LOW		  |
-	      EBC0_CFG_EMPH_LOW		  |
-	      EBC0_CFG_CSTC_DRIVEN	  |
-	      EBC0_CFG_BPF_ONEDW	  |
-	      EBC0_CFG_EMS_8BIT		  |
-	      EBC0_CFG_PME_DISABLED	  |
-	      EBC0_CFG_PMT_ENCODE(0)	  );
-
-	/*-------------------------------------------------------------------------+
-	  | Initialize EBC Bank 0-4
-	  +-------------------------------------------------------------------------*/
-	/* EBC Bank0 */
-	mtebc(PB0AP, ebc0_cs0_bnap_value);
-	mtebc(PB0CR, ebc0_cs0_bncr_value);
-	/* EBC Bank1 */
-	mtebc(PB1AP, ebc0_cs1_bnap_value);
-	mtebc(PB1CR, ebc0_cs1_bncr_value);
-	/* EBC Bank2 */
-	mtebc(PB2AP, ebc0_cs2_bnap_value);
-	mtebc(PB2CR, ebc0_cs2_bncr_value);
-	/* EBC Bank3 */
-	mtebc(PB3AP, ebc0_cs3_bnap_value);
-	mtebc(PB3CR, ebc0_cs3_bncr_value);
-	/* EBC Bank4 */
-	mtebc(PB4AP, ebc0_cs4_bnap_value);
-	mtebc(PB4CR, ebc0_cs4_bncr_value);
-
-	return;
-}
-
-
-/*----------------------------------------------------------------------------+
-  | get_uart_configuration.
-  +----------------------------------------------------------------------------*/
-uart_config_nb_t get_uart_configuration(void)
-{
-	return (L4);
-}
-
-/*----------------------------------------------------------------------------+
-  | set_phy_configuration_through_fpga => to EPLD
-  +----------------------------------------------------------------------------*/
-void set_phy_configuration_through_fpga(zmii_config_t config)
-{
-
-	unsigned long fpga_selection_reg;
-
-	fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
-
-	switch(config)
-	{
-	case ZMII_CONFIGURATION_IS_MII:
-		fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
-		break;
-	case ZMII_CONFIGURATION_IS_RMII:
-		fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
-		break;
-	case ZMII_CONFIGURATION_IS_SMII:
-		fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
-		break;
-	case ZMII_CONFIGURATION_UNKNOWN:
-	default:
-		break;
-	}
-	out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
-
-}
-
-/*----------------------------------------------------------------------------+
-  | scp_selection_in_fpga.
-  +----------------------------------------------------------------------------*/
-void scp_selection_in_fpga(void)
-{
-	unsigned long fpga_selection_2_reg;
-
-	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
-	fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
-	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
-  | iic1_selection_in_fpga.
-  +----------------------------------------------------------------------------*/
-void iic1_selection_in_fpga(void)
-{
-	unsigned long fpga_selection_2_reg;
-
-	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
-	fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
-	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
-  | dma_a_b_selection_in_fpga.
-  +----------------------------------------------------------------------------*/
-void dma_a_b_selection_in_fpga(void)
-{
-	unsigned long fpga_selection_2_reg;
-
-	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
-	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
-  | dma_a_b_unselect_in_fpga.
-  +----------------------------------------------------------------------------*/
-void dma_a_b_unselect_in_fpga(void)
-{
-	unsigned long fpga_selection_2_reg;
-
-	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
-	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
-  | dma_c_d_selection_in_fpga.
-  +----------------------------------------------------------------------------*/
-void dma_c_d_selection_in_fpga(void)
-{
-	unsigned long fpga_selection_2_reg;
-
-	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
-	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
-  | dma_c_d_unselect_in_fpga.
-  +----------------------------------------------------------------------------*/
-void dma_c_d_unselect_in_fpga(void)
-{
-	unsigned long fpga_selection_2_reg;
-
-	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
-	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
-}
-
-/*----------------------------------------------------------------------------+
-  | usb2_device_selection_in_fpga.
-  +----------------------------------------------------------------------------*/
-void usb2_device_selection_in_fpga(void)
-{
-	unsigned long fpga_selection_1_reg;
-
-	fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
-	out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
-}
-
-/*----------------------------------------------------------------------------+
-  | usb2_device_reset_through_fpga.
-  +----------------------------------------------------------------------------*/
-void usb2_device_reset_through_fpga(void)
-{
-	/* Perform soft Reset pulse */
-	unsigned long fpga_reset_reg;
-	int i;
-
-	fpga_reset_reg = in8(FPGA_RESET_REG);
-	out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
-	for (i=0; i<500; i++)
-		udelay(1000);
-	out8(FPGA_RESET_REG,fpga_reset_reg);
-}
-
-/*----------------------------------------------------------------------------+
-  | usb2_host_selection_in_fpga.
-  +----------------------------------------------------------------------------*/
-void usb2_host_selection_in_fpga(void)
-{
-	unsigned long fpga_selection_1_reg;
-
-	fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
-	out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
-}
-
-/*----------------------------------------------------------------------------+
-  | ndfc_selection_in_fpga.
-  +----------------------------------------------------------------------------*/
-void ndfc_selection_in_fpga(void)
-{
-	unsigned long fpga_selection_1_reg;
-
-	fpga_selection_1_reg  = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
-	fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
-	fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
-	out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
-}
-
-/*----------------------------------------------------------------------------+
-  | uart_selection_in_fpga.
-  +----------------------------------------------------------------------------*/
-void uart_selection_in_fpga(uart_config_nb_t uart_config)
-{
-	/* FPGA register */
-	unsigned char	fpga_selection_3_reg;
-
-	/* Read FPGA Reagister */
-	fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
-
-	switch (uart_config)
-	{
-	case L1:
-		/* ----------------------------------------------------------------------- */
-		/* L1 configuration:	UART0 = 8 pins */
-		/* ----------------------------------------------------------------------- */
-		/* Configure FPGA */
-		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
-		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
-		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
-
-		break;
-
-	case L2:
-		/* ----------------------------------------------------------------------- */
-		/* L2 configuration:	UART0 = 4 pins */
-		/*			UART1 = 4 pins */
-		/* ----------------------------------------------------------------------- */
-		/* Configure FPGA */
-		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
-		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
-		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
-
-		break;
-
-	case L3:
-		/* ----------------------------------------------------------------------- */
-		/* L3 configuration:	UART0 = 4 pins */
-		/*			UART1 = 2 pins */
-		/*			UART2 = 2 pins */
-		/* ----------------------------------------------------------------------- */
-		/* Configure FPGA */
-		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
-		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
-		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
-		break;
-
-	case L4:
-		/* Configure FPGA */
-		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
-		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
-		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
-
-		break;
-
-	default:
-		/* Unsupported UART configuration number */
-		for (;;)
-			;
-		break;
-
-	}
-}
-
-
-/*----------------------------------------------------------------------------+
-  | init_default_gpio
-  +----------------------------------------------------------------------------*/
-void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
-	int i;
-
-	/* Init GPIO0 */
-	for(i=0; i<GPIO_MAX; i++)
-	{
-		gpio_tab[GPIO0][i].add	  = GPIO0_BASE;
-		gpio_tab[GPIO0][i].in_out = GPIO_DIS;
-		gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
-	}
-
-	/* Init GPIO1 */
-	for(i=0; i<GPIO_MAX; i++)
-	{
-		gpio_tab[GPIO1][i].add	  = GPIO1_BASE;
-		gpio_tab[GPIO1][i].in_out = GPIO_DIS;
-		gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
-	}
-
-	/* EBC_CS_N(5) - GPIO0_10 */
-	gpio_tab[GPIO0][10].in_out    = GPIO_OUT;
-	gpio_tab[GPIO0][10].alt_nb    = GPIO_ALT1;
-
-	/* EBC_CS_N(4) - GPIO0_9 */
-	gpio_tab[GPIO0][9].in_out    = GPIO_OUT;
-	gpio_tab[GPIO0][9].alt_nb    = GPIO_ALT1;
-}
-
-/*----------------------------------------------------------------------------+
-  | update_uart_ios
-  +------------------------------------------------------------------------------
-  |
-  | Set UART Configuration in PowerPC440EP
-  |
-  | +---------------------------------------------------------------------+
-  | | Configuartion   |	  Connector   | Nb of pins | Pins   | Associated  |
-  | |	 Number	      |	  Port Name   |	 available | naming |	CORE	  |
-  | +-----------------+---------------+------------+--------+-------------+
-  | |	  L1	      |	  Port_A      |	    8	   | UART   | UART core 0 |
-  | +-----------------+---------------+------------+--------+-------------+
-  | |	  L2	      |	  Port_A      |	    4	   | UART1  | UART core 0 |
-  | |	 (L2D)	      |	  Port_B      |	    4	   | UART2  | UART core 1 |
-  | +-----------------+---------------+------------+--------+-------------+
-  | |	  L3	      |	  Port_A      |	    4	   | UART1  | UART core 0 |
-  | |	 (L3D)	      |	  Port_B      |	    2	   | UART2  | UART core 1 |
-  | |		      |	  Port_C      |	    2	   | UART3  | UART core 2 |
-  | +-----------------+---------------+------------+--------+-------------+
-  | |		      |	  Port_A      |	    2	   | UART1  | UART core 0 |
-  | |	  L4	      |	  Port_B      |	    2	   | UART2  | UART core 1 |
-  | |	 (L4D)	      |	  Port_C      |	    2	   | UART3  | UART core 2 |
-  | |		      |	  Port_D      |	    2	   | UART4  | UART core 3 |
-  | +-----------------+---------------+------------+--------+-------------+
-  |
-  |  Involved GPIOs
-  |
-  | +------------------------------------------------------------------------------+
-  | |  GPIO   |	  Aternate 1	 | I/O |  Alternate 2	 | I/O | Alternate 3 | I/O |
-  | +---------+------------------+-----+-----------------+-----+-------------+-----+
-  | | GPIO1_2 | UART0_DCD_N	 |  I  | UART1_DSR_CTS_N |  I  | UART2_SOUT  |	O  |
-  | | GPIO1_3 | UART0_8PIN_DSR_N |  I  | UART1_RTS_DTR_N |  O  | UART2_SIN   |	I  |
-  | | GPIO1_4 | UART0_8PIN_CTS_N |  I  | NA		 |  NA | UART3_SIN   |	I  |
-  | | GPIO1_5 | UART0_RTS_N	 |  O  | NA		 |  NA | UART3_SOUT  |	O  |
-  | | GPIO1_6 | UART0_DTR_N	 |  O  | UART1_SOUT	 |  O  | NA	     |	NA |
-  | | GPIO1_7 | UART0_RI_N	 |  I  | UART1_SIN	 |  I  | NA	     |	NA |
-  | +------------------------------------------------------------------------------+
-  |
-  |
-  +----------------------------------------------------------------------------*/
-
-void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
-	switch (uart_config)
-	{
-	case L1:
-		/* ----------------------------------------------------------------------- */
-		/* L1 configuration:	UART0 = 8 pins */
-		/* ----------------------------------------------------------------------- */
-		/* Update GPIO Configuration Table */
-		gpio_tab[GPIO1][2].in_out = GPIO_IN;
-		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
-
-		gpio_tab[GPIO1][3].in_out = GPIO_IN;
-		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
-
-		gpio_tab[GPIO1][4].in_out = GPIO_IN;
-		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
-
-		gpio_tab[GPIO1][5].in_out = GPIO_OUT;
-		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
-
-		gpio_tab[GPIO1][6].in_out = GPIO_OUT;
-		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
-
-		gpio_tab[GPIO1][7].in_out = GPIO_IN;
-		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
-
-		break;
-
-	case L2:
-		/* ----------------------------------------------------------------------- */
-		/* L2 configuration:	UART0 = 4 pins */
-		/*			UART1 = 4 pins */
-		/* ----------------------------------------------------------------------- */
-		/* Update GPIO Configuration Table */
-		gpio_tab[GPIO1][2].in_out = GPIO_IN;
-		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
-
-		gpio_tab[GPIO1][3].in_out = GPIO_OUT;
-		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
-
-		gpio_tab[GPIO1][4].in_out = GPIO_IN;
-		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
-
-		gpio_tab[GPIO1][5].in_out = GPIO_OUT;
-		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
-
-		gpio_tab[GPIO1][6].in_out = GPIO_OUT;
-		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
-
-		gpio_tab[GPIO1][7].in_out = GPIO_IN;
-		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
-
-		break;
-
-	case L3:
-		/* ----------------------------------------------------------------------- */
-		/* L3 configuration:	UART0 = 4 pins */
-		/*			UART1 = 2 pins */
-		/*			UART2 = 2 pins */
-		/* ----------------------------------------------------------------------- */
-		/* Update GPIO Configuration Table */
-		gpio_tab[GPIO1][2].in_out = GPIO_OUT;
-		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
-
-		gpio_tab[GPIO1][3].in_out = GPIO_IN;
-		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
-
-		gpio_tab[GPIO1][4].in_out = GPIO_IN;
-		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
-
-		gpio_tab[GPIO1][5].in_out = GPIO_OUT;
-		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
-
-		gpio_tab[GPIO1][6].in_out = GPIO_OUT;
-		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
-
-		gpio_tab[GPIO1][7].in_out = GPIO_IN;
-		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
-
-		break;
-
-	case L4:
-		/* ----------------------------------------------------------------------- */
-		/* L4 configuration:	UART0 = 2 pins */
-		/*			UART1 = 2 pins */
-		/*			UART2 = 2 pins */
-		/*			UART3 = 2 pins */
-		/* ----------------------------------------------------------------------- */
-		/* Update GPIO Configuration Table */
-		gpio_tab[GPIO1][2].in_out = GPIO_OUT;
-		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
-
-		gpio_tab[GPIO1][3].in_out = GPIO_IN;
-		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
-
-		gpio_tab[GPIO1][4].in_out = GPIO_IN;
-		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
-
-		gpio_tab[GPIO1][5].in_out = GPIO_OUT;
-		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
-
-		gpio_tab[GPIO1][6].in_out = GPIO_OUT;
-		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
-
-		gpio_tab[GPIO1][7].in_out = GPIO_IN;
-		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
-
-		break;
-
-	default:
-		/* Unsupported UART configuration number */
-		printf("ERROR - Unsupported UART configuration number.\n\n");
-		for (;;)
-			;
-		break;
-
-	}
-
-	/* Set input Selection Register on Alt_Receive for UART Input Core */
-	out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
-	out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
-	out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
-}
-
-/*----------------------------------------------------------------------------+
-  | update_ndfc_ios(void).
-  +----------------------------------------------------------------------------*/
-void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
-	/* Update GPIO Configuration Table */
-	gpio_tab[GPIO0][6].in_out = GPIO_OUT;	    /* EBC_CS_N(1) */
-	gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO0][7].in_out = GPIO_OUT;	    /* EBC_CS_N(2) */
-	gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
-
-#if 0
-	gpio_tab[GPIO0][7].in_out = GPIO_OUT;	    /* EBC_CS_N(3) */
-	gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
-#endif
-}
-
-/*----------------------------------------------------------------------------+
-  | update_zii_ios(void).
-  +----------------------------------------------------------------------------*/
-void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
-	/* Update GPIO Configuration Table */
-	gpio_tab[GPIO0][12].in_out = GPIO_IN;	    /* ZII_p0Rxd(0) */
-	gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO0][13].in_out = GPIO_IN;	    /* ZII_p0Rxd(1) */
-	gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO0][14].in_out = GPIO_IN;	    /* ZII_p0Rxd(2) */
-	gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO0][15].in_out = GPIO_IN;	    /* ZII_p0Rxd(3) */
-	gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO0][16].in_out = GPIO_OUT;	    /* ZII_p0Txd(0) */
-	gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO0][17].in_out = GPIO_OUT;	    /* ZII_p0Txd(1) */
-	gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO0][18].in_out = GPIO_OUT;	    /* ZII_p0Txd(2) */
-	gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO0][19].in_out = GPIO_OUT;	    /* ZII_p0Txd(3) */
-	gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO0][20].in_out = GPIO_IN;	    /* ZII_p0Rx_er */
-	gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO0][21].in_out = GPIO_IN;	    /* ZII_p0Rx_dv */
-	gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO0][22].in_out = GPIO_IN;	    /* ZII_p0Crs */
-	gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO0][23].in_out = GPIO_OUT;	    /* ZII_p0Tx_er */
-	gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO0][24].in_out = GPIO_OUT;	    /* ZII_p0Tx_en */
-	gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO0][25].in_out = GPIO_IN;	    /* ZII_p0Col */
-	gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
-
-}
-
-/*----------------------------------------------------------------------------+
-  | update_uic_0_3_irq_ios().
-  +----------------------------------------------------------------------------*/
-void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
-	gpio_tab[GPIO1][8].in_out = GPIO_IN;	    /* UIC_IRQ(0) */
-	gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO1][9].in_out = GPIO_IN;	    /* UIC_IRQ(1) */
-	gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO1][10].in_out = GPIO_IN;	    /* UIC_IRQ(2) */
-	gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO1][11].in_out = GPIO_IN;	    /* UIC_IRQ(3) */
-	gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
-}
-
-/*----------------------------------------------------------------------------+
-  | update_uic_4_9_irq_ios().
-  +----------------------------------------------------------------------------*/
-void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
-	gpio_tab[GPIO1][12].in_out = GPIO_IN;	    /* UIC_IRQ(4) */
-	gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO1][13].in_out = GPIO_IN;	    /* UIC_IRQ(6) */
-	gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO1][14].in_out = GPIO_IN;	    /* UIC_IRQ(7) */
-	gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO1][15].in_out = GPIO_IN;	    /* UIC_IRQ(8) */
-	gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO1][16].in_out = GPIO_IN;	    /* UIC_IRQ(9) */
-	gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
-}
-
-/*----------------------------------------------------------------------------+
-  | update_dma_a_b_ios().
-  +----------------------------------------------------------------------------*/
-void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
-	gpio_tab[GPIO1][12].in_out = GPIO_OUT;	    /* DMA_ACK(1) */
-	gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
-
-	gpio_tab[GPIO1][13].in_out = GPIO_BI;	    /* DMA_EOT/TC(1) */
-	gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
-
-	gpio_tab[GPIO1][14].in_out = GPIO_IN;	    /* DMA_REQ(0) */
-	gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
-
-	gpio_tab[GPIO1][15].in_out = GPIO_OUT;	    /* DMA_ACK(0) */
-	gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
-
-	gpio_tab[GPIO1][16].in_out = GPIO_BI;	    /* DMA_EOT/TC(0) */
-	gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
-}
-
-/*----------------------------------------------------------------------------+
-  | update_dma_c_d_ios().
-  +----------------------------------------------------------------------------*/
-void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
-	gpio_tab[GPIO0][0].in_out = GPIO_IN;	    /* DMA_REQ(2) */
-	gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
-
-	gpio_tab[GPIO0][1].in_out = GPIO_OUT;	    /* DMA_ACK(2) */
-	gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
-
-	gpio_tab[GPIO0][2].in_out = GPIO_BI;	    /* DMA_EOT/TC(2) */
-	gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
-
-	gpio_tab[GPIO0][3].in_out = GPIO_IN;	    /* DMA_REQ(3) */
-	gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
-
-	gpio_tab[GPIO0][4].in_out = GPIO_OUT;	    /* DMA_ACK(3) */
-	gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
-
-	gpio_tab[GPIO0][5].in_out = GPIO_BI;	    /* DMA_EOT/TC(3) */
-	gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
-
-}
-
-/*----------------------------------------------------------------------------+
-  | update_ebc_master_ios().
-  +----------------------------------------------------------------------------*/
-void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
-	gpio_tab[GPIO0][27].in_out = GPIO_IN;	    /* EXT_EBC_REQ */
-	gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO0][29].in_out = GPIO_OUT;	    /* EBC_EXT_HDLA */
-	gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO0][30].in_out = GPIO_OUT;	    /* EBC_EXT_ACK */
-	gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO0][31].in_out = GPIO_OUT;	    /* EBC_EXR_BUSREQ */
-	gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
-}
-
-/*----------------------------------------------------------------------------+
-  | update_usb2_device_ios().
-  +----------------------------------------------------------------------------*/
-void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
-	gpio_tab[GPIO0][26].in_out = GPIO_IN;	    /* USB2D_RXVALID */
-	gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
-
-	gpio_tab[GPIO0][27].in_out = GPIO_IN;	    /* USB2D_RXERROR */
-	gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
-
-	gpio_tab[GPIO0][28].in_out = GPIO_OUT;	    /* USB2D_TXVALID */
-	gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
-
-	gpio_tab[GPIO0][29].in_out = GPIO_OUT;	    /* USB2D_PAD_SUSPNDM */
-	gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
-
-	gpio_tab[GPIO0][30].in_out = GPIO_OUT;	    /* USB2D_XCVRSELECT */
-	gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
-
-	gpio_tab[GPIO0][31].in_out = GPIO_OUT;	    /* USB2D_TERMSELECT */
-	gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
-
-	gpio_tab[GPIO1][0].in_out = GPIO_OUT;	    /* USB2D_OPMODE0 */
-	gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
-
-	gpio_tab[GPIO1][1].in_out = GPIO_OUT;	    /* USB2D_OPMODE1 */
-	gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
-
-}
-
-/*----------------------------------------------------------------------------+
-  | update_pci_patch_ios().
-  +----------------------------------------------------------------------------*/
-void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
-	gpio_tab[GPIO0][29].in_out = GPIO_OUT;	    /* EBC_EXT_HDLA */
-	gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
-}
-
-/*----------------------------------------------------------------------------+
-  |   set_chip_gpio_configuration(unsigned char gpio_core,
-  |                               gpio_param_s (*gpio_tab)[GPIO_MAX])
-  |   Put the core impacted by clock modification and sharing in reset.
-  |   Config the select registers to resolve the sharing depending of the config.
-  |   Configure the GPIO registers.
-  |
-  +----------------------------------------------------------------------------*/
-void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
-{
-	unsigned char i=0, j=0, reg_offset = 0;
-	unsigned long gpio_reg, gpio_core_add;
-
-	/* GPIO config of the GPIOs 0 to 31 */
-	for (i=0; i<GPIO_MAX; i++, j++)
-	{
-		if (i == GPIO_MAX/2)
-		{
-			reg_offset = 4;
-			j = i-16;
-		}
-
-		gpio_core_add = gpio_tab[gpio_core][i].add;
-
-		if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
-		     (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
-		{
-			switch (gpio_tab[gpio_core][i].alt_nb)
-			{
-			case GPIO_SEL:
-				break;
-
-			case GPIO_ALT1:
-				gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
-				gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
-				out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
-				break;
-
-			case GPIO_ALT2:
-				gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
-				gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
-				out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
-				break;
-
-			case GPIO_ALT3:
-				gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
-				gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
-				out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
-				break;
-			}
-		}
-		if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
-		     (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
-		{
-
-			switch (gpio_tab[gpio_core][i].alt_nb)
-			{
-			case GPIO_SEL:
-				break;
-			case GPIO_ALT1:
-				gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
-				gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
-				out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
-				gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
-				gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
-				out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
-				break;
-			case GPIO_ALT2:
-				gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
-				gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
-				out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
-				gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
-				gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
-				out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
-				break;
-			case GPIO_ALT3:
-				gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
-				gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
-				out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
-				gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
-				gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
-				out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
-				break;
-			}
-		}
-	}
-}
-
-/*----------------------------------------------------------------------------+
-  | force_bup_core_selection.
-  +----------------------------------------------------------------------------*/
-void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
-{
-	/* Pointer invalid */
-	if (core_select_P == NULL)
-	{
-		printf("Configuration invalid pointer 1\n");
-		for (;;)
-			;
-	}
-
-	/* L4 Selection */
-	*(core_select_P+UART_CORE0)	       = CORE_SELECTED;
-	*(core_select_P+UART_CORE1)	       = CORE_SELECTED;
-	*(core_select_P+UART_CORE2)	       = CORE_SELECTED;
-	*(core_select_P+UART_CORE3)	       = CORE_SELECTED;
-
-	/* RMII Selection */
-	*(core_select_P+RMII_SEL)		= CORE_SELECTED;
-
-	/* External Interrupt 0-9 selection */
-	*(core_select_P+UIC_0_3)		= CORE_SELECTED;
-	*(core_select_P+UIC_4_9)		= CORE_SELECTED;
-
-	*(core_select_P+SCP_CORE)	        = CORE_SELECTED;
-	*(core_select_P+DMA_CHANNEL_CD)		= CORE_SELECTED;
-	*(core_select_P+PACKET_REJ_FUNC_AVAIL)	= CORE_SELECTED;
-	*(core_select_P+USB1_DEVICE)		= CORE_SELECTED;
-
-	if (is_nand_selected()) {
-		*(core_select_P+NAND_FLASH)	= CORE_SELECTED;
-	}
-
-	*config_val_P = CONFIG_IS_VALID;
-
-}
-
-/*----------------------------------------------------------------------------+
-  | configure_ppc440ep_pins.
-  +----------------------------------------------------------------------------*/
-void configure_ppc440ep_pins(void)
-{
-	uart_config_nb_t uart_configuration;
-	config_validity_t config_val = CONFIG_IS_INVALID;
-
-	/* Create Core Selection Table */
-	core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
-		{
-			CORE_NOT_SELECTED,	/* IIC_CORE, */
-			CORE_NOT_SELECTED,	/* SPC_CORE, */
-			CORE_NOT_SELECTED,	/* DMA_CHANNEL_AB, */
-			CORE_NOT_SELECTED,	/* UIC_4_9, */
-			CORE_NOT_SELECTED,	/* USB2_HOST, */
-			CORE_NOT_SELECTED,	/* DMA_CHANNEL_CD, */
-			CORE_NOT_SELECTED,	/* USB2_DEVICE, */
-			CORE_NOT_SELECTED,	/* PACKET_REJ_FUNC_AVAIL, */
-			CORE_NOT_SELECTED,	/* USB1_DEVICE, */
-			CORE_NOT_SELECTED,	/* EBC_MASTER, */
-			CORE_NOT_SELECTED,	/* NAND_FLASH, */
-			CORE_NOT_SELECTED,	/* UART_CORE0, */
-			CORE_NOT_SELECTED,	/* UART_CORE1, */
-			CORE_NOT_SELECTED,	/* UART_CORE2, */
-			CORE_NOT_SELECTED,	/* UART_CORE3, */
-			CORE_NOT_SELECTED,	/* MII_SEL, */
-			CORE_NOT_SELECTED,	/* RMII_SEL, */
-			CORE_NOT_SELECTED,	/* SMII_SEL, */
-			CORE_NOT_SELECTED,	/* PACKET_REJ_FUNC_EN */
-			CORE_NOT_SELECTED,	/* UIC_0_3 */
-			CORE_NOT_SELECTED,	/* USB1_HOST */
-			CORE_NOT_SELECTED	/* PCI_PATCH */
-		};
-
-	gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
-
-	/* Table Default Initialisation + FPGA Access */
-	init_default_gpio(gpio_tab);
-	set_chip_gpio_configuration(GPIO0, gpio_tab);
-	set_chip_gpio_configuration(GPIO1, gpio_tab);
-
-	/* Update Table */
-	force_bup_core_selection(ppc440ep_core_selection, &config_val);
-#if 0 /* test-only */
-	/* If we are running PIBS 1, force known configuration */
-	update_core_selection_table(ppc440ep_core_selection, &config_val);
-#endif
-
-	/*----------------------------------------------------------------------------+
-	  | SDR + ios table update + fpga initialization
-	  +----------------------------------------------------------------------------*/
-	unsigned long sdr0_pfc1	    = 0;
-	unsigned long sdr0_usb0	    = 0;
-	unsigned long sdr0_mfr	    = 0;
-
-	/* PCI Always selected */
-
-	/* I2C Selection */
-	if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
-	{
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
-		iic1_selection_in_fpga();
-	}
-
-	/* SCP Selection */
-	if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
-	{
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
-		scp_selection_in_fpga();
-	}
-
-	/* UIC 0:3 Selection */
-	if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
-	{
-		update_uic_0_3_irq_ios(gpio_tab);
-		dma_a_b_unselect_in_fpga();
-	}
-
-	/* UIC 4:9 Selection */
-	if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
-	{
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
-		update_uic_4_9_irq_ios(gpio_tab);
-	}
-
-	/* DMA AB Selection */
-	if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
-	{
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
-		update_dma_a_b_ios(gpio_tab);
-		dma_a_b_selection_in_fpga();
-	}
-
-	/* DMA CD Selection */
-	if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
-	{
-		update_dma_c_d_ios(gpio_tab);
-		dma_c_d_selection_in_fpga();
-	}
-
-	/* EBC Master Selection */
-	if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
-	{
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
-		update_ebc_master_ios(gpio_tab);
-	}
-
-	/* PCI Patch Enable */
-	if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
-	{
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
-		update_pci_patch_ios(gpio_tab);
-	}
-
-	/* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
-	if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
-	{
-		/* Not Implemented in PowerPC 440EP Pass1-Pass2 */
-		printf("Invalid configuration => USB2 Host selected\n");
-		for (;;)
-			;
-		/*usb2_host_selection_in_fpga(); */
-	}
-
-	/* USB2.0 Device Selection */
-	if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
-	{
-		update_usb2_device_ios(gpio_tab);
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
-
-		mfsdr(SDR0_USB0, sdr0_usb0);
-		sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
-		sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
-		mtsdr(SDR0_USB0, sdr0_usb0);
-
-		usb2_device_selection_in_fpga();
-	}
-
-	/* USB1.1 Device Selection */
-	if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
-	{
-		mfsdr(SDR0_USB0, sdr0_usb0);
-		sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
-		sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
-		mtsdr(SDR0_USB0, sdr0_usb0);
-	}
-
-	/* USB1.1 Host Selection */
-	if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
-	{
-		mfsdr(SDR0_USB0, sdr0_usb0);
-		sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
-		sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
-		mtsdr(SDR0_USB0, sdr0_usb0);
-	}
-
-	/* NAND Flash Selection */
-	if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
-	{
-		update_ndfc_ios(gpio_tab);
-		mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL   |
-		      SDR0_CUST0_NDFC_ENABLE	|
-		      SDR0_CUST0_NDFC_BW_8_BIT	|
-		      SDR0_CUST0_NDFC_ARE_MASK	|
-		      SDR0_CUST0_CHIPSELGAT_EN1 |
-		      SDR0_CUST0_CHIPSELGAT_EN2);
-		ndfc_selection_in_fpga();
-	}
-	else
-	{
-		/* Set Mux on EMAC */
-		mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL);
-	}
-
-	/* MII Selection */
-	if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
-	{
-		update_zii_ios(gpio_tab);
-		mfsdr(SDR0_MFR, sdr0_mfr);
-		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
-		mtsdr(SDR0_MFR, sdr0_mfr);
-
-		set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
-	}
-
-	/* RMII Selection */
-	if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
-	{
-		update_zii_ios(gpio_tab);
-		mfsdr(SDR0_MFR, sdr0_mfr);
-		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
-		mtsdr(SDR0_MFR, sdr0_mfr);
-
-		set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
-	}
-
-	/* SMII Selection */
-	if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
-	{
-		update_zii_ios(gpio_tab);
-		mfsdr(SDR0_MFR, sdr0_mfr);
-		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
-		mtsdr(SDR0_MFR, sdr0_mfr);
-
-		set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
-	}
-
-	/* UART Selection */
-	uart_configuration = get_uart_configuration();
-	switch (uart_configuration)
-	{
-	case L1:	 /* L1 Selection */
-		/* UART0 8 pins Only */
-		/*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS;	  /* Chip Pb */
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
-		break;
-	case L2:	 /* L2 Selection */
-		/* UART0 and UART1 4 pins */
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
-		break;
-	case L3:	 /* L3 Selection */
-		/* UART0 4 pins, UART1 and UART2 2 pins */
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
-		break;
-	case L4:	 /* L4 Selection */
-		/* UART0, UART1, UART2 and UART3 2 pins */
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
-		break;
-	}
-	update_uart_ios(uart_configuration, gpio_tab);
-
-	/* UART Selection in all cases */
-	uart_selection_in_fpga(uart_configuration);
-
-	/* Packet Reject Function Available */
-	if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
-	{
-		/* Set UPR Bit in SDR0_PFC1 Register */
-		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
-	}
-
-	/* Packet Reject Function Enable */
-	if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
-	{
-		mfsdr(SDR0_MFR, sdr0_mfr);
-		sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
-		mtsdr(SDR0_MFR, sdr0_mfr);
-	}
-
-	/* Perform effective access to hardware */
-	mtsdr(SDR0_PFC1, sdr0_pfc1);
-	set_chip_gpio_configuration(GPIO0, gpio_tab);
-	set_chip_gpio_configuration(GPIO1, gpio_tab);
-
-	/* USB2.0 Device Reset must be done after GPIO setting */
-	if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
-		usb2_device_reset_through_fpga();
-
-}
diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h
deleted file mode 100644
index 49f200a..0000000
--- a/board/amcc/bamboo/bamboo.h
+++ /dev/null
@@ -1,348 +0,0 @@
-/*
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*----------------------------------------------------------------------------+
-  | FPGA registers and bit definitions
-  +----------------------------------------------------------------------------*/
-/*
- * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0.
- * TLB initialization makes it correspond to logical address 0x80001FF0.
- * => Done init_chip.s in bootlib
- */
-#define FPGA_BASE_ADDR	0x80002000
-
-/*----------------------------------------------------------------------------+
-  | Board Jumpers Setting Register
-  |   Board Settings provided by jumpers
-  +----------------------------------------------------------------------------*/
-#define FPGA_SETTING_REG	    (FPGA_BASE_ADDR+0x3)
-/* Boot from small flash */
-#define	    FPGA_SET_REG_BOOT_SMALL_FLASH	    0x80
-/* Operational Flash versus SRAM position in Memory Map */
-#define	    FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK	    0x40
-#define	     FPGA_SET_REG_OP_CODE_FLASH_ABOVE	     0x40
-#define	     FPGA_SET_REG_SRAM_ABOVE		     0x00
-/* Boot From NAND Flash */
-#define	    FPGA_SET_REG_BOOT_NAND_FLASH_MASK	    0x40
-#define	    FPGA_SET_REG_BOOT_NAND_FLASH_SELECT	     0x00
-/* On Board PCI Arbiter Select */
-#define	    FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK   0x10
-#define	    FPGA_SET_REG_PCI_EXT_ARBITER_SEL	    0x00
-
-/*----------------------------------------------------------------------------+
-  | Functions Selection Register 1
-  +----------------------------------------------------------------------------*/
-#define FPGA_SELECTION_1_REG	    (FPGA_BASE_ADDR+0x4)
-#define	    FPGA_SEL_1_REG_PHY_MASK	    0xE0
-#define	    FPGA_SEL_1_REG_MII		    0x80
-#define	    FPGA_SEL_1_REG_RMII		    0x40
-#define	    FPGA_SEL_1_REG_SMII		    0x20
-#define	    FPGA_SEL_1_REG_USB2_DEV_SEL	    0x10	   /* USB2 Device Selection */
-#define	    FPGA_SEL_1_REG_USB2_HOST_SEL    0x08	   /* USB2 Host Selection */
-#define	    FPGA_SEL_1_REG_NF_SELEC_MASK    0x07	   /* NF Selection Mask */
-#define	    FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04	   /* NF0 Selected by NF_CS1 */
-#define	    FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02	   /* NF1 Selected by NF_CS2 */
-#define	    FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01	   /* NF1 Selected by NF_CS3 */
-
-/*----------------------------------------------------------------------------+
-  | Functions Selection Register 2
-  +----------------------------------------------------------------------------*/
-#define FPGA_SELECTION_2_REG	    (FPGA_BASE_ADDR+0x5)
-#define	    FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80	   /* IIC1 / SCP Selection */
-#define	    FPGA_SEL2_REG_SEL_FRAM	    0x80	   /* FRAM on IIC1 bus selected - SCP Select */
-#define	    FPGA_SEL2_REG_SEL_SCP	    0x80	   /* Identical to SCP Selection */
-#define	    FPGA_SEL2_REG_SEL_IIC1	    0x00	   /* IIC1 Selection - Default Value */
-#define	    FPGA_SEL2_REG_SEL_DMA_A_B	    0x40	   /* DMA A & B channels selected */
-#define	    FPGA_SEL2_REG_SEL_DMA_C_D	    0x20	   /* DMA C & D channels selected */
-#define	    FPGA_SEL2_REG_DMA_EOT_TC_3_SEL  0x10	   /* 0 = EOT - input to 440EP */
-							   /* 1 = TC - output from 440EP */
-#define	    FPGA_SEL2_REG_DMA_EOT_TC_2_SEL  0x08	   /* 0 = EOT (input to 440EP) */
-							   /* 1 = TC (output from 440EP) */
-#define	    FPGA_SEL2_REG_SEL_GPIO_1	    0x04	   /* EBC_GPIO & USB2_GPIO selected */
-#define	    FPGA_SEL2_REG_SEL_GPIO_2	    0x02	   /* Ether._GPIO & UART_GPIO selected */
-#define	    FPGA_SEL2_REG_SEL_GPIO_3	    0x01	   /* DMA_GPIO & Trace_GPIO selected */
-
-/*----------------------------------------------------------------------------+
-  | Functions Selection Register 3
-  +----------------------------------------------------------------------------*/
-#define FPGA_SELECTION_3_REG	    (FPGA_BASE_ADDR+0x6)
-#define	    FPGA_SEL3_REG_EXP_SLOT_EN		    0x80    /* Expansion Slot enabled */
-#define	    FPGA_SEL3_REG_SEL_UART_CONFIG_MASK	    0x70
-#define	    FPGA_SEL3_REG_SEL_UART_CONFIG1	    0x40    /* one 8_pin UART */
-#define	    FPGA_SEL3_REG_SEL_UART_CONFIG2	    0x20    /* two 4_pin UARTs */
-#define	    FPGA_SEL3_REG_SEL_UART_CONFIG3	    0x10    /* one 4_pin & two 2_pin UARTs */
-#define	    FPGA_SEL3_REG_SEL_UART_CONFIG4	    0x08    /* four 2_pin UARTs */
-#define	    FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART   0x00    /* DTR/DSR mode for 4_pin_UART */
-#define	    FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART   0x04    /* RTS/CTS mode for 4_pin_UART */
-
-/*----------------------------------------------------------------------------+
-  | Soft Reset Register
-  +----------------------------------------------------------------------------*/
-#define FPGA_RESET_REG		    (FPGA_BASE_ADDR+0x7)
-#define	    FPGA_RESET_REG_RESET_USB20_DEV	    0x80    /* Hard Reset of the GT3200 */
-#define	    FPGA_RESET_REG_RESET_DISPLAY	    0x40    /* Hard Reset on Display Device */
-#define	    FPGA_RESET_REG_STATUS_LED_0		    0x08    /* 1 = Led On */
-#define	    FPGA_RESET_REG_STATUS_LED_1		    0x04    /* 1 = Led On */
-#define	    FPGA_RESET_REG_STATUS_LED_2		    0x02    /* 1 = Led On */
-#define	    FPGA_RESET_REG_STATUS_LED_3		    0x01    /* 1 = Led On */
-
-
-/*----------------------------------------------------------------------------+
-| SDR Configuration registers
-+----------------------------------------------------------------------------*/
-#define	  SDR0_SDSTP1_EBC_ROM_BS_MASK  0x00006000  /* EBC Boot Size Mask */
-#define	  SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000    /* EBC 32 bits */
-#define	  SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000    /* EBC 16 Bits */
-#define	  SDR0_SDSTP1_EBC_ROM_BS_8BIT  0x00000000    /* EBC  8 Bits */
-
-#define	  SDR0_SDSTP1_BOOT_SEL_MASK    0x00001800   /* Boot device Selection Mask */
-#define	  SDR0_SDSTP1_BOOT_SEL_EBC     0x00000000     /* EBC */
-#define	  SDR0_SDSTP1_BOOT_SEL_PCI     0x00000800     /* PCI */
-#define	  SDR0_SDSTP1_BOOT_SEL_NDFC    0x00001000     /* NDFC */
-
-/* Serial Device Enabled - Addr = 0xA8 */
-#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
-/* Serial Device Enabled - Addr = 0xA4 */
-#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
-
-/* Pin Straps Reg */
-#define SDR0_PSTRP0		     0x0040
-#define SDR0_PSTRP0_BOOTSTRAP_MASK	0xE0000000  /* Strap Bits */
-
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000  /* Default strap settings 0 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000  /* Default strap settings 1 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000  /* Default strap settings 2 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000  /* Default strap settings 3 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000  /* Default strap settings 4 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000  /* Default strap settings 5 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000  /* Default strap settings 6 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000  /* Default strap settings 7 */
-
-/*----------------------------------------------------------------------------+
-| EBC Configuration Register - EBC0_CFG
-+----------------------------------------------------------------------------*/
-/* External Bus Three-State Control */
-#define EBC0_CFG_EBTC_DRIVEN	    0x80000000
-/* Device-Paced Time-out Disable */
-#define EBC0_CFG_PTD_ENABLED	    0x00000000
-/* Ready Timeout Count */
-#define EBC0_CFG_RTC_MASK	    0x38000000
-#define EBC0_CFG_RTC_16PERCLK	    0x00000000
-#define EBC0_CFG_RTC_32PERCLK	    0x08000000
-#define EBC0_CFG_RTC_64PERCLK	    0x10000000
-#define EBC0_CFG_RTC_128PERCLK	    0x18000000
-#define EBC0_CFG_RTC_256PERCLK	    0x20000000
-#define EBC0_CFG_RTC_512PERCLK	    0x28000000
-#define EBC0_CFG_RTC_1024PERCLK	    0x30000000
-#define EBC0_CFG_RTC_2048PERCLK	    0x38000000
-/* External Master Priority Low */
-#define EBC0_CFG_EMPL_LOW	    0x00000000
-#define EBC0_CFG_EMPL_MEDIUM_LOW    0x02000000
-#define EBC0_CFG_EMPL_MEDIUM_HIGH   0x04000000
-#define EBC0_CFG_EMPL_HIGH	    0x06000000
-/* External Master Priority High */
-#define EBC0_CFG_EMPH_LOW	    0x00000000
-#define EBC0_CFG_EMPH_MEDIUM_LOW    0x00800000
-#define EBC0_CFG_EMPH_MEDIUM_HIGH   0x01000000
-#define EBC0_CFG_EMPH_HIGH	    0x01800000
-/* Chip Select Three-State Control */
-#define EBC0_CFG_CSTC_DRIVEN	    0x00400000
-/* Burst Prefetch */
-#define EBC0_CFG_BPF_ONEDW	    0x00000000
-#define EBC0_CFG_BPF_TWODW	    0x00100000
-#define EBC0_CFG_BPF_FOURDW	    0x00200000
-/* External Master Size */
-#define EBC0_CFG_EMS_8BIT	    0x00000000
-/* Power Management Enable */
-#define EBC0_CFG_PME_DISABLED	    0x00000000
-#define EBC0_CFG_PME_ENABLED	    0x00020000
-/* Power Management Timer */
-#define EBC0_CFG_PMT_ENCODE(n)		((((unsigned long)(n))&0x1F)<<12)
-
-/*----------------------------------------------------------------------------+
-| Peripheral Bank Configuration Register - EBC0_BnCR
-+----------------------------------------------------------------------------*/
-/* BAS - Base Address Select */
-#define EBC0_BNCR_BAS_ENCODE(n)		((((unsigned long)(n))&0xFFF00000)<<0)
-/* BS - Bank Size */
-#define EBC0_BNCR_BS_MASK	0x000E0000
-#define EBC0_BNCR_BS_1MB	0x00000000
-#define EBC0_BNCR_BS_2MB	0x00020000
-#define EBC0_BNCR_BS_4MB	0x00040000
-#define EBC0_BNCR_BS_8MB	0x00060000
-#define EBC0_BNCR_BS_16MB	0x00080000
-#define EBC0_BNCR_BS_32MB	0x000A0000
-#define EBC0_BNCR_BS_64MB	0x000C0000
-#define EBC0_BNCR_BS_128MB	0x000E0000
-/* BU - Bank Usage */
-#define EBC0_BNCR_BU_MASK	0x00018000
-#define EBC0_BNCR_BU_RO		    0x00008000
-#define EBC0_BNCR_BU_WO		    0x00010000
-#define EBC0_BNCR_BU_RW		0x00018000
-/* BW - Bus Width */
-#define EBC0_BNCR_BW_MASK	0x00006000
-#define EBC0_BNCR_BW_8BIT	0x00000000
-#define EBC0_BNCR_BW_16BIT	0x00002000
-#define EBC0_BNCR_BW_32BIT	0x00004000
-
-/*----------------------------------------------------------------------------+
-| Peripheral Bank Access Parameters - EBC0_BnAP
-+----------------------------------------------------------------------------*/
-/* Burst Mode Enable */
-#define EBC0_BNAP_BME_ENABLED	    0x80000000
-#define EBC0_BNAP_BME_DISABLED	    0x00000000
-/* Transfert Wait */
-#define EBC0_BNAP_TWT_ENCODE(n)	    ((((unsigned long)(n))&0xFF)<<23)	/* Bits 1:8 */
-/* Chip Select On Timing */
-#define EBC0_BNAP_CSN_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<18)	/* Bits 12:13 */
-/* Output Enable On Timing */
-#define EBC0_BNAP_OEN_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<16)	/* Bits 14:15 */
-/* Write Back Enable On Timing */
-#define EBC0_BNAP_WBN_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<14)	/* Bits 16:17 */
-/* Write Back Enable Off Timing */
-#define EBC0_BNAP_WBF_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<12)	/* Bits 18:19 */
-/* Transfert Hold */
-#define EBC0_BNAP_TH_ENCODE(n)	    ((((unsigned long)(n))&0x7)<<9)	/* Bits 20:22 */
-/* PerReady Enable */
-#define EBC0_BNAP_RE_ENABLED	    0x00000100
-#define EBC0_BNAP_RE_DISABLED	    0x00000000
-/* Sample On Ready */
-#define EBC0_BNAP_SOR_DELAYED	    0x00000000
-#define EBC0_BNAP_SOR_NOT_DELAYED   0x00000080
-/* Byte Enable Mode */
-#define EBC0_BNAP_BEM_WRITEONLY	    0x00000000
-#define EBC0_BNAP_BEM_RW	    0x00000040
-/* Parity Enable */
-#define EBC0_BNAP_PEN_DISABLED	    0x00000000
-#define EBC0_BNAP_PEN_ENABLED	    0x00000020
-
-/*----------------------------------------------------------------------------+
-| Define Boot devices
-+----------------------------------------------------------------------------*/
-/* */
-#define BOOT_FROM_SMALL_FLASH		0x00
-#define BOOT_FROM_LARGE_FLASH_OR_SRAM	0x01
-#define BOOT_FROM_NAND_FLASH0		0x02
-#define BOOT_FROM_PCI			0x03
-#define BOOT_DEVICE_UNKNOWN		0x04
-
-
-#define	 PVR_POWERPC_440EP_PASS1    0x42221850
-#define	 PVR_POWERPC_440EP_PASS2    0x422218D3
-
-#define GPIO0		0
-#define GPIO1		1
-
-/*#define MAX_SELECTION_NB	CORE_NB */
-#define MAX_CORE_SELECT_NB	22
-
-/*----------------------------------------------------------------------------+
-  | PPC440EP GPIOs addresses.
-  +----------------------------------------------------------------------------*/
-#define GPIO0_REAL	 0xEF600B00
-
-#define GPIO1_REAL	 0xEF600C00
-
-/* Offsets */
-#define GPIOx_OR    0x00	/* GPIO Output Register */
-#define GPIOx_TCR   0x04	/* GPIO Three-State Control Register */
-#define GPIOx_OSL   0x08	/* GPIO Output Select Register (Bits 0-31) */
-#define GPIOx_OSH   0x0C	/* GPIO Ouput Select Register (Bits 32-63) */
-#define GPIOx_TSL   0x10	/* GPIO Three-State Select Register (Bits 0-31) */
-#define GPIOx_TSH   0x14	/* GPIO Three-State Select Register  (Bits 32-63) */
-#define GPIOx_ODR   0x18	/* GPIO Open drain Register */
-#define GPIOx_IR    0x1C	/* GPIO Input Register */
-#define GPIOx_RR1   0x20	/* GPIO Receive Register 1 */
-#define GPIOx_RR2   0x24	/* GPIO Receive Register 2 */
-#define GPIOx_RR3   0x28	/* GPIO Receive Register 3 */
-#define GPIOx_IS1L  0x30	/* GPIO Input Select Register 1 (Bits 0-31) */
-#define GPIOx_IS1H  0x34	/* GPIO Input Select Register 1 (Bits 32-63) */
-#define GPIOx_IS2L  0x38	/* GPIO Input Select Register 2 (Bits 0-31) */
-#define GPIOx_IS2H  0x3C	/* GPIO Input Select Register 2 (Bits 32-63) */
-#define GPIOx_IS3L  0x40	/* GPIO Input Select Register 3 (Bits 0-31) */
-#define GPIOx_IS3H  0x44	/* GPIO Input Select Register 3 (Bits 32-63) */
-
-/* GPIO0 */
-#define GPIO0_IS1L	(GPIO0_BASE+GPIOx_IS1L)
-#define GPIO0_IS1H	(GPIO0_BASE+GPIOx_IS1H)
-#define GPIO0_IS2L	(GPIO0_BASE+GPIOx_IS2L)
-#define GPIO0_IS2H	(GPIO0_BASE+GPIOx_IS2H)
-#define GPIO0_IS3L	(GPIO0_BASE+GPIOx_IS3L)
-#define GPIO0_IS3H	(GPIO0_BASE+GPIOx_IS3L)
-
-/* GPIO1 */
-#define GPIO1_IS1L	(GPIO1_BASE+GPIOx_IS1L)
-#define GPIO1_IS1H	(GPIO1_BASE+GPIOx_IS1H)
-#define GPIO1_IS2L	(GPIO1_BASE+GPIOx_IS2L)
-#define GPIO1_IS2H	(GPIO1_BASE+GPIOx_IS2H)
-#define GPIO1_IS3L	(GPIO1_BASE+GPIOx_IS3L)
-#define GPIO1_IS3H	(GPIO1_BASE+GPIOx_IS3L)
-
-#define GPIO_OS(x)	(x+GPIOx_OSL)	 /* GPIO Output Register High or Low */
-#define GPIO_TS(x)	(x+GPIOx_TSL)	 /* GPIO Three-state Control Reg High or Low */
-#define GPIO_IS1(x)	(x+GPIOx_IS1L)	 /* GPIO Input register1 High or Low */
-#define GPIO_IS2(x)	(x+GPIOx_IS2L)	 /* GPIO Input register2 High or Low */
-#define GPIO_IS3(x)	(x+GPIOx_IS3L)	 /* GPIO Input register3 High or Low */
-
-
-/*----------------------------------------------------------------------------+
-  |			XX     XX
-  |
-  | XXXXXX   XXX XX    XXX    XXX
-  |    XX    XX X XX	XX     XX
-  |   XX     XX X XX	XX     XX
-  |  XX	     XX	  XX	XX     XX
-  | XXXXXX   XXX  XXX  XXXX   XXXX
-  +----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------+
-  | Defines
-  +----------------------------------------------------------------------------*/
-typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
-			   ZMII_CONFIGURATION_IS_MII,
-			   ZMII_CONFIGURATION_IS_RMII,
-			   ZMII_CONFIGURATION_IS_SMII
-} zmii_config_t;
-
-/*----------------------------------------------------------------------------+
-  | Declare Configuration values
-  +----------------------------------------------------------------------------*/
-typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
-typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
-typedef enum config_list {  IIC_CORE,
-			    SCP_CORE,
-			    DMA_CHANNEL_AB,
-			    UIC_4_9,
-			    USB2_HOST,
-			    DMA_CHANNEL_CD,
-			    USB2_DEVICE,
-			    PACKET_REJ_FUNC_AVAIL,
-			    USB1_DEVICE,
-			    EBC_MASTER,
-			    NAND_FLASH,
-			    UART_CORE0,
-			    UART_CORE1,
-			    UART_CORE2,
-			    UART_CORE3,
-			    MII_SEL,
-			    RMII_SEL,
-			    SMII_SEL,
-			    PACKET_REJ_FUNC_EN,
-			    UIC_0_3,
-			    USB1_HOST,
-			    PCI_PATCH,
-			    CORE_NB
-} core_list_t;
-
-typedef enum block3_value { B3_V1,  B3_V2,  B3_V3,  B3_V4,  B3_V5,
-			    B3_V6,  B3_V7,  B3_V8,  B3_V9,  B3_V10,
-			    B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
-			    B3_V16, B3_VALUE_UNKNOWN
-} block3_value_t;
-
-typedef enum config_validity { CONFIG_IS_VALID,
-			       CONFIG_IS_INVALID
-} config_validity_t;
diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk
deleted file mode 100644
index 9cb071e..0000000
--- a/board/amcc/bamboo/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2002-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c
deleted file mode 100644
index 6dbe09f..0000000
--- a/board/amcc/bamboo/flash.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * (C) Copyright 2004-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
- * Add support for Am29F016D and dynamic switch setting.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/ppc440.h>
-#include "bamboo.h"
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif				/* DEBUG */
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
-
-/*
- * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
- */
-static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
-	{0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
-	{0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66      */
-	{0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash  */
-	{0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
-	{0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
-	{0x00000000, 0x00000000, 0x00000000}, /* 5:boot from             */
-	{0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66      */
-	{0x00000000, 0x00000000, 0x00000000}, /* 7:boot from             */
-	{0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
-};
-
-/*
- * include common flash code (for amcc boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static int write_word(flash_info_t * info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
-	unsigned long total_b = 0;
-	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
-	unsigned short index = 0;
-	int i;
-	unsigned long val;
-	unsigned long ebc_boot_size;
-	unsigned long boot_selection;
-
-	mfsdr(SDR0_PINSTP, val);
-	index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29;
-
-	if ((index == 5) || (index == 7)) {
-		/*
-		 * Boot Settings in IIC EEprom address 0xA8 or 0xA4
-		 * Read Serial Device Strap Register1 in PPC440EP
-		 */
-		mfsdr(SDR0_SDSTP1, val);
-		boot_selection  = val & SDR0_SDSTP1_BOOT_SEL_MASK;
-		ebc_boot_size   = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
-
-		switch(boot_selection) {
-		case SDR0_SDSTP1_BOOT_SEL_EBC:
-			switch(ebc_boot_size) {
-			case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
-				index = 3;
-				break;
-			case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
-				index = 0;
-				break;
-			}
-			break;
-
-		case SDR0_SDSTP1_BOOT_SEL_PCI:
-			index = 1;
-			break;
-
-		case SDR0_SDSTP1_BOOT_SEL_NDFC:
-			index = 2;
-			break;
-		}
-	} else if (index == 0) {
-		if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) {
-			index = 8; /* sram below op code flash -> new index 8 */
-		}
-	}
-
-	DEBUGF("\n");
-	DEBUGF("FLASH: Index: %d\n", index);
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-		flash_info[i].sector_count = -1;
-		flash_info[i].size = 0;
-
-		/* check whether the address is 0 */
-		if (flash_addr_table[index][i] == 0)
-			continue;
-
-		DEBUGF("Detection bank %d...\n", i);
-		/* call flash_get_size() to initialize sector address */
-		size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
-				   &flash_info[i]);
-		flash_info[i].size = size_b[i];
-		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
-			       i, size_b[i], size_b[i] << 20);
-			flash_info[i].sector_count = -1;
-			flash_info[i].size = 0;
-		}
-
-		/* Monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
-				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
-				    &flash_info[i]);
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
-				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[i]);
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR_REDUND)
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
-				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[i]);
-#endif
-#endif
-
-		total_b += flash_info[i].size;
-	}
-
-	return total_b;
-}
diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S
deleted file mode 100644
index 5c7c839..0000000
--- a/board/amcc/bamboo/init.S
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-	.section .bootpg,"ax"
-	.globl tlbtab
-
-tlbtab:
-	tlbtab_start
-
-	/*
-	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
-	 * speed up boot process. It is patched after relocation to enable SA_I
-	 */
-	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
-
-	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
-
-	/* PCI base & peripherals */
-	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I)
-	tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_RWX | SA_W|SA_I)
-
-	/* PCI */
-	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG)
-
-	/* USB 2.0 Device */
-	tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
-
-	tlbtab_end
diff --git a/board/amcc/bubinga/Kconfig b/board/amcc/bubinga/Kconfig
deleted file mode 100644
index fc40f6e..0000000
--- a/board/amcc/bubinga/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TARGET_BUBINGA
-
-config SYS_BOARD
-	default "bubinga"
-
-config SYS_VENDOR
-	default "amcc"
-
-config SYS_CONFIG_NAME
-	default "bubinga"
-
-config DISPLAY_BOARDINFO
-	bool
-	default y
-
-endif
diff --git a/board/amcc/bubinga/MAINTAINERS b/board/amcc/bubinga/MAINTAINERS
deleted file mode 100644
index 3299cc3..0000000
--- a/board/amcc/bubinga/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BUBINGA BOARD
-#M:	-
-S:	Maintained
-F:	board/amcc/bubinga/
-F:	include/configs/bubinga.h
-F:	configs/bubinga_defconfig
diff --git a/board/amcc/bubinga/Makefile b/board/amcc/bubinga/Makefile
deleted file mode 100644
index 0e7ebca..0000000
--- a/board/amcc/bubinga/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= bubinga.o flash.o
diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c
deleted file mode 100644
index 5c1e071..0000000
--- a/board/amcc/bubinga/bubinga.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-long int spd_sdram(void);
-
-int board_early_init_f(void)
-{
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
-	mtdcr(UIC0CR, 0x00000010);
-	mtdcr(UIC0PR, 0xFFFF7FF0);	/* set int polarities */
-	mtdcr(UIC0TR, 0x00000010);	/* set int trigger levels */
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-
-	/*
-	 * Configure CPC0_PCI to enable PerWE as output
-	 * and enable the internal PCI arbiter if selected
-	 */
-	if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB)
-		mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
-	else
-		mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN);
-
-	return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	puts("Board: Bubinga - AMCC PPC405EP Evaluation Board");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return (0);
-}
-
-/* -------------------------------------------------------------------------
-  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
-  the necessary info for SDRAM controller configuration
-   ------------------------------------------------------------------------- */
-phys_size_t initdram(int board_type)
-{
-	long int ret;
-
-	ret = spd_sdram();
-	return ret;
-}
diff --git a/board/amcc/bubinga/flash.c b/board/amcc/bubinga/flash.c
deleted file mode 100644
index a9d0ed8..0000000
--- a/board/amcc/bubinga/flash.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
-
-#undef DEBUG
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif				/* DEBUG */
-
-/*
- * include common flash code (for amcc boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static void flash_get_offsets(ulong base, flash_info_t * info);
-
-unsigned long flash_init(void)
-{
-	unsigned long size_b0, size_b1;
-	int i;
-	uint pbcr;
-	unsigned long base_b0, base_b1;
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	size_b0 =
-	    flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-		       size_b0, size_b0 << 20);
-	}
-
-	/* Only one bank */
-	if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
-		/* Setup offsets */
-		flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
-
-		/* Monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET,
-				    CONFIG_SYS_MONITOR_BASE,
-				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
-				    &flash_info[0]);
-#ifdef CONFIG_ENV_IS_IN_FLASH
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
-				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[0]);
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
-				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[0]);
-#endif
-
-		size_b1 = 0;
-		flash_info[0].size = size_b0;
-	}
-
-	/* 2 banks */
-	else {
-		size_b1 =
-		    flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
-				   &flash_info[1]);
-
-		/* Re-do sizing to get full correct info */
-
-		if (size_b1) {
-			mtdcr(EBC0_CFGADDR, PB0CR);
-			pbcr = mfdcr(EBC0_CFGDATA);
-			mtdcr(EBC0_CFGADDR, PB0CR);
-			base_b1 = -size_b1;
-			pbcr = (pbcr & 0x0001ffff) | base_b1 |
-			    (((size_b1 / 1024 / 1024) - 1) << 17);
-			mtdcr(EBC0_CFGDATA, pbcr);
-			/*          printf("PB1CR = %x\n", pbcr); */
-		}
-
-		if (size_b0) {
-			mtdcr(EBC0_CFGADDR, PB1CR);
-			pbcr = mfdcr(EBC0_CFGDATA);
-			mtdcr(EBC0_CFGADDR, PB1CR);
-			base_b0 = base_b1 - size_b0;
-			pbcr = (pbcr & 0x0001ffff) | base_b0 |
-			    (((size_b0 / 1024 / 1024) - 1) << 17);
-			mtdcr(EBC0_CFGDATA, pbcr);
-			/*            printf("PB0CR = %x\n", pbcr); */
-		}
-
-		size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
-
-		flash_get_offsets(base_b0, &flash_info[0]);
-
-		/* monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET,
-				    base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN,
-				    base_b0 + size_b0 - 1, &flash_info[0]);
-		/* Also protect sector containing initial power-up instruction */
-		/* (flash_protect() checks address range - other call ignored) */
-		(void)flash_protect(FLAG_PROTECT_SET,
-				    0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
-		(void)flash_protect(FLAG_PROTECT_SET,
-				    0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]);
-
-		if (size_b1) {
-			/* Re-do sizing to get full correct info */
-			size_b1 =
-			    flash_get_size((vu_long *) base_b1, &flash_info[1]);
-
-			flash_get_offsets(base_b1, &flash_info[1]);
-
-			/* monitor protection ON by default */
-			(void)flash_protect(FLAG_PROTECT_SET,
-					    base_b1 + size_b1 - CONFIG_SYS_MONITOR_LEN,
-					    base_b1 + size_b1 - 1,
-					    &flash_info[1]);
-			/* monitor protection OFF by default (one is enough) */
-			(void)flash_protect(FLAG_PROTECT_CLEAR,
-					    base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN,
-					    base_b0 + size_b0 - 1,
-					    &flash_info[0]);
-		} else {
-			flash_info[1].flash_id = FLASH_UNKNOWN;
-			flash_info[1].sector_count = -1;
-		}
-
-		flash_info[0].size = size_b0;
-		flash_info[1].size = size_b1;
-	}			/* else 2 banks */
-	return (size_b0 + size_b1);
-}
-
-static void flash_get_offsets(ulong base, flash_info_t * info)
-{
-	int i;
-
-	/* set up sector start address table */
-	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    (info->flash_id == FLASH_AM040)) {
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00010000);
-	} else {
-		if (info->flash_id & FLASH_BTYPE) {
-			/* set sector offsets for bottom boot block type        */
-			info->start[0] = base + 0x00000000;
-			info->start[1] = base + 0x00004000;
-			info->start[2] = base + 0x00006000;
-			info->start[3] = base + 0x00008000;
-			for (i = 4; i < info->sector_count; i++) {
-				info->start[i] =
-				    base + (i * 0x00010000) - 0x00030000;
-			}
-		} else {
-			/* set sector offsets for top boot block type           */
-			i = info->sector_count - 1;
-			info->start[i--] = base + info->size - 0x00004000;
-			info->start[i--] = base + info->size - 0x00006000;
-			info->start[i--] = base + info->size - 0x00008000;
-			for (; i >= 0; i--) {
-				info->start[i] = base + i * 0x00010000;
-			}
-		}
-	}
-}
diff --git a/board/amcc/canyonlands/Kconfig b/board/amcc/canyonlands/Kconfig
deleted file mode 100644
index a655dbc..0000000
--- a/board/amcc/canyonlands/Kconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-if TARGET_CANYONLANDS
-
-config SYS_BOARD
-	default "canyonlands"
-
-config SYS_VENDOR
-	default "amcc"
-
-config SYS_CONFIG_NAME
-	default "canyonlands"
-
-choice BOARD_TYPE
-	prompt "Select which board to build for"
-	optional
-
-config CANYONLANDS
-	bool "Glacier"
-	help
-	  Select this to build for the Canyonlands 460EX board.
-
-config GLACIER
-	bool "Glacier"
-	help
-	  Select this to build for the Glacier 460GT board.
-
-config ARCHES
-	bool "Arches"
-	help
-	  Select this to build for the Arches dual 460GT board.
-
-endchoice
-
-config DISPLAY_BOARDINFO
-	bool
-	default y
-
-endif
diff --git a/board/amcc/canyonlands/MAINTAINERS b/board/amcc/canyonlands/MAINTAINERS
deleted file mode 100644
index 8be8a52..0000000
--- a/board/amcc/canyonlands/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-CANYONLANDS BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/amcc/canyonlands/
-F:	include/configs/canyonlands.h
-F:	configs/arches_defconfig
-F:	configs/canyonlands_defconfig
-F:	configs/glacier_defconfig
-F:	configs/glacier_ramboot_defconfig
diff --git a/board/amcc/canyonlands/Makefile b/board/amcc/canyonlands/Makefile
deleted file mode 100644
index ba0765f..0000000
--- a/board/amcc/canyonlands/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2008
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= canyonlands.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-extra-y	+= init.o
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
deleted file mode 100644
index dc2e3ba..0000000
--- a/board/amcc/canyonlands/canyonlands.c
+++ /dev/null
@@ -1,521 +0,0 @@
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc440.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/4xx_pcie.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/errno.h>
-#include <usb.h>
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct board_bcsr {
-	u8	board_id;
-	u8	cpld_rev;
-	u8	led_user;
-	u8	board_status;
-	u8	reset_ctrl;
-	u8	flash_ctrl;
-	u8	eth_ctrl;
-	u8	usb_ctrl;
-	u8	irq_ctrl;
-};
-
-#define BOARD_CANYONLANDS_PCIE	1
-#define BOARD_CANYONLANDS_SATA	2
-#define BOARD_GLACIER		3
-#define BOARD_ARCHES		4
-
-/*
- * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
- * board specific values.
- */
-#if defined(CONFIG_ARCHES)
-u32 ddr_wrdtr(u32 default_val) {
-	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
-}
-#else
-u32 ddr_wrdtr(u32 default_val) {
-	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
-}
-
-u32 ddr_clktr(u32 default_val) {
-	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
-}
-#endif
-
-#if defined(CONFIG_ARCHES)
-/*
- * FPGA read/write helper macros
- */
-static inline int board_fpga_read(int offset)
-{
-	int data;
-
-	data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
-
-	return data;
-}
-
-static inline void board_fpga_write(int offset, int data)
-{
-	out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
-}
-
-/*
- * CPLD read/write helper macros
- */
-static inline int board_cpld_read(int offset)
-{
-	int data;
-
-	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
-	data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
-
-	return data;
-}
-
-static inline void board_cpld_write(int offset, int data)
-{
-	out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
-	out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
-}
-#else
-static int pvr_460ex(void)
-{
-	u32 pvr = get_pvr();
-
-	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
-	    (pvr == PVR_460EX_RB))
-		return 1;
-
-	return 0;
-}
-#endif	/* defined(CONFIG_ARCHES) */
-
-int board_early_init_f(void)
-{
-#if !defined(CONFIG_ARCHES)
-	u32 sdr0_cust0;
-	struct board_bcsr *bcsr_data =
-		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
-
-#endif
-
-	/*
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all */
-	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC1ER, 0x00000000);	/* disable all */
-	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC2ER, 0x00000000);	/* disable all */
-	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC3ER, 0x00000000);	/* disable all */
-	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
-
-#if !defined(CONFIG_ARCHES)
-	/* SDR Setting - enable NDFC */
-	mfsdr(SDR0_CUST0, sdr0_cust0);
-	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
-		SDR0_CUST0_NDFC_ENABLE		|
-		SDR0_CUST0_NDFC_BW_8_BIT	|
-		SDR0_CUST0_NDFC_ARE_MASK	|
-		SDR0_CUST0_NDFC_BAC_ENCODE(3)	|
-		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
-	mtsdr(SDR0_CUST0, sdr0_cust0);
-#endif
-
-	/*
-	 * Configure PFC (Pin Function Control) registers
-	 * UART0: 4 pins
-	 */
-	mtsdr(SDR0_PFC1, 0x00040000);
-
-	/* Enable PCI host functionality in SDR0_PCI0 */
-	mtsdr(SDR0_PCI0, 0xe0000000);
-
-#if !defined(CONFIG_ARCHES)
-	/* Enable ethernet and take out of reset */
-	out_8(&bcsr_data->eth_ctrl, 0) ;
-
-	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
-	out_8(&bcsr_data->flash_ctrl, 0) ;
-	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */
-
-	/* Setup PLB4-AHB bridge based on the system address map */
-	mtdcr(AHB_TOP, 0x8000004B);
-	mtdcr(AHB_BOT, 0x8000004B);
-
-#endif
-
-	return 0;
-}
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
-int board_usb_init(int index, enum usb_init_type init)
-{
-	struct board_bcsr *bcsr_data =
-		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
-	u8 val;
-
-	/* Enable USB host & USB-OTG */
-	val = in_8(&bcsr_data->usb_ctrl);
-	val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
-	out_8(&bcsr_data->usb_ctrl, val);
-
-	/*
-	 * Configure USB-STP pins as alternate and not GPIO
-	 * It seems to be neccessary to configure the STP pins as GPIO
-	 * input at powerup (perhaps while USB reset is asserted). So
-	 * we configure those pins to their "real" function now.
-	 */
-	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
-	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
-
-	return 0;
-}
-
-int usb_board_stop(void)
-{
-	struct board_bcsr *bcsr_data =
-		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
-	u8 val;
-
-	/* Disable USB host & USB-OTG */
-	val = in_8(&bcsr_data->usb_ctrl);
-	val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
-	out_8(&bcsr_data->usb_ctrl, val);
-
-	/* Reconfigure USB-STP pins as input */
-	gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
-	gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
-
-	return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	return usb_board_stop();
-}
-#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
-
-#if !defined(CONFIG_ARCHES)
-static void canyonlands_sata_init(int board_type)
-{
-	u32 reg;
-
-	if (board_type == BOARD_CANYONLANDS_SATA) {
-		/* Put SATA in reset */
-		SDR_WRITE(SDR0_SRST1, 0x00020001);
-
-		/* Set the phy for SATA, not PCI-E port 0 */
-		reg = SDR_READ(PESDR0_PHY_CTL_RST);
-		SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
-		reg = SDR_READ(PESDR0_L0CLK);
-		SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
-		SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
-		SDR_WRITE(PESDR0_L0DRV, 0x00000104);
-
-		/* Bring SATA out of reset */
-		SDR_WRITE(SDR0_SRST1, 0x00000000);
-	}
-}
-#endif	/* !defined(CONFIG_ARCHES) */
-
-int get_cpu_num(void)
-{
-	int cpu = NA_OR_UNKNOWN_CPU;
-
-#if defined(CONFIG_ARCHES)
-	int cpu_num;
-
-	cpu_num = board_fpga_read(0x3);
-
-	/* sanity check; assume cpu numbering starts and increments from 0 */
-	if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
-		cpu = cpu_num;
-#endif
-
-	return cpu;
-}
-
-#if !defined(CONFIG_ARCHES)
-int checkboard(void)
-{
-	struct board_bcsr *bcsr_data =
-		(struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	if (pvr_460ex()) {
-		printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
-		if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
-			gd->board_type = BOARD_CANYONLANDS_PCIE;
-		else
-			gd->board_type = BOARD_CANYONLANDS_SATA;
-	} else {
-		printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
-		gd->board_type = BOARD_GLACIER;
-	}
-
-	switch (gd->board_type) {
-	case BOARD_CANYONLANDS_PCIE:
-	case BOARD_GLACIER:
-		puts(", 2*PCIe");
-		break;
-
-	case BOARD_CANYONLANDS_SATA:
-		puts(", 1*PCIe/1*SATA");
-		break;
-	}
-
-	printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	canyonlands_sata_init(gd->board_type);
-
-	return (0);
-}
-
-#else	/* defined(CONFIG_ARCHES) */
-
-int checkboard(void)
-{
-	char *s = getenv("serial#");
-
-	printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
-	printf("       Revision %02x.%02x ",
-				board_fpga_read(0x0), board_fpga_read(0x1));
-
-	gd->board_type = BOARD_ARCHES;
-
-	/* Only CPU0 has access to CPLD registers */
-	if (get_cpu_num() == 0) {
-		u8 cfg_sw = board_cpld_read(0x1);
-		printf("(FPGA=%02x, CPLD=%02x)\n",
-				board_fpga_read(0x2), board_cpld_read(0x0));
-		printf("       Configuration Switch %d%d%d%d\n",
-				((cfg_sw >> 3) & 0x01),
-				((cfg_sw >> 2) & 0x01),
-				((cfg_sw >> 1) & 0x01),
-				((cfg_sw >> 0) & 0x01));
-	} else
-		printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
-
-
-	if (s != NULL)
-		printf("       Serial# %s\n", s);
-
-	return 0;
-}
-#endif	/* !defined(CONFIG_ARCHES) */
-
-#if defined(CONFIG_PCI)
-int board_pcie_first(void)
-{
-	/*
-	 * Canyonlands with SATA enabled has only one PCIe slot
-	 * (2nd one).
-	 */
-	if (gd->board_type == BOARD_CANYONLANDS_SATA)
-		return 1;
-
-	return 0;
-}
-#endif /* CONFIG_PCI */
-
-int board_early_init_r (void)
-{
-	/*
-	 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
-	 * boot EBC mapping only supports a maximum of 16MBytes
-	 * (4.ff00.0000 - 4.ffff.ffff).
-	 * To solve this problem, the FLASH has to get remapped to another
-	 * EBC address which accepts bigger regions:
-	 *
-	 * 0xfc00.0000 -> 4.cc00.0000
-	 */
-
-	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
-	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
-
-	/* Remove TLB entry of boot EBC mapping */
-	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
-
-	/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
-	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
-		    TLB_WORD2_I_ENABLE);
-
-	/*
-	 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
-	 * 0xfc00.0000 is possible
-	 */
-
-	/*
-	 * Clear potential errors resulting from auto-calibration.
-	 * If not done, then we could get an interrupt later on when
-	 * exceptions are enabled.
-	 */
-	set_mcsr(get_mcsr());
-
-	return 0;
-}
-
-#if !defined(CONFIG_ARCHES)
-int misc_init_r(void)
-{
-	u32 sdr0_srst1 = 0;
-	u32 eth_cfg;
-	u8 val;
-
-	/*
-	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
-	 * This is board specific, so let's do it here.
-	 */
-	mfsdr(SDR0_ETH_CFG, eth_cfg);
-	/* disable SGMII mode */
-	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
-		     SDR0_ETH_CFG_SGMII1_ENABLE |
-		     SDR0_ETH_CFG_SGMII0_ENABLE);
-	/* Set the for 2 RGMII mode */
-	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
-	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
-	if (pvr_460ex())
-		eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
-	else
-		eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
-	mtsdr(SDR0_ETH_CFG, eth_cfg);
-
-	/*
-	 * The AHB Bridge core is held in reset after power-on or reset
-	 * so enable it now
-	 */
-	mfsdr(SDR0_SRST1, sdr0_srst1);
-	sdr0_srst1 &= ~SDR0_SRST1_AHB;
-	mtsdr(SDR0_SRST1, sdr0_srst1);
-
-	/*
-	 * RTC/M41T62:
-	 * Disable square wave output: Batterie will be drained
-	 * quickly, when this output is not disabled
-	 */
-	val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
-	val &= ~0x40;
-	i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
-
-	return 0;
-}
-
-#else	/* defined(CONFIG_ARCHES) */
-
-int misc_init_r(void)
-{
-	u32 eth_cfg = 0;
-	u32 eth_pll;
-	u32 reg;
-
-	/*
-	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
-	 * This is board specific, so let's do it here.
-	 */
-
-	/* enable SGMII mode */
-	eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
-			SDR0_ETH_CFG_SGMII1_ENABLE |
-			SDR0_ETH_CFG_SGMII2_ENABLE);
-
-	/* Set EMAC for MDIO */
-	eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
-
-	/* bypass the TAHOE0/TAHOE1 cores for U-Boot */
-	eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
-
-	mtsdr(SDR0_ETH_CFG, eth_cfg);
-
-	/* reset all SGMII interfaces */
-	mfsdr(SDR0_SRST1,   reg);
-	reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
-	mtsdr(SDR0_SRST1, reg);
-	mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
-	mtsdr(SDR0_SRST1,   0x00000000);
-
-	do {
-		mfsdr(SDR0_ETH_PLL, eth_pll);
-	} while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
-
-	return 0;
-}
-#endif	/* !defined(CONFIG_ARCHES) */
-
-#ifdef CONFIG_OF_BOARD_SETUP
-extern int __ft_board_setup(void *blob, bd_t *bd);
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	__ft_board_setup(blob, bd);
-
-	if (gd->board_type == BOARD_CANYONLANDS_SATA) {
-		/*
-		 * When SATA is selected we need to disable the first PCIe
-		 * node in the device tree, so that Linux doesn't initialize
-		 * it.
-		 */
-		fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
-				     "disabled", sizeof("disabled"), 1);
-	}
-
-	if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
-		/*
-		 * When PCIe is selected we need to disable the SATA
-		 * node in the device tree, so that Linux doesn't initialize
-		 * it.
-		 */
-		fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
-				     "disabled", sizeof("disabled"), 1);
-	}
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/amcc/canyonlands/chip_config.c b/board/amcc/canyonlands/chip_config.c
deleted file mode 100644
index e485570..0000000
--- a/board/amcc/canyonlands/chip_config.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * (C) Copyright 2008-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-struct ppc4xx_config ppc4xx_config_val[] = {
-	{
-		"600-nor", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"800-nor", "NOR  CPU: 800 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"1000-nor", "NOR  CPU:1000 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"1066-nor", "NOR  CPU:1066 PLB: 266 OPB:  88 EBC:  88",
-		{
-			0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-#if !defined(CONFIG_ARCHES)
-	{
-		"600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0,
-			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0,
-			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0,
-			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"1066-nand", "NAND CPU:1066 PLB: 266 OPB:  88 EBC:  88",
-		{
-			0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0,
-			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-#endif
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/amcc/canyonlands/config.mk b/board/amcc/canyonlands/config.mk
deleted file mode 100644
index 5cc90d2..0000000
--- a/board/amcc/canyonlands/config.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2008-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-#
-# AMCC 460EX/460GT Evaluation Board (Canyonlands) board
-#
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
deleted file mode 100644
index bf00bd6..0000000
--- a/board/amcc/canyonlands/init.S
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-	.section .bootpg,"ax"
-	.globl tlbtab
-
-tlbtab:
-	tlbtab_start
-
-	/*
-	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
-	 * use the speed up boot process. It is patched after relocation to
-	 * enable SA_I
-	 */
-	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */
-
-	/*
-	 * TLB entries for SDRAM are not needed on this platform.
-	 * They are dynamically generated in the SPD DDR(2) detection
-	 * routine.
-	 */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
-	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
-#endif
-
-	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
-
-	/* PCIe UTL register */
-	tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_RW | SA_IG)
-
-#if !defined(CONFIG_ARCHES)
-	/* TLB-entry for NAND */
-	tlbentry(CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 4, AC_RWX | SA_IG)
-
-	/* TLB-entry for CPLD */
-	tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_RW | SA_IG)
-#else
-	/* TLB-entry for FPGA */
-	tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_RW | SA_IG)
-#endif
-
-	/* TLB-entry for OCM */
-	tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_RWX | SA_I)
-
-	/* TLB-entry for Local Configuration registers => peripherals */
-	tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
-
-	/* AHB: Internal USB Peripherals (USB, SATA) */
-	tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_RWX | SA_IG)
-
-#if defined(CONFIG_RAPIDIO)
-	/* TLB-entries for RapidIO (SRIO) */
-	tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR,
-					0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR,
-					0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR,
-					0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K,  0x00100000,
-					0x4, AC_RW | SA_IG)
-#endif
-
-	tlbtab_end
diff --git a/board/amcc/canyonlands/u-boot-ram.lds b/board/amcc/canyonlands/u-boot-ram.lds
deleted file mode 100644
index 1750c74..0000000
--- a/board/amcc/canyonlands/u-boot-ram.lds
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    _image_copy_start = .;
-    arch/powerpc/cpu/ppc4xx/start.o	(.text*)
-    board/amcc/canyonlands/init.o	(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    KEEP(*(.got))
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : {
-	*(.data.init)
-	. = ALIGN(256);
-	LONG(0) LONG(0)		/* Extend u-boot.bin to here */
-  }
-  __init_end = .;
-  _end = .;
-  _image_binary_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c
deleted file mode 100644
index 4b2300b..0000000
--- a/board/amcc/common/flash.c
+++ /dev/null
@@ -1,934 +0,0 @@
-/*
- * (C) Copyright 2004-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
- * Add support for Am29F016D and dynamic switch setting.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word(flash_info_t * info, ulong dest, ulong data);
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static int write_word_1(flash_info_t * info, ulong dest, ulong data);
-static int write_word_2(flash_info_t * info, ulong dest, ulong data);
-static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
-static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
-static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
-static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
-#endif
-
-void flash_print_info(flash_info_t * info)
-{
-	int i;
-	int k;
-	int size;
-	int erased;
-	volatile unsigned long *flash;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:
-		printf("AMD ");
-		break;
-	case FLASH_MAN_STM:
-		printf("STM ");
-		break;
-	case FLASH_MAN_FUJ:
-		printf("FUJITSU ");
-		break;
-	case FLASH_MAN_SST:
-		printf("SST ");
-		break;
-	case FLASH_MAN_MX:
-		printf ("MACRONIX ");
-		break;
-	default:
-		printf("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM040:
-		printf("AM29F040 (512 Kbit, uniform sector size)\n");
-		break;
-	case FLASH_AM400B:
-		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM400T:
-		printf("AM29LV400T (4 Mbit, top boot sector)\n");
-		break;
-	case FLASH_AM800B:
-		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM800T:
-		printf("AM29LV800T (8 Mbit, top boot sector)\n");
-		break;
-	case FLASH_AMD016:
-		printf("AM29F016D (16 Mbit, uniform sector size)\n");
-		break;
-	case FLASH_AM160B:
-		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM160T:
-		printf("AM29LV160T (16 Mbit, top boot sector)\n");
-		break;
-	case FLASH_AM320B:
-		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM320T:
-		printf("AM29LV320T (32 Mbit, top boot sector)\n");
-		break;
-	case FLASH_AM033C:
-		printf("AM29LV033C (32 Mbit, top boot sector)\n");
-		break;
-	case FLASH_SST800A:
-		printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
-		break;
-	case FLASH_SST160A:
-		printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
-		break;
-	case FLASH_STMW320DT:
-		printf ("M29W320DT (32 M, top sector)\n");
-		break;
-	case FLASH_MXLV320T:
-		printf ("MXLV320T (32 Mbit, top sector)\n");
-		break;
-	default:
-		printf("Unknown Chip Type\n");
-		break;
-	}
-
-	printf("  Size: %ld KB in %d Sectors\n",
-	       info->size >> 10, info->sector_count);
-
-	printf("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		/*
-		 * Check if whole sector is erased
-		 */
-		if (i != (info->sector_count - 1))
-			size = info->start[i + 1] - info->start[i];
-		else
-			size = info->start[0] + info->size - info->start[i];
-		erased = 1;
-		flash = (volatile unsigned long *)info->start[i];
-		size = size >> 2;	/* divide by 4 for longword access */
-		for (k = 0; k < size; k++) {
-			if (*flash++ != 0xffffffff) {
-				erased = 0;
-				break;
-			}
-		}
-
-		if ((i % 5) == 0)
-			printf("\n   ");
-		printf(" %08lX%s%s",
-		       info->start[i],
-		       erased ? " E" : "  ", info->protect[i] ? "RO " : "   ");
-	}
-	printf("\n");
-	return;
-}
-
-
-/*
- * The following code cannot be run from FLASH!
- */
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-{
-	/* bit 0 used for big flash marking */
-	if ((ulong)addr & 0x1) {
-		return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
-	} else {
-		return flash_get_size_1(addr, info);
-	}
-}
-
-static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
-#else
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-#endif
-{
-	short i;
-	CONFIG_SYS_FLASH_WORD_SIZE value;
-	ulong base = (ulong) addr;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
-
-	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
-
-	/* Write auto select command: read Manufacturer ID */
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
-	udelay(1000);
-
-	value = addr2[0];
-	DEBUGF("FLASH MANUFACT: %x\n", value);
-
-	switch (value) {
-	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
-		info->flash_id = FLASH_MAN_SST;
-		break;
-	case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
-		info->flash_id = FLASH_MAN_STM;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);	/* no or unknown flash  */
-	}
-
-	value = addr2[1];	/* device ID */
-	DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
-	switch (value) {
-	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B:
-		info->flash_id += FLASH_AM040;
-		info->sector_count = 8;
-		info->size = 0x0080000;		/* => 512 KiB */
-		break;
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B:
-		info->flash_id += FLASH_AM040;
-		info->sector_count = 8;
-		info->size = 0x0080000;		/* => 512 KiB */
-		break;
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B:
-		info->flash_id += FLASH_AM040;
-		info->sector_count = 8;
-		info->size = 0x0080000;		/* => 512 KiB */
-		break;
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D:
-		info->flash_id += FLASH_AMD016;
-		info->sector_count = 32;
-		info->size = 0x00200000;	/* => 2 MiB */
-		break;
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C:
-		info->flash_id += FLASH_AMDLV033C;
-		info->sector_count = 64;
-		info->size = 0x00400000;	/* => 4 MiB */
-		break;
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00080000;	/* => 512 KiB */
-		break;
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00080000;	/* => 512 KiB */
-		break;
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00100000;	/* => 1 MiB */
-		break;
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00100000;	/* => 1 MiB */
-		break;
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00200000;	/* => 2 MiB */
-		break;
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00200000;	/* => 2 MiB */
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);	/* => no or unknown flash */
-	}
-
-	/* set up sector start address table */
-	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
-	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00010000);
-	} else {
-		if (info->flash_id & FLASH_BTYPE) {
-			/* set sector offsets for bottom boot block type */
-			info->start[0] = base + 0x00000000;
-			info->start[1] = base + 0x00004000;
-			info->start[2] = base + 0x00006000;
-			info->start[3] = base + 0x00008000;
-			for (i = 4; i < info->sector_count; i++) {
-				info->start[i] =
-				    base + (i * 0x00010000) - 0x00030000;
-			}
-		} else {
-			/* set sector offsets for top boot block type */
-			i = info->sector_count - 1;
-			info->start[i--] = base + info->size - 0x00004000;
-			info->start[i--] = base + info->size - 0x00006000;
-			info->start[i--] = base + info->size - 0x00008000;
-			for (; i >= 0; i--) {
-				info->start[i] = base + i * 0x00010000;
-			}
-		}
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
-
-		/* For AMD29033C flash we need to resend the command of *
-		 * reading flash protection for upper 8 Mb of flash     */
-		if (i == 32) {
-			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
-			addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
-			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
-		}
-
-		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
-			info->protect[i] = 0;
-		else
-			info->protect[i] = addr2[2] & 1;
-	}
-
-	/* issue bank reset to return to read mode */
-	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
-
-	return (info->size);
-}
-
-static int wait_for_DQ7_1(flash_info_t * info, int sect)
-{
-	ulong start, now, last;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
-	    (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-	start = get_timer(0);
-	last = start;
-	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
-	       (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf("Timeout\n");
-			return -1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc('.');
-			last = now;
-		}
-	}
-	return 0;
-}
-
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
-	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
-	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
-	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) ||
-	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
-		return flash_erase_2(info, s_first, s_last);
-	} else {
-		return flash_erase_1(info, s_first, s_last);
-	}
-}
-
-static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
-#else
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-#endif
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
-	int flag, prot, sect;
-	int i;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf("- missing\n");
-		} else {
-			printf("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf("- Warning: %d protected sectors will not be erased!\n",
-		       prot);
-	} else {
-		printf("\n");
-	}
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
-				for (i = 0; i < 50; i++)
-					udelay(1000);	/* wait 1 ms */
-			} else {
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
-			}
-			/*
-			 * Wait for each sector to complete, it's more
-			 * reliable.  According to AMD Spec, you must
-			 * issue all erase commands within a specified
-			 * timeout.  This has been seen to fail, especially
-			 * if printf()s are included (for debug)!!
-			 */
-			wait_for_DQ7_1(info, sect);
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay(1000);
-
-	/* reset to read mode */
-	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
-
-	printf(" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-		for (; i < 4 && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < 4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i = 0; i < 4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < 4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *) cp);
-	}
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static int write_word(flash_info_t * info, ulong dest, ulong data)
-{
-	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
-	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
-	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) ||
-	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
-		return write_word_2(info, dest, data);
-	} else {
-		return write_word_1(info, dest, data);
-	}
-}
-
-static int write_word_1(flash_info_t * info, ulong dest, ulong data)
-#else
-static int write_word(flash_info_t * info, ulong dest, ulong data)
-#endif
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
-	ulong start;
-	int i;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data) {
-		return (2);
-	}
-
-	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
-		int flag;
-
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
-
-		dest2[i] = data2[i];
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		/* data polling for D7 */
-		start = get_timer(0);
-		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
-		       (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
-
-			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-				return (1);
-			}
-		}
-	}
-
-	return (0);
-}
-
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-
-#undef  CONFIG_SYS_FLASH_WORD_SIZE
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
-{
-	short i;
-	int n;
-	CONFIG_SYS_FLASH_WORD_SIZE value;
-	ulong base = (ulong) addr;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
-
-	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
-
-	/* Write auto select command: read Manufacturer ID */
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
-	udelay(1000);
-
-	value = addr2[0];
-	DEBUGF("FLASH MANUFACT: %x\n", value);
-
-	switch (value) {
-	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
-		info->flash_id = FLASH_MAN_SST;
-		break;
-	case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
-		info->flash_id = FLASH_MAN_STM;
-		break;
-	case (CONFIG_SYS_FLASH_WORD_SIZE) MX_MANUFACT:
-		info->flash_id = FLASH_MAN_MX;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);	/* no or unknown flash  */
-	}
-
-	value = addr2[1];	/* device ID */
-
-	DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
-	switch (value) {
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
-		info->flash_id += FLASH_AM320T;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MiB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MiB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT:
-		info->flash_id += FLASH_STMW320DT;
-		info->sector_count = 67;
-		info->size = 0x00400000;  break;	/* => 4 MiB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)MX_ID_LV320T:
-		info->flash_id += FLASH_MXLV320T;
-		info->sector_count = 71;
-		info->size = 0x00400000;
-		break;	/* => 4 MB	*/
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);	/* => no or unknown flash */
-	}
-
-	/* set up sector start address table */
-	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
-	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00010000);
-	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
-		/* set sector offsets for top boot block type		*/
-		base += info->size;
-		i = info->sector_count;
-		/*  1 x 16k boot sector */
-		base -= 16 << 10;
-		--i;
-		info->start[i] = base;
-		/*  2 x 8k  boot sectors */
-		for (n=0; n<2; ++n) {
-			base -= 8 << 10;
-			--i;
-			info->start[i] = base;
-		}
-		/*  1 x 32k boot sector */
-		base -= 32 << 10;
-		--i;
-		info->start[i] = base;
-
-		while (i > 0) {			/* 64k regular sectors	*/
-			base -= 64 << 10;
-			--i;
-			info->start[i] = base;
-		}
-	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) {
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00002000;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000a000;
-		info->start[i--] = base + info->size - 0x0000c000;
-		info->start[i--] = base + info->size - 0x0000e000;
-		info->start[i--] = base + info->size - 0x00010000;
-
-		for (; i >= 0; i--)
-			info->start[i] = base + i * 0x00010000;
-	} else {
-		if (info->flash_id & FLASH_BTYPE) {
-			/* set sector offsets for bottom boot block type */
-			info->start[0] = base + 0x00000000;
-			info->start[1] = base + 0x00002000;
-			info->start[2] = base + 0x00004000;
-			info->start[3] = base + 0x00006000;
-			info->start[4] = base + 0x00008000;
-			info->start[5] = base + 0x0000a000;
-			info->start[6] = base + 0x0000c000;
-			info->start[7] = base + 0x0000e000;
-			for (i = 8; i < info->sector_count; i++) {
-				info->start[i] =
-				    base + ((i-7) * 0x00010000);
-			}
-		} else {
-			/* set sector offsets for top boot block type */
-			i = info->sector_count - 1;
-			info->start[i--] = base + info->size - 0x00002000;
-			info->start[i--] = base + info->size - 0x00004000;
-			info->start[i--] = base + info->size - 0x00006000;
-			info->start[i--] = base + info->size - 0x00008000;
-			info->start[i--] = base + info->size - 0x0000a000;
-			info->start[i--] = base + info->size - 0x0000c000;
-			info->start[i--] = base + info->size - 0x0000e000;
-			for (; i >= 0; i--) {
-				info->start[i] = base + i * 0x00010000;
-			}
-		}
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
-
-		/* For AMD29033C flash we need to resend the command of *
-		 * reading flash protection for upper 8 Mb of flash     */
-		if (i == 32) {
-			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
-			addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
-			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
-		}
-
-		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
-			info->protect[i] = 0;
-		else
-			info->protect[i] = addr2[2] & 1;
-	}
-
-	/* issue bank reset to return to read mode */
-	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
-
-	return (info->size);
-}
-
-static int wait_for_DQ7_2(flash_info_t * info, int sect)
-{
-	ulong start, now, last;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
-	    (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-	start = get_timer(0);
-	last = start;
-	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
-	       (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf("Timeout\n");
-			return -1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc('.');
-			last = now;
-		}
-	}
-	return 0;
-}
-
-static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
-	int flag, prot, sect;
-	int i;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf("- missing\n");
-		} else {
-			printf("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf("- Warning: %d protected sectors will not be erased!\n",
-		       prot);
-	} else {
-		printf("\n");
-	}
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
-				for (i = 0; i < 50; i++)
-					udelay(1000);	/* wait 1 ms */
-			} else {
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
-			}
-			/*
-			 * Wait for each sector to complete, it's more
-			 * reliable.  According to AMD Spec, you must
-			 * issue all erase commands within a specified
-			 * timeout.  This has been seen to fail, especially
-			 * if printf()s are included (for debug)!!
-			 */
-			wait_for_DQ7_2(info, sect);
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay(1000);
-
-	/* reset to read mode */
-	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
-
-	printf(" done\n");
-	return 0;
-}
-
-static int write_word_2(flash_info_t * info, ulong dest, ulong data)
-{
-	ulong *data_ptr = &data;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
-	ulong start;
-	int i;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data) {
-		return (2);
-	}
-
-	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
-		int flag;
-
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
-
-		dest2[i] = data2[i];
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		/* data polling for D7 */
-		start = get_timer(0);
-		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
-		       (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
-
-			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-				return (1);
-			}
-		}
-	}
-
-	return (0);
-}
-#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */
diff --git a/board/amcc/katmai/Kconfig b/board/amcc/katmai/Kconfig
deleted file mode 100644
index 59d3ef5..0000000
--- a/board/amcc/katmai/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TARGET_KATMAI
-
-config SYS_BOARD
-	default "katmai"
-
-config SYS_VENDOR
-	default "amcc"
-
-config SYS_CONFIG_NAME
-	default "katmai"
-
-config DISPLAY_BOARDINFO
-	bool
-	default y
-
-endif
diff --git a/board/amcc/katmai/MAINTAINERS b/board/amcc/katmai/MAINTAINERS
deleted file mode 100644
index f089352..0000000
--- a/board/amcc/katmai/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-KATMAI BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/amcc/katmai/
-F:	include/configs/katmai.h
-F:	configs/katmai_defconfig
diff --git a/board/amcc/katmai/Makefile b/board/amcc/katmai/Makefile
deleted file mode 100644
index b738def..0000000
--- a/board/amcc/katmai/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= katmai.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-extra-y	+= init.o
diff --git a/board/amcc/katmai/chip_config.c b/board/amcc/katmai/chip_config.c
deleted file mode 100644
index 5e711c4..0000000
--- a/board/amcc/katmai/chip_config.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-struct ppc4xx_config ppc4xx_config_val[] = {
-	{
-		"400-133","CPU: 400 PLB: 133 OPB:  66 EBC:  66",
-		{ 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
-	},
-	{
-		"500-166","CPU: 500 PLB: 166 OPB:  83 EBC:  83",
-		{ 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
-	},
-	{
-		"533-133","CPU: 533 PLB: 133 OPB:  66 EBC:  66",
-		{ 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 }
-	},
-	{
-		"667-133","CPU: 667 PLB: 133 OPB:  66 EBC:  66",
-		{ 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 }
-	},
-	{
-		"667-166","CPU: 667 PLB: 166 OPB:  83 EBC:  83",
-		{ 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 }
-	},
-	{
-		"800-160","CPU: 800 PLB: 160 OPB:  53 EBC:  17",
-		{ 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 }
-	},
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/amcc/katmai/config.mk b/board/amcc/katmai/config.mk
deleted file mode 100644
index 6108f79..0000000
--- a/board/amcc/katmai/config.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-#
-# AMCC 440SPe Evaluation (Katmai) board
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S
deleted file mode 100644
index 32f2667..0000000
--- a/board/amcc/katmai/init.S
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-
-	.section .bootpg,"ax"
-
-/**************************************************************************
- * TLB table for revA
- *************************************************************************/
-	.globl tlbtabA
-tlbtabA:
-	tlbtab_start
-
-	/*
-	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
-	 * speed up boot process. It is patched after relocation to enable SA_I
-	 */
-	tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
-
-	/*
-	 * TLB entries for SDRAM are not needed on this platform.
-	 * They are dynamically generated in the SPD DDR(2) detection
-	 * routine.
-	 */
-
-	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
-	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
-	tlbtab_end
-
-/**************************************************************************
- * TLB table for revB
- *
- * Notice: revB of the 440SPe chip is very strict about PLB real addresses
- * and ranges to be mapped for config space: it seems to only work with
- * d_nnnn_nnnn range (hangs the core upon config transaction attempts when
- * set otherwise) while revA uses c_nnnn_nnnn.
- *************************************************************************/
-	.globl tlbtabB
-tlbtabB:
-	tlbtab_start
-
-	/*
-	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
-	 * speed up boot process. It is patched after relocation to enable SA_I
-	 */
-	tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
-
-	/*
-	 * TLB entries for SDRAM are not needed on this platform.
-	 * They are dynamically generated in the SPD DDR(2) detection
-	 * routine.
-	 */
-
-	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
-
-	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
-	tlbtab_end
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
deleted file mode 100644
index 6ae340b..0000000
--- a/board/amcc/katmai/katmai.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * (C) Copyright 2007-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <i2c.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <netdev.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/4xx_pcie.h>
-#include <asm/errno.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f (void)
-{
-	unsigned long mfr;
-
-	/*----------------------------------------------------------------------+
-	 * Interrupt controller setup for the Katmai 440SPe Evaluation board.
-	 *-----------------------------------------------------------------------+
-	 *-----------------------------------------------------------------------+
-	 * Interrupt | Source                            | Pol.  | Sensi.| Crit. |
-	 *-----------+-----------------------------------+-------+-------+-------+
-	 * IRQ 00    | UART0                             | High  | Level | Non   |
-	 * IRQ 01    | UART1                             | High  | Level | Non   |
-	 * IRQ 02    | IIC0                              | High  | Level | Non   |
-	 * IRQ 03    | IIC1                              | High  | Level | Non   |
-	 * IRQ 04    | PCI0X0 MSG IN                     | High  | Level | Non   |
-	 * IRQ 05    | PCI0X0 CMD Write                  | High  | Level | Non   |
-	 * IRQ 06    | PCI0X0 Power Mgt                  | High  | Level | Non   |
-	 * IRQ 07    | PCI0X0 VPD Access                 | Rising| Edge  | Non   |
-	 * IRQ 08    | PCI0X0 MSI level 0                | High  | Lvl/ed| Non   |
-	 * IRQ 09    | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non   |
-	 * IRQ 10    | UIC2 Non-critical Int.            | NA    | NA    | Non   |
-	 * IRQ 11    | UIC2 Critical Interrupt           | NA    | NA    | Crit  |
-	 * IRQ 12    | PCI Express MSI Level 0           | Rising| Edge  | Non   |
-	 * IRQ 13    | PCI Express MSI Level 1           | Rising| Edge  | Non   |
-	 * IRQ 14    | PCI Express MSI Level 2           | Rising| Edge  | Non   |
-	 * IRQ 15    | PCI Express MSI Level 3           | Rising| Edge  | Non   |
-	 * IRQ 16    | UIC3 Non-critical Int.            | NA    | NA    | Non   |
-	 * IRQ 17    | UIC3 Critical Interrupt           | NA    | NA    | Crit  |
-	 * IRQ 18    | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non   |
-	 * IRQ 19    | DMA Channel 0 FIFO Full           | High  | Level | Non   |
-	 * IRQ 20    | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
-	 * IRQ 21    | DMA Channel 1 FIFO Full           | High  | Level | Non   |
-	 * IRQ 22    | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
-	 * IRQ 23    | I2O Inbound Doorbell              | High  | Level | Non   |
-	 * IRQ 24    | Inbound Post List FIFO Not Empt   | High  | Level | Non   |
-	 * IRQ 25    | I2O Region 0 LL PLB Write         | High  | Level | Non   |
-	 * IRQ 26    | I2O Region 1 LL PLB Write         | High  | Level | Non   |
-	 * IRQ 27    | I2O Region 0 HB PLB Write         | High  | Level | Non   |
-	 * IRQ 28    | I2O Region 1 HB PLB Write         | High  | Level | Non   |
-	 * IRQ 29    | GPT Down Count Timer              | Rising| Edge  | Non   |
-	 * IRQ 30    | UIC1 Non-critical Int.            | NA    | NA    | Non   |
-	 * IRQ 31    | UIC1 Critical Interrupt           | NA    | NA    | Crit. |
-	 *------------------------------------------------------------------------
-	 * IRQ 32    | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non   |
-	 * IRQ 33    | MAL Serr                          | High  | Level | Non   |
-	 * IRQ 34    | MAL Txde                          | High  | Level | Non   |
-	 * IRQ 35    | MAL Rxde                          | High  | Level | Non   |
-	 * IRQ 36    | DMC CE or DMC UE                  | High  | Level | Non   |
-	 * IRQ 37    | EBC or UART2                      | High  |Lvl Edg| Non   |
-	 * IRQ 38    | MAL TX EOB                        | High  | Level | Non   |
-	 * IRQ 39    | MAL RX EOB                        | High  | Level | Non   |
-	 * IRQ 40    | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non   |
-	 * IRQ 41    | PCIX0 MSI level 2                 | High  |Lvl Edg| Non   |
-	 * IRQ 42    | PCIX0 MSI level 3                 | High  |Lvl Edg| Non   |
-	 * IRQ 43    | L2 Cache                          | Risin | Edge  | Non   |
-	 * IRQ 44    | GPT Compare Timer 0               | Risin | Edge  | Non   |
-	 * IRQ 45    | GPT Compare Timer 1               | Risin | Edge  | Non   |
-	 * IRQ 46    | GPT Compare Timer 2               | Risin | Edge  | Non   |
-	 * IRQ 47    | GPT Compare Timer 3               | Risin | Edge  | Non   |
-	 * IRQ 48    | GPT Compare Timer 4               | Risin | Edge  | Non   |
-	 * IRQ 49    | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non   |
-	 * IRQ 50    | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non   |
-	 * IRQ 51    | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non   |
-	 * IRQ 52    | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
-	 * IRQ 53    | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non   |
-	 * IRQ 54    | DMA Error                         | High  | Level | Non   |
-	 * IRQ 55    | DMA I2O Error                     | High  | Level | Non   |
-	 * IRQ 56    | Serial ROM                        | High  | Level | Non   |
-	 * IRQ 57    | PCIX0 Error                       | High  | Edge  | Non   |
-	 * IRQ 58    | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non   |
-	 * IRQ 59    | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non   |
-	 * IRQ 60    | EMAC0 Interrupt                   | High  | Level | Non   |
-	 * IRQ 61    | EMAC0 Wake-up                     | High  | Level | Non   |
-	 * IRQ 62    | Reserved                          | High  | Level | Non   |
-	 * IRQ 63    | XOR                               | High  | Level | Non   |
-	 *-----------------------------------------------------------------------
-	 * IRQ 64    | PE0 AL                            | High  | Level | Non   |
-	 * IRQ 65    | PE0 VPD Access                    | Risin | Edge  | Non   |
-	 * IRQ 66    | PE0 Hot Reset Request             | Risin | Edge  | Non   |
-	 * IRQ 67    | PE0 Hot Reset Request             | Falli | Edge  | Non   |
-	 * IRQ 68    | PE0 TCR                           | High  | Level | Non   |
-	 * IRQ 69    | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
-	 * IRQ 70    | PE0 DCR Error                     | High  | Level | Non   |
-	 * IRQ 71    | Reserved                          | N/A   | N/A   | Non   |
-	 * IRQ 72    | PE1 AL                            | High  | Level | Non   |
-	 * IRQ 73    | PE1 VPD Access                    | Risin | Edge  | Non   |
-	 * IRQ 74    | PE1 Hot Reset Request             | Risin | Edge  | Non   |
-	 * IRQ 75    | PE1 Hot Reset Request             | Falli | Edge  | Non   |
-	 * IRQ 76    | PE1 TCR                           | High  | Level | Non   |
-	 * IRQ 77    | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
-	 * IRQ 78    | PE1 DCR Error                     | High  | Level | Non   |
-	 * IRQ 79    | Reserved                          | N/A   | N/A   | Non   |
-	 * IRQ 80    | PE2 AL                            | High  | Level | Non   |
-	 * IRQ 81    | PE2 VPD Access                    | Risin | Edge  | Non   |
-	 * IRQ 82    | PE2 Hot Reset Request             | Risin | Edge  | Non   |
-	 * IRQ 83    | PE2 Hot Reset Request             | Falli | Edge  | Non   |
-	 * IRQ 84    | PE2 TCR                           | High  | Level | Non   |
-	 * IRQ 85    | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
-	 * IRQ 86    | PE2 DCR Error                     | High  | Level | Non   |
-	 * IRQ 87    | Reserved                          | N/A   | N/A   | Non   |
-	 * IRQ 88    | External IRQ(5)                   | Progr | Progr | Non   |
-	 * IRQ 89    | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
-	 * IRQ 90    | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
-	 * IRQ 91    | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
-	 * IRQ 92    | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
-	 * IRQ 93    | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
-	 * IRQ 94    | Reserved                          | N/A   | N/A   | Non   |
-	 * IRQ 95    | Reserved                          | N/A   | N/A   | Non   |
-	 *-----------------------------------------------------------------------
-	 * IRQ 96    | PE0 INTA                          | High  | Level | Non   |
-	 * IRQ 97    | PE0 INTB                          | High  | Level | Non   |
-	 * IRQ 98    | PE0 INTC                          | High  | Level | Non   |
-	 * IRQ 99    | PE0 INTD                          | High  | Level | Non   |
-	 * IRQ 100   | PE1 INTA                          | High  | Level | Non   |
-	 * IRQ 101   | PE1 INTB                          | High  | Level | Non   |
-	 * IRQ 102   | PE1 INTC                          | High  | Level | Non   |
-	 * IRQ 103   | PE1 INTD                          | High  | Level | Non   |
-	 * IRQ 104   | PE2 INTA                          | High  | Level | Non   |
-	 * IRQ 105   | PE2 INTB                          | High  | Level | Non   |
-	 * IRQ 106   | PE2 INTC                          | High  | Level | Non   |
-	 * IRQ 107   | PE2 INTD                          | Risin | Edge  | Non   |
-	 * IRQ 108   | PCI Express MSI Level 4           | Risin | Edge  | Non   |
-	 * IRQ 109   | PCI Express MSI Level 5           | Risin | Edge  | Non   |
-	 * IRQ 110   | PCI Express MSI Level 6           | Risin | Edge  | Non   |
-	 * IRQ 111   | PCI Express MSI Level 7           | Risin | Edge  | Non   |
-	 * IRQ 116   | PCI Express MSI Level 12          | Risin | Edge  | Non   |
-	 * IRQ 112   | PCI Express MSI Level 8           | Risin | Edge  | Non   |
-	 * IRQ 113   | PCI Express MSI Level 9           | Risin | Edge  | Non   |
-	 * IRQ 114   | PCI Express MSI Level 10          | Risin | Edge  | Non   |
-	 * IRQ 115   | PCI Express MSI Level 11          | Risin | Edge  | Non   |
-	 * IRQ 117   | PCI Express MSI Level 13          | Risin | Edge  | Non   |
-	 * IRQ 118   | PCI Express MSI Level 14          | Risin | Edge  | Non   |
-	 * IRQ 119   | PCI Express MSI Level 15          | Risin | Edge  | Non   |
-	 * IRQ 120   | PCI Express MSI Level 16          | Risin | Edge  | Non   |
-	 * IRQ 121   | PCI Express MSI Level 17          | Risin | Edge  | Non   |
-	 * IRQ 122   | PCI Express MSI Level 18          | Risin | Edge  | Non   |
-	 * IRQ 123   | PCI Express MSI Level 19          | Risin | Edge  | Non   |
-	 * IRQ 124   | PCI Express MSI Level 20          | Risin | Edge  | Non   |
-	 * IRQ 125   | PCI Express MSI Level 21          | Risin | Edge  | Non   |
-	 * IRQ 126   | PCI Express MSI Level 22          | Risin | Edge  | Non   |
-	 * IRQ 127   | PCI Express MSI Level 23          | Risin | Edge  | Non   |
-	 *-----------+-----------------------------------+-------+-------+-------+ */
-	/*-------------------------------------------------------------------------+
-	 * Put UICs in PowerPC440SPemode.
-	 * Initialise UIC registers.  Clear all interrupts.  Disable all interrupts.
-	 * Set critical interrupt values.  Set interrupt polarities.  Set interrupt
-	 * trigger levels.  Make bit 0 High  priority.  Clear all interrupts again.
-	 *------------------------------------------------------------------------*/
-	mtdcr (UIC3SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (UIC3ER, 0x00000000);	/* disable all interrupts */
-	mtdcr (UIC3CR, 0x00000000);	/* Set Critical / Non Critical interrupts: */
-	mtdcr (UIC3PR, 0xffffffff);	/* Set Interrupt Polarities*/
-	mtdcr (UIC3TR, 0x001fffff);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC3VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (UIC3SR, 0x00000000);	/* clear all  interrupts*/
-	mtdcr (UIC3SR, 0xffffffff);	/* clear all  interrupts*/
-
-
-	mtdcr (UIC2SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (UIC2ER, 0x00000000);	/* disable all interrupts*/
-	mtdcr (UIC2CR, 0x00000000);	/* Set Critical / Non Critical interrupts*/
-	mtdcr (UIC2PR, 0xebebebff);	/* Set Interrupt Polarities*/
-	mtdcr (UIC2TR, 0x74747400);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC2VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (UIC2SR, 0x00000000);	/* clear all interrupts */
-	mtdcr (UIC2SR, 0xffffffff);	/* clear all interrupts */
-
-	mtdcr (UIC1SR, 0xffffffff);	/* Clear all interrupts*/
-	mtdcr (UIC1ER, 0x00000000);	/* disable all interrupts*/
-	mtdcr (UIC1CR, 0x00000000);	/* Set Critical / Non Critical interrupts*/
-	mtdcr (UIC1PR, 0xffffffff);	/* Set Interrupt Polarities */
-	mtdcr (UIC1TR, 0x001f8040);	/* Set Interrupt Trigger Levels*/
-	mtdcr (UIC1VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (UIC1SR, 0x00000000);	/* clear all interrupts*/
-	mtdcr (UIC1SR, 0xffffffff);	/* clear all interrupts*/
-
-	mtdcr (UIC0SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (UIC0ER, 0x00000000);	/* disable all interrupts excepted cascade    to be checked */
-	mtdcr (UIC0CR, 0x00104001);	/* Set Critical / Non Critical interrupts*/
-	mtdcr (UIC0PR, 0xffffffff);	/* Set Interrupt Polarities*/
-	mtdcr (UIC0TR, 0x010f0004);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC0VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (UIC0SR, 0x00000000);	/* clear all interrupts*/
-	mtdcr (UIC0SR, 0xffffffff);	/* clear all interrupts*/
-
-	mfsdr(SDR0_MFR, mfr);
-	mfr |= SDR0_MFR_FIXD;		/* Workaround for PCI/DMA */
-	mtsdr(SDR0_MFR, mfr);
-
-	mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
-
-	out32(GPIO0_OR, CONFIG_SYS_GPIO_OR);
-	out32(GPIO0_ODR, CONFIG_SYS_GPIO_ODR);
-	out32(GPIO0_TCR, CONFIG_SYS_GPIO_TCR);
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf("Board: Katmai - AMCC 440SPe Evaluation Board");
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-/*
- * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
- * board specific values.
- */
-u32 ddr_wrdtr(u32 default_val) {
-	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
-}
-
-u32 ddr_clktr(u32 default_val) {
-	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
-}
-
-#if defined(CONFIG_PCI)
-int board_pcie_card_present(int port)
-{
-	u32 val;
-
-	val = in32(GPIO0_IR);
-	switch (port) {
-	case 0:
-		return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0));
-	case 1:
-		return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1));
-	case 2:
-		return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2));
-	default:
-		return 0;
-	}
-}
-#endif	/* defined(CONFIG_PCI) */
-
-int board_eth_init(bd_t *bis)
-{
-	cpu_eth_init(bis);
-	return pci_eth_init(bis);
-}
diff --git a/board/amcc/kilauea/Kconfig b/board/amcc/kilauea/Kconfig
deleted file mode 100644
index 5dfd9eb..0000000
--- a/board/amcc/kilauea/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TARGET_KILAUEA
-
-config SYS_BOARD
-	default "kilauea"
-
-config SYS_VENDOR
-	default "amcc"
-
-config SYS_CONFIG_NAME
-	default "kilauea"
-
-config DISPLAY_BOARDINFO
-	bool
-	default y
-
-endif
diff --git a/board/amcc/kilauea/MAINTAINERS b/board/amcc/kilauea/MAINTAINERS
deleted file mode 100644
index 12bbcb1..0000000
--- a/board/amcc/kilauea/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-KILAUEA BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/amcc/kilauea/
-F:	include/configs/kilauea.h
-F:	configs/haleakala_defconfig
-F:	configs/kilauea_defconfig
diff --git a/board/amcc/kilauea/Makefile b/board/amcc/kilauea/Makefile
deleted file mode 100644
index 754dadc..0000000
--- a/board/amcc/kilauea/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= kilauea.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
diff --git a/board/amcc/kilauea/chip_config.c b/board/amcc/kilauea/chip_config.c
deleted file mode 100644
index 7e9dd3b..0000000
--- a/board/amcc/kilauea/chip_config.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */
-
-struct ppc4xx_config ppc4xx_config_val[] = {
-	{
-		"333-nor","NOR  CPU: 333 PLB: 166 OPB:  83 EBC:  83",
-		{
-			0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
-			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"400-133-nor", "NOR  CPU: 400 PLB: 133 OPB:  66 EBC:  66",
-		{
-			0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
-			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"400-nor", "NOR  CPU: 400 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
-			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"533-nor", "NOR  CPU: 533 PLB: 177 OPB:  88 EBC:  88",
-		{
-			0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
-			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"533-nand", "NOR  CPU: 533 PLB: 177 OPB:  88 EBC:  88",
-		{
-			0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00,
-			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"600-nor", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
-			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"600-nand", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00,
-			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"666-nor", "NOR  CPU: 666 PLB: 222 OPB: 111 EBC: 111",
-		{
-			0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
-			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-		}
-	},
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/amcc/kilauea/config.mk b/board/amcc/kilauea/config.mk
deleted file mode 100644
index 0dc15c1..0000000
--- a/board/amcc/kilauea/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2007-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
deleted file mode 100644
index abfaa1e..0000000
--- a/board/amcc/kilauea/kilauea.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc405.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#include <asm/4xx_pcie.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-static int board_cpld_version(void)
-{
-	u32 cpld;
-
-	cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE);
-	if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) {
-		/*
-		 * Magic not found -> "old" CPLD revision which needs
-		 * the "old" EBC configuration
-		 */
-		mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) |
-		      EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE |
-		      EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) |
-		      EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) |
-		      EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) |
-		      EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED |
-		      EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED);
-
-		/*
-		 * Return 0 for "old" CPLD version
-		 */
-		return 0;
-	}
-
-	/*
-	 * Magic found -> "new" CPLD revision which needs no new
-	 * EBC configuration
-	 */
-	return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8;
-}
-
-/*
- * Board early initialization function
- */
-int board_early_init_f (void)
-{
-	u32 val;
-
-	/*--------------------------------------------------------------------+
-	 | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
-	 +--------------------------------------------------------------------+
-	+---------------------------------------------------------------------+
-	|Interrupt| Source                            | Pol.  | Sensi.| Crit. |
-	+---------+-----------------------------------+-------+-------+-------+
-	| IRQ 00  | UART0                             | High  | Level | Non   |
-	| IRQ 01  | UART1                             | High  | Level | Non   |
-	| IRQ 02  | IIC0                              | High  | Level | Non   |
-	| IRQ 03  | TBD                               | High  | Level | Non   |
-	| IRQ 04  | TBD                               | High  | Level | Non   |
-	| IRQ 05  | EBM                               | High  | Level | Non   |
-	| IRQ 06  | BGI                               | High  | Level | Non   |
-	| IRQ 07  | IIC1                              | Rising| Edge  | Non   |
-	| IRQ 08  | SPI                               | High  | Lvl/ed| Non   |
-	| IRQ 09  | External IRQ 0 - (PCI-Express)    | pgm H | Pgm   | Non   |
-	| IRQ 10  | MAL TX EOB                        | High  | Level | Non   |
-	| IRQ 11  | MAL RX EOB                        | High  | Level | Non   |
-	| IRQ 12  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
-	| IRQ 13  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
-	| IRQ 14  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
-	| IRQ 15  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
-	| IRQ 16  | PCIE0 AL                          | high  | Level | Non   |
-	| IRQ 17  | PCIE0 VPD access                  | rising| Edge  | Non   |
-	| IRQ 18  | PCIE0 hot reset request           | rising| Edge  | Non   |
-	| IRQ 19  | PCIE0 hot reset request           | faling| Edge  | Non   |
-	| IRQ 20  | PCIE0 TCR                         | High  | Level | Non   |
-	| IRQ 21  | PCIE0 MSI level0                  | High  | Level | Non   |
-	| IRQ 22  | PCIE0 MSI level1                  | High  | Level | Non   |
-	| IRQ 23  | Security EIP-94                   | High  | Level | Non   |
-	| IRQ 24  | EMAC0 interrupt                   | High  | Level | Non   |
-	| IRQ 25  | EMAC1 interrupt                   | High  | Level | Non   |
-	| IRQ 26  | PCIE0 MSI level2                  | High  | Level | Non   |
-	| IRQ 27  | External IRQ 4                    | pgm H | Pgm   | Non   |
-	| IRQ 28  | UIC2 Non-critical Int.            | High  | Level | Non   |
-	| IRQ 29  | UIC2 Critical Interrupt           | High  | Level | Crit. |
-	| IRQ 30  | UIC1 Non-critical Int.            | High  | Level | Non   |
-	| IRQ 31  | UIC1 Critical Interrupt           | High  | Level | Crit. |
-	|----------------------------------------------------------------------
-	| IRQ 32  | MAL Serr                          | High  | Level | Non   |
-	| IRQ 33  | MAL Txde                          | High  | Level | Non   |
-	| IRQ 34  | MAL Rxde                          | High  | Level | Non   |
-	| IRQ 35  | PCIE0 bus master VC0              |falling| Edge  | Non   |
-	| IRQ 36  | PCIE0 DCR Error                   | High  | Level | Non   |
-	| IRQ 37  | EBC                               | High  |Lvl Edg| Non   |
-	| IRQ 38  | NDFC                              | High  | Level | Non   |
-	| IRQ 39  | GPT Compare Timer 8               | Risin | Edge  | Non   |
-	| IRQ 40  | GPT Compare Timer 9               | Risin | Edge  | Non   |
-	| IRQ 41  | PCIE1 AL                          | high  | Level | Non   |
-	| IRQ 42  | PCIE1 VPD access                  | rising| edge  | Non   |
-	| IRQ 43  | PCIE1 hot reset request           | rising| Edge  | Non   |
-	| IRQ 44  | PCIE1 hot reset request           | faling| Edge  | Non   |
-	| IRQ 45  | PCIE1 TCR                         | High  | Level | Non   |
-	| IRQ 46  | PCIE1 bus master VC0              |falling| Edge  | Non   |
-	| IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
-	| IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
-	| IRQ 49  | Ext. IRQ 7                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 50  | Ext. IRQ 8 -                      |pgm (H)|pgm/Lvl| Non   |
-	| IRQ 51  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
-	| IRQ 52  | GPT Compare Timer 5               | high  | Edge  | Non   |
-	| IRQ 53  | GPT Compare Timer 6               | high  | Edge  | Non   |
-	| IRQ 54  | GPT Compare Timer 7               | high  | Edge  | Non   |
-	| IRQ 55  | Serial ROM                        | High  | Level | Non   |
-	| IRQ 56  | GPT Decrement Pulse               | High  | Level | Non   |
-	| IRQ 57  | Ext. IRQ 2                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 58  | Ext. IRQ 5                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 59  | Ext. IRQ 6                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 60  | EMAC0 Wake-up                     | High  | Level | Non   |
-	| IRQ 61  | Ext. IRQ 1                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 62  | EMAC1 Wake-up                     | High  | Level | Non   |
-	|----------------------------------------------------------------------
-	| IRQ 64  | PE0 AL                            | High  | Level | Non   |
-	| IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
-	| IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
-	| IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
-	| IRQ 68  | PE0 TCR                           | High  | Level | Non   |
-	| IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
-	| IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
-	| IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 72  | PE1 AL                            | High  | Level | Non   |
-	| IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
-	| IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
-	| IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
-	| IRQ 76  | PE1 TCR                           | High  | Level | Non   |
-	| IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
-	| IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
-	| IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 80  | PE2 AL                            | High  | Level | Non   |
-	| IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
-	| IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
-	| IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
-	| IRQ 84  | PE2 TCR                           | High  | Level | Non   |
-	| IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
-	| IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
-	| IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
-	| IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
-	| IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
-	|---------------------------------------------------------------------
-	+---------+-----------------------------------+-------+-------+------*/
-	/*--------------------------------------------------------------------+
-	 | Initialise UIC registers.  Clear all interrupts.  Disable all
-	 | interrupts.
-	 | Set critical interrupt values.  Set interrupt polarities.  Set
-	 | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
-	 | interrupts again.
-	 +-------------------------------------------------------------------*/
-
-	mtdcr (UIC2SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (UIC2ER, 0x00000000);	/* disable all interrupts */
-	mtdcr (UIC2CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (UIC2PR, 0xf7ffffff);	/* Set Interrupt Polarities */
-	mtdcr (UIC2TR, 0x01e1fff8);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC2VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (UIC2SR, 0x00000000);	/* clear all interrupts */
-	mtdcr (UIC2SR, 0xffffffff);	/* clear all interrupts */
-
-	mtdcr (UIC1SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (UIC1ER, 0x00000000);	/* disable all interrupts */
-	mtdcr (UIC1CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (UIC1PR, 0xfffac785);	/* Set Interrupt Polarities */
-	mtdcr (UIC1TR, 0x001d0040);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC1VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (UIC1SR, 0x00000000);	/* clear all interrupts */
-	mtdcr (UIC1SR, 0xffffffff);	/* clear all interrupts */
-
-	mtdcr (UIC0SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (UIC0ER, 0x0000000a);	/* Disable all interrupts */
-					/* Except cascade UIC0 and UIC1 */
-	mtdcr (UIC0CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (UIC0PR, 0xffbfefef);	/* Set Interrupt Polarities */
-	mtdcr (UIC0TR, 0x00007000);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC0VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (UIC0SR, 0x00000000);	/* clear all interrupts */
-	mtdcr (UIC0SR, 0xffffffff);	/* clear all interrupts */
-
-	/*
-	 * Note: Some cores are still in reset when the chip starts, so
-	 * take them out of reset
-	 */
-	mtsdr(SDR0_SRST, 0);
-
-	/* Configure 405EX for NAND usage */
-	val = SDR0_CUST0_MUX_NDFC_SEL |
-		SDR0_CUST0_NDFC_ENABLE |
-		SDR0_CUST0_NDFC_BW_8_BIT |
-		SDR0_CUST0_NRB_BUSY |
-		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
-	mtsdr(SDR0_CUST0, val);
-
-	/*
-	 * Configure PFC (Pin Function Control) registers
-	 * -> Enable USB
-	 */
-	val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
-	mtsdr(SDR0_PFC1, val);
-
-	/*
-	 * The CPLD version detection has to be the first access to
-	 * the CPLD, so we need to make this access this early and
-	 * save the CPLD version for later.
-	 */
-	gd->board_type = board_cpld_version();
-
-	/*
-	 * Configure FPGA register with PCIe reset
-	 */
-	out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4);	/* assert PCIe reset */
-	mdelay(50);
-	out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7);	/* deassert PCIe reset */
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_ENV_IS_IN_FLASH
-	/* Monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      -CONFIG_SYS_MONITOR_LEN,
-		      0xffffffff,
-		      &flash_info[0]);
-#endif
-
-	return 0;
-}
-
-static int is_405exr(void)
-{
-	u32 pvr = get_pvr();
-
-	if (pvr & 0x00000004)
-		return 0;		/* bit 2 set -> 405EX */
-
-	return 1;			/* bit 2 cleared -> 405EXr */
-}
-
-int board_emac_count(void)
-{
-	/*
-	 * 405EXr only has one EMAC interface, 405EX has two
-	 */
-	if (is_405exr())
-		return 1;
-	else
-		return 2;
-}
-
-/*
- * Override the weak default implementation and return the
- * last PCIe slot number (max number - 1).
- */
-int board_pcie_last(void)
-{
-	/*
-	 * 405EXr only has one EMAC interface, 405EX has two
-	 */
-	if (is_405exr())
-		return 1 - 1;
-	else
-		return 2 - 1;
-}
-
-int checkboard (void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	if (is_405exr())
-		printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board");
-	else
-		printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	printf(" (CPLD rev. %ld)\n", gd->board_type);
-
-	return (0);
-}
diff --git a/board/amcc/luan/Kconfig b/board/amcc/luan/Kconfig
deleted file mode 100644
index 36b44ff..0000000
--- a/board/amcc/luan/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TARGET_LUAN
-
-config SYS_BOARD
-	default "luan"
-
-config SYS_VENDOR
-	default "amcc"
-
-config SYS_CONFIG_NAME
-	default "luan"
-
-config DISPLAY_BOARDINFO
-	bool
-	default y
-
-endif
diff --git a/board/amcc/luan/MAINTAINERS b/board/amcc/luan/MAINTAINERS
deleted file mode 100644
index a23296d..0000000
--- a/board/amcc/luan/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-LUAN BOARD
-M:	John Otken <jotken@softadvances.com>
-S:	Maintained
-F:	board/amcc/luan/
-F:	include/configs/luan.h
-F:	configs/luan_defconfig
diff --git a/board/amcc/luan/Makefile b/board/amcc/luan/Makefile
deleted file mode 100644
index 345ad56..0000000
--- a/board/amcc/luan/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= luan.o flash.o
-extra-y	+= init.o
diff --git a/board/amcc/luan/config.mk b/board/amcc/luan/config.mk
deleted file mode 100644
index f18b097..0000000
--- a/board/amcc/luan/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/amcc/luan/epld.h b/board/amcc/luan/epld.h
deleted file mode 100644
index 569d78c..0000000
--- a/board/amcc/luan/epld.h
+++ /dev/null
@@ -1,85 +0,0 @@
-#define EPLD0_FSEL_FB2		0x80
-#define EPLD0_BOOT_SMALL_FLASH	0x40	/* 0 boot from large flash, 1 from small flash */
-#define EPLD0_RAW_CARD_BIT0	0x20	/* raw card EC level */
-#define EPLD0_RAW_CARD_BIT1	0x10
-#define EPLD0_RAW_CARD_BIT2	0x08
-#define EPLD0_EXT_ARB_SEL_N	0x04	/* 0 select on-board ext PCI-X, 1 internal arbiter */
-#define EPLD0_FLASH_ONBRD_N	0x02	/* 0 small flash/SRAM active, 1 block access */
-#define EPLD0_FLASH_SRAM_SEL_N	0x01	/* 0 SRAM at mem top, 1 small flash at mem top */
-
-#define EPLD1_CLK_CNTL0		0x80	/* FSEL-FB1 of MPC9772 */
-#define EPLD1_PCIL0_CNTL1	0x40	/* S*0 of 9531 */
-#define EPLD1_PCIL0_CNTL2	0x20	/* S*1 of 9531 */
-#define EPLD1_CLK_CNTL3		0x10	/* FSEL-B1 of MPC9772 */
-#define EPLD1_CLK_CNTL4		0x08	/* FSEL-B0 of MPC9772 */
-#define EPLD1_MASTER_CLOCK6	0x04	/* clock source select 6 */
-#define EPLD1_MASTER_CLOCK7	0x02	/* clock source select 7 */
-#define EPLD1_MASTER_CLOCK8	0x01	/* clock source select 8 */
-
-#define EPLD2_ETH_MODE_10	0x80	/* Ethernet mode 10   (default = 1) */
-#define EPLD2_ETH_MODE_100	0x40	/* Ethernet mode 100  (default = 1) */
-#define EPLD2_ETH_MODE_1000	0x20	/* Ethernet mode 1000 (default = 1) */
-#define EPLD2_ETH_DUPLEX_MODE	0x10	/* Ethernet force full duplex mode */
-#define EPLD2_RESET_ETH_N	0x08	/* Ethernet reset (default = 1) */
-#define EPLD2_ETH_AUTO_NEGO	0x04	/* Ethernet auto negotiation */
-#define EPLD2_DEFAULT_UART_N	0x01	/* 0 select DSR DTR for UART1 */
-
-#define EPLD3_STATUS_LED4	0x08	/* status LED 8 (1 = LED on) */
-#define EPLD3_STATUS_LED3	0x04	/* status LED 4 (1 = LED on) */
-#define EPLD3_STATUS_LED2	0x02	/* status LED 2 (1 = LED on) */
-#define EPLD3_STATUS_LED1	0x01	/* status LED 1 (1 = LED on) */
-
-#define EPLD4_PCIL0_VTH1	0x80	/* PCI-X 0 VTH1 status */
-#define EPLD4_PCIL0_VTH2	0x40	/* PCI-X 0 VTH2 status */
-#define EPLD4_PCIL0_VTH3	0x20	/* PCI-X 0 VTH3 status */
-#define EPLD4_PCIL0_VTH4	0x10	/* PCI-X 0 VTH4 status */
-#define EPLD4_PCIX1_VTH1	0x08	/* PCI-X 1 VTH1 status */
-#define EPLD4_PCIX1_VTH2	0x04	/* PCI-X 1 VTH2 status */
-#define EPLD4_PCIX1_VTH3	0x02	/* PCI-X 1 VTH3 status */
-#define EPLD4_PCIX1_VTH4	0x01	/* PCI-X 1 VTH4 status */
-
-#define EPLD5_PCIL0_INT0	0x80	/* PCIX0 INT0 status, write 0 to reset */
-#define EPLD5_PCIL0_INT1	0x40	/* PCIX0 INT1 status, write 0 to reset */
-#define EPLD5_PCIL0_INT2	0x20	/* PCIX0 INT2 status, write 0 to reset */
-#define EPLD5_PCIL0_INT3	0x10	/* PCIX0 INT3 status, write 0 to reset */
-#define EPLD5_PCIX1_INT0	0x08	/* PCIX1 INT0 status, write 0 to reset */
-#define EPLD5_PCIX1_INT1	0x04	/* PCIX1 INT1 status, write 0 to reset */
-#define EPLD5_PCIX1_INT2	0x02	/* PCIX1 INT2 status, write 0 to reset */
-#define EPLD5_PCIX1_INT3	0x01	/* PCIX1 INT3 status, write 0 to reset */
-
-#define EPLD6_PCIL0_RESET_CTL	0x80	/* 0=enable slot reset, 1=disable slot reset */
-#define EPLD6_PCIX1_RESET_CTL	0x40	/* 0=enable slot reset, 1=disable slot reset */
-#define EPLD6_ETH_INT_MODE	0x20	/* 0=IRQ5 recv's external eth int */
-#define EPLD6_PCIX2_RESET_CTL	0x10	/* 0=enable slot reset, 1=disable slot reset */
-#define EPLD6_PCI1_CLKCNTL1	0x80	/* PCI1 clock control S*0 of 9531 */
-#define EPLD6_PCI1_CLKCNTL2	0x40	/* PCI1 clock control S*1 of 9531 */
-#define EPLD6_PCI2_CLKCNTL1	0x20	/* PCI2 clock control S*0 of 9531 */
-#define EPLD6_PCI2_CLKCNTL2	0x10	/* PCI2 clock control S*1 of 9531 */
-
-#define EPLD7_VTH1		0x80	/* PCI2 VTH1 status */
-#define EPLD7_VTH2		0x40	/* PCI2 VTH2 status */
-#define EPLD7_VTH3		0x20	/* PCI2 VTH3 status */
-#define EPLD7_VTH4		0x10	/* PCI2 VTH4 status */
-#define EPLD7_INTA_MODE		0x80	/* see S5 on SW2 for details */
-#define EPLD7_PCI_INT_MODE_N	0x40	/* see S1 on SW2 for details */
-#define EPLD7_WRITE_ENABLE_GPIO	0x20	/* see S2 on SW2 for details */
-#define EPLD7_WRITE_ENABLE_INT	0x10	/* see S3 on SW2 for details */
-
-
-typedef struct {
-    unsigned char  status;		/* misc status */
-    unsigned char  clock;		/* clock status, PCI-X clock control */
-    unsigned char  ethuart;		/* Ethernet, UART status */
-    unsigned char  leds;		/* LED register */
-    unsigned char  vth01;		/* PCI0, PCI1 VTH register */
-    unsigned char  pciints;		/* PCI0, PCI1 interrupts */
-    unsigned char  pci2;		/* PCI2 interrupts, clock control */
-    unsigned char  vth2;		/* PCI2 VTH register */
-    unsigned char  filler1[4096-8];
-    unsigned char  gpio00;		/* GPIO bits  0-7 */
-    unsigned char  gpio08;		/* GPIO bits  8-15 */
-    unsigned char  gpio16;		/* GPIO bits 16-23 */
-    unsigned char  gpio24;		/* GPIO bits 24-31 */
-    unsigned char  filler2[4096-4];
-    unsigned char  version;		/* EPLD version */
-} epld_t;
diff --git a/board/amcc/luan/flash.c b/board/amcc/luan/flash.c
deleted file mode 100644
index a242bef..0000000
--- a/board/amcc/luan/flash.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
- * Add support for Am29F016D and dynamic switch setting.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-#undef DEBUG
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif				/* DEBUG */
-
-static unsigned long flash_addr_table[1][CONFIG_SYS_MAX_FLASH_BANKS] = {
-	{0xff900000, 0xff980000, 0xffc00000},	/* 0:000: configuraton 3 */
-};
-
-/*
- * include common flash code (for amcc boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-
-unsigned long flash_init(void)
-{
-	unsigned long total_b = 0;
-	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
-	unsigned short index = 0;
-	int i;
-
-	/* read FPGA base register FPGA_REG0 */
-
-	DEBUGF("\n");
-	DEBUGF("FLASH: Index: %d\n", index);
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-		flash_info[i].sector_count = -1;
-		flash_info[i].size = 0;
-
-		/* check whether the address is 0 */
-		if (flash_addr_table[index][i] == 0) {
-			continue;
-		}
-
-		/* call flash_get_size() to initialize sector address */
-		size_b[i] = flash_get_size((vu_long *)
-					   flash_addr_table[index][i],
-					   &flash_info[i]);
-		flash_info[i].size = size_b[i];
-		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
-			       i, size_b[i], size_b[i] << 20);
-			flash_info[i].sector_count = -1;
-			flash_info[i].size = 0;
-		}
-
-		/* Monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
-				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
-				    &flash_info[2]);
-#ifdef CONFIG_ENV_IS_IN_FLASH
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
-				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[2]);
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
-				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[2]);
-#endif
-
-		total_b += flash_info[i].size;
-	}
-
-	return total_b;
-}
diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S
deleted file mode 100644
index 0f4a78e..0000000
--- a/board/amcc/luan/init.S
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-
-	.section .bootpg,"ax"
-	.globl tlbtab
-
-tlbtab:
-	tlbtab_start
-
-	/*
-	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
-	 * speed up boot process. It is patched after relocation to enable SA_I
-	 */
-	tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_RWX | SA_G)
-
-	tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_RWX | SA_IG)
-	tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_RWX | SA_IG)
-	tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_RWX | SA_IG)
-	tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_RWX | SA_IG)
-	tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_RW | SA_IG)
-
-	/*
-	 * TLB entries for SDRAM are not needed on this platform.
-	 * They are dynamically generated in the SPD DDR(2) detection
-	 * routine.
-	 */
-
-	/* internal ram (l2 cache) */
-	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_I)
-
-	/* peripherals at f0000000 */
-	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_RW | SA_IG)
-
-	/* PCI */
-	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_RW | SA_IG)
-	tlbtab_end
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
deleted file mode 100644
index 774671d..0000000
--- a/board/amcc/luan/luan.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * (C) Copyright 2005
- * John Otken, jotken@softadvances.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-isram.h>
-#include <spd_sdram.h>
-#include "epld.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-
-/*************************************************************************
- *  int board_early_init_f()
- *
- ************************************************************************/
-int board_early_init_f(void)
-{
-	u32 mfr;
-
-	mtebc( PB0AP,  0x03800000 );	/* set chip selects */
-	mtebc( PB0CR,  0xffc58000 );	/* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
-	mtebc( PB1AP,  0x03800000 );
-	mtebc( PB1CR,  0xff018000 );	/* ebc0_b1cr, 1MB at 0xff000000 CS1 */
-	mtebc( PB2AP,  0x03800000 );
-	mtebc( PB2CR,  0xff838000 );	/* ebc0_b2cr, 2MB at 0xff800000 CS2 */
-
-	mtdcr( UIC1SR, 0xffffffff );	/* Clear all interrupts */
-	mtdcr( UIC1ER, 0x00000000 );	/* disable all interrupts */
-	mtdcr( UIC1CR, 0x00000000 );	/* Set Critical / Non Critical interrupts */
-	mtdcr( UIC1PR, 0x7fff83ff );	/* Set Interrupt Polarities */
-	mtdcr( UIC1TR, 0x001f8000 );	/* Set Interrupt Trigger Levels */
-	mtdcr( UIC1VR, 0x00000001 );	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr( UIC1SR, 0x00000000 );	/* clear all interrupts */
-	mtdcr( UIC1SR, 0xffffffff );
-
-	mtdcr( UIC0SR, 0xffffffff );	/* Clear all interrupts */
-	mtdcr( UIC0ER, 0x00000000 );	/* disable all interrupts excepted cascade */
-	mtdcr( UIC0CR, 0x00000001 );	/* Set Critical / Non Critical interrupts */
-	mtdcr( UIC0PR, 0xffffffff );	/* Set Interrupt Polarities */
-	mtdcr( UIC0TR, 0x01000004 );	/* Set Interrupt Trigger Levels */
-	mtdcr( UIC0VR, 0x00000001 );	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr( UIC0SR, 0x00000000 );	/* clear all interrupts */
-	mtdcr( UIC0SR, 0xffffffff );
-
-	mfsdr(SDR0_MFR, mfr);
-	mfr |= SDR0_MFR_FIXD;		/* Workaround for PCI/DMA */
-	mtsdr(SDR0_MFR, mfr);
-
-	return  0;
-}
-
-
-/*************************************************************************
- *  int misc_init_r()
- *
- ************************************************************************/
-int misc_init_r(void)
-{
-	volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE;
-
-	/* set modes of operation */
-	x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
-		EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
-	/* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
-	x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
-
-	/* put Ethernet+PHY in reset */
-	x->ethuart &= ~EPLD2_RESET_ETH_N;
-	udelay(10000);
-	/* take Ethernet+PHY out of reset */
-	x->ethuart |= EPLD2_RESET_ETH_N;
-
-	return  0;
-}
-
-
-/*************************************************************************
- *  int checkboard()
- *
- ************************************************************************/
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf("Board: Luan - AMCC PPC440SP Evaluation Board");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return  0;
-}
-
-/*
- * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
- * board specific values.
- */
-u32 ddr_clktr(u32 default_val) {
-	return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
-}
-
-/*************************************************************************
- *  hw_watchdog_reset
- *
- *	This routine is called to reset (keep alive) the watchdog timer
- *
- ************************************************************************/
-#if defined(CONFIG_HW_WATCHDOG)
-void hw_watchdog_reset(void)
-{
-}
-#endif
-
-
-/*************************************************************************
- *  int on_off()
- *
- ************************************************************************/
-static int on_off( const char *s )
-{
-	if (strcmp(s, "on") == 0) {
-		return  1;
-	} else if (strcmp(s, "off") == 0) {
-		return  0;
-	}
-	return  -1;
-}
-
-
-/*************************************************************************
- *  void l2cache_disable()
- *
- ************************************************************************/
-static void l2cache_disable(void)
-{
-	mtdcr( L2_CACHE_CFG, 0 );
-}
-
-
-/*************************************************************************
- *  void l2cache_enable()
- *
- ************************************************************************/
-static void l2cache_enable(void)	/* see p258 7.4.1 Enabling L2 Cache */
-{
-	mtdcr( L2_CACHE_CFG, 0x80000000 );	/* enable L2_MODE L2_CFG[L2M] */
-
-	mtdcr( L2_CACHE_ADDR, 0 );		/* set L2_ADDR with all zeros */
-
-	mtdcr( L2_CACHE_CMD, 0x80000000 );	/* issue HCLEAR command via L2_CMD */
-
-	while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 ))  ;; /* poll L2_SR for completion */
-
-	mtdcr( L2_CACHE_CMD, 0x10000000 );	/* clear cache errors L2_CMD[CCP] */
-
-	mtdcr( L2_CACHE_CMD, 0x08000000 );	/* clear tag errors L2_CMD[CTE] */
-
-	mtdcr( L2_CACHE_SNP0, 0 );		/* snoop registers */
-	mtdcr( L2_CACHE_SNP1, 0 );
-
-	__asm__ volatile ("sync");		/* msync */
-
-	mtdcr( L2_CACHE_CFG, 0xe0000000 );	/* inst and data use L2 */
-
-	__asm__ volatile ("sync");
-}
-
-
-/*************************************************************************
- *  int l2cache_status()
- *
- ************************************************************************/
-static int l2cache_status(void)
-{
-	return  (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0;
-}
-
-
-/*************************************************************************
- *  int do_l2cache()
- *
- ************************************************************************/
-int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] )
-{
-	switch (argc) {
-	case 2:			/* on / off	*/
-		switch (on_off(argv[1])) {
-		case 0:	l2cache_disable();
-			break;
-		case 1:	l2cache_enable();
-			break;
-		}
-		/* FALL TROUGH */
-	case 1:			/* get status */
-		printf ("L2 Cache is %s\n",
-			l2cache_status() ? "ON" : "OFF");
-		return 0;
-	default:
-		return cmd_usage(cmdtp);
-	}
-
-	return  0;
-}
-
-
-U_BOOT_CMD(
-	l2cache,   2,   1,     do_l2cache,
-	"enable or disable L2 cache",
-	"[on, off]\n"
-	"    - enable or disable L2 cache"
-);
diff --git a/board/amcc/makalu/Kconfig b/board/amcc/makalu/Kconfig
deleted file mode 100644
index 7f8498a..0000000
--- a/board/amcc/makalu/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TARGET_MAKALU
-
-config SYS_BOARD
-	default "makalu"
-
-config SYS_VENDOR
-	default "amcc"
-
-config SYS_CONFIG_NAME
-	default "makalu"
-
-config DISPLAY_BOARDINFO
-	bool
-	default y
-
-endif
diff --git a/board/amcc/makalu/MAINTAINERS b/board/amcc/makalu/MAINTAINERS
deleted file mode 100644
index ecd5e19..0000000
--- a/board/amcc/makalu/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MAKALU BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/amcc/makalu/
-F:	include/configs/makalu.h
-F:	configs/makalu_defconfig
diff --git a/board/amcc/makalu/Makefile b/board/amcc/makalu/Makefile
deleted file mode 100644
index dcf162c..0000000
--- a/board/amcc/makalu/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= makalu.o cmd_pll.o
-obj-y	+= init.o
diff --git a/board/amcc/makalu/cmd_pll.c b/board/amcc/makalu/cmd_pll.c
deleted file mode 100644
index f12655b..0000000
--- a/board/amcc/makalu/cmd_pll.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * ehnus: change pll frequency.
- * Wed Sep  5 11:45:17 CST 2007
- * hsun@udtech.com.cn
- */
-
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <i2c.h>
-
-#ifdef CONFIG_CMD_EEPROM
-
-#define EEPROM_CONF_OFFSET		0
-#define EEPROM_TEST_OFFSET		16
-#define EEPROM_SDSTP_PARAM		16
-
-#define PLL_NAME_MAX			12
-#define BUF_STEP			8
-
-/* eeprom_wirtes 8Byte per op. */
-#define EEPROM_ALTER_FREQ(freq)						\
-	do {								\
-		int __i;						\
-		for (__i = 0; __i < 2; __i++)				\
-			eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR,		\
-				      EEPROM_CONF_OFFSET + __i*BUF_STEP, \
-				      pll_select[freq],			\
-				      BUF_STEP + __i*BUF_STEP);		\
-	} while (0)
-
-#define PDEBUG
-#ifdef	PDEBUG
-#define PLL_DEBUG	pll_debug(EEPROM_CONF_OFFSET)
-#else
-#define PLL_DEBUG
-#endif
-
-typedef enum {
-	PLL_ebc20,
-	PLL_333,
-	PLL_4001,
-	PLL_4002,
-	PLL_533,
-	PLL_600,
-	PLL_666,	/* For now, kilauea can't support */
-	RCONF,
-	WTEST,
-	PLL_TOTAL
-} pll_freq_t;
-
-static const char
-pll_name[][PLL_NAME_MAX] = {
-	"PLL_ebc20",
-	"PLL_333",
-	"PLL_400@1",
-	"PLL_400@2",
-	"PLL_533",
-	"PLL_600",
-	"PLL_666",
-	"RCONF",
-	"WTEST",
-	""
-};
-
-/*
- * ehnus:
- */
-static uchar
-pll_select[][EEPROM_SDSTP_PARAM] = {
-	/* 0: CPU 333MHz EBC 20MHz, for test only */
-	{
-		0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00,
-		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-	},
-
-	/* 0: 333 */
-	{
-		0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
-		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-	},
-
-	/* 1: 400_266 */
-	{
-		0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
-		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-	},
-
-	/* 2: 400 */
-	{
-		0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
-		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-	},
-
-	/* 3: 533 */
-	{
-		0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
-		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-	},
-
-	/* 4: 600 */
-	{
-		0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
-		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-	},
-
-	/* 5: 666 */
-	{
-		0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
-		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-	},
-
-	{}
-};
-
-static uchar
-testbuf[EEPROM_SDSTP_PARAM] = {
-	0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
-	0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
-};
-
-static void
-pll_debug(int off)
-{
-	int i;
-	uchar buffer[EEPROM_SDSTP_PARAM];
-
-	memset(buffer, 0, sizeof(buffer));
-	eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off,
-		    buffer, EEPROM_SDSTP_PARAM);
-
-	printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
-	for (i = 0; i < EEPROM_SDSTP_PARAM; i++)
-		printf("%02x ", buffer[i]);
-	printf("\n");
-}
-
-static void
-test_write(void)
-{
-	printf("Debug: test eeprom_write ... ");
-
-	/*
-	 * Write twice, 8 bytes per write
-	 */
-	eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
-		      testbuf, 8);
-	eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
-		      testbuf, 16);
-	printf("done\n");
-
-	pll_debug(EEPROM_TEST_OFFSET);
-}
-
-int
-do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	char c = '\0';
-	pll_freq_t pll_freq;
-
-	if (argc < 2)
-		return cmd_usage(cmdtp);
-
-	for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++) {
-		if (!strcmp(pll_name[pll_freq], argv[1]))
-			break;
-	}
-
-	switch (pll_freq) {
-	case PLL_ebc20:
-	case PLL_333:
-	case PLL_4001:
-	case PLL_4002:
-	case PLL_533:
-	case PLL_600:
-		EEPROM_ALTER_FREQ(pll_freq);
-		break;
-
-	case PLL_666:		/* not support */
-		printf("Choose this option will result in a boot failure."
-		       "\nContinue? (Y/N): ");
-
-		c = getc(); putc('\n');
-
-		if ((c == 'y') || (c == 'Y')) {
-			EEPROM_ALTER_FREQ(pll_freq);
-			break;
-		}
-		goto ret;
-
-	case RCONF:
-		pll_debug(EEPROM_CONF_OFFSET);
-		goto ret;
-	case WTEST:
-		printf("DEBUG: write test\n");
-		test_write();
-		goto ret;
-
-	default:
-		printf("Invalid options\n\n");
-		return cmd_usage(cmdtp);
-	}
-
-	printf("PLL set to %s, "
-	       "reset the board to take effect\n", pll_name[pll_freq]);
-
-	PLL_DEBUG;
-ret:
-	return 0;
-}
-
-U_BOOT_CMD(
-	pllalter, CONFIG_SYS_MAXARGS, 1,        do_pll_alter,
-	"change pll frequence",
-	"pllalter <selection>      - change pll frequence \n\n\
-	** New freq take effect after reset. ** \n\
-	----------------------------------------------\n\
-	PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\
-	\t	Same as PLL_333	\n\
-	\t	except          \n\
-	\t	EBC: 20 MHz     \n\
-	----------------------------------------------\n\
-	PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\
-	\t	VCO: 666 MHz  \n\
-	\t	CPU: 333 MHz  \n\
-	\t	PLB: 166 MHz  \n\
-	\t	OPB: 83 MHz   \n\
-	\t	DDR: 83 MHz   \n\
-	------------------------------------------------\n\
-	PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\
-	\t	VCO: 800 MHz  \n\
-	\t	CPU: 400 MHz  \n\
-	\t	PLB: 133 MHz  \n\
-	\t	OPB: 66  MHz  \n\
-	\t	DDR: 133 MHz  \n\
-	------------------------------------------------\n\
-	PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\
-	\t	VCO: 800 MHz  \n\
-	\t	CPU: 400 MHz  \n\
-	\t	PLB: 200 MHz  \n\
-	\t	OPB: 100 MHz  \n\
-	\t	DDR: 200 MHz  \n\
-	----------------------------------------------\n\
-	PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\
-	\t	VCO: 1066 MHz  \n\
-	\t	CPU: 533  MHz  \n\
-	\t	PLB: 177  MHz  \n\
-	\t	OPB: 88   MHz  \n\
-	\t	DDR: 177  MHz  \n\
-	----------------------------------------------\n\
-	PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\
-	\t	VCO: 1200 MHz  \n\
-	\t	CPU: 600  MHz  \n\
-	\t	PLB: 200  MHz  \n\
-	\t	OPB: 100  MHz  \n\
-	\t	DDR: 200  MHz  \n\
-	----------------------------------------------\n\
-	PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\
-	\t	VCO: 1333 MHz  \n\
-	\t	CPU: 666  MHz  \n\
-	\t	PLB: 166  MHz  \n\
-	\t	OPB: 83   MHz  \n\
-	\t	DDR: 166  MHz  \n\
-	-----------------------------------------------\n\
-	RCONF: Read current eeprom configuration.      \n\
-	-----------------------------------------------\n\
-	WTEST: Test EEPROM write with predefined values\n\
-	-----------------------------------------------"
-);
-
-#endif	/* CONFIG_CMD_EEPROM */
diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S
deleted file mode 100644
index e15c622..0000000
--- a/board/amcc/makalu/init.S
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2008 Nuovation System Designs, LLC
- *   Grant Erickson <gerickson@nuovations.com>
- *
- * (C) Copyright 2007-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Originally based on code provided from Senao and AMCC
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-	.globl  ext_bus_cntlr_init
-ext_bus_cntlr_init:
-	blr
diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c
deleted file mode 100644
index a6ad2a1..0000000
--- a/board/amcc/makalu/makalu.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc405.h>
-#include <libfdt.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/io.h>
-#include <fdt_support.h>
-#include <asm/errno.h>
-
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#include <asm/4xx_pcie.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/*
- * Board early initialization function
- */
-int board_early_init_f (void)
-{
-	u32 val;
-
-	/*--------------------------------------------------------------------+
-	 | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
-	 +--------------------------------------------------------------------+
-	+---------------------------------------------------------------------+
-	|Interrupt| Source                            | Pol.  | Sensi.| Crit. |
-	+---------+-----------------------------------+-------+-------+-------+
-	| IRQ 00  | UART0                             | High  | Level | Non   |
-	| IRQ 01  | UART1                             | High  | Level | Non   |
-	| IRQ 02  | IIC0                              | High  | Level | Non   |
-	| IRQ 03  | TBD                               | High  | Level | Non   |
-	| IRQ 04  | TBD                               | High  | Level | Non   |
-	| IRQ 05  | EBM                               | High  | Level | Non   |
-	| IRQ 06  | BGI                               | High  | Level | Non   |
-	| IRQ 07  | IIC1                              | Rising| Edge  | Non   |
-	| IRQ 08  | SPI                               | High  | Lvl/ed| Non   |
-	| IRQ 09  | External IRQ 0 - (PCI-Express)    | pgm H | Pgm   | Non   |
-	| IRQ 10  | MAL TX EOB                        | High  | Level | Non   |
-	| IRQ 11  | MAL RX EOB                        | High  | Level | Non   |
-	| IRQ 12  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
-	| IRQ 13  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
-	| IRQ 14  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
-	| IRQ 15  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
-	| IRQ 16  | PCIE0 AL                          | high  | Level | Non   |
-	| IRQ 17  | PCIE0 VPD access                  | rising| Edge  | Non   |
-	| IRQ 18  | PCIE0 hot reset request           | rising| Edge  | Non   |
-	| IRQ 19  | PCIE0 hot reset request           | faling| Edge  | Non   |
-	| IRQ 20  | PCIE0 TCR                         | High  | Level | Non   |
-	| IRQ 21  | PCIE0 MSI level0                  | High  | Level | Non   |
-	| IRQ 22  | PCIE0 MSI level1                  | High  | Level | Non   |
-	| IRQ 23  | Security EIP-94                   | High  | Level | Non   |
-	| IRQ 24  | EMAC0 interrupt                   | High  | Level | Non   |
-	| IRQ 25  | EMAC1 interrupt                   | High  | Level | Non   |
-	| IRQ 26  | PCIE0 MSI level2                  | High  | Level | Non   |
-	| IRQ 27  | External IRQ 4                    | pgm H | Pgm   | Non   |
-	| IRQ 28  | UIC2 Non-critical Int.            | High  | Level | Non   |
-	| IRQ 29  | UIC2 Critical Interrupt           | High  | Level | Crit. |
-	| IRQ 30  | UIC1 Non-critical Int.            | High  | Level | Non   |
-	| IRQ 31  | UIC1 Critical Interrupt           | High  | Level | Crit. |
-	|----------------------------------------------------------------------
-	| IRQ 32  | MAL Serr                          | High  | Level | Non   |
-	| IRQ 33  | MAL Txde                          | High  | Level | Non   |
-	| IRQ 34  | MAL Rxde                          | High  | Level | Non   |
-	| IRQ 35  | PCIE0 bus master VC0              |falling| Edge  | Non   |
-	| IRQ 36  | PCIE0 DCR Error                   | High  | Level | Non   |
-	| IRQ 37  | EBC                               | High  |Lvl Edg| Non   |
-	| IRQ 38  | NDFC                              | High  | Level | Non   |
-	| IRQ 39  | GPT Compare Timer 8               | Risin | Edge  | Non   |
-	| IRQ 40  | GPT Compare Timer 9               | Risin | Edge  | Non   |
-	| IRQ 41  | PCIE1 AL                          | high  | Level | Non   |
-	| IRQ 42  | PCIE1 VPD access                  | rising| edge  | Non   |
-	| IRQ 43  | PCIE1 hot reset request           | rising| Edge  | Non   |
-	| IRQ 44  | PCIE1 hot reset request           | faling| Edge  | Non   |
-	| IRQ 45  | PCIE1 TCR                         | High  | Level | Non   |
-	| IRQ 46  | PCIE1 bus master VC0              |falling| Edge  | Non   |
-	| IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
-	| IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
-	| IRQ 49  | Ext. IRQ 7                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 50  | Ext. IRQ 8 -                      |pgm (H)|pgm/Lvl| Non   |
-	| IRQ 51  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
-	| IRQ 52  | GPT Compare Timer 5               | high  | Edge  | Non   |
-	| IRQ 53  | GPT Compare Timer 6               | high  | Edge  | Non   |
-	| IRQ 54  | GPT Compare Timer 7               | high  | Edge  | Non   |
-	| IRQ 55  | Serial ROM                        | High  | Level | Non   |
-	| IRQ 56  | GPT Decrement Pulse               | High  | Level | Non   |
-	| IRQ 57  | Ext. IRQ 2                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 58  | Ext. IRQ 5                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 59  | Ext. IRQ 6                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 60  | EMAC0 Wake-up                     | High  | Level | Non   |
-	| IRQ 61  | Ext. IRQ 1                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 62  | EMAC1 Wake-up                     | High  | Level | Non   |
-	|----------------------------------------------------------------------
-	| IRQ 64  | PE0 AL                            | High  | Level | Non   |
-	| IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
-	| IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
-	| IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
-	| IRQ 68  | PE0 TCR                           | High  | Level | Non   |
-	| IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
-	| IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
-	| IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 72  | PE1 AL                            | High  | Level | Non   |
-	| IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
-	| IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
-	| IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
-	| IRQ 76  | PE1 TCR                           | High  | Level | Non   |
-	| IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
-	| IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
-	| IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 80  | PE2 AL                            | High  | Level | Non   |
-	| IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
-	| IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
-	| IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
-	| IRQ 84  | PE2 TCR                           | High  | Level | Non   |
-	| IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
-	| IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
-	| IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
-	| IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
-	| IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
-	|---------------------------------------------------------------------
-	+---------+-----------------------------------+-------+-------+------*/
-	/*--------------------------------------------------------------------+
-	 | Initialise UIC registers.  Clear all interrupts.  Disable all
-	 | interrupts.
-	 | Set critical interrupt values.  Set interrupt polarities.  Set
-	 | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
-	 | interrupts again.
-	 +-------------------------------------------------------------------*/
-
-	mtdcr (UIC2SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (UIC2ER, 0x00000000);	/* disable all interrupts */
-	mtdcr (UIC2CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (UIC2PR, 0xf7ffffff);	/* Set Interrupt Polarities */
-	mtdcr (UIC2TR, 0x01e1fff8);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC2VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (UIC2SR, 0x00000000);	/* clear all interrupts */
-	mtdcr (UIC2SR, 0xffffffff);	/* clear all interrupts */
-
-	mtdcr (UIC1SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (UIC1ER, 0x00000000);	/* disable all interrupts */
-	mtdcr (UIC1CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (UIC1PR, 0xfffac785);	/* Set Interrupt Polarities */
-	mtdcr (UIC1TR, 0x001d0040);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC1VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (UIC1SR, 0x00000000);	/* clear all interrupts */
-	mtdcr (UIC1SR, 0xffffffff);	/* clear all interrupts */
-
-	mtdcr (UIC0SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (UIC0ER, 0x0000000a);	/* Disable all interrupts */
-					/* Except cascade UIC0 and UIC1 */
-	mtdcr (UIC0CR, 0x00000000);	/* Set Critical / Non Critical interrupts */
-	mtdcr (UIC0PR, 0xffbfefef);	/* Set Interrupt Polarities */
-	mtdcr (UIC0TR, 0x00007000);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC0VR, 0x00000001);	/* Set Vect base=0,INT31 Highest priority */
-	mtdcr (UIC0SR, 0x00000000);	/* clear all interrupts */
-	mtdcr (UIC0SR, 0xffffffff);	/* clear all interrupts */
-
-	/*
-	 * Note: Some cores are still in reset when the chip starts, so
-	 * take them out of reset
-	 */
-	mtsdr(SDR0_SRST, 0);
-
-	/* Reset PCIe slots */
-	gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 0);
-	udelay(100);
-	gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 1);
-
-	/*
-	 * Configure PFC (Pin Function Control) registers
-	 * -> Enable USB
-	 */
-	val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
-	mtsdr(SDR0_PFC1, val);
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_ENV_IS_IN_FLASH
-	/* Monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      -CONFIG_SYS_MONITOR_LEN,
-		      0xffffffff,
-		      &flash_info[0]);
-#endif
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf("Board: Makalu - AMCC PPC405EX Evaluation Board");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return (0);
-}
diff --git a/board/amcc/redwood/Kconfig b/board/amcc/redwood/Kconfig
deleted file mode 100644
index fee6441..0000000
--- a/board/amcc/redwood/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TARGET_REDWOOD
-
-config SYS_BOARD
-	default "redwood"
-
-config SYS_VENDOR
-	default "amcc"
-
-config SYS_CONFIG_NAME
-	default "redwood"
-
-config DISPLAY_BOARDINFO
-	bool
-	default y
-
-endif
diff --git a/board/amcc/redwood/MAINTAINERS b/board/amcc/redwood/MAINTAINERS
deleted file mode 100644
index 756b301..0000000
--- a/board/amcc/redwood/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-REDWOOD BOARD
-M:	Feng Kan <fkan@amcc.com>
-S:	Maintained
-F:	board/amcc/redwood/
-F:	include/configs/redwood.h
-F:	configs/redwood_defconfig
diff --git a/board/amcc/redwood/Makefile b/board/amcc/redwood/Makefile
deleted file mode 100644
index 2bc632b..0000000
--- a/board/amcc/redwood/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2008
-# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= redwood.o
-extra-y	+= init.o
diff --git a/board/amcc/redwood/config.mk b/board/amcc/redwood/config.mk
deleted file mode 100644
index 42b3e5f..0000000
--- a/board/amcc/redwood/config.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# (C) Copyright 2008
-# Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-#
-# AMCC 460SX Reference Platform (redwood) board
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/amcc/redwood/init.S b/board/amcc/redwood/init.S
deleted file mode 100644
index fd05130..0000000
--- a/board/amcc/redwood/init.S
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * (C) Copyright 2008
- * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-
-	.section .bootpg,"ax"
-	.globl tlbtab
-tlbtab:
-	tlbtab_start
-
-	/*
-	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
-	 * speed up boot process. It is patched after relocation to enable SA_I
-	 */
-	tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
-
-	/*
-	 * TLB entries for SDRAM are not needed on this platform.
-	 * They are dynamically generated in the SPD DDR(2) detection
-	 * routine.
-	 */
-
-	/* Although 512 KB, map 256k at a time */
-	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
-	tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_RWX | SA_I)
-
-	tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
-
-	/*
-	 * Peripheral base
-	 */
-	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_RW | SA_IG)
-	tlbtab_end
diff --git a/board/amcc/redwood/redwood.c b/board/amcc/redwood/redwood.c
deleted file mode 100644
index 15c3884..0000000
--- a/board/amcc/redwood/redwood.c
+++ /dev/null
@@ -1,440 +0,0 @@
-/*
- * This is the main board level file for the Redwood AMCC board.
- *
- * (C) Copyright 2008
- * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include "redwood.h"
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <i2c.h>
-#include <asm/io.h>
-
-int compare_to_true(char *str);
-char *remove_l_w_space(char *in_str);
-char *remove_t_w_space(char *in_str);
-int get_console_port(void);
-
-static void early_init_EBC(void);
-static int bootdevice_selected(void);
-static void early_reinit_EBC(int);
-static void early_init_UIC(void);
-
-/*
- * Define Boot devices
- */
-#define BOOT_FROM_8BIT_SRAM			0x00
-#define BOOT_FROM_16BIT_SRAM			0x01
-#define BOOT_FROM_32BIT_SRAM			0x02
-#define BOOT_FROM_8BIT_NAND			0x03
-#define BOOT_FROM_16BIT_NOR			0x04
-#define BOOT_DEVICE_UNKNOWN			0xff
-
-/*
- * EBC Devices Characteristics
- *   Peripheral Bank Access Parameters       -   EBC_BxAP
- *   Peripheral Bank Configuration Register  -   EBC_BxCR
- */
-
-/*
- * 8 bit width SRAM
- * BU Value
- * BxAP : 0x03800000  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
- * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0000000000000
- * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0000000000000
- */
-#define EBC_BXAP_8BIT_SRAM					\
-	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(7)  |	\
-	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
-	EBC_BXAP_CSN_ENCODE(0)  | EBC_BXAP_OEN_ENCODE(0)  |	\
-	EBC_BXAP_WBN_ENCODE(0)  | EBC_BXAP_WBF_ENCODE(0)  |	\
-	EBC_BXAP_TH_ENCODE(0)   | EBC_BXAP_RE_DISABLED    |	\
-	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_WRITEONLY  |	\
-	EBC_BXAP_PEN_DISABLED
-
-#define EBC_BXAP_16BIT_SRAM	EBC_BXAP_8BIT_SRAM
-#define EBC_BXAP_32BIT_SRAM	EBC_BXAP_8BIT_SRAM
-
-/*
- * NAND flash
- * BU Value
- * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
- * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
- * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
-*/
-#define EBC_BXAP_NAND						\
-	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(7)  |	\
-	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
-	EBC_BXAP_CSN_ENCODE(0)  | EBC_BXAP_OEN_ENCODE(0)  |	\
-	EBC_BXAP_WBN_ENCODE(0)  | EBC_BXAP_WBF_ENCODE(0)  |	\
-	EBC_BXAP_TH_ENCODE(0)   | EBC_BXAP_RE_DISABLED    |	\
-	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_WRITEONLY  |	\
-	EBC_BXAP_PEN_DISABLED
-
-/*
- * NOR flash
- * BU Value
- * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
- * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
- * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
-*/
-#define EBC_BXAP_NOR						\
-	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(7)  |	\
-	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
-	EBC_BXAP_CSN_ENCODE(0)  | EBC_BXAP_OEN_ENCODE(0)  |	\
-	EBC_BXAP_WBN_ENCODE(0)  | EBC_BXAP_WBF_ENCODE(0)  |	\
-	EBC_BXAP_TH_ENCODE(0)   | EBC_BXAP_RE_DISABLED    |	\
-	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_WRITEONLY  |	\
-	EBC_BXAP_PEN_DISABLED
-
-/*
- * FPGA
- * BU value :
- * B1AP = 0x05895240  - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
- * B1CR = 0xe201a000  - BAS = e20 - 000 11 01 00000000000000
- */
-#define EBC_BXAP_FPGA						\
-	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(11) |	\
-	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
-	EBC_BXAP_CSN_ENCODE(10) | EBC_BXAP_OEN_ENCODE(1)  |	\
-	EBC_BXAP_WBN_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(1)  |	\
-	EBC_BXAP_TH_ENCODE(1)   | EBC_BXAP_RE_DISABLED    |	\
-	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_RW         |	\
-	EBC_BXAP_PEN_DISABLED
-
-#define EBC_BXCR_8BIT_SRAM_CS0						\
-	EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_1MB           |	\
-	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT
-
-#define EBC_BXCR_32BIT_SRAM_CS0						\
-	EBC_BXCR_BAS_ENCODE(0xFFC00000) | EBC_BXCR_BS_1MB           |	\
-	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_32BIT
-
-#define EBC_BXCR_NAND_CS0						\
-	EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB          |	\
-	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT
-
-#define EBC_BXCR_16BIT_SRAM_CS0						\
-	EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_2MB           |	\
-	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
-
-#define EBC_BXCR_NOR_CS0						\
-	EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB          |	\
-	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
-
-#define EBC_BXCR_NOR_CS1						\
-	EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB         |	\
-	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
-
-#define EBC_BXCR_NAND_CS1						\
-	EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB         |	\
-	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT
-
-#define EBC_BXCR_NAND_CS2						\
-	EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_128MB         |	\
-	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT
-
-#define EBC_BXCR_SRAM_CS2						\
-	EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_4MB           |	\
-	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_32BIT
-
-#define EBC_BXCR_LARGE_FLASH_CS2					\
-	EBC_BXCR_BAS_ENCODE(0xE7000000) | EBC_BXCR_BS_16MB          |	\
-	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
-
-#define EBC_BXCR_FPGA_CS3						\
-	EBC_BXCR_BAS_ENCODE(0xE2000000) | EBC_BXCR_BS_1MB           |	\
-	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT
-
-/*****************************************************************************
- * UBOOT initiated board specific function calls
- ****************************************************************************/
-
-int board_early_init_f(void)
-{
-	int computed_boot_device = BOOT_DEVICE_UNKNOWN;
-
-	/*
-	 * Initialise EBC
-	 */
-	early_init_EBC();
-
-	/*
-	 * Determine which boot device was selected
-	 */
-	computed_boot_device = bootdevice_selected();
-
-	/*
-	 * Reinit EBC based on selected boot device
-	 */
-	early_reinit_EBC(computed_boot_device);
-
-	/*
-	 * Setup for UIC on 460SX redwood board
-	 */
-	early_init_UIC();
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf("Board: Redwood - AMCC 460SX Reference Board");
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-static void early_init_EBC(void)
-{
-	/*
-	 * Initialize EBC CONFIG -
-	 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
-	 * default value :
-	 *      0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
-	 */
-	mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
-	      EBC_CFG_PTD_ENABLE |
-	      EBC_CFG_RTC_16PERCLK |
-	      EBC_CFG_ATC_PREVIOUS |
-	      EBC_CFG_DTC_PREVIOUS |
-	      EBC_CFG_CTC_PREVIOUS |
-	      EBC_CFG_OEO_PREVIOUS |
-	      EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_16);
-
-	/*
-	 * PART 1 : Initialize EBC Bank 3
-	 * ==============================
-	 * Bank1 is always associated to the EPLD.
-	 * It has to be initialized prior to other banks settings computation
-	 * since some board registers values may be needed to determine the
-	 * boot type
-	 */
-	mtebc(PB1AP, EBC_BXAP_FPGA);
-	mtebc(PB1CR, EBC_BXCR_FPGA_CS3);
-
-}
-
-static int bootdevice_selected(void)
-{
-	unsigned long sdr0_pinstp;
-	unsigned long bootstrap_settings;
-	int computed_boot_device = BOOT_DEVICE_UNKNOWN;
-
-	/*
-	 *  Determine which boot device was selected
-	 *  =================================================
-	 *
-	 *  Read Pin Strap Register in PPC460SX
-	 *  Result can either be :
-	 *   - Boot strap = boot from EBC 8bits     => Small Flash
-	 *   - Boot strap = boot from PCI
-	 *   - Boot strap = IIC
-	 *  In case of boot from IIC, read Serial Device Strap Register1
-	 *
-	 *  Result can either be :
-	 *   - Boot from EBC  - EBC Bus Width = 8bits    => Small Flash
-	 *   - Boot from EBC  - EBC Bus Width = 16bits   => Large Flash or SRAM
-	 *   - Boot from PCI
-	 */
-
-	/* Read Pin Strap Register in PPC460SX */
-	mfsdr(SDR0_PINSTP, sdr0_pinstp);
-	bootstrap_settings = sdr0_pinstp & SDR0_PSTRP0_BOOTSTRAP_MASK;
-
-	switch (bootstrap_settings) {
-	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
-		/*
-		 * Boot from SRAM, 8bit width
-		 */
-		computed_boot_device = BOOT_FROM_8BIT_SRAM;
-		break;
-	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
-		/*
-		 * Boot from SRAM, 32bit width
-		 */
-		computed_boot_device = BOOT_FROM_32BIT_SRAM;
-		break;
-	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
-		/*
-		 * Boot from NAND, 8bit width
-		 */
-		computed_boot_device = BOOT_FROM_8BIT_NAND;
-		break;
-	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
-		/*
-		 * Boot from SRAM, 16bit width
-		 * Boot setting in IIC EEPROM 0x50
-		 */
-		computed_boot_device = BOOT_FROM_16BIT_SRAM;
-		break;
-	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS5:
-		/*
-		 * Boot from NOR, 16bit width
-		 * Boot setting in IIC EEPROM 0x54
-		 */
-		computed_boot_device = BOOT_FROM_16BIT_NOR;
-		break;
-	default:
-		/* should not be */
-		computed_boot_device = BOOT_DEVICE_UNKNOWN;
-		break;
-	}
-
-	return computed_boot_device;
-}
-
-static void early_reinit_EBC(int computed_boot_device)
-{
-	/*
-	 *  Compute EBC settings depending on selected boot device
-	 *  ======================================================
-	 *
-	 * Resulting EBC init will be among following configurations :
-	 *
-	 *  - Boot from EBC 8bits => boot from Small Flash selected
-	 *            EBC-CS0     = Small Flash
-	 *            EBC-CS2     = Large Flash and SRAM
-	 *
-	 *  - Boot from EBC 16bits => boot from Large Flash or SRAM
-	 *            EBC-CS0     = Large Flash or SRAM
-	 *            EBC-CS2     = Small Flash
-	 *
-	 *  - Boot from PCI
-	 *            EBC-CS0     = not initialized to avoid address contention
-	 *            EBC-CS2     = same as boot from Small Flash selected
-	 */
-
-	unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
-	unsigned long ebc0_cs1_bxap_value = 0, ebc0_cs1_bxcr_value = 0;
-	unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
-
-	switch (computed_boot_device) {
-		/*-------------------------------------------------------------------*/
-	case BOOT_FROM_8BIT_SRAM:
-		/*-------------------------------------------------------------------*/
-		ebc0_cs0_bxap_value = EBC_BXAP_8BIT_SRAM;
-		ebc0_cs0_bxcr_value = EBC_BXCR_8BIT_SRAM_CS0;
-		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
-		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
-		ebc0_cs2_bxap_value = EBC_BXAP_NAND;
-		ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
-		break;
-
-		/*-------------------------------------------------------------------*/
-	case BOOT_FROM_16BIT_SRAM:
-		/*-------------------------------------------------------------------*/
-		ebc0_cs0_bxap_value = EBC_BXAP_16BIT_SRAM;
-		ebc0_cs0_bxcr_value = EBC_BXCR_16BIT_SRAM_CS0;
-		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
-		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
-		ebc0_cs2_bxap_value = EBC_BXAP_NAND;
-		ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
-		break;
-
-		/*-------------------------------------------------------------------*/
-	case BOOT_FROM_32BIT_SRAM:
-		/*-------------------------------------------------------------------*/
-		ebc0_cs0_bxap_value = EBC_BXAP_32BIT_SRAM;
-		ebc0_cs0_bxcr_value = EBC_BXCR_32BIT_SRAM_CS0;
-		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
-		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
-		ebc0_cs2_bxap_value = EBC_BXAP_NAND;
-		ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
-		break;
-
-		/*-------------------------------------------------------------------*/
-	case BOOT_FROM_16BIT_NOR:
-		/*-------------------------------------------------------------------*/
-		ebc0_cs0_bxap_value = EBC_BXAP_NOR;
-		ebc0_cs0_bxcr_value = EBC_BXCR_NOR_CS0;
-		ebc0_cs1_bxap_value = EBC_BXAP_NAND;
-		ebc0_cs1_bxcr_value = EBC_BXCR_NAND_CS1;
-		ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
-		ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
-		break;
-
-		/*-------------------------------------------------------------------*/
-	case BOOT_FROM_8BIT_NAND:
-		/*-------------------------------------------------------------------*/
-		ebc0_cs0_bxap_value = EBC_BXAP_NAND;
-		ebc0_cs0_bxcr_value = EBC_BXCR_NAND_CS0;
-		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
-		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
-		ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
-		ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
-		break;
-
-		/*-------------------------------------------------------------------*/
-	default:
-		/*-------------------------------------------------------------------*/
-		/* BOOT_DEVICE_UNKNOWN */
-		break;
-	}
-
-	mtebc(PB0AP, ebc0_cs0_bxap_value);
-	mtebc(PB0CR, ebc0_cs0_bxcr_value);
-	mtebc(PB1AP, ebc0_cs1_bxap_value);
-	mtebc(PB1CR, ebc0_cs1_bxcr_value);
-	mtebc(PB2AP, ebc0_cs2_bxap_value);
-	mtebc(PB2CR, ebc0_cs2_bxcr_value);
-}
-
-static void early_init_UIC(void)
-{
-	/*
-	 * Initialise UIC registers.  Clear all interrupts.  Disable all
-	 * interrupts.
-	 * Set critical interrupt values.  Set interrupt polarities.  Set
-	 * interrupt trigger levels.  Make bit 0 High  priority.  Clear all
-	 * interrupts again.
-	 */
-	mtdcr(UIC3SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr(UIC3ER, 0x00000000);	/* disable all interrupts */
-	mtdcr(UIC3CR, 0x00000000);	/* Set Critical / Non Critical
-					 * interrupts */
-	mtdcr(UIC3PR, 0xffffffff);	/* Set Interrupt Polarities */
-	mtdcr(UIC3TR, 0x001fffff);	/* Set Interrupt Trigger Levels */
-	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC3SR, 0xffffffff);	/* clear all  interrupts */
-
-	mtdcr(UIC2SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr(UIC2ER, 0x00000000);	/* disable all interrupts */
-	mtdcr(UIC2CR, 0x00000000);	/* Set Critical / Non Critical
-					 * interrupts */
-	mtdcr(UIC2PR, 0xebebebff);	/* Set Interrupt Polarities */
-	mtdcr(UIC2TR, 0x74747400);	/* Set Interrupt Trigger Levels */
-	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all interrupts */
-
-	mtdcr(UIC1SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr(UIC1ER, 0x00000000);	/* disable all interrupts */
-	mtdcr(UIC1CR, 0x00000000);	/* Set Critical / Non Critical
-					 * interrupts */
-	mtdcr(UIC1PR, 0xffffffff);	/* Set Interrupt Polarities */
-	mtdcr(UIC1TR, 0x001fc0ff);	/* Set Interrupt Trigger Levels */
-	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all interrupts */
-
-	mtdcr(UIC0SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all interrupts excepted
-					 * cascade to be checked */
-	mtdcr(UIC0CR, 0x00104001);	/* Set Critical / Non Critical
-					 * interrupts */
-	mtdcr(UIC0PR, 0xffffffff);	/* Set Interrupt Polarities */
-	mtdcr(UIC0TR, 0x000f003c);	/* Set Interrupt Trigger Levels */
-	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all interrupts */
-
-}
diff --git a/board/amcc/redwood/redwood.h b/board/amcc/redwood/redwood.h
deleted file mode 100644
index 9c36073..0000000
--- a/board/amcc/redwood/redwood.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * (C) Copyright 2008
- * Feng Kan, Applied Micro Circuit Corp., fkan@amcc.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __REDWOOD_H_
-#define __REDWOOD_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*----------------------------------------------------------------------------+
-| Defines
-+----------------------------------------------------------------------------*/
-/* Pin Straps Reg */
-#define SDR0_PSTRP0			0x0040
-#define SDR0_PSTRP0_BOOTSTRAP_MASK	0xE0000000	/* Strap Bits */
-
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0	0x00000000	/* Default strap settings 0 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1	0x20000000	/* Default strap settings 1 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2	0x40000000	/* Default strap settings 2 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3	0x60000000	/* Default strap settings 3 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4	0x80000000	/* Default strap settings 4 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5	0xA0000000	/* Default strap settings 5 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6	0xC0000000	/* Default strap settings 6 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7	0xE0000000	/* Default strap settings 7 */
-
-#ifdef __cplusplus
-}
-#endif
-#endif				/* __REDWOOD_H_ */
diff --git a/board/amcc/sequoia/Kconfig b/board/amcc/sequoia/Kconfig
deleted file mode 100644
index 6e6e408..0000000
--- a/board/amcc/sequoia/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TARGET_SEQUOIA
-
-config SYS_BOARD
-	default "sequoia"
-
-config SYS_VENDOR
-	default "amcc"
-
-config SYS_CONFIG_NAME
-	default "sequoia"
-
-config DISPLAY_BOARDINFO
-	bool
-	default y
-
-endif
diff --git a/board/amcc/sequoia/MAINTAINERS b/board/amcc/sequoia/MAINTAINERS
deleted file mode 100644
index 6c28a37..0000000
--- a/board/amcc/sequoia/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-SEQUOIA BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/amcc/sequoia/
-F:	include/configs/sequoia.h
-F:	configs/rainier_defconfig
-F:	configs/rainier_ramboot_defconfig
-F:	configs/sequoia_defconfig
-F:	configs/sequoia_ramboot_defconfig
diff --git a/board/amcc/sequoia/Makefile b/board/amcc/sequoia/Makefile
deleted file mode 100644
index b4ab5da..0000000
--- a/board/amcc/sequoia/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= sequoia.o sdram.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-extra-y	+= init.o
diff --git a/board/amcc/sequoia/chip_config.c b/board/amcc/sequoia/chip_config.c
deleted file mode 100644
index eef9316..0000000
--- a/board/amcc/sequoia/chip_config.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-struct ppc4xx_config ppc4xx_config_val[] = {
-	{
-		"333-133-nor", "NOR  CPU: 333 PLB: 133 OPB:  66 EBC:  66",
-		{
-			0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"333-166-nor", "NOR  CPU: 333 PLB: 166 OPB:  83 EBC:  55",
-		{
-			0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"333-166-nand", "NAND CPU: 333 PLB: 166 OPB:  83 EBC:  55",
-		{
-			0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xd0, 0x30,
-			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"400-133-nor", "NOR  CPU: 400 PLB: 133 OPB:  66 EBC:  66",
-		{
-			0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"400-160-nor", "NOR  CPU: 400 PLB: 160 OPB:  80 EBC:  53",
-		{
-			0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"416-166-nor", "NOR  CPU: 416 PLB: 166 OPB:  83 EBC:  55",
-		{
-			0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"416-166-nand", "NAND CPU: 416 PLB: 166 OPB:  83 EBC:  55",
-		{
-			0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xd0, 0x10,
-			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"500-166-nor", "NOR  CPU: 500 PLB: 166 OPB:  83 EBC:  55",
-		{
-			0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"500-166-nand", "NAND CPU: 500 PLB: 166 OPB:  83 EBC:  55",
-		{
-			0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xd0, 0x30,
-			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"533-133-nor", "NOR  CPU: 533 PLB: 133 OPB:  66 EBC:  66",
-		{
-			0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"667-133-nor", "NOR  CPU: 667 PLB: 133 OPB:  66 EBC:  66",
-		{
-			0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"667-166-nor", "NOR  CPU: 667 PLB: 166 OPB:  83 EBC:  55",
-		{
-			0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"667-166-nand", "NAND CPU: 667 PLB: 166 OPB:  83 EBC:  55",
-		{
-			0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x30,
-			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/amcc/sequoia/config.mk b/board/amcc/sequoia/config.mk
deleted file mode 100644
index 824e78f..0000000
--- a/board/amcc/sequoia/config.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# (C) Copyright 2002-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-#
-# AMCC 440EPx Reference Platform (Sequoia) board
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
deleted file mode 100644
index f876639..0000000
--- a/board/amcc/sequoia/init.S
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-
-/*
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- */
-    .section .bootpg,"ax"
-    .globl tlbtab
-
-tlbtab:
-	tlbtab_start
-
-	/* vxWorks needs this as first entry for the Machine Check interrupt */
-	tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
-
-	/*
-	 * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This
-	 * entry is already configured for SDRAM via the JTAG debugger and mustn't
-	 * be re-initialized by this RAM-booting U-Boot version.
-	 */
-#ifndef CONFIG_SYS_RAMBOOT
-	/* TLB-entry for DDR SDRAM (Up to 2GB) */
-#ifdef CONFIG_4xx_DCACHE
-	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_G)
-#else
-	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
-#endif
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/* TLB-entry for EBC */
-	tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_RWX | SA_IG )
-
-	/* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
-	 * speed up boot process. It is patched after relocation to enable SA_I
-	 */
-	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
-	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
-#endif
-
-	/* TLB-entry for PCI Memory */
-	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
-	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
-	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
-	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
-
-	/* TLB-entry for NAND */
-	tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
-
-	/* TLB-entry for Internal Registers & OCM */
-	tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_RWX | SA_I )
-
-	/*TLB-entry PCI registers*/
-	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG )
-
-	/* TLB-entry for peripherals */
-	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
-
-	/* TLB-entry PCI IO Space - from sr@denx.de */
-	tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
-
-	tlbtab_end
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
deleted file mode 100644
index 67640d7..0000000
--- a/board/amcc/sequoia/sdram.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * (C) Copyright 2006
- * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* define DEBUG for debug output */
-#undef DEBUG
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc440.h>
-
-/*-----------------------------------------------------------------------------+
- * Prototypes
- *-----------------------------------------------------------------------------*/
-extern int denali_wait_for_dlllock(void);
-extern void denali_core_search_data_eye(void);
-
-/*************************************************************************
- *
- * initdram -- 440EPx's DDR controller is a DENALI Core
- *
- ************************************************************************/
-phys_size_t initdram (int board_type)
-{
-#if !defined(CONFIG_SYS_RAMBOOT)
-	ulong speed = get_bus_freq(0);
-
-	mtsdram(DDR0_02, 0x00000000);
-
-	mtsdram(DDR0_00, 0x0000190A);
-	mtsdram(DDR0_01, 0x01000000);
-	mtsdram(DDR0_03, 0x02030602);
-	mtsdram(DDR0_04, 0x0A020200);
-	mtsdram(DDR0_05, 0x02020308);
-	mtsdram(DDR0_06, 0x0102C812);
-	mtsdram(DDR0_07, 0x000D0100);
-	mtsdram(DDR0_08, 0x02430001);
-	mtsdram(DDR0_09, 0x00011D5F);
-	mtsdram(DDR0_10, 0x00000100);
-	mtsdram(DDR0_11, 0x0027C800);
-	mtsdram(DDR0_12, 0x00000003);
-	mtsdram(DDR0_14, 0x00000000);
-	mtsdram(DDR0_17, 0x19000000);
-	mtsdram(DDR0_18, 0x19191919);
-	mtsdram(DDR0_19, 0x19191919);
-	mtsdram(DDR0_20, 0x0B0B0B0B);
-	mtsdram(DDR0_21, 0x0B0B0B0B);
-	mtsdram(DDR0_22, 0x00267F0B);
-	mtsdram(DDR0_23, 0x00000000);
-	mtsdram(DDR0_24, 0x01010002);
-	if (speed > 133333334)
-		mtsdram(DDR0_26, 0x5B26050C);
-	else
-		mtsdram(DDR0_26, 0x5B260408);
-	mtsdram(DDR0_27, 0x0000682B);
-	mtsdram(DDR0_28, 0x00000000);
-	mtsdram(DDR0_31, 0x00000000);
-	mtsdram(DDR0_42, 0x01000006);
-	mtsdram(DDR0_43, 0x030A0200);
-	mtsdram(DDR0_44, 0x00000003);
-	mtsdram(DDR0_02, 0x00000001);
-
-	denali_wait_for_dlllock();
-#endif /* #ifndef CONFIG_SYS_RAMBOOT */
-
-#ifdef CONFIG_DDR_DATA_EYE
-	/* -----------------------------------------------------------+
-	 * Perform data eye search if requested.
-	 * ----------------------------------------------------------*/
-	denali_core_search_data_eye();
-#endif
-
-	/*
-	 * Clear possible errors resulting from data-eye-search.
-	 * If not done, then we could get an interrupt later on when
-	 * exceptions are enabled.
-	 */
-	set_mcsr(get_mcsr());
-
-	return (CONFIG_SYS_MBYTES_SDRAM << 20);
-}
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
deleted file mode 100644
index 91c6cbf..0000000
--- a/board/amcc/sequoia/sequoia.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * (C) Copyright 2006-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/bitops.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if !defined(CONFIG_SYS_NO_FLASH)
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-#endif
-
-extern void __ft_board_setup(void *blob, bd_t *bd);
-ulong flash_get_size(ulong base, int banknum);
-
-static inline u32 get_async_pci_freq(void)
-{
-	if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
-		CONFIG_SYS_BCSR5_PCI66EN)
-		return 66666666;
-	else
-		return 33333333;
-}
-
-int board_early_init_f(void)
-{
-	u32 sdr0_cust0;
-	u32 sdr0_pfc1, sdr0_pfc2;
-	u32 reg;
-
-	mtdcr(EBC0_CFGADDR, EBC0_CFG);
-	mtdcr(EBC0_CFGDATA, 0xb8400000);
-
-	/*
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all */
-	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(UIC0PR, 0xfffff7ff);	/* per ref-board manual */
-	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC1ER, 0x00000000);	/* disable all */
-	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC2ER, 0x00000000);	/* disable all */
-	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-
-	/* Check and reconfigure the PCI sync clock if necessary */
-	ppc4xx_pci_sync_clock_config(get_async_pci_freq());
-
-	/* 50MHz tmrclk */
-	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
-
-	/* clear write protects */
-	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00);
-
-	/* enable Ethernet */
-	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00);
-
-	/* enable USB device */
-	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20);
-
-	/* select Ethernet (and optionally IIC1) pins */
-	mfsdr(SDR0_PFC1, sdr0_pfc1);
-	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
-		SDR0_PFC1_SELECT_CONFIG_4;
-#ifdef CONFIG_I2C_MULTI_BUS
-	sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
-#endif
-	/* Two UARTs, so we need 4-pin mode.  Also, we want CTS/RTS mode. */
-	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
-	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
-	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
-
-	mfsdr(SDR0_PFC2, sdr0_pfc2);
-	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
-		SDR0_PFC2_SELECT_CONFIG_4;
-	mtsdr(SDR0_PFC2, sdr0_pfc2);
-	mtsdr(SDR0_PFC1, sdr0_pfc1);
-
-	/* PCI arbiter enabled */
-	mfsdr(SDR0_PCI0, reg);
-	mtsdr(SDR0_PCI0, 0x80000000 | reg);
-
-	/* setup NAND FLASH */
-	mfsdr(SDR0_CUST0, sdr0_cust0);
-	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
-		SDR0_CUST0_NDFC_ENABLE		|
-		SDR0_CUST0_NDFC_BW_8_BIT	|
-		SDR0_CUST0_NDFC_ARE_MASK	|
-		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
-	mtsdr(SDR0_CUST0, sdr0_cust0);
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-#if !defined(CONFIG_SYS_NO_FLASH)
-	uint pbcr;
-	int size_val = 0;
-#endif
-#ifdef CONFIG_440EPX
-	unsigned long usb2d0cr = 0;
-	unsigned long usb2phy0cr, usb2h0cr = 0;
-	unsigned long sdr0_pfc1;
-	char *act = getenv("usbact");
-#endif
-	u32 reg;
-
-#if !defined(CONFIG_SYS_NO_FLASH)
-	/* Re-do flash sizing to get full correct info */
-
-	/* adjust flash start and offset */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-	gd->bd->bi_flashoffset = 0;
-
-#if defined(CONFIG_SYS_RAMBOOT)
-	mtdcr(EBC0_CFGADDR, PB3CR);
-#else
-	mtdcr(EBC0_CFGADDR, PB0CR);
-#endif
-	pbcr = mfdcr(EBC0_CFGDATA);
-	size_val = ffs(gd->bd->bi_flashsize) - 21;
-	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-#if defined(CONFIG_SYS_RAMBOOT)
-	mtdcr(EBC0_CFGADDR, PB3CR);
-#else
-	mtdcr(EBC0_CFGADDR, PB0CR);
-#endif
-	mtdcr(EBC0_CFGDATA, pbcr);
-
-	/*
-	 * Re-check to get correct base address
-	 */
-	flash_get_size(gd->bd->bi_flashstart, 0);
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-	/* Monitor protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CONFIG_SYS_MONITOR_LEN,
-			    0xffffffff,
-			    &flash_info[0]);
-
-	/* Env protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    CONFIG_ENV_ADDR_REDUND,
-			    CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
-			    &flash_info[0]);
-#endif
-#endif /* CONFIG_SYS_NO_FLASH */
-
-	/*
-	 * USB suff...
-	 */
-#ifdef CONFIG_440EPX
-	if (act == NULL || strcmp(act, "hostdev") == 0) {
-		/* SDR Setting */
-		mfsdr(SDR0_PFC1, sdr0_pfc1);
-		mfsdr(SDR0_USB2D0CR, usb2d0cr);
-		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-		mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
-
-		/*
-		 * An 8-bit/60MHz interface is the only possible alternative
-		 * when connecting the Device to the PHY
-		 */
-		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
-		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
-
-		/*
-		 * To enable the USB 2.0 Device function
-		 * through the UTMI interface
-		 */
-		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
-		usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
-
-		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
-		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
-
-		mtsdr(SDR0_PFC1, sdr0_pfc1);
-		mtsdr(SDR0_USB2D0CR, usb2d0cr);
-		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-		mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
-		/*clear resets*/
-		udelay (1000);
-		mtsdr(SDR0_SRST1, 0x00000000);
-		udelay (1000);
-		mtsdr(SDR0_SRST0, 0x00000000);
-
-		printf("USB:   Host(int phy) Device(ext phy)\n");
-
-	} else if (strcmp(act, "dev") == 0) {
-		/*-------------------PATCH-------------------------------*/
-		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
-		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-
-		udelay (1000);
-		mtsdr(SDR0_SRST1, 0x672c6000);
-
-		udelay (1000);
-		mtsdr(SDR0_SRST0, 0x00000080);
-
-		udelay (1000);
-		mtsdr(SDR0_SRST1, 0x60206000);
-
-		*(unsigned int *)(0xe0000350) = 0x00000001;
-
-		udelay (1000);
-		mtsdr(SDR0_SRST1, 0x60306000);
-		/*-------------------PATCH-------------------------------*/
-
-		/* SDR Setting */
-		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-		mfsdr(SDR0_USB2H0CR, usb2h0cr);
-		mfsdr(SDR0_USB2D0CR, usb2d0cr);
-		mfsdr(SDR0_PFC1, sdr0_pfc1);
-
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
-
-		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
-		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
-
-		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
-		usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
-
-		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
-		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
-
-		mtsdr(SDR0_USB2H0CR, usb2h0cr);
-		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-		mtsdr(SDR0_USB2D0CR, usb2d0cr);
-		mtsdr(SDR0_PFC1, sdr0_pfc1);
-
-		/* clear resets */
-		udelay (1000);
-		mtsdr(SDR0_SRST1, 0x00000000);
-		udelay (1000);
-		mtsdr(SDR0_SRST0, 0x00000000);
-
-		printf("USB:   Device(int phy)\n");
-	}
-#endif /* CONFIG_440EPX */
-
-	mfsdr(SDR0_SRST1, reg);		/* enable security/kasumi engines */
-	reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
-	mtsdr(SDR0_SRST1, reg);
-
-	/*
-	 * Clear PLB4A0_ACR[WRP]
-	 * This fix will make the MAL burst disabling patch for the Linux
-	 * EMAC driver obsolete.
-	 */
-	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
-	mtdcr(PLB4A0_ACR, reg);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-	u8 rev;
-	u32 clock = get_async_pci_freq();
-
-#ifdef CONFIG_440EPX
-	printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
-#else
-	printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
-#endif
-
-	rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
-	printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	/*
-	 * Reconfiguration of the PCI sync clock is already done,
-	 * now check again if everything is in range:
-	 */
-	if (ppc4xx_pci_sync_clock_config(clock)) {
-		printf("ERROR: PCI clocking incorrect (async=%d "
-		       "sync=%ld)!\n", clock, get_PCI_freq());
-	}
-
-	return (0);
-}
-
-#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
-/*
- * Assign interrupts to PCI devices.
- */
-void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
-	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
-}
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
-/*
- * On NAND-booting sequoia, we need to patch the chips select numbers
- * in the dtb (CS0 - NAND, CS3 - NOR)
- */
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	int rc;
-	int len;
-	int nodeoffset;
-	struct fdt_property *prop;
-	u32 *reg;
-	char path[32];
-
-	/* First do common fdt setup */
-	__ft_board_setup(blob, bd);
-
-	/* And now configure NOR chip select to 3 instead of 0 */
-	strcpy(path, "/plb/opb/ebc/nor_flash@0,0");
-	nodeoffset = fdt_path_offset(blob, path);
-	prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
-	if (prop == NULL) {
-		printf("Unable to update NOR chip select for NAND booting\n");
-		return -FDT_ERR_NOTFOUND;
-	}
-	reg = (u32 *)&prop->data[0];
-	reg[0] = 3;
-	rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
-	if (rc) {
-		printf("Unable to update property NOR mappings\n");
-		return rc;
-	}
-
-	/* And now configure NAND chip select to 0 instead of 3 */
-	strcpy(path, "/plb/opb/ebc/ndfc@3,0");
-	nodeoffset = fdt_path_offset(blob, path);
-	prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
-	if (prop == NULL) {
-		printf("Unable to update NDFC chip select for NAND booting\n");
-		return len;
-	}
-	reg = (u32 *)&prop->data[0];
-	reg[0] = 0;
-	rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
-	if (rc) {
-		printf("Unable to update property NDFC mapping\n");
-		return rc;
-	}
-
-	return 0;
-}
-#endif /* CONFIG_SYS_RAMBOOT */
diff --git a/board/amcc/sequoia/u-boot-ram.lds b/board/amcc/sequoia/u-boot-ram.lds
deleted file mode 100644
index ef08be8..0000000
--- a/board/amcc/sequoia/u-boot-ram.lds
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    arch/powerpc/cpu/ppc4xx/start.o	(.text*)
-    board/amcc/sequoia/init.o		(.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    KEEP(*(.got))
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/amcc/walnut/Kconfig b/board/amcc/walnut/Kconfig
deleted file mode 100644
index d4c451d..0000000
--- a/board/amcc/walnut/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TARGET_WALNUT
-
-config SYS_BOARD
-	default "walnut"
-
-config SYS_VENDOR
-	default "amcc"
-
-config SYS_CONFIG_NAME
-	default "walnut"
-
-config DISPLAY_BOARDINFO
-	bool
-	default y
-
-endif
diff --git a/board/amcc/walnut/MAINTAINERS b/board/amcc/walnut/MAINTAINERS
deleted file mode 100644
index 2a98c85..0000000
--- a/board/amcc/walnut/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-WALNUT BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/amcc/walnut/
-F:	include/configs/walnut.h
-F:	configs/sycamore_defconfig
-F:	configs/walnut_defconfig
diff --git a/board/amcc/walnut/Makefile b/board/amcc/walnut/Makefile
deleted file mode 100644
index 9228170..0000000
--- a/board/amcc/walnut/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= walnut.o flash.o
diff --git a/board/amcc/walnut/flash.c b/board/amcc/walnut/flash.c
deleted file mode 100644
index cc0f425..0000000
--- a/board/amcc/walnut/flash.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-#undef DEBUG
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif				/* DEBUG */
-
-/*
- * include common flash code (for amcc boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static void flash_get_offsets(ulong base, flash_info_t * info);
-
-unsigned long flash_init(void)
-{
-	unsigned long size_b0, size_b1;
-	int i;
-	uint pbcr;
-	unsigned long base_b0, base_b1;
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	size_b0 =
-	    flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-		       size_b0, size_b0 << 20);
-	}
-
-	/* Only one bank */
-	if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
-		/* Setup offsets */
-		flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
-
-		/* Monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET,
-				    CONFIG_SYS_MONITOR_BASE,
-				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
-				    &flash_info[0]);
-#ifdef CONFIG_ENV_IS_IN_FLASH
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
-				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[0]);
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
-				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[0]);
-#endif
-
-		size_b1 = 0;
-		flash_info[0].size = size_b0;
-	} else {
-		/* 2 banks */
-		size_b1 =
-		    flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
-				   &flash_info[1]);
-
-		/* Re-do sizing to get full correct info */
-
-		if (size_b1) {
-			mtdcr(EBC0_CFGADDR, PB0CR);
-			pbcr = mfdcr(EBC0_CFGDATA);
-			mtdcr(EBC0_CFGADDR, PB0CR);
-			base_b1 = -size_b1;
-			pbcr =
-			    (pbcr & 0x0001ffff) | base_b1 |
-			    (((size_b1 / 1024 / 1024) - 1) << 17);
-			mtdcr(EBC0_CFGDATA, pbcr);
-			/*          printf("PB1CR = %x\n", pbcr); */
-		}
-
-		if (size_b0) {
-			mtdcr(EBC0_CFGADDR, PB1CR);
-			pbcr = mfdcr(EBC0_CFGDATA);
-			mtdcr(EBC0_CFGADDR, PB1CR);
-			base_b0 = base_b1 - size_b0;
-			pbcr =
-			    (pbcr & 0x0001ffff) | base_b0 |
-			    (((size_b0 / 1024 / 1024) - 1) << 17);
-			mtdcr(EBC0_CFGDATA, pbcr);
-			/*            printf("PB0CR = %x\n", pbcr); */
-		}
-
-		size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
-
-		flash_get_offsets(base_b0, &flash_info[0]);
-
-		/* monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET,
-				    base_b0 + size_b0 - monitor_flash_len,
-				    base_b0 + size_b0 - 1, &flash_info[0]);
-
-		if (size_b1) {
-			/* Re-do sizing to get full correct info */
-			size_b1 =
-			    flash_get_size((vu_long *) base_b1, &flash_info[1]);
-
-			flash_get_offsets(base_b1, &flash_info[1]);
-
-			/* monitor protection ON by default */
-			(void)flash_protect(FLAG_PROTECT_SET,
-					    base_b1 + size_b1 -
-					    monitor_flash_len,
-					    base_b1 + size_b1 - 1,
-					    &flash_info[1]);
-			/* monitor protection OFF by default (one is enough) */
-			(void)flash_protect(FLAG_PROTECT_CLEAR,
-					    base_b0 + size_b0 -
-					    monitor_flash_len,
-					    base_b0 + size_b0 - 1,
-					    &flash_info[0]);
-		} else {
-			flash_info[1].flash_id = FLASH_UNKNOWN;
-			flash_info[1].sector_count = -1;
-		}
-
-		flash_info[0].size = size_b0;
-		flash_info[1].size = size_b1;
-	}			/* else 2 banks */
-	return (size_b0 + size_b1);
-}
-
-
-static void flash_get_offsets(ulong base, flash_info_t * info)
-{
-	int i;
-
-	/* set up sector start address table */
-	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    (info->flash_id == FLASH_AM040)) {
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00010000);
-	} else {
-		if (info->flash_id & FLASH_BTYPE) {
-			/* set sector offsets for bottom boot block type        */
-			info->start[0] = base + 0x00000000;
-			info->start[1] = base + 0x00004000;
-			info->start[2] = base + 0x00006000;
-			info->start[3] = base + 0x00008000;
-			for (i = 4; i < info->sector_count; i++) {
-				info->start[i] =
-				    base + (i * 0x00010000) - 0x00030000;
-			}
-		} else {
-			/* set sector offsets for top boot block type           */
-			i = info->sector_count - 1;
-			info->start[i--] = base + info->size - 0x00004000;
-			info->start[i--] = base + info->size - 0x00006000;
-			info->start[i--] = base + info->size - 0x00008000;
-			for (; i >= 0; i--) {
-				info->start[i] = base + i * 0x00010000;
-			}
-		}
-	}
-}
diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c
deleted file mode 100644
index c948209..0000000
--- a/board/amcc/walnut/walnut.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <spd_sdram.h>
-
-int board_early_init_f(void)
-{
-	/*-------------------------------------------------------------------------+
-	  | Interrupt controller setup for the Walnut/Sycamore board.
-	  | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
-	  |       IRQ 16    405GP internally generated; active low; level sensitive
-	  |       IRQ 17-24 RESERVED
-	  |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
-	  |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
-	  |       IRQ 27 (EXT IRQ 2) Not Used
-	  |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
-	  |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
-	  |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
-	  |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
-	  | Note for Walnut board:
-	  |       An interrupt taken for the FPGA (IRQ 25) indicates that either
-	  |       the Mouse, Keyboard, IRDA, or External Expansion caused the
-	  |       interrupt. The FPGA must be read to determine which device
-	  |       caused the interrupt. The default setting of the FPGA clears
-	  |
-	  +-------------------------------------------------------------------------*/
-
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
-	mtdcr(UIC0CR, 0x00000020);	/* set all but FPGA SMI to be non-critical */
-	mtdcr(UIC0PR, 0xFFFFFFE0);	/* set int polarities */
-	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
-	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-
-	/* set UART1 control to select CTS/RTS */
-#define FPGA_BRDC       0xF0300004
-	*(volatile char *)(FPGA_BRDC) |= 0x1;
-
-	return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-	uint pvr = get_pvr();
-
-	if (pvr == PVR_405GPR_RB) {
-		puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board");
-	} else {
-		puts("Board: Walnut - AMCC PPC405GP Evaluation Board");
-	}
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return (0);
-}
-
-/*
- * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
- * the necessary info for SDRAM controller configuration
- */
-phys_size_t initdram(int board_type)
-{
-	return spd_sdram();
-}
diff --git a/board/amcc/yosemite/Kconfig b/board/amcc/yosemite/Kconfig
deleted file mode 100644
index ec51236..0000000
--- a/board/amcc/yosemite/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TARGET_YOSEMITE
-
-config SYS_BOARD
-	default "yosemite"
-
-config SYS_VENDOR
-	default "amcc"
-
-config SYS_CONFIG_NAME
-	default "yosemite"
-
-config DISPLAY_BOARDINFO
-	bool
-	default y
-
-endif
diff --git a/board/amcc/yosemite/MAINTAINERS b/board/amcc/yosemite/MAINTAINERS
deleted file mode 100644
index 3f553e1..0000000
--- a/board/amcc/yosemite/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-YOSEMITE BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/amcc/yosemite/
-F:	include/configs/yosemite.h
-F:	configs/yellowstone_defconfig
-F:	configs/yosemite_defconfig
diff --git a/board/amcc/yosemite/Makefile b/board/amcc/yosemite/Makefile
deleted file mode 100644
index daf020a..0000000
--- a/board/amcc/yosemite/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= yosemite.o
-extra-y	+= init.o
diff --git a/board/amcc/yosemite/config.mk b/board/amcc/yosemite/config.mk
deleted file mode 100644
index f18b097..0000000
--- a/board/amcc/yosemite/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/amcc/yosemite/init.S b/board/amcc/yosemite/init.S
deleted file mode 100644
index 529cc65..0000000
--- a/board/amcc/yosemite/init.S
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0+
-*/
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-
-    .section .bootpg,"ax"
-    .globl tlbtab
-
-tlbtab:
-    tlbtab_start
-
-    /*
-     * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
-     * speed up boot process. It is patched after relocation to enable SA_I
-     */
-    tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/)
-
-    /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-    tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
-
-    tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
-    tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG )
-    tlbentry( CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I )
-
-    /* PCI */
-    tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG )
-    tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG )
-    tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG )
-    tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG )
-
-    /* USB 2.0 Device */
-    tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG )
-
-    tlbtab_end
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
deleted file mode 100644
index 56b5191..0000000
--- a/board/amcc/yosemite/yosemite.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <spd_sdram.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-static inline u32 get_async_pci_freq(void)
-{
-	if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
-		CONFIG_SYS_BCSR5_PCI66EN)
-		return 66666666;
-	else
-		return 33333333;
-}
-
-int board_early_init_f(void)
-{
-	register uint reg;
-
-	/*--------------------------------------------------------------------
-	 * Setup the external bus controller/chip selects
-	 *-------------------------------------------------------------------*/
-	mtdcr(EBC0_CFGADDR, EBC0_CFG);
-	reg = mfdcr(EBC0_CFGDATA);
-	mtdcr(EBC0_CFGDATA, reg | 0x04000000);	/* Set ATC */
-
-	/*--------------------------------------------------------------------
-	 * Setup the GPIO pins
-	 *-------------------------------------------------------------------*/
-	/*CPLD cs */
-	/*setup Address lines for flash size 64Meg. */
-	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
-	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
-	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
-
-	/*setup emac */
-	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
-	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
-	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
-	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
-	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
-
-	/*UART1 */
-	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
-	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
-	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
-
-	/* external interrupts IRQ0...3 */
-	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
-	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
-	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
-
-#ifdef CONFIG_440EP
-	/*setup USB 2.0 */
-	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
-	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
-	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
-	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
-	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
-#endif
-
-	/*--------------------------------------------------------------------
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 *-------------------------------------------------------------------*/
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all */
-	mtdcr(UIC0CR, 0x00000009);	/* ATI & UIC1 crit are critical */
-	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
-	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
-	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC1ER, 0x00000000);	/* disable all */
-	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
-	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-
-	/*--------------------------------------------------------------------
-	 * Setup other serial configuration
-	 *-------------------------------------------------------------------*/
-	mfsdr(SDR0_PCI0, reg);
-	mtsdr(SDR0_PCI0, 0x80000000 | reg);	/* PCI arbiter enabled */
-	mtsdr(SDR0_PFC0, 0x00003e00);	/* Pin function */
-	mtsdr(SDR0_PFC1, 0x00048000);	/* Pin function: UART0 has 4 pins */
-
-	/* Check and reconfigure the PCI sync clock if necessary */
-	ppc4xx_pci_sync_clock_config(get_async_pci_freq());
-
-	/*clear tmrclk divisor */
-	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;
-
-	/*enable ethernet */
-	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x08) = 0xf0;
-
-#ifdef CONFIG_440EP
-	/*enable usb 1.1 fs device and remove usb 2.0 reset */
-	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x09) = 0x00;
-#endif
-
-	/*get rid of flash write protect */
-	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x07) = 0x00;
-
-	return 0;
-}
-
-int misc_init_r (void)
-{
-	uint pbcr;
-	int size_val = 0;
-
-	/* Re-do sizing to get full correct info */
-	mtdcr(EBC0_CFGADDR, PB0CR);
-	pbcr = mfdcr(EBC0_CFGDATA);
-	switch (gd->bd->bi_flashsize) {
-	case 1 << 20:
-		size_val = 0;
-		break;
-	case 2 << 20:
-		size_val = 1;
-		break;
-	case 4 << 20:
-		size_val = 2;
-		break;
-	case 8 << 20:
-		size_val = 3;
-		break;
-	case 16 << 20:
-		size_val = 4;
-		break;
-	case 32 << 20:
-		size_val = 5;
-		break;
-	case 64 << 20:
-		size_val = 6;
-		break;
-	case 128 << 20:
-		size_val = 7;
-		break;
-	}
-	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-	mtdcr(EBC0_CFGADDR, PB0CR);
-	mtdcr(EBC0_CFGDATA, pbcr);
-
-	/* adjust flash start and offset */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-	gd->bd->bi_flashoffset = 0;
-
-	/* Monitor protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CONFIG_SYS_MONITOR_LEN,
-			    0xffffffff,
-			    &flash_info[0]);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-	u8 rev;
-	u32 clock = get_async_pci_freq();
-
-#ifdef CONFIG_440EP
-	printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
-#else
-	printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
-#endif
-
-	rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
-	printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	/*
-	 * Reconfiguration of the PCI sync clock is already done,
-	 * now check again if everything is in range:
-	 */
-	if (ppc4xx_pci_sync_clock_config(clock)) {
-		printf("ERROR: PCI clocking incorrect (async=%d "
-		       "sync=%ld)!\n", clock, get_PCI_freq());
-	}
-
-	return (0);
-}
-
-/*************************************************************************
- *  initdram -- doesn't use serial presence detect.
- *
- *  Assumes:    256 MB, ECC, non-registered
- *              PLB @ 133 MHz
- *
- ************************************************************************/
-#define NUM_TRIES 64
-#define NUM_READS 10
-
-void sdram_tr1_set(int ram_address, int* tr1_value)
-{
-	int i;
-	int j, k;
-	volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;
-	int first_good = -1, last_bad = 0x1ff;
-
-	unsigned long test[NUM_TRIES] = {
-		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
-		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
-		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
-		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
-		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
-		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
-		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
-		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
-		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
-		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
-		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
-		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
-		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
-		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
-		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
-		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
-
-	/* go through all possible SDRAM0_TR1[RDCT] values */
-	for (i=0; i<=0x1ff; i++) {
-		/* set the current value for TR1 */
-		mtsdram(SDRAM0_TR1, (0x80800800 | i));
-
-		/* write values */
-		for (j=0; j<NUM_TRIES; j++) {
-			ram_pointer[j] = test[j];
-
-			/* clear any cache at ram location */
-			__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
-		}
-
-		/* read values back */
-		for (j=0; j<NUM_TRIES; j++) {
-			for (k=0; k<NUM_READS; k++) {
-				/* clear any cache at ram location */
-				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
-
-				if (ram_pointer[j] != test[j])
-					break;
-			}
-
-			/* read error */
-			if (k != NUM_READS) {
-				break;
-			}
-		}
-
-		/* we have a SDRAM0_TR1[RDCT] that is part of the window */
-		if (j == NUM_TRIES) {
-			if (first_good == -1)
-				first_good = i;		/* found beginning of window */
-		} else { /* bad read */
-			/* if we have not had a good read then don't care */
-			if(first_good != -1) {
-				/* first failure after a good read */
-				last_bad = i-1;
-				break;
-			}
-		}
-	}
-
-	/* return the current value for TR1 */
-	*tr1_value = (first_good + last_bad) / 2;
-}
-
-phys_size_t initdram(int board)
-{
-	register uint reg;
-	int tr1_bank1, tr1_bank2;
-
-	/*--------------------------------------------------------------------
-	 * Setup some default
-	 *------------------------------------------------------------------*/
-	mtsdram(SDRAM0_UABBA, 0x00000000);	/* ubba=0 (default)             */
-	mtsdram(SDRAM0_SLIO, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */
-	mtsdram(SDRAM0_DEVOPT, 0x00000000);	/* dll=0 ds=0 (normal)          */
-	mtsdram(SDRAM0_CLKTR, 0x40000000);	/* ?? */
-	mtsdram(SDRAM0_WDDCTR, 0x40000000);	/* ?? */
-
-	/*clear this first, if the DDR is enabled by a debugger
-	  then you can not make changes. */
-	mtsdram(SDRAM0_CFG0, 0x00000000);	/* Disable EEC */
-
-	/*--------------------------------------------------------------------
-	 * Setup for board-specific specific mem
-	 *------------------------------------------------------------------*/
-	/*
-	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
-	 */
-	mtsdram(SDRAM0_B0CR, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
-	mtsdram(SDRAM0_B1CR, 0x080a4001);	/* SDBA=0x080 128MB, Mode 3, enabled */
-
-	mtsdram(SDRAM0_TR0, 0x410a4012);	/* ?? */
-	mtsdram(SDRAM0_RTR, 0x04080000);	/* ?? */
-	mtsdram(SDRAM0_CFG1, 0x00000000);	/* Self-refresh exit, disable PM    */
-	mtsdram(SDRAM0_CFG0, 0x30000000);	/* Disable EEC */
-	udelay(400);		/* Delay 200 usecs (min)            */
-
-	/*--------------------------------------------------------------------
-	 * Enable the controller, then wait for DCEN to complete
-	 *------------------------------------------------------------------*/
-	mtsdram(SDRAM0_CFG0, 0x80000000);	/* Enable */
-
-	for (;;) {
-		mfsdram(SDRAM0_MCSTS, reg);
-		if (reg & 0x80000000)
-			break;
-	}
-
-	sdram_tr1_set(0x00000000, &tr1_bank1);
-	sdram_tr1_set(0x08000000, &tr1_bank2);
-	mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
-
-	return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024);	/* return bytes */
-}
-
-/*************************************************************************
- *  hw_watchdog_reset
- *
- *	This routine is called to reset (keep alive) the watchdog timer
- *
- ************************************************************************/
-#if defined(CONFIG_HW_WATCHDOG)
-void hw_watchdog_reset(void)
-{
-
-}
-#endif
-
-void board_reset(void)
-{
-	/* give reset to BCSR */
-	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x06) = 0x09;
-}
diff --git a/board/amcc/yucca/Kconfig b/board/amcc/yucca/Kconfig
deleted file mode 100644
index 338b6a9..0000000
--- a/board/amcc/yucca/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TARGET_YUCCA
-
-config SYS_BOARD
-	default "yucca"
-
-config SYS_VENDOR
-	default "amcc"
-
-config SYS_CONFIG_NAME
-	default "yucca"
-
-config DISPLAY_BOARDINFO
-	bool
-	default y
-
-endif
diff --git a/board/amcc/yucca/MAINTAINERS b/board/amcc/yucca/MAINTAINERS
deleted file mode 100644
index 1cbdb0e..0000000
--- a/board/amcc/yucca/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-YUCCA BOARD
-#M:	-
-S:	Maintained
-F:	board/amcc/yucca/
-F:	include/configs/yucca.h
-F:	configs/yucca_defconfig
diff --git a/board/amcc/yucca/Makefile b/board/amcc/yucca/Makefile
deleted file mode 100644
index 5b1af32..0000000
--- a/board/amcc/yucca/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= yucca.o flash.o cmd_yucca.o
-extra-y	+= init.o
diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c
deleted file mode 100644
index cc78284..0000000
--- a/board/amcc/yucca/cmd_yucca.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * hacked for evb440spe
- */
-
-#include <common.h>
-#include <cli.h>
-#include <command.h>
-#include <console.h>
-#include "yucca.h"
-#include <i2c.h>
-#include <asm/byteorder.h>
-
-extern void print_evb440spe_info(void);
-static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag,
-		int flag, int argc, char * const argv[]);
-
-/* ------------------------------------------------------------------------- */
-int do_evb440spe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	return setBootStrapClock (cmdtp, 1, flag, argc, argv);
-}
-
-/* ------------------------------------------------------------------------- */
-/* Modify memory.
- *
- * Syntax:
- *	evb440spe wrclk prom0,prom1
- */
-static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
-		int argc, char * const argv[])
-{
-	uchar	chip;
-	ulong	data;
-	int	nbytes;
-
-	char sysClock[4];
-	char cpuClock[4];
-	char plbClock[4];
-	char pcixClock[4];
-
-	if (argc < 3)
-		return cmd_usage(cmdtp);
-
-	if (strcmp(argv[2], "prom0") == 0)
-		chip = IIC0_BOOTPROM_ADDR;
-	else
-		chip = IIC0_ALT_BOOTPROM_ADDR;
-
-	do {
-		printf("enter sys clock frequency 33 or 66 MHz or quit to abort\n");
-		nbytes = cli_readline(" ? ");
-
-		if (strcmp(console_buffer, "quit") == 0)
-			return 0;
-
-		if ((strcmp(console_buffer, "33") != 0) &
-				(strcmp(console_buffer, "66") != 0))
-			nbytes=0;
-
-		strcpy(sysClock, console_buffer);
-
-	} while (nbytes == 0);
-
-	do {
-		if (strcmp(sysClock, "66") == 0) {
-			printf("enter cpu clock frequency 400, 533 MHz or quit to abort\n");
-		} else {
-#ifdef	CONFIG_STRESS
-			printf("enter cpu clock frequency 400, 500, 533, 667 MHz or quit to abort\n");
-#else
-			printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n");
-#endif
-		}
-		nbytes = cli_readline(" ? ");
-
-		if (strcmp(console_buffer, "quit") == 0)
-			return 0;
-
-		if (strcmp(sysClock, "66") == 0) {
-			if ((strcmp(console_buffer, "400") != 0) &
-					(strcmp(console_buffer, "533") != 0)
-#ifdef	CONFIG_STRESS
-					& (strcmp(console_buffer, "667") != 0)
-#endif
-			   ) {
-				nbytes = 0;
-			}
-		} else {
-			if ((strcmp(console_buffer, "400") != 0) &
-					(strcmp(console_buffer, "500") != 0) &
-					(strcmp(console_buffer, "533") != 0)
-#ifdef	CONFIG_STRESS
-					& (strcmp(console_buffer, "667") != 0)
-#endif
-			   ) {
-				nbytes = 0;
-			}
-		}
-
-		strcpy(cpuClock, console_buffer);
-
-	} while (nbytes == 0);
-
-	if (strcmp(cpuClock, "500") == 0){
-		strcpy(plbClock, "166");
-	} else if (strcmp(cpuClock, "533") == 0){
-		strcpy(plbClock, "133");
-	} else {
-		do {
-			if (strcmp(cpuClock, "400") == 0)
-				printf("enter plb clock frequency 100, 133 MHz or quit to abort\n");
-
-#ifdef	CONFIG_STRESS
-			if (strcmp(cpuClock, "667") == 0)
-				printf("enter plb clock frequency 133, 166 MHz or quit to abort\n");
-
-#endif
-			nbytes = cli_readline(" ? ");
-
-			if (strcmp(console_buffer, "quit") == 0)
-				return 0;
-
-			if (strcmp(cpuClock, "400") == 0) {
-				if ((strcmp(console_buffer, "100") != 0) &
-						(strcmp(console_buffer, "133") != 0))
-					nbytes = 0;
-			}
-#ifdef	CONFIG_STRESS
-			if (strcmp(cpuClock, "667") == 0) {
-				if ((strcmp(console_buffer, "133") != 0) &
-						(strcmp(console_buffer, "166") != 0))
-					nbytes = 0;
-			}
-#endif
-			strcpy(plbClock, console_buffer);
-
-		} while (nbytes == 0);
-	}
-
-	do {
-		printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n");
-		nbytes = cli_readline(" ? ");
-
-		if (strcmp(console_buffer, "quit") == 0)
-			return 0;
-
-		if ((strcmp(console_buffer, "33") != 0) &
-				(strcmp(console_buffer, "66") != 0) &
-				(strcmp(console_buffer, "100") != 0) &
-				(strcmp(console_buffer, "133") != 0)) {
-			nbytes = 0;
-		}
-		strcpy(pcixClock, console_buffer);
-
-	} while (nbytes == 0);
-
-	printf("\nsys clk   = %s MHz\n", sysClock);
-	printf("cpu clk   = %s MHz\n", cpuClock);
-	printf("plb clk   = %s MHz\n", plbClock);
-	printf("Pci-X clk = %s MHz\n", pcixClock);
-
-	do {
-		printf("\npress [y] to write I2C bootstrap\n");
-		printf("or [n] to abort.\n");
-		printf("Don't forget to set board switches\n");
-		printf("according to your choice before re-starting\n");
-		printf("(refer to 440spe_uboot_kit_um_1_01.pdf)\n");
-
-		nbytes = cli_readline(" ? ");
-		if (strcmp(console_buffer, "n") == 0)
-			return 0;
-
-	} while (nbytes == 0);
-
-	if (strcmp(sysClock, "33") == 0) {
-		if ((strcmp(cpuClock, "400") == 0) &
-				(strcmp(plbClock, "100") == 0))
-			data = 0x8678c206;
-
-		if ((strcmp(cpuClock, "400") == 0) &
-				(strcmp(plbClock, "133") == 0))
-			data = 0x8678c2c6;
-
-		if ((strcmp(cpuClock, "500") == 0))
-			data = 0x8778f2c6;
-
-		if ((strcmp(cpuClock, "533") == 0))
-			data = 0x87790252;
-
-#ifdef	CONFIG_STRESS
-		if ((strcmp(cpuClock, "667") == 0) &
-				(strcmp(plbClock, "133") == 0))
-			data = 0x87794256;
-
-		if ((strcmp(cpuClock, "667") == 0) &
-				(strcmp(plbClock, "166") == 0))
-			data = 0x87794206;
-
-#endif
-	}
-	if (strcmp(sysClock, "66") == 0) {
-		if ((strcmp(cpuClock, "400") == 0) &
-				(strcmp(plbClock, "100") == 0))
-			data = 0x84706206;
-
-		if ((strcmp(cpuClock, "400") == 0) &
-				(strcmp(plbClock, "133") == 0))
-			data = 0x847062c6;
-
-		if ((strcmp(cpuClock, "533") == 0))
-			data = 0x85708206;
-
-#ifdef	CONFIG_STRESS
-		if ((strcmp(cpuClock, "667") == 0) &
-				(strcmp(plbClock, "133") == 0))
-			data = 0x8570a256;
-
-		if ((strcmp(cpuClock, "667") == 0) &
-				(strcmp(plbClock, "166") == 0))
-			data = 0x8570a206;
-
-#endif
-	}
-
-#ifdef	DEBUG
-	printf(" pin strap0 to write in i2c  = %x\n", data);
-#endif	/* DEBUG */
-
-	if (i2c_write(chip, 0, 1, (uchar *)&data, 4) != 0)
-		printf("Error writing strap0 in %s\n", argv[2]);
-
-	if (strcmp(pcixClock, "33") == 0)
-		data = 0x00000701;
-
-	if (strcmp(pcixClock, "66") == 0)
-		data = 0x00000601;
-
-	if (strcmp(pcixClock, "100") == 0)
-		data = 0x00000501;
-
-	if (strcmp(pcixClock, "133") == 0)
-		data = 0x00000401;
-
-	if (strcmp(plbClock, "166") == 0)
-		data = data | 0x05950000;
-	else
-		data = data | 0x05A50000;
-
-#ifdef	DEBUG
-	printf(" pin strap1 to write in i2c  = %x\n", data);
-#endif	/* DEBUG */
-
-	udelay(1000);
-	if (i2c_write(chip, 4, 1, (uchar *)&data, 4) != 0)
-		printf("Error writing strap1 in %s\n", argv[2]);
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	evb440spe,	3,	1,	do_evb440spe,
-	"program the serial device strap",
-	"wrclk [prom0|prom1] - program the serial device strap"
-);
diff --git a/board/amcc/yucca/config.mk b/board/amcc/yucca/config.mk
deleted file mode 100644
index 53d3f34..0000000
--- a/board/amcc/yucca/config.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-#
-# AMCC 440SPe Reference Platform (yucca) board
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c
deleted file mode 100644
index b1fd657..0000000
--- a/board/amcc/yucca/flash.c
+++ /dev/null
@@ -1,1033 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
- * Add support for Am29F016D and dynamic switch setting.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Modified 4/5/2001
- * Wait for completion of each sector erase command issued
- * 4/5/2001
- * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/ppc440.h>
-#include "yucca.h"
-
-#ifdef DEBUG
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif				/* DEBUG */
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
-
-/*
- * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
- */
-static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
-	{0xfff00000, 0xfff80000, 0xe7c00001}, /* 0:boot from small flash */
-	{0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66      */
-	{0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash  */
-	{0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
-	{0xe7F00000, 0xe7F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
-	{0x00000000, 0x00000000, 0x00000000}, /* 5:boot from             */
-	{0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66      */
-	{0x00000000, 0x00000000, 0x00000000}, /* 7:boot from             */
-	{0xfff00000, 0xfff80000, 0xe7c00001}, /* 8:boot from small flash */
-};
-
-/*
- * include common flash code (for amcc boards)
- */
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word(flash_info_t * info, ulong dest, ulong data);
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static int write_word_1(flash_info_t * info, ulong dest, ulong data);
-static int write_word_2(flash_info_t * info, ulong dest, ulong data);
-static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
-static int flash_erase_2(flash_info_t * info, int s_first, int s_last);
-static ulong flash_get_size_1(vu_long * addr, flash_info_t * info);
-static ulong flash_get_size_2(vu_long * addr, flash_info_t * info);
-#endif
-
-void flash_print_info(flash_info_t * info)
-{
-	int i;
-	int k;
-	int size;
-	int erased;
-	volatile unsigned long *flash;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-		case FLASH_MAN_AMD:
-			printf("AMD ");
-			break;
-		case FLASH_MAN_STM:
-			printf("STM ");
-			break;
-		case FLASH_MAN_FUJ:
-			printf("FUJITSU ");
-			break;
-		case FLASH_MAN_SST:
-			printf("SST ");
-			break;
-		case FLASH_MAN_MX:
-			printf("MIXC ");
-			break;
-		default:
-			printf("Unknown Vendor ");
-			break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-		case FLASH_AM040:
-			printf("AM29F040 (512 Kbit, uniform sector size)\n");
-			break;
-		case FLASH_AM400B:
-			printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
-			break;
-		case FLASH_AM400T:
-			printf("AM29LV400T (4 Mbit, top boot sector)\n");
-			break;
-		case FLASH_AM800B:
-			printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
-			break;
-		case FLASH_AM800T:
-			printf("AM29LV800T (8 Mbit, top boot sector)\n");
-			break;
-		case FLASH_AMD016:
-			printf("AM29F016D (16 Mbit, uniform sector size)\n");
-			break;
-		case FLASH_AM160B:
-			printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
-			break;
-		case FLASH_AM160T:
-			printf("AM29LV160T (16 Mbit, top boot sector)\n");
-			break;
-		case FLASH_AM320B:
-			printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
-			break;
-		case FLASH_AM320T:
-			printf("AM29LV320T (32 Mbit, top boot sector)\n");
-			break;
-		case FLASH_AM033C:
-			printf("AM29LV033C (32 Mbit, top boot sector)\n");
-			break;
-		case FLASH_SST800A:
-			printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
-			break;
-		case FLASH_SST160A:
-			printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
-			break;
-		case FLASH_STMW320DT:
-			printf ("M29W320DT (32 M, top sector)\n");
-			break;
-		case FLASH_MXLV320T:
-			printf ("MXLV320T (32 Mbit, top sector)\n");
-			break;
-		default:
-			printf("Unknown Chip Type\n");
-			break;
-	}
-
-	printf("  Size: %ld KB in %d Sectors\n",
-			info->size >> 10, info->sector_count);
-
-	printf("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		/*
-		 * Check if whole sector is erased
-		 */
-		if (i != (info->sector_count - 1))
-			size = info->start[i + 1] - info->start[i];
-		else
-			size = info->start[0] + info->size - info->start[i];
-		erased = 1;
-		flash = (volatile unsigned long *)info->start[i];
-		size = size >> 2;	/* divide by 4 for longword access */
-		for (k = 0; k < size; k++) {
-			if (*flash++ != 0xffffffff) {
-				erased = 0;
-				break;
-			}
-		}
-
-		if ((i % 5) == 0)
-			printf("\n   ");
-		printf(" %08lX%s%s",
-				info->start[i],
-				erased ? " E" : "  ",
-				info->protect[i] ? "RO " : "   ");
-	}
-	printf("\n");
-	return;
-}
-
-
-/*
- * The following code cannot be run from FLASH!
- */
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-{
-	/* bit 0 used for big flash marking */
-	if ((ulong)addr & 0x1)
-		return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info);
-	else
-		return flash_get_size_1(addr, info);
-}
-
-static ulong flash_get_size_1(vu_long * addr, flash_info_t * info)
-#else
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-#endif
-{
-	short i;
-	CONFIG_SYS_FLASH_WORD_SIZE value;
-	ulong base = (ulong) addr;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
-
-	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
-
-	/* Write auto select command: read Manufacturer ID */
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
-	udelay(1000);
-
-	value = addr2[0];
-	DEBUGF("FLASH MANUFACT: %x\n", value);
-
-	switch (value) {
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
-			info->flash_id = FLASH_MAN_AMD;
-			break;
-		case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
-			info->flash_id = FLASH_MAN_FUJ;
-			break;
-		case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
-			info->flash_id = FLASH_MAN_SST;
-			break;
-		case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
-			info->flash_id = FLASH_MAN_STM;
-			break;
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			info->sector_count = 0;
-			info->size = 0;
-			return (0);	/* no or unknown flash  */
-	}
-
-	value = addr2[1];	/* device ID            */
-	DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
-	switch (value) {
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B:
-			info->flash_id += FLASH_AM040;
-			info->sector_count = 8;
-			info->size = 0x0080000;	/* => 512 ko */
-			break;
-
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B:
-			info->flash_id += FLASH_AM040;
-			info->sector_count = 8;
-			info->size = 0x0080000;	/* => 512 ko */
-			break;
-
-		case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B:
-			info->flash_id += FLASH_AM040;
-			info->sector_count = 8;
-			info->size = 0x0080000;	/* => 512 ko */
-			break;
-
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D:
-			info->flash_id += FLASH_AMD016;
-			info->sector_count = 32;
-			info->size = 0x00200000;
-			break;		/* => 2 MB              */
-
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C:
-			info->flash_id += FLASH_AMDLV033C;
-			info->sector_count = 64;
-			info->size = 0x00400000;
-			break;		/* => 4 MB              */
-
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T:
-			info->flash_id += FLASH_AM400T;
-			info->sector_count = 11;
-			info->size = 0x00080000;
-			break;		/* => 0.5 MB            */
-
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B:
-			info->flash_id += FLASH_AM400B;
-			info->sector_count = 11;
-			info->size = 0x00080000;
-			break;		/* => 0.5 MB            */
-
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T:
-			info->flash_id += FLASH_AM800T;
-			info->sector_count = 19;
-			info->size = 0x00100000;
-			break;		/* => 1 MB              */
-
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B:
-			info->flash_id += FLASH_AM800B;
-			info->sector_count = 19;
-			info->size = 0x00100000;
-			break;		/* => 1 MB              */
-
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T:
-			info->flash_id += FLASH_AM160T;
-			info->sector_count = 35;
-			info->size = 0x00200000;
-			break;		/* => 2 MB              */
-
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B:
-			info->flash_id += FLASH_AM160B;
-			info->sector_count = 35;
-			info->size = 0x00200000;
-			break;		/* => 2 MB              */
-
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			return (0);	/* => no or unknown flash */
-	}
-
-	/* set up sector start address table */
-	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-			((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
-			((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00010000);
-	} else {
-		if (info->flash_id & FLASH_BTYPE) {
-			/* set sector offsets for bottom boot block type        */
-			info->start[0] = base + 0x00000000;
-			info->start[1] = base + 0x00004000;
-			info->start[2] = base + 0x00006000;
-			info->start[3] = base + 0x00008000;
-			for (i = 4; i < info->sector_count; i++) {
-				info->start[i] =
-					base + (i * 0x00010000) - 0x00030000;
-			}
-		} else {
-			/* set sector offsets for top boot block type           */
-			i = info->sector_count - 1;
-			info->start[i--] = base + info->size - 0x00004000;
-			info->start[i--] = base + info->size - 0x00006000;
-			info->start[i--] = base + info->size - 0x00008000;
-			for (; i >= 0; i--) {
-				info->start[i] = base + i * 0x00010000;
-			}
-		}
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
-
-		/* For AMD29033C flash we need to resend the command of *
-		 * reading flash protection for upper 8 Mb of flash     */
-		if (i == 32) {
-			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
-			addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
-			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
-		}
-
-		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
-			info->protect[i] = 0;
-		else
-			info->protect[i] = addr2[2] & 1;
-	}
-
-	/* issue bank reset to return to read mode */
-	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
-
-	return (info->size);
-}
-
-static int wait_for_DQ7_1(flash_info_t * info, int sect)
-{
-	ulong start, now, last;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
-		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-	start = get_timer(0);
-	last = start;
-	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
-			(CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf("Timeout\n");
-			return -1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc('.');
-			last = now;
-		}
-	}
-	return 0;
-}
-
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
-	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
-			((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
-			((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
-			((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
-		return flash_erase_2(info, s_first, s_last);
-	} else {
-		return flash_erase_1(info, s_first, s_last);
-	}
-}
-
-static int flash_erase_1(flash_info_t * info, int s_first, int s_last)
-#else
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-#endif
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
-	int flag, prot, sect;
-	int i;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN)
-			printf("- missing\n");
-		else
-			printf("- no sectors to erase\n");
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect])
-			prot++;
-	}
-
-	if (prot)
-		printf("- Warning: %d protected sectors will not be erased!", prot);
-
-	printf("\n");
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
-				for (i = 0; i < 50; i++)
-					udelay(1000);	/* wait 1 ms */
-			} else {
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
-			}
-			/*
-			 * Wait for each sector to complete, it's more
-			 * reliable.  According to AMD Spec, you must
-			 * issue all erase commands within a specified
-			 * timeout.  This has been seen to fail, especially
-			 * if printf()s are included (for debug)!!
-			 */
-			wait_for_DQ7_1(info, sect);
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay(1000);
-
-	/* reset to read mode */
-	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
-
-	printf(" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp)
-			data = (data << 8) | (*(uchar *) cp);
-
-		for (; i < 4 && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-
-		for (; cnt == 0 && i < 4; ++i, ++cp)
-			data = (data << 8) | (*(uchar *) cp);
-
-		if ((rc = write_word(info, wp, data)) != 0)
-			return (rc);
-
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i = 0; i < 4; ++i)
-			data = (data << 8) | *src++;
-
-		if ((rc = write_word(info, wp, data)) != 0)
-			return (rc);
-
-		wp += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0)
-		return (0);
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < 4; ++i, ++cp)
-		data = (data << 8) | (*(uchar *) cp);
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static int write_word(flash_info_t * info, ulong dest, ulong data)
-{
-	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
-			((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
-			((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) ||
-			((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) {
-		return write_word_2(info, dest, data);
-	} else {
-		return write_word_1(info, dest, data);
-	}
-}
-
-static int write_word_1(flash_info_t * info, ulong dest, ulong data)
-#else
-static int write_word(flash_info_t * info, ulong dest, ulong data)
-#endif
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
-	ulong start;
-	int i, flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data)
-		return (2);
-
-	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
-
-		dest2[i] = data2[i];
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		/* data polling for D7 */
-		start = get_timer(0);
-		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
-				(data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
-
-			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
-				return (1);
-		}
-	}
-
-	return (0);
-}
-
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-
-#undef  CONFIG_SYS_FLASH_WORD_SIZE
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
-{
-	short i;
-	int n;
-	CONFIG_SYS_FLASH_WORD_SIZE value;
-	ulong base = (ulong) addr;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
-
-	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
-
-	/* issue bank reset to return to read mode */
-	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
-	/* Write auto select command: read Manufacturer ID */
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
-	udelay(1000);
-
-	value = addr2[0];
-	DEBUGF("FLASH MANUFACT: %x\n", value);
-
-	switch (value) {
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
-			info->flash_id = FLASH_MAN_AMD;
-			break;
-		case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
-			info->flash_id = FLASH_MAN_FUJ;
-			break;
-		case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
-			info->flash_id = FLASH_MAN_SST;
-			break;
-		case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
-			info->flash_id = FLASH_MAN_STM;
-			break;
-		case (CONFIG_SYS_FLASH_WORD_SIZE) MX_MANUFACT:
-			info->flash_id = FLASH_MAN_MX;
-			break;
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			info->sector_count = 0;
-			info->size = 0;
-			return (0);	/* no or unknown flash  */
-	}
-
-	value = addr2[1];	/* device ID            */
-	DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
-	switch (value) {
-		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
-			info->flash_id += FLASH_AM320T;
-			info->sector_count = 71;
-			info->size = 0x00400000;
-			break;	/* => 4 MB	*/
-		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
-			info->flash_id += FLASH_AM320B;
-			info->sector_count = 71;
-			info->size = 0x00400000;
-			break;	/* => 4 MB	*/
-		case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT:
-			info->flash_id += FLASH_STMW320DT;
-			info->sector_count = 67;
-			info->size = 0x00400000;
-			break;	/* => 4 MB	*/
-		case (CONFIG_SYS_FLASH_WORD_SIZE)MX_ID_LV320T:
-			info->flash_id += FLASH_MXLV320T;
-			info->sector_count = 71;
-			info->size = 0x00400000;
-			break;	/* => 4 MB	*/
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			return (0);	/* => no or unknown flash */
-	}
-
-	/* set up sector start address table */
-	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-			((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) ||
-			((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) {
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00010000);
-	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
-		/* set sector offsets for top boot block type		*/
-		base += info->size;
-		i = info->sector_count;
-		/*  1 x 16k boot sector */
-		base -= 16 << 10;
-		--i;
-		info->start[i] = base;
-		/*  2 x 8k  boot sectors */
-		for (n = 0; n < 2; ++n) {
-			base -= 8 << 10;
-			--i;
-			info->start[i] = base;
-		}
-		/*  1 x 32k boot sector */
-		base -= 32 << 10;
-		--i;
-		info->start[i] = base;
-
-		while (i > 0) {			/* 64k regular sectors	*/
-			base -= 64 << 10;
-			--i;
-			info->start[i] = base;
-		}
-	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) {
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00002000;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000a000;
-		info->start[i--] = base + info->size - 0x0000c000;
-		info->start[i--] = base + info->size - 0x0000e000;
-		info->start[i--] = base + info->size - 0x00010000;
-
-		for (; i >= 0; i--)
-			info->start[i] = base + i * 0x00010000;
-	} else {
-		if (info->flash_id & FLASH_BTYPE) {
-			/* set sector offsets for bottom boot block type        */
-			info->start[0] = base + 0x00000000;
-			info->start[1] = base + 0x00004000;
-			info->start[2] = base + 0x00006000;
-			info->start[3] = base + 0x00008000;
-
-			for (i = 4; i < info->sector_count; i++)
-				info->start[i] = base + (i * 0x00010000) - 0x00030000;
-		} else {
-			/* set sector offsets for top boot block type           */
-			i = info->sector_count - 1;
-			info->start[i--] = base + info->size - 0x00004000;
-			info->start[i--] = base + info->size - 0x00006000;
-			info->start[i--] = base + info->size - 0x00008000;
-
-			for (; i >= 0; i--)
-				info->start[i] = base + i * 0x00010000;
-		}
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
-
-		/* For AMD29033C flash we need to resend the command of *
-		 * reading flash protection for upper 8 Mb of flash     */
-		if (i == 32) {
-			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
-			addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
-			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
-		}
-
-		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
-			info->protect[i] = 0;
-		else
-			info->protect[i] = addr2[2] & 1;
-	}
-
-	/* issue bank reset to return to read mode */
-	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
-
-	return (info->size);
-}
-
-static int wait_for_DQ7_2(flash_info_t * info, int sect)
-{
-	ulong start, now, last;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
-		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-	start = get_timer(0);
-	last = start;
-	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
-			(CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf("Timeout\n");
-			return -1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc('.');
-			last = now;
-		}
-	}
-	return 0;
-}
-
-static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
-	int flag, prot, sect;
-	int i;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN)
-			printf("- missing\n");
-		else
-			printf("- no sectors to erase\n");
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect])
-			prot++;
-	}
-
-	if (prot)
-		printf("- Warning: %d protected sectors will not be erased!",	prot);
-
-	printf("\n");
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
-				for (i = 0; i < 50; i++)
-					udelay(1000);	/* wait 1 ms */
-			} else {
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
-				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
-			}
-			/*
-			 * Wait for each sector to complete, it's more
-			 * reliable.  According to AMD Spec, you must
-			 * issue all erase commands within a specified
-			 * timeout.  This has been seen to fail, especially
-			 * if printf()s are included (for debug)!!
-			 */
-			wait_for_DQ7_2(info, sect);
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay(1000);
-
-	/* reset to read mode */
-	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
-
-	printf(" done\n");
-	return 0;
-}
-
-static int write_word_2(flash_info_t * info, ulong dest, ulong data)
-{
-	ulong *data_ptr = &data;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
-	ulong start;
-	int i;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data)
-		return (2);
-
-	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
-		int flag;
-
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
-
-		dest2[i] = data2[i];
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		/* data polling for D7 */
-		start = get_timer(0);
-		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
-				(data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
-
-			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
-				return (1);
-		}
-	}
-
-	return (0);
-}
-#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static int write_word(flash_info_t * info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
-	unsigned long total_b = 0;
-	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
-	unsigned short index = 0;
-	int i;
-	unsigned long val;
-	unsigned long ebc_boot_size;
-	unsigned long boot_selection;
-
-	mfsdr(sdr_pstrp0, val);
-	index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 28;
-
-	if ((index == 0xc) || (index == 8)) {
-		/*
-		 * Boot Settings in IIC EEprom address 0xA8 or 0xA0
-		 * Read Serial Device Strap Register1 in PPC440SPe
-		 */
-		mfsdr(SDR0_SDSTP1, val);
-		boot_selection  = val & SDR0_SDSTP1_BOOT_SEL_MASK;
-		ebc_boot_size   = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
-
-		switch(boot_selection) {
-			case SDR0_SDSTP1_BOOT_SEL_EBC:
-				switch(ebc_boot_size) {
-					case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
-						index = 3;
-						break;
-					case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
-						index = 0;
-						break;
-				}
-				break;
-
-			case SDR0_SDSTP1_BOOT_SEL_PCI:
-				index = 1;
-				break;
-
-		}
-	} /*else if (index == 0) {*/
-/*		if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE)*/
-/*			index = 8;*/ /* sram below op code flash -> new index 8*/
-/*	}*/
-
-	DEBUGF("\n");
-	DEBUGF("FLASH: Index: %d\n", index);
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-		flash_info[i].sector_count = -1;
-		flash_info[i].size = 0;
-
-		/* check whether the address is 0 */
-		if (flash_addr_table[index][i] == 0)
-			continue;
-
-		/* call flash_get_size() to initialize sector address */
-		size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
-				&flash_info[i]);
-
-		flash_info[i].size = size_b[i];
-
-		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
-					i, size_b[i], size_b[i] << 20);
-			flash_info[i].sector_count = -1;
-			flash_info[i].size = 0;
-		}
-
-		/* Monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
-				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
-				    &flash_info[i]);
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
-				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[i]);
-#if defined(CONFIG_ENV_ADDR_REDUND)
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
-				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[i]);
-#endif
-#endif
-		total_b += flash_info[i].size;
-	}
-
-	return total_b;
-}
diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S
deleted file mode 100644
index 7da5c0d..0000000
--- a/board/amcc/yucca/init.S
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-
-	.section .bootpg,"ax"
-
-/**************************************************************************
- * TLB table for revA
- *************************************************************************/
-	.globl tlbtabA
-tlbtabA:
-	tlbtab_start
-
-	/*
-	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
-	 * speed up boot process. It is patched after relocation to enable SA_I
-	 */
-	tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
-
-	/*
-	 * TLB entries for SDRAM are not needed on this platform.
-	 * They are dynamically generated in the SPD DDR(2) detection
-	 * routine.
-	 */
-
-	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
-	tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
-
-	tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
-	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
-	tlbtab_end
-
-/**************************************************************************
- * TLB table for revB
- *
- * Notice: revB of the 440SPe chip is very strict about PLB real addresses
- * and ranges to be mapped for config space: it seems to only work with
- * d_nnnn_nnnn range (hangs the core upon config transaction attempts when
- * set otherwise) while revA uses c_nnnn_nnnn.
- *************************************************************************/
-	.globl tlbtabB
-tlbtabB:
-	tlbtab_start
-
-	/*
-	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
-	 * speed up boot process. It is patched after relocation to enable SA_I
-	 */
-	tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
-
-	/*
-	 * TLB entries for SDRAM are not needed on this platform.
-	 * They are dynamically generated in the SPD DDR(2) detection
-	 * routine.
-	 */
-
-	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
-	tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
-
-	tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
-	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
-	tlbtab_end
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
deleted file mode 100644
index c0445ef..0000000
--- a/board/amcc/yucca/yucca.c
+++ /dev/null
@@ -1,714 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Port to AMCC-440SPE Evaluation Board SOP - April 2005
- *
- * PCIe supporting routines derived from Linux 440SPe PCIe driver.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <i2c.h>
-#include <netdev.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/4xx_pcie.h>
-#include <asm/errno.h>
-
-#include "yucca.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void fpga_init (void);
-
-#define DEBUG_ENV
-#ifdef DEBUG_ENV
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-
-int board_early_init_f (void)
-{
-/*----------------------------------------------------------------------------+
-| Define Boot devices
-+----------------------------------------------------------------------------*/
-#define BOOT_FROM_SMALL_FLASH		0x00
-#define BOOT_FROM_LARGE_FLASH_OR_SRAM	0x01
-#define BOOT_FROM_PCI			0x02
-#define BOOT_DEVICE_UNKNOWN		0x03
-
-/*----------------------------------------------------------------------------+
-| EBC Devices Characteristics
-|   Peripheral Bank Access Parameters       -   EBC_BxAP
-|   Peripheral Bank Configuration Register  -   EBC_BxCR
-+----------------------------------------------------------------------------*/
-
-/*
- * Small Flash and FRAM
- * BU Value
- * BxAP : 0x03800000  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
- * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0000000000000
- * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0000000000000
- */
-#define EBC_BXAP_SMALL_FLASH		EBC_BXAP_BME_DISABLED	| \
-					EBC_BXAP_TWT_ENCODE(7)	| \
-					EBC_BXAP_BCE_DISABLE	| \
-					EBC_BXAP_BCT_2TRANS	| \
-					EBC_BXAP_CSN_ENCODE(0)	| \
-					EBC_BXAP_OEN_ENCODE(0)	| \
-					EBC_BXAP_WBN_ENCODE(0)	| \
-					EBC_BXAP_WBF_ENCODE(0)	| \
-					EBC_BXAP_TH_ENCODE(0)	| \
-					EBC_BXAP_RE_DISABLED	| \
-					EBC_BXAP_SOR_DELAYED	| \
-					EBC_BXAP_BEM_WRITEONLY	| \
-					EBC_BXAP_PEN_DISABLED
-
-#define EBC_BXCR_SMALL_FLASH_CS0	EBC_BXCR_BAS_ENCODE(0xFF000000)	| \
-					EBC_BXCR_BS_16MB		| \
-					EBC_BXCR_BU_RW			| \
-					EBC_BXCR_BW_8BIT
-
-#define EBC_BXCR_SMALL_FLASH_CS2	EBC_BXCR_BAS_ENCODE(0xe7000000)	| \
-					EBC_BXCR_BS_16MB		| \
-					EBC_BXCR_BU_RW			| \
-					EBC_BXCR_BW_8BIT
-
-/*
- * Large Flash and SRAM
- * BU Value
- * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
- * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
- * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
-*/
-#define EBC_BXAP_LARGE_FLASH		EBC_BXAP_BME_DISABLED	| \
-					EBC_BXAP_TWT_ENCODE(7)	| \
-					EBC_BXAP_BCE_DISABLE	| \
-					EBC_BXAP_BCT_2TRANS	| \
-					EBC_BXAP_CSN_ENCODE(0)	| \
-					EBC_BXAP_OEN_ENCODE(0)	| \
-					EBC_BXAP_WBN_ENCODE(0)	| \
-					EBC_BXAP_WBF_ENCODE(0)	| \
-					EBC_BXAP_TH_ENCODE(0)	| \
-					EBC_BXAP_RE_DISABLED	| \
-					EBC_BXAP_SOR_DELAYED	| \
-					EBC_BXAP_BEM_WRITEONLY	| \
-					EBC_BXAP_PEN_DISABLED
-
-#define EBC_BXCR_LARGE_FLASH_CS0	EBC_BXCR_BAS_ENCODE(0xFF000000)	| \
-					EBC_BXCR_BS_16MB		| \
-					EBC_BXCR_BU_RW			| \
-					EBC_BXCR_BW_16BIT
-
-#define EBC_BXCR_LARGE_FLASH_CS2	EBC_BXCR_BAS_ENCODE(0xE7000000)	| \
-					EBC_BXCR_BS_16MB		| \
-					EBC_BXCR_BU_RW			| \
-					EBC_BXCR_BW_16BIT
-
-/*
- * FPGA
- * BU value :
- * B1AP = 0x05895240  - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
- * B1CR = 0xe201a000  - BAS = e20 - 000 11 01 00000000000000
- */
-#define EBC_BXAP_FPGA			EBC_BXAP_BME_DISABLED	| \
-					EBC_BXAP_TWT_ENCODE(11)	| \
-					EBC_BXAP_BCE_DISABLE	| \
-					EBC_BXAP_BCT_2TRANS	| \
-					EBC_BXAP_CSN_ENCODE(10)	| \
-					EBC_BXAP_OEN_ENCODE(1)	| \
-					EBC_BXAP_WBN_ENCODE(1)	| \
-					EBC_BXAP_WBF_ENCODE(1)	| \
-					EBC_BXAP_TH_ENCODE(1)	| \
-					EBC_BXAP_RE_DISABLED	| \
-					EBC_BXAP_SOR_DELAYED	| \
-					EBC_BXAP_BEM_RW		| \
-					EBC_BXAP_PEN_DISABLED
-
-#define EBC_BXCR_FPGA_CS1		EBC_BXCR_BAS_ENCODE(0xe2000000)	| \
-					EBC_BXCR_BS_1MB			| \
-					EBC_BXCR_BU_RW			| \
-					EBC_BXCR_BW_16BIT
-
-	 unsigned long mfr;
-	/*
-	 * Define Variables for EBC initialization depending on BOOTSTRAP option
-	 */
-	unsigned long sdr0_pinstp, sdr0_sdstp1 ;
-	unsigned long bootstrap_settings, ebc_data_width, boot_selection;
-	int computed_boot_device = BOOT_DEVICE_UNKNOWN;
-
-	/*-------------------------------------------------------------------+
-	 | Initialize EBC CONFIG -
-	 | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
-	 | default value :
-	 |	0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
-	 |
-	 +-------------------------------------------------------------------*/
-	mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
-			EBC_CFG_PTD_ENABLE |
-			EBC_CFG_RTC_16PERCLK |
-			EBC_CFG_ATC_PREVIOUS |
-			EBC_CFG_DTC_PREVIOUS |
-			EBC_CFG_CTC_PREVIOUS |
-			EBC_CFG_OEO_PREVIOUS |
-			EBC_CFG_EMC_DEFAULT |
-			EBC_CFG_PME_DISABLE |
-			EBC_CFG_PR_16);
-
-	/*-------------------------------------------------------------------+
-	 |
-	 |  PART 1 : Initialize EBC Bank 1
-	 |  ==============================
-	 | Bank1 is always associated to the EPLD.
-	 | It has to be initialized prior to other banks settings computation
-	 | since some board registers values may be needed to determine the
-	 | boot type
-	 |
-	 +-------------------------------------------------------------------*/
-	mtebc(PB1AP, EBC_BXAP_FPGA);
-	mtebc(PB1CR, EBC_BXCR_FPGA_CS1);
-
-	/*-------------------------------------------------------------------+
-	 |
-	 |  PART 2 : Determine which boot device was selected
-	 |  =================================================
-	 |
-	 |  Read Pin Strap Register in PPC440SPe
-	 |  Result can either be :
-	 |   - Boot strap = boot from EBC 8bits     => Small Flash
-	 |   - Boot strap = boot from PCI
-	 |   - Boot strap = IIC
-	 |  In case of boot from IIC, read Serial Device Strap Register1
-	 |
-	 |  Result can either be :
-	 |   - Boot from EBC  - EBC Bus Width = 8bits    => Small Flash
-	 |   - Boot from EBC  - EBC Bus Width = 16bits   => Large Flash or SRAM
-	 |   - Boot from PCI
-	 |
-	 +-------------------------------------------------------------------*/
-	/* Read Pin Strap Register in PPC440SP */
-	mfsdr(SDR0_PINSTP, sdr0_pinstp);
-	bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
-
-	switch (bootstrap_settings) {
-		case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
-			/*
-			 * Strapping Option A
-			 * Boot from EBC - 8 bits , Small Flash
-			 */
-			computed_boot_device = BOOT_FROM_SMALL_FLASH;
-			break;
-		case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
-			/*
-			 * Strappping Option B
-			 * Boot from PCI
-			 */
-			computed_boot_device = BOOT_FROM_PCI;
-			break;
-		case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
-		case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
-			/*
-			 * Strapping Option C or D
-			 * Boot Settings in IIC EEprom address 0x50 or 0x54
-			 * Read Serial Device Strap Register1 in PPC440SPe
-			 */
-			mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
-			boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
-			ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
-
-			switch (boot_selection) {
-				case SDR0_SDSTP1_ERPN_EBC:
-					switch (ebc_data_width) {
-						case SDR0_SDSTP1_EBCW_16_BITS:
-							computed_boot_device =
-								BOOT_FROM_LARGE_FLASH_OR_SRAM;
-							break;
-						case SDR0_SDSTP1_EBCW_8_BITS :
-							computed_boot_device = BOOT_FROM_SMALL_FLASH;
-							break;
-					}
-					break;
-
-				case SDR0_SDSTP1_ERPN_PCI:
-					computed_boot_device = BOOT_FROM_PCI;
-					break;
-				default:
-					/* should not occure */
-					computed_boot_device = BOOT_DEVICE_UNKNOWN;
-			}
-			break;
-		default:
-			/* should not be */
-			computed_boot_device = BOOT_DEVICE_UNKNOWN;
-			break;
-	}
-
-	/*-------------------------------------------------------------------+
-	 |
-	 |  PART 3 : Compute EBC settings depending on selected boot device
-	 |  ======   ======================================================
-	 |
-	 | Resulting EBC init will be among following configurations :
-	 |
-	 |  - Boot from EBC 8bits => boot from Small Flash selected
-	 |            EBC-CS0     = Small Flash
-	 |            EBC-CS2     = Large Flash and SRAM
-	 |
-	 |  - Boot from EBC 16bits => boot from Large Flash or SRAM
-	 |            EBC-CS0     = Large Flash or SRAM
-	 |            EBC-CS2     = Small Flash
-	 |
-	 |  - Boot from PCI
-	 |            EBC-CS0     = not initialized to avoid address contention
-	 |            EBC-CS2     = same as boot from Small Flash selected
-	 |
-	 +-------------------------------------------------------------------*/
-	unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
-	unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
-
-	switch (computed_boot_device) {
-		/*-------------------------------------------------------------------*/
-		case BOOT_FROM_PCI:
-		/*-------------------------------------------------------------------*/
-			/*
-			 * By Default CS2 is affected to LARGE Flash
-			 * do not initialize SMALL FLASH to avoid address contention
-			 * Large Flash
-			 */
-			ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
-			ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
-			break;
-
-		/*-------------------------------------------------------------------*/
-		case BOOT_FROM_SMALL_FLASH:
-		/*-------------------------------------------------------------------*/
-			ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
-			ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
-
-			/*
-			 * Large Flash or SRAM
-			 */
-			/* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
-			ebc0_cs2_bxap_value = 0x048ff240;
-			ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
-			break;
-
-		/*-------------------------------------------------------------------*/
-		case BOOT_FROM_LARGE_FLASH_OR_SRAM:
-		/*-------------------------------------------------------------------*/
-			ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
-			ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
-
-			/* Small flash */
-			ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
-			ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
-			break;
-
-		/*-------------------------------------------------------------------*/
-		default:
-		/*-------------------------------------------------------------------*/
-			/* BOOT_DEVICE_UNKNOWN */
-			break;
-	}
-
-	mtebc(PB0AP, ebc0_cs0_bxap_value);
-	mtebc(PB0CR, ebc0_cs0_bxcr_value);
-	mtebc(PB2AP, ebc0_cs2_bxap_value);
-	mtebc(PB2CR, ebc0_cs2_bxcr_value);
-
-	/*--------------------------------------------------------------------+
-	 | Interrupt controller setup for the AMCC 440SPe Evaluation board.
-	 +--------------------------------------------------------------------+
-	+---------------------------------------------------------------------+
-	|Interrupt| Source                            | Pol.  | Sensi.| Crit. |
-	+---------+-----------------------------------+-------+-------+-------+
-	| IRQ 00  | UART0                             | High  | Level | Non   |
-	| IRQ 01  | UART1                             | High  | Level | Non   |
-	| IRQ 02  | IIC0                              | High  | Level | Non   |
-	| IRQ 03  | IIC1                              | High  | Level | Non   |
-	| IRQ 04  | PCI0X0 MSG IN                     | High  | Level | Non   |
-	| IRQ 05  | PCI0X0 CMD Write                  | High  | Level | Non   |
-	| IRQ 06  | PCI0X0 Power Mgt                  | High  | Level | Non   |
-	| IRQ 07  | PCI0X0 VPD Access                 | Rising| Edge  | Non   |
-	| IRQ 08  | PCI0X0 MSI level 0                | High  | Lvl/ed| Non   |
-	| IRQ 09  | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non   |
-	| IRQ 10  | UIC2 Non-critical Int.            | NA    | NA    | Non   |
-	| IRQ 11  | UIC2 Critical Interrupt           | NA    | NA    | Crit  |
-	| IRQ 12  | PCI Express MSI Level 0           | Rising| Edge  | Non   |
-	| IRQ 13  | PCI Express MSI Level 1           | Rising| Edge  | Non   |
-	| IRQ 14  | PCI Express MSI Level 2           | Rising| Edge  | Non   |
-	| IRQ 15  | PCI Express MSI Level 3           | Rising| Edge  | Non   |
-	| IRQ 16  | UIC3 Non-critical Int.            | NA    | NA    | Non   |
-	| IRQ 17  | UIC3 Critical Interrupt           | NA    | NA    | Crit  |
-	| IRQ 18  | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non   |
-	| IRQ 19  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
-	| IRQ 20  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
-	| IRQ 21  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
-	| IRQ 22  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
-	| IRQ 23  | I2O Inbound Doorbell              | High  | Level | Non   |
-	| IRQ 24  | Inbound Post List FIFO Not Empt   | High  | Level | Non   |
-	| IRQ 25  | I2O Region 0 LL PLB Write         | High  | Level | Non   |
-	| IRQ 26  | I2O Region 1 LL PLB Write         | High  | Level | Non   |
-	| IRQ 27  | I2O Region 0 HB PLB Write         | High  | Level | Non   |
-	| IRQ 28  | I2O Region 1 HB PLB Write         | High  | Level | Non   |
-	| IRQ 29  | GPT Down Count Timer              | Rising| Edge  | Non   |
-	| IRQ 30  | UIC1 Non-critical Int.            | NA    | NA    | Non   |
-	| IRQ 31  | UIC1 Critical Interrupt           | NA    | NA    | Crit. |
-	|----------------------------------------------------------------------
-	| IRQ 32  | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non   |
-	| IRQ 33  | MAL Serr                          | High  | Level | Non   |
-	| IRQ 34  | MAL Txde                          | High  | Level | Non   |
-	| IRQ 35  | MAL Rxde                          | High  | Level | Non   |
-	| IRQ 36  | DMC CE or DMC UE                  | High  | Level | Non   |
-	| IRQ 37  | EBC or UART2                      | High  |Lvl Edg| Non   |
-	| IRQ 38  | MAL TX EOB                        | High  | Level | Non   |
-	| IRQ 39  | MAL RX EOB                        | High  | Level | Non   |
-	| IRQ 40  | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non   |
-	| IRQ 41  | PCIX0 MSI level 2                 | High  |Lvl Edg| Non   |
-	| IRQ 42  | PCIX0 MSI level 3                 | High  |Lvl Edg| Non   |
-	| IRQ 43  | L2 Cache                          | Risin | Edge  | Non   |
-	| IRQ 44  | GPT Compare Timer 0               | Risin | Edge  | Non   |
-	| IRQ 45  | GPT Compare Timer 1               | Risin | Edge  | Non   |
-	| IRQ 46  | GPT Compare Timer 2               | Risin | Edge  | Non   |
-	| IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
-	| IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
-	| IRQ 49  | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 50  | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non   |
-	| IRQ 51  | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non   |
-	| IRQ 52  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
-	| IRQ 53  | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non   |
-	| IRQ 54  | DMA Error                         | High  | Level | Non   |
-	| IRQ 55  | DMA I2O Error                     | High  | Level | Non   |
-	| IRQ 56  | Serial ROM                        | High  | Level | Non   |
-	| IRQ 57  | PCIX0 Error                       | High  | Edge  | Non   |
-	| IRQ 58  | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non   |
-	| IRQ 59  | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non   |
-	| IRQ 60  | EMAC0 Interrupt                   | High  | Level | Non   |
-	| IRQ 61  | EMAC0 Wake-up                     | High  | Level | Non   |
-	| IRQ 62  | Reserved                          | High  | Level | Non   |
-	| IRQ 63  | XOR                               | High  | Level | Non   |
-	|----------------------------------------------------------------------
-	| IRQ 64  | PE0 AL                            | High  | Level | Non   |
-	| IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
-	| IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
-	| IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
-	| IRQ 68  | PE0 TCR                           | High  | Level | Non   |
-	| IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
-	| IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
-	| IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 72  | PE1 AL                            | High  | Level | Non   |
-	| IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
-	| IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
-	| IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
-	| IRQ 76  | PE1 TCR                           | High  | Level | Non   |
-	| IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
-	| IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
-	| IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 80  | PE2 AL                            | High  | Level | Non   |
-	| IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
-	| IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
-	| IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
-	| IRQ 84  | PE2 TCR                           | High  | Level | Non   |
-	| IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
-	| IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
-	| IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
-	| IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
-	| IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
-	|---------------------------------------------------------------------
-	| IRQ 96  | PE0 INTA                          | High  | Level | Non   |
-	| IRQ 97  | PE0 INTB                          | High  | Level | Non   |
-	| IRQ 98  | PE0 INTC                          | High  | Level | Non   |
-	| IRQ 99  | PE0 INTD                          | High  | Level | Non   |
-	| IRQ 100 | PE1 INTA                          | High  | Level | Non   |
-	| IRQ 101 | PE1 INTB                          | High  | Level | Non   |
-	| IRQ 102 | PE1 INTC                          | High  | Level | Non   |
-	| IRQ 103 | PE1 INTD                          | High  | Level | Non   |
-	| IRQ 104 | PE2 INTA                          | High  | Level | Non   |
-	| IRQ 105 | PE2 INTB                          | High  | Level | Non   |
-	| IRQ 106 | PE2 INTC                          | High  | Level | Non   |
-	| IRQ 107 | PE2 INTD                          | Risin | Edge  | Non   |
-	| IRQ 108 | PCI Express MSI Level 4           | Risin | Edge  | Non   |
-	| IRQ 109 | PCI Express MSI Level 5           | Risin | Edge  | Non   |
-	| IRQ 110 | PCI Express MSI Level 6           | Risin | Edge  | Non   |
-	| IRQ 111 | PCI Express MSI Level 7           | Risin | Edge  | Non   |
-	| IRQ 116 | PCI Express MSI Level 12          | Risin | Edge  | Non   |
-	| IRQ 112 | PCI Express MSI Level 8           | Risin | Edge  | Non   |
-	| IRQ 113 | PCI Express MSI Level 9           | Risin | Edge  | Non   |
-	| IRQ 114 | PCI Express MSI Level 10          | Risin | Edge  | Non   |
-	| IRQ 115 | PCI Express MSI Level 11          | Risin | Edge  | Non   |
-	| IRQ 117 | PCI Express MSI Level 13          | Risin | Edge  | Non   |
-	| IRQ 118 | PCI Express MSI Level 14          | Risin | Edge  | Non   |
-	| IRQ 119 | PCI Express MSI Level 15          | Risin | Edge  | Non   |
-	| IRQ 120 | PCI Express MSI Level 16          | Risin | Edge  | Non   |
-	| IRQ 121 | PCI Express MSI Level 17          | Risin | Edge  | Non   |
-	| IRQ 122 | PCI Express MSI Level 18          | Risin | Edge  | Non   |
-	| IRQ 123 | PCI Express MSI Level 19          | Risin | Edge  | Non   |
-	| IRQ 124 | PCI Express MSI Level 20          | Risin | Edge  | Non   |
-	| IRQ 125 | PCI Express MSI Level 21          | Risin | Edge  | Non   |
-	| IRQ 126 | PCI Express MSI Level 22          | Risin | Edge  | Non   |
-	| IRQ 127 | PCI Express MSI Level 23          | Risin | Edge  | Non   |
-	+---------+-----------------------------------+-------+-------+------*/
-	/*--------------------------------------------------------------------+
-	 | Put UICs in PowerPC440SPemode.
-	 | Initialise UIC registers.  Clear all interrupts.  Disable all
-	 | interrupts.
-	 | Set critical interrupt values.  Set interrupt polarities.  Set
-	 | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
-	 | interrupts again.
-	 +-------------------------------------------------------------------*/
-	mtdcr (UIC3SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (UIC3ER, 0x00000000);	/* disable all interrupts */
-	mtdcr (UIC3CR, 0x00000000);	/* Set Critical / Non Critical
-					 * interrupts */
-	mtdcr (UIC3PR, 0xffffffff);	/* Set Interrupt Polarities */
-	mtdcr (UIC3TR, 0x001fffff);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC3VR, 0x00000001);	/* Set Vect base=0,INT31 Highest
-					 * priority */
-	mtdcr (UIC3SR, 0x00000000);	/* clear all  interrupts */
-	mtdcr (UIC3SR, 0xffffffff);	/* clear all  interrupts */
-
-	mtdcr (UIC2SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (UIC2ER, 0x00000000);	/* disable all interrupts */
-	mtdcr (UIC2CR, 0x00000000);	/* Set Critical / Non Critical
-					 * interrupts */
-	mtdcr (UIC2PR, 0xebebebff);	/* Set Interrupt Polarities */
-	mtdcr (UIC2TR, 0x74747400);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC2VR, 0x00000001);	/* Set Vect base=0,INT31 Highest
-					 * priority */
-	mtdcr (UIC2SR, 0x00000000);	/* clear all interrupts */
-	mtdcr (UIC2SR, 0xffffffff);	/* clear all interrupts */
-
-	mtdcr (UIC1SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (UIC1ER, 0x00000000);	/* disable all interrupts */
-	mtdcr (UIC1CR, 0x00000000);	/* Set Critical / Non Critical
-					 * interrupts */
-	mtdcr (UIC1PR, 0xffffffff);	/* Set Interrupt Polarities */
-	mtdcr (UIC1TR, 0x001f8040);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC1VR, 0x00000001);	/* Set Vect base=0,INT31 Highest
-					 * priority */
-	mtdcr (UIC1SR, 0x00000000);	/* clear all interrupts */
-	mtdcr (UIC1SR, 0xffffffff);	/* clear all interrupts */
-
-	mtdcr (UIC0SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr (UIC0ER, 0x00000000);	/* disable all interrupts excepted
-					 * cascade to be checked */
-	mtdcr (UIC0CR, 0x00104001);	/* Set Critical / Non Critical
-					 * interrupts */
-	mtdcr (UIC0PR, 0xffffffff);	/* Set Interrupt Polarities */
-	mtdcr (UIC0TR, 0x010f0004);	/* Set Interrupt Trigger Levels */
-	mtdcr (UIC0VR, 0x00000001);	/* Set Vect base=0,INT31 Highest
-					 * priority */
-	mtdcr (UIC0SR, 0x00000000);	/* clear all interrupts */
-	mtdcr (UIC0SR, 0xffffffff);	/* clear all interrupts */
-
-	mfsdr(SDR0_MFR, mfr);
-	mfr |= SDR0_MFR_FIXD;		/* Workaround for PCI/DMA */
-	mtsdr(SDR0_MFR, mfr);
-
-	fpga_init();
-
-	return 0;
-}
-
-int checkboard (void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf("Board: Yucca - AMCC 440SPe Evaluation Board");
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-/*
- * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
- * board specific values.
- */
-static int ppc440spe_rev_a(void)
-{
-	if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
-		return 1;
-	else
-		return 0;
-}
-
-u32 ddr_wrdtr(u32 default_val) {
-	/*
-	 * Yucca boards with 440SPe rev. A need a slightly different setup
-	 * for the MCIF0_WRDTR register.
-	 */
-	if (ppc440spe_rev_a())
-		return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
-
-	return default_val;
-}
-
-u32 ddr_clktr(u32 default_val) {
-	/*
-	 * Yucca boards with 440SPe rev. A need a slightly different setup
-	 * for the MCIF0_CLKTR register.
-	 */
-	if (ppc440spe_rev_a())
-		return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
-
-	return default_val;
-}
-
-#if defined(CONFIG_PCI)
-int board_pcie_card_present(int port)
-{
-	u16 reg;
-
-	reg = in_be16((u16 *)FPGA_REG1C);
-	switch(port) {
-	case 0:
-		return !(reg & FPGA_REG1C_PE0_PRSNT);
-	case 1:
-		return !(reg & FPGA_REG1C_PE1_PRSNT);
-	case 2:
-		return !(reg & FPGA_REG1C_PE2_PRSNT);
-	default:
-		return 0;
-	}
-}
-
-/*
- * For the given slot, set endpoint mode, send power to the slot,
- * turn on the green LED and turn off the yellow LED, enable the
- * clock. In endpoint mode reset bit is read only.
- */
-void board_pcie_setup_port(int port, int rootpoint)
-{
-	u16 power, clock, green_led, yellow_led,
-		reset_off, rp, ep;
-
-	switch (port) {
-	case 0:
-		rp = FPGA_REG1C_PE0_ROOTPOINT;
-		ep = 0;
-		break;
-	case 1:
-		rp = 0;
-		ep = FPGA_REG1C_PE1_ENDPOINT;
-		break;
-	case 2:
-		rp = 0;
-		ep = FPGA_REG1C_PE2_ENDPOINT;
-		break;
-
-	default:
-		return;
-	}
-
-	power = FPGA_REG1A_PWRON_ENCODE(port);
-	green_led = FPGA_REG1A_GLED_ENCODE(port);
-	clock = FPGA_REG1A_REFCLK_ENCODE(port);
-	yellow_led = FPGA_REG1A_YLED_ENCODE(port);
-	reset_off = FPGA_REG1C_PERST_ENCODE(port);
-
-	out_be16((u16 *)FPGA_REG1A, ~(power | clock | green_led) &
-		 (yellow_led | in_be16((u16 *)FPGA_REG1A)));
-
-	out_be16((u16 *)FPGA_REG1C, ~(ep | reset_off) &
-		 (rp | in_be16((u16 *)FPGA_REG1C)));
-
-	if (rootpoint) {
-		/*
-		 * Leave device in reset for a while after powering on the
-		 * slot to give it a chance to initialize.
-		 */
-		udelay(250 * 1000);
-
-		out_be16((u16 *)FPGA_REG1C,
-			 reset_off | in_be16((u16 *)FPGA_REG1C));
-	}
-}
-#endif	/* defined(CONFIG_PCI) */
-
-int misc_init_f (void)
-{
-	uint reg;
-
-	out16(FPGA_REG10, (in16(FPGA_REG10) &
-			~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
-				FPGA_REG10_10MHZ_ENABLE |
-				FPGA_REG10_100MHZ_ENABLE |
-				FPGA_REG10_GIGABIT_ENABLE |
-				FPGA_REG10_FULL_DUPLEX );
-
-	udelay(10000);	/* wait 10ms */
-
-	out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
-
-	/* minimal init for PCIe */
-	/* pci express 0 Endpoint Mode */
-	mfsdr(SDRN_PESDR_DLPSET(0), reg);
-	reg &= (~0x00400000);
-	mtsdr(SDRN_PESDR_DLPSET(0), reg);
-	/* pci express 1 Rootpoint  Mode */
-	mfsdr(SDRN_PESDR_DLPSET(1), reg);
-	reg |= 0x00400000;
-	mtsdr(SDRN_PESDR_DLPSET(1), reg);
-	/* pci express 2 Rootpoint  Mode */
-	mfsdr(SDRN_PESDR_DLPSET(2), reg);
-	reg |= 0x00400000;
-	mtsdr(SDRN_PESDR_DLPSET(2), reg);
-
-	out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
-				~FPGA_REG1C_PE0_ROOTPOINT &
-				~FPGA_REG1C_PE1_ENDPOINT  &
-				~FPGA_REG1C_PE2_ENDPOINT));
-
-	return 0;
-}
-
-void fpga_init(void)
-{
-	/*
-	 * by default sdram access is disabled by fpga
-	 */
-	out16(FPGA_REG10, (in16 (FPGA_REG10) |
-				FPGA_REG10_SDRAM_ENABLE |
-				FPGA_REG10_ENABLE_DISPLAY ));
-
-	return;
-}
-
-/*---------------------------------------------------------------------------+
- | onboard_pci_arbiter_selected => from EPLD
- +---------------------------------------------------------------------------*/
-int onboard_pci_arbiter_selected(int core_pci)
-{
-#if 0
-	unsigned long onboard_pci_arbiter_sel;
-
-	onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
-
-	if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
-		return (BOARD_OPTION_SELECTED);
-	else
-#endif
-	return (BOARD_OPTION_NOT_SELECTED);
-}
-
-int board_eth_init(bd_t *bis)
-{
-	cpu_eth_init(bis);
-	return pci_eth_init(bis);
-}
diff --git a/board/amcc/yucca/yucca.h b/board/amcc/yucca/yucca.h
deleted file mode 100644
index ac9e5ae..0000000
--- a/board/amcc/yucca/yucca.h
+++ /dev/null
@@ -1,350 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __YUCCA_H_
-#define __YUCCA_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*----------------------------------------------------------------------------+
-| Defines
-+----------------------------------------------------------------------------*/
-
-#define TMR_FREQ_EXT		25000000
-#define BOARD_UART_CLOCK	11059200
-
-#define BOARD_OPTION_SELECTED		1
-#define BOARD_OPTION_NOT_SELECTED	0
-
-#define ENGINEERING_CLOCK_CHECKING "clk_chk"
-#define ENGINEERING_EXTERNAL_CLOCK "ext_clk"
-
-#define ENGINEERING_CLOCK_CHECKING_DATA	1
-#define ENGINEERING_EXTERNAL_CLOCK_DATA	2
-
-/* ethernet definition */
-#define MAX_ENETMODE_PARM	3
-#define ENETMODE_NEG		0
-#define ENETMODE_SPEED		1
-#define ENETMODE_DUPLEX		2
-
-#define ENETMODE_AUTONEG	0
-#define ENETMODE_NO_AUTONEG	1
-#define ENETMODE_10		2
-#define ENETMODE_100		3
-#define ENETMODE_1000		4
-#define ENETMODE_HALF		5
-#define ENETMODE_FULL		6
-
-#define NUM_TLB_ENTRIES          64
-
-/* MICRON SPD JEDEC ID Code (first byte) - SPD data byte [64] */
-#define MICRON_SPD_JEDEC_ID 0x2c
-
-/*----------------------------------------------------------------------------+
-| TLB specific defines.
-+----------------------------------------------------------------------------*/
-#define TLB_256MB_ALIGN_MASK	0xF0000000
-#define TLB_16MB_ALIGN_MASK	0xFF000000
-#define TLB_1MB_ALIGN_MASK	0xFFF00000
-#define TLB_256KB_ALIGN_MASK	0xFFFC0000
-#define TLB_64KB_ALIGN_MASK	0xFFFF0000
-#define TLB_16KB_ALIGN_MASK	0xFFFFC000
-#define TLB_4KB_ALIGN_MASK	0xFFFFF000
-#define TLB_1KB_ALIGN_MASK	0xFFFFFC00
-#define TLB_256MB_SIZE		0x10000000
-#define TLB_16MB_SIZE		0x01000000
-#define TLB_1MB_SIZE		0x00100000
-#define TLB_256KB_SIZE		0x00040000
-#define TLB_64KB_SIZE		0x00010000
-#define TLB_16KB_SIZE		0x00004000
-#define TLB_4KB_SIZE		0x00001000
-#define TLB_1KB_SIZE		0x00000400
-
-#define TLB_WORD0_EPN_MASK	0xFFFFFC00
-#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
-#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
-#define TLB_WORD0_V_MASK	0x00000200
-#define TLB_WORD0_V_ENABLE	0x00000200
-#define TLB_WORD0_V_DISABLE	0x00000000
-#define TLB_WORD0_TS_MASK	0x00000100
-#define TLB_WORD0_TS_1		0x00000100
-#define TLB_WORD0_TS_0		0x00000000
-#define TLB_WORD0_SIZE_MASK	0x000000F0
-#define TLB_WORD0_SIZE_1KB	0x00000000
-#define TLB_WORD0_SIZE_4KB	0x00000010
-#define TLB_WORD0_SIZE_16KB	0x00000020
-#define TLB_WORD0_SIZE_64KB	0x00000030
-#define TLB_WORD0_SIZE_256KB	0x00000040
-#define TLB_WORD0_SIZE_1MB	0x00000050
-#define TLB_WORD0_SIZE_16MB	0x00000070
-#define TLB_WORD0_SIZE_256MB	0x00000090
-#define TLB_WORD0_TPAR_MASK	0x0000000F
-#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
-#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
-
-#define TLB_WORD1_RPN_MASK	0xFFFFFC00
-#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
-#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
-#define TLB_WORD1_PAR1_MASK	0x00000300
-#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
-#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
-#define TLB_WORD1_PAR1_0	0x00000000
-#define TLB_WORD1_PAR1_1	0x00000100
-#define TLB_WORD1_PAR1_2	0x00000200
-#define TLB_WORD1_PAR1_3	0x00000300
-#define TLB_WORD1_ERPN_MASK	0x0000000F
-#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
-#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
-
-#define TLB_WORD2_PAR2_MASK	0xC0000000
-#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
-#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
-#define TLB_WORD2_PAR2_0	0x00000000
-#define TLB_WORD2_PAR2_1	0x40000000
-#define TLB_WORD2_PAR2_2	0x80000000
-#define TLB_WORD2_PAR2_3	0xC0000000
-#define TLB_WORD2_U0_MASK	0x00008000
-#define TLB_WORD2_U0_ENABLE	0x00008000
-#define TLB_WORD2_U0_DISABLE	0x00000000
-#define TLB_WORD2_U1_MASK	0x00004000
-#define TLB_WORD2_U1_ENABLE	0x00004000
-#define TLB_WORD2_U1_DISABLE	0x00000000
-#define TLB_WORD2_U2_MASK	0x00002000
-#define TLB_WORD2_U2_ENABLE	0x00002000
-#define TLB_WORD2_U2_DISABLE	0x00000000
-#define TLB_WORD2_U3_MASK	0x00001000
-#define TLB_WORD2_U3_ENABLE	0x00001000
-#define TLB_WORD2_U3_DISABLE	0x00000000
-#define TLB_WORD2_W_MASK	0x00000800
-#define TLB_WORD2_W_ENABLE	0x00000800
-#define TLB_WORD2_W_DISABLE	0x00000000
-#define TLB_WORD2_I_MASK	0x00000400
-#define TLB_WORD2_I_ENABLE	0x00000400
-#define TLB_WORD2_I_DISABLE	0x00000000
-#define TLB_WORD2_M_MASK	0x00000200
-#define TLB_WORD2_M_ENABLE	0x00000200
-#define TLB_WORD2_M_DISABLE	0x00000000
-#define TLB_WORD2_G_MASK	0x00000100
-#define TLB_WORD2_G_ENABLE	0x00000100
-#define TLB_WORD2_G_DISABLE	0x00000000
-#define TLB_WORD2_E_MASK	0x00000080
-#define TLB_WORD2_E_ENABLE	0x00000080
-#define TLB_WORD2_E_DISABLE	0x00000000
-#define TLB_WORD2_UX_MASK	0x00000020
-#define TLB_WORD2_UX_ENABLE	0x00000020
-#define TLB_WORD2_UX_DISABLE	0x00000000
-#define TLB_WORD2_UW_MASK	0x00000010
-#define TLB_WORD2_UW_ENABLE	0x00000010
-#define TLB_WORD2_UW_DISABLE	0x00000000
-#define TLB_WORD2_UR_MASK	0x00000008
-#define TLB_WORD2_UR_ENABLE	0x00000008
-#define TLB_WORD2_UR_DISABLE	0x00000000
-#define TLB_WORD2_SX_MASK	0x00000004
-#define TLB_WORD2_SX_ENABLE	0x00000004
-#define TLB_WORD2_SX_DISABLE	0x00000000
-#define TLB_WORD2_SW_MASK	0x00000002
-#define TLB_WORD2_SW_ENABLE	0x00000002
-#define TLB_WORD2_SW_DISABLE	0x00000000
-#define TLB_WORD2_SR_MASK	0x00000001
-#define TLB_WORD2_SR_ENABLE	0x00000001
-#define TLB_WORD2_SR_DISABLE	0x00000000
-
-/*----------------------------------------------------------------------------+
-| Board specific defines.
-+----------------------------------------------------------------------------*/
-#define NONCACHE_MEMORY_SIZE     (64*1024)
-#define NONCACHE_AREA0_ENDOFFSET (64*1024)
-#define NONCACHE_AREA1_ENDOFFSET (32*1024)
-
-#define FLASH_SECTORSIZE	0x00010000
-
-/* SDRAM MICRON */
-#define SDRAM_MICRON		0x2C
-
-#define SDRAM_TRUE		1
-#define SDRAM_FALSE		0
-#define SDRAM_DDR1		1
-#define SDRAM_DDR2		2
-#define SDRAM_NONE		0
-#define MAXDIMMS		2		/* Changes le 12/01/05 pour 1.6 */
-#define MAXRANKS		4		/* Changes le 12/01/05 pour 1.6 */
-#define MAXBANKSPERDIMM		2
-#define MAXRANKSPERDIMM		2
-#define MAXBXCF			4		/* Changes le 12/01/05 pour 1.6 */
-#define MAXSDRAMMEMORY		0xFFFFFFFF	/* 4GB */
-#define ERROR_STR_LENGTH	256
-#define MAX_SPD_BYTES		256		/* Max number of bytes on the DIMM's SPD EEPROM */
-
-/*----------------------------------------------------------------------------+
-| SDR Configuration registers
-+----------------------------------------------------------------------------*/
-/* Serial Device Strap Reg 0 */
-#define sdr_pstrp0	0x0040
-
-#define	SDR0_SDSTP1_EBC_ROM_BS_MASK	0x00000080 /* EBC Boot bus width Mask */
-#define	SDR0_SDSTP1_EBC_ROM_BS_16BIT	0x00000080 /* EBC 16 Bits */
-#define	SDR0_SDSTP1_EBC_ROM_BS_8BIT	0x00000000 /* EBC  8 Bits */
-
-#define	SDR0_SDSTP1_BOOT_SEL_MASK	0x00080000 /* Boot device Selection Mask */
-#define	SDR0_SDSTP1_BOOT_SEL_EBC	0x00000000 /* EBC */
-#define	SDR0_SDSTP1_BOOT_SEL_PCI	0x00080000 /* PCI */
-
-#define	SDR0_SDSTP1_EBC_SIZE_MASK	0x00000060 /* Boot rom size Mask */
-#define	SDR0_SDSTP1_BOOT_SIZE_16MB	0x00000060 /* 16 MB */
-#define	SDR0_SDSTP1_BOOT_SIZE_8MB	0x00000040 /*  8 MB */
-#define	SDR0_SDSTP1_BOOT_SIZE_4MB	0x00000020 /*  4 MB */
-#define	SDR0_SDSTP1_BOOT_SIZE_2MB	0x00000000 /*  2 MB */
-
-/* Serial Device Enabled - Addr = 0xA8 */
-#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5
-/* Serial Device Enabled - Addr = 0xA4 */
-#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7
-
-/* Pin Straps Reg */
-#define SDR0_PSTRP0			0x0040
-#define SDR0_PSTRP0_BOOTSTRAP_MASK	0xE0000000  /* Strap Bits */
-
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0	0x00000000  /* Default strap settings 0 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1	0x20000000  /* Default strap settings 1 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2	0x40000000  /* Default strap settings 2 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3	0x60000000  /* Default strap settings 3 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4	0x80000000  /* Default strap settings 4 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5	0xA0000000  /* Default strap settings 5 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6	0xC0000000  /* Default strap settings 6 */
-#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7	0xE0000000  /* Default strap settings 7 */
-
-/* fpgareg - defines are in include/config/YUCCA.h */
-
-#define SDR0_CUST0_ENET3_MASK		0x00000080
-#define SDR0_CUST0_ENET3_COPPER		0x00000000
-#define SDR0_CUST0_ENET3_FIBER		0x00000080
-#define SDR0_CUST0_RGMII3_MASK		0x00000070
-#define SDR0_CUST0_RGMII3_ENCODE(n)	((((unsigned long)(n))&0x7)<<4)
-#define SDR0_CUST0_RGMII3_DECODE(n)	((((unsigned long)(n))>>4)&0x07)
-#define SDR0_CUST0_RGMII3_DISAB		0x00000000
-#define SDR0_CUST0_RGMII3_RTBI		0x00000040
-#define SDR0_CUST0_RGMII3_RGMII		0x00000050
-#define SDR0_CUST0_RGMII3_TBI		0x00000060
-#define SDR0_CUST0_RGMII3_GMII		0x00000070
-#define SDR0_CUST0_ENET2_MASK		0x00000008
-#define SDR0_CUST0_ENET2_COPPER		0x00000000
-#define SDR0_CUST0_ENET2_FIBER		0x00000008
-#define SDR0_CUST0_RGMII2_MASK		0x00000007
-#define SDR0_CUST0_RGMII2_ENCODE(n)	((((unsigned long)(n))&0x7)<<0)
-#define SDR0_CUST0_RGMII2_DECODE(n)	((((unsigned long)(n))>>0)&0x07)
-#define SDR0_CUST0_RGMII2_DISAB		0x00000000
-#define SDR0_CUST0_RGMII2_RTBI		0x00000004
-#define SDR0_CUST0_RGMII2_RGMII		0x00000005
-#define SDR0_CUST0_RGMII2_TBI		0x00000006
-#define SDR0_CUST0_RGMII2_GMII		0x00000007
-
-#define ONE_MILLION			1000000
-#define ONE_BILLION			1000000000
-
-/*----------------------------------------------------------------------------+
-|                               X
-|                              XX
-| XX  XXX   XXXXX   XX XXX    XXXXX
-| XX  XX        X    XXX XX    XX
-| XX  XX   XXXXXX    XX        XX
-| XX  XX   X   XX    XX        XX XX
-|  XXX XX  XXXXX X  XXXX        XXX
-+----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------+
-| Declare Configuration values
-+----------------------------------------------------------------------------*/
-
-typedef enum config_selection {
-	CONFIG_NOT_SELECTED,
-	CONFIG_SELECTED
-} config_selection_t;
-
-typedef enum config_list {
-	UART2_IN_SERVICE_MODE,
-	CPU_TRACE_MODE,
-	UART1_CTS_RTS,
-	CONFIG_NB
-} config_list_t;
-
-#define MAX_CONFIG_SELECT_NB			3
-
-#define BOARD_INFO_UART2_IN_SERVICE_MODE	1
-#define BOARD_INFO_CPU_TRACE_MODE		2
-#define BOARD_INFO_UART1_CTS_RTS_MODE		4
-
-void force_bup_config_selection(config_selection_t *confgi_select_P);
-void update_config_selection_table(config_selection_t *config_select_P);
-void display_config_selection(config_selection_t *config_select_P);
-
-/*----------------------------------------------------------------------------+
-|                     XX
-|
-|   XXXX    XX XXX   XXX     XXXX
-|  XX        XX  XX   XX    XX  XX
-|  XX  XXX   XX  XX   XX    XX  XX
-|  XX  XX    XXXXX    XX    XX  XX
-|   XXXX     XX      XXXX    XXXX
-|           XXXX
-|
-|
-|
-| +------------------------------------------------------------------+
-| |  GPIO/Secondary func | Primary Function | I/O | Alternate1 | I/O |
-| +----------------------+------------------+-----+------------+-----+
-| |                      |                  |     |            |     |
-| | GPIO0_0              | PCIX0REQ2_N      | I/O |  TRCCLK    |     |
-| | GPIO0_1              | PCIX0REQ3_N      | I/O |  TRCBS0    |     |
-| | GPIO0_2              | PCIX0GNT2_N      | I/O |  TRCBS1    |     |
-| | GPIO0_3              | PCIX0GNT3_N      | I/O |  TRCBS2    |     |
-| | GPIO0_4              | PCIX1REQ2_N      | I/O |  TRCES0    |     |
-| | GPIO0_5              | PCIX1REQ3_N      | I/O |  TRCES1    |     |
-| | GPIO0_6              | PCIX1GNT2_N      | I/O |  TRCES2    | NA  |
-| | GPIO0_7              | PCIX1GNT3_N      | I/O |  TRCES3    | NA  |
-| | GPIO0_8              | PERREADY         |  I  |  TRCES4    | NA  |
-| | GPIO0_9              | PERCS1_N         |  O  |  TRCTS0    | NA  |
-| | GPIO0_10             | PERCS2_N         |  O  |  TRCTS1    | NA  |
-| | GPIO0_11             | IRQ0             |  I  |  TRCTS2    | NA  |
-| | GPIO0_12             | IRQ1             |  I  |  TRCTS3    | NA  |
-| | GPIO0_13             | IRQ2             |  I  |  TRCTS4    | NA  |
-| | GPIO0_14             | IRQ3             |  I  |  TRCTS5    | NA  |
-| | GPIO0_15             | IRQ4             |  I  |  TRCTS6    | NA  |
-| | GPIO0_16             | IRQ5             |  I  |  UART2RX   |  I  |
-| | GPIO0_17             | PERBE0_N         |  O  |  UART2TX   |  O  |
-| | GPIO0_18             | PCI0GNT0_N       | I/O |  NA        | NA  |
-| | GPIO0_19             | PCI0GNT1_N       | I/O |  NA        | NA  |
-| | GPIO0_20             | PCI0REQ0_N       | I/O |  NA        | NA  |
-| | GPIO0_21             | PCI0REQ1_N       | I/O |  NA        | NA  |
-| | GPIO0_22             | PCI1GNT0_N       | I/O |  NA        | NA  |
-| | GPIO0_23             | PCI1GNT1_N       | I/O |  NA        | NA  |
-| | GPIO0_24             | PCI1REQ0_N       | I/O |  NA        | NA  |
-| | GPIO0_25             | PCI1REQ1_N       | I/O |  NA        | NA  |
-| | GPIO0_26             | PCI2GNT0_N       | I/O |  NA        | NA  |
-| | GPIO0_27             | PCI2GNT1_N       | I/O |  NA        | NA  |
-| | GPIO0_28             | PCI2REQ0_N       | I/O |  NA        | NA  |
-| | GPIO0_29             | PCI2REQ1_N       | I/O |  NA        | NA  |
-| | GPIO0_30             | UART1RX          |  I  |  NA        | NA  |
-| | GPIO0_31             | UART1TX          |  O  |  NA        | NA  |
-| |                      |                  |     |            |     |
-| +----------------------+------------------+-----+------------+-----+
-|
-+----------------------------------------------------------------------------*/
-
-unsigned long auto_calc_speed(void);
-/*----------------------------------------------------------------------------+
-| Prototypes
-+----------------------------------------------------------------------------*/
-void print_evb440spe_info(void);
-
-int onboard_pci_arbiter_selected(int core_pci);
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __YUCCA_H_ */
diff --git a/board/amlogic/odroid-c2/README b/board/amlogic/odroid-c2/README
index d6d266a..b407c04 100644
--- a/board/amlogic/odroid-c2/README
+++ b/board/amlogic/odroid-c2/README
@@ -18,6 +18,7 @@ Schematics are available on the manufacturer website.
 
 Currently the u-boot port supports the following devices:
  - serial
+ - eMMC, microSD
  - Ethernet
 
 u-boot compilation
diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c
index b61daaa..b29f56d 100644
--- a/board/amlogic/odroid-c2/odroid-c2.c
+++ b/board/amlogic/odroid-c2/odroid-c2.c
@@ -5,10 +5,10 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <asm/io.h>
 #include <asm/arch/gxbb.h>
 #include <asm/arch/sm.h>
-#include <dm/platdata.h>
 #include <phy.h>
 
 #define EFUSE_SN_OFFSET		20
@@ -24,6 +24,7 @@ int board_init(void)
 int misc_init_r(void)
 {
 	u8 mac_addr[EFUSE_MAC_SIZE];
+	char serial[EFUSE_SN_SIZE];
 	ssize_t len;
 
 	/* Set RGMII mode */
@@ -50,5 +51,12 @@ int misc_init_r(void)
 			eth_setenv_enetaddr("ethaddr", mac_addr);
 	}
 
+	if (!getenv("serial#")) {
+		len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
+			EFUSE_SN_SIZE);
+		if (len == EFUSE_SN_SIZE) 
+			setenv("serial#", serial);
+	}
+
 	return 0;
 }
diff --git a/board/aries/m28evk/Kconfig b/board/aries/m28evk/Kconfig
new file mode 100644
index 0000000..ab5577c
--- /dev/null
+++ b/board/aries/m28evk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M28EVK
+
+config SYS_BOARD
+	default "m28evk"
+
+config SYS_VENDOR
+	default "aries"
+
+config SYS_SOC
+	default "mxs"
+
+config SYS_CONFIG_NAME
+	default "m28evk"
+
+endif
diff --git a/board/aries/m28evk/MAINTAINERS b/board/aries/m28evk/MAINTAINERS
new file mode 100644
index 0000000..aad6313
--- /dev/null
+++ b/board/aries/m28evk/MAINTAINERS
@@ -0,0 +1,6 @@
+M28EVK BOARD
+#M:	Marek Vasut <marek.vasut@gmail.com>
+S:	Orphan (since 2017-07)
+F:	board/aries/m28evk/
+F:	include/configs/m28evk.h
+F:	configs/m28evk_defconfig
diff --git a/board/denx/m28evk/Makefile b/board/aries/m28evk/Makefile
index 5e890b1..5e890b1 100644
--- a/board/denx/m28evk/Makefile
+++ b/board/aries/m28evk/Makefile
diff --git a/board/aries/m28evk/README b/board/aries/m28evk/README
new file mode 100644
index 0000000..9f0d995
--- /dev/null
+++ b/board/aries/m28evk/README
@@ -0,0 +1,13 @@
+Aries M28EVK
+============
+
+Files of the M28/M28EVK port
+----------------------------
+
+arch/arm/cpu/arm926ejs/mxs/	- The CPU support code for the Freescale i.MX28
+arch/arm/include/asm/arch-mxs/	- Header files for the Freescale i.MX28
+board/aries/m28evk/		- M28EVK board specific files
+include/configs/m28evk.h	- M28EVK configuration file
+
+Follow the instructions from doc/README.mxs to generate a bootable SD card or to
+boot from NAND flash.
diff --git a/board/aries/m28evk/m28evk.c b/board/aries/m28evk/m28evk.c
new file mode 100644
index 0000000..c990ea9
--- /dev/null
+++ b/board/aries/m28evk/m28evk.c
@@ -0,0 +1,173 @@
+/*
+ * Aries M28 module
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+	/* IO0 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK0, 480000);
+	/* IO1 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+	/* SSP0 clock at 96MHz */
+	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+	/* SSP2 clock at 160MHz */
+	mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
+
+#ifdef	CONFIG_CMD_USB
+	mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
+	mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 |
+			MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
+	gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0);
+
+	mxs_iomux_setup_pad(MX28_PAD_AUART3_RX__GPIO_3_12 |
+			MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
+	gpio_direction_output(MX28_PAD_AUART3_RX__GPIO_3_12, 0);
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return mxs_dram_init();
+}
+
+#ifdef	CONFIG_CMD_MMC
+static int m28_mmc_wp(int id)
+{
+	if (id != 0) {
+		printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
+		return 1;
+	}
+
+	return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	/* Configure WP as input. */
+	gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
+	/* Turn on the power to the card. */
+	gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
+
+	return mxsmmc_initialize(bis, 0, m28_mmc_wp, NULL);
+}
+#endif
+
+#ifdef	CONFIG_CMD_NET
+
+#define	MII_OPMODE_STRAP_OVERRIDE	0x16
+#define	MII_PHY_CTRL1			0x1e
+#define	MII_PHY_CTRL2			0x1f
+
+int fecmxc_mii_postcall(int phy)
+{
+#if	defined(CONFIG_ARIES_M28_V11) || defined(CONFIG_ARIES_M28_V10)
+	/* KZ8031 PHY on old boards. */
+	const uint32_t freq = 0x0080;
+#else
+	/* KZ8021 PHY on new boards. */
+	const uint32_t freq = 0x0000;
+#endif
+
+	miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
+	miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
+	if (phy == 3)
+		miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8100 | freq);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	struct mxs_clkctrl_regs *clkctrl_regs =
+		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+	struct eth_device *dev;
+	int ret;
+
+	ret = cpu_eth_init(bis);
+	if (ret)
+		return ret;
+
+	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
+		CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
+		CLKCTRL_ENET_TIME_SEL_RMII_CLK);
+
+#if !defined(CONFIG_ARIES_M28_V11) && !defined(CONFIG_ARIES_M28_V10)
+	/* Reset the new PHY */
+	gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0);
+	udelay(10000);
+	gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1);
+	udelay(10000);
+#endif
+
+	ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+	if (ret) {
+		printf("FEC MXS: Unable to init FEC0\n");
+		return ret;
+	}
+
+	ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
+	if (ret) {
+		printf("FEC MXS: Unable to init FEC1\n");
+		return ret;
+	}
+
+	dev = eth_get_dev_by_name("FEC0");
+	if (!dev) {
+		printf("FEC MXS: Unable to get FEC0 device entry\n");
+		return -EINVAL;
+	}
+
+	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+	if (ret) {
+		printf("FEC MXS: Unable to register FEC0 mii postcall\n");
+		return ret;
+	}
+
+	dev = eth_get_dev_by_name("FEC1");
+	if (!dev) {
+		printf("FEC MXS: Unable to get FEC1 device entry\n");
+		return -EINVAL;
+	}
+
+	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+	if (ret) {
+		printf("FEC MXS: Unable to register FEC1 mii postcall\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+#endif
diff --git a/board/aries/m28evk/spl_boot.c b/board/aries/m28evk/spl_boot.c
new file mode 100644
index 0000000..e27a74e
--- /dev/null
+++ b/board/aries/m28evk/spl_boot.c
@@ -0,0 +1,206 @@
+/*
+ * ARIES M28 Boot setup
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define	MUX_CONFIG_LED	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_LCD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_TSC	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_GPMI	(MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+#define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+	/* LED */
+	MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED,
+
+	/* framebuffer */
+	MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
+
+	/* UART1 */
+#ifdef	CONFIG_ARIES_M28_V10
+	MX28_PAD_AUART0_CTS__DUART_RX,
+	MX28_PAD_AUART0_RTS__DUART_TX,
+#else
+	MX28_PAD_PWM0__DUART_RX,
+	MX28_PAD_PWM1__DUART_TX,
+#endif
+	MX28_PAD_AUART0_TX__DUART_RTS,
+	MX28_PAD_AUART0_RX__DUART_CTS,
+
+	/* UART2 */
+	MX28_PAD_AUART1_RX__AUART1_RX,
+	MX28_PAD_AUART1_TX__AUART1_TX,
+	MX28_PAD_AUART1_RTS__AUART1_RTS,
+	MX28_PAD_AUART1_CTS__AUART1_CTS,
+
+	/* CAN */
+	MX28_PAD_GPMI_RDY2__CAN0_TX,
+	MX28_PAD_GPMI_RDY3__CAN0_RX,
+
+	/* TSC2007 */
+	MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_TSC,
+
+	/* MMC0 */
+	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
+		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+	MX28_PAD_SSP0_SCK__SSP0_SCK |
+		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
+	MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0 |
+		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),	/* Power */
+	MX28_PAD_AUART2_CTS__GPIO_3_10,	/* WP */
+
+	/* GPMI NAND */
+	MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RDN__GPMI_RDN |
+		(MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+	MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
+	MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
+
+	/* FEC Ethernet */
+	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
+
+	MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
+	MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
+#if !defined(CONFIG_ARIES_M28_V11) && !defined(CONFIG_ARIES_M28_V10)
+	MX28_PAD_AUART2_RTS__GPIO_3_11,	/* PHY reset */
+#endif
+
+	/* I2C */
+	MX28_PAD_I2C0_SCL__I2C0_SCL,
+	MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+	/* EMI */
+	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+
+	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+	/* SPI2 (for flash) */
+	MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
+	MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
+	MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
+	MX28_PAD_SSP2_SS0__SSP2_D3 |
+		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
+};
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/board/aries/m53evk/Kconfig b/board/aries/m53evk/Kconfig
new file mode 100644
index 0000000..2d49b40
--- /dev/null
+++ b/board/aries/m53evk/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_M53EVK
+
+config SYS_BOARD
+	default "m53evk"
+
+config SYS_VENDOR
+	default "aries"
+
+config SYS_SOC
+	default "mx5"
+
+config SYS_CONFIG_NAME
+	default "m53evk"
+
+endif
diff --git a/board/aries/m53evk/MAINTAINERS b/board/aries/m53evk/MAINTAINERS
new file mode 100644
index 0000000..73a68cf
--- /dev/null
+++ b/board/aries/m53evk/MAINTAINERS
@@ -0,0 +1,6 @@
+M53EVK BOARD
+#M:	Marek Vasut <marek.vasut@gmail.com>
+S:	Orphan (since 2017-07)
+F:	board/aries/m53evk/
+F:	include/configs/m53evk.h
+F:	configs/m53evk_defconfig
diff --git a/board/aries/m53evk/Makefile b/board/aries/m53evk/Makefile
new file mode 100644
index 0000000..daa0fe4
--- /dev/null
+++ b/board/aries/m53evk/Makefile
@@ -0,0 +1,8 @@
+#
+# Aries M53EVK
+# Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= m53evk.o
diff --git a/board/aries/m53evk/imximage.cfg b/board/aries/m53evk/imximage.cfg
new file mode 100644
index 0000000..e4f3ce5
--- /dev/null
+++ b/board/aries/m53evk/imximage.cfg
@@ -0,0 +1,92 @@
+/*
+ * Aries M53 DRAM init values
+ * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/mach-imx/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION	2
+
+
+/* Boot Offset 0x400, valid for both SD and NAND boot. */
+BOOT_OFFSET	FLASH_OFFSET_STANDARD
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x53fa86f4 0x00000000	 /* GRP_DDRMODE_CTL */
+DATA 4 0x53fa8714 0x00000000	 /* GRP_DDRMODE */
+DATA 4 0x53fa86fc 0x00000000	 /* GRP_DDRPKE */
+DATA 4 0x53fa8724 0x04000000	 /* GRP_DDR_TYPE */
+
+DATA 4 0x53fa872c 0x00300000	 /* GRP_B3DS */
+DATA 4 0x53fa8554 0x00300000	 /* DRAM_DQM3 */
+DATA 4 0x53fa8558 0x00300040	 /* DRAM_SDQS3 */
+
+DATA 4 0x53fa8728 0x00300000	 /* GRP_B2DS */
+DATA 4 0x53fa8560 0x00300000	 /* DRAM_DQM2 */
+DATA 4 0x53fa8568 0x00300040	 /* DRAM_SDQS2 */
+
+DATA 4 0x53fa871c 0x00300000	 /* GRP_B1DS */
+DATA 4 0x53fa8594 0x00300000	 /* DRAM_DQM1 */
+DATA 4 0x53fa8590 0x00300040	 /* DRAM_SDQS1 */
+
+DATA 4 0x53fa8718 0x00300000	 /* GRP_B0DS */
+DATA 4 0x53fa8584 0x00300000	 /* DRAM_DQM0 */
+DATA 4 0x53fa857c 0x00300040	 /* DRAM_SDQS0 */
+
+DATA 4 0x53fa8578 0x00300000	 /* DRAM_SDCLK_0 */
+DATA 4 0x53fa8570 0x00300000	 /* DRAM_SDCLK_1 */
+
+DATA 4 0x53fa8574 0x00300000	 /* DRAM_CAS */
+DATA 4 0x53fa8588 0x00300000	 /* DRAM_RAS */
+DATA 4 0x53fa86f0 0x00300000	 /* GRP_ADDDS */
+DATA 4 0x53fa8720 0x00300000	 /* GRP_CTLDS */
+
+DATA 4 0x53fa8564 0x00300040	 /* DRAM_SDODT1 */
+DATA 4 0x53fa8580 0x00300040	 /* DRAM_SDODT0 */
+
+/* ESDCTL */
+DATA 4 0x63fd9088 0x32383535
+DATA 4 0x63fd9090 0x40383538
+DATA 4 0x63fd907c 0x0136014d
+DATA 4 0x63fd9080 0x01510141
+
+DATA 4 0x63fd9018 0x00011740
+DATA 4 0x63fd9000 0xc3190000
+DATA 4 0x63fd900c 0x555952e3
+DATA 4 0x63fd9010 0xb68e8b63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f0e21
+DATA 4 0x63fd9008 0x12273030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x092080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x09208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00001800
+DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x63fd9058 0x00022227
+DATA 4 0x63fd901c 0x00000000
diff --git a/board/aries/m53evk/m53evk.c b/board/aries/m53evk/m53evk.c
new file mode 100644
index 0000000..ece8957
--- /dev/null
+++ b/board/aries/m53evk/m53evk.c
@@ -0,0 +1,404 @@
+/*
+ * Aries M53 module
+ *
+ * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/mach-imx/mx5_video.h>
+#include <asm/spl.h>
+#include <linux/errno.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <spl.h>
+#include <fsl_esdhc.h>
+#include <asm/gpio.h>
+#include <usb/ehci-ci.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+/* Special MXCFB sync flags are here. */
+#include "../drivers/video/mxcfb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uint32_t mx53_dram_size[2];
+
+phys_size_t get_effective_memsize(void)
+{
+	/*
+	 * WARNING: We must override get_effective_memsize() function here
+	 * to report only the size of the first DRAM bank. This is to make
+	 * U-Boot relocator place U-Boot into valid memory, that is, at the
+	 * end of the first DRAM bank. If we did not override this function
+	 * like so, U-Boot would be placed at the address of the first DRAM
+	 * bank + total DRAM size - sizeof(uboot), which in the setup where
+	 * each DRAM bank contains 512MiB of DRAM would result in placing
+	 * U-Boot into invalid memory area close to the end of the first
+	 * DRAM bank.
+	 */
+	return mx53_dram_size[0];
+}
+
+int dram_init(void)
+{
+	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
+
+	gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = mx53_dram_size[0];
+
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = mx53_dram_size[1];
+
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	static const iomux_v3_cfg_t uart_pads[] = {
+		MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
+		MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX5
+int board_ehci_hcd_init(int port)
+{
+	if (port == 0) {
+		/* USB OTG PWRON */
+		imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
+					PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
+		gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
+
+		/* USB OTG Over Current */
+		imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
+	} else if (port == 1) {
+		/* USB Host PWRON */
+		imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
+					PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
+		gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
+
+		/* USB Host Over Current */
+		imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
+	}
+
+	return 0;
+}
+#endif
+
+static void setup_iomux_fec(void)
+{
+	static const iomux_v3_cfg_t fec_pads[] = {
+		/* MDIO pads */
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+
+		/* FEC 0 pads */
+		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+
+		/* FEC 1 pads */
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
+				PAD_CTL_HYS | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg = {
+	MMC_SDHC1_BASE_ADDR,
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
+	gpio_direction_input(IMX_GPIO_NR(1, 1));
+
+	return !gpio_get_value(IMX_GPIO_NR(1, 1));
+}
+
+#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+		MX53_PAD_EIM_DA13__GPIO3_13,
+
+		MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */
+	};
+
+	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
+
+	/* GPIO 2_31 is SD power */
+	gpio_direction_output(IMX_GPIO_NR(2, 31), 0);
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+#endif
+
+#ifdef CONFIG_VIDEO
+static struct fb_videomode const ampire_wvga = {
+	.name		= "Ampire",
+	.refresh	= 60,
+	.xres		= 800,
+	.yres		= 480,
+	.pixclock	= 29851, /* picosecond (33.5 MHz) */
+	.left_margin	= 89,
+	.right_margin	= 164,
+	.upper_margin	= 23,
+	.lower_margin	= 10,
+	.hsync_len	= 10,
+	.vsync_len	= 10,
+	.sync		= FB_SYNC_CLK_LAT_FALL,
+};
+
+int board_video_skip(void)
+{
+	int ret;
+	ret = ipuv3_fb_init(&ampire_wvga, 1, IPU_PIX_FMT_RGB666);
+	if (ret)
+		printf("Ampire LCD cannot be configured: %d\n", ret);
+	return ret;
+}
+#endif
+
+#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+static void setup_iomux_i2c(void)
+{
+	static const iomux_v3_cfg_t i2c_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
+}
+
+static void setup_iomux_video(void)
+{
+	static const iomux_v3_cfg_t lcd_pads[] = {
+		MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0,
+		MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1,
+		MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2,
+		MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3,
+		MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4,
+		MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5,
+		MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6,
+		MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7,
+		MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8,
+		MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9,
+		MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10,
+		MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11,
+		MX53_PAD_EIM_A17__IPU_DISP1_DAT_12,
+		MX53_PAD_EIM_A18__IPU_DISP1_DAT_13,
+		MX53_PAD_EIM_A19__IPU_DISP1_DAT_14,
+		MX53_PAD_EIM_A20__IPU_DISP1_DAT_15,
+		MX53_PAD_EIM_A21__IPU_DISP1_DAT_16,
+		MX53_PAD_EIM_A22__IPU_DISP1_DAT_17,
+		MX53_PAD_EIM_A23__IPU_DISP1_DAT_18,
+		MX53_PAD_EIM_A24__IPU_DISP1_DAT_19,
+		MX53_PAD_EIM_D31__IPU_DISP1_DAT_20,
+		MX53_PAD_EIM_D30__IPU_DISP1_DAT_21,
+		MX53_PAD_EIM_D26__IPU_DISP1_DAT_22,
+		MX53_PAD_EIM_D27__IPU_DISP1_DAT_23,
+		MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK,
+		MX53_PAD_EIM_DA13__IPU_DI1_D0_CS,
+		MX53_PAD_EIM_DA14__IPU_DI1_D1_CS,
+		MX53_PAD_EIM_DA15__IPU_DI1_PIN1,
+		MX53_PAD_EIM_DA11__IPU_DI1_PIN2,
+		MX53_PAD_EIM_DA12__IPU_DI1_PIN3,
+		MX53_PAD_EIM_A25__IPU_DI1_PIN12,
+		MX53_PAD_EIM_DA10__IPU_DI1_PIN15,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+}
+
+static void setup_iomux_nand(void)
+{
+	static const iomux_v3_cfg_t nand_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
+				PAD_CTL_PUS_100K_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
+				PAD_CTL_PUS_100K_UP),
+		NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
+				PAD_CTL_DSE_HIGH),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
+				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
+				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
+				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
+				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
+				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
+				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
+				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+		NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
+				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
+	};
+
+	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+}
+
+static void m53_set_clock(void)
+{
+	int ret;
+	const uint32_t ref_clk = MXC_HCLK;
+	const uint32_t dramclk = 400;
+	uint32_t cpuclk;
+
+	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
+					    PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
+	gpio_direction_input(IMX_GPIO_NR(4, 0));
+
+	/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
+	cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
+
+	ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
+	if (ret)
+		printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);
+
+	ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
+	if (ret) {
+		printf("CPU:   Switch peripheral clock to %dMHz failed\n",
+			dramclk);
+	}
+
+	ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
+	if (ret)
+		printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
+}
+
+static void m53_set_nand(void)
+{
+	u32 i;
+
+	/* NAND flash is muxed on ATA pins */
+	setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
+
+	/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
+	for (i = 0x4; i < 0x94; i += 0x18) {
+		clrbits_le32(WEIM_BASE_ADDR + i,
+			     WEIM_GCR2_MUX16_BYP_GRANT_MASK);
+	}
+
+	mxc_set_clock(0, 33, MXC_NFC_CLK);
+	enable_nfc_clk(1);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	setup_iomux_fec();
+	setup_iomux_i2c();
+	setup_iomux_nand();
+	setup_iomux_video();
+
+	m53_set_clock();
+
+	mxc_set_sata_internal_clock();
+
+	/* NAND clock @ 33MHz */
+	m53_set_nand();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Aries M53EVK\n");
+
+	return 0;
+}
+
+/*
+ * NAND SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+	setup_iomux_nand();
+	m53_set_clock();
+	m53_set_nand();
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NAND;
+}
+#endif
diff --git a/board/aries/ma5d4evk/Kconfig b/board/aries/ma5d4evk/Kconfig
new file mode 100644
index 0000000..56b4f4a
--- /dev/null
+++ b/board/aries/ma5d4evk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MA5D4EVK
+
+config SYS_BOARD
+	default "ma5d4evk"
+
+config SYS_VENDOR
+	default "aries"
+
+config SYS_CONFIG_NAME
+	default "ma5d4evk"
+
+endif
diff --git a/board/aries/ma5d4evk/MAINTAINERS b/board/aries/ma5d4evk/MAINTAINERS
new file mode 100644
index 0000000..a2fab52
--- /dev/null
+++ b/board/aries/ma5d4evk/MAINTAINERS
@@ -0,0 +1,6 @@
+Aries MA5D4EVK BOARD
+#M:	Marek Vasut <marek.vasut@gmail.com>
+S:	Orphan (since 2017-07)
+F:	board/aries/ma5d4evk/
+F:	include/configs/ma5d4evk.h
+F:	configs/ma5d4evk_defconfig
diff --git a/board/denx/ma5d4evk/Makefile b/board/aries/ma5d4evk/Makefile
index b12b5dc..b12b5dc 100644
--- a/board/denx/ma5d4evk/Makefile
+++ b/board/aries/ma5d4evk/Makefile
diff --git a/board/aries/ma5d4evk/ma5d4evk.c b/board/aries/ma5d4evk/ma5d4evk.c
new file mode 100644
index 0000000..b9294fc
--- /dev/null
+++ b/board/aries/ma5d4evk/ma5d4evk.c
@@ -0,0 +1,456 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_usba_udc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/sama5d3_smc.h>
+#include <asm/arch/sama5d4.h>
+#include <atmel_hlcdc.h>
+#include <atmel_mci.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <spl.h>
+#include <version.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u8 boot_mode_sf;
+
+#ifdef CONFIG_ATMEL_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
+}
+
+static void ma5d4evk_spi0_hw_init(void)
+{
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* SPI0_MISO */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* SPI0_MOSI */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* SPI0_SPCK */
+
+	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);	/* SPI0_CS0 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+#ifdef CONFIG_CMD_USB
+static void ma5d4evk_usb_hw_init(void)
+{
+	at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
+	at91_set_pio_output(AT91_PIO_PORTE, 14, 0);
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	.vl_col			= 800,
+	.vl_row			= 480,
+	.vl_clk			= 33500000,
+	.vl_bpix		= LCD_BPP,
+	.vl_tft			= 1,
+	.vl_hsync_len		= 10,
+	.vl_left_margin		= 89,
+	.vl_right_margin	= 164,
+	.vl_vsync_len		= 10,
+	.vl_upper_margin	= 23,
+	.vl_lower_margin	= 10,
+	.mmio			= ATMEL_BASE_LCDC,
+};
+
+/* No power up/down pin for the LCD pannel */
+void lcd_enable(void)	{ /* Empty! */ }
+void lcd_disable(void)	{ /* Empty! */ }
+
+unsigned int has_lcdc(void)
+{
+	return 1;
+}
+
+static void ma5d4evk_lcd_hw_init(void)
+{
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 1);	/* LCDPWM */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0);	/* LCDDISP */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0);	/* LCDVSYNC */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* LCDHSYNC */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0);	/* LCDDOTCK */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 1);	/* LCDDEN */
+
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  0, 0);	/* LCDD0 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  1, 0);	/* LCDD1 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  2, 0);	/* LCDD2 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  3, 0);	/* LCDD3 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  4, 0);	/* LCDD4 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  5, 0);	/* LCDD5 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  6, 0);	/* LCDD6 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  7, 0);	/* LCDD7 */
+
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  8, 0);	/* LCDD9 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  9, 0);	/* LCDD8 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* LCDD10 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* LCDD11 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* LCDD12 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* LCDD13 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* LCDD14 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* LCDD15 */
+
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* LCDD16 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* LCDD17 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* LCDD18 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* LCDD19 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* LCDD20 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0);	/* LCDD21 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0);	/* LCDD22 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0);	/* LCDD23 */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+
+#endif /* CONFIG_LCD */
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+/* On-SoM eMMC */
+void ma5d4evk_mci0_hw_init(void)
+{
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 5, 1);	/* MCI1 CDA */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 6, 1);	/* MCI1 DA0 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 7, 1);	/* MCI1 DA1 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 8, 1);	/* MCI1 DA2 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 9, 1);	/* MCI1 DA3 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 10, 1);	/* MCI1 DA4 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 11, 1);	/* MCI1 DA5 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 12, 1);	/* MCI1 DA6 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 13, 1);	/* MCI1 DA7 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 4, 0);	/* MCI1 CLK */
+
+	/*
+	 * As the mci io internal pull down is too strong, so if the io needs
+	 * external pull up, the pull up resistor will be very small, if so
+	 * the power consumption will increase, so disable the internal pull
+	 * down to save the power.
+	 */
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_MCI0);
+}
+
+/* On-board MicroSD slot */
+void ma5d4evk_mci1_hw_init(void)
+{
+	at91_pio3_set_c_periph(AT91_PIO_PORTE, 19, 1);	/* MCI1 CDA */
+	at91_pio3_set_c_periph(AT91_PIO_PORTE, 20, 1);	/* MCI1 DA0 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTE, 21, 1);	/* MCI1 DA1 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTE, 22, 1);	/* MCI1 DA2 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTE, 23, 1);	/* MCI1 DA3 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTE, 18, 0);	/* MCI1 CLK */
+
+	/*
+	 * As the mci io internal pull down is too strong, so if the io needs
+	 * external pull up, the pull up resistor will be very small, if so
+	 * the power consumption will increase, so disable the internal pull
+	 * down to save the power.
+	 */
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
+
+	/* Deal with WP pin on the microSD slot. */
+	at91_set_pio_output(AT91_PIO_PORTE, 16, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 16, 1);
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_MCI1);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+	void *mci0 = (void *)ATMEL_BASE_MCI0;
+	void *mci1 = (void *)ATMEL_BASE_MCI1;
+
+	/* De-assert reset on On-SoM eMMC */
+	at91_set_pio_output(AT91_PIO_PORTE, 15, 1);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTE, 15, 0);
+
+	ret = atmel_mci_init(boot_mode_sf ? mci0 : mci1);
+	if (ret)	/* eMMC init failed, skip it. */
+		at91_set_pio_output(AT91_PIO_PORTE, 15, 0);
+
+	/* Enable the power supply to On-board MicroSD */
+	at91_set_pio_output(AT91_PIO_PORTE, 17, 0);
+	ret = atmel_mci_init(boot_mode_sf ? mci1 : mci0);
+	if (ret)	/* uSD init failed, power it down. */
+		at91_set_pio_output(AT91_PIO_PORTE, 17, 1);
+
+	return 0;
+}
+#endif /* CONFIG_GENERIC_ATMEL_MCI */
+
+#ifdef CONFIG_MACB
+void ma5d4evk_macb0_hw_init(void)
+{
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* ETXCK_EREFCK */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* ERXDV */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* ERX0 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* ERX1 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* ERXER */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* ETXEN */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* ETX0 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* ETX1 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* EMDIO */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* EMDC */
+
+	/* Enable clock */
+	at91_periph_clk_enable(ATMEL_ID_GMAC0);
+}
+#endif
+
+static void ma5d4evk_serial_hw_init(void)
+{
+	/* USART0 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);	/* TXD */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 0);	/* RXD */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 0);	/* RTS */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 0);	/* CTS */
+	at91_periph_clk_enable(ATMEL_ID_USART0);
+
+	/* USART1 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 17, 1);	/* TXD */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 16, 0);	/* RXD */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 15, 0);	/* RTS */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 14, 0);	/* CTS */
+	at91_periph_clk_enable(ATMEL_ID_USART1);
+}
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+	at91_periph_clk_enable(ATMEL_ID_PIOE);
+
+	/* Configure LEDs as OFF */
+	at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
+	at91_set_pio_output(AT91_PIO_PORTD, 29, 0);
+	at91_set_pio_output(AT91_PIO_PORTD, 30, 0);
+
+	ma5d4evk_serial_hw_init();
+
+	return 0;
+}
+
+static void board_identify(void)
+{
+	struct spi_flash *sf;
+	sf = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
+			     CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
+	boot_mode_sf = (sf != NULL);
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_ATMEL_SPI
+	ma5d4evk_spi0_hw_init();
+#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+	ma5d4evk_mci0_hw_init();
+	ma5d4evk_mci1_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	ma5d4evk_macb0_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	ma5d4evk_lcd_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	ma5d4evk_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	at91_udp_hw_init();
+#endif
+
+	board_identify();
+
+	/* Reset CAN controllers */
+	at91_set_pio_output(AT91_PIO_PORTB, 21, 0);
+	udelay(100);
+	at91_set_pio_output(AT91_PIO_PORTB, 21, 1);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTB, 21, 0);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("bootmode", boot_mode_sf ? "sf" : "emmc");
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
+#endif
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+	usb_eth_initialize(bis);
+#endif
+#endif
+
+	return rc;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_ATMEL_SPI
+	ma5d4evk_spi0_hw_init();
+#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+	ma5d4evk_mci0_hw_init();
+	ma5d4evk_mci1_hw_init();
+#endif
+	board_identify();
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = spl_boot_device();
+
+	switch (spl_boot_list[0]) {
+	case BOOT_DEVICE_MMC1:
+	case BOOT_DEVICE_MMC2:
+		spl_boot_list[0] = BOOT_DEVICE_MMC1;
+		break;
+	case BOOT_DEVICE_SPI:
+		break;
+	case BOOT_DEVICE_USB:
+		spl_boot_list[0] = BOOT_DEVICE_MMC2;
+		break;
+	}
+}
+
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_13 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+	ddr2->rtr = 0x2b0;
+
+	ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct atmel_mpddrc_config ddr2;
+
+	ddr2_conf(&ddr2);
+
+	/* enable MPDDR clock */
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	writel(AT91_PMC_DDR, &pmc->scer);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	u32 tmp;
+
+	tmp = AT91_PMC_PLLAR_29 |
+	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+	      AT91_PMC_PLLXR_MUL(87) |
+	      AT91_PMC_PLLXR_DIV(1);
+	at91_plla_init(tmp);
+
+	writel(0x0 << 8, &pmc->pllicpr);
+
+	tmp = AT91_PMC_MCKR_H32MXDIV |
+	      AT91_PMC_MCKR_PLLADIV_2 |
+	      AT91_PMC_MCKR_MDIV_3 |
+	      AT91_PMC_MCKR_CSS_PLLA;
+	at91_mck_init(tmp);
+}
+#endif
diff --git a/board/aries/mcvevk/MAINTAINERS b/board/aries/mcvevk/MAINTAINERS
new file mode 100644
index 0000000..0b719a1
--- /dev/null
+++ b/board/aries/mcvevk/MAINTAINERS
@@ -0,0 +1,5 @@
+Aries MCVEVK BOARD
+#M:	Marek Vasut <marek.vasut@gmail.com>
+S:	Orphan (since 2017-07)
+F:	include/configs/socfpga_mcvevk.h
+F:	configs/socfpga_mcvevk_defconfig
diff --git a/board/denx/mcvevk/Makefile b/board/aries/mcvevk/Makefile
index 86f9b78..86f9b78 100644
--- a/board/denx/mcvevk/Makefile
+++ b/board/aries/mcvevk/Makefile
diff --git a/board/denx/mcvevk/qts/iocsr_config.h b/board/aries/mcvevk/qts/iocsr_config.h
index 3021830..3021830 100644
--- a/board/denx/mcvevk/qts/iocsr_config.h
+++ b/board/aries/mcvevk/qts/iocsr_config.h
diff --git a/board/denx/mcvevk/qts/pinmux_config.h b/board/aries/mcvevk/qts/pinmux_config.h
index ea2f7ab..ea2f7ab 100644
--- a/board/denx/mcvevk/qts/pinmux_config.h
+++ b/board/aries/mcvevk/qts/pinmux_config.h
diff --git a/board/denx/mcvevk/qts/pll_config.h b/board/aries/mcvevk/qts/pll_config.h
index b718b39..b718b39 100644
--- a/board/denx/mcvevk/qts/pll_config.h
+++ b/board/aries/mcvevk/qts/pll_config.h
diff --git a/board/aries/mcvevk/qts/sdram_config.h b/board/aries/mcvevk/qts/sdram_config.h
new file mode 100644
index 0000000..ff64f55
--- /dev/null
+++ b/board/aries/mcvevk/qts/sdram_config.h
@@ -0,0 +1,344 @@
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			140
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		1560
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64	0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x49
+#define RW_MGR_GUARANTEED_READ	0x4C
+#define RW_MGR_GUARANTEED_READ_CONT	0x54
+#define RW_MGR_GUARANTEED_WRITE	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7B
+#define RW_MGR_IDLE_LOOP2	0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0	0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x59
+#define RW_MGR_READ_B2B_WAIT1	0x61
+#define RW_MGR_READ_B2B_WAIT2	0x6B
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7D
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	7
+#define CALIB_VFIFO_OFFSET	5
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	312
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x55550496
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	4
+#define RW_MGR_MEM_DATA_WIDTH	32
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
+#define TINIT_CNTR0_VAL	99
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	99
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080421,
+	0x10080520,
+	0x10090044,
+	0x100a0008,
+	0x100b0000,
+	0x10380400,
+	0x10080441,
+	0x100804c0,
+	0x100a0024,
+	0x10090010,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/denx/mcvevk/socfpga.c b/board/aries/mcvevk/socfpga.c
index 6be58f0..6be58f0 100644
--- a/board/denx/mcvevk/socfpga.c
+++ b/board/aries/mcvevk/socfpga.c
diff --git a/board/aristainetos/aristainetos-v1.c b/board/aristainetos/aristainetos-v1.c
index b8fed2e..b3f5c99 100644
--- a/board/aristainetos/aristainetos-v1.c
+++ b/board/aristainetos/aristainetos-v1.c
@@ -14,12 +14,12 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
diff --git a/board/aristainetos/aristainetos-v2.c b/board/aristainetos/aristainetos-v2.c
index fa4b4d2..6abc215 100644
--- a/board/aristainetos/aristainetos-v2.c
+++ b/board/aristainetos/aristainetos-v2.c
@@ -14,12 +14,12 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index d1e6850..872fedd 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -14,12 +14,12 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
index 30e720d..1abfe88 100644
--- a/board/armadeus/apf27/apf27.c
+++ b/board/armadeus/apf27/apf27.c
@@ -16,7 +16,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/gpio.h>
 #include <asm/gpio.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include "apf27.h"
 #include "crc.h"
 #include "fpga.h"
@@ -119,7 +119,7 @@ static int apf27_devices_init(void)
 	mx27_fec_init_pins();
 #endif
 
-#ifdef CONFIG_MXC_MMC
+#ifdef CONFIG_MMC_MXC
 	mx27_sd2_init_pins();
 	imx_gpio_mode((GPIO_PORTF | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 16));
 	gpio_request(PC_PWRON, "pc_pwron");
@@ -193,7 +193,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size  = get_ram_size((void *)PHYS_SDRAM_1,
@@ -204,6 +204,8 @@ void dram_init_banksize(void)
 					     PHYS_SDRAM_2_SIZE);
 	else
 		gd->bd->bi_dram[1].size = 0;
+
+	return 0;
 }
 
 ulong board_get_usable_ram_top(ulong total_size)
diff --git a/board/armadeus/opos6uldev/Kconfig b/board/armadeus/opos6uldev/Kconfig
new file mode 100644
index 0000000..e66f060
--- /dev/null
+++ b/board/armadeus/opos6uldev/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_OPOS6ULDEV
+
+config SYS_BOARD
+	default "opos6uldev"
+
+config SYS_VENDOR
+	default "armadeus"
+
+config SYS_CONFIG_NAME
+	default "opos6uldev"
+
+config IMX_CONFIG
+	default "arch/arm/mach-imx/spl_sd.cfg"
+
+endif
diff --git a/board/armadeus/opos6uldev/MAINTAINERS b/board/armadeus/opos6uldev/MAINTAINERS
new file mode 100644
index 0000000..e46c669
--- /dev/null
+++ b/board/armadeus/opos6uldev/MAINTAINERS
@@ -0,0 +1,6 @@
+OPOS6ULDev BOARD
+M:	Sébastien Szymanski <sebastien.szymanski@armadeus.com>
+S:	Maintained
+F:	board/armadeus/opos6uldev/
+F:	include/configs/opos6uldev.h
+F:	configs/opos6uldev_defconfig
diff --git a/board/armadeus/opos6uldev/Makefile b/board/armadeus/opos6uldev/Makefile
new file mode 100644
index 0000000..fd14fd7
--- /dev/null
+++ b/board/armadeus/opos6uldev/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2017 Armadeus Systems
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := board.o
diff --git a/board/armadeus/opos6uldev/board.c b/board/armadeus/opos6uldev/board.c
new file mode 100644
index 0000000..646094a
--- /dev/null
+++ b/board/armadeus/opos6uldev/board.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2017 Armadeus Systems
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/opos6ul.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/io.h>
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_VIDEO_MXS
+#define LCD_PAD_CTRL ( \
+	PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm \
+)
+
+static iomux_v3_cfg_t const lcd_pads[] = {
+	MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+
+	MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+int setup_lcd(void)
+{
+	struct gpio_desc backlight;
+	int ret;
+
+	enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
+
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+	/* Set Brightness to high */
+	ret = dm_gpio_lookup_name("GPIO4_10", &backlight);
+	if (ret) {
+		printf("Cannot get GPIO4_10\n");
+		return ret;
+	}
+
+	ret = dm_gpio_request(&backlight, "backlight");
+	if (ret) {
+		printf("Cannot request GPIO4_10\n");
+		return ret;
+	}
+
+	dm_gpio_set_dir_flags(&backlight, GPIOD_IS_OUT);
+	dm_gpio_set_value(&backlight, 1);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+#endif
+
+int opos6ul_board_late_init(void)
+{
+#ifdef CONFIG_VIDEO_MXS
+	setup_lcd();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#define UART_PAD_CTRL (						\
+	PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST			\
+)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+void opos6ul_setup_uart_debug(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c
index cbe7061..c3bafd4 100644
--- a/board/armltd/integrator/integrator.c
+++ b/board/armltd/integrator/integrator.c
@@ -18,12 +18,13 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <netdev.h>
 #include <asm/io.h>
-#include <dm/platdata.h>
 #include <dm/platform_data/serial_pl01x.h>
 #include "arm-ebi.h"
 #include "integrator-sc.h"
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c
index d3b3b31..89ab8f7 100644
--- a/board/armltd/vexpress/vexpress_common.c
+++ b/board/armltd/vexpress/vexpress_common.c
@@ -21,6 +21,7 @@
 #include <errno.h>
 #include <netdev.h>
 #include <asm/io.h>
+#include <asm/mach-types.h>
 #include <asm/arch/systimer.h>
 #include <asm/arch/sysctrl.h>
 #include <asm/arch/wdt.h>
@@ -109,7 +110,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size =
@@ -117,6 +118,8 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size =
 			get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+
+	return 0;
 }
 
 /*
diff --git a/board/armltd/vexpress/vexpress_tc2.c b/board/armltd/vexpress/vexpress_tc2.c
index ebb41a8..c7adf95 100644
--- a/board/armltd/vexpress/vexpress_tc2.c
+++ b/board/armltd/vexpress/vexpress_tc2.c
@@ -7,7 +7,11 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <asm/armv7.h>
 #include <asm/io.h>
+#include <asm/u-boot.h>
+#include <common.h>
+#include <libfdt.h>
 
 #define SCC_BASE	0x7fff0000
 
@@ -31,3 +35,51 @@ bool armv7_boot_nonsec_default(void)
 	return (readl((u32 *)(SCC_BASE + 0x700)) & ((1 << 12) | (1 << 13))) == 0;
 #endif
 }
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *fdt, bd_t *bd)
+{
+	int offset, tmp, len;
+	const struct fdt_property *prop;
+	const char *cci_compatible = "arm,cci-400-ctrl-if";
+
+#ifdef CONFIG_ARMV7_NONSEC
+	if (!armv7_boot_nonsec())
+		return 0;
+#else
+	return 0;
+#endif
+	/* Booting in nonsec mode, disable CCI access */
+	offset = fdt_path_offset(fdt, "/cpus");
+	if (offset < 0) {
+		printf("couldn't find /cpus\n");
+		return offset;
+	}
+
+	/* delete cci-control-port in each cpu node */
+	for (tmp = fdt_first_subnode(fdt, offset); tmp >= 0;
+	     tmp = fdt_next_subnode(fdt, tmp))
+		fdt_delprop(fdt, tmp, "cci-control-port");
+
+	/* disable all ace cci slave ports */
+	offset = fdt_node_offset_by_prop_value(fdt, offset, "compatible",
+					       cci_compatible, 20);
+	while (offset > 0) {
+		prop = fdt_get_property(fdt, offset, "interface-type",
+					&len);
+		if (!prop)
+			continue;
+		if (len < 4)
+			continue;
+		if (strcmp(prop->data, "ace"))
+			continue;
+
+		fdt_setprop_string(fdt, offset, "status", "disabled");
+
+		offset = fdt_node_offset_by_prop_value(fdt, offset, "compatible",
+						       cci_compatible, 20);
+	}
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c
index b3fb09c..0608a5a 100644
--- a/board/armltd/vexpress64/pcie.c
+++ b/board/armltd/vexpress64/pcie.c
@@ -123,7 +123,7 @@ void xr3pci_setup_atr(void)
 	base += XR3PCI_ATR_TABLE_SIZE;
 
 	/* setup IO space translation */
-	xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, XR3_PCI_IOSPACE_START,
+	xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, 0,
 			     XR3_PCI_IOSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_IO);
 
 	base += XR3PCI_ATR_TABLE_SIZE;
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index e34af6c..26e22c4 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -6,12 +6,12 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <dm.h>
 #include <malloc.h>
 #include <errno.h>
 #include <netdev.h>
 #include <asm/io.h>
 #include <linux/compiler.h>
-#include <dm/platdata.h>
 #include <dm/platform_data/serial_pl01x.h>
 #include "pcie.h"
 #include <asm/armv8/mmu.h>
@@ -70,7 +70,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
@@ -78,6 +78,8 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 #endif
+
+	return 0;
 }
 
 /*
diff --git a/board/aspeed/evb_ast2500/Kconfig b/board/aspeed/evb_ast2500/Kconfig
new file mode 100644
index 0000000..73a8ae8
--- /dev/null
+++ b/board/aspeed/evb_ast2500/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_EVB_AST2500
+
+config SYS_BOARD
+	default "evb_ast2500"
+
+config SYS_VENDOR
+	default "aspeed"
+
+config SYS_CONFIG_NAME
+	default "evb_ast2500"
+
+endif
diff --git a/board/aspeed/evb_ast2500/Makefile b/board/aspeed/evb_ast2500/Makefile
new file mode 100644
index 0000000..4564098
--- /dev/null
+++ b/board/aspeed/evb_ast2500/Makefile
@@ -0,0 +1 @@
+obj-y += evb_ast2500.o
diff --git a/board/aspeed/evb_ast2500/evb_ast2500.c b/board/aspeed/evb_ast2500/evb_ast2500.c
new file mode 100644
index 0000000..649e3ba
--- /dev/null
+++ b/board/aspeed/evb_ast2500/evb_ast2500.c
@@ -0,0 +1,6 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c
index 7ec7cb3..d011ae5 100644
--- a/board/astro/mcf5373l/mcf5373l.c
+++ b/board/astro/mcf5373l/mcf5373l.c
@@ -27,7 +27,7 @@ int checkboard(void)
 	return 0;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
 	sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
@@ -79,8 +79,10 @@ phys_size_t initdram(int board_type)
 	 * (Do not rely on the SDCS register(s) being set to 0x00000000
 	 * during reset as stated in the data sheet.)
 	 */
-	return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 				0x80000000 - CONFIG_SYS_SDRAM_BASE);
+
+	return 0;
 }
 
 #define UART_BASE MMAP_UART0
diff --git a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c
index 28e6111..abe69ab 100644
--- a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c
+++ b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c
@@ -272,7 +272,7 @@ DECLARE_GLOBAL_DATA_PTR;
 int board_init(void)
 {
 	/* board id for linux */
-	gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO_800EVA;
+	gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO800EVA;
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100;
 
diff --git a/board/atmel/at91rm9200ek/at91rm9200ek.c b/board/atmel/at91rm9200ek/at91rm9200ek.c
index 98d76a6..36f147b 100644
--- a/board/atmel/at91rm9200ek/at91rm9200ek.c
+++ b/board/atmel/at91rm9200ek/at91rm9200ek.c
@@ -12,6 +12,7 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <asm/mach-types.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pio.h>
 #include <asm/arch/at91_common.h>
diff --git a/board/atmel/at91sam9260ek/Makefile b/board/atmel/at91sam9260ek/Makefile
index c6edbee..07c6184 100644
--- a/board/atmel/at91sam9260ek/Makefile
+++ b/board/atmel/at91sam9260ek/Makefile
@@ -10,5 +10,5 @@
 #
 
 obj-y	+= at91sam9260ek.o
-obj-y	+= led.o
+obj-$(CONFIG_AT91_LED) += led.o
 obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
index 98193bf..d3ce947 100644
--- a/board/atmel/at91sam9260ek/at91sam9260ek.c
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -7,18 +7,13 @@
  */
 
 #include <common.h>
+#include <debug_uart.h>
 #include <asm/io.h>
 #include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
-#include <atmel_mci.h>
-
-#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
-# include <net.h>
-#endif
-#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -67,82 +62,31 @@ static void at91sam9260ek_nand_hw_init(void)
 }
 #endif
 
-#ifdef CONFIG_MACB
-static void at91sam9260ek_macb_hw_init(void)
-{
-	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-
-	at91_periph_clk_enable(ATMEL_ID_EMAC0);
-
-	/*
-	 * Disable pull-up on:
-	 *	RXDV (PA17) => PHY normal mode (not Test mode)
-	 *	ERX0 (PA14) => PHY ADDR0
-	 *	ERX1 (PA15) => PHY ADDR1
-	 *	ERX2 (PA25) => PHY ADDR2
-	 *	ERX3 (PA26) => PHY ADDR3
-	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
-	 *
-	 * PHY has internal pull-down
-	 */
-	writel(pin_to_mask(AT91_PIN_PA14) |
-		pin_to_mask(AT91_PIN_PA15) |
-		pin_to_mask(AT91_PIN_PA17) |
-		pin_to_mask(AT91_PIN_PA25) |
-		pin_to_mask(AT91_PIN_PA26) |
-		pin_to_mask(AT91_PIN_PA28),
-		&pioa->pudr);
-
-	at91_phy_reset();
-
-	/* Re-enable pull-up */
-	writel(pin_to_mask(AT91_PIN_PA14) |
-		pin_to_mask(AT91_PIN_PA15) |
-		pin_to_mask(AT91_PIN_PA17) |
-		pin_to_mask(AT91_PIN_PA25) |
-		pin_to_mask(AT91_PIN_PA26) |
-		pin_to_mask(AT91_PIN_PA28),
-		&pioa->puer);
-
-	/* Initialize EMAC=MACB hardware */
-	at91_macb_hw_init();
-}
-#endif
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(bd_t *bd)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
 {
-	at91_mci_hw_init();
-
-	return atmel_mci_init((void *)ATMEL_BASE_MCI);
+	at91_seriald_hw_init();
 }
 #endif
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-	at91_periph_clk_enable(ATMEL_ID_PIOA);
-	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	at91_periph_clk_enable(ATMEL_ID_PIOC);
-
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
 	return 0;
 }
+#endif
 
 int board_init(void)
 {
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-	at91_seriald_hw_init();
 #ifdef CONFIG_CMD_NAND
 	at91sam9260ek_nand_hw_init();
 #endif
-#ifdef CONFIG_HAS_DATAFLASH
-	at91_spi0_hw_init((1 << 0) | (1 << 1));
-#endif
-#ifdef CONFIG_MACB
-	at91sam9260ek_macb_hw_init();
-#endif
-
 	return 0;
 }
 
@@ -159,12 +103,3 @@ void reset_phy(void)
 {
 }
 #endif
-
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_MACB
-	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
-#endif
-	return rc;
-}
diff --git a/board/atmel/at91sam9261ek/Makefile b/board/atmel/at91sam9261ek/Makefile
index c547fed..d7ba153 100644
--- a/board/atmel/at91sam9261ek/Makefile
+++ b/board/atmel/at91sam9261ek/Makefile
@@ -10,5 +10,5 @@
 #
 
 obj-y += at91sam9261ek.o
-obj-y += led.o
+obj-$(CONFIG_AT91_LED) += led.o
 obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c
index 6398bcb..c11bb2c 100644
--- a/board/atmel/at91sam9261ek/at91sam9261ek.c
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <debug_uart.h>
 #include <asm/io.h>
 #include <asm/arch/at91sam9261.h>
 #include <asm/arch/at91sam9261_matrix.h>
@@ -21,6 +22,7 @@
 #include <net.h>
 #include <netdev.h>
 #endif
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -212,7 +214,7 @@ void lcd_show_board_info(void)
 		dram_size += gd->bd->bi_dram[i].size;
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i]->size;
+		nand_size += get_nand_dev_by_index(i)->size;
 	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 		dram_size >> 20,
 		nand_size >> 20 );
@@ -220,6 +222,23 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif
 
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
+	return 0;
+}
+#endif
+
 int board_init(void)
 {
 #ifdef CONFIG_AT91SAM9G10EK
@@ -232,13 +251,9 @@ int board_init(void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-	at91_seriald_hw_init();
 #ifdef CONFIG_CMD_NAND
 	at91sam9261ek_nand_hw_init();
 #endif
-#ifdef CONFIG_HAS_DATAFLASH
-	at91_spi0_hw_init(1 << 0);
-#endif
 #ifdef CONFIG_DRIVER_DM9000
 	at91sam9261ek_dm9000_hw_init();
 #endif
diff --git a/board/atmel/at91sam9263ek/Makefile b/board/atmel/at91sam9263ek/Makefile
index 7b31f18..f3cd9d5 100644
--- a/board/atmel/at91sam9263ek/Makefile
+++ b/board/atmel/at91sam9263ek/Makefile
@@ -10,5 +10,5 @@
 #
 
 obj-y += at91sam9263ek.o
-obj-y += led.o
+obj-$(CONFIG_AT91_LED) += led.o
 obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index 04e5812..bb06e56 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <debug_uart.h>
 #include <linux/sizes.h>
 #include <asm/arch/at91sam9263.h>
 #include <asm/arch/at91sam9_smc.h>
@@ -19,11 +20,7 @@
 #include <asm/arch/hardware.h>
 #include <lcd.h>
 #include <atmel_lcdc.h>
-#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
-#include <net.h>
-#endif
-#include <netdev.h>
-#include <atmel_mci.h>
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -77,34 +74,6 @@ static void at91sam9263ek_nand_hw_init(void)
 }
 #endif
 
-#ifdef CONFIG_MACB
-static void at91sam9263ek_macb_hw_init(void)
-{
-	at91_pio_t	*pio	= (at91_pio_t *) ATMEL_BASE_PIO;
-
-	at91_periph_clk_enable(ATMEL_ID_EMAC);
-
-	/*
-	 * Disable pull-up on:
-	 *	RXDV (PC25) => PHY normal mode (not Test mode)
-	 * 	ERX0 (PE25) => PHY ADDR0
-	 *	ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
-	 *
-	 * PHY has internal pull-down
-	 */
-	writel(1 << 25, &pio->pioc.pudr);
-	writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
-
-	at91_phy_reset();
-
-	/* Re-enable pull-up */
-	writel(1 << 25, &pio->pioc.puer);
-	writel((1 << 25) | (1 <<26), &pio->pioe.puer);
-
-	at91_macb_hw_init();
-}
-#endif
-
 #ifdef CONFIG_LCD
 vidinfo_t panel_info = {
 	.vl_col =		240,
@@ -166,14 +135,14 @@ static void at91sam9263ek_lcd_hw_init(void)
 #include <nand.h>
 #include <version.h>
 
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
 extern flash_info_t flash_info[];
 #endif
 
 void lcd_show_board_info(void)
 {
 	ulong dram_size, nand_size;
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
 	ulong flash_size;
 #endif
 	int i;
@@ -191,8 +160,8 @@ void lcd_show_board_info(void)
 		dram_size += gd->bd->bi_dram[i].size;
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i]->size;
-#ifndef CONFIG_SYS_NO_FLASH
+		nand_size += get_nand_dev_by_index(i)->size;
+#ifdef CONFIG_MTD_NOR_FLASH
 	flash_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
 		flash_size += flash_info[i].size;
@@ -200,7 +169,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("  %ld MB SDRAM, %ld MB NAND",
 		dram_size >> 20,
 		nand_size >> 20 );
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
 	lcd_printf (",\n  %ld MB NOR",
 		flash_size >> 20);
 #endif
@@ -209,24 +178,22 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif
 
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(bd_t *bd)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
 {
-	at91_mci_hw_init();
-
-	return atmel_mci_init((void *)ATMEL_BASE_MCI1);
+	at91_seriald_hw_init();
 }
 #endif
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-	at91_periph_clk_enable(ATMEL_ID_PIOA);
-	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
-
-	at91_seriald_hw_init();
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
 	return 0;
 }
+#endif
 
 int board_init(void)
 {
@@ -238,13 +205,6 @@ int board_init(void)
 #ifdef CONFIG_CMD_NAND
 	at91sam9263ek_nand_hw_init();
 #endif
-#ifdef CONFIG_HAS_DATAFLASH
-	at91_set_pio_output(AT91_PIO_PORTE, 20, 1);	/* select spi0 clock */
-	at91_spi0_hw_init(1 << 0);
-#endif
-#ifdef CONFIG_MACB
-	at91sam9263ek_macb_hw_init();
-#endif
 #ifdef CONFIG_USB_OHCI_NEW
 	at91_uhp_hw_init();
 #endif
@@ -267,12 +227,3 @@ void reset_phy(void)
 {
 }
 #endif
-
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_MACB
-	rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00);
-#endif
-	return rc;
-}
diff --git a/board/atmel/at91sam9m10g45ek/Makefile b/board/atmel/at91sam9m10g45ek/Makefile
index e5448ec..55cd946 100644
--- a/board/atmel/at91sam9m10g45ek/Makefile
+++ b/board/atmel/at91sam9m10g45ek/Makefile
@@ -10,4 +10,4 @@
 #
 
 obj-y += at91sam9m10g45ek.o
-obj-y += led.o
+obj-(CONFIG_AT91_LED) += led.o
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index 6871916..903732b 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <debug_uart.h>
 #include <asm/io.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/at91sam9g45_matrix.h>
@@ -17,11 +18,7 @@
 #include <lcd.h>
 #include <linux/mtd/nand.h>
 #include <atmel_lcdc.h>
-#include <atmel_mci.h>
-#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
-#include <net.h>
-#endif
-#include <netdev.h>
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -149,39 +146,6 @@ static void at91sam9m10g45ek_usb_hw_init(void)
 }
 #endif
 
-#ifdef CONFIG_MACB
-static void at91sam9m10g45ek_macb_hw_init(void)
-{
-	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-
-	at91_periph_clk_enable(ATMEL_ID_EMAC);
-
-	/*
-	 * Disable pull-up on:
-	 *      RXDV (PA15) => PHY normal mode (not Test mode)
-	 *      ERX0 (PA12) => PHY ADDR0
-	 *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
-	 *
-	 * PHY has internal pull-down
-	 */
-	writel(pin_to_mask(AT91_PIN_PA15) |
-	       pin_to_mask(AT91_PIN_PA12) |
-	       pin_to_mask(AT91_PIN_PA13),
-	       &pioa->pudr);
-
-	at91_phy_reset();
-
-	/* Re-enable pull-up */
-	writel(pin_to_mask(AT91_PIN_PA15) |
-	       pin_to_mask(AT91_PIN_PA12) |
-	       pin_to_mask(AT91_PIN_PA13),
-	       &pioa->puer);
-
-	/* And the pins. */
-	at91_macb_hw_init();
-}
-#endif
-
 #ifdef CONFIG_LCD
 
 vidinfo_t panel_info = {
@@ -272,7 +236,7 @@ void lcd_show_board_info(void)
 		dram_size += gd->bd->bi_dram[i].size;
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i]->size;
+		nand_size += get_nand_dev_by_index(i)->size;
 	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 		dram_size >> 20,
 		nand_size >> 20 );
@@ -280,20 +244,22 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif
 
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(bd_t *bis)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
 {
-	at91_mci_hw_init();
-
-	return atmel_mci_init((void *)ATMEL_BASE_MCI0);
+	at91_seriald_hw_init();
 }
 #endif
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-	at91_seriald_hw_init();
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
 	return 0;
 }
+#endif
 
 int board_init(void)
 {
@@ -313,15 +279,6 @@ int board_init(void)
 #ifdef CONFIG_CMD_USB
 	at91sam9m10g45ek_usb_hw_init();
 #endif
-#ifdef CONFIG_HAS_DATAFLASH
-	at91_spi0_hw_init(1 << 0);
-#endif
-#ifdef CONFIG_ATMEL_SPI
-	at91_spi0_hw_init(1 << 4);
-#endif
-#ifdef CONFIG_MACB
-	at91sam9m10g45ek_macb_hw_init();
-#endif
 #ifdef CONFIG_LCD
 	at91sam9m10g45ek_lcd_hw_init();
 #endif
@@ -340,48 +297,3 @@ void reset_phy(void)
 {
 }
 #endif
-
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_MACB
-	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
-#endif
-	return rc;
-}
-
-/* SPI chip select control */
-#ifdef CONFIG_ATMEL_SPI
-#include <spi.h>
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs < 2;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	switch(slave->cs) {
-		case 1:
-			at91_set_gpio_output(AT91_PIN_PB18, 0);
-			break;
-		case 0:
-		default:
-			at91_set_gpio_output(AT91_PIN_PB3, 0);
-			break;
-	}
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	switch(slave->cs) {
-		case 1:
-			at91_set_gpio_output(AT91_PIN_PB18, 1);
-			break;
-		case 0:
-		default:
-			at91_set_gpio_output(AT91_PIN_PB3, 1);
-		break;
-	}
-}
-#endif /* CONFIG_ATMEL_SPI */
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
index fc4f50d..fec9316 100644
--- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -13,9 +13,9 @@
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/at91_pio.h>
 #include <asm/arch/clk.h>
+#include <debug_uart.h>
 #include <lcd.h>
 #include <atmel_hlcdc.h>
-#include <atmel_mci.h>
 #include <netdev.h>
 
 #ifdef CONFIG_LCD_INFO
@@ -71,10 +71,10 @@ static void at91sam9n12ek_nand_hw_init(void)
 	/* Configure ENABLE pin for NandFlash */
 	at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
 
-	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);    /* NAND OE */
-	at91_set_a_periph(AT91_PIO_PORTD, 1, 1);    /* NAND WE */
-	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);    /* ALE */
-	at91_set_a_periph(AT91_PIO_PORTD, 3, 1);    /* CLE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);    /* NAND OE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);    /* NAND WE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1);    /* ALE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1);    /* CLE */
 }
 #endif
 
@@ -124,7 +124,7 @@ void lcd_show_board_info(void)
 		dram_size += gd->bd->bi_dram[i].size;
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i]->size;
+		nand_size += get_nand_dev_by_index(i)->size;
 	lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
 		dram_size >> 20,
 		nand_size >> 20);
@@ -132,48 +132,6 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif /* CONFIG_LCD */
 
-/* SPI chip select control */
-#ifdef CONFIG_ATMEL_SPI
-#include <spi.h>
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs < 2;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	switch (slave->cs) {
-	case 0:
-		at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
-		break;
-	case 1:
-		at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
-		break;
-	}
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	switch (slave->cs) {
-	case 0:
-		at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
-		break;
-	case 1:
-		at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
-		break;
-	}
-}
-#endif /* CONFIG_ATMEL_SPI */
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(bd_t *bd)
-{
-	at91_mci_hw_init();
-
-	return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
-}
-#endif
-
 #ifdef CONFIG_KS8851_MLL
 void at91sam9n12ek_ks8851_hw_init(void)
 {
@@ -194,7 +152,7 @@ void at91sam9n12ek_ks8851_hw_init(void)
 	       &smc->cs[2].mode);
 
 	/* Configure NCS2 PIN */
-	at91_set_b_periph(AT91_PIO_PORTD, 19, 0);
+	at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0);
 }
 #endif
 
@@ -205,14 +163,22 @@ void at91sam9n12ek_usb_hw_init(void)
 }
 #endif
 
-int board_early_init_f(void)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
 {
-	at91_periph_clk_enable(ATMEL_ID_PIOAB);
-	at91_periph_clk_enable(ATMEL_ID_PIOCD);
-
 	at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
 	return 0;
 }
+#endif
 
 int board_init(void)
 {
@@ -223,10 +189,6 @@ int board_init(void)
 	at91sam9n12ek_nand_hw_init();
 #endif
 
-#ifdef CONFIG_ATMEL_SPI
-	at91_spi0_hw_init(1 << 0);
-#endif
-
 #ifdef CONFIG_LCD
 	at91_lcd_hw_init();
 #endif
diff --git a/board/atmel/at91sam9rlek/Makefile b/board/atmel/at91sam9rlek/Makefile
index 51daf8d..7acfee5 100644
--- a/board/atmel/at91sam9rlek/Makefile
+++ b/board/atmel/at91sam9rlek/Makefile
@@ -10,5 +10,5 @@
 #
 
 obj-y += at91sam9rlek.o
-obj-y += led.o
+obj-$(CONFIG_AT91_LED) += led.o
 obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c
index 994f246..6b13bdf 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -7,7 +7,9 @@
  */
 
 #include <common.h>
+#include <debug_uart.h>
 #include <asm/io.h>
+#include <asm/mach-types.h>
 #include <asm/arch/at91sam9rl.h>
 #include <asm/arch/at91sam9rl_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
@@ -18,10 +20,6 @@
 
 #include <lcd.h>
 #include <atmel_lcdc.h>
-#include <atmel_mci.h>
-#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
-#include <net.h>
-#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -151,7 +149,7 @@ void lcd_show_board_info(void)
 		dram_size += gd->bd->bi_dram[i].size;
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i]->size;
+		nand_size += get_nand_dev_by_index(i)->size;
 	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 		dram_size >> 20,
 		nand_size >> 20 );
@@ -159,24 +157,22 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif
 
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(bd_t *bis)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
 {
-	at91_mci_hw_init();
-
-	return atmel_mci_init((void *)ATMEL_BASE_MCI);
+	at91_seriald_hw_init();
 }
 #endif
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-	at91_periph_clk_enable(ATMEL_ID_PIOA);
-	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	at91_periph_clk_enable(ATMEL_ID_PIOC);
-	at91_periph_clk_enable(ATMEL_ID_PIOD);
-
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
 	return 0;
 }
+#endif
 
 int board_init(void)
 {
@@ -185,13 +181,9 @@ int board_init(void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-	at91_seriald_hw_init();
 #ifdef CONFIG_CMD_NAND
 	at91sam9rlek_nand_hw_init();
 #endif
-#ifdef CONFIG_HAS_DATAFLASH
-	at91_spi0_hw_init(1 << 0);
-#endif
 #ifdef CONFIG_LCD
 	at91sam9rlek_lcd_hw_init();
 #endif
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index b0d440d..2452e63 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -12,20 +12,14 @@
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
+#include <debug_uart.h>
 #include <lcd.h>
 #include <atmel_hlcdc.h>
-#include <atmel_mci.h>
-#ifdef CONFIG_MACB
-#include <net.h>
-#endif
-#include <netdev.h>
 #ifdef CONFIG_LCD_INFO
 #include <nand.h>
 #include <version.h>
 #endif
-#ifdef CONFIG_ATMEL_SPI
-#include <spi.h>
-#endif
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -77,36 +71,21 @@ static void at91sam9x5ek_nand_hw_init(void)
 	/* Enable NandFlash */
 	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 
-	at91_set_a_periph(AT91_PIO_PORTD, 0, 1);	/* NAND OE */
-	at91_set_a_periph(AT91_PIO_PORTD, 1, 1);	/* NAND WE */
-	at91_set_a_periph(AT91_PIO_PORTD, 2, 1);	/* NAND ALE */
-	at91_set_a_periph(AT91_PIO_PORTD, 3, 1);	/* NAND CLE */
-	at91_set_a_periph(AT91_PIO_PORTD, 6, 1);
-	at91_set_a_periph(AT91_PIO_PORTD, 7, 1);
-	at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
-	at91_set_a_periph(AT91_PIO_PORTD, 9, 1);
-	at91_set_a_periph(AT91_PIO_PORTD, 10, 1);
-	at91_set_a_periph(AT91_PIO_PORTD, 11, 1);
-	at91_set_a_periph(AT91_PIO_PORTD, 12, 1);
-	at91_set_a_periph(AT91_PIO_PORTD, 13, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);	/* NAND OE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);	/* NAND WE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1);	/* NAND ALE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1);	/* NAND CLE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
+	at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
 }
 #endif
 
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-
-#ifdef CONFIG_MACB
-	if (has_emac0())
-		rc = macb_eth_initialize(0,
-			(void *)ATMEL_BASE_EMAC0, 0x00);
-	if (has_emac1())
-		rc = macb_eth_initialize(1,
-			(void *)ATMEL_BASE_EMAC1, 0x00);
-#endif
-	return rc;
-}
-
 #ifdef CONFIG_LCD
 vidinfo_t panel_info = {
 	.vl_col	= 800,
@@ -128,49 +107,49 @@ vidinfo_t panel_info = {
 void lcd_enable(void)
 {
 	if (has_lcdc())
-		at91_set_a_periph(AT91_PIO_PORTC, 29, 1);	/* power up */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 1);	/* power up */
 }
 
 void lcd_disable(void)
 {
 	if (has_lcdc())
-		at91_set_a_periph(AT91_PIO_PORTC, 29, 0);	/* power down */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0);	/* power down */
 }
 
 static void at91sam9x5ek_lcd_hw_init(void)
 {
 	if (has_lcdc()) {
-		at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDPWM */
-		at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDVSYNC */
-		at91_set_a_periph(AT91_PIO_PORTC, 28, 0);	/* LCDHSYNC */
-		at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDDISP */
-		at91_set_a_periph(AT91_PIO_PORTC, 29, 0);	/* LCDDEN */
-		at91_set_a_periph(AT91_PIO_PORTC, 30, 0);	/* LCDPCK */
-
-		at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDD0 */
-		at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDD1 */
-		at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDD2 */
-		at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDD3 */
-		at91_set_a_periph(AT91_PIO_PORTC, 4, 0);	/* LCDD4 */
-		at91_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* LCDD5 */
-		at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD6 */
-		at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD7 */
-		at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD8 */
-		at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD9 */
-		at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD10 */
-		at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD11 */
-		at91_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD12 */
-		at91_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD13 */
-		at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD14 */
-		at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD15 */
-		at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD16 */
-		at91_set_a_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD17 */
-		at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD18 */
-		at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD19 */
-		at91_set_a_periph(AT91_PIO_PORTC, 20, 0);	/* LCDD20 */
-		at91_set_a_periph(AT91_PIO_PORTC, 21, 0);	/* LCDD21 */
-		at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD22 */
-		at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD23 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDPWM */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDVSYNC */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 28, 0);	/* LCDHSYNC */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDDISP */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 29, 0);	/* LCDDEN */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 30, 0);	/* LCDPCK */
+
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDD0 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDD1 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDD2 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDD3 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 4, 0);	/* LCDD4 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* LCDD5 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD6 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD7 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD8 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD9 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD10 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD11 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD12 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD13 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD14 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD15 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD16 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD17 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD18 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD19 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 20, 0);	/* LCDD20 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 21, 0);	/* LCDD21 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD22 */
+		at91_pio3_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD23 */
 
 		at91_periph_clk_enable(ATMEL_ID_LCDC);
 	}
@@ -196,7 +175,7 @@ void lcd_show_board_info(void)
 			dram_size += gd->bd->bi_dram[i].size;
 		nand_size = 0;
 		for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-			nand_size += nand_info[i]->size;
+			nand_size += get_nand_dev_by_index(i)->size;
 		lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
 			dram_size >> 20,
 			nand_size >> 20);
@@ -205,54 +184,22 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif /* CONFIG_LCD */
 
-/* SPI chip select control */
-#ifdef CONFIG_ATMEL_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs < 2;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
 {
-	switch (slave->cs) {
-	case 1:
-		at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
-		break;
-	case 0:
-	default:
-		at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
-		break;
-	}
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	switch (slave->cs) {
-	case 1:
-		at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
-		break;
-	case 0:
-	default:
-		at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
-		break;
-	}
-}
-#endif /* CONFIG_ATMEL_SPI */
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(bd_t *bd)
-{
-	at91_mci_hw_init();
-
-	return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
+	at91_seriald_hw_init();
 }
 #endif
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-	at91_seriald_hw_init();
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
 	return 0;
 }
+#endif
 
 int board_init(void)
 {
@@ -266,15 +213,7 @@ int board_init(void)
 	at91sam9x5ek_nand_hw_init();
 #endif
 
-#ifdef CONFIG_ATMEL_SPI
-	at91_spi0_hw_init(1 << 4);
-#endif
-
-#ifdef CONFIG_MACB
-	at91_macb_hw_init();
-#endif
-
-#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
+#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD)
 	at91_uhp_hw_init();
 #endif
 #ifdef CONFIG_LCD
@@ -300,8 +239,6 @@ void at91_spl_board_init(void)
 	at91_mci_hw_init();
 #elif CONFIG_SYS_USE_NANDFLASH
 	at91sam9x5ek_nand_hw_init();
-#elif CONFIG_SYS_USE_SPIFLASH
-	at91_spi0_hw_init(1 << 4);
 #endif
 }
 
diff --git a/board/atmel/atngw100/Kconfig b/board/atmel/atngw100/Kconfig
deleted file mode 100644
index 28037b6..0000000
--- a/board/atmel/atngw100/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_ATNGW100
-
-config SYS_BOARD
-	default "atngw100"
-
-config SYS_VENDOR
-	default "atmel"
-
-config SYS_SOC
-	default "at32ap700x"
-
-config SYS_CONFIG_NAME
-	default "atngw100"
-
-endif
diff --git a/board/atmel/atngw100/MAINTAINERS b/board/atmel/atngw100/MAINTAINERS
deleted file mode 100644
index 1c319f6..0000000
--- a/board/atmel/atngw100/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ATNGW100 BOARD
-#M:	Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-S:	Orphan (since 2014-06)
-F:	board/atmel/atngw100/
-F:	include/configs/atngw100.h
-F:	configs/atngw100_defconfig
diff --git a/board/atmel/atngw100/Makefile b/board/atmel/atngw100/Makefile
deleted file mode 100644
index f9b93c9..0000000
--- a/board/atmel/atngw100/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Copyright (C) 2005-2006 Atmel Corporation
-#
-# SPDX-License-Identifier:	GPL-2.0+
-
-obj-y	:= atngw100.o
diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c
deleted file mode 100644
index dacd427..0000000
--- a/board/atmel/atngw100/atngw100.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/sdram.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/hmatrix.h>
-#include <asm/arch/mmu.h>
-#include <asm/arch/portmux.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
-	{
-		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_NONE,
-	}, {
-		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_WRBACK,
-	},
-};
-
-static const struct sdram_config sdram_config = {
-	.data_bits	= SDRAM_DATA_16BIT,
-	.row_bits	= 13,
-	.col_bits	= 9,
-	.bank_bits	= 2,
-	.cas		= 3,
-	.twr		= 2,
-	.trc		= 7,
-	.trp		= 2,
-	.trcd		= 2,
-	.tras		= 5,
-	.txsr		= 5,
-	/* 7.81 us */
-	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
-};
-
-int board_early_init_f(void)
-{
-	/* Enable SDRAM in the EBI mux */
-	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
-
-	portmux_enable_ebi(16, 23, 0, PORTMUX_DRIVE_HIGH);
-	sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
-
-	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
-
-#if defined(CONFIG_MACB)
-	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
-	portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
-#endif
-#if defined(CONFIG_MMC)
-	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
-#endif
-#if defined(CONFIG_ATMEL_SPI)
-	portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
-#endif
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	gd->bd->bi_phy_id[0] = 0x01;
-	gd->bd->bi_phy_id[1] = 0x03;
-	return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bi)
-{
-	macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
-	macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
-	return 0;
-}
-#endif
-
-/* SPI chip select control */
-#ifdef CONFIG_ATMEL_SPI
-#include <spi.h>
-
-#define ATNGW100_DATAFLASH_CS_PIN	GPIO_PIN_PA(3)
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
-}
-#endif /* CONFIG_ATMEL_SPI */
diff --git a/board/atmel/atngw100mkii/Kconfig b/board/atmel/atngw100mkii/Kconfig
deleted file mode 100644
index ca04269..0000000
--- a/board/atmel/atngw100mkii/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_ATNGW100MKII
-
-config SYS_BOARD
-	default "atngw100mkii"
-
-config SYS_VENDOR
-	default "atmel"
-
-config SYS_SOC
-	default "at32ap700x"
-
-config SYS_CONFIG_NAME
-	default "atngw100mkii"
-
-endif
diff --git a/board/atmel/atngw100mkii/MAINTAINERS b/board/atmel/atngw100mkii/MAINTAINERS
deleted file mode 100644
index 54eb1da..0000000
--- a/board/atmel/atngw100mkii/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ATNGW100MKII BOARD
-M:	Andreas Bießmann <andreas@biessmann.org>
-S:	Maintained
-F:	board/atmel/atngw100mkii/
-F:	include/configs/atngw100mkii.h
-F:	configs/atngw100mkii_defconfig
diff --git a/board/atmel/atngw100mkii/Makefile b/board/atmel/atngw100mkii/Makefile
deleted file mode 100644
index 90bf5bc..0000000
--- a/board/atmel/atngw100mkii/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Copyright (C) 2005-2006 Atmel Corporation
-#
-# SPDX-License-Identifier:	GPL-2.0+
-
-obj-y	:= atngw100mkii.o
diff --git a/board/atmel/atngw100mkii/atngw100mkii.c b/board/atmel/atngw100mkii/atngw100mkii.c
deleted file mode 100644
index 68662c4..0000000
--- a/board/atmel/atngw100mkii/atngw100mkii.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Copyright (C) 2010 Atmel Corporation
- *
- * Copyright (C) 2012 Andreas Bießmann <andreas@biessmann.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <spi.h>
-#include <netdev.h>
-
-#include <asm/io.h>
-#include <asm/sdram.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/hmatrix.h>
-#include <asm/arch/mmu.h>
-#include <asm/arch/portmux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
-	{
-		/* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
-		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_NONE,
-	}, {
-		/* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */
-		.virt_pgno	= EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= EBI_SRAM_CS3_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_NONE,
-	}, {
-		/* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */
-		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_WRBACK,
-	},
-};
-
-static const struct sdram_config sdram_config = {
-	.data_bits	= SDRAM_DATA_32BIT,
-	.row_bits	= 13,
-	.col_bits	= 10,
-	.bank_bits	= 2,
-	.cas		= 3,
-	.twr		= 2,
-	.trc		= 7,
-	.trp		= 2,
-	.trcd		= 2,
-	.tras		= 5,
-	.txsr		= 6,
-	/* 7.81 us */
-	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
-};
-
-int board_early_init_f(void)
-{
-	/* Enable SDRAM in the EBI mux */
-	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)
-			| HMATRIX_BIT(EBI_NAND_ENABLE));
-
-	portmux_enable_ebi(32, 23, PORTMUX_EBI_NAND,
-			PORTMUX_DRIVE_HIGH);
-	portmux_select_gpio(PORTMUX_PORT_E, 1 << 23,
-			PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH
-			| PORTMUX_DRIVE_MIN);
-
-	sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
-
-	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
-
-#if defined(CONFIG_MACB)
-	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
-	portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
-#endif
-#if defined(CONFIG_MMC)
-	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
-#endif
-#if defined(CONFIG_ATMEL_SPI)
-	portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
-#endif
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	gd->bd->bi_phy_id[0] = 0x01;
-	gd->bd->bi_phy_id[1] = 0x03;
-	return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bi)
-{
-	macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
-	macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
-	return 0;
-}
-#endif
-
-/* SPI chip select control */
-#ifdef CONFIG_ATMEL_SPI
-#define ATNGW100_DATAFLASH_CS_PIN	GPIO_PIN_PA(3)
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
-}
-#endif /* CONFIG_ATMEL_SPI */
diff --git a/board/atmel/atstk1000/Kconfig b/board/atmel/atstk1000/Kconfig
deleted file mode 100644
index b4fa9a2..0000000
--- a/board/atmel/atstk1000/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_ATSTK1002
-
-config SYS_BOARD
-	default "atstk1000"
-
-config SYS_VENDOR
-	default "atmel"
-
-config SYS_SOC
-	default "at32ap700x"
-
-config SYS_CONFIG_NAME
-	default "atstk1002"
-
-endif
diff --git a/board/atmel/atstk1000/MAINTAINERS b/board/atmel/atstk1000/MAINTAINERS
deleted file mode 100644
index 1070f98..0000000
--- a/board/atmel/atstk1000/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ATSTK1000 BOARD
-M:	Andreas Bießmann <andreas.biessmann@corscience.de>
-S:	Maintained
-F:	board/atmel/atstk1000/
-F:	include/configs/atstk1002.h
-F:	configs/atstk1002_defconfig
diff --git a/board/atmel/atstk1000/Makefile b/board/atmel/atstk1000/Makefile
deleted file mode 100644
index ad76631..0000000
--- a/board/atmel/atstk1000/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2005-2006 Atmel Corporation
-#
-# SPDX-License-Identifier:	GPL-2.0+
-
-obj-y			+= atstk1000.o
diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c
deleted file mode 100644
index 679b674..0000000
--- a/board/atmel/atstk1000/atstk1000.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/sdram.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/hmatrix.h>
-#include <asm/arch/mmu.h>
-#include <asm/arch/portmux.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
-	{
-		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_NONE,
-	}, {
-		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_WRBACK,
-	},
-};
-
-static const struct sdram_config sdram_config = {
-	.data_bits	= SDRAM_DATA_32BIT,
-#ifdef CONFIG_ATSTK1000_16MB_SDRAM
-	/* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
-	.row_bits	= 12,
-#else
-	/* MT48LC2M32B2P-5 (8 MB) on motherboard */
-	.row_bits	= 11,
-#endif
-	.col_bits	= 8,
-	.bank_bits	= 2,
-	.cas		= 3,
-	.twr		= 2,
-	.trc		= 7,
-	.trp		= 2,
-	.trcd		= 2,
-	.tras		= 5,
-	.txsr		= 5,
-	/* 15.6 us */
-	.refresh_period	= (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
-};
-
-int board_early_init_f(void)
-{
-	/* Enable SDRAM in the EBI mux */
-	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
-
-	portmux_enable_ebi(sdram_config.data_bits, 23, 0, PORTMUX_DRIVE_HIGH);
-	sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
-
-	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
-
-#if defined(CONFIG_MACB)
-	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
-	portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
-#endif
-#if defined(CONFIG_MMC)
-	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
-#endif
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	gd->bd->bi_phy_id[0] = 0x10;
-	gd->bd->bi_phy_id[1] = 0x11;
-	return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bi)
-{
-	macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
-	macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
-	return 0;
-}
-#endif
diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
index 93df7ba..48f45b3 100644
--- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c
+++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
@@ -7,17 +7,15 @@
 
 #include <common.h>
 #include <atmel_hlcdc.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <i2c.h>
 #include <lcd.h>
-#include <mmc.h>
-#include <net.h>
-#include <netdev.h>
-#include <spi.h>
 #include <version.h>
 #include <asm/io.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/atmel_pio4.h>
 #include <asm/arch/atmel_mpddrc.h>
-#include <asm/arch/atmel_usba_udc.h>
 #include <asm/arch/atmel_sdhci.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
@@ -25,32 +23,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
-}
-
-static void board_spi0_hw_init(void)
-{
-	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
-	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
-	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);
-
-	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
-
-	at91_periph_clk_enable(ATMEL_ID_SPI0);
-}
-
 static void board_usb_hw_init(void)
 {
 	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
@@ -141,71 +113,7 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif /* CONFIG_LCD */
 
-static void board_gmac_hw_init(void)
-{
-	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0);	/* GTXCK */
-	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0);	/* GTXEN */
-	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0);	/* GRXDV */
-	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0);	/* GRXER */
-	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0);	/* GRX0 */
-	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0);	/* GRX1 */
-	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0);	/* GTX0 */
-	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0);	/* GTX1 */
-	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0);	/* GMDC */
-	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0);	/* GMDIO */
-
-	at91_periph_clk_enable(ATMEL_ID_GMAC);
-}
-
-static void board_sdhci0_hw_init(void)
-{
-	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0);	/* SDMMC0_CK */
-	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0);	/* SDMMC0_CMD */
-	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0);	/* SDMMC0_DAT0 */
-	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0);	/* SDMMC0_DAT1 */
-	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0);	/* SDMMC0_DAT2 */
-	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0);	/* SDMMC0_DAT3 */
-	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 6, 0);	/* SDMMC0_DAT4 */
-	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 7, 0);	/* SDMMC0_DAT5 */
-	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 8, 0);	/* SDMMC0_DAT6 */
-	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0);	/* SDMMC0_DAT7 */
-	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* SDMMC0_RSTN */
-	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* SDMMC0_VDDSEL */
-	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* SDMMC0_CD */
-
-	at91_periph_clk_enable(ATMEL_ID_SDMMC0);
-	at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0,
-					 GCK_CSS_UPLL_CLK, 1);
-}
-
-static void board_sdhci1_hw_init(void)
-{
-	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 18, 0);	/* SDMMC1_DAT0 */
-	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 19, 0);	/* SDMMC1_DAT1 */
-	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 20, 0);	/* SDMMC1_DAT2 */
-	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 21, 0);	/* SDMMC1_DAT3 */
-	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 22, 0);	/* SDMMC1_CK */
-	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 27, 0);	/* SDMMC1_RSTN */
-	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 28, 0);	/* SDMMC1_CMD */
-	atmel_pio4_set_e_periph(AT91_PIO_PORTA, 30, 0);	/* SDMMC1_CD */
-
-	at91_periph_clk_enable(ATMEL_ID_SDMMC1);
-	at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1,
-					 GCK_CSS_UPLL_CLK, 1);
-}
-
-int board_mmc_init(bd_t *bis)
-{
-#ifdef CONFIG_ATMEL_SDHCI0
-	atmel_sdhci_init((void *)ATMEL_BASE_SDMMC0, ATMEL_ID_SDMMC0);
-#endif
-#ifdef CONFIG_ATMEL_SDHCI1
-	atmel_sdhci_init((void *)ATMEL_BASE_SDMMC1, ATMEL_ID_SDMMC1);
-#endif
-
-	return 0;
-}
-
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
 static void board_uart1_hw_init(void)
 {
 	atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1);	/* URXD1 */
@@ -214,46 +122,34 @@ static void board_uart1_hw_init(void)
 	at91_periph_clk_enable(ATMEL_ID_UART1);
 }
 
-int board_early_init_f(void)
+void board_debug_uart_init(void)
 {
-	at91_periph_clk_enable(ATMEL_ID_PIOA);
-	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	at91_periph_clk_enable(ATMEL_ID_PIOC);
-	at91_periph_clk_enable(ATMEL_ID_PIOD);
-
 	board_uart1_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
 
 	return 0;
 }
+#endif
 
 int board_init(void)
 {
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-#ifdef CONFIG_ATMEL_SPI
-	board_spi0_hw_init();
-#endif
-#ifdef CONFIG_ATMEL_SDHCI
-#ifdef CONFIG_ATMEL_SDHCI0
-	board_sdhci0_hw_init();
-#endif
-#ifdef CONFIG_ATMEL_SDHCI1
-	board_sdhci1_hw_init();
-#endif
-#endif
-#ifdef CONFIG_MACB
-	board_gmac_hw_init();
-#endif
 #ifdef CONFIG_LCD
 	board_lcd_hw_init();
 #endif
 #ifdef CONFIG_CMD_USB
 	board_usb_hw_init();
 #endif
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-	at91_udp_hw_init();
-#endif
 
 	return 0;
 }
@@ -265,39 +161,59 @@ int dram_init(void)
 	return 0;
 }
 
-int board_eth_init(bd_t *bis)
+#ifdef CONFIG_CMD_I2C
+static int set_ethaddr_from_eeprom(void)
 {
-	int rc = 0;
-
-#ifdef CONFIG_MACB
-	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+	const int ETH_ADDR_LEN = 6;
+	unsigned char ethaddr[ETH_ADDR_LEN];
+	const char *ETHADDR_NAME = "ethaddr";
+	struct udevice *bus, *dev;
+
+	if (getenv(ETHADDR_NAME))
+		return 0;
+
+	if (uclass_get_device_by_seq(UCLASS_I2C, 1, &bus)) {
+		printf("Cannot find I2C bus 1\n");
+		return -1;
+	}
+
+	if (dm_i2c_probe(bus, AT24MAC_ADDR, 0, &dev)) {
+		printf("Failed to probe I2C chip\n");
+		return -1;
+	}
+
+	if (dm_i2c_read(dev, AT24MAC_REG, ethaddr, ETH_ADDR_LEN)) {
+		printf("Failed to read ethernet address from EEPROM\n");
+		return -1;
+	}
+
+	if (!is_valid_ethaddr(ethaddr)) {
+		printf("The ethernet address read from EEPROM is not valid!\n");
+		return -1;
+	}
+
+	return eth_setenv_enetaddr(ETHADDR_NAME, ethaddr);
+}
+#else
+static int set_ethaddr_from_eeprom(void)
+{
+	return 0;
+}
 #endif
 
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-	usba_udc_probe(&pdata);
-#ifdef CONFIG_USB_ETH_RNDIS
-	usb_eth_initialize(bis);
-#endif
-#endif
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	set_ethaddr_from_eeprom();
 
-	return rc;
+	return 0;
 }
+#endif
 
 /* SPL */
 #ifdef CONFIG_SPL_BUILD
 void spl_board_init(void)
 {
-#ifdef CONFIG_SYS_USE_SERIALFLASH
-	board_spi0_hw_init();
-#endif
-#ifdef CONFIG_ATMEL_SDHCI
-#ifdef CONFIG_ATMEL_SDHCI0
-	board_sdhci0_hw_init();
-#endif
-#ifdef CONFIG_ATMEL_SDHCI1
-	board_sdhci1_hw_init();
-#endif
-#endif
 }
 
 static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
index 2b9da91..ba7f9f2 100644
--- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -6,16 +6,13 @@
  */
 
 #include <common.h>
-#include <mmc.h>
 #include <asm/io.h>
 #include <asm/arch/sama5d3_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
-#include <atmel_mci.h>
-#include <net.h>
-#include <netdev.h>
+#include <debug_uart.h>
 #include <spl.h>
 #include <asm/arch/atmel_mpddrc.h>
 #include <asm/arch/at91_wdt.h>
@@ -65,24 +62,26 @@ static void sama5d3_xplained_usb_hw_init(void)
 #ifdef CONFIG_GENERIC_ATMEL_MCI
 static void sama5d3_xplained_mci0_hw_init(void)
 {
-	at91_mci_hw_init();
-
 	at91_set_pio_output(AT91_PIO_PORTE, 2, 0);	/* MCI0 Power */
 }
 #endif
 
-int board_early_init_f(void)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
 {
-	at91_periph_clk_enable(ATMEL_ID_PIOA);
-	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	at91_periph_clk_enable(ATMEL_ID_PIOC);
-	at91_periph_clk_enable(ATMEL_ID_PIOD);
-	at91_periph_clk_enable(ATMEL_ID_PIOE);
-
 	at91_seriald_hw_init();
+}
+#endif
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
 	return 0;
 }
+#endif
 
 int board_init(void)
 {
@@ -98,10 +97,6 @@ int board_init(void)
 #ifdef CONFIG_GENERIC_ATMEL_MCI
 	sama5d3_xplained_mci0_hw_init();
 #endif
-#ifdef CONFIG_MACB
-	at91_gmac_hw_init();
-	at91_macb_hw_init();
-#endif
 	return 0;
 }
 
@@ -113,30 +108,14 @@ int dram_init(void)
 	return 0;
 }
 
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_MACB
-	macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
-	macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(bd_t *bis)
-{
-	atmel_mci_init((void *)ATMEL_BASE_MCI0);
-
-	return 0;
-}
-#endif
-
 /* SPL */
 #ifdef CONFIG_SPL_BUILD
 void spl_board_init(void)
 {
 #ifdef CONFIG_SYS_USE_MMC
+#ifdef CONFIG_GENERIC_ATMEL_MCI
 	sama5d3_xplained_mci0_hw_init();
+#endif
 #elif CONFIG_SYS_USE_NANDFLASH
 	sama5d3_xplained_nand_hw_init();
 #endif
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index fa90270..c1f2769 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -6,29 +6,22 @@
  */
 
 #include <common.h>
-#include <mmc.h>
 #include <asm/io.h>
 #include <asm/arch/sama5d3_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
+#include <debug_uart.h>
 #include <lcd.h>
 #include <linux/ctype.h>
 #include <atmel_hlcdc.h>
-#include <atmel_mci.h>
 #include <phy.h>
 #include <micrel.h>
-#include <net.h>
-#include <netdev.h>
 #include <spl.h>
 #include <asm/arch/atmel_mpddrc.h>
 #include <asm/arch/at91_wdt.h>
 
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-#include <asm/arch/atmel_usba_udc.h>
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 /* ------------------------------------------------------------------------- */
@@ -68,7 +61,7 @@ void sama5d3xek_nand_hw_init(void)
 }
 #endif
 
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
 static void sama5d3xek_nor_hw_init(void)
 {
 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
@@ -95,31 +88,31 @@ static void sama5d3xek_nor_hw_init(void)
 	       &smc->cs[0].mode);
 
 	/* Address pin (A1 ~ A23) configuration */
-	at91_set_a_periph(AT91_PIO_PORTE, 1, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 2, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 3, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 4, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 5, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 6, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 7, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 8, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 9, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 10, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 11, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 12, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 13, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 14, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 15, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 16, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 17, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 18, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 19, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 20, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 21, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 22, 0);
-	at91_set_a_periph(AT91_PIO_PORTE, 23, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 1, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 2, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 3, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 4, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 5, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 6, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 7, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 8, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 9, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 10, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 11, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 12, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 13, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 14, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 15, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 16, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 17, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 18, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 19, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 20, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 21, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 22, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 23, 0);
 	/* CS0 pin configuration */
-	at91_set_a_periph(AT91_PIO_PORTE, 26, 0);
+	at91_pio3_set_a_periph(AT91_PIO_PORTE, 26, 0);
 }
 #endif
 
@@ -135,8 +128,6 @@ static void sama5d3xek_usb_hw_init(void)
 #ifdef CONFIG_GENERIC_ATMEL_MCI
 static void sama5d3xek_mci_hw_init(void)
 {
-	at91_mci_hw_init();
-
 	at91_set_pio_output(AT91_PIO_PORTB, 10, 0);	/* MCI0 Power */
 }
 #endif
@@ -170,14 +161,14 @@ static void sama5d3xek_lcd_hw_init(void)
 	gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
 
 	/* The higher 8 bit of LCD is board related */
-	at91_set_c_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD16 */
-	at91_set_c_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD17 */
-	at91_set_c_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD18 */
-	at91_set_c_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD19 */
-	at91_set_c_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD20 */
-	at91_set_c_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD21 */
-	at91_set_c_periph(AT91_PIO_PORTE, 27, 0);	/* LCDD22 */
-	at91_set_c_periph(AT91_PIO_PORTE, 28, 0);	/* LCDD23 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD16 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD17 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD18 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD19 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD20 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD21 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTE, 27, 0);	/* LCDD22 */
+	at91_pio3_set_c_periph(AT91_PIO_PORTE, 28, 0);	/* LCDD23 */
 
 	/* Configure lower 16 bit of LCD and enable clock */
 	at91_lcd_hw_init();
@@ -207,7 +198,7 @@ void lcd_show_board_info(void)
 	nand_size = 0;
 #ifdef CONFIG_NAND_ATMEL
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i]->size;
+		nand_size += get_nand_dev_by_index(i)->size;
 #endif
 	lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
 		   dram_size >> 20, nand_size >> 20);
@@ -215,18 +206,22 @@ void lcd_show_board_info(void)
 #endif /* CONFIG_LCD_INFO */
 #endif /* CONFIG_LCD */
 
-int board_early_init_f(void)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
 {
-	at91_periph_clk_enable(ATMEL_ID_PIOA);
-	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	at91_periph_clk_enable(ATMEL_ID_PIOC);
-	at91_periph_clk_enable(ATMEL_ID_PIOD);
-	at91_periph_clk_enable(ATMEL_ID_PIOE);
-
 	at91_seriald_hw_init();
+}
+#endif
 
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
 	return 0;
 }
+#endif
 
 int board_init(void)
 {
@@ -236,27 +231,15 @@ int board_init(void)
 #ifdef CONFIG_NAND_ATMEL
 	sama5d3xek_nand_hw_init();
 #endif
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
 	sama5d3xek_nor_hw_init();
 #endif
 #ifdef CONFIG_CMD_USB
 	sama5d3xek_usb_hw_init();
 #endif
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-	at91_udp_hw_init();
-#endif
 #ifdef CONFIG_GENERIC_ATMEL_MCI
 	sama5d3xek_mci_hw_init();
 #endif
-#ifdef CONFIG_ATMEL_SPI
-	at91_spi0_hw_init(1 << 0);
-#endif
-#ifdef CONFIG_MACB
-	if (has_emac())
-		at91_macb_hw_init();
-	if (has_gmac())
-		at91_gmac_hw_init();
-#endif
 #ifdef CONFIG_LCD
 	if (has_lcdc())
 		sama5d3xek_lcd_hw_init();
@@ -271,104 +254,6 @@ int dram_init(void)
 	return 0;
 }
 
-int board_phy_config(struct phy_device *phydev)
-{
-	/* board specific timings for GMAC */
-	if (has_gmac()) {
-		/* rx data delay */
-		ksz9021_phy_extended_write(phydev,
-					   MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
-					   0x2222);
-		/* tx data delay */
-		ksz9021_phy_extended_write(phydev,
-					   MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
-					   0x2222);
-		/* rx/tx clock delay */
-		ksz9021_phy_extended_write(phydev,
-					   MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
-					   0xf2f4);
-	}
-
-	/* always run the PHY's config routine */
-	if (phydev->drv->config)
-		return phydev->drv->config(phydev);
-
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-
-#ifdef CONFIG_MACB
-	if (has_emac())
-		rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
-	if (has_gmac())
-		rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
-#endif
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-	usba_udc_probe(&pdata);
-#ifdef CONFIG_USB_ETH_RNDIS
-	usb_eth_initialize(bis);
-#endif
-#endif
-
-	return rc;
-}
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-int board_mmc_init(bd_t *bis)
-{
-	int rc = 0;
-
-	rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);
-
-	return rc;
-}
-#endif
-
-/* SPI chip select control */
-#ifdef CONFIG_ATMEL_SPI
-#include <spi.h>
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs < 4;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	switch (slave->cs) {
-	case 0:
-		at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
-	case 1:
-		at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
-	case 2:
-		at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
-	case 3:
-		at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
-	default:
-		break;
-	}
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	switch (slave->cs) {
-	case 0:
-		at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
-	case 1:
-		at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
-	case 2:
-		at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
-	case 3:
-		at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
-	default:
-		break;
-	}
-}
-#endif /* CONFIG_ATMEL_SPI */
-
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
@@ -392,12 +277,8 @@ int board_late_init(void)
 #ifdef CONFIG_SPL_BUILD
 void spl_board_init(void)
 {
-#ifdef CONFIG_SYS_USE_MMC
-	sama5d3xek_mci_hw_init();
-#elif CONFIG_SYS_USE_NANDFLASH
+#if CONFIG_SYS_USE_NANDFLASH
 	sama5d3xek_nand_hw_init();
-#elif CONFIG_SYS_USE_SERIALFLASH
-	at91_spi0_hw_init(1 << 0);
 #endif
 }
 
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index 23ec274..854afcb 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -10,52 +10,18 @@
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/atmel_mpddrc.h>
-#include <asm/arch/atmel_usba_udc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/sama5d3_smc.h>
 #include <asm/arch/sama5d4.h>
 #include <atmel_hlcdc.h>
-#include <atmel_mci.h>
+#include <debug_uart.h>
 #include <lcd.h>
-#include <mmc.h>
-#include <net.h>
-#include <netdev.h>
 #include <nand.h>
-#include <spi.h>
 #include <version.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_ATMEL_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
-}
-
-static void sama5d4_xplained_spi0_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* SPI0_SPCK */
-
-	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);	/* SPI0_CS0 */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_SPI0);
-}
-#endif /* CONFIG_ATMEL_SPI */
-
 #ifdef CONFIG_NAND_ATMEL
 static void sama5d4_xplained_nand_hw_init(void)
 {
@@ -82,20 +48,20 @@ static void sama5d4_xplained_nand_hw_init(void)
 	       AT91_SMC_MODE_TDF_CYCLE(3),
 	       &smc->cs[3].mode);
 
-	at91_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* D0 */
-	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* D1 */
-	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* D2 */
-	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* D3 */
-	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* D4 */
-	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* D5 */
-	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* D6 */
-	at91_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* D7 */
-	at91_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* RE */
-	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* WE */
-	at91_set_a_periph(AT91_PIO_PORTC, 15, 1);	/* NCS */
-	at91_set_a_periph(AT91_PIO_PORTC, 16, 1);	/* RDY */
-	at91_set_a_periph(AT91_PIO_PORTC, 17, 1);	/* ALE */
-	at91_set_a_periph(AT91_PIO_PORTC, 18, 1);	/* CLE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* D0 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* D1 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* D2 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* D3 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* D4 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* D5 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* D6 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* D7 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* RE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* WE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1);	/* NCS */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1);	/* RDY */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1);	/* ALE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1);	/* CLE */
 }
 #endif
 
@@ -134,39 +100,39 @@ unsigned int has_lcdc(void)
 
 static void sama5d4_xplained_lcd_hw_init(void)
 {
-	at91_set_a_periph(AT91_PIO_PORTA, 24, 0);	/* LCDPWM */
-	at91_set_a_periph(AT91_PIO_PORTA, 25, 0);	/* LCDDISP */
-	at91_set_a_periph(AT91_PIO_PORTA, 26, 0);	/* LCDVSYNC */
-	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* LCDHSYNC */
-	at91_set_a_periph(AT91_PIO_PORTA, 28, 0);	/* LCDDOTCK */
-	at91_set_a_periph(AT91_PIO_PORTA, 29, 0);	/* LCDDEN */
-
-	at91_set_a_periph(AT91_PIO_PORTA,  0, 0);	/* LCDD0 */
-	at91_set_a_periph(AT91_PIO_PORTA,  1, 0);	/* LCDD1 */
-	at91_set_a_periph(AT91_PIO_PORTA,  2, 0);	/* LCDD2 */
-	at91_set_a_periph(AT91_PIO_PORTA,  3, 0);	/* LCDD3 */
-	at91_set_a_periph(AT91_PIO_PORTA,  4, 0);	/* LCDD4 */
-	at91_set_a_periph(AT91_PIO_PORTA,  5, 0);	/* LCDD5 */
-	at91_set_a_periph(AT91_PIO_PORTA,  6, 0);	/* LCDD6 */
-	at91_set_a_periph(AT91_PIO_PORTA,  7, 0);	/* LCDD7 */
-
-	at91_set_a_periph(AT91_PIO_PORTA,  8, 0);	/* LCDD9 */
-	at91_set_a_periph(AT91_PIO_PORTA,  9, 0);	/* LCDD8 */
-	at91_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* LCDD10 */
-	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* LCDD11 */
-	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* LCDD12 */
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* LCDD13 */
-	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* LCDD14 */
-	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* LCDD15 */
-
-	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* LCDD16 */
-	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* LCDD17 */
-	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* LCDD18 */
-	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* LCDD19 */
-	at91_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* LCDD20 */
-	at91_set_a_periph(AT91_PIO_PORTA, 21, 0);	/* LCDD21 */
-	at91_set_a_periph(AT91_PIO_PORTA, 22, 0);	/* LCDD22 */
-	at91_set_a_periph(AT91_PIO_PORTA, 23, 0);	/* LCDD23 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0);	/* LCDPWM */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0);	/* LCDDISP */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0);	/* LCDVSYNC */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* LCDHSYNC */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0);	/* LCDDOTCK */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0);	/* LCDDEN */
+
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  0, 0);	/* LCDD0 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  1, 0);	/* LCDD1 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  2, 0);	/* LCDD2 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  3, 0);	/* LCDD3 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  4, 0);	/* LCDD4 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  5, 0);	/* LCDD5 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  6, 0);	/* LCDD6 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  7, 0);	/* LCDD7 */
+
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  8, 0);	/* LCDD9 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  9, 0);	/* LCDD8 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* LCDD10 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* LCDD11 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* LCDD12 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* LCDD13 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* LCDD14 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* LCDD15 */
+
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* LCDD16 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* LCDD17 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* LCDD18 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* LCDD19 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* LCDD20 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0);	/* LCDD21 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0);	/* LCDD22 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0);	/* LCDD23 */
 
 	/* Enable clock */
 	at91_periph_clk_enable(ATMEL_ID_LCDC);
@@ -191,7 +157,7 @@ void lcd_show_board_info(void)
 	nand_size = 0;
 #ifdef CONFIG_NAND_ATMEL
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i]->size;
+		nand_size += get_nand_dev_by_index(i)->size;
 #endif
 	lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
 		   dram_size >> 20, nand_size >> 20);
@@ -200,109 +166,46 @@ void lcd_show_board_info(void)
 
 #endif /* CONFIG_LCD */
 
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-void sama5d4_xplained_mci1_hw_init(void)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+static void sama5d4_xplained_serial3_hw_init(void)
 {
-	at91_set_c_periph(AT91_PIO_PORTE, 19, 1);	/* MCI1 CDA */
-	at91_set_c_periph(AT91_PIO_PORTE, 20, 1);	/* MCI1 DA0 */
-	at91_set_c_periph(AT91_PIO_PORTE, 21, 1);	/* MCI1 DA1 */
-	at91_set_c_periph(AT91_PIO_PORTE, 22, 1);	/* MCI1 DA2 */
-	at91_set_c_periph(AT91_PIO_PORTE, 23, 1);	/* MCI1 DA3 */
-	at91_set_c_periph(AT91_PIO_PORTE, 18, 0);	/* MCI1 CLK */
-
-	/*
-	 * As the mci io internal pull down is too strong, so if the io needs
-	 * external pull up, the pull up resistor will be very small, if so
-	 * the power consumption will increase, so disable the interanl pull
-	 * down to save the power.
-	 */
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
+	at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1);	/* TXD3 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0);	/* RXD3 */
 
 	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_MCI1);
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	/* Enable the power supply */
-	at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
-
-	return atmel_mci_init((void *)ATMEL_BASE_MCI1);
+	at91_periph_clk_enable(ATMEL_ID_USART3);
 }
-#endif /* CONFIG_GENERIC_ATMEL_MCI */
 
-#ifdef CONFIG_MACB
-void sama5d4_xplained_macb0_hw_init(void)
+void board_debug_uart_init(void)
 {
-	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* ETXCK_EREFCK */
-	at91_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* ERXDV */
-	at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* ERX0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* ERX1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* ERXER */
-	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* ETXEN */
-	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* ETX0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* ETX1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* EMDIO */
-	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* EMDC */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_GMAC0);
+	sama5d4_xplained_serial3_hw_init();
 }
 #endif
 
-static void sama5d4_xplained_serial3_hw_init(void)
-{
-	at91_set_b_periph(AT91_PIO_PORTE, 17, 1);	/* TXD3 */
-	at91_set_b_periph(AT91_PIO_PORTE, 16, 0);	/* RXD3 */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_USART3);
-}
-
+#ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-	at91_periph_clk_enable(ATMEL_ID_PIOA);
-	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	at91_periph_clk_enable(ATMEL_ID_PIOC);
-	at91_periph_clk_enable(ATMEL_ID_PIOD);
-	at91_periph_clk_enable(ATMEL_ID_PIOE);
-
-	sama5d4_xplained_serial3_hw_init();
-
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
 	return 0;
 }
+#endif
 
 int board_init(void)
 {
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-#ifdef CONFIG_ATMEL_SPI
-	sama5d4_xplained_spi0_hw_init();
-#endif
 #ifdef CONFIG_NAND_ATMEL
 	sama5d4_xplained_nand_hw_init();
 #endif
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-	sama5d4_xplained_mci1_hw_init();
-#endif
-#ifdef CONFIG_MACB
-	sama5d4_xplained_macb0_hw_init();
-#endif
 #ifdef CONFIG_LCD
 	sama5d4_xplained_lcd_hw_init();
 #endif
 #ifdef CONFIG_CMD_USB
 	sama5d4_xplained_usb_hw_init();
 #endif
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-	at91_udp_hw_init();
-#endif
 
 	return 0;
 }
@@ -314,34 +217,12 @@ int dram_init(void)
 	return 0;
 }
 
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-
-#ifdef CONFIG_MACB
-	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
-#endif
-
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-	usba_udc_probe(&pdata);
-#ifdef CONFIG_USB_ETH_RNDIS
-	usb_eth_initialize(bis);
-#endif
-#endif
-
-	return rc;
-}
-
 /* SPL */
 #ifdef CONFIG_SPL_BUILD
 void spl_board_init(void)
 {
-#ifdef CONFIG_SYS_USE_MMC
-	sama5d4_xplained_mci1_hw_init();
-#elif CONFIG_SYS_USE_NANDFLASH
+#if CONFIG_SYS_USE_NANDFLASH
 	sama5d4_xplained_nand_hw_init();
-#elif CONFIG_SYS_USE_SERIALFLASH
-	sama5d4_xplained_spi0_hw_init();
 #endif
 }
 
diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c
index 72bad23..ba79746 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -10,52 +10,18 @@
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/atmel_mpddrc.h>
-#include <asm/arch/atmel_usba_udc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/sama5d3_smc.h>
 #include <asm/arch/sama5d4.h>
 #include <atmel_hlcdc.h>
-#include <atmel_mci.h>
+#include <debug_uart.h>
 #include <lcd.h>
-#include <mmc.h>
-#include <net.h>
-#include <netdev.h>
 #include <nand.h>
-#include <spi.h>
 #include <version.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_ATMEL_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
-}
-
-static void sama5d4ek_spi0_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* SPI0_SPCK */
-
-	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);	/* SPI0_CS0 */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_SPI0);
-}
-#endif /* CONFIG_ATMEL_SPI */
-
 #ifdef CONFIG_NAND_ATMEL
 static void sama5d4ek_nand_hw_init(void)
 {
@@ -82,20 +48,20 @@ static void sama5d4ek_nand_hw_init(void)
 	       AT91_SMC_MODE_TDF_CYCLE(3),
 	       &smc->cs[3].mode);
 
-	at91_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* D0 */
-	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* D1 */
-	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* D2 */
-	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* D3 */
-	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* D4 */
-	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* D5 */
-	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* D6 */
-	at91_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* D7 */
-	at91_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* RE */
-	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* WE */
-	at91_set_a_periph(AT91_PIO_PORTC, 15, 1);	/* NCS */
-	at91_set_a_periph(AT91_PIO_PORTC, 16, 1);	/* RDY */
-	at91_set_a_periph(AT91_PIO_PORTC, 17, 1);	/* ALE */
-	at91_set_a_periph(AT91_PIO_PORTC, 18, 1);	/* CLE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* D0 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* D1 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* D2 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* D3 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* D4 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* D5 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* D6 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0);	/* D7 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0);	/* RE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* WE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1);	/* NCS */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1);	/* RDY */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1);	/* ALE */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1);	/* CLE */
 }
 #endif
 
@@ -135,33 +101,33 @@ unsigned int has_lcdc(void)
 
 static void sama5d4ek_lcd_hw_init(void)
 {
-	at91_set_a_periph(AT91_PIO_PORTA, 24, 0);	/* LCDPWM */
-	at91_set_a_periph(AT91_PIO_PORTA, 25, 0);	/* LCDDISP */
-	at91_set_a_periph(AT91_PIO_PORTA, 26, 0);	/* LCDVSYNC */
-	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* LCDHSYNC */
-	at91_set_a_periph(AT91_PIO_PORTA, 28, 0);	/* LCDDOTCK */
-	at91_set_a_periph(AT91_PIO_PORTA, 29, 0);	/* LCDDEN */
-
-	at91_set_a_periph(AT91_PIO_PORTA,  2, 0);	/* LCDD2 */
-	at91_set_a_periph(AT91_PIO_PORTA,  3, 0);	/* LCDD3 */
-	at91_set_a_periph(AT91_PIO_PORTA,  4, 0);	/* LCDD4 */
-	at91_set_a_periph(AT91_PIO_PORTA,  5, 0);	/* LCDD5 */
-	at91_set_a_periph(AT91_PIO_PORTA,  6, 0);	/* LCDD6 */
-	at91_set_a_periph(AT91_PIO_PORTA,  7, 0);	/* LCDD7 */
-
-	at91_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* LCDD10 */
-	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* LCDD11 */
-	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* LCDD12 */
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* LCDD13 */
-	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* LCDD14 */
-	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* LCDD15 */
-
-	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* LCDD18 */
-	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* LCDD19 */
-	at91_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* LCDD20 */
-	at91_set_a_periph(AT91_PIO_PORTA, 21, 0);	/* LCDD21 */
-	at91_set_a_periph(AT91_PIO_PORTA, 22, 0);	/* LCDD22 */
-	at91_set_a_periph(AT91_PIO_PORTA, 23, 0);	/* LCDD23 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0);	/* LCDPWM */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0);	/* LCDDISP */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0);	/* LCDVSYNC */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* LCDHSYNC */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0);	/* LCDDOTCK */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0);	/* LCDDEN */
+
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  2, 0);	/* LCDD2 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  3, 0);	/* LCDD3 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  4, 0);	/* LCDD4 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  5, 0);	/* LCDD5 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  6, 0);	/* LCDD6 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA,  7, 0);	/* LCDD7 */
+
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* LCDD10 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* LCDD11 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* LCDD12 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* LCDD13 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* LCDD14 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* LCDD15 */
+
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* LCDD18 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* LCDD19 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* LCDD20 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0);	/* LCDD21 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0);	/* LCDD22 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0);	/* LCDD23 */
 
 	/* Enable clock */
 	at91_periph_clk_enable(ATMEL_ID_LCDC);
@@ -187,7 +153,7 @@ void lcd_show_board_info(void)
 	nand_size = 0;
 #ifdef CONFIG_NAND_ATMEL
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i]->size;
+		nand_size += get_nand_dev_by_index(i)->size;
 #endif
 	lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
 		   dram_size >> 20, nand_size >> 20);
@@ -196,109 +162,46 @@ void lcd_show_board_info(void)
 
 #endif /* CONFIG_LCD */
 
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-void sama5d4ek_mci1_hw_init(void)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+static void sama5d4ek_serial3_hw_init(void)
 {
-	at91_set_c_periph(AT91_PIO_PORTE, 19, 1);	/* MCI1 CDA */
-	at91_set_c_periph(AT91_PIO_PORTE, 20, 1);	/* MCI1 DA0 */
-	at91_set_c_periph(AT91_PIO_PORTE, 21, 1);	/* MCI1 DA1 */
-	at91_set_c_periph(AT91_PIO_PORTE, 22, 1);	/* MCI1 DA2 */
-	at91_set_c_periph(AT91_PIO_PORTE, 23, 1);	/* MCI1 DA3 */
-	at91_set_c_periph(AT91_PIO_PORTE, 18, 0);	/* MCI1 CLK */
-
-	/*
-	 * As the mci io internal pull down is too strong, so if the io needs
-	 * external pull up, the pull up resistor will be very small, if so
-	 * the power consumption will increase, so disable the interanl pull
-	 * down to save the power.
-	 */
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
+	at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1);	/* TXD3 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0);	/* RXD3 */
 
 	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_MCI1);
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	/* Enable power for MCI1 interface */
-	at91_set_pio_output(AT91_PIO_PORTE, 15, 0);
-
-	return atmel_mci_init((void *)ATMEL_BASE_MCI1);
+	at91_periph_clk_enable(ATMEL_ID_USART3);
 }
-#endif /* CONFIG_GENERIC_ATMEL_MCI */
 
-#ifdef CONFIG_MACB
-void sama5d4ek_macb0_hw_init(void)
+void board_debug_uart_init(void)
 {
-	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* ETXCK_EREFCK */
-	at91_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* ERXDV */
-	at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* ERX0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* ERX1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* ERXER */
-	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* ETXEN */
-	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* ETX0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* ETX1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* EMDIO */
-	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* EMDC */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_GMAC0);
+	sama5d4ek_serial3_hw_init();
 }
 #endif
 
-static void sama5d4ek_serial3_hw_init(void)
-{
-	at91_set_b_periph(AT91_PIO_PORTE, 17, 1);	/* TXD3 */
-	at91_set_b_periph(AT91_PIO_PORTE, 16, 0);	/* RXD3 */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_USART3);
-}
-
+#ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-	at91_periph_clk_enable(ATMEL_ID_PIOA);
-	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	at91_periph_clk_enable(ATMEL_ID_PIOC);
-	at91_periph_clk_enable(ATMEL_ID_PIOD);
-	at91_periph_clk_enable(ATMEL_ID_PIOE);
-
-	sama5d4ek_serial3_hw_init();
-
+#ifdef CONFIG_DEBUG_UART
+	debug_uart_init();
+#endif
 	return 0;
 }
+#endif
 
 int board_init(void)
 {
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-#ifdef CONFIG_ATMEL_SPI
-	sama5d4ek_spi0_hw_init();
-#endif
 #ifdef CONFIG_NAND_ATMEL
 	sama5d4ek_nand_hw_init();
 #endif
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-	sama5d4ek_mci1_hw_init();
-#endif
-#ifdef CONFIG_MACB
-	sama5d4ek_macb0_hw_init();
-#endif
 #ifdef CONFIG_LCD
 	sama5d4ek_lcd_hw_init();
 #endif
 #ifdef CONFIG_CMD_USB
 	sama5d4ek_usb_hw_init();
 #endif
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-	at91_udp_hw_init();
-#endif
 
 	return 0;
 }
@@ -310,34 +213,12 @@ int dram_init(void)
 	return 0;
 }
 
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-
-#ifdef CONFIG_MACB
-	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
-#endif
-
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-	usba_udc_probe(&pdata);
-#ifdef CONFIG_USB_ETH_RNDIS
-	usb_eth_initialize(bis);
-#endif
-#endif
-
-	return rc;
-}
-
 /* SPL */
 #ifdef CONFIG_SPL_BUILD
 void spl_board_init(void)
 {
-#ifdef CONFIG_SYS_USE_MMC
-	sama5d4ek_mci1_hw_init();
-#elif CONFIG_SYS_USE_NANDFLASH
+#if CONFIG_SYS_USE_NANDFLASH
 	sama5d4ek_nand_hw_init();
-#elif CONFIG_SYS_USE_SERIALFLASH
-	sama5d4ek_spi0_hw_init();
 #endif
 }
 
@@ -349,7 +230,6 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 		    ATMEL_MPDDRC_CR_NR_ROW_14 |
 		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 		    ATMEL_MPDDRC_CR_NB_8BANKS |
-		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
 		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 
@@ -379,6 +259,8 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 void mem_init(void)
 {
 	struct atmel_mpddrc_config ddr2;
+	const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+	u32 tmp;
 
 	ddr2_conf(&ddr2);
 
@@ -386,6 +268,19 @@ void mem_init(void)
 	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
 	at91_system_clk_enable(AT91_PMC_DDR);
 
+	tmp = ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE;
+	writel(tmp, &mpddr->rd_data_path);
+
+	tmp = readl(&mpddr->io_calibr);
+	tmp = (tmp & ~(ATMEL_MPDDRC_IO_CALIBR_RDIV |
+	       ATMEL_MPDDRC_IO_CALIBR_TZQIO |
+	       ATMEL_MPDDRC_IO_CALIBR_CALCODEP |
+	       ATMEL_MPDDRC_IO_CALIBR_CALCODEN)) |
+	       ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 |
+	       ATMEL_MPDDRC_IO_CALIBR_TZQIO_(8) |
+	       ATMEL_MPDDRC_IO_CALIBR_EN_CALIB;
+	writel(tmp, &mpddr->io_calibr);
+
 	/* DDRAM2 Controller initialize */
 	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
 }
diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c
index 4fb36a2..f78c007 100644
--- a/board/avionic-design/common/tamonten.c
+++ b/board/avionic-design/common/tamonten.c
@@ -28,7 +28,7 @@ void gpio_early_init(void)
 }
 #endif
 
-#ifdef CONFIG_TEGRA_MMC
+#ifdef CONFIG_MMC_SDHCI_TEGRA
 /*
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
index eeced79..1ad4ef9 100644
--- a/board/bachmann/ot1200/ot1200.c
+++ b/board/bachmann/ot1200/ot1200.c
@@ -12,10 +12,10 @@
 #include <asm/arch/iomux.h>
 #include <malloc.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/sys_proto.h>
 #include <mmc.h>
@@ -273,10 +273,6 @@ int board_mmc_init(bd_t *bis)
 	return 0;
 }
 
-static iomux_v3_cfg_t const pwm_pad[] = {
-	MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM),
-};
-
 static void leds_on(void)
 {
 	/* turn on all possible leds connected via GPIO expander */
@@ -342,7 +338,7 @@ int board_init(void)
 
 	leds_on();
 
-#ifdef CONFIG_CMD_SATA
+#ifdef CONFIG_SATA
 	setup_sata();
 #endif
 
diff --git a/board/barco/platinum/platinum.c b/board/barco/platinum/platinum.c
index 1485a48..f74fa13 100644
--- a/board/barco/platinum/platinum.c
+++ b/board/barco/platinum/platinum.c
@@ -18,8 +18,8 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
 
 #include "platinum.h"
 
diff --git a/board/barco/platinum/platinum_picon.c b/board/barco/platinum/platinum_picon.c
index 0384a26..716aec2 100644
--- a/board/barco/platinum/platinum_picon.c
+++ b/board/barco/platinum/platinum_picon.c
@@ -11,8 +11,8 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
 #include <i2c.h>
 #include <miiphy.h>
 
diff --git a/board/barco/platinum/platinum_titanium.c b/board/barco/platinum/platinum_titanium.c
index 73a955f..bbcd1c5 100644
--- a/board/barco/platinum/platinum_titanium.c
+++ b/board/barco/platinum/platinum_titanium.c
@@ -9,8 +9,8 @@
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
 #include <miiphy.h>
 #include <micrel.h>
 
diff --git a/board/barco/platinum/spl_picon.c b/board/barco/platinum/spl_picon.c
index ec57cf1..f49adf0 100644
--- a/board/barco/platinum/spl_picon.c
+++ b/board/barco/platinum/spl_picon.c
@@ -14,9 +14,9 @@
 #include <asm/arch/mx6-ddr.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
 #include <spl.h>
 
 #include "platinum.h"
diff --git a/board/barco/platinum/spl_titanium.c b/board/barco/platinum/spl_titanium.c
index d1ba85a..c27fb48 100644
--- a/board/barco/platinum/spl_titanium.c
+++ b/board/barco/platinum/spl_titanium.c
@@ -14,9 +14,9 @@
 #include <asm/arch/mx6-ddr.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
 #include <spl.h>
 
 #include "platinum.h"
diff --git a/board/barco/titanium/imximage.cfg b/board/barco/titanium/imximage.cfg
index 7219256..4fb6982 100644
--- a/board/barco/titanium/imximage.cfg
+++ b/board/barco/titanium/imximage.cfg
@@ -7,7 +7,7 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/barco/titanium/titanium.c b/board/barco/titanium/titanium.c
index 84a7b84..caa598d 100644
--- a/board/barco/titanium/titanium.c
+++ b/board/barco/titanium/titanium.c
@@ -13,9 +13,9 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <micrel.h>
diff --git a/board/bct-brettl2/Kconfig b/board/bct-brettl2/Kconfig
deleted file mode 100644
index 9c5407e..0000000
--- a/board/bct-brettl2/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BCT_BRETTL2
-
-config SYS_BOARD
-	default "bct-brettl2"
-
-config SYS_CONFIG_NAME
-	default "bct-brettl2"
-
-endif
diff --git a/board/bct-brettl2/MAINTAINERS b/board/bct-brettl2/MAINTAINERS
deleted file mode 100644
index 32245d4..0000000
--- a/board/bct-brettl2/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BCT-BRETTL2 BOARD
-M:	Peter Meerwald <devel@bct-electronic.com>
-S:	Maintained
-F:	board/bct-brettl2/
-F:	include/configs/bct-brettl2.h
-F:	configs/bct-brettl2_defconfig
diff --git a/board/bct-brettl2/Makefile b/board/bct-brettl2/Makefile
deleted file mode 100644
index 28fccc0..0000000
--- a/board/bct-brettl2/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bct-brettl2.o gpio_cfi_flash.o cled.o
-obj-$(CONFIG_BFIN_MAC) += smsc9303.o
diff --git a/board/bct-brettl2/bct-brettl2.c b/board/bct-brettl2/bct-brettl2.c
deleted file mode 100644
index adb8605..0000000
--- a/board/bct-brettl2/bct-brettl2.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * U-Boot - main board file for BCT brettl2
- *
- * Copyright (c) 2010 BCT Electronic GmbH
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-#include <asm/gpio.h>
-#include <net.h>
-#include <netdev.h>
-#include <miiphy.h>
-
-#include "../cm-bf537e/gpio_cfi_flash.h"
-#include "smsc9303.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: bct-brettl2 board\n");
-	printf("       Support: http://www.bct-electronic.com/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
-	int retry = 3;
-	int ret;
-
-	ret = bfin_EMAC_initialize(bis);
-
-	uchar enetaddr[6];
-	if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
-		printf("setting MAC %pM\n", enetaddr);
-	}
-	puts("       ");
-
-	puts("initialize SMSC LAN9303i ethernet switch\n");
-
-	while (retry-- > 0) {
-		if (init_smsc9303i_mii())
-			return ret;
-	}
-
-	return ret;
-}
-#endif
-
-static void init_tlv320aic31(void)
-{
-	puts("Audio: setup TIMER0 to enable 16.384 MHz clock for tlv320aic31\n");
-	peripheral_request(P_TMR0, "tlv320aic31 clock");
-	bfin_write_TIMER0_CONFIG(0x020d);
-	bfin_write_TIMER0_PERIOD(0x0008);
-	bfin_write_TIMER0_WIDTH(0x0008/2);
-	bfin_write_TIMER_ENABLE(bfin_read_TIMER_ENABLE() | 1);
-	SSYNC();
-	udelay(10000);
-
-	puts("       resetting tlv320aic31\n");
-
-	gpio_request(GPIO_PF2, "tlv320aic31");
-	gpio_direction_output(GPIO_PF2, 0);
-	udelay(10000);
-	gpio_direction_output(GPIO_PF2, 1);
-	udelay(10000);
-	gpio_free(GPIO_PF2);
-}
-
-static void init_mute_pin(void)
-{
-	printf("       unmute class D amplifier\n");
-
-	gpio_request(GPIO_PF5, "mute");
-	gpio_direction_output(GPIO_PF5, 1);
-	gpio_free(GPIO_PF5);
-}
-
-/* sometimes LEDs (speech, status) are still on after reboot, turn 'em off */
-static void turn_leds_off(void)
-{
-	printf("       turn LEDs off\n");
-
-	gpio_request(GPIO_PF6, "led");
-	gpio_direction_output(GPIO_PF6, 0);
-	gpio_free(GPIO_PF6);
-
-	gpio_request(GPIO_PF15, "led");
-	gpio_direction_output(GPIO_PF15, 0);
-	gpio_free(GPIO_PF15);
-}
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
-	gpio_cfi_flash_init();
-	init_tlv320aic31();
-	init_mute_pin();
-	turn_leds_off();
-
-	return 0;
-}
diff --git a/board/bct-brettl2/cled.c b/board/bct-brettl2/cled.c
deleted file mode 100644
index dcb91bd..0000000
--- a/board/bct-brettl2/cled.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * cled.c - control color led
- *
- * Copyright (c) 2010 BCT Electronic GmbH
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include <asm/io.h>
-
-int do_cled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong addr = 0x20000000 + 0x200000; /* AMS2 */
-	uchar data;
-
-	if (argc < 2)
-		return cmd_usage(cmdtp);
-
-	data = simple_strtoul(argv[1], NULL, 10);
-	outb(data, addr);
-
-	printf("cled, write %02x\n", data);
-
-	return 0;
-}
-
-U_BOOT_CMD(cled, 2, 0, do_cled,
-	"set/clear color LED",
-	"");
diff --git a/board/bct-brettl2/gpio_cfi_flash.c b/board/bct-brettl2/gpio_cfi_flash.c
deleted file mode 100644
index b385c7f..0000000
--- a/board/bct-brettl2/gpio_cfi_flash.c
+++ /dev/null
@@ -1,4 +0,0 @@
-#define GPIO_PIN_1 GPIO_PG5
-#define GPIO_PIN_2 GPIO_PG6
-#define GPIO_PIN_3 GPIO_PG7
-#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/bct-brettl2/smsc9303.c b/board/bct-brettl2/smsc9303.c
deleted file mode 100644
index 15eea7a..0000000
--- a/board/bct-brettl2/smsc9303.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * smsc9303.c - routines to initialize SMSC 9303 switch
- *
- * Copyright (c) 2010 BCT Electronic GmbH
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <miiphy.h>
-
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-
-static int smc9303i_write_mii(unsigned char addr, unsigned char reg, unsigned short data)
-{
-	const char *devname = miiphy_get_current_dev();
-
-	if (!devname)
-	    return 0;
-
-	if (miiphy_write(devname, addr, reg, data) != 0)
-	    return 0;
-
-	return 1;
-}
-
-static int smc9303i_write_reg(unsigned short reg, unsigned int data)
-{
-	const char *devname = miiphy_get_current_dev();
-	unsigned char mii_addr = 0x10 | (reg >> 6);
-	unsigned char mii_reg = (reg & 0x3c) >> 1;
-
-	if (!devname)
-	    return 0;
-
-	if (miiphy_write(devname, mii_addr, mii_reg|0, data & 0xffff) != 0)
-	    return 0;
-
-	if (miiphy_write(devname, mii_addr, mii_reg|1, data >> 16) != 0)
-	    return 0;
-
-	return 1;
-}
-
-static int smc9303i_read_reg(unsigned short reg, unsigned int *data)
-{
-	const char *devname = miiphy_get_current_dev();
-	unsigned char mii_addr = 0x10 | (reg >> 6);
-	unsigned char mii_reg = (reg & 0x3c) >> 1;
-	unsigned short tmp1, tmp2;
-
-	if (!devname)
-	    return 0;
-
-	if (miiphy_read(devname, mii_addr, mii_reg|0, &tmp1) != 0)
-	    return 0;
-
-	if (miiphy_read(devname, mii_addr, mii_reg|1, &tmp2) != 0)
-	    return 0;
-
-	*data = (tmp2 << 16) | tmp1;
-
-	return 1;
-}
-
-#if 0
-static int smc9303i_read_mii(unsigned char addr, unsigned char reg, unsigned short *data)
-{
-	const char *devname = miiphy_get_current_dev();
-
-	if (!devname)
-	    return 0;
-
-	if (miiphy_read(devname, addr, reg, data) != 0)
-	    return 0;
-
-	return 1;
-}
-#endif
-
-typedef struct {
-	unsigned short reg;
-	unsigned int value;
-} smsc9303i_config_entry1_t;
-
-static const smsc9303i_config_entry1_t smsc9303i_config_table1[] =
-{
-	{0x1a0, 0x00000006}, /* Port 1 Manual Flow Control Register */
-	{0x1a4, 0x00000006}, /* Port 2 Manual Flow Control Register */
-	{0x1a8, 0x00000006}, /* Port 0 Manual Flow Control Register */
-};
-
-typedef struct
-{
-	unsigned char addr;
-	unsigned char reg;
-	unsigned short value;
-} smsc9303i_config_entry2_t;
-
-static const smsc9303i_config_entry2_t smsc9303i_config_table2[] =
-{
-	{0x01, 0x00, 0x0100}, /* Port0 PHY Basic Control Register */
-	{0x02, 0x00, 0x1100}, /* Port1 PHY Basic Control Register */
-	{0x03, 0x00, 0x1100}, /* Port2 PHY Basic Control Register */
-
-	{0x01, 0x04, 0x0001}, /* Port0 PHY Auto-Negotiation Advertisement Register */
-	{0x02, 0x04, 0x2de1}, /* Port1 PHY Auto-Negotiation Advertisement Register */
-	{0x03, 0x04, 0x2de1}, /* Port2 PHY Auto-Negotiation Advertisement Register */
-
-	{0x01, 0x11, 0x0000}, /* Port0 PHY Mode Control/Status Register */
-	{0x02, 0x11, 0x0000}, /* Port1 PHY Mode Control/Status Register */
-	{0x03, 0x11, 0x0000}, /* Port2 PHY Mode Control/Status Register */
-
-	{0x01, 0x12, 0x0021}, /* Port0 PHY Special Modes Register */
-	{0x02, 0x12, 0x00e2}, /* Port1 PHY Special Modes Register */
-	{0x03, 0x12, 0x00e3}, /* Port2 PHY Special Modes Register */
-	{0x01, 0x1b, 0x0000}, /* Port0 PHY Special Control/Status Indication Register */
-	{0x02, 0x1b, 0x0000}, /* Port1 PHY Special Control/Status Indication Register */
-	{0x03, 0x1b, 0x0000}, /* Port2 PHY Special Control/Status Indication Register */
-	{0x01, 0x1e, 0x0000}, /* Port0 PHY Interrupt Source Flags Register */
-	{0x02, 0x1e, 0x0000}, /* Port1 PHY Interrupt Source Flags Register */
-	{0x03, 0x1e, 0x0000}, /* Port2 PHY Interrupt Source Flags Register */
-};
-
-int init_smsc9303i_mii(void)
-{
-	unsigned int data;
-	unsigned int i;
-
-	printf("       reset SMSC LAN9303i\n");
-
-	gpio_request(GPIO_PG10, "smsc9303");
-	gpio_direction_output(GPIO_PG10, 0);
-	udelay(10000);
-	gpio_direction_output(GPIO_PG10, 1);
-	udelay(10000);
-
-	gpio_free(GPIO_PG10);
-
-#if defined(CONFIG_MII_INIT)
-	mii_init();
-#endif
-
-	printf("       write SMSC LAN9303i configuration\n");
-
-	if (!smc9303i_read_reg(0x50, &data))
-		return 0;
-
-	if ((data >> 16) != 0x9303)	{
-		/* chip id not found */
-		printf("       error identifying SMSC LAN9303i\n");
-		return 0;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table1); i++) {
-		const smsc9303i_config_entry1_t *entry = &smsc9303i_config_table1[i];
-
-		if (!smc9303i_write_reg(entry->reg, entry->value)) {
-			printf("       error writing SMSC LAN9303i configuration\n");
-			return 0;
-		}
-	}
-
-	for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table2); i++) {
-		const smsc9303i_config_entry2_t *entry = &smsc9303i_config_table2[i];
-
-		if (!smc9303i_write_mii(entry->addr, entry->reg, entry->value)) {
-			printf("       error writing SMSC LAN9303i configuration\n");
-			return 0;
-		}
-	}
-
-	return 1;
-}
diff --git a/board/bct-brettl2/smsc9303.h b/board/bct-brettl2/smsc9303.h
deleted file mode 100644
index a4ba40e..0000000
--- a/board/bct-brettl2/smsc9303.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * smsc9303.h - routines to initialize SMSC 9303 switch
- *
- * Copyright (c) 2010 BCT Electronic GmbH
- *
- * Licensed under the GPL-2 or later.
- */
-
-int init_smsc9303i_mii(void);
diff --git a/board/beckhoff/mx53cx9020/Kconfig b/board/beckhoff/mx53cx9020/Kconfig
new file mode 100644
index 0000000..dcdafb6
--- /dev/null
+++ b/board/beckhoff/mx53cx9020/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX53CX9020
+
+config SYS_BOARD
+	default "mx53cx9020"
+
+config SYS_VENDOR
+	default "beckhoff"
+
+config SYS_CONFIG_NAME
+	default "mx53cx9020"
+
+endif
diff --git a/board/beckhoff/mx53cx9020/MAINTAINERS b/board/beckhoff/mx53cx9020/MAINTAINERS
new file mode 100644
index 0000000..f84413e
--- /dev/null
+++ b/board/beckhoff/mx53cx9020/MAINTAINERS
@@ -0,0 +1,6 @@
+MX53 CX9020
+M:	Patrick Bruenn <p.bruenn@beckhoff.com>
+S:	Maintained
+F:	board/beckhoff/mx53cx9020/
+F:	include/configs/mx53cx9020.h
+F:	configs/mx53cx9020_defconfig
diff --git a/board/beckhoff/mx53cx9020/Makefile b/board/beckhoff/mx53cx9020/Makefile
new file mode 100644
index 0000000..a01c0f1
--- /dev/null
+++ b/board/beckhoff/mx53cx9020/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2015  Beckhoff Automation GmbH & Co. KG
+# Patrick Bruenn <p.bruenn@beckhoff.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y               += mx53cx9020.o
+obj-$(CONFIG_VIDEO) += mx53cx9020_video.o
diff --git a/board/beckhoff/mx53cx9020/imximage.cfg b/board/beckhoff/mx53cx9020/imximage.cfg
new file mode 100644
index 0000000..a11d04c
--- /dev/null
+++ b/board/beckhoff/mx53cx9020/imximage.cfg
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2015  Beckhoff Automation GmbH
+ * Patrick Bruenn <p.bruenn@beckhoff.com>
+ *
+ * Based on <u-boot>/board/freescale/mx53loco/imximage.cfg
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x53fa8554 0x00300000
+DATA 4 0x53fa8558 0x00300040
+DATA 4 0x53fa8560 0x00300000
+DATA 4 0x53fa8564 0x00300040
+DATA 4 0x53fa8568 0x00300040
+DATA 4 0x53fa8570 0x00300000
+DATA 4 0x53fa8574 0x00300000
+DATA 4 0x53fa8578 0x00300000
+DATA 4 0x53fa857c 0x00300040
+DATA 4 0x53fa8580 0x00300040
+DATA 4 0x53fa8584 0x00300000
+DATA 4 0x53fa8588 0x00300000
+DATA 4 0x53fa8590 0x00300040
+DATA 4 0x53fa8594 0x00300000
+DATA 4 0x53fa86f0 0x00300000
+DATA 4 0x53fa86f4 0x00000000
+DATA 4 0x53fa86fc 0x00000000
+DATA 4 0x53fa8714 0x00000000
+DATA 4 0x53fa8718 0x00300000
+DATA 4 0x53fa871c 0x00300000
+DATA 4 0x53fa8720 0x00300000
+DATA 4 0x53fa8724 0x00000000
+DATA 4 0x53fa8728 0x00300000
+DATA 4 0x53fa872c 0x00300000
+DATA 4 0x63fd9088 0x35343535
+DATA 4 0x63fd9090 0x4d444c44
+DATA 4 0x63fd907c 0x01370138
+DATA 4 0x63fd9080 0x013b013c
+DATA 4 0x63fd9018 0x00011740
+DATA 4 0x63fd9000 0x83190000
+DATA 4 0x63fd900c 0x40425333
+DATA 4 0x63fd9010 0xb68e8a63
+DATA 4 0x63fd9014 0x01ff00db
+DATA 4 0x63fd902c 0x000026d2
+DATA 4 0x63fd9030 0x009f0e21
+DATA 4 0x63fd9008 0x12273030
+DATA 4 0x63fd9004 0x0002002d
+DATA 4 0x63fd901c 0x00008032
+DATA 4 0x63fd901c 0x00008033
+DATA 4 0x63fd901c 0x00028031
+DATA 4 0x63fd901c 0x052080b0
+DATA 4 0x63fd901c 0x04008040
+DATA 4 0x63fd9000 0xc3190000
+DATA 4 0x63fd901c 0x0000803a
+DATA 4 0x63fd901c 0x0000803b
+DATA 4 0x63fd901c 0x00028039
+DATA 4 0x63fd901c 0x05208138
+DATA 4 0x63fd901c 0x04008048
+DATA 4 0x63fd9020 0x00005800
+DATA 4 0x63fd9040 0x05380003
+DATA 4 0x63fd9058 0x00022227
+DATA 4 0x63fd901c 0x00000000
diff --git a/board/beckhoff/mx53cx9020/mx53cx9020.c b/board/beckhoff/mx53cx9020/mx53cx9020.c
new file mode 100644
index 0000000..a18a4e8
--- /dev/null
+++ b/board/beckhoff/mx53cx9020/mx53cx9020.c
@@ -0,0 +1,369 @@
+/*
+ * Copyright (C) 2015  Beckhoff Automation GmbH & Co. KG
+ * Patrick Bruenn <p.bruenn@beckhoff.com>
+ *
+ * Based on <u-boot>/board/freescale/mx53loco/mx53loco.c
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux-mx53.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/mx5_video.h>
+#include <ACEX1K.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/gpio.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <fs.h>
+#include <dm/platform_data/serial_mxc.h>
+
+enum LED_GPIOS {
+	GPIO_SD1_CD = IMX_GPIO_NR(1, 1),
+	GPIO_SD2_CD = IMX_GPIO_NR(1, 4),
+	GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16),
+	GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17),
+	GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18),
+	GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19),
+	GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20),
+	GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21),
+	GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22),
+	GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23),
+	GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24),
+	GPIO_SUPS_INT = IMX_GPIO_NR(3, 31),
+	GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8),
+	GPIO_C3_STATUS = IMX_GPIO_NR(6, 7),
+	GPIO_C3_DONE = IMX_GPIO_NR(6, 9),
+};
+
+#define CCAT_BASE_ADDR ((void *)0xf0000000)
+#define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32))
+#define CCAT_SIZE 1191788
+#define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12)
+static const char CCAT_SIGNATURE[] = "CCAT";
+
+static const u32 CCAT_MODE_CONFIG = 0x0024DC81;
+static const u32 CCAT_MODE_RUN = 0x0033DC8F;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static uint32_t mx53_dram_size[2];
+
+phys_size_t get_effective_memsize(void)
+{
+	/*
+	 * WARNING: We must override get_effective_memsize() function here
+	 * to report only the size of the first DRAM bank. This is to make
+	 * U-Boot relocator place U-Boot into valid memory, that is, at the
+	 * end of the first DRAM bank. If we did not override this function
+	 * like so, U-Boot would be placed at the address of the first DRAM
+	 * bank + total DRAM size - sizeof(uboot), which in the setup where
+	 * each DRAM bank contains 512MiB of DRAM would result in placing
+	 * U-Boot into invalid memory area close to the end of the first
+	 * DRAM bank.
+	 */
+	return mx53_dram_size[0];
+}
+
+int dram_init(void)
+{
+	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
+	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
+
+	gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = mx53_dram_size[0];
+
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = mx53_dram_size[1];
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	struct fuse_bank *bank = &iim->bank[0];
+	struct fuse_bank0_regs *fuse =
+	    (struct fuse_bank0_regs *)bank->fuse_regs;
+
+	int rev = readl(&fuse->gp[6]);
+
+	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
+
+/*
+ * Set CCAT mode
+ * @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN
+ */
+void weim_cs0_settings(u32 mode)
+{
+	struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+	writel(0x0, &weim_regs->cs0gcr1);
+	writel(mode, &weim_regs->cs0gcr1);
+	writel(0x00001002, &weim_regs->cs0gcr2);
+
+	writel(0x04000000, &weim_regs->cs0rcr1);
+	writel(0x00000000, &weim_regs->cs0rcr2);
+
+	writel(0x04000000, &weim_regs->cs0wcr1);
+	writel(0x00000000, &weim_regs->cs0wcr2);
+}
+
+static void setup_gpio_eim(void)
+{
+	gpio_direction_input(GPIO_C3_STATUS);
+	gpio_direction_input(GPIO_C3_DONE);
+	gpio_direction_output(GPIO_C3_CONFIG, 1);
+
+	weim_cs0_settings(CCAT_MODE_RUN);
+}
+
+static void setup_gpio_sups(void)
+{
+	gpio_direction_input(GPIO_SUPS_INT);
+
+	static const int BLINK_INTERVALL = 50000;
+	int status = 1;
+	while (gpio_get_value(GPIO_SUPS_INT)) {
+		/* signal "CX SUPS power fail" */
+		gpio_set_value(GPIO_LED_PWR_R,
+			       (++status / BLINK_INTERVALL) % 2);
+	}
+
+	/* signal "CX power up" */
+	gpio_set_value(GPIO_LED_PWR_R, 1);
+}
+
+static void setup_gpio_leds(void)
+{
+	gpio_direction_output(GPIO_LED_SD2_R, 0);
+	gpio_direction_output(GPIO_LED_SD2_B, 0);
+	gpio_direction_output(GPIO_LED_SD2_G, 0);
+	gpio_direction_output(GPIO_LED_SD1_R, 0);
+	gpio_direction_output(GPIO_LED_SD1_B, 0);
+	gpio_direction_output(GPIO_LED_SD1_G, 0);
+	gpio_direction_output(GPIO_LED_PWR_R, 0);
+	gpio_direction_output(GPIO_LED_PWR_B, 0);
+	gpio_direction_output(GPIO_LED_PWR_G, 0);
+}
+
+#ifdef CONFIG_USB_EHCI_MX5
+int board_ehci_hcd_init(int port)
+{
+	/* request VBUS power enable pin, GPIO7_8 */
+	gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+	{MMC_SDHC1_BASE_ADDR},
+	{MMC_SDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret;
+
+	gpio_direction_input(GPIO_SD1_CD);
+	gpio_direction_input(GPIO_SD2_CD);
+
+	if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
+		ret = !gpio_get_value(GPIO_SD1_CD);
+	else
+		ret = !gpio_get_value(GPIO_SD2_CD);
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	u32 index;
+	int ret;
+
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
+		switch (index) {
+		case 0:
+			break;
+		case 1:
+			break;
+		default:
+			printf("Warning: you configured more ESDHC controller(%d) as supported by the board(2)\n",
+			       CONFIG_SYS_FSL_ESDHC_NUM);
+			return -EINVAL;
+		}
+		ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+#endif
+
+static int power_init(void)
+{
+	/* nothing to do on CX9020 */
+	return 0;
+}
+
+static void clock_1GHz(void)
+{
+	int ret;
+	u32 ref_clk = MXC_HCLK;
+	/*
+	 * After increasing voltage to 1.25V, we can switch
+	 * CPU clock to 1GHz and DDR to 400MHz safely
+	 */
+	ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
+	if (ret)
+		printf("CPU:   Switch CPU clock to 1GHZ failed\n");
+
+	ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
+	ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
+	if (ret)
+		printf("CPU:   Switch DDR clock to 400MHz failed\n");
+}
+
+int board_early_init_f(void)
+{
+	setup_gpio_leds();
+	setup_gpio_sups();
+	setup_gpio_eim();
+	setup_iomux_lcd();
+
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	mxc_set_sata_internal_clock();
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Beckhoff CX9020\n");
+
+	return 0;
+}
+
+static int ccat_config_fn(int assert_config, int flush, int cookie)
+{
+	/* prepare FPGA for programming */
+	weim_cs0_settings(CCAT_MODE_CONFIG);
+	gpio_set_value(GPIO_C3_CONFIG, 0);
+	udelay(1);
+	gpio_set_value(GPIO_C3_CONFIG, 1);
+	udelay(230);
+
+	return FPGA_SUCCESS;
+}
+
+static int ccat_status_fn(int cookie)
+{
+	return FPGA_FAIL;
+}
+
+static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie)
+{
+	const uint8_t *const buffer = buf;
+
+	/* program CCAT */
+	int i;
+	for (i = 0; i < buf_len; ++i)
+		writeb(buffer[i], CCAT_BASE_ADDR);
+
+	writeb(0xff, CCAT_BASE_ADDR);
+	writeb(0xff, CCAT_BASE_ADDR);
+
+	return FPGA_SUCCESS;
+}
+
+static int ccat_done_fn(int cookie)
+{
+	/* programming complete? */
+	return gpio_get_value(GPIO_C3_DONE);
+}
+
+static int ccat_post_fn(int cookie)
+{
+	/* switch to FPGA run mode */
+	weim_cs0_settings(CCAT_MODE_RUN);
+	invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR);
+
+	if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) {
+		printf("Verifing CCAT firmware failed, signature not found\n");
+		return FPGA_FAIL;
+	}
+
+	/* signal "CX booting OS" */
+	gpio_set_value(GPIO_LED_PWR_R, 1);
+	gpio_set_value(GPIO_LED_PWR_G, 1);
+	gpio_set_value(GPIO_LED_PWR_B, 0);
+	return FPGA_SUCCESS;
+}
+
+static Altera_CYC2_Passive_Serial_fns ccat_fns = {
+	.config = ccat_config_fn,
+	.status = ccat_status_fn,
+	.done = ccat_done_fn,
+	.write = ccat_write_fn,
+	.abort = ccat_post_fn,
+	.post = ccat_post_fn,
+};
+
+static Altera_desc ccat_fpga = {
+	.family = Altera_CYC2,
+	.iface = passive_serial,
+	.size = CCAT_SIZE,
+	.iface_fns = &ccat_fns,
+	.base = CCAT_BASE_ADDR,
+};
+
+int board_late_init(void)
+{
+	if (!power_init())
+		clock_1GHz();
+
+	fpga_init();
+	fpga_add(fpga_altera, &ccat_fpga);
+
+	return 0;
+}
diff --git a/board/beckhoff/mx53cx9020/mx53cx9020_video.c b/board/beckhoff/mx53cx9020/mx53cx9020_video.c
new file mode 100644
index 0000000..4da83da
--- /dev/null
+++ b/board/beckhoff/mx53cx9020/mx53cx9020_video.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2015  Beckhoff Automation GmbH & Co. KG
+ * Patrick Bruenn <p.bruenn@beckhoff.com>
+ *
+ * Based on <u-boot>/board/freescale/mx53loco/mx53loco_video.c
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/list.h>
+#include <asm/gpio.h>
+#include <asm/arch/iomux-mx53.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+#define CX9020_DVI_PWD	IMX_GPIO_NR(6, 1)
+
+static struct fb_videomode const vga_640x480 = {
+	.name = "VESA_VGA_640x480",
+	.refresh = 60,
+	.xres = 640,
+	.yres = 480,
+	.pixclock = 39721,	/* picosecond (25.175 MHz) */
+	.left_margin = 40,
+	.right_margin = 60,
+	.upper_margin = 10,
+	.lower_margin = 10,
+	.hsync_len = 20,
+	.vsync_len = 10,
+	.sync = 0,
+	.vmode = FB_VMODE_NONINTERLACED
+};
+
+void setup_iomux_lcd(void)
+{
+	/* Turn on DVI_PWD */
+	imx_iomux_v3_setup_pad(MX53_PAD_CSI0_DAT15__GPIO6_1);
+	gpio_direction_output(CX9020_DVI_PWD, 1);
+}
+
+int board_video_skip(void)
+{
+	const int ret = ipuv3_fb_init(&vga_640x480, 0, IPU_PIX_FMT_RGB24);
+	if (ret)
+		printf("VESA VG 640x480 cannot be configured: %d\n", ret);
+	return ret;
+}
diff --git a/board/bf506f-ezkit/Kconfig b/board/bf506f-ezkit/Kconfig
deleted file mode 100644
index e6fc12c..0000000
--- a/board/bf506f-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF506F_EZKIT
-
-config SYS_BOARD
-	default "bf506f-ezkit"
-
-config SYS_CONFIG_NAME
-	default "bf506f-ezkit"
-
-endif
diff --git a/board/bf506f-ezkit/MAINTAINERS b/board/bf506f-ezkit/MAINTAINERS
deleted file mode 100644
index aaf1b7e..0000000
--- a/board/bf506f-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF506F-EZKIT BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf506f-ezkit/
-F:	include/configs/bf506f-ezkit.h
-F:	configs/bf506f-ezkit_defconfig
diff --git a/board/bf506f-ezkit/Makefile b/board/bf506f-ezkit/Makefile
deleted file mode 100644
index 7efe1bc..0000000
--- a/board/bf506f-ezkit/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf506f-ezkit.o
diff --git a/board/bf506f-ezkit/bf506f-ezkit.c b/board/bf506f-ezkit/bf506f-ezkit.c
deleted file mode 100644
index 77e40ae..0000000
--- a/board/bf506f-ezkit/bf506f-ezkit.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-
-int checkboard(void)
-{
-	printf("Board: ADI BF506F EZ-Kit board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	bfin_write_EBIU_MODE(1);
-	SSYNC();
-	bfin_write_FLASH_CONTROL_CLEAR(1);
-	udelay(1);
-	bfin_write_FLASH_CONTROL_SET(1);
-	return 0;
-}
diff --git a/board/bf518f-ezbrd/Kconfig b/board/bf518f-ezbrd/Kconfig
deleted file mode 100644
index a0e80a8..0000000
--- a/board/bf518f-ezbrd/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF518F_EZBRD
-
-config SYS_BOARD
-	default "bf518f-ezbrd"
-
-config SYS_CONFIG_NAME
-	default "bf518f-ezbrd"
-
-endif
diff --git a/board/bf518f-ezbrd/MAINTAINERS b/board/bf518f-ezbrd/MAINTAINERS
deleted file mode 100644
index 6727ae4..0000000
--- a/board/bf518f-ezbrd/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF518F-EZBRD BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf518f-ezbrd/
-F:	include/configs/bf518f-ezbrd.h
-F:	configs/bf518f-ezbrd_defconfig
diff --git a/board/bf518f-ezbrd/Makefile b/board/bf518f-ezbrd/Makefile
deleted file mode 100644
index e9e23ed..0000000
--- a/board/bf518f-ezbrd/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf518f-ezbrd.o
diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c
deleted file mode 100644
index a14e509..0000000
--- a/board/bf518f-ezbrd/bf518f-ezbrd.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <spi.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/otp.h>
-#include <asm/sdh.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF518F EZ-Board board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-#if defined(CONFIG_BFIN_MAC)
-static void board_init_enetaddr(uchar *mac_addr)
-{
-#ifndef CONFIG_SYS_NO_FLASH
-	/* we cram the MAC in the last flash sector */
-	uchar *board_mac_addr = (uchar *)0x203F0096;
-	if (is_valid_ethaddr(board_mac_addr)) {
-		memcpy(mac_addr, board_mac_addr, 6);
-		eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
-#endif
-}
-
-/* Only the first run of boards had a KSZ switch */
-#if defined(CONFIG_BFIN_SPI) && __SILICON_REVISION__ == 0
-# define KSZ_POSSIBLE 1
-#else
-# define KSZ_POSSIBLE 0
-#endif
-
-#define KSZ_MAX_HZ    5000000
-
-#define KSZ_WRITE     0x02
-#define KSZ_READ      0x03
-
-#define KSZ_REG_CHID  0x00	/* Register 0: Chip ID0 */
-#define KSZ_REG_STPID 0x01	/* Register 1: Chip ID1 / Start Switch */
-#define KSZ_REG_GC9   0x0b	/* Register 11: Global Control 9 */
-#define KSZ_REG_P3C0  0x30	/* Register 48: Port 3 Control 0 */
-
-static int ksz8893m_transfer(struct spi_slave *slave, uchar dir, uchar reg,
-			     uchar data, uchar result[3])
-{
-	unsigned char dout[3] = { dir, reg, data, };
-	return spi_xfer(slave, sizeof(dout) * 8, dout, result, SPI_XFER_BEGIN | SPI_XFER_END);
-}
-
-static int ksz8893m_reg_set(struct spi_slave *slave, uchar reg, uchar data)
-{
-	unsigned char din[3];
-	return ksz8893m_transfer(slave, KSZ_WRITE, reg, data, din);
-}
-
-static int ksz8893m_reg_read(struct spi_slave *slave, uchar reg)
-{
-	int ret;
-	unsigned char din[3];
-	ret = ksz8893m_transfer(slave, KSZ_READ, reg, 0, din);
-	return ret ? ret : din[2];
-}
-
-static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask)
-{
-	return ksz8893m_reg_set(slave, reg, ksz8893m_reg_read(slave, reg) & mask);
-}
-
-static int ksz8893m_reset(struct spi_slave *slave)
-{
-	int ret = 0;
-
-	/* Disable STPID mode */
-	ret |= ksz8893m_reg_clear(slave, KSZ_REG_GC9, 0x01);
-
-	/* Disable VLAN tag insert on Port3 */
-	ret |= ksz8893m_reg_clear(slave, KSZ_REG_P3C0, 0x04);
-
-	/* Start switch */
-	ret |= ksz8893m_reg_set(slave, KSZ_REG_STPID, 0x01);
-
-	return ret;
-}
-
-static bool board_ksz_init(void)
-{
-	static bool switch_is_alive = false;
-
-	if (!switch_is_alive) {
-		struct spi_slave *slave = spi_setup_slave(0, 1, KSZ_MAX_HZ, SPI_MODE_3);
-		if (slave) {
-			if (!spi_claim_bus(slave)) {
-				bool phy_is_ksz = (ksz8893m_reg_read(slave, KSZ_REG_CHID) == 0x88);
-				int ret = phy_is_ksz ? ksz8893m_reset(slave) : 0;
-				switch_is_alive = (ret == 0);
-				spi_release_bus(slave);
-			}
-			spi_free_slave(slave);
-		}
-	}
-
-	return switch_is_alive;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	if (KSZ_POSSIBLE) {
-		if (!board_ksz_init())
-			return 0;
-	}
-	return bfin_EMAC_initialize(bis);
-}
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_BFIN_MAC
-	uchar enetaddr[6];
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-		board_init_enetaddr(enetaddr);
-#endif
-
-#ifndef CONFIG_SYS_NO_FLASH
-	/* we use the last sector for the MAC address / POST LDR */
-	extern flash_info_t flash_info[];
-	flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
-#endif
-
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	/* connect async banks by default */
-	const unsigned short pins[] = {
-		P_AMS2, P_AMS3, 0,
-	};
-	return peripheral_request_list(pins, "async");
-}
-
-#ifdef CONFIG_BFIN_SDH
-int board_mmc_init(bd_t *bis)
-{
-	return bfin_mmc_init(bis);
-}
-#endif
diff --git a/board/bf525-ucr2/Kconfig b/board/bf525-ucr2/Kconfig
deleted file mode 100644
index cd52daa..0000000
--- a/board/bf525-ucr2/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF525_UCR2
-
-config SYS_BOARD
-	default "bf525-ucr2"
-
-config SYS_CONFIG_NAME
-	default "bf525-ucr2"
-
-endif
diff --git a/board/bf525-ucr2/MAINTAINERS b/board/bf525-ucr2/MAINTAINERS
deleted file mode 100644
index f2e9575..0000000
--- a/board/bf525-ucr2/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-BF525-UCR2 BOARD
-M:	Haitao Zhang <hzhang@ucrobotics.com>
-M:	Chong Huang <chuang@ucrobotics.com>
-S:	Maintained
-F:	board/bf525-ucr2/
-F:	include/configs/bf525-ucr2.h
-F:	configs/bf525-ucr2_defconfig
diff --git a/board/bf525-ucr2/Makefile b/board/bf525-ucr2/Makefile
deleted file mode 100644
index 1be1d31..0000000
--- a/board/bf525-ucr2/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf525-ucr2.o
diff --git a/board/bf525-ucr2/bf525-ucr2.c b/board/bf525-ucr2/bf525-ucr2.c
deleted file mode 100644
index 36a725c..0000000
--- a/board/bf525-ucr2/bf525-ucr2.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* U-Boot - bf525-ucr2.c  board specific routines
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-
-int checkboard(void)
-{
-	printf("Board: bf525-ucr2\n");
-	printf("Support: http://www.ucrobotics.com/\n");
-	return 0;
-}
diff --git a/board/bf526-ezbrd/Kconfig b/board/bf526-ezbrd/Kconfig
deleted file mode 100644
index e138ea5..0000000
--- a/board/bf526-ezbrd/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF526_EZBRD
-
-config SYS_BOARD
-	default "bf526-ezbrd"
-
-config SYS_CONFIG_NAME
-	default "bf526-ezbrd"
-
-endif
diff --git a/board/bf526-ezbrd/MAINTAINERS b/board/bf526-ezbrd/MAINTAINERS
deleted file mode 100644
index f7c2d18..0000000
--- a/board/bf526-ezbrd/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF526-EZBRD BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf526-ezbrd/
-F:	include/configs/bf526-ezbrd.h
-F:	configs/bf526-ezbrd_defconfig
diff --git a/board/bf526-ezbrd/Makefile b/board/bf526-ezbrd/Makefile
deleted file mode 100644
index c4882c9..0000000
--- a/board/bf526-ezbrd/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf526-ezbrd.o
diff --git a/board/bf526-ezbrd/bf526-ezbrd.c b/board/bf526-ezbrd/bf526-ezbrd.c
deleted file mode 100644
index a506d1b..0000000
--- a/board/bf526-ezbrd/bf526-ezbrd.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/otp.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF526 EZ-Board board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
-{
-#ifndef CONFIG_SYS_NO_FLASH
-	/* we cram the MAC in the last flash sector */
-	uchar *board_mac_addr = (uchar *)0x203F0096;
-	if (is_valid_ethaddr(board_mac_addr)) {
-		memcpy(mac_addr, board_mac_addr, 6);
-		eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
-#endif
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_BFIN_MAC
-	uchar enetaddr[6];
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-		board_init_enetaddr(enetaddr);
-#endif
-
-#ifndef CONFIG_SYS_NO_FLASH
-	/* we use the last sector for the MAC address / POST LDR */
-	extern flash_info_t flash_info[];
-	flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
-#endif
-
-	return 0;
-}
diff --git a/board/bf527-ad7160-eval/Kconfig b/board/bf527-ad7160-eval/Kconfig
deleted file mode 100644
index fe56241..0000000
--- a/board/bf527-ad7160-eval/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF527_AD7160_EVAL
-
-config SYS_BOARD
-	default "bf527-ad7160-eval"
-
-config SYS_CONFIG_NAME
-	default "bf527-ad7160-eval"
-
-endif
diff --git a/board/bf527-ad7160-eval/MAINTAINERS b/board/bf527-ad7160-eval/MAINTAINERS
deleted file mode 100644
index e93de1a..0000000
--- a/board/bf527-ad7160-eval/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF527-AD7160-EVAL BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf527-ad7160-eval/
-F:	include/configs/bf527-ad7160-eval.h
-F:	configs/bf527-ad7160-eval_defconfig
diff --git a/board/bf527-ad7160-eval/Makefile b/board/bf527-ad7160-eval/Makefile
deleted file mode 100644
index c225f72..0000000
--- a/board/bf527-ad7160-eval/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf527-ad7160-eval.o
diff --git a/board/bf527-ad7160-eval/bf527-ad7160-eval.c b/board/bf527-ad7160-eval/bf527-ad7160-eval.c
deleted file mode 100644
index 9180630..0000000
--- a/board/bf527-ad7160-eval/bf527-ad7160-eval.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/pll.h>
-
-int checkboard(void)
-{
-	printf("Board: ADI BF527 AD7160-EVAL board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	/* CLKIN Buffer Output Enable */
-	bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
-	return 0;
-}
diff --git a/board/bf527-ezkit/Kconfig b/board/bf527-ezkit/Kconfig
deleted file mode 100644
index df49d7a..0000000
--- a/board/bf527-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF527_EZKIT
-
-config SYS_BOARD
-	default "bf527-ezkit"
-
-config SYS_CONFIG_NAME
-	default "bf527-ezkit"
-
-endif
diff --git a/board/bf527-ezkit/MAINTAINERS b/board/bf527-ezkit/MAINTAINERS
deleted file mode 100644
index 7a95396..0000000
--- a/board/bf527-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-BF527-EZKIT BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf527-ezkit/
-F:	include/configs/bf527-ezkit.h
-F:	configs/bf527-ezkit_defconfig
-F:	configs/bf527-ezkit-v2_defconfig
diff --git a/board/bf527-ezkit/Makefile b/board/bf527-ezkit/Makefile
deleted file mode 100644
index 53ec9e7..0000000
--- a/board/bf527-ezkit/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf527-ezkit.o
-obj-$(CONFIG_VIDEO)      += video.o
diff --git a/board/bf527-ezkit/bf527-ezkit.c b/board/bf527-ezkit/bf527-ezkit.c
deleted file mode 100644
index c4f58fa..0000000
--- a/board/bf527-ezkit/bf527-ezkit.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/mach-common/bits/otp.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF527 EZ-Kit board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
-{
-	/* the MAC is stored in OTP memory page 0xDF */
-	uint32_t ret;
-	uint64_t otp_mac;
-
-	ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
-	if (!(ret & OTP_MASTER_ERROR)) {
-		uchar *otp_mac_p = (uchar *)&otp_mac;
-
-		for (ret = 0; ret < 6; ++ret)
-			mac_addr[ret] = otp_mac_p[5 - ret];
-
-		if (is_valid_ethaddr(mac_addr))
-			eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_BFIN_MAC
-	uchar enetaddr[6];
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-		board_init_enetaddr(enetaddr);
-#endif
-
-	return 0;
-}
-
-#ifdef CONFIG_USB_BLACKFIN
-void board_musb_init(void)
-{
-	/*
-	 * BF527 EZ-KITs require PG13 to be high for HOST mode
-	 */
-	gpio_request(GPIO_PG13, "musb-vbus");
-	gpio_direction_output(GPIO_PG13, 1);
-}
-#endif
diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c
deleted file mode 100644
index a57f9fe..0000000
--- a/board/bf527-ezkit/video.c
+++ /dev/null
@@ -1,445 +0,0 @@
-/*
- * video.c - run splash screen on lcd
- *
- * Copyright (c) 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/dma.h>
-#include <spi.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-
-#include <lzma/LzmaTypes.h>
-#include <lzma/LzmaDec.h>
-#include <lzma/LzmaTools.h>
-
-#include <asm/mach-common/bits/ppi.h>
-#include <asm/mach-common/bits/timer.h>
-
-#define LCD_X_RES		320	/* Horizontal Resolution */
-#define LCD_Y_RES		240	/* Vertical Resolution */
-#define DMA_BUS_SIZE		16
-
-#include EASYLOGO_HEADER
-
-#ifdef CONFIG_BF527_EZKIT_REV_2_1 /* lq035q1 */
-
-/* Interface 16/18-bit TFT over an 8-bit wide PPI using a
- * small Programmable Logic Device (CPLD)
- * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
- */
-
-#ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
-#define LCD_BPP		16	/* Bit Per Pixel */
-#define CLOCKS_PPIX	2	/* Clocks per pixel */
-#define CPLD_DELAY	3	/* RGB565 pipeline delay */
-#endif
-
-#ifdef CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
-#define LCD_BPP		24	/* Bit Per Pixel */
-#define CLOCKS_PPIX	3	/* Clocks per pixel */
-#define CPLD_DELAY	5	/* RGB888 pipeline delay */
-#endif
-
-/*
- * HS and VS timing parameters (all in number of PPI clk ticks)
- */
-
-#define H_ACTPIX	(LCD_X_RES * CLOCKS_PPIX)	/* active horizontal pixel */
-#define H_PERIOD	(336 * CLOCKS_PPIX)		/* HS period */
-#define H_PULSE		(2 * CLOCKS_PPIX)		/* HS pulse width */
-#define H_START		(7 * CLOCKS_PPIX + CPLD_DELAY)	/* first valid pixel */
-
-#define U_LINE		4				/* Blanking Lines */
-
-#define V_LINES		(LCD_Y_RES + U_LINE)		/* total vertical lines */
-#define V_PULSE		(2 * CLOCKS_PPIX)		/* VS pulse width (1-5 H_PERIODs) */
-#define V_PERIOD	(H_PERIOD * V_LINES)		/* VS period */
-
-#define ACTIVE_VIDEO_MEM_OFFSET	((U_LINE / 2) * LCD_X_RES * (LCD_BPP / 8))
-
-/*
- * LCD Modes
- */
-#define LQ035_RL	(0 << 8)	/* Right -> Left Scan */
-#define LQ035_LR	(1 << 8)	/* Left -> Right Scan */
-#define LQ035_TB	(1 << 9)	/* Top -> Botton Scan */
-#define LQ035_BT	(0 << 9)	/* Botton -> Top Scan */
-#define LQ035_BGR	(1 << 11)	/* Use BGR format */
-#define LQ035_RGB	(0 << 11)	/* Use RGB format */
-#define LQ035_NORM	(1 << 13)	/* Reversal */
-#define LQ035_REV	(0 << 13)	/* Reversal */
-
-#define LQ035_INDEX			0x74
-#define LQ035_DATA			0x76
-
-#define LQ035_DRIVER_OUTPUT_CTL		0x1
-#define LQ035_SHUT_CTL			0x11
-
-#define LQ035_DRIVER_OUTPUT_MASK	(LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV)
-#define LQ035_DRIVER_OUTPUT_DEFAULT	(0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK)
-
-#define LQ035_SHUT			(1 << 0)	/* Shutdown */
-#define LQ035_ON			(0 << 0)	/* Shutdown */
-
-#ifndef CONFIG_LQ035Q1_LCD_MODE
-#define CONFIG_LQ035Q1_LCD_MODE		(LQ035_NORM | LQ035_RL | LQ035_TB | LQ035_BGR)
-#endif
-
-#else /* t350mcqb */
-
-#define LCD_BPP		24	/* Bit Per Pixel */
-#define CLOCKS_PPIX	3	/* Clocks per pixel */
-
-/* HS and VS timing parameters (all in number of PPI clk ticks) */
-#define H_ACTPIX	(LCD_X_RES * CLOCKS_PPIX)	/* active horizontal pixel */
-#define H_PERIOD	(408 * CLOCKS_PPIX)		/* HS period */
-#define H_PULSE		90				/* HS pulse width */
-#define H_START		204				/* first valid pixel */
-
-#define U_LINE		1				/* Blanking Lines */
-
-#define V_LINES		(LCD_Y_RES + U_LINE)		/* total vertical lines */
-#define V_PULSE		(3 * H_PERIOD)			/* VS pulse width (1-5 H_PERIODs) */
-#define V_PERIOD	(H_PERIOD * V_LINES)		/* VS period */
-
-#define ACTIVE_VIDEO_MEM_OFFSET	(U_LINE * H_ACTPIX)
-#endif
-
-#define LCD_PIXEL_SIZE		(LCD_BPP / 8)
-#define DMA_SIZE16		2
-
-#define PPI_TX_MODE		0x2
-#define PPI_XFER_TYPE_11	0xC
-#define PPI_PORT_CFG_01		0x10
-#define PPI_PACK_EN		0x80
-#define PPI_POLS_1		0x8000
-
-#ifdef CONFIG_BF527_EZKIT_REV_2_1
-static struct spi_slave *slave;
-static int lq035q1_control(unsigned char reg, unsigned short value)
-{
-	int ret;
-	u8 regs[3] = {LQ035_INDEX, 0, 0};
-	u8 data[3] = {LQ035_DATA, 0, 0};
-	u8 dummy[3];
-
-	regs[2] = reg;
-	data[1] = value >> 8;
-	data[2] = value & 0xFF;
-
-	if (!slave) {
-		/* FIXME: Verify the max SCK rate */
-		slave = spi_setup_slave(CONFIG_LQ035Q1_SPI_BUS,
-				CONFIG_LQ035Q1_SPI_CS, 20000000,
-				SPI_MODE_3);
-		if (!slave)
-			return -1;
-	}
-
-	if (spi_claim_bus(slave))
-		return -1;
-
-	ret = spi_xfer(slave, 24, regs, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
-	ret |= spi_xfer(slave, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
-
-	spi_release_bus(slave);
-
-	return ret;
-}
-#endif
-
-/* enable and disable PPI functions */
-void EnablePPI(void)
-{
-	bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
-}
-
-void DisablePPI(void)
-{
-	bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
-}
-
-void Init_Ports(void)
-{
-	const unsigned short pins[] = {
-		P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
-		P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_FS2, 0,
-	};
-	peripheral_request_list(pins, "lcd");
-}
-
-void Init_PPI(void)
-{
-
-	bfin_write_PPI_DELAY(H_START);
-	bfin_write_PPI_COUNT(H_ACTPIX - 1);
-	bfin_write_PPI_FRAME(V_LINES);
-
-	/* PPI control, to be replaced with definitions */
-	bfin_write_PPI_CONTROL(
-			PPI_TX_MODE		|	/* output mode , PORT_DIR */
-			PPI_XFER_TYPE_11	|	/* sync mode XFR_TYPE */
-			PPI_PORT_CFG_01		|	/* two frame sync PORT_CFG */
-			PPI_PACK_EN		|	/* packing enabled PACK_EN */
-			PPI_POLS_1			/* faling edge syncs POLS */
-	);
-}
-
-void Init_DMA(void *dst)
-{
-	bfin_write_DMA0_START_ADDR(dst);
-
-	/* X count */
-	bfin_write_DMA0_X_COUNT(H_ACTPIX / 2);
-	bfin_write_DMA0_X_MODIFY(DMA_BUS_SIZE / 8);
-
-	/* Y count */
-	bfin_write_DMA0_Y_COUNT(V_LINES);
-	bfin_write_DMA0_Y_MODIFY(DMA_BUS_SIZE / 8);
-
-	/* DMA Config */
-	bfin_write_DMA0_CONFIG(
-		WDSIZE_16	|	/* 16 bit DMA */
-		DMA2D 		|	/* 2D DMA */
-		FLOW_AUTO		/* autobuffer mode */
-	);
-}
-
-void EnableDMA(void)
-{
-	bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() | DMAEN);
-}
-
-void DisableDMA(void)
-{
-	bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() & ~DMAEN);
-}
-
-/* Init TIMER0 as Frame Sync 1 generator */
-void InitTIMER0(void)
-{
-	bfin_write_TIMER_DISABLE(TIMDIS0);			/* disable Timer */
-	SSYNC();
-	bfin_write_TIMER_STATUS(TIMIL0 | TOVF_ERR0 | TRUN0);	/* clear status */
-	SSYNC();
-
-	bfin_write_TIMER0_PERIOD(H_PERIOD);
-	SSYNC();
-	bfin_write_TIMER0_WIDTH(H_PULSE);
-	SSYNC();
-
-	bfin_write_TIMER0_CONFIG(
-				PWM_OUT |
-				PERIOD_CNT   |
-				TIN_SEL      |
-				CLK_SEL      |
-				EMU_RUN
-	);
-	SSYNC();
-}
-
-void EnableTIMER0(void)
-{
-	bfin_write_TIMER_ENABLE(TIMEN0);
-	SSYNC();
-}
-
-void DisableTIMER0(void)
-{
-	bfin_write_TIMER_DISABLE(TIMDIS0);
-	SSYNC();
-}
-
-
-void InitTIMER1(void)
-{
-	bfin_write_TIMER_DISABLE(TIMDIS1);			/* disable Timer */
-	SSYNC();
-	bfin_write_TIMER_STATUS(TIMIL1 | TOVF_ERR1 | TRUN1);	/* clear status */
-	SSYNC();
-
-	bfin_write_TIMER1_PERIOD(V_PERIOD);
-	SSYNC();
-	bfin_write_TIMER1_WIDTH(V_PULSE);
-	SSYNC();
-
-	bfin_write_TIMER1_CONFIG(
-				PWM_OUT |
-				PERIOD_CNT   |
-				TIN_SEL      |
-				CLK_SEL      |
-				EMU_RUN
-	);
-	SSYNC();
-}
-
-void EnableTIMER1(void)
-{
-	bfin_write_TIMER_ENABLE(TIMEN1);
-	SSYNC();
-}
-
-void DisableTIMER1(void)
-{
-	bfin_write_TIMER_DISABLE(TIMDIS1);
-	SSYNC();
-}
-
-void EnableTIMER12(void)
-{
-	bfin_write_TIMER_ENABLE(TIMEN1 | TIMEN0);
-	SSYNC();
-}
-
-int video_init(void *dst)
-{
-
-#ifdef CONFIG_BF527_EZKIT_REV_2_1
-	lq035q1_control(LQ035_SHUT_CTL, LQ035_ON);
-	lq035q1_control(LQ035_DRIVER_OUTPUT_CTL, (CONFIG_LQ035Q1_LCD_MODE &
-		LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT);
-#endif
-	Init_Ports();
-	Init_DMA(dst);
-	EnableDMA();
-	InitTIMER0();
-	InitTIMER1();
-	Init_PPI();
-	EnablePPI();
-
-#ifdef CONFIG_BF527_EZKIT_REV_2_1
-	EnableTIMER12();
-#else
-	/* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
-	EnableTIMER1();
-	/* Add Some Delay ... */
-	SSYNC();
-	SSYNC();
-	SSYNC();
-	SSYNC();
-
-	/* now start frame sync 1 */
-	EnableTIMER0();
-#endif
-
-	return 0;
-}
-
-static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
-{
-	if (dcache_status())
-		blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
-
-	bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-	/* Setup destination start address */
-	bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
-					+ (y * LCD_X_RES * LCD_PIXEL_SIZE));
-	/* Setup destination xcount */
-	bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
-	/* Setup destination xmodify */
-	bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
-
-	/* Setup destination ycount */
-	bfin_write_MDMA_D0_Y_COUNT(logo->height);
-	/* Setup destination ymodify */
-	bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
-
-
-	/* Setup Source start address */
-	bfin_write_MDMA_S0_START_ADDR(logo->data);
-	/* Setup Source xcount */
-	bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
-	/* Setup Source xmodify */
-	bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
-
-	/* Setup Source ycount */
-	bfin_write_MDMA_S0_Y_COUNT(logo->height);
-	/* Setup Source ymodify */
-	bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
-
-
-	/* Enable source DMA */
-	bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
-	SSYNC();
-	bfin_write_MDMA_D0_CONFIG(WNR | DMAEN  | WDSIZE_16 | DMA2D);
-
-	while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
-
-	bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
-	bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
-
-}
-
-void video_stop(void)
-{
-	DisablePPI();
-	DisableDMA();
-	DisableTIMER0();
-	DisableTIMER1();
-#ifdef CONFIG_BF527_EZKIT_REV_2_1
-	lq035q1_control(LQ035_SHUT_CTL, LQ035_SHUT);
-#endif
-}
-
-int drv_video_init(void)
-{
-	int error, devices = 1;
-	struct stdio_dev videodev;
-
-	u8 *dst;
-	u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
-
-	dst = malloc(fbmem_size);
-
-	if (dst == NULL) {
-		printf("Failed to alloc FB memory\n");
-		return -1;
-	}
-
-#ifdef EASYLOGO_ENABLE_GZIP
-	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
-	unsigned long src_len = EASYLOGO_ENABLE_GZIP;
-	error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len);
-	bfin_logo.data = data;
-#elif defined(EASYLOGO_ENABLE_LZMA)
-	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
-	SizeT lzma_len = bfin_logo.size;
-	error = lzmaBuffToBuffDecompress(data, &lzma_len,
-		bfin_logo.data, EASYLOGO_ENABLE_LZMA);
-	bfin_logo.data = data;
-#else
-	error = 0;
-#endif
-
-	if (error) {
-		puts("Failed to decompress logo\n");
-		free(dst);
-		return -1;
-	}
-
-	memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
-
-	dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
-			(LCD_X_RES - bfin_logo.width) / 2,
-			(LCD_Y_RES - bfin_logo.height) / 2);
-
-	video_init(dst);		/* Video initialization */
-
-	memset(&videodev, 0, sizeof(videodev));
-
-	strcpy(videodev.name, "video");
-
-	error = stdio_register(&videodev);
-
-	return (error == 0) ? devices : error;
-}
diff --git a/board/bf527-sdp/Kconfig b/board/bf527-sdp/Kconfig
deleted file mode 100644
index 928bd77..0000000
--- a/board/bf527-sdp/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF527_SDP
-
-config SYS_BOARD
-	default "bf527-sdp"
-
-config SYS_CONFIG_NAME
-	default "bf527-sdp"
-
-endif
diff --git a/board/bf527-sdp/MAINTAINERS b/board/bf527-sdp/MAINTAINERS
deleted file mode 100644
index 32ccfc5..0000000
--- a/board/bf527-sdp/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF527-SDP BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf527-sdp/
-F:	include/configs/bf527-sdp.h
-F:	configs/bf527-sdp_defconfig
diff --git a/board/bf527-sdp/Makefile b/board/bf527-sdp/Makefile
deleted file mode 100644
index 77acb42..0000000
--- a/board/bf527-sdp/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf527-sdp.o
diff --git a/board/bf527-sdp/bf527-sdp.c b/board/bf527-sdp/bf527-sdp.c
deleted file mode 100644
index 0c6094b..0000000
--- a/board/bf527-sdp/bf527-sdp.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/mach-common/bits/pll.h>
-
-int checkboard(void)
-{
-	printf("Board: ADI BF527 SDP board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-
-	/* Enable access to parallel flash */
-	gpio_request(GPIO_PG0, "parallel-flash");
-	gpio_direction_output(GPIO_PG0, 0);
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	/* CLKIN Buffer Output Enable */
-	bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
-
-	return 0;
-}
diff --git a/board/bf527-sdp/config.mk b/board/bf527-sdp/config.mk
deleted file mode 100644
index 1d46cfc..0000000
--- a/board/bf527-sdp/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6
diff --git a/board/bf533-ezkit/Kconfig b/board/bf533-ezkit/Kconfig
deleted file mode 100644
index 555ab29..0000000
--- a/board/bf533-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF533_EZKIT
-
-config SYS_BOARD
-	default "bf533-ezkit"
-
-config SYS_CONFIG_NAME
-	default "bf533-ezkit"
-
-endif
diff --git a/board/bf533-ezkit/MAINTAINERS b/board/bf533-ezkit/MAINTAINERS
deleted file mode 100644
index bfa7c3c..0000000
--- a/board/bf533-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF533-EZKIT BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf533-ezkit/
-F:	include/configs/bf533-ezkit.h
-F:	configs/bf533-ezkit_defconfig
diff --git a/board/bf533-ezkit/Makefile b/board/bf533-ezkit/Makefile
deleted file mode 100644
index bf7a2c4..0000000
--- a/board/bf533-ezkit/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf533-ezkit.o flash.o
diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c
deleted file mode 100644
index 6879319..0000000
--- a/board/bf533-ezkit/bf533-ezkit.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include "psd4256.h"
-#include "flash-defines.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF533 EZ-Kit Lite board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
-	/* Set direction bits for Video en/decoder reset as output      */
-	*(volatile unsigned char *)(CONFIG_SYS_FLASH1_BASE + PSD_PORTA_DIR) =
-	    PSDA_VDEC_RST | PSDA_VENC_RST;
-	/* Deactivate Video en/decoder reset lines                      */
-	*(volatile unsigned char *)(CONFIG_SYS_FLASH1_BASE + PSD_PORTA_DOUT) =
-	    PSDA_VDEC_RST | PSDA_VENC_RST;
-
-	return 0;
-}
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
-	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk
deleted file mode 100644
index 7f9138b..0000000
--- a/board/bf533-ezkit/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf533-ezkit/flash-defines.h b/board/bf533-ezkit/flash-defines.h
deleted file mode 100644
index 7822a9d..0000000
--- a/board/bf533-ezkit/flash-defines.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * U-Boot - flash-defines.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __FLASHDEFINES_H__
-#define __FLASHDEFINES_H__
-
-#include <common.h>
-
-#define V_ULONG(a)		(*(volatile unsigned long *)( a ))
-#define V_BYTE(a)		(*(volatile unsigned char *)( a ))
-#define BUFFER_SIZE		0x80000
-#define NO_COMMAND		0
-#define GET_CODES		1
-#define RESET			2
-#define WRITE			3
-#define FILL			4
-#define ERASE_ALL		5
-#define ERASE_SECT		6
-#define READ			7
-#define GET_SECTNUM		8
-#define FLASH_START_L		0x0000
-#define FLASH_START_H		0x2000
-#define FLASH_TOT_SECT		40
-#define FLASH_SIZE		0x220000
-#define FLASH_MAN_ST		2
-#define CONFIG_SYS_FLASH0_BASE		0x20000000
-#define CONFIG_SYS_FLASH1_BASE		0x20200000
-#define RESET_VAL		0xF0
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-int get_codes(void);
-int poll_toggle_bit(long lOffset);
-void reset_flash(void);
-int erase_flash(void);
-int erase_block_flash(int, unsigned long);
-void unlock_flash(long lOffset);
-int write_data(long lStart, long lCount, uchar *pnData);
-int FillData(long lStart, long lCount, long lStride, int *pnData);
-int read_data(long lStart, long lCount, long lStride, int *pnData);
-int read_flash(long nOffset, int *pnValue);
-int write_flash(long nOffset, int nValue);
-void get_sector_number(long lOffset, int *pnSector);
-int GetSectorProtectionStatus(flash_info_t * info, int nSector);
-int GetOffset(int nBlock);
-
-#define WRITESEQ1		0x0AAA
-#define WRITESEQ2		0x0554
-#define WRITESEQ3		0x0AAA
-#define WRITESEQ4		0x0AAA
-#define WRITESEQ5		0x0554
-#define WRITESEQ6		0x0AAA
-#define WRITEDATA1		0xaa
-#define WRITEDATA2		0x55
-#define WRITEDATA3		0x80
-#define WRITEDATA4		0xaa
-#define WRITEDATA5		0x55
-#define WRITEDATA6		0x10
-#define PriFlashABegin		0
-#define SecFlashABegin		32
-#define SecFlashBBegin		36
-#define PriFlashAOff		0x0
-#define PriFlashBOff		0x100000
-#define SecFlashAOff		0x200000
-#define SecFlashBOff		0x280000
-#define INVALIDLOCNSTART	0x20270000
-#define INVALIDLOCNEND		0x20280000
-#define BlockEraseVal		0x30
-#define UNLOCKDATA1		0xaa
-#define UNLOCKDATA2		0x55
-#define UNLOCKDATA3		0xa0
-#define GETCODEDATA1		0xaa
-#define GETCODEDATA2		0x55
-#define GETCODEDATA3		0x90
-#define SecFlashASec1Off	0x200000
-#define SecFlashASec2Off	0x204000
-#define SecFlashASec3Off	0x206000
-#define SecFlashASec4Off	0x208000
-#define SecFlashAEndOff		0x210000
-#define SecFlashBSec1Off	0x280000
-#define SecFlashBSec2Off	0x284000
-#define SecFlashBSec3Off	0x286000
-#define SecFlashBSec4Off	0x288000
-#define SecFlashBEndOff		0x290000
-
-#define SECT32			32
-#define SECT33			33
-#define SECT34			34
-#define SECT35			35
-#define SECT36			36
-#define SECT37			37
-#define SECT38			38
-#define SECT39			39
-
-#define FLASH_SUCCESS	0
-#define FLASH_FAIL	-1
-
-#endif
diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c
deleted file mode 100644
index a7b3519..0000000
--- a/board/bf533-ezkit/flash.c
+++ /dev/null
@@ -1,473 +0,0 @@
-/*
- * U-Boot - flash.c Flash driver for PSD4256GV
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/io.h>
-#include "flash-defines.h"
-
-int AFP_NumSectors = 40;
-long AFP_SectorSize1 = 0x10000;
-int AFP_SectorSize2 = 0x4000;
-
-void flash_reset(void)
-{
-	reset_flash();
-}
-
-unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, int bank_flag)
-{
-	int id = 0, i = 0;
-	static int FlagDev = 1;
-
-	id = get_codes();
-	if (FlagDev) {
-#ifdef DEBUG
-		printf("Device ID of the Flash is %x\n", id);
-#endif
-		FlagDev = 0;
-	}
-	info->flash_id = id;
-
-	switch (bank_flag) {
-	case 0:
-		for (i = PriFlashABegin; i < SecFlashABegin; i++)
-			info->start[i] = (baseaddr + (i * AFP_SectorSize1));
-		info->size = 0x200000;
-		info->sector_count = 32;
-		break;
-	case 1:
-		info->start[0] = baseaddr + SecFlashASec1Off;
-		info->start[1] = baseaddr + SecFlashASec2Off;
-		info->start[2] = baseaddr + SecFlashASec3Off;
-		info->start[3] = baseaddr + SecFlashASec4Off;
-		info->size = 0x10000;
-		info->sector_count = 4;
-		break;
-	case 2:
-		info->start[0] = baseaddr + SecFlashBSec1Off;
-		info->start[1] = baseaddr + SecFlashBSec2Off;
-		info->start[2] = baseaddr + SecFlashBSec3Off;
-		info->start[3] = baseaddr + SecFlashBSec4Off;
-		info->size = 0x10000;
-		info->sector_count = 4;
-		break;
-	}
-	return (info->size);
-}
-
-unsigned long flash_init(void)
-{
-	unsigned long size_b0, size_b1, size_b2;
-	int i;
-
-	size_b0 = size_b1 = size_b2 = 0;
-#ifdef DEBUG
-	printf("Flash Memory Start 0x%x\n", CONFIG_SYS_FLASH_BASE);
-	printf("Memory Map for the Flash\n");
-	printf("0x20000000 - 0x200FFFFF Flash A Primary (1MB)\n");
-	printf("0x20100000 - 0x201FFFFF Flash B Primary (1MB)\n");
-	printf("0x20200000 - 0x2020FFFF Flash A Secondary (64KB)\n");
-	printf("0x20280000 - 0x2028FFFF Flash B Secondary (64KB)\n");
-	printf("Please type command flinfo for information on Sectors \n");
-#endif
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	size_b0 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[0], 0);
-	size_b1 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[1], 1);
-	size_b2 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[2], 2);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
-		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-		       size_b0, size_b0 >> 20);
-	}
-
-	(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_FLASH0_BASE,
-			    (flash_info[0].start[2] - 1), &flash_info[0]);
-
-	return (size_b0 + size_b1 + size_b2);
-}
-
-void flash_print_info(flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id) {
-	case FLASH_PSD4256GV:
-		printf("ST Microelectronics ");
-		break;
-	default:
-		printf("Unknown Vendor: (0x%08lX) ", info->flash_id);
-		break;
-	}
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf("\n   ");
-		printf(" %08lX%s",
-		       info->start[i], info->protect[i] ? " (RO)" : "     ");
-	}
-	printf("\n");
-	return;
-}
-
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
-	int cnt = 0, i;
-	int prot, sect;
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect])
-			prot++;
-	}
-
-	if (prot)
-		printf("- Warning: %d protected sectors will not be erased!\n",
-		       prot);
-	else
-		printf("\n");
-
-	cnt = s_last - s_first + 1;
-
-	if (cnt == FLASH_TOT_SECT) {
-		printf("Erasing flash, Please Wait \n");
-		if (erase_flash() < 0) {
-			printf("Erasing flash failed \n");
-			return FLASH_FAIL;
-		}
-	} else {
-		printf("Erasing Flash locations, Please Wait\n");
-		for (i = s_first; i <= s_last; i++) {
-			if (info->protect[i] == 0) {	/* not protected */
-				if (erase_block_flash(i, info->start[i]) < 0) {
-					printf("Error Sector erasing \n");
-					return FLASH_FAIL;
-				}
-			}
-		}
-	}
-	return FLASH_SUCCESS;
-}
-
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	int ret;
-	int d;
-	if (addr % 2) {
-		read_flash(addr - 1 - CONFIG_SYS_FLASH_BASE, &d);
-		d = (int)((d & 0x00FF) | (*src++ << 8));
-		ret = write_data(addr - 1, 2, (uchar *) & d);
-		if (ret == FLASH_FAIL)
-			return ERR_NOT_ERASED;
-		ret = write_data(addr + 1, cnt - 1, src);
-	} else
-		ret = write_data(addr, cnt, src);
-	if (ret == FLASH_FAIL)
-		return ERR_NOT_ERASED;
-	return FLASH_SUCCESS;
-}
-
-int write_data(long lStart, long lCount, uchar * pnData)
-{
-	long i = 0;
-	unsigned long ulOffset = lStart - CONFIG_SYS_FLASH_BASE;
-	int d;
-	int nSector = 0;
-	int flag = 0;
-
-	if (lCount % 2) {
-		flag = 1;
-		lCount = lCount - 1;
-	}
-
-	for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) {
-		get_sector_number(ulOffset, &nSector);
-		read_flash(ulOffset, &d);
-		if (d != 0xffff) {
-			printf
-			    ("Flash not erased at offset 0x%lx Please erase to reprogram\n",
-			     ulOffset);
-			return FLASH_FAIL;
-		}
-		unlock_flash(ulOffset);
-		d = (int)(pnData[i] | pnData[i + 1] << 8);
-		write_flash(ulOffset, d);
-		if (poll_toggle_bit(ulOffset) < 0) {
-			printf("Error programming the flash \n");
-			return FLASH_FAIL;
-		}
-		if ((i > 0) && (!(i % AFP_SectorSize2)))
-			printf(".");
-	}
-	if (flag) {
-		get_sector_number(ulOffset, &nSector);
-		read_flash(ulOffset, &d);
-		if (d != 0xffff) {
-			printf
-			    ("Flash not erased at offset 0x%lx Please erase to reprogram\n",
-			     ulOffset);
-			return FLASH_FAIL;
-		}
-		unlock_flash(ulOffset);
-		d = (int)(pnData[i] | (d & 0xFF00));
-		write_flash(ulOffset, d);
-		if (poll_toggle_bit(ulOffset) < 0) {
-			printf("Error programming the flash \n");
-			return FLASH_FAIL;
-		}
-	}
-	return FLASH_SUCCESS;
-}
-
-int read_data(long ulStart, long lCount, long lStride, int *pnData)
-{
-	long i = 0;
-	int j = 0;
-	long ulOffset = ulStart;
-	int iShift = 0;
-	int iNumWords = 2;
-	int nLeftover = lCount % 4;
-	int nHi, nLow;
-	int nSector = 0;
-
-	for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
-		for (iShift = 0, j = 0; j < iNumWords; j += 2) {
-			if ((ulOffset >= INVALIDLOCNSTART)
-			    && (ulOffset < INVALIDLOCNEND))
-				return FLASH_FAIL;
-
-			get_sector_number(ulOffset, &nSector);
-			read_flash(ulOffset, &nLow);
-			ulOffset += (lStride * 2);
-			read_flash(ulOffset, &nHi);
-			ulOffset += (lStride * 2);
-			pnData[i] = (nHi << 16) | nLow;
-		}
-	}
-	if (nLeftover > 0) {
-		if ((ulOffset >= INVALIDLOCNSTART)
-		    && (ulOffset < INVALIDLOCNEND))
-			return FLASH_FAIL;
-
-		get_sector_number(ulOffset, &nSector);
-		read_flash(ulOffset, &pnData[i]);
-	}
-	return FLASH_SUCCESS;
-}
-
-int write_flash(long nOffset, int nValue)
-{
-	long addr;
-
-	addr = (CONFIG_SYS_FLASH_BASE + nOffset);
-	SSYNC();
-	*(unsigned volatile short *)addr = nValue;
-	SSYNC();
-	if (poll_toggle_bit(nOffset) < 0)
-		return FLASH_FAIL;
-	return FLASH_SUCCESS;
-}
-
-int read_flash(long nOffset, int *pnValue)
-{
-	int nValue = 0x0;
-	long addr = (CONFIG_SYS_FLASH_BASE + nOffset);
-
-	if (nOffset != 0x2)
-		reset_flash();
-	SSYNC();
-	nValue = *(volatile unsigned short *)addr;
-	SSYNC();
-	*pnValue = nValue;
-	return true;
-}
-
-int poll_toggle_bit(long lOffset)
-{
-	unsigned int u1, u2;
-	unsigned long timeout = 0xFFFFFFFF;
-	volatile unsigned long *FB =
-	    (volatile unsigned long *)(0x20000000 + lOffset);
-	while (1) {
-		if (timeout < 0)
-			break;
-		u1 = *(volatile unsigned short *)FB;
-		u2 = *(volatile unsigned short *)FB;
-		if ((u1 & 0x0040) == (u2 & 0x0040))
-			return FLASH_SUCCESS;
-		if ((u2 & 0x0020) == 0x0000)
-			continue;
-		u1 = *(volatile unsigned short *)FB;
-		if ((u2 & 0x0040) == (u1 & 0x0040))
-			return FLASH_SUCCESS;
-		else {
-			reset_flash();
-			return FLASH_FAIL;
-		}
-		timeout--;
-	}
-	printf("Time out occurred \n");
-	if (timeout < 0)
-		return FLASH_FAIL;
-}
-
-void reset_flash(void)
-{
-	write_flash(WRITESEQ1, RESET_VAL);
-	/* Wait for 10 micro seconds */
-	udelay(10);
-}
-
-int erase_flash(void)
-{
-	write_flash(WRITESEQ1, WRITEDATA1);
-	write_flash(WRITESEQ2, WRITEDATA2);
-	write_flash(WRITESEQ3, WRITEDATA3);
-	write_flash(WRITESEQ4, WRITEDATA4);
-	write_flash(WRITESEQ5, WRITEDATA5);
-	write_flash(WRITESEQ6, WRITEDATA6);
-
-	if (poll_toggle_bit(0x0000) < 0)
-		return FLASH_FAIL;
-
-	write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1);
-	write_flash(SecFlashAOff + WRITESEQ2, WRITEDATA2);
-	write_flash(SecFlashAOff + WRITESEQ3, WRITEDATA3);
-	write_flash(SecFlashAOff + WRITESEQ4, WRITEDATA4);
-	write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5);
-	write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6);
-
-	if (poll_toggle_bit(SecFlashASec1Off) < 0)
-		return FLASH_FAIL;
-
-	write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1);
-	write_flash(PriFlashBOff + WRITESEQ2, WRITEDATA2);
-	write_flash(PriFlashBOff + WRITESEQ3, WRITEDATA3);
-	write_flash(PriFlashBOff + WRITESEQ4, WRITEDATA4);
-	write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5);
-	write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6);
-
-	if (poll_toggle_bit(PriFlashBOff) < 0)
-		return FLASH_FAIL;
-
-	write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1);
-	write_flash(SecFlashBOff + WRITESEQ2, WRITEDATA2);
-	write_flash(SecFlashBOff + WRITESEQ3, WRITEDATA3);
-	write_flash(SecFlashBOff + WRITESEQ4, WRITEDATA4);
-	write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5);
-	write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6);
-
-	if (poll_toggle_bit(SecFlashBOff) < 0)
-		return FLASH_FAIL;
-
-	return FLASH_SUCCESS;
-}
-
-int erase_block_flash(int nBlock, unsigned long address)
-{
-	long ulSectorOff = 0x0;
-
-	if ((nBlock < 0) || (nBlock > AFP_NumSectors))
-		return false;
-
-	ulSectorOff = (address - CONFIG_SYS_FLASH_BASE);
-
-	write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
-	write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
-	write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3);
-	write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4);
-	write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5);
-
-	write_flash(ulSectorOff, BlockEraseVal);
-
-	if (poll_toggle_bit(ulSectorOff) < 0)
-		return FLASH_FAIL;
-
-	return FLASH_SUCCESS;
-}
-
-void unlock_flash(long ulOffset)
-{
-	unsigned long ulOffsetAddr = ulOffset;
-	ulOffsetAddr &= 0xFFFF0000;
-
-	write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1);
-	write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2);
-	write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3);
-}
-
-int get_codes()
-{
-	int dev_id = 0;
-
-	write_flash(WRITESEQ1, GETCODEDATA1);
-	write_flash(WRITESEQ2, GETCODEDATA2);
-	write_flash(WRITESEQ3, GETCODEDATA3);
-
-	read_flash(0x0002, &dev_id);
-	dev_id &= 0x00FF;
-
-	reset_flash();
-
-	return dev_id;
-}
-
-void get_sector_number(long ulOffset, int *pnSector)
-{
-	int nSector = 0;
-
-	if (ulOffset >= SecFlashAOff) {
-		if ((ulOffset < SecFlashASec1Off)
-		    && (ulOffset < SecFlashASec2Off)) {
-			nSector = SECT32;
-		} else if ((ulOffset >= SecFlashASec2Off)
-			   && (ulOffset < SecFlashASec3Off)) {
-			nSector = SECT33;
-		} else if ((ulOffset >= SecFlashASec3Off)
-			   && (ulOffset < SecFlashASec4Off)) {
-			nSector = SECT34;
-		} else if ((ulOffset >= SecFlashASec4Off)
-			   && (ulOffset < SecFlashAEndOff)) {
-			nSector = SECT35;
-		}
-	} else if (ulOffset >= SecFlashBOff) {
-		if ((ulOffset < SecFlashBSec1Off)
-		    && (ulOffset < SecFlashBSec2Off)) {
-			nSector = SECT36;
-		}
-		if ((ulOffset < SecFlashBSec2Off)
-		    && (ulOffset < SecFlashBSec3Off)) {
-			nSector = SECT37;
-		}
-		if ((ulOffset < SecFlashBSec3Off)
-		    && (ulOffset < SecFlashBSec4Off)) {
-			nSector = SECT38;
-		}
-		if ((ulOffset < SecFlashBSec4Off)
-		    && (ulOffset < SecFlashBEndOff)) {
-			nSector = SECT39;
-		}
-	} else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) {
-		nSector = ulOffset & 0xffff0000;
-		nSector = ulOffset >> 16;
-		nSector = nSector & 0x000ff;
-	}
-
-	if ((nSector >= 0) && (nSector < AFP_NumSectors)) {
-		*pnSector = nSector;
-	}
-}
diff --git a/board/bf533-ezkit/psd4256.h b/board/bf533-ezkit/psd4256.h
deleted file mode 100644
index 9256696..0000000
--- a/board/bf533-ezkit/psd4256.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * U-Boot - psd4256.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Flash A/B Port A configuration registers.
- * Addresses are offset values to CONFIG_SYS_FLASH1_BASE
- * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B.
- */
-
-#define	PSD_PORTA_DIN	0x070000
-#define	PSD_PORTA_DOUT	0x070004
-#define	PSD_PORTA_DIR	0x070006
-
-/*
- * Flash A/B Port B configuration registers
- * Addresses are offset values to CONFIG_SYS_FLASH1_BASE
- * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B.
- */
-
-#define	PSD_PORTB_DIN	0x070001
-#define	PSD_PORTB_DOUT	0x070005
-#define	PSD_PORTB_DIR	0x070007
-
-/*
- * Flash A Port A Bit definitions
- */
-
-#define	PSDA_PPICLK1	0x20	/* PPI Clock select bit 1               */
-#define	PSDA_PPICLK0	0x10	/* PPI Clock select bit 0               */
-#define	PSDA_VDEC_RST	0x08	/* Video decoder reset, 0 = RESET       */
-#define	PSDA_VENC_RST	0x04	/* Video encoder reset, 0 = RESET       */
-#define	PSDA_CODEC_RST	0x01	/* Codec reset, 0 = RESET               */
-
-/*
- * Flash A Port B Bit definitions
- */
-
-#define	PSDA_LED9	0x20	/* LED 9, 1 = LED ON                    */
-#define	PSDA_LED8	0x10	/* LED 8, 1 = LED ON                    */
-#define	PSDA_LED7	0x08	/* LED 7, 1 = LED ON                    */
-#define	PSDA_LED6	0x04	/* LED 6, 1 = LED ON                    */
-#define	PSDA_LED5	0x02	/* LED 5, 1 = LED ON                    */
-#define	PSDA_LED4	0x01	/* LED 4, 1 = LED ON                    */
diff --git a/board/bf533-stamp/Kconfig b/board/bf533-stamp/Kconfig
deleted file mode 100644
index 0cffde3..0000000
--- a/board/bf533-stamp/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF533_STAMP
-
-config SYS_BOARD
-	default "bf533-stamp"
-
-config SYS_CONFIG_NAME
-	default "bf533-stamp"
-
-endif
diff --git a/board/bf533-stamp/MAINTAINERS b/board/bf533-stamp/MAINTAINERS
deleted file mode 100644
index c7aeefa..0000000
--- a/board/bf533-stamp/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF533-STAMP BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf533-stamp/
-F:	include/configs/bf533-stamp.h
-F:	configs/bf533-stamp_defconfig
diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile
deleted file mode 100644
index 041c98e..0000000
--- a/board/bf533-stamp/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf533-stamp.o
-obj-$(CONFIG_STAMP_CF) += ide-cf.o
-obj-$(CONFIG_VIDEO) += video.o
diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c
deleted file mode 100644
index eb000a6..0000000
--- a/board/bf533-stamp/bf533-stamp.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF533 Stamp board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-/* PF0 and PF1 are used to switch between the ethernet and flash:
- *         PF0  PF1
- *  flash:  0    0
- *  ether:  1    0
- */
-void swap_to(int device_id)
-{
-	gpio_request(GPIO_PF0, "eth_flash_swap");
-	gpio_request(GPIO_PF1, "eth_flash_swap");
-	gpio_direction_output(GPIO_PF0, device_id == ETHERNET);
-	gpio_direction_output(GPIO_PF1, 0);
-	SSYNC();
-}
-
-#if defined(CONFIG_MISC_INIT_R)
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
-#ifdef CONFIG_STAMP_CF
-	cf_ide_init();
-#endif
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-
-#define STATUS_LED_OFF 0
-#define STATUS_LED_ON  1
-
-static int gpio_setup;
-
-static void stamp_led_set(int LED1, int LED2, int LED3)
-{
-	if (!gpio_setup) {
-		gpio_request(GPIO_PF2, "boot_progress");
-		gpio_request(GPIO_PF3, "boot_progress");
-		gpio_request(GPIO_PF4, "boot_progress");
-		gpio_direction_output(GPIO_PF2, LED1);
-		gpio_direction_output(GPIO_PF3, LED2);
-		gpio_direction_output(GPIO_PF4, LED3);
-		gpio_setup = 1;
-	} else {
-		gpio_set_value(GPIO_PF2, LED1);
-		gpio_set_value(GPIO_PF3, LED2);
-		gpio_set_value(GPIO_PF4, LED3);
-	}
-}
-
-void show_boot_progress(int status)
-{
-	switch (status) {
-	case BOOTSTAGE_ID_CHECK_MAGIC:
-		stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON);
-		break;
-	case BOOTSTAGE_ID_CHECK_HEADER:
-		stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF);
-		break;
-	case BOOTSTAGE_ID_CHECK_CHECKSUM:
-		stamp_led_set(STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON);
-		break;
-	case BOOTSTAGE_ID_CHECK_ARCH:
-		stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF);
-		break;
-	case BOOTSTAGE_ID_CHECK_IMAGETYPE:
-	case BOOTSTAGE_ID_DECOMP_IMAGE:
-		stamp_led_set(STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON);
-		break;
-	case BOOTSTAGE_ID_KERNEL_LOADED:
-	case BOOTSTAGE_ID_CHECK_BOOT_OS:
-		stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF);
-		break;
-	case BOOTSTAGE_ID_BOOT_OS_RETURNED:
-	case BOOTSTAGE_ID_RD_MAGIC:
-	case BOOTSTAGE_ID_RD_HDR_CHECKSUM:
-	case BOOTSTAGE_ID_RD_CHECKSUM:
-	case BOOTSTAGE_ID_RAMDISK:
-	case BOOTSTAGE_ID_NO_RAMDISK:
-	case BOOTSTAGE_ID_RUN_OS:
-		stamp_led_set(STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_OFF);
-		break;
-	default:
-		stamp_led_set(STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON);
-		break;
-	}
-}
-#endif
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
-	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk
deleted file mode 100644
index 7f9138b..0000000
--- a/board/bf533-stamp/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf533-stamp/ide-cf.c b/board/bf533-stamp/ide-cf.c
deleted file mode 100644
index 3e4080e..0000000
--- a/board/bf533-stamp/ide-cf.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * CF IDE addon card code
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-void cf_outb(unsigned char val, volatile unsigned char *addr)
-{
-	/* "ETHERNET" means the expansion memory banks */
-	swap_to(ETHERNET);
-
-	*addr = val;
-	SSYNC();
-
-	swap_to(FLASH);
-}
-
-unsigned char cf_inb(volatile unsigned char *addr)
-{
-	unsigned char c;
-
-	swap_to(ETHERNET);
-
-	c = *addr;
-	SSYNC();
-
-	swap_to(FLASH);
-
-	return c;
-}
-
-void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
-{
-	int i;
-
-	swap_to(ETHERNET);
-
-	for (i = 0; i < words; i++) {
-		*(sect_buf + i) = *addr;
-		SSYNC();
-	}
-
-	swap_to(FLASH);
-}
-
-void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
-{
-	int i;
-
-	swap_to(ETHERNET);
-
-	for (i = 0; i < words; i++) {
-		*addr = *(sect_buf + i);
-		SSYNC();
-	}
-
-	swap_to(FLASH);
-}
-
-/* Definitions used in  Compact Flash Boot support */
-#define FIO_EDGE_CF_BITS	0x0000
-#define FIO_POLAR_CF_BITS	0x0000
-#define FIO_EDGE_BITS		0x1E0
-#define FIO_POLAR_BITS		0x160
-
-/* Compact flash status bits in status register */
-#define CF_STAT_BITS	0x00000060
-
-void cf_ide_init(void)
-{
-	int i, cf_stat;
-
-	/* Check whether CF card is inserted */
-	bfin_write_FIO_EDGE(FIO_EDGE_CF_BITS);
-	bfin_write_FIO_POLAR(FIO_POLAR_CF_BITS);
-	for (i = 0; i < 0x300; i++)
-		asm volatile("nop;");
-
-	cf_stat = bfin_read_FIO_FLAG_S() & CF_STAT_BITS;
-
-	bfin_write_FIO_EDGE(FIO_EDGE_BITS);
-	bfin_write_FIO_POLAR(FIO_POLAR_BITS);
-
-	if (!cf_stat) {
-		for (i = 0; i < 0x3000; i++)
-			asm volatile("nop;");
-
-		ide_init();
-	}
-}
diff --git a/board/bf533-stamp/video.c b/board/bf533-stamp/video.c
deleted file mode 100644
index e9b9a9a..0000000
--- a/board/bf533-stamp/video.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * BF533-STAMP splash driver
- *
- * Copyright (c) 2006-2008 Analog Devices Inc.
- * (C) Copyright 2000
- * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
- * (C) Copyright 2002
- * Wolfgang Denk, wd@denx.de
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/dma.h>
-#include <i2c.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-
-#define DMA_SIZE16	2
-
-#include <asm/mach-common/bits/ppi.h>
-
-#define NTSC_FRAME_ADDR 0x06000000
-#include "video.h"
-
-/* NTSC OUTPUT SIZE  720 * 240 */
-#define VERTICAL	2
-#define HORIZONTAL	4
-
-int is_vblank_line(const int line)
-{
-	/*
-	 *  This array contains a single bit for each line in
-	 *  an NTSC frame.
-	 */
-	if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528))
-		return true;
-
-	return false;
-}
-
-int NTSC_framebuffer_init(char *base_address)
-{
-	const int NTSC_frames = 1;
-	const int NTSC_lines = 525;
-	char *dest = base_address;
-	int frame_num, line_num;
-
-	for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) {
-		for (line_num = 1; line_num <= NTSC_lines; ++line_num) {
-			unsigned int code;
-			int offset = 0;
-			int i;
-
-			if (is_vblank_line(line_num))
-				offset++;
-
-			if (line_num > 266 || line_num < 3)
-				offset += 2;
-
-			/* Output EAV code */
-			code = system_code_map[offset].eav;
-			write_dest_byte((char)(code >> 24) & 0xff);
-			write_dest_byte((char)(code >> 16) & 0xff);
-			write_dest_byte((char)(code >> 8) & 0xff);
-			write_dest_byte((char)(code) & 0xff);
-
-			/* Output horizontal blanking */
-			for (i = 0; i < 67 * 2; ++i) {
-				write_dest_byte(0x80);
-				write_dest_byte(0x10);
-			}
-
-			/* Output SAV */
-			code = system_code_map[offset].sav;
-			write_dest_byte((char)(code >> 24) & 0xff);
-			write_dest_byte((char)(code >> 16) & 0xff);
-			write_dest_byte((char)(code >> 8) & 0xff);
-			write_dest_byte((char)(code) & 0xff);
-
-			/* Output empty horizontal data */
-			for (i = 0; i < 360 * 2; ++i) {
-				write_dest_byte(0x80);
-				write_dest_byte(0x10);
-			}
-		}
-	}
-
-	return dest - base_address;
-}
-
-void fill_frame(char *Frame, int Value)
-{
-	int *OddPtr32;
-	int OddLine;
-	int *EvenPtr32;
-	int EvenLine;
-	int i;
-	int *data;
-	int m, n;
-
-	/* fill odd and even frames */
-	for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) {
-		OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276);
-		EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276);
-		for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) {
-			*OddPtr32 = Value;
-			*EvenPtr32 = Value;
-		}
-	}
-
-	for (m = 0; m < VERTICAL; m++) {
-		data = (int *)u_boot_logo.data;
-		for (OddLine = (22 + m), EvenLine = (285 + m);
-		     OddLine < (u_boot_logo.height * VERTICAL) + (22 + m);
-		     OddLine += VERTICAL, EvenLine += VERTICAL) {
-			OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276);
-			EvenPtr32 =
-			    (int *)((Frame + ((EvenLine) * 1716)) + 276);
-			for (i = 0; i < u_boot_logo.width / 2; i++) {
-				/* enlarge one pixel to m x n */
-				for (n = 0; n < HORIZONTAL; n++) {
-					*OddPtr32++ = *data;
-					*EvenPtr32++ = *data;
-				}
-				data++;
-			}
-		}
-	}
-}
-
-static void video_init(char *NTSCFrame)
-{
-	NTSC_framebuffer_init(NTSCFrame);
-	fill_frame(NTSCFrame, BLUE);
-
-	bfin_write_PPI_CONTROL(0x0082);
-	bfin_write_PPI_FRAME(0x020D);
-
-	bfin_write_DMA0_START_ADDR(NTSCFrame);
-	bfin_write_DMA0_X_COUNT(0x035A);
-	bfin_write_DMA0_X_MODIFY(0x0002);
-	bfin_write_DMA0_Y_COUNT(0x020D);
-	bfin_write_DMA0_Y_MODIFY(0x0002);
-	bfin_write_DMA0_CONFIG(0x1015);
-	bfin_write_PPI_CONTROL(0x0083);
-}
-
-void video_stop(void)
-{
-	bfin_write_PPI_CONTROL(0);
-	bfin_write_DMA0_CONFIG(0);
-}
-
-int drv_video_init(void)
-{
-	struct stdio_dev videodev;
-
-	video_init((void *)NTSC_FRAME_ADDR);
-
-	memset(&videodev, 0, sizeof(videodev));
-	strcpy(videodev.name, "video");
-
-	return stdio_register(&videodev);
-}
diff --git a/board/bf533-stamp/video.h b/board/bf533-stamp/video.h
deleted file mode 100644
index 949c3d8..0000000
--- a/board/bf533-stamp/video.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#include <video_logo.h>
-#define write_dest_byte(val) {*dest++=val;}
-#define BLACK   (0x01800180)	/* black pixel pattern   */
-#define BLUE    (0x296E29F0)	/* blue pixel pattern    */
-#define RED     (0x51F0515A)	/* red pixel pattern     */
-#define MAGENTA (0x6ADE6ACA)	/* magenta pixel pattern */
-#define GREEN   (0x91229136)	/* green pixel pattern   */
-#define CYAN    (0xAA10AAA6)	/* cyan pixel pattern    */
-#define YELLOW  (0xD292D210)	/* yellow pixel pattern  */
-#define WHITE   (0xFE80FE80)	/* white pixel pattern   */
-
-typedef struct {
-	unsigned int sav;
-	unsigned int eav;
-} system_code_type;
-
-const system_code_type system_code_map[] = {
-	{ 0xFF000080, 0xFF00009D },
-	{ 0xFF0000AB, 0xFF0000B6 },
-	{ 0xFF0000C7, 0xFF0000DA },
-	{ 0xFF0000EC, 0xFF0000F1 },
-};
diff --git a/board/bf537-minotaur/Kconfig b/board/bf537-minotaur/Kconfig
deleted file mode 100644
index 204f609..0000000
--- a/board/bf537-minotaur/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF537_MINOTAUR
-
-config SYS_BOARD
-	default "bf537-minotaur"
-
-config SYS_CONFIG_NAME
-	default "bf537-minotaur"
-
-endif
diff --git a/board/bf537-minotaur/MAINTAINERS b/board/bf537-minotaur/MAINTAINERS
deleted file mode 100644
index 04643b1..0000000
--- a/board/bf537-minotaur/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF537-MINOTAUR BOARD
-M:	Martin Strubel <strubel@section5.ch>
-S:	Maintained
-F:	board/bf537-minotaur/
-F:	include/configs/bf537-minotaur.h
-F:	configs/bf537-minotaur_defconfig
diff --git a/board/bf537-minotaur/Makefile b/board/bf537-minotaur/Makefile
deleted file mode 100644
index 13ed8bf..0000000
--- a/board/bf537-minotaur/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf537-minotaur.o
diff --git a/board/bf537-minotaur/bf537-minotaur.c b/board/bf537-minotaur/bf537-minotaur.c
deleted file mode 100644
index 34750ec..0000000
--- a/board/bf537-minotaur/bf537-minotaur.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <netdev.h>
-#include <net.h>
-#include <asm/blackfin.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: CSP BF537 Minotaur board\n");
-	printf("       Support: http://www.camsig.co.uk/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
diff --git a/board/bf537-minotaur/config.mk b/board/bf537-minotaur/config.mk
deleted file mode 100644
index 7402f44..0000000
--- a/board/bf537-minotaur/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/bf537-pnav/Kconfig b/board/bf537-pnav/Kconfig
deleted file mode 100644
index acb1f89..0000000
--- a/board/bf537-pnav/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF537_PNAV
-
-config SYS_BOARD
-	default "bf537-pnav"
-
-config SYS_CONFIG_NAME
-	default "bf537-pnav"
-
-endif
diff --git a/board/bf537-pnav/MAINTAINERS b/board/bf537-pnav/MAINTAINERS
deleted file mode 100644
index b8b22a3..0000000
--- a/board/bf537-pnav/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF537-PNAV BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf537-pnav/
-F:	include/configs/bf537-pnav.h
-F:	configs/bf537-pnav_defconfig
diff --git a/board/bf537-pnav/Makefile b/board/bf537-pnav/Makefile
deleted file mode 100644
index f7af8cd..0000000
--- a/board/bf537-pnav/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf537-pnav.o
diff --git a/board/bf537-pnav/bf537-pnav.c b/board/bf537-pnav/bf537-pnav.c
deleted file mode 100644
index c3b06f0..0000000
--- a/board/bf537-pnav/bf537-pnav.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <netdev.h>
-#include <net.h>
-#include <asm/blackfin.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF537 PNAV board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
diff --git a/board/bf537-srv1/Kconfig b/board/bf537-srv1/Kconfig
deleted file mode 100644
index 2ddcd69..0000000
--- a/board/bf537-srv1/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF537_SRV1
-
-config SYS_BOARD
-	default "bf537-srv1"
-
-config SYS_CONFIG_NAME
-	default "bf537-srv1"
-
-endif
diff --git a/board/bf537-srv1/MAINTAINERS b/board/bf537-srv1/MAINTAINERS
deleted file mode 100644
index c8f1458..0000000
--- a/board/bf537-srv1/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF537-SRV1 BOARD
-M:	Martin Strubel <strubel@section5.ch>
-S:	Maintained
-F:	board/bf537-srv1/
-F:	include/configs/bf537-srv1.h
-F:	configs/bf537-srv1_defconfig
diff --git a/board/bf537-srv1/Makefile b/board/bf537-srv1/Makefile
deleted file mode 100644
index 1815fc5..0000000
--- a/board/bf537-srv1/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf537-srv1.o
diff --git a/board/bf537-srv1/bf537-srv1.c b/board/bf537-srv1/bf537-srv1.c
deleted file mode 100644
index fc22c07..0000000
--- a/board/bf537-srv1/bf537-srv1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <netdev.h>
-#include <net.h>
-#include <asm/blackfin.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: Surveyor SRV1 board\n");
-	printf("       Support: http://www.surveyor.com/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
diff --git a/board/bf537-srv1/config.mk b/board/bf537-srv1/config.mk
deleted file mode 100644
index 7402f44..0000000
--- a/board/bf537-srv1/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/bf537-stamp/Kconfig b/board/bf537-stamp/Kconfig
deleted file mode 100644
index 4f86128..0000000
--- a/board/bf537-stamp/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF537_STAMP
-
-config SYS_BOARD
-	default "bf537-stamp"
-
-config SYS_CONFIG_NAME
-	default "bf537-stamp"
-
-endif
diff --git a/board/bf537-stamp/MAINTAINERS b/board/bf537-stamp/MAINTAINERS
deleted file mode 100644
index 7d9c133..0000000
--- a/board/bf537-stamp/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF537-STAMP BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf537-stamp/
-F:	include/configs/bf537-stamp.h
-F:	configs/bf537-stamp_defconfig
diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile
deleted file mode 100644
index 4008e3a..0000000
--- a/board/bf537-stamp/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf537-stamp.o
-obj-$(CONFIG_BFIN_IDE)   += ide-cf.o
-obj-$(CONFIG_HAS_POST)   += post-memory.o
diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c
deleted file mode 100644
index 9b9daf4..0000000
--- a/board/bf537-stamp/bf537-stamp.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include <net.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF537 stamp board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
-{
-#ifndef CONFIG_SYS_NO_FLASH
-	/* we cram the MAC in the last flash sector */
-	uchar *board_mac_addr = (uchar *)0x203F0000;
-	if (is_valid_ethaddr(board_mac_addr)) {
-		memcpy(mac_addr, board_mac_addr, 6);
-		eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
-#endif
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
-#ifdef CONFIG_BFIN_MAC
-	uchar enetaddr[6];
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-		board_init_enetaddr(enetaddr);
-#endif
-
-#ifndef CONFIG_SYS_NO_FLASH
-	/* we use the last sector for the MAC address / POST LDR */
-	extern flash_info_t flash_info[];
-	flash_protect(FLAG_PROTECT_SET, 0x203F0000, 0x203FFFFF, &flash_info[0]);
-#endif
-
-#ifdef CONFIG_BFIN_IDE
-	cf_ide_init();
-#endif
-
-	return 0;
-}
diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk
deleted file mode 100644
index ab0fbec..0000000
--- a/board/bf537-stamp/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
-LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/bf537-stamp/ide-cf.c b/board/bf537-stamp/ide-cf.c
deleted file mode 100644
index 5a3720d..0000000
--- a/board/bf537-stamp/ide-cf.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * CF IDE addon card code
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <asm/blackfin.h>
-
-void cf_outb(unsigned char val, volatile unsigned char *addr)
-{
-	*(addr) = val;
-	SSYNC();
-}
-
-unsigned char cf_inb(volatile unsigned char *addr)
-{
-	volatile unsigned char c;
-
-	c = *(addr);
-	SSYNC();
-
-	return c;
-}
-
-void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words)
-{
-	int i;
-
-	for (i = 0; i < words; i++)
-		*(sect_buf + i) = *(addr);
-	SSYNC();
-}
-
-void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
-{
-	int i;
-
-	for (i = 0; i < words; i++)
-		*(addr) = *(sect_buf + i);
-	SSYNC();
-}
-
-void cf_ide_init(void)
-{
-#if defined(CONFIG_BFIN_TRUE_IDE)
-	/* Enable ATASEL when in True IDE mode */
-	printf("Using CF True IDE Mode\n");
-	cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_ENA);
-	udelay(1000);
-#elif defined(CONFIG_BFIN_CF_IDE)
-	/* Disable ATASEL when we're in Common Memory Mode */
-	printf("Using CF Common Memory Mode\n");
-	cf_outb(0, (unsigned char *)CONFIG_CF_ATASEL_DIS);
-	udelay(1000);
-#elif defined(CONFIG_BFIN_HDD_IDE)
-	printf("Using HDD IDE Mode\n");
-#endif
-	ide_init();
-}
diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c
deleted file mode 100644
index 2dea92f..0000000
--- a/board/bf537-stamp/post-memory.c
+++ /dev/null
@@ -1,257 +0,0 @@
-#include <common.h>
-#include <asm/io.h>
-
-#include <post.h>
-#include <watchdog.h>
-
-#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
-#define CLKIN 25000000
-#define PATTERN1 0x5A5A5A5A
-#define PATTERN2 0xAAAAAAAA
-
-#define CCLK_NUM	4
-#define SCLK_NUM	3
-
-void post_out_buff(char *buff);
-void post_init_pll(int mult, int div);
-int post_init_sdram(int sclk);
-void post_init_uart(int sclk);
-
-const int pll[CCLK_NUM][SCLK_NUM][2] = {
-	{ {20, 4}, {20, 5}, {20, 10} },	/* CCLK = 500M */
-	{ {16, 4}, {16, 5}, {16, 8} },	/* CCLK = 400M */
-	{ {8, 2}, {8, 4}, {8, 5} },	/* CCLK = 200M */
-	{ {4, 1}, {4, 2}, {4, 4} }	/* CCLK = 100M */
-};
-const char *const log[CCLK_NUM][SCLK_NUM] = {
-	{"CCLK-500MHz SCLK-125MHz:    Writing...\0",
-	 "CCLK-500MHz SCLK-100MHz:    Writing...\0",
-	 "CCLK-500MHz SCLK- 50MHz:    Writing...\0",},
-	{"CCLK-400MHz SCLK-100MHz:    Writing...\0",
-	 "CCLK-400MHz SCLK- 80MHz:    Writing...\0",
-	 "CCLK-400MHz SCLK- 50MHz:    Writing...\0",},
-	{"CCLK-200MHz SCLK-100MHz:    Writing...\0",
-	 "CCLK-200MHz SCLK- 50MHz:    Writing...\0",
-	 "CCLK-200MHz SCLK- 40MHz:    Writing...\0",},
-	{"CCLK-100MHz SCLK-100MHz:    Writing...\0",
-	 "CCLK-100MHz SCLK- 50MHz:    Writing...\0",
-	 "CCLK-100MHz SCLK- 25MHz:    Writing...\0",},
-};
-
-int memory_post_test(int flags)
-{
-	int addr;
-	int m, n;
-	int sclk, sclk_temp;
-	int ret = 1;
-
-	sclk_temp = CLKIN / 1000000;
-	sclk_temp = sclk_temp * CONFIG_VCO_MULT;
-	for (sclk = 0; sclk_temp > 0; sclk++)
-		sclk_temp -= CONFIG_SCLK_DIV;
-	sclk = sclk * 1000000;
-	post_init_uart(sclk);
-	if (post_hotkeys_pressed() == 0)
-		return 0;
-
-	for (m = 0; m < CCLK_NUM; m++) {
-		for (n = 0; n < SCLK_NUM; n++) {
-			/* Calculate the sclk */
-			sclk_temp = CLKIN / 1000000;
-			sclk_temp = sclk_temp * pll[m][n][0];
-			for (sclk = 0; sclk_temp > 0; sclk++)
-				sclk_temp -= pll[m][n][1];
-			sclk = sclk * 1000000;
-
-			post_init_pll(pll[m][n][0], pll[m][n][1]);
-			post_init_sdram(sclk);
-			post_init_uart(sclk);
-			post_out_buff("\n\r\0");
-			post_out_buff(log[m][n]);
-			for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4)
-				*(unsigned long *)addr = PATTERN1;
-			post_out_buff("Reading...\0");
-			for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4) {
-				if ((*(unsigned long *)addr) != PATTERN1) {
-					post_out_buff("Error\n\r\0");
-					ret = 0;
-				}
-			}
-			post_out_buff("OK\n\r\0");
-		}
-	}
-	if (ret)
-		post_out_buff("memory POST passed\n\r\0");
-	else
-		post_out_buff("memory POST failed\n\r\0");
-
-	post_out_buff("\n\r\n\r\0");
-	return 1;
-}
-
-void post_init_uart(int sclk)
-{
-	int divisor;
-
-	for (divisor = 0; sclk > 0; divisor++)
-		sclk -= 57600 * 16;
-
-	bfin_write_PORTF_FER(0x000F);
-	bfin_write_PORTH_FER(0xFFFF);
-
-	bfin_write_UART_GCTL(0x00);
-	bfin_write_UART_LCR(0x83);
-	SSYNC();
-	bfin_write_UART_DLL(divisor & 0xFF);
-	SSYNC();
-	bfin_write_UART_DLH((divisor >> 8) & 0xFF);
-	SSYNC();
-	bfin_write_UART_LCR(0x03);
-	SSYNC();
-	bfin_write_UART_GCTL(0x01);
-	SSYNC();
-}
-
-void post_out_buff(char *buff)
-{
-
-	int i = 0;
-	for (i = 0; i < 0x80000; i++)
-		;
-	i = 0;
-	while ((buff[i] != '\0') && (i != 100)) {
-		while (!(bfin_read_pUART_LSR() & 0x20)) ;
-		bfin_write_UART_THR(buff[i]);
-		SSYNC();
-		i++;
-	}
-	for (i = 0; i < 0x80000; i++)
-		;
-}
-
-void post_init_pll(int mult, int div)
-{
-
-	bfin_write_SIC_IWR(0x01);
-	bfin_write_PLL_CTL((mult << 9));
-	bfin_write_PLL_DIV(div);
-	asm("CLI R2;");
-	asm("IDLE;");
-	asm("STI R2;");
-	while (!(bfin_read_PLL_STAT() & 0x20)) ;
-}
-
-int post_init_sdram(int sclk)
-{
-	int SDRAM_tRP, SDRAM_tRP_num, SDRAM_tRAS, SDRAM_tRAS_num, SDRAM_tRCD,
-	    SDRAM_tWR;
-	int SDRAM_Tref, SDRAM_NRA, SDRAM_CL, SDRAM_SIZE, SDRAM_WIDTH,
-	    mem_SDGCTL, mem_SDBCTL, mem_SDRRC;
-
-	if ((sclk > 119402985)) {
-		SDRAM_tRP = TRP_2;
-		SDRAM_tRP_num = 2;
-		SDRAM_tRAS = TRAS_7;
-		SDRAM_tRAS_num = 7;
-		SDRAM_tRCD = TRCD_2;
-		SDRAM_tWR = TWR_2;
-	} else if ((sclk > 104477612) && (sclk <= 119402985)) {
-		SDRAM_tRP = TRP_2;
-		SDRAM_tRP_num = 2;
-		SDRAM_tRAS = TRAS_6;
-		SDRAM_tRAS_num = 6;
-		SDRAM_tRCD = TRCD_2;
-		SDRAM_tWR = TWR_2;
-	} else if ((sclk > 89552239) && (sclk <= 104477612)) {
-		SDRAM_tRP = TRP_2;
-		SDRAM_tRP_num = 2;
-		SDRAM_tRAS = TRAS_5;
-		SDRAM_tRAS_num = 5;
-		SDRAM_tRCD = TRCD_2;
-		SDRAM_tWR = TWR_2;
-	} else if ((sclk > 74626866) && (sclk <= 89552239)) {
-		SDRAM_tRP = TRP_2;
-		SDRAM_tRP_num = 2;
-		SDRAM_tRAS = TRAS_4;
-		SDRAM_tRAS_num = 4;
-		SDRAM_tRCD = TRCD_2;
-		SDRAM_tWR = TWR_2;
-	} else if ((sclk > 66666667) && (sclk <= 74626866)) {
-		SDRAM_tRP = TRP_2;
-		SDRAM_tRP_num = 2;
-		SDRAM_tRAS = TRAS_3;
-		SDRAM_tRAS_num = 3;
-		SDRAM_tRCD = TRCD_2;
-		SDRAM_tWR = TWR_2;
-	} else if ((sclk > 59701493) && (sclk <= 66666667)) {
-		SDRAM_tRP = TRP_1;
-		SDRAM_tRP_num = 1;
-		SDRAM_tRAS = TRAS_4;
-		SDRAM_tRAS_num = 4;
-		SDRAM_tRCD = TRCD_1;
-		SDRAM_tWR = TWR_2;
-	} else if ((sclk > 44776119) && (sclk <= 59701493)) {
-		SDRAM_tRP = TRP_1;
-		SDRAM_tRP_num = 1;
-		SDRAM_tRAS = TRAS_3;
-		SDRAM_tRAS_num = 3;
-		SDRAM_tRCD = TRCD_1;
-		SDRAM_tWR = TWR_2;
-	} else if ((sclk > 29850746) && (sclk <= 44776119)) {
-		SDRAM_tRP = TRP_1;
-		SDRAM_tRP_num = 1;
-		SDRAM_tRAS = TRAS_2;
-		SDRAM_tRAS_num = 2;
-		SDRAM_tRCD = TRCD_1;
-		SDRAM_tWR = TWR_2;
-	} else if (sclk <= 29850746) {
-		SDRAM_tRP = TRP_1;
-		SDRAM_tRP_num = 1;
-		SDRAM_tRAS = TRAS_1;
-		SDRAM_tRAS_num = 1;
-		SDRAM_tRCD = TRCD_1;
-		SDRAM_tWR = TWR_2;
-	} else {
-		SDRAM_tRP = TRP_1;
-		SDRAM_tRP_num = 1;
-		SDRAM_tRAS = TRAS_1;
-		SDRAM_tRAS_num = 1;
-		SDRAM_tRCD = TRCD_1;
-		SDRAM_tWR = TWR_2;
-	}
-	/*SDRAM INFORMATION: */
-	SDRAM_Tref = 64;	/* Refresh period in milliseconds */
-	SDRAM_NRA = 4096;	/* Number of row addresses in SDRAM */
-	SDRAM_CL = CL_3;	/* 2 */
-
-	SDRAM_SIZE = EBSZ_64;
-	SDRAM_WIDTH = EBCAW_10;
-
-	mem_SDBCTL = SDRAM_WIDTH | SDRAM_SIZE | EBE;
-
-	/* Equation from section 17 (p17-46) of BF533 HRM */
-	mem_SDRRC =
-	    (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) -
-	    (SDRAM_tRAS_num + SDRAM_tRP_num);
-
-	/* Enable SCLK Out */
-	mem_SDGCTL =
-	    (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR
-	     | PSS);
-
-	SSYNC();
-
-	bfin_write_EBIU_SDGCTL(bfin_write_EBIU_SDGCTL() | 0x1000000);
-	/* Set the SDRAM Refresh Rate control register based on SSCLK value */
-	bfin_write_EBIU_SDRRC(mem_SDRRC);
-
-	/* SDRAM Memory Bank Control Register */
-	bfin_write_EBIU_SDBCTL(mem_SDBCTL);
-
-	/* SDRAM Memory Global Control Register */
-	bfin_write_EBIU_SDGCTL(mem_SDGCTL);
-	SSYNC();
-	return mem_SDRRC;
-}
-
-#endif				/* CONFIG_POST & CONFIG_SYS_POST_MEMORY */
diff --git a/board/bf538f-ezkit/Kconfig b/board/bf538f-ezkit/Kconfig
deleted file mode 100644
index e40fcdb..0000000
--- a/board/bf538f-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF538F_EZKIT
-
-config SYS_BOARD
-	default "bf538f-ezkit"
-
-config SYS_CONFIG_NAME
-	default "bf538f-ezkit"
-
-endif
diff --git a/board/bf538f-ezkit/MAINTAINERS b/board/bf538f-ezkit/MAINTAINERS
deleted file mode 100644
index 7964735..0000000
--- a/board/bf538f-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF538F-EZKIT BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf538f-ezkit/
-F:	include/configs/bf538f-ezkit.h
-F:	configs/bf538f-ezkit_defconfig
diff --git a/board/bf538f-ezkit/Makefile b/board/bf538f-ezkit/Makefile
deleted file mode 100644
index eb1703e..0000000
--- a/board/bf538f-ezkit/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf538f-ezkit.o
diff --git a/board/bf538f-ezkit/bf538f-ezkit.c b/board/bf538f-ezkit/bf538f-ezkit.c
deleted file mode 100644
index 2dd4c0c..0000000
--- a/board/bf538f-ezkit/bf538f-ezkit.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <config.h>
-#include <asm/blackfin.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF538F EZ-Kit Lite board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
-	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/bf538f-ezkit/config.mk b/board/bf538f-ezkit/config.mk
deleted file mode 100644
index 7f9138b..0000000
--- a/board/bf538f-ezkit/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/bf548-ezkit/Kconfig b/board/bf548-ezkit/Kconfig
deleted file mode 100644
index 550227f..0000000
--- a/board/bf548-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF548_EZKIT
-
-config SYS_BOARD
-	default "bf548-ezkit"
-
-config SYS_CONFIG_NAME
-	default "bf548-ezkit"
-
-endif
diff --git a/board/bf548-ezkit/MAINTAINERS b/board/bf548-ezkit/MAINTAINERS
deleted file mode 100644
index e2683bb..0000000
--- a/board/bf548-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF548-EZKIT BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf548-ezkit/
-F:	include/configs/bf548-ezkit.h
-F:	configs/bf548-ezkit_defconfig
diff --git a/board/bf548-ezkit/Makefile b/board/bf548-ezkit/Makefile
deleted file mode 100644
index e4d0caa..0000000
--- a/board/bf548-ezkit/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf548-ezkit.o
-obj-$(CONFIG_VIDEO)      += video.o
diff --git a/board/bf548-ezkit/bf548-ezkit.c b/board/bf548-ezkit/bf548-ezkit.c
deleted file mode 100644
index 31d6eee..0000000
--- a/board/bf548-ezkit/bf548-ezkit.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-#include <asm/sdh.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF548 EZ-Kit board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	/* Set async addr lines as peripheral */
-	const unsigned short pins[] = {
-		P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
-		P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20,
-		P_A21, P_A22, P_A23, P_A24, 0
-	};
-	return peripheral_request_list(pins, "async");
-}
-
-#ifdef CONFIG_SMC911X
-int board_eth_init(bd_t *bis)
-{
-	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-#endif
-
-#ifdef CONFIG_BFIN_SDH
-int board_mmc_init(bd_t *bis)
-{
-	return bfin_mmc_init(bis);
-}
-#endif
-
-#ifdef CONFIG_USB_BLACKFIN
-void board_musb_init(void)
-{
-	/*
-	 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both device
-	 * and OTG host modes, while rev 1.1 and greater require PE7 to
-	 * be low for device mode and high for host mode.  We set it high
-	 * here because we are in host mode.
-	 */
-	gpio_request(GPIO_PE7, "musb-vbus");
-	gpio_direction_output(GPIO_PE7, 1);
-}
-#endif
diff --git a/board/bf548-ezkit/config.mk b/board/bf548-ezkit/config.mk
deleted file mode 100644
index 7bb8e9c..0000000
--- a/board/bf548-ezkit/config.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA       := --dma 6
-LDR_FLAGS-BFIN_BOOT_FIFO       := --dma 1
-LDR_FLAGS-BFIN_BOOT_SPI_MASTER := --dma 1
-LDR_FLAGS-BFIN_BOOT_UART       := --dma 1
-LDR_FLAGS-BFIN_BOOT_NAND       := --dma 6
diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c
deleted file mode 100644
index 3765993..0000000
--- a/board/bf548-ezkit/video.c
+++ /dev/null
@@ -1,335 +0,0 @@
-/*
- * video.c - run splash screen on lcd
- *
- * Copyright (c) 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/dma.h>
-#include <i2c.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-
-#include <lzma/LzmaTypes.h>
-#include <lzma/LzmaDec.h>
-#include <lzma/LzmaTools.h>
-
-#define DMA_SIZE16	2
-
-#include <asm/mach-common/bits/eppi.h>
-
-#include EASYLOGO_HEADER
-
-#define LCD_X_RES		480	/*Horizontal Resolution */
-#define LCD_Y_RES		272	/* Vertical Resolution */
-
-#define LCD_BPP			24	/* Bit Per Pixel */
-#define LCD_PIXEL_SIZE		(LCD_BPP / 8)
-#define	DMA_BUS_SIZE		32
-#define ACTIVE_VIDEO_MEM_OFFSET 0
-
-/* 	-- Horizontal synchronizing --
- *
- * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
- * (LCY-W-06602A Page 9 of 22)
- *
- * Clock Frequency 	1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
- *
- * Period 		TH - 525 - Clock
- * Pulse width 		THp - 41 - Clock
- * Horizontal period 	THd - 480 - Clock
- * Back porch 		THb - 2 - Clock
- * Front porch 		THf - 2 - Clock
- *
- * -- Vertical synchronizing --
- * Period 		TV - 286 - Line
- * Pulse width 		TVp - 10 - Line
- * Vertical period 	TVd - 272 - Line
- * Back porch 		TVb - 2 - Line
- * Front porch 		TVf - 2 - Line
- */
-
-#define	LCD_CLK         	(8*1000*1000)	/* 8MHz */
-
-/* # active data to transfer after Horizontal Delay clock */
-#define EPPI_HCOUNT		LCD_X_RES
-
-/* # active lines to transfer after Vertical Delay clock */
-#define EPPI_VCOUNT		LCD_Y_RES
-
-/* Samples per Line = 480 (active data) + 45 (padding) */
-#define EPPI_LINE		525
-
-/* Lines per Frame = 272 (active data) + 14 (padding) */
-#define EPPI_FRAME		286
-
-/* FS1 (Hsync) Width (Typical)*/
-#define EPPI_FS1W_HBL		41
-
-/* FS1 (Hsync) Period (Typical) */
-#define EPPI_FS1P_AVPL		EPPI_LINE
-
-/* Horizontal Delay clock after assertion of Hsync (Typical) */
-#define EPPI_HDELAY		43
-
-/* FS2 (Vsync) Width    = FS1 (Hsync) Period * 10 */
-#define EPPI_FS2W_LVB		(EPPI_LINE * 10)
-
- /* FS2 (Vsync) Period   = FS1 (Hsync) Period * Lines per Frame */
-#define EPPI_FS2P_LAVF		(EPPI_LINE * EPPI_FRAME)
-
-/* Vertical Delay after assertion of Vsync (2 Lines) */
-#define EPPI_VDELAY		12
-
-#define EPPI_CLIP		0xFF00FF00
-
-/* EPPI Control register configuration value for RGB out
- * - EPPI as Output
- * GP 2 frame sync mode,
- * Internal Clock generation disabled, Internal FS generation enabled,
- * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
- * FS1 & FS2 are active high,
- * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
- * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
- * Swapping Enabled,
- * One (DMA) Channel Mode,
- * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
- * Regular watermark - when FIFO is 100% full,
- * Urgent watermark - when FIFO is 75% full
- */
-
-#define EPPI_CONTROL		(0x20136E2E)
-
-static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
-{
-	u32 sclk = get_sclk();
-
-	/* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
-
-	return (((sclk / target_ppi_clk) / 2) - 1);
-}
-
-void Init_PPI(void)
-{
-	u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
-
-	bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
-	bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
-	bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
-	bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
-	bfin_write_EPPI0_CLIP(EPPI_CLIP);
-
-	bfin_write_EPPI0_FRAME(EPPI_FRAME);
-	bfin_write_EPPI0_LINE(EPPI_LINE);
-
-	bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
-	bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
-	bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
-	bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
-
-	bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
-
-/*
- * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
- * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
- */
-#if defined(CONFIG_VIDEO_RGB666)
-		bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
-					 RGB_FMT_EN);
-#else
-		bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
-					 ~RGB_FMT_EN);
-#endif
-
-}
-
-#define               DEB2_URGENT  0x2000     /* DEB2 Urgent */
-
-void Init_DMA(void *dst)
-{
-
-#if defined(CONFIG_DEB_DMA_URGENT)
-	bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT);
-#endif
-
-	bfin_write_DMA12_START_ADDR(dst);
-
-	/* X count */
-	bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
-	bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8);
-
-	/* Y count */
-	bfin_write_DMA12_Y_COUNT(LCD_Y_RES);
-	bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8);
-
-	/* DMA Config */
-	bfin_write_DMA12_CONFIG(
-		WDSIZE_32	|	/* 32 bit DMA */
-		DMA2D 		|	/* 2D DMA */
-		FLOW_AUTO		/* autobuffer mode */
-	);
-}
-
-void Init_Ports(void)
-{
-	const unsigned short pins[] = {
-		P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
-		P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9,
-		P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
-		P_PPI0_D15, P_PPI0_D16, P_PPI0_D17,
-#if !defined(CONFIG_VIDEO_RGB666)
-		P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22,
-		P_PPI0_D23,
-#endif
-		P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0,
-	};
-	peripheral_request_list(pins, "lcd");
-
-	gpio_request(GPIO_PE3, "lcd-disp");
-	gpio_direction_output(GPIO_PE3, 1);
-}
-
-void EnableDMA(void)
-{
-	bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN);
-}
-
-void DisableDMA(void)
-{
-	bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN);
-}
-
-/* enable and disable PPI functions */
-void EnablePPI(void)
-{
-	bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
-}
-
-void DisablePPI(void)
-{
-	bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
-}
-
-int video_init(void *dst)
-{
-	Init_Ports();
-	Init_DMA(dst);
-	EnableDMA();
-	Init_PPI();
-	EnablePPI();
-
-	return 0;
-}
-
-void video_stop(void)
-{
-	DisablePPI();
-	DisableDMA();
-}
-
-static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
-{
-	if (dcache_status())
-		blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
-
-	bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-	/* Setup destination start address */
-	bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
-					+ (y * LCD_X_RES * LCD_PIXEL_SIZE));
-	/* Setup destination xcount */
-	bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
-	/* Setup destination xmodify */
-	bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
-
-	/* Setup destination ycount */
-	bfin_write_MDMA_D0_Y_COUNT(logo->height);
-	/* Setup destination ymodify */
-	bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
-
-
-	/* Setup Source start address */
-	bfin_write_MDMA_S0_START_ADDR(logo->data);
-	/* Setup Source xcount */
-	bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
-	/* Setup Source xmodify */
-	bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
-
-	/* Setup Source ycount */
-	bfin_write_MDMA_S0_Y_COUNT(logo->height);
-	/* Setup Source ymodify */
-	bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
-
-
-	/* Enable source DMA */
-	bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
-	SSYNC();
-	bfin_write_MDMA_D0_CONFIG(WNR | DMAEN  | WDSIZE_16 | DMA2D);
-
-	while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
-
-	bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
-	bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
-
-}
-
-int drv_video_init(void)
-{
-	int error, devices = 1;
-	struct stdio_dev videodev;
-
-	u8 *dst;
-	u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
-
-	dst = malloc(fbmem_size);
-
-	if (dst == NULL) {
-		printf("Failed to alloc FB memory\n");
-		return -1;
-	}
-
-#ifdef EASYLOGO_ENABLE_GZIP
-	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
-	unsigned long src_len = EASYLOGO_ENABLE_GZIP;
-	error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len);
-	bfin_logo.data = data;
-#elif defined(EASYLOGO_ENABLE_LZMA)
-	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
-	SizeT lzma_len = bfin_logo.size;
-	error = lzmaBuffToBuffDecompress(data, &lzma_len,
-		bfin_logo.data, EASYLOGO_ENABLE_LZMA);
-	bfin_logo.data = data;
-#else
-	error = 0;
-#endif
-
-	if (error) {
-		puts("Failed to decompress logo\n");
-		free(dst);
-		return -1;
-	}
-
-	memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
-
-	dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
-			(LCD_X_RES - bfin_logo.width) / 2,
-			(LCD_Y_RES - bfin_logo.height) / 2);
-
-	video_init(dst);		/* Video initialization */
-
-	memset(&videodev, 0, sizeof(videodev));
-
-	strcpy(videodev.name, "video");
-
-	error = stdio_register(&videodev);
-
-	return (error == 0) ? devices : error;
-}
diff --git a/board/bf561-acvilon/Kconfig b/board/bf561-acvilon/Kconfig
deleted file mode 100644
index ba1580d..0000000
--- a/board/bf561-acvilon/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF561_ACVILON
-
-config SYS_BOARD
-	default "bf561-acvilon"
-
-config SYS_CONFIG_NAME
-	default "bf561-acvilon"
-
-endif
diff --git a/board/bf561-acvilon/MAINTAINERS b/board/bf561-acvilon/MAINTAINERS
deleted file mode 100644
index 056ee0b..0000000
--- a/board/bf561-acvilon/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF561-ACVILON BOARD
-M:	Valentin Yakovenkov <yakovenkov@niistt.ru>
-S:	Maintained
-F:	board/bf561-acvilon/
-F:	include/configs/bf561-acvilon.h
-F:	configs/bf561-acvilon_defconfig
diff --git a/board/bf561-acvilon/Makefile b/board/bf561-acvilon/Makefile
deleted file mode 100644
index 08e2fad..0000000
--- a/board/bf561-acvilon/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2009 CJSC "NII STT", Russia, Smolensk
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf561-acvilon.o
diff --git a/board/bf561-acvilon/bf561-acvilon.c b/board/bf561-acvilon/bf561-acvilon.c
deleted file mode 100644
index da4c844..0000000
--- a/board/bf561-acvilon/bf561-acvilon.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * File:         board/bf561-acvilon/bf561-acvilon.c
- * Based on:     board/bf561-ezkit/bf561-ezkit.c
- * Author:
- *
- * Created:      2009-06-23
- * Description:  Acvilon System On Module board file
- *
- * Modified:
- *               Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
- *               Copyright (c) 2005-2008 Analog Devices Inc.
- *
- *               (C) Copyright 2000-2004
- *               Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Bugs:
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board:  CJSC \"NII STT\"-=Acvilon Platform=- [U-Boot]\n");
-	printf("       Support: http://www.niistt.ru/\n");
-	return 0;
-}
-
-#ifdef CONFIG_SMC911X
-int board_eth_init(bd_t *bis)
-{
-	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-#endif
diff --git a/board/bf561-acvilon/config.mk b/board/bf561-acvilon/config.mk
deleted file mode 100644
index 854d7db..0000000
--- a/board/bf561-acvilon/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/bf561-ezkit/Kconfig b/board/bf561-ezkit/Kconfig
deleted file mode 100644
index 495a5c5..0000000
--- a/board/bf561-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF561_EZKIT
-
-config SYS_BOARD
-	default "bf561-ezkit"
-
-config SYS_CONFIG_NAME
-	default "bf561-ezkit"
-
-endif
diff --git a/board/bf561-ezkit/MAINTAINERS b/board/bf561-ezkit/MAINTAINERS
deleted file mode 100644
index 5ced3bb..0000000
--- a/board/bf561-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF561-EZKIT BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf561-ezkit/
-F:	include/configs/bf561-ezkit.h
-F:	configs/bf561-ezkit_defconfig
diff --git a/board/bf561-ezkit/Makefile b/board/bf561-ezkit/Makefile
deleted file mode 100644
index 3d534d2..0000000
--- a/board/bf561-ezkit/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf561-ezkit.o
diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c
deleted file mode 100644
index 534c39c..0000000
--- a/board/bf561-ezkit/bf561-ezkit.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: ADI BF561 EZ-Kit Lite board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
-	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk
deleted file mode 100644
index 854d7db..0000000
--- a/board/bf561-ezkit/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/bf609-ezkit/Kconfig b/board/bf609-ezkit/Kconfig
deleted file mode 100644
index 7992e1e..0000000
--- a/board/bf609-ezkit/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BF609_EZKIT
-
-config SYS_BOARD
-	default "bf609-ezkit"
-
-config SYS_CONFIG_NAME
-	default "bf609-ezkit"
-
-endif
diff --git a/board/bf609-ezkit/MAINTAINERS b/board/bf609-ezkit/MAINTAINERS
deleted file mode 100644
index acfc6c7..0000000
--- a/board/bf609-ezkit/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BF609-EZKIT BOARD
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-F:	board/bf609-ezkit/
-F:	include/configs/bf609-ezkit.h
-F:	configs/bf609-ezkit_defconfig
diff --git a/board/bf609-ezkit/Makefile b/board/bf609-ezkit/Makefile
deleted file mode 100644
index e4184ee..0000000
--- a/board/bf609-ezkit/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= bf609-ezkit.o
-obj-$(CONFIG_BFIN_SOFT_SWITCH)   += soft_switch.o
diff --git a/board/bf609-ezkit/bf609-ezkit.c b/board/bf609-ezkit/bf609-ezkit.c
deleted file mode 100644
index c993ca6..0000000
--- a/board/bf609-ezkit/bf609-ezkit.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/io.h>
-#include <asm/sdh.h>
-#include <asm/portmux.h>
-#include "soft_switch.h"
-
-int checkboard(void)
-{
-	printf("Board: ADI BF609 EZ-Kit board\n");
-	printf("       Support: http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	static const unsigned short pins[] = {
-		P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
-		P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
-		P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
-	};
-	peripheral_request_list(pins, "smc0");
-
-	return 0;
-}
-
-#ifdef CONFIG_ETH_DESIGNWARE
-int board_eth_init(bd_t *bis)
-{
-	int ret = 0;
-
-	if (CONFIG_DW_PORTS & 1) {
-		static const unsigned short pins[] = P_RMII0;
-		if (!peripheral_request_list(pins, "emac0"))
-			ret += designware_initialize(EMAC0_MACCFG, 0);
-	}
-	if (CONFIG_DW_PORTS & 2) {
-		static const unsigned short pins[] = P_RMII1;
-		if (!peripheral_request_list(pins, "emac1"))
-			ret += designware_initialize(EMAC1_MACCFG, 0);
-	}
-
-	return ret;
-}
-#endif
-
-#ifdef CONFIG_BFIN_SDH
-int board_mmc_init(bd_t *bis)
-{
-	return bfin_mmc_init(bis);
-}
-#endif
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
-	printf("other init\n");
-	return setup_board_switches();
-}
diff --git a/board/bf609-ezkit/soft_switch.c b/board/bf609-ezkit/soft_switch.c
deleted file mode 100644
index 7c117ea..0000000
--- a/board/bf609-ezkit/soft_switch.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "soft_switch.h"
-
-struct switch_config {
-	uchar dir0; /* IODIRA */
-	uchar dir1; /* IODIRB */
-	uchar value0; /* OLATA */
-	uchar value1; /* OLATB */
-};
-
-static struct switch_config switch_config_array[NUM_SWITCH] = {
-	{
-/*
-	U45 Port A                     U45 Port B
-
-	7---------------  RMII_CLK_EN  |  7--------------- ~TEMP_THERM_EN
-	| 6------------- ~CNT0ZM_EN    |  | 6------------- ~TEMP_IRQ_EN
-	| | 5----------- ~CNT0DG_EN    |  | | 5----------- ~UART0CTS_146_EN
-	| | | 4--------- ~CNT0UD_EN    |  | | | 4--------- ~UART0CTS_RST_EN
-	| | | | 3------- ~CAN0RX_EN    |  | | | | 3------- ~UART0CTS_RTS_LPBK
-	| | | | | 2----- ~CAN0_ERR_EN  |  | | | | | 2----- ~UART0CTS_EN
-	| | | | | | 1--- ~CAN_STB      |  | | | | | | 1--- ~UART0RX_EN
-	| | | | | | | 0-  CAN_EN       |  | | | | | | | 0- ~UART0RTS_EN
-	| | | | | | | |                |  | | | | | | | |
-	O O O O O O O O                |  O O O O O O O O   (I/O direction)
-	1 0 0 0 0 0 1 1                |  1 1 1 1 1 0 0 0   (value being set)
-*/
-		.dir0 = 0x0, /* all output */
-		.dir1 = 0x0, /* all output */
-		.value0 = RMII_CLK_EN | CAN_STB | CAN_EN,
-		.value1 = TEMP_THERM_EN | TEMP_IRQ_EN | UART0CTS_146_EN
-				| UART0CTS_RST_EN | UART0CTS_RTS_LPBK,
-	},
-	{
-/*
-	U46 Port A                       U46 Port B
-
-	7--------------- ~LED4_GPIO_EN   |  7---------------  EMPTY
-	| 6------------- ~LED3_GPIO_EN   |  | 6------------- ~SPI0D3_EN
-	| | 5----------- ~LED2_GPIO_EN   |  | | 5----------- ~SPI0D2_EN
-	| | | 4--------- ~LED1_GPIO_EN   |  | | | 4--------- ~SPIFLASH_CS_EN
-	| | | | 3-------  SMC0_LP0_EN    |  | | | | 3------- ~SD_WP_EN
-	| | | | | 2-----  EMPTY          |  | | | | | 2----- ~SD_CD_EN
-	| | | | | | 1---  SMC0_EPPI2     |  | | | | | | 1--- ~PUSHBUTTON2_EN
-			  _LP1_SWITCH
-	| | | | | | | 0-  OVERRIDE_SMC0  |  | | | | | | | 0- ~PUSHBUTTON1_EN
-			  _LP0_BOOT
-	| | | | | | | |                  |  | | | | | | | |
-	O O O O O O O O                  |  O O O O O O O O   (I/O direction)
-	0 0 0 0 0 X 0 1                  |  X 0 0 0 0 0 0 0   (value being set)
-*/
-		.dir0 = 0x0, /* all output */
-		.dir1 = 0x0, /* all output */
-#ifdef CONFIG_BFIN_LINKPORT
-		.value0 = OVERRIDE_SMC0_LP0_BOOT,
-#else
-		.value0 = SMC0_EPPI2_LP1_SWITCH,
-#endif
-		.value1 = 0x0,
-	},
-	{
-/*
-	U47 Port A                         U47 Port B
-
-	7--------------- ~PD2_SPI0MISO |  7---------------  EMPTY
-			  _EI3_EN
-	| 6------------- ~PD1_SPI0D3   |  | 6-------------  EMPTY
-			  _EPPI1D17
-			  _SPI0SEL2
-			  _EI3_EN
-	| | 5----------- ~PD0_SPI0D2   |  | | 5-----------  EMPTY
-			  _EPPI1D16
-			  _SPI0SEL3
-			  _EI3_EN
-	| | | 4--------- ~WAKE_PUSH    |  | | | 4---------  EMPTY
-			  BUTTON_EN
-	| | | | 3------- ~ETHERNET_EN  |  | | | | 3-------  EMPTY
-	| | | | | 2-----  PHYAD0       |  | | | | | 2-----  EMPTY
-	| | | | | | 1---  PHY_PWR      |  | | | | | | 1--- ~PD4_SPI0CK_EI3_EN
-			  _DWN_INT
-	| | | | | | | 0- ~PHYINT_EN    |  | | | | | | | 0- ~PD3_SPI0MOSI_EI3_EN
-	| | | | | | | |                |  | | | | | | | |
-	O O O O O I I O                |  O O O O O O O O   (I/O direction)
-	1 1 1 0 0 0 0 0                |  X X X X X X 1 1   (value being set)
-*/
-		.dir0 = 0x6, /* bits 1 and 2 input, all others output */
-		.dir1 = 0x0, /* all output */
-		.value0 = PD1_SPI0D3_EN | PD0_SPI0D2_EN,
-		.value1 = 0,
-	},
-};
-
-static int setup_soft_switch(int addr, struct switch_config *config)
-{
-	int ret = 0;
-
-	ret = i2c_write(addr, OLATA, 1, &config->value0, 1);
-	if (ret)
-		return ret;
-	ret = i2c_write(addr, OLATB, 1, &config->value1, 1);
-	if (ret)
-		return ret;
-
-	ret = i2c_write(addr, IODIRA, 1, &config->dir0, 1);
-	if (ret)
-		return ret;
-	return i2c_write(addr, IODIRB, 1, &config->dir1, 1);
-}
-
-int config_switch_bit(int addr, int port, int bit, int dir, uchar value)
-{
-	int ret, data_reg, dir_reg;
-	uchar tmp;
-
-	if (port == IO_PORT_A) {
-		data_reg = OLATA;
-		dir_reg = IODIRA;
-	} else {
-		data_reg = OLATB;
-		dir_reg = IODIRB;
-	}
-
-	if (dir == IO_PORT_INPUT) {
-		ret = i2c_read(addr, dir_reg, 1, &tmp, 1);
-		if (ret)
-			return ret;
-		tmp |= bit;
-		return i2c_write(addr, dir_reg, 1, &tmp, 1);
-	} else {
-		ret = i2c_read(addr, data_reg, 1, &tmp, 1);
-		if (ret)
-			return ret;
-		if (value)
-			tmp |= bit;
-		else
-			tmp &= ~bit;
-		ret = i2c_write(addr, data_reg, 1, &tmp, 1);
-		if (ret)
-			return ret;
-		ret = i2c_read(addr, dir_reg, 1, &tmp, 1);
-		if (ret)
-			return ret;
-		tmp &= ~bit;
-		return i2c_write(addr, dir_reg, 1, &tmp, 1);
-	}
-}
-
-int setup_board_switches(void)
-{
-	int ret;
-	int i;
-
-	for (i = 0; i < NUM_SWITCH; i++) {
-		ret = setup_soft_switch(SWITCH_ADDR + i,
-				&switch_config_array[i]);
-		if (ret)
-			return ret;
-	}
-	return 0;
-}
diff --git a/board/bf609-ezkit/soft_switch.h b/board/bf609-ezkit/soft_switch.h
deleted file mode 100644
index 75d64e2..0000000
--- a/board/bf609-ezkit/soft_switch.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BOARD_SOFT_SWITCH_H__
-#define __BOARD_SOFT_SWITCH_H__
-
-#include <asm/soft_switch.h>
-
-/* switch 0 port A */
-#define CAN_EN                 0x1
-#define CAN_STB                0x2
-#define CAN0_ERR_EN            0x4
-#define CAN0RX_EN              0x8
-#define CNT0UD_EN              0x10
-#define CNT0DG_EN              0x20
-#define CNT0ZM_EN              0x40
-#define RMII_CLK_EN            0x80
-
-/* switch 0 port B */
-#define UART0RTS_EN            0x1
-#define UART0RX_EN             0x2
-#define UART0CTS_EN            0x4
-#define UART0CTS_RTS_LPBK      0x8
-#define UART0CTS_RST_EN        0x10
-#define UART0CTS_146_EN        0x20
-#define TEMP_IRQ_EN            0x40
-#define TEMP_THERM_EN          0x80
-
-/* switch 1 port A */
-#define OVERRIDE_SMC0_LP0_BOOT 0x1
-#define SMC0_EPPI2_LP1_SWITCH  0x2
-#define SMC0_LP0_EN            0x8
-#define LED1_GPIO_EN           0x10
-#define LED2_GPIO_EN           0x20
-#define LED3_GPIO_EN           0x40
-#define LED4_GPIO_EN           0x80
-
-/* switch 1 port B */
-#define PUSHBUTTON1_EN         0x1
-#define PUSHBUTTON2_EN         0x2
-#define SD_CD_EN               0x4
-#define SD_WP_EN               0x8
-#define SPIFLASH_CS_EN         0x10
-#define SPI0D2_EN              0x20
-#define SPI0D3_EN              0x40
-
-/* switch 2 port A */
-#define PHYINT_EN              0x1
-#define PHY_PWR_DWN_INT        0x2
-#define PHYAD0                 0x4
-#define ETHERNET_EN            0x8
-#define WAKE_PUSHBUTTON_EN     0x10
-#define PD0_SPI0D2_EN          0x20
-#define PD1_SPI0D3_EN          0x40
-#define PD2_SPI0MISO_EN        0x80
-
-/* switch 2 port B */
-#define PD3_SPI0MOSI_EN        0x1
-#define PD4_SPI0CK_EN          0x2
-
-#ifdef CONFIG_BFIN_BOARD_VERSION_1_0
-#define SWITCH_ADDR     0x21
-#else
-#define SWITCH_ADDR     0x20
-#endif
-
-#define NUM_SWITCH      3
-#define IODIRA          0x0
-#define IODIRB          0x1
-#define OLATA           0x14
-#define OLATB           0x15
-
-int setup_board_switches(void);
-
-#endif /* __BOARD_SOFT_SWITCH_H__ */
diff --git a/board/blackstamp/Kconfig b/board/blackstamp/Kconfig
deleted file mode 100644
index 7ce086a..0000000
--- a/board/blackstamp/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BLACKSTAMP
-
-config SYS_BOARD
-	default "blackstamp"
-
-config SYS_CONFIG_NAME
-	default "blackstamp"
-
-endif
diff --git a/board/blackstamp/MAINTAINERS b/board/blackstamp/MAINTAINERS
deleted file mode 100644
index a0d72c6..0000000
--- a/board/blackstamp/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-BLACKSTAMP BOARD
-M:	Wojtek Skulski <skulski@pas.rochester.edu>
-M:	Wojtek Skulski <info@skutek.com>
-M:	Benjamin Matthews <mben12@gmail.com>
-S:	Maintained
-F:	board/blackstamp/
-F:	include/configs/blackstamp.h
-F:	configs/blackstamp_defconfig
diff --git a/board/blackstamp/Makefile b/board/blackstamp/Makefile
deleted file mode 100644
index 2ae79da..0000000
--- a/board/blackstamp/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= blackstamp.o
diff --git a/board/blackstamp/blackstamp.c b/board/blackstamp/blackstamp.c
deleted file mode 100644
index d233b8a..0000000
--- a/board/blackstamp/blackstamp.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * U-Boot - blackstamp.c BlackStamp board specific routines
- * Most code stolen from boards/bf533-stamp/bf533-stamp.c
- * Edited to the BlackStamp by Ben Matthews for UR LLE
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: BlackStamp\n");
-	printf("Support: http://blackfin.uclinux.org/gf/project/blackstamp/\n");
-	return 0;
-}
-
-#ifdef SHARED_RESOURCES
-void swap_to(int device_id)
-{
-	gpio_request(GPIO_PF0, "eth_flash_swap");
-	gpio_direction_output(GPIO_PF0, device_id == ETHERNET);
-	SSYNC();
-}
-#endif
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
-	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/blackvme/Kconfig b/board/blackvme/Kconfig
deleted file mode 100644
index 5e73f84..0000000
--- a/board/blackvme/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BLACKVME
-
-config SYS_BOARD
-	default "blackvme"
-
-config SYS_CONFIG_NAME
-	default "blackvme"
-
-endif
diff --git a/board/blackvme/MAINTAINERS b/board/blackvme/MAINTAINERS
deleted file mode 100644
index 3f8b32c..0000000
--- a/board/blackvme/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-BLACKVME BOARD
-M:	Wojtek Skulski <skulski@pas.rochester.edu>
-M:	Wojtek Skulski <info@skutek.com>
-M:	Benjamin Matthews <mben12@gmail.com>
-S:	Maintained
-F:	board/blackvme/
-F:	include/configs/blackvme.h
-F:	configs/blackvme_defconfig
diff --git a/board/blackvme/Makefile b/board/blackvme/Makefile
deleted file mode 100644
index 9a61775..0000000
--- a/board/blackvme/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= blackvme.o
diff --git a/board/blackvme/blackvme.c b/board/blackvme/blackvme.c
deleted file mode 100644
index d8932ed..0000000
--- a/board/blackvme/blackvme.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* U-Boot - blackvme.c  board specific routines
- * (c) Wojtek Skulski 2010 info@skutek.com
- * Board info: http://www.skutek.com
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-
-int checkboard(void)
-{
-	printf("Board: BlackVME\n");
-	printf("Support: http://www.skutek.com/\n");
-	return 0;
-}
-
-#ifdef CONFIG_DRIVER_AX88180
-/*
- * The ax88180 driver had to be patched to work around a bug
- * in Marvell 88E1111 B2 silicon. E-mail me for explanations.
- */
-int board_eth_init(bd_t *bis)
-{
-	return ax88180_initialize(bis);
-}
-#endif	/* CONFIG_DRIVER_AX88180 */
diff --git a/board/bluegiga/apx4devkit/apx4devkit.c b/board/bluegiga/apx4devkit/apx4devkit.c
index 08e79bd..2215c29 100644
--- a/board/bluegiga/apx4devkit/apx4devkit.c
+++ b/board/bluegiga/apx4devkit/apx4devkit.c
@@ -17,6 +17,7 @@
 #include <common.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
+#include <asm/setup.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux-mx28.h>
 #include <asm/arch/clock.h>
diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c
index 2a36d29..e82c691 100644
--- a/board/bluewater/gurnard/gurnard.c
+++ b/board/bluewater/gurnard/gurnard.c
@@ -21,6 +21,7 @@
 #include <spi.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
+#include <asm/mach-types.h>
 #include <asm/arch/at91sam9g45_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
@@ -414,12 +415,6 @@ void reset_phy(void)
 {
 }
 
-/* This breaks the Ethernet MAC at present */
-void enable_caches(void)
-{
-	dcache_enable();
-}
-
 /* SPI chip select control - only used for FPGA programming */
 #ifdef CONFIG_ATMEL_SPI
 
diff --git a/board/bluewater/snapper9260/snapper9260.c b/board/bluewater/snapper9260/snapper9260.c
index 2d1a89e..7e9da4e 100644
--- a/board/bluewater/snapper9260/snapper9260.c
+++ b/board/bluewater/snapper9260/snapper9260.c
@@ -12,6 +12,7 @@
 #include <dm.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
+#include <asm/mach-types.h>
 #include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c
index e90693f..38577f3 100644
--- a/board/bosch/shc/board.c
+++ b/board/bosch/shc/board.c
@@ -632,7 +632,7 @@ void arch_preboot_os(void)
 	leds_set_finish();
 }
 
-#if defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	int ret;
diff --git a/board/boundary/nitrogen6x/nitrogen6dl.cfg b/board/boundary/nitrogen6x/nitrogen6dl.cfg
index 1cdccad..5c3e961 100644
--- a/board/boundary/nitrogen6x/nitrogen6dl.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6dl.cfg
@@ -20,6 +20,9 @@ BOOT_FROM      spi
 
 #define __ASSEMBLY__
 #include <config.h>
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
 #include "asm/arch/mx6-ddr.h"
 #include "asm/arch/iomux.h"
 #include "asm/arch/crm_regs.h"
diff --git a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
index 516d67e..fe19ed0 100644
--- a/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6dl2g.cfg
@@ -20,6 +20,9 @@ BOOT_FROM      spi
 
 #define __ASSEMBLY__
 #include <config.h>
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
 #include "asm/arch/mx6-ddr.h"
 #include "asm/arch/iomux.h"
 #include "asm/arch/crm_regs.h"
diff --git a/board/boundary/nitrogen6x/nitrogen6q.cfg b/board/boundary/nitrogen6x/nitrogen6q.cfg
index b6642e6..60e1885 100644
--- a/board/boundary/nitrogen6x/nitrogen6q.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6q.cfg
@@ -20,6 +20,9 @@ BOOT_FROM      spi
 
 #define __ASSEMBLY__
 #include <config.h>
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
 #include "asm/arch/mx6-ddr.h"
 #include "asm/arch/iomux.h"
 #include "asm/arch/crm_regs.h"
diff --git a/board/boundary/nitrogen6x/nitrogen6q2g.cfg b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
index fe6dfc1..7a3ee94 100644
--- a/board/boundary/nitrogen6x/nitrogen6q2g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6q2g.cfg
@@ -20,6 +20,9 @@ BOOT_FROM      spi
 
 #define __ASSEMBLY__
 #include <config.h>
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
 #include "asm/arch/mx6-ddr.h"
 #include "asm/arch/iomux.h"
 #include "asm/arch/crm_regs.h"
diff --git a/board/boundary/nitrogen6x/nitrogen6s.cfg b/board/boundary/nitrogen6x/nitrogen6s.cfg
index ca30cd6..2540b7b 100644
--- a/board/boundary/nitrogen6x/nitrogen6s.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6s.cfg
@@ -20,6 +20,9 @@ BOOT_FROM      spi
 
 #define __ASSEMBLY__
 #include <config.h>
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
 #include "asm/arch/mx6-ddr.h"
 #include "asm/arch/iomux.h"
 #include "asm/arch/crm_regs.h"
diff --git a/board/boundary/nitrogen6x/nitrogen6s1g.cfg b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
index b1489fb..946af7b 100644
--- a/board/boundary/nitrogen6x/nitrogen6s1g.cfg
+++ b/board/boundary/nitrogen6x/nitrogen6s1g.cfg
@@ -20,6 +20,9 @@ BOOT_FROM      spi
 
 #define __ASSEMBLY__
 #include <config.h>
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
 #include "asm/arch/mx6-ddr.h"
 #include "asm/arch/iomux.h"
 #include "asm/arch/crm_regs.h"
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index a3a56ca..17fd6f5 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -13,14 +13,14 @@
 #include <asm/arch/sys_proto.h>
 #include <malloc.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/spi.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/spi.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <micrel.h>
@@ -903,7 +903,7 @@ int board_init(void)
 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 
-#ifdef CONFIG_CMD_SATA
+#ifdef CONFIG_SATA
 	setup_sata();
 #endif
 
diff --git a/board/br4/Kconfig b/board/br4/Kconfig
deleted file mode 100644
index a10a060..0000000
--- a/board/br4/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_BR4
-
-config SYS_BOARD
-	default "br4"
-
-config SYS_CONFIG_NAME
-	default "br4"
-
-endif
diff --git a/board/br4/MAINTAINERS b/board/br4/MAINTAINERS
deleted file mode 100644
index 4085da5..0000000
--- a/board/br4/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BR4 BOARD
-M:	Dimitar Penev <dpn@switchfin.org>
-S:	Maintained
-F:	board/br4/
-F:	include/configs/br4.h
-F:	configs/br4_defconfig
diff --git a/board/br4/Makefile b/board/br4/Makefile
deleted file mode 100644
index c6c03ab..0000000
--- a/board/br4/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) Switchfin Org. <dpn@switchfin.org>
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= br4.o
diff --git a/board/br4/br4.c b/board/br4/br4.c
deleted file mode 100644
index 6f3f170..0000000
--- a/board/br4/br4.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) Switchfin Org. <dpn@switchfin.org>
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-
-int checkboard(void)
-{
-	printf("Board: Switchvoice BR4 Appliance\n");
-	printf("       Support: http://www.switchvoice.com/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
diff --git a/board/broadcom/bcm23550_w1d/bcm23550_w1d.c b/board/broadcom/bcm23550_w1d/bcm23550_w1d.c
index 0cb059f..5f4c634 100644
--- a/board/broadcom/bcm23550_w1d/bcm23550_w1d.c
+++ b/board/broadcom/bcm23550_w1d/bcm23550_w1d.c
@@ -62,13 +62,15 @@ int dram_init(void)
 }
 
 /* This is called after dram_init() so use get_ram_size result */
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
-#ifdef CONFIG_KONA_SDHCI
+#ifdef CONFIG_MMC_SDHCI_KONA
 /*
  * mmc_init - Initializes mmc
  */
diff --git a/board/broadcom/bcm28155_ap/bcm28155_ap.c b/board/broadcom/bcm28155_ap/bcm28155_ap.c
index b3a4a41..f5b94f6 100644
--- a/board/broadcom/bcm28155_ap/bcm28155_ap.c
+++ b/board/broadcom/bcm28155_ap/bcm28155_ap.c
@@ -69,13 +69,15 @@ int dram_init(void)
 }
 
 /* This is called after dram_init() so use get_ram_size result */
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
-#ifdef CONFIG_KONA_SDHCI
+#ifdef CONFIG_MMC_SDHCI_KONA
 /*
  * mmc_init - Initializes mmc
  */
diff --git a/board/broadcom/bcm958712k/MAINTAINERS b/board/broadcom/bcm958712k/MAINTAINERS
new file mode 100644
index 0000000..024fb14
--- /dev/null
+++ b/board/broadcom/bcm958712k/MAINTAINERS
@@ -0,0 +1,6 @@
+BCM958712K BOARD
+M:	Jon Mason <jon.mason@broadcom.com>
+S:	Maintained
+F:	board/broadcom/bcmns2/
+F:	include/configs/bcm_northstar2.h
+F:	configs/bcm958712k_defconfig
diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c
index c28b203..a409622 100644
--- a/board/broadcom/bcm_ep/board.c
+++ b/board/broadcom/bcm_ep/board.c
@@ -37,10 +37,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 int board_early_init_f(void)
diff --git a/board/broadcom/bcmns2/Kconfig b/board/broadcom/bcmns2/Kconfig
new file mode 100644
index 0000000..3ac6724
--- /dev/null
+++ b/board/broadcom/bcmns2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BCMNS2
+
+config SYS_BOARD
+	default "bcmns2"
+
+config SYS_VENDOR
+	default "broadcom"
+
+config SYS_SOC
+	default "ns2"
+
+config SYS_CONFIG_NAME
+	default "bcm_northstar2"
+
+endif
diff --git a/board/broadcom/bcmns2/Makefile b/board/broadcom/bcmns2/Makefile
new file mode 100644
index 0000000..f6ddd80
--- /dev/null
+++ b/board/broadcom/bcmns2/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Broadcom Ltd.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= northstar2.o
diff --git a/board/broadcom/bcmns2/northstar2.c b/board/broadcom/bcmns2/northstar2.c
new file mode 100644
index 0000000..10279a5
--- /dev/null
+++ b/board/broadcom/bcmns2/northstar2.c
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2016 Broadcom Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region ns2_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0xff80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = ns2_mem_map;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+				    PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE);
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	psci_system_reset();
+}
diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c
index 5899aa6..0265e9b 100644
--- a/board/cadence/xtfpga/xtfpga.c
+++ b/board/cadence/xtfpga/xtfpga.c
@@ -7,7 +7,7 @@
 
 #include <common.h>
 #include <command.h>
-#include <dm/platdata.h>
+#include <dm.h>
 #include <dm/platform_data/net_ethoc.h>
 #include <linux/ctype.h>
 #include <linux/string.h>
@@ -48,10 +48,12 @@ int checkboard(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
 	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
 }
 
 int board_postclk_init(void)
diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c
index d627b24..ee8f5e8 100644
--- a/board/calao/usb_a9263/usb_a9263.c
+++ b/board/calao/usb_a9263/usb_a9263.c
@@ -18,25 +18,9 @@
 #include <asm/io.h>
 #include <net.h>
 #include <netdev.h>
-#include <dataflash.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_HAS_DATAFLASH
-AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
-
-struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
-	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
-};
-
-/*define the area offsets*/
-dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
-	{0x00000000, 0x00001FFF, FLAG_PROTECT_SET, 0, "Bootstrap"},
-	{0x00002000, 0x00003FFF, FLAG_PROTECT_CLEAR, 0, "Environment"},
-	{0x00004000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"},
-};
-#endif
-
 #ifdef CONFIG_CMD_NAND
 static void usb_a9263_nand_hw_init(void)
 {
@@ -115,9 +99,6 @@ int board_init(void)
 #ifdef CONFIG_CMD_NAND
 	usb_a9263_nand_hw_init();
 #endif
-#ifdef CONFIG_HAS_DATAFLASH
-	at91_spi0_hw_init(1 << 0);
-#endif
 #ifdef CONFIG_MACB
 	usb_a9263_macb_hw_init();
 #endif
diff --git a/board/canmb/Kconfig b/board/canmb/Kconfig
deleted file mode 100644
index b5cf205..0000000
--- a/board/canmb/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CANMB
-
-config SYS_BOARD
-	default "canmb"
-
-config SYS_CONFIG_NAME
-	default "canmb"
-
-endif
diff --git a/board/canmb/MAINTAINERS b/board/canmb/MAINTAINERS
deleted file mode 100644
index 71750ea..0000000
--- a/board/canmb/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CANMB BOARD
-#M:	-
-S:	Maintained
-F:	board/canmb/
-F:	include/configs/canmb.h
-F:	configs/canmb_defconfig
diff --git a/board/canmb/Makefile b/board/canmb/Makefile
deleted file mode 100644
index 4286a91..0000000
--- a/board/canmb/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2005-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= canmb.o
-
diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c
deleted file mode 100644
index 15c934d..0000000
--- a/board/canmb/canmb.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * (C) Copyright 2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-
-#if defined(CONFIG_MPC5200_DDR)
-#include "mt46v16m16-75.h"
-#else
-#include "mt48lc16m32s2-75.h"
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-#endif
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *            is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set tap delay */
-	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	}
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else {
-		dramsize2 = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20)) {
-		dramsize2 = 0;
-	}
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
-			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
-	if (dramsize2 >= 0x13) {
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	} else {
-		dramsize2 = 0;
-	}
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	return dramsize + dramsize2;
-}
-
-int checkboard (void)
-{
-	puts ("Board: CANMB\n");
-	return 0;
-}
-
-int board_early_init_r (void)
-{
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-	*(vu_long *)MPC5XXX_BOOTCS_START =
-	*(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
-	*(vu_long *)MPC5XXX_BOOTCS_STOP =
-	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
-	return 0;
-}
diff --git a/board/canmb/mt48lc16m32s2-75.h b/board/canmb/mt48lc16m32s2-75.h
deleted file mode 100644
index 0133eaa..0000000
--- a/board/canmb/mt48lc16m32s2-75.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	0		/* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c
index 960ca53..02253af 100644
--- a/board/cavium/thunderx/thunderx.c
+++ b/board/cavium/thunderx/thunderx.c
@@ -5,6 +5,7 @@
 **/
 
 #include <common.h>
+#include <dm.h>
 #include <malloc.h>
 #include <errno.h>
 #include <linux/compiler.h>
@@ -13,7 +14,6 @@
 #include <asm/armv8/mmu.h>
 
 #if !CONFIG_IS_ENABLED(OF_CONTROL)
-#include <dm/platdata.h>
 #include <dm/platform_data/serial_pl01x.h>
 
 static const struct pl01x_serial_platdata serial0 = {
diff --git a/board/ccv/xpress/imximage.cfg b/board/ccv/xpress/imximage.cfg
index 92167c9..d98bc36 100644
--- a/board/ccv/xpress/imximage.cfg
+++ b/board/ccv/xpress/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/ccv/xpress/xpress.c b/board/ccv/xpress/xpress.c
index 3193abf..542e534 100644
--- a/board/ccv/xpress/xpress.c
+++ b/board/ccv/xpress/xpress.c
@@ -12,9 +12,9 @@
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/io.h>
 #include <common.h>
 #include <fsl_esdhc.h>
diff --git a/board/cei/cei-tk1-som/cei-tk1-som.c b/board/cei/cei-tk1-som/cei-tk1-som.c
index 9ba7490..7c87bd1 100644
--- a/board/cei/cei-tk1-som/cei-tk1-som.c
+++ b/board/cei/cei-tk1-som/cei-tk1-som.c
@@ -39,6 +39,7 @@ void pinmux_init(void)
 #ifdef CONFIG_PCI_TEGRA
 int tegra_pcie_board_init(void)
 {
+/* TODO: Convert to driver model
 	struct udevice *pmic;
 	int err;
 
@@ -59,6 +60,7 @@ int tegra_pcie_board_init(void)
 		error("failed to set SD4 voltage: %d\n", err);
 		return err;
 	}
+*/
 
 	return 0;
 }
diff --git a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
index aad74ef..ed82b2b 100644
--- a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
+++ b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <spl.h>
+#include <asm/gpio.h>
 
 void board_boot_order(u32 *spl_boot_list)
 {
@@ -13,3 +14,19 @@ void board_boot_order(u32 *spl_boot_list)
 	spl_boot_list[0] = BOOT_DEVICE_MMC2;
 	spl_boot_list[1] = BOOT_DEVICE_MMC1;
 }
+
+#define GPIO7A3_HUB_RST	227
+
+int rk_board_late_init(void)
+{
+	int ret;
+
+	ret = gpio_request(GPIO7A3_HUB_RST, "hub_rst");
+	if (ret)
+		return ret;
+	ret = gpio_direction_output(GPIO7A3_HUB_RST, 1);
+	if (ret)
+		return ret;
+
+	return 0;
+}
diff --git a/board/cirrus/edb93xx/edb93xx.c b/board/cirrus/edb93xx/edb93xx.c
index 8963d3a..02e2896 100644
--- a/board/cirrus/edb93xx/edb93xx.c
+++ b/board/cirrus/edb93xx/edb93xx.c
@@ -18,6 +18,7 @@
 #include <common.h>
 #include <netdev.h>
 #include <asm/io.h>
+#include <asm/mach-types.h>
 #include <asm/arch/ep93xx.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -216,9 +217,11 @@ static unsigned dram_init_banksize_int(int print)
 	return dram_total;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	dram_init_banksize_int(0);
+
+	return 0;
 }
 
 /* called in board_init_f (before relocation) */
@@ -282,101 +285,3 @@ int dram_init(void)
 	gd->ram_size = dram_init_banksize_int(1);
 	return 0;
 }
-
-
-#ifdef CONFIG_EP93XX_SPI
-#include <spi.h>
-
-/*
- * EGIO0-EGIPO7 -> port A
- * EGIO8-EGIP15 -> port B
- */
-
-static void ep93xx_set_epgio(unsigned num)
-{
-	struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
-	if (num < 8)
-		writel(readl(&regs->padr) | (1<<num), &regs->padr);
-	else
-		writel(readl(&regs->pbdr) | (1<<(num-8)), &regs->pbdr);
-}
-
-static void ep93xx_clear_epgio(unsigned num)
-{
-	struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
-	if (num < 8)
-		writel(readl(&regs->padr) & (~(1<<num)), &regs->padr);
-	else
-		writel(readl(&regs->pbdr) & (~(1<<(num-8))), &regs->pbdr);
-}
-
-static void ep93xx_dir_epgio_out(unsigned num)
-{
-	struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
-	if (num < 8)
-		writel(readl(&regs->paddr) | (1<<num), &regs->paddr);
-	else
-		writel(readl(&regs->pbddr) | (1<<(num-8)), &regs->pbddr);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	if (bus == 0 && cs < 16)
-		return 1;
-
-	return 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	ep93xx_clear_epgio(slave->cs);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	ep93xx_set_epgio(slave->cs);
-}
-
-#ifdef CONFIG_MMC_SPI
-#include <mmc.h>
-
-#ifndef CONFIG_MMC_SPI_CS_EPGIO
-# define CONFIG_MMC_SPI_CS_EPGIO	4
-#endif
-
-#ifndef CONFIG_MMC_SPI_SPEED
-# define CONFIG_MMC_SPI_SPEED		25000000
-#endif
-
-#ifndef CONFIG_MMC_SPI_MODE
-# define CONFIG_MMC_SPI_MODE		SPI_MODE_0
-#endif
-
-int board_mmc_init(bd_t *bis)
-{
-	struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
-
-	ep93xx_set_epgio(CONFIG_MMC_SPI_CS_EPGIO);
-	ep93xx_dir_epgio_out(CONFIG_MMC_SPI_CS_EPGIO);
-
-#ifdef CONFIG_MMC_SPI_POWER_EGPIO
-	ep93xx_dir_epgio_out(CONFIG_MMC_SPI_POWER_EGPIO);
-	ep93xx_set_epgio(CONFIG_MMC_SPI_POWER_EGPIO);
-#elif defined(CONFIG_MMC_SPI_NPOWER_EGPIO)
-	ep93xx_dir_epgio_out(CONFIG_MMC_SPI_NPOWER_EGPIO);
-	ep93xx_clear_epgio(CONFIG_MMC_SPI_NPOWER_EGPIO);
-#endif
-	struct mmc *mmc = mmc_spi_init(0, CONFIG_MMC_SPI_CS_EPGIO,
-				CONFIG_MMC_SPI_SPEED, CONFIG_MMC_SPI_MODE);
-
-	if (!mmc) {
-		printf("Failed to create MMC Device\n");
-		return 1;
-	}
-	mmc_init(mmc);
-	return 0;
-}
-
-
-#endif /* CONFIG_MMC_SPI */
-#endif /* CONFIG_EP93XX_SPI */
diff --git a/board/cm-bf527/Kconfig b/board/cm-bf527/Kconfig
deleted file mode 100644
index 8d14179..0000000
--- a/board/cm-bf527/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF527
-
-config SYS_BOARD
-	default "cm-bf527"
-
-config SYS_CONFIG_NAME
-	default "cm-bf527"
-
-endif
diff --git a/board/cm-bf527/MAINTAINERS b/board/cm-bf527/MAINTAINERS
deleted file mode 100644
index fefcfcf..0000000
--- a/board/cm-bf527/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF527 BOARD
-#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S:	Orphan (since 2014-03)
-F:	board/cm-bf527/
-F:	include/configs/cm-bf527.h
-F:	configs/cm-bf527_defconfig
diff --git a/board/cm-bf527/Makefile b/board/cm-bf527/Makefile
deleted file mode 100644
index 1d662c6..0000000
--- a/board/cm-bf527/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= cm-bf527.o gpio_cfi_flash.o
diff --git a/board/cm-bf527/cm-bf527.c b/board/cm-bf527/cm-bf527.c
deleted file mode 100644
index 0c2138b..0000000
--- a/board/cm-bf527/cm-bf527.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/otp.h>
-#include "../cm-bf537e/gpio_cfi_flash.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: Bluetechnix CM-BF527 board\n");
-	printf("       Support: http://www.bluetechnix.at/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
-{
-	/* the MAC is stored in OTP memory page 0xDF */
-	uint32_t ret;
-	uint64_t otp_mac;
-
-	ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac);
-	if (!(ret & OTP_MASTER_ERROR)) {
-		uchar *otp_mac_p = (uchar *)&otp_mac;
-
-		for (ret = 0; ret < 6; ++ret)
-			mac_addr[ret] = otp_mac_p[5 - ret];
-
-		if (is_valid_ethaddr(mac_addr))
-			eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
-
-int misc_init_r(void)
-{
-#ifdef CONFIG_BFIN_MAC
-	uchar enetaddr[6];
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-		board_init_enetaddr(enetaddr);
-#endif
-
-	gpio_cfi_flash_init();
-
-	return 0;
-}
diff --git a/board/cm-bf527/gpio_cfi_flash.c b/board/cm-bf527/gpio_cfi_flash.c
deleted file mode 100644
index 6e62fff..0000000
--- a/board/cm-bf527/gpio_cfi_flash.c
+++ /dev/null
@@ -1,3 +0,0 @@
-#define GPIO_PIN_1 GPIO_PH9
-#define GPIO_PIN_2 GPIO_PG11
-#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/cm-bf533/Kconfig b/board/cm-bf533/Kconfig
deleted file mode 100644
index cedd752..0000000
--- a/board/cm-bf533/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF533
-
-config SYS_BOARD
-	default "cm-bf533"
-
-config SYS_CONFIG_NAME
-	default "cm-bf533"
-
-endif
diff --git a/board/cm-bf533/MAINTAINERS b/board/cm-bf533/MAINTAINERS
deleted file mode 100644
index 0bf51fb..0000000
--- a/board/cm-bf533/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF533 BOARD
-#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S:	Orphan (since 2014-03)
-F:	board/cm-bf533/
-F:	include/configs/cm-bf533.h
-F:	configs/cm-bf533_defconfig
diff --git a/board/cm-bf533/Makefile b/board/cm-bf533/Makefile
deleted file mode 100644
index 41e100d..0000000
--- a/board/cm-bf533/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= cm-bf533.o
diff --git a/board/cm-bf533/cm-bf533.c b/board/cm-bf533/cm-bf533.c
deleted file mode 100644
index 02ef076..0000000
--- a/board/cm-bf533/cm-bf533.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: Bluetechnix CM-BF533 board\n");
-	printf("       Support: http://www.bluetechnix.at/\n");
-	return 0;
-}
-
-#ifdef CONFIG_SMC91111
-int board_eth_init(bd_t *bis)
-{
-	return smc91111_initialize(0, CONFIG_SMC91111_BASE);
-}
-#endif
diff --git a/board/cm-bf533/config.mk b/board/cm-bf533/config.mk
deleted file mode 100644
index 7f9138b..0000000
--- a/board/cm-bf533/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf537e/Kconfig b/board/cm-bf537e/Kconfig
deleted file mode 100644
index af2e548..0000000
--- a/board/cm-bf537e/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF537E
-
-config SYS_BOARD
-	default "cm-bf537e"
-
-config SYS_CONFIG_NAME
-	default "cm-bf537e"
-
-endif
diff --git a/board/cm-bf537e/MAINTAINERS b/board/cm-bf537e/MAINTAINERS
deleted file mode 100644
index 63d2428..0000000
--- a/board/cm-bf537e/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF537E BOARD
-#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S:	Orphan (since 2014-03)
-F:	board/cm-bf537e/
-F:	include/configs/cm-bf537e.h
-F:	configs/cm-bf537e_defconfig
diff --git a/board/cm-bf537e/Makefile b/board/cm-bf537e/Makefile
deleted file mode 100644
index 317098c..0000000
--- a/board/cm-bf537e/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= cm-bf537e.o gpio_cfi_flash.o
diff --git a/board/cm-bf537e/cm-bf537e.c b/board/cm-bf537e/cm-bf537e.c
deleted file mode 100644
index 7e4cfc2..0000000
--- a/board/cm-bf537e/cm-bf537e.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include "gpio_cfi_flash.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: Bluetechnix CM-BF537E board\n");
-	printf("       Support: http://www.bluetechnix.at/\n");
-	return 0;
-}
-
-#ifndef CONFIG_BFIN_MAC
-# define bfin_EMAC_initialize(x) 1
-#endif
-#ifndef CONFIG_SMC911X
-# define smc911x_initialize(n, x) 1
-#endif
-int board_eth_init(bd_t *bis)
-{
-	/* return ok if at least 1 eth device works */
-	return bfin_EMAC_initialize(bis) &
-	       smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-
-int misc_init_r(void)
-{
-	gpio_cfi_flash_init();
-
-	return 0;
-}
diff --git a/board/cm-bf537e/config.mk b/board/cm-bf537e/config.mk
deleted file mode 100644
index 7f9138b..0000000
--- a/board/cm-bf537e/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf537e/gpio_cfi_flash.c b/board/cm-bf537e/gpio_cfi_flash.c
deleted file mode 100644
index 1075cc4..0000000
--- a/board/cm-bf537e/gpio_cfi_flash.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
- *
- * Copyright (c) 2009-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include "gpio_cfi_flash.h"
-
-/* Allow this driver to be shared among boards */
-#ifndef GPIO_PIN_1
-#define GPIO_PIN_1  GPIO_PF4
-#endif
-#define GPIO_MASK_1 (1 << 21)
-#ifndef GPIO_PIN_2
-#define GPIO_MASK_2 (0)
-#else
-#define GPIO_MASK_2 (1 << 22)
-#endif
-#ifndef GPIO_PIN_3
-#define GPIO_MASK_3 (0)
-#else
-#define GPIO_MASK_3 (1 << 23)
-#endif
-#define GPIO_MASK   (GPIO_MASK_1 | GPIO_MASK_2 | GPIO_MASK_3)
-
-void *gpio_cfi_flash_swizzle(void *vaddr)
-{
-	unsigned long addr = (unsigned long)vaddr;
-
-	gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
-
-#ifdef GPIO_PIN_2
-	gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
-#endif
-
-#ifdef GPIO_PIN_3
-	gpio_set_value(GPIO_PIN_3, addr & GPIO_MASK_3);
-#endif
-
-	SSYNC();
-	udelay(1);
-
-	return (void *)(addr & ~GPIO_MASK);
-}
-
-#define __raw_writeq(value, addr) *(volatile u64 *)addr = value
-#define __raw_readq(addr) *(volatile u64 *)addr
-
-#define MAKE_FLASH(size, sfx) \
-void flash_write##size(u##size value, void *addr) \
-{ \
-	__raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \
-} \
-u##size flash_read##size(void *addr) \
-{ \
-	return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \
-}
-MAKE_FLASH(8, b)  /* flash_write8()  flash_read8() */
-MAKE_FLASH(16, w) /* flash_write16() flash_read16() */
-MAKE_FLASH(32, l) /* flash_write32() flash_read32() */
-MAKE_FLASH(64, q) /* flash_write64() flash_read64() */
-
-void gpio_cfi_flash_init(void)
-{
-	gpio_request(GPIO_PIN_1, "gpio_cfi_flash");
-	gpio_direction_output(GPIO_PIN_1, 0);
-#ifdef GPIO_PIN_2
-	gpio_request(GPIO_PIN_2, "gpio_cfi_flash");
-	gpio_direction_output(GPIO_PIN_2, 0);
-#endif
-#ifdef GPIO_PIN_3
-	gpio_request(GPIO_PIN_3, "gpio_cfi_flash");
-	gpio_direction_output(GPIO_PIN_3, 0);
-#endif
-}
diff --git a/board/cm-bf537e/gpio_cfi_flash.h b/board/cm-bf537e/gpio_cfi_flash.h
deleted file mode 100644
index 5211e97..0000000
--- a/board/cm-bf537e/gpio_cfi_flash.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
- *
- * Copyright (c) 2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-void *gpio_cfi_flash_swizzle(void *vaddr);
-void gpio_cfi_flash_init(void);
diff --git a/board/cm-bf537u/Kconfig b/board/cm-bf537u/Kconfig
deleted file mode 100644
index baf9e8c..0000000
--- a/board/cm-bf537u/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF537U
-
-config SYS_BOARD
-	default "cm-bf537u"
-
-config SYS_CONFIG_NAME
-	default "cm-bf537u"
-
-endif
diff --git a/board/cm-bf537u/MAINTAINERS b/board/cm-bf537u/MAINTAINERS
deleted file mode 100644
index a89cfca..0000000
--- a/board/cm-bf537u/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF537U BOARD
-#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S:	Orphan (since 2014-03)
-F:	board/cm-bf537u/
-F:	include/configs/cm-bf537u.h
-F:	configs/cm-bf537u_defconfig
diff --git a/board/cm-bf537u/Makefile b/board/cm-bf537u/Makefile
deleted file mode 100644
index 835d5b7..0000000
--- a/board/cm-bf537u/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= cm-bf537u.o gpio_cfi_flash.o
diff --git a/board/cm-bf537u/cm-bf537u.c b/board/cm-bf537u/cm-bf537u.c
deleted file mode 100644
index aad72a9..0000000
--- a/board/cm-bf537u/cm-bf537u.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include "../cm-bf537e/gpio_cfi_flash.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: Bluetechnix CM-BF537U board\n");
-	printf("       Support: http://www.bluetechnix.at/\n");
-	return 0;
-}
-
-#ifndef CONFIG_BFIN_MAC
-# define bfin_EMAC_initialize(x) 1
-#endif
-#ifndef CONFIG_SMC911X
-# define smc911x_initialize(n, x) 1
-#endif
-int board_eth_init(bd_t *bis)
-{
-	/* return ok if at least 1 eth device works */
-	return bfin_EMAC_initialize(bis) &
-	       smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-
-int misc_init_r(void)
-{
-	gpio_cfi_flash_init();
-
-	return 0;
-}
diff --git a/board/cm-bf537u/config.mk b/board/cm-bf537u/config.mk
deleted file mode 100644
index 7f9138b..0000000
--- a/board/cm-bf537u/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/cm-bf537u/gpio_cfi_flash.c b/board/cm-bf537u/gpio_cfi_flash.c
deleted file mode 100644
index ef5ea8b..0000000
--- a/board/cm-bf537u/gpio_cfi_flash.c
+++ /dev/null
@@ -1,2 +0,0 @@
-#define GPIO_PIN_1 GPIO_PH0
-#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/cm-bf548/Kconfig b/board/cm-bf548/Kconfig
deleted file mode 100644
index b96cb5f..0000000
--- a/board/cm-bf548/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF548
-
-config SYS_BOARD
-	default "cm-bf548"
-
-config SYS_CONFIG_NAME
-	default "cm-bf548"
-
-endif
diff --git a/board/cm-bf548/MAINTAINERS b/board/cm-bf548/MAINTAINERS
deleted file mode 100644
index b7f5779..0000000
--- a/board/cm-bf548/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF548 BOARD
-#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S:	Orphan (since 2014-03)
-F:	board/cm-bf548/
-F:	include/configs/cm-bf548.h
-F:	configs/cm-bf548_defconfig
diff --git a/board/cm-bf548/Makefile b/board/cm-bf548/Makefile
deleted file mode 100644
index 1e11b8c..0000000
--- a/board/cm-bf548/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= cm-bf548.o
-obj-$(CONFIG_VIDEO)      += video.o
diff --git a/board/cm-bf548/cm-bf548.c b/board/cm-bf548/cm-bf548.c
deleted file mode 100644
index d9d018b..0000000
--- a/board/cm-bf548/cm-bf548.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/portmux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: Bluetechnix CM-BF548 board\n");
-	printf("       Support: http://www.bluetechnix.at/\n");
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	/* Set async addr lines as peripheral */
-	const unsigned short pins[] = {
-		P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
-		P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20,
-		P_A21, P_A22, P_A23, P_A24, 0
-	};
-	return peripheral_request_list(pins, "async");
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC911X
-	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
-	return rc;
-}
diff --git a/board/cm-bf548/config.mk b/board/cm-bf548/config.mk
deleted file mode 100644
index beb9834..0000000
--- a/board/cm-bf548/config.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA       := --dma 6
-LDR_FLAGS-BFIN_BOOT_FIFO       := --dma 1
-LDR_FLAGS-BFIN_BOOT_SPI_MASTER := --dma 1
-LDR_FLAGS-BFIN_BOOT_UART       := --dma 1
diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c
deleted file mode 100644
index b8cc873..0000000
--- a/board/cm-bf548/video.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * video.c - run splash screen on lcd
- *
- * Copyright (c) 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <stdarg.h>
-#include <common.h>
-#include <config.h>
-#include <malloc.h>
-#include <asm/blackfin.h>
-#include <asm/clock.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-#include <asm/mach-common/bits/dma.h>
-#include <i2c.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-
-#include <lzma/LzmaTypes.h>
-#include <lzma/LzmaDec.h>
-#include <lzma/LzmaTools.h>
-
-#define DMA_SIZE16	2
-
-#include <asm/mach-common/bits/eppi.h>
-
-#include EASYLOGO_HEADER
-
-#define LCD_X_RES		480	/*Horizontal Resolution */
-#define LCD_Y_RES		272	/* Vertical Resolution */
-
-#define LCD_BPP			24	/* Bit Per Pixel */
-#define LCD_PIXEL_SIZE		(LCD_BPP / 8)
-#define	DMA_BUS_SIZE		32
-#define ACTIVE_VIDEO_MEM_OFFSET 0
-
-/* 	-- Horizontal synchronizing --
- *
- * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
- * (LCY-W-06602A Page 9 of 22)
- *
- * Clock Frequency 	1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
- *
- * Period 		TH - 525 - Clock
- * Pulse width 		THp - 41 - Clock
- * Horizontal period 	THd - 480 - Clock
- * Back porch 		THb - 2 - Clock
- * Front porch 		THf - 2 - Clock
- *
- * -- Vertical synchronizing --
- * Period 		TV - 286 - Line
- * Pulse width 		TVp - 10 - Line
- * Vertical period 	TVd - 272 - Line
- * Back porch 		TVb - 2 - Line
- * Front porch 		TVf - 2 - Line
- */
-
-#define	LCD_CLK         	(8*1000*1000)	/* 8MHz */
-
-/* # active data to transfer after Horizontal Delay clock */
-#define EPPI_HCOUNT		LCD_X_RES
-
-/* # active lines to transfer after Vertical Delay clock */
-#define EPPI_VCOUNT		LCD_Y_RES
-
-/* Samples per Line = 480 (active data) + 45 (padding) */
-#define EPPI_LINE		525
-
-/* Lines per Frame = 272 (active data) + 14 (padding) */
-#define EPPI_FRAME		286
-
-/* FS1 (Hsync) Width (Typical)*/
-#define EPPI_FS1W_HBL		41
-
-/* FS1 (Hsync) Period (Typical) */
-#define EPPI_FS1P_AVPL		EPPI_LINE
-
-/* Horizontal Delay clock after assertion of Hsync (Typical) */
-#define EPPI_HDELAY		43
-
-/* FS2 (Vsync) Width    = FS1 (Hsync) Period * 10 */
-#define EPPI_FS2W_LVB		(EPPI_LINE * 10)
-
- /* FS2 (Vsync) Period   = FS1 (Hsync) Period * Lines per Frame */
-#define EPPI_FS2P_LAVF		(EPPI_LINE * EPPI_FRAME)
-
-/* Vertical Delay after assertion of Vsync (2 Lines) */
-#define EPPI_VDELAY		12
-
-#define EPPI_CLIP		0xFF00FF00
-
-/* EPPI Control register configuration value for RGB out
- * - EPPI as Output
- * GP 2 frame sync mode,
- * Internal Clock generation disabled, Internal FS generation enabled,
- * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
- * FS1 & FS2 are active high,
- * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
- * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
- * Swapping Enabled,
- * One (DMA) Channel Mode,
- * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
- * Regular watermark - when FIFO is 100% full,
- * Urgent watermark - when FIFO is 75% full
- */
-
-#define EPPI_CONTROL		(0x20136E2E)
-
-static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
-{
-	u32 sclk = get_sclk();
-
-	/* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
-
-	return (((sclk / target_ppi_clk) / 2) - 1);
-}
-
-void Init_PPI(void)
-{
-	u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
-
-	bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
-	bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
-	bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
-	bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
-	bfin_write_EPPI0_CLIP(EPPI_CLIP);
-
-	bfin_write_EPPI0_FRAME(EPPI_FRAME);
-	bfin_write_EPPI0_LINE(EPPI_LINE);
-
-	bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
-	bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
-	bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
-	bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
-
-	bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
-
-/*
- * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
- * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
- */
-#if defined(CONFIG_VIDEO_RGB666)
-	bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
-				 RGB_FMT_EN);
-#else
-	bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
-				 ~RGB_FMT_EN);
-#endif
-
-}
-
-#define               DEB2_URGENT  0x2000	/* DEB2 Urgent */
-
-void Init_DMA(void *dst)
-{
-#if defined(CONFIG_DEB_DMA_URGENT)
-	bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT);
-#endif
-
-	bfin_write_DMA12_START_ADDR(dst);
-
-	/* X count */
-	bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
-	bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8);
-
-	/* Y count */
-	bfin_write_DMA12_Y_COUNT(LCD_Y_RES);
-	bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8);
-
-	/* DMA Config */
-	bfin_write_DMA12_CONFIG(
-	    WDSIZE_32 |	/* 32 bit DMA */
-	    DMA2D |		/* 2D DMA */
-	    FLOW_AUTO		/* autobuffer mode */
-	);
-}
-
-void Init_Ports(void)
-{
-	const unsigned short pins[] = {
-		P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
-		P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9,
-		P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
-		P_PPI0_D15, P_PPI0_D16, P_PPI0_D17,
-#if !defined(CONFIG_VIDEO_RGB666)
-		P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22,
-		P_PPI0_D23,
-#endif
-		P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0,
-	};
-	peripheral_request_list(pins, "lcd");
-
-	gpio_request(GPIO_PE3, "lcd-disp");
-	gpio_direction_output(GPIO_PE3, 1);
-}
-
-void EnableDMA(void)
-{
-	bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN);
-}
-
-void DisableDMA(void)
-{
-	bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN);
-}
-
-/* enable and disable PPI functions */
-void EnablePPI(void)
-{
-	bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
-}
-
-void DisablePPI(void)
-{
-	bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
-}
-
-int video_init(void *dst)
-{
-	Init_Ports();
-	Init_DMA(dst);
-	EnableDMA();
-	Init_PPI();
-	EnablePPI();
-
-	return 0;
-}
-
-void video_stop(void)
-{
-	DisablePPI();
-	DisableDMA();
-}
-
-static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
-{
-	if (dcache_status())
-		blackfin_dcache_flush_range(logo->data,
-					    logo->data + logo->size);
-
-	bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
-
-	/* Setup destination start address */
-	bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
-				      + (y * LCD_X_RES * LCD_PIXEL_SIZE));
-	/* Setup destination xcount */
-	bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
-	/* Setup destination xmodify */
-	bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
-
-	/* Setup destination ycount */
-	bfin_write_MDMA_D0_Y_COUNT(logo->height);
-	/* Setup destination ymodify */
-	bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE +
-				    DMA_SIZE16);
-
-	/* Setup Source start address */
-	bfin_write_MDMA_S0_START_ADDR(logo->data);
-	/* Setup Source xcount */
-	bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
-	/* Setup Source xmodify */
-	bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
-
-	/* Setup Source ycount */
-	bfin_write_MDMA_S0_Y_COUNT(logo->height);
-	/* Setup Source ymodify */
-	bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
-
-	/* Enable source DMA */
-	bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
-	SSYNC();
-	bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
-
-	while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN) ;
-
-	bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE
-				      | DMA_ERR);
-	bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE
-				      | DMA_ERR);
-
-}
-
-int drv_video_init(void)
-{
-	int error, devices = 1;
-	struct stdio_dev videodev;
-
-	u8 *dst;
-	u32 fbmem_size =
-	    LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
-
-	dst = malloc(fbmem_size);
-
-	if (dst == NULL) {
-		printf("Failed to alloc FB memory\n");
-		return -1;
-	}
-
-#ifdef EASYLOGO_ENABLE_GZIP
-	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
-	unsigned long src_len = EASYLOGO_ENABLE_GZIP;
-	error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len);
-	bfin_logo.data = data;
-#elif defined(EASYLOGO_ENABLE_LZMA)
-	unsigned char *data = EASYLOGO_DECOMP_BUFFER;
-	SizeT lzma_len = bfin_logo.size;
-	error = lzmaBuffToBuffDecompress(data, &lzma_len,
-		bfin_logo.data, EASYLOGO_ENABLE_LZMA);
-	bfin_logo.data = data;
-#else
-	error = 0;
-#endif
-
-	if (error) {
-		puts("Failed to decompress logo\n");
-		free(dst);
-		return -1;
-	}
-
-	memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0],
-	       fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
-
-	dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
-		    (LCD_X_RES - bfin_logo.width) / 2,
-		    (LCD_Y_RES - bfin_logo.height) / 2);
-
-	video_init(dst);	/* Video initialization */
-
-	memset(&videodev, 0, sizeof(videodev));
-
-	strcpy(videodev.name, "video");
-
-	error = stdio_register(&videodev);
-
-	return (error == 0) ? devices : error;
-}
diff --git a/board/cm-bf561/Kconfig b/board/cm-bf561/Kconfig
deleted file mode 100644
index 8b302a5..0000000
--- a/board/cm-bf561/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM_BF561
-
-config SYS_BOARD
-	default "cm-bf561"
-
-config SYS_CONFIG_NAME
-	default "cm-bf561"
-
-endif
diff --git a/board/cm-bf561/MAINTAINERS b/board/cm-bf561/MAINTAINERS
deleted file mode 100644
index 9c86c8d..0000000
--- a/board/cm-bf561/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM-BF561 BOARD
-#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S:	Orphan (since 2014-03)
-F:	board/cm-bf561/
-F:	include/configs/cm-bf561.h
-F:	configs/cm-bf561_defconfig
diff --git a/board/cm-bf561/Makefile b/board/cm-bf561/Makefile
deleted file mode 100644
index e0f0c34..0000000
--- a/board/cm-bf561/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= cm-bf561.o
diff --git a/board/cm-bf561/cm-bf561.c b/board/cm-bf561/cm-bf561.c
deleted file mode 100644
index 99b7eb2..0000000
--- a/board/cm-bf561/cm-bf561.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: Bluetechnix CM-BF561 core module\n");
-	printf("       Support: http://www.bluetechnix.at/\n");
-	return 0;
-}
-
-#ifdef CONFIG_SMC911X
-int board_eth_init(bd_t *bis)
-{
-	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-#endif
diff --git a/board/cm-bf561/config.mk b/board/cm-bf561/config.mk
deleted file mode 100644
index 854d7db..0000000
--- a/board/cm-bf561/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/cm5200/Kconfig b/board/cm5200/Kconfig
deleted file mode 100644
index ccea5c9..0000000
--- a/board/cm5200/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CM5200
-
-config SYS_BOARD
-	default "cm5200"
-
-config SYS_CONFIG_NAME
-	default "cm5200"
-
-endif
diff --git a/board/cm5200/MAINTAINERS b/board/cm5200/MAINTAINERS
deleted file mode 100644
index 1e1df3f..0000000
--- a/board/cm5200/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM5200 BOARD
-#M:	-
-S:	Maintained
-F:	board/cm5200/
-F:	include/configs/cm5200.h
-F:	configs/cm5200_defconfig
diff --git a/board/cm5200/Makefile b/board/cm5200/Makefile
deleted file mode 100644
index 76f8b9f..0000000
--- a/board/cm5200/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= cm5200.o cmd_cm5200.o fwupdate.o
diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
deleted file mode 100644
index fce998d..0000000
--- a/board/cm5200/cm5200.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- * (C) Copyright 2003-2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2004-2005
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * Adapted to U-Boot 1.2 by:
- *   Bartlomiej Sieka <tur@semihalf.com>:
- *      - HW ID readout from EEPROM
- *      - module detection
- *   Grzegorz Bernacki <gjb@semihalf.com>:
- *      - run-time SDRAM controller configuration
- *      - LIBFDT support
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <i2c.h>
-#include <linux/ctype.h>
-
-#ifdef CONFIG_OF_LIBFDT
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif /* CONFIG_OF_LIBFDT */
-
-
-#include "cm5200.h"
-#include "fwupdate.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static hw_id_t hw_id;
-
-
-#ifndef CONFIG_SYS_RAMBOOT
-/*
- * Helper function to initialize SDRAM controller.
- */
-static void sdram_start(int hi_addr, mem_conf_t *mem_conf)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000000 |
-						hi_addr_bit;
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000002 |
-						hi_addr_bit;
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 |
-						hi_addr_bit;
-
-	/* auto refresh, second time */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 |
-						hi_addr_bit;
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = mem_conf->mode;
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | hi_addr_bit;
-}
-#endif /* CONFIG_SYS_RAMBOOT */
-
-
-/*
- * Retrieve memory configuration for a given module. board_type is the index
- * in hw_id_list[] corresponding to the module we are executing on; we return
- * SDRAM controller settings approprate for this module.
- */
-static mem_conf_t* get_mem_config(int board_type)
-{
-	switch(board_type){
-		case CM1_QA:
-			return memory_config[0];
-		case CM11_QA:
-		case CMU1_QA:
-			return memory_config[1];
-		default:
-			printf("ERROR: Unknown module, using a default SDRAM "
-				"configuration - things may not work!!!.\n");
-			return memory_config[0];
-	}
-}
-
-
-/*
- * Initalize SDRAM - configure SDRAM controller, detect memory size.
- */
-phys_size_t initdram(int board_type)
-{
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-	mem_conf_t *mem_conf;
-
-	mem_conf = get_mem_config(board_type);
-
-	/* configure SDRAM start/end for detection */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = mem_conf->config1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = mem_conf->config2;
-
-	sdram_start(0, mem_conf);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1, mem_conf);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0, mem_conf);
-		dramsize = test1;
-	} else
-		dramsize = test2;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
-			__builtin_ffs(dramsize >> 20) - 1;
-	} else
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-#else /* CONFIG_SYS_RAMBOOT */
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-#endif /* !CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller.  Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of
-	 * the MPC5200B User's Manual.
-	 */
-	*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
-	__asm__ volatile ("sync");
-
-	return dramsize;
-}
-
-
-/*
- * Read module hardware identification data from the I2C EEPROM.
- */
-static void read_hw_id(hw_id_t hw_id)
-{
-	int i;
-	for (i = 0; i < HW_ID_ELEM_COUNT; ++i)
-		if (i2c_read(CONFIG_SYS_I2C_EEPROM,
-				hw_id_format[i].offset,
-				2,
-				(uchar *)&hw_id[i][0],
-				hw_id_format[i].length) != 0)
-			printf("ERROR: can't read HW ID from EEPROM\n");
-}
-
-
-/*
- * Identify module we are running on, set gd->board_type to the index in
- * hw_id_list[] corresponding to the module identifed, or to
- * CM5200_UNKNOWN_MODULE if we can't identify the module.
- */
-static void identify_module(hw_id_t hw_id)
-{
-	int i, j, element;
-	char match;
-	gd->board_type = CM5200_UNKNOWN_MODULE;
-	for (i = 0; i < sizeof (hw_id_list) / sizeof (char **); ++i) {
-		match = 1;
-		for (j = 0; j < sizeof (hw_id_identify) / sizeof (int); ++j) {
-			element = hw_id_identify[j];
-			if (strncmp(hw_id_list[i][element],
-					&hw_id[element][0],
-					hw_id_format[element].length) != 0) {
-				match = 0;
-				break;
-			}
-		}
-		if (match) {
-			gd->board_type = i;
-			break;
-		}
-	}
-}
-
-
-/*
- * Compose string with module name.
- * buf is assumed to have enough space, and be null-terminated.
- */
-static void compose_module_name(hw_id_t hw_id, char *buf)
-{
-	char tmp[MODULE_NAME_MAXLEN];
-	strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length);
-	strncat(buf, ".", 1);
-	strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length);
-	strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length);
-	strncat(buf, " (", 2);
-	strncat(buf, &hw_id[IDENTIFICATION_NUMBER][0],
-		hw_id_format[IDENTIFICATION_NUMBER].length);
-	sprintf(tmp, " / %u.%u)",
-		hw_id[MAJOR_SW_VERSION][0],
-		hw_id[MINOR_SW_VERSION][0]);
-	strcat(buf, tmp);
-}
-
-
-/*
- * Compose string with hostname.
- * buf is assumed to have enough space, and be null-terminated.
- */
-static void compose_hostname(hw_id_t hw_id, char *buf)
-{
-	char *p;
-	strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length);
-	strncat(buf, "_", 1);
-	strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length);
-	strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length);
-	for (p = buf; *p; ++p)
-		*p = tolower(*p);
-
-}
-
-
-#ifdef CONFIG_OF_BOARD_SETUP
-/*
- * Update 'model' and 'memory' properties in the blob according to the module
- * that we are running on.
- */
-static void ft_blob_update(void *blob, bd_t *bd)
-{
-	int len, ret, nodeoffset = 0;
-	char module_name[MODULE_NAME_MAXLEN] = {0};
-
-	compose_module_name(hw_id, module_name);
-	len = strlen(module_name) + 1;
-
-	ret = fdt_setprop(blob, nodeoffset, "model", module_name, len);
-	if (ret < 0)
-	printf("ft_blob_update(): cannot set /model property err:%s\n",
-		fdt_strerror(ret));
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-
-/*
- * Read HW ID from I2C EEPROM and detect the modue we are running on. Note
- * that we need to use local variable for readout, because global data is not
- * writable yet (and we'll have to redo the readout later on).
- */
-int checkboard(void)
-{
-	hw_id_t hw_id_tmp;
-	char module_name_tmp[MODULE_NAME_MAXLEN] = "";
-
-	/*
-	 * We need I2C to access HW ID data from EEPROM, so we call i2c_init()
-	 * here despite the fact that it will be called again later on. We
-	 * also use a little trick to silence I2C-related output.
-	 */
-	gd->flags |= GD_FLG_SILENT;
-	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-	gd->flags &= ~GD_FLG_SILENT;
-
-	read_hw_id(hw_id_tmp);
-	identify_module(hw_id_tmp);	/* this sets gd->board_type */
-	compose_module_name(hw_id_tmp, module_name_tmp);
-
-	if (gd->board_type != CM5200_UNKNOWN_MODULE)
-		printf("Board: %s\n", module_name_tmp);
-	else
-		printf("Board: unrecognized cm5200 module (%s)\n",
-			module_name_tmp);
-
-	return 0;
-}
-
-
-int board_early_init_r(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write access for detection
-	 * process. Note that CS_BOOT cannot be cleared when executing in
-	 * flash.
-	 */
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-
-	/* Now that we can write to global data, read HW ID again. */
-	read_hw_id(hw_id);
-	return 0;
-}
-
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
-	uchar buf[6];
-	char str[18];
-	char hostname[MODULE_NAME_MAXLEN];
-
-	/* Read ethaddr from EEPROM */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) {
-		sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X",
-			buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
-		/* Check if MAC addr is owned by Schindler */
-		if (strstr(str, "00:06:C3") != str)
-			printf(LOG_PREFIX "Warning - Illegal MAC address (%s)"
-				" in EEPROM.\n", str);
-		else {
-			printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n",
-				str);
-			setenv("ethaddr", str);
-		}
-	} else {
-		printf(LOG_PREFIX "Warning - Unable to read MAC from I2C"
-			" device at address %02X:%04X\n", CONFIG_SYS_I2C_EEPROM,
-			CONFIG_MAC_OFFSET);
-	}
-#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT) */
-	if (!getenv("ethaddr"))
-		printf(LOG_PREFIX "MAC address not set, networking is not "
-					"operational\n");
-
-	/* set the hostname appropriate to the module we're running on */
-	hostname[0] = 0x00;
-	compose_hostname(hw_id, hostname);
-	setenv("hostname", hostname);
-
-	return 0;
-}
-#endif /* CONFIG_MISC_INIT_R */
-
-
-#ifdef CONFIG_LAST_STAGE_INIT
-int last_stage_init(void)
-{
-#ifdef CONFIG_USB_STORAGE
-	cm5200_fwupdate();
-#endif /* CONFIG_USB_STORAGE */
-	return 0;
-}
-#endif /* CONFIG_LAST_STAGE_INIT */
-
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-	ft_blob_update(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/cm5200/cm5200.h b/board/cm5200/cm5200.h
deleted file mode 100644
index c2573f3..0000000
--- a/board/cm5200/cm5200.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * (C) Copyright 2007 DENX Software Engineering
- *
- * Author: Bartlomiej Sieka <tur@semihalf.com>
- * Author: Grzegorz Bernacki <gjb@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _CM5200_H
-#define _CM5200_H
-
-
-/*
- * Definitions and declarations for the modules of the cm5200 platform. Mostly
- * related to reading the hardware identification data (HW ID) from the I2C
- * EEPROM, detection of the particular module we are executing on, and
- * appropriate SDRAM controller initialization.
- */
-
-
-#define CM5200_UNKNOWN_MODULE	0xffffffff
-
-enum {
-	DEVICE_NAME,		/* 0 */
-	GENERATION,		/* 1 */
-	PCB_NAME,		/* 2 */
-	FORM,			/* 3 */
-	VERSION,		/* 4 */
-	IDENTIFICATION_NUMBER,	/* 5 */
-	MAJOR_SW_VERSION,	/* 6 */
-	MINOR_SW_VERSION,	/* 7 */
-	/* add new alements above this line */
-	HW_ID_ELEM_COUNT	/* count */
-};
-
-/*
- * Sect. 4.1 "CM1.Q/CMU1.Q Supervisory Microcontroller Interface Definition"
- */
-
-#define DEVICE_NAME_OFFSET		0x02
-#define GENERATION_OFFSET		0x0b
-#define PCB_NAME_OFFSET			0x0c
-#define FORM_OFFSET			0x15
-#define VERSION_OFFSET			0x16
-#define IDENTIFICATION_NUMBER_OFFSET	0x19
-#define MAJOR_SW_VERSION_OFFSET		0x0480
-#define MINOR_SW_VERSION_OFFSET		0x0481
-
-
-#define DEVICE_NAME_LEN			0x09
-#define GENERATION_LEN			0x01
-#define PCB_NAME_LEN			0x09
-#define FORM_LEN			0x01
-#define VERSION_LEN			0x03
-#define IDENTIFICATION_NUMBER_LEN	0x09
-#define MAJOR_SW_VERSION_LEN		0x01
-#define MINOR_SW_VERSION_LEN		0x01
-
-#define HW_ID_ELEM_MAXLEN		0x09	/* MAX(XXX_LEN) */
-
-/* entire HW ID in EEPROM is 64 bytes, so longer module name is unlikely */
-#define MODULE_NAME_MAXLEN		64
-
-
-/* storage for HW ID read from EEPROM */
-typedef char hw_id_t[HW_ID_ELEM_COUNT][HW_ID_ELEM_MAXLEN];
-
-
-/* HW ID layout in EEPROM */
-static struct {
-	unsigned int offset;
-	unsigned int length;
-} hw_id_format[HW_ID_ELEM_COUNT] = {
-	{DEVICE_NAME_OFFSET,		DEVICE_NAME_LEN},
-	{GENERATION_OFFSET,		GENERATION_LEN},
-	{PCB_NAME_OFFSET,		PCB_NAME_LEN},
-	{FORM_OFFSET,			FORM_LEN},
-	{VERSION_OFFSET,		VERSION_LEN},
-	{IDENTIFICATION_NUMBER_OFFSET,	IDENTIFICATION_NUMBER_LEN},
-	{MAJOR_SW_VERSION_OFFSET,	MAJOR_SW_VERSION_LEN},
-	{MINOR_SW_VERSION_OFFSET,	MINOR_SW_VERSION_LEN},
-};
-
-
-/* HW ID data found in EEPROM on supported modules */
-static char *cm1_qa_hw_id[HW_ID_ELEM_COUNT] = {
-	"CM",		/* DEVICE_NAME */
-	"1",		/* GENERATION */
-	"CM1",		/* PCB_NAME */
-	"Q",		/* FORM */
-	"A",		/* VERSION */
-	"591881",	/* IDENTIFICATION_NUMBER */
-	"",		/* MAJOR_SW_VERSION */
-	"",		/* MINOR_SW_VERSION */
-};
-
-static char *cm11_qa_hw_id[HW_ID_ELEM_COUNT] = {
-	"CM",		/* DEVICE_NAME */
-	"1",		/* GENERATION */
-	"CM11",		/* PCB_NAME */
-	"Q",		/* FORM */
-	"A",		/* VERSION */
-	"594200",	/* IDENTIFICATION_NUMBER */
-	"",		/* MAJOR_SW_VERSION */
-	"",		/* MINOR_SW_VERSION */
-};
-
-static char *cmu1_qa_hw_id[HW_ID_ELEM_COUNT] = {
-	"CMU",		/* DEVICE_NAME */
-	"1",		/* GENERATION */
-	"CMU1",		/* PCB_NAME */
-	"Q",		/* FORM */
-	"A",		/* VERSION */
-	"594128",	/* IDENTIFICATION_NUMBER */
-	"",		/* MAJOR_SW_VERSION */
-	"",		/* MINOR_SW_VERSION */
-};
-
-
-/* list of known modules */
-static char **hw_id_list[] = {
-	cm1_qa_hw_id,
-	cm11_qa_hw_id,
-	cmu1_qa_hw_id,
-};
-
-/* indices to the above list - keep in sync */
-enum {
-	CM1_QA,
-	CM11_QA,
-	CMU1_QA,
-};
-
-
-/* identify modules based on these hw id elements */
-static int hw_id_identify[] = {
-	PCB_NAME,
-	FORM,
-	VERSION,
-};
-
-
-/* Registers' settings for SDRAM controller intialization */
-typedef struct {
-	ulong mode;
-	ulong control;
-	ulong config1;
-	ulong config2;
-} mem_conf_t;
-
-static mem_conf_t k4s561632E = {
-	0x00CD0000,      /* CASL 3, burst length 8 */
-	0x514F0000,
-	0xE2333900,
-	0x8EE70000
-};
-
-static mem_conf_t mt48lc32m16a2 = {
-	0x00CD0000,      /* CASL 3, burst length 8 */
-	0x514F0000,
-	0xD2322800,
-	0x8AD70000
-};
-
-static mem_conf_t* memory_config[] = {
-	&k4s561632E,
-	&mt48lc32m16a2
-};
-
-#endif /* _CM5200_H */
diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c
deleted file mode 100644
index 9c40ad7..0000000
--- a/board/cm5200/cmd_cm5200.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/*
- * (C) Copyright 2007 Markus Kappeler <markus.kappeler@objectxp.com>
- *
- * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-#include <usb.h>
-
-#ifdef CONFIG_CMD_BSP
-
-static int do_i2c_test(char * const argv[])
-{
-	unsigned char temp, temp1;
-
-	printf("Starting I2C Test\n"
-		"Please set Jumper:\nI2C SDA 2-3\nI2C SCL 2-3\n\n"
-		"Please press any key to start\n\n");
-	getc();
-
-	temp = 0xf0; /* set io 0-4 as output */
-	i2c_write(CONFIG_SYS_I2C_IO, 3, 1, (uchar *)&temp, 1);
-
-	printf("Press I2C4-7. LED I2C0-3 should have the same state\n\n"
-		"Press any key to stop\n\n");
-
-	while (!tstc()) {
-		i2c_read(CONFIG_SYS_I2C_IO, 0, 1, (uchar *)&temp, 1);
-		temp1 = (temp >> 4) & 0x03;
-		temp1 |= (temp >> 3) & 0x08; /* S302 -> LED303 */
-		temp1 |= (temp >> 5) & 0x04; /* S303 -> LED302 */
-		temp = temp1;
-		i2c_write(CONFIG_SYS_I2C_IO, 1, 1, (uchar *)&temp, 1);
-	}
-	getc();
-
-	return 0;
-}
-
-static int do_usb_test(char * const argv[])
-{
-	int i;
-	static int usb_stor_curr_dev = -1; /* current device */
-
-	printf("Starting USB Test\n"
-		"Please insert USB Memmory Stick\n\n"
-		"Please press any key to start\n\n");
-	getc();
-
-	usb_stop();
-	printf("(Re)start USB...\n");
-	i = usb_init();
-#ifdef CONFIG_USB_STORAGE
-		/* try to recognize storage devices immediately */
-		if (i >= 0)
-			usb_stor_curr_dev = usb_stor_scan(1);
-#endif /* CONFIG_USB_STORAGE */
-	if (usb_stor_curr_dev >= 0)
-		printf("Found USB Storage Dev continue with Test...\n");
-	else {
-		printf("No USB Storage Device detected.. Stop Test\n");
-		return 1;
-	}
-
-	usb_stor_info();
-
-	printf("stopping USB..\n");
-	usb_stop();
-
-	return 0;
-}
-
-static int do_led_test(char * const argv[])
-{
-	int i = 0;
-	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-
-	printf("Starting LED Test\n"
-		"Please set Switch S500 all off\n\n"
-		"Please press any key to start\n\n");
-	getc();
-
-	/* configure timer 2-3 for simple GPIO output High */
-	gpt->gpt2.emsr |= 0x00000034;
-	gpt->gpt3.emsr |= 0x00000034;
-
-	(*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x80000000;
-	(*(vu_long *)MPC5XXX_WU_GPIO_DIR) |= 0x80000000;
-	printf("Please press any key to stop\n\n");
-	while (!tstc()) {
-		if (i == 1) {
-			(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000;
-			gpt->gpt2.emsr &= ~0x00000010;
-			gpt->gpt3.emsr &= ~0x00000010;
-		} else if (i == 2) {
-			(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000;
-			gpt->gpt2.emsr &= ~0x00000010;
-			gpt->gpt3.emsr |= 0x00000010;
-		} else if (i >= 3) {
-			(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000;
-			gpt->gpt3.emsr &= ~0x00000010;
-			gpt->gpt2.emsr |= 0x00000010;
-			i = 0;
-		}
-		i++;
-		udelay(200000);
-	}
-	getc();
-
-	(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000;
-	gpt->gpt2.emsr |= 0x00000010;
-	gpt->gpt3.emsr |= 0x00000010;
-
-	return 0;
-}
-
-static int do_rs232_test(char * const argv[])
-{
-	int error_status = 0;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
-
-	/* Configure PSC 2-3-6 as GPIO */
-	gpio->port_config &= 0xFF0FF80F;
-
-	switch (simple_strtoul(argv[2], NULL, 10)) {
-	case 1:
-		/* check RTS <-> CTS loop */
-		/* set rts to 0 */
-		printf("Uart 1 test: RX TX tested by using U-Boot\n"
-			"Please connect RTS with CTS on Uart1 plug\n\n"
-			"Press any key to start\n\n");
-		getc();
-
-		psc1->op1 |= 0x01;
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		/* check status at cts */
-		if ((psc1->ip & 0x01) != 0) {
-			error_status = 3;
-			printf("%s: failure at rs232_1, cts status is %d "
-				"(should be 0)\n",
-				__FUNCTION__, (psc1->ip & 0x01));
-		}
-
-		/* set rts to 1 */
-		psc1->op0 |= 0x01;
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		/* check status at cts */
-		if ((psc1->ip & 0x01) != 1) {
-			error_status = 3;
-			printf("%s: failure at rs232_1, cts status is %d "
-				"(should be 1)\n",
-				__FUNCTION__, (psc1->ip & 0x01));
-		}
-		break;
-	case 2:
-		/* set PSC2_0, PSC2_2 as output and PSC2_1, PSC2_3 as input */
-		printf("Uart 2 test: Please use RS232 Loopback plug on UART2\n"
-			"\nPress any key to start\n\n");
-		getc();
-
-		gpio->simple_gpioe &= ~(0x000000F0);
-		gpio->simple_gpioe |= 0x000000F0;
-		gpio->simple_ddr &= ~(0x000000F0);
-		gpio->simple_ddr |= 0x00000050;
-
-		/* check TXD <-> RXD loop */
-		/* set TXD to 1 */
-		gpio->simple_dvo |= (1 << 4);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000020) != 0x00000020) {
-			error_status = 2;
-			printf("%s: failure at rs232_2, rxd status is %d "
-				"(should be 1)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000020) >> 5);
-		}
-
-		/* set TXD to 0 */
-		gpio->simple_dvo &= ~(1 << 4);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000020) != 0x00000000) {
-			error_status = 2;
-			printf("%s: failure at rs232_2, rxd status is %d "
-				"(should be 0)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000020) >> 5);
-		}
-
-		/* check RTS <-> CTS loop */
-		/* set RTS to 1 */
-		gpio->simple_dvo |= (1 << 6);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000080) != 0x00000080) {
-			error_status = 3;
-			printf("%s: failure at rs232_2, cts status is %d "
-				"(should be 1)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000080) >> 7);
-		}
-
-		/* set RTS to 0 */
-		gpio->simple_dvo &= ~(1 << 6);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000080) != 0x00000000) {
-			error_status = 3;
-			printf("%s: failure at rs232_2, cts status is %d "
-				"(should be 0)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000080) >> 7);
-		}
-		break;
-	case 3:
-		/* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */
-		printf("Uart 3 test: Please use RS232 Loopback plug on UART2\n"
-			"\nPress any key to start\n\n");
-		getc();
-
-		gpio->simple_gpioe &= ~(0x00000F00);
-		gpio->simple_gpioe |= 0x00000F00;
-
-		gpio->simple_ddr &= ~(0x00000F00);
-		gpio->simple_ddr |= 0x00000500;
-
-		/* check TXD <-> RXD loop */
-		/* set TXD to 1 */
-		gpio->simple_dvo |= (1 << 8);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000200) != 0x00000200) {
-			error_status = 2;
-			printf("%s: failure at rs232_3, rxd status is %d "
-				"(should be 1)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000200) >> 9);
-		}
-
-		/* set TXD to 0 */
-		gpio->simple_dvo &= ~(1 << 8);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000200) != 0x00000000) {
-			error_status = 2;
-			printf("%s: failure at rs232_3, rxd status is %d "
-				"(should be 0)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000200) >> 9);
-		}
-
-		/* check RTS <-> CTS loop */
-		/* set RTS to 1 */
-		gpio->simple_dvo |= (1 << 10);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000800) != 0x00000800) {
-			error_status = 3;
-			printf("%s: failure at rs232_3, cts status is %d "
-				"(should be 1)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000800) >> 11);
-		}
-
-		/* set RTS to 0 */
-		gpio->simple_dvo &= ~(1 << 10);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000800) != 0x00000000) {
-			error_status = 3;
-			printf("%s: failure at rs232_3, cts status is %d "
-				"(should be 0)\n", __FUNCTION__,
-				(gpio->simple_ival & 0x00000800) >> 11);
-		}
-		break;
-	case 4:
-		/* set PSC6_2, PSC6_3 as output and PSC6_0, PSC6_1 as input */
-		printf("Uart 4 test: Please use RS232 Loopback plug on UART2\n"
-			"\nPress any key to start\n\n");
-		getc();
-
-		gpio->simple_gpioe &= ~(0xF0000000);
-		gpio->simple_gpioe |= 0x30000000;
-
-		gpio->simple_ddr &= ~(0xf0000000);
-		gpio->simple_ddr |= 0x30000000;
-
-		(*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x30000000;
-		(*(vu_long *)MPC5XXX_WU_GPIO_DIR) &= ~(0x30000000);
-
-		/* check TXD <-> RXD loop */
-		/* set TXD to 1 */
-		gpio->simple_dvo |= (1 << 28);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) !=
-				0x10000000) {
-			error_status = 2;
-			printf("%s: failure at rs232_4, rxd status is %lu "
-				"(should be 1)\n", __FUNCTION__,
-				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
-					0x10000000) >> 28);
-		}
-
-		/* set TXD to 0 */
-		gpio->simple_dvo &= ~(1 << 28);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) !=
-				0x00000000) {
-			error_status = 2;
-			printf("%s: failure at rs232_4, rxd status is %lu "
-				"(should be 0)\n", __FUNCTION__,
-				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
-					0x10000000) >> 28);
-		}
-
-		/* check RTS <-> CTS loop */
-		/* set RTS to 1 */
-		gpio->simple_dvo |= (1 << 29);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) !=
-				0x20000000) {
-			error_status = 3;
-			printf("%s: failure at rs232_4, cts status is %lu "
-				"(should be 1)\n", __FUNCTION__,
-				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
-					0x20000000) >> 29);
-		}
-
-		/* set RTS to 0 */
-		gpio->simple_dvo &= ~(1 << 29);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) !=
-				0x00000000) {
-			error_status = 3;
-			printf("%s: failure at rs232_4, cts status is %lu "
-				"(should be 0)\n", __FUNCTION__,
-				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
-					0x20000000) >> 29);
-		}
-		break;
-	default:
-		printf("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]);
-		error_status = 1;
-		break;
-	}
-	gpio->port_config |= (CONFIG_SYS_GPS_PORT_CONFIG & 0xFF0FF80F);
-
-	return error_status;
-}
-
-static int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int rcode = -1;
-
-	switch (argc) {
-	case 2:
-		if (strncmp(argv[1], "i2c", 3) == 0)
-			rcode = do_i2c_test(argv);
-		else if (strncmp(argv[1], "led", 3) == 0)
-			rcode = do_led_test(argv);
-		else if (strncmp(argv[1], "usb", 3) == 0)
-			rcode = do_usb_test(argv);
-		break;
-	case 3:
-		if (strncmp(argv[1], "rs232", 3) == 0)
-			rcode = do_rs232_test(argv);
-		break;
-	}
-
-	switch (rcode) {
-	case -1:
-		printf("Usage:\n"
-			"fkt { i2c | led | usb }\n"
-			"fkt rs232 number\n");
-		rcode = 1;
-		break;
-	case 0:
-		printf("Test passed\n");
-		break;
-	default:
-		printf("Test failed with code: %d\n", rcode);
-	}
-
-	return rcode;
-}
-
-U_BOOT_CMD(
-	fkt,	4,	1,	cmd_fkt,
-	"Function test routines",
-	"i2c\n"
-	"     - Test I2C communication\n"
-	"fkt led\n"
-	"     - Test LEDs\n"
-	"fkt rs232 number\n"
-	"     - Test RS232 (loopback plug(s) for RS232 required)\n"
-	"fkt usb\n"
-	"     - Test USB communication"
-);
-#endif /* CONFIG_CMD_BSP */
diff --git a/board/cm5200/fwupdate.c b/board/cm5200/fwupdate.c
deleted file mode 100644
index 4740c83..0000000
--- a/board/cm5200/fwupdate.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * (C) Copyright 2007 Schindler Lift Inc.
- * (C) Copyright 2007 DENX Software Engineering
- *
- * Author: Michel Marti <mma@objectxp.com>
- * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>:
- *   - code clean-up
- *   - bugfix for overwriting bootargs by user
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <fat.h>
-#include <malloc.h>
-#include <image.h>
-#include <usb.h>
-#include <fat.h>
-
-#include "fwupdate.h"
-
-static int load_rescue_image(ulong);
-
-void cm5200_fwupdate(void)
-{
-	cmd_tbl_t *bcmd;
-	char *rsargs;
-	char *tmp = NULL;
-	char ka[16];
-	char * const argv[3] = { "bootm", ka, NULL };
-
-	/* Check if rescue system is disabled... */
-	if (getenv("norescue")) {
-		printf(LOG_PREFIX "Rescue System disabled.\n");
-		return;
-	}
-
-	/* Check if we have a USB storage device and load image */
-	if (load_rescue_image(LOAD_ADDR))
-		return;
-
-	bcmd = find_cmd("bootm");
-	if (!bcmd)
-		return;
-
-	sprintf(ka, "%lx", (ulong)LOAD_ADDR);
-
-	/* prepare our bootargs */
-	rsargs = getenv("rs-args");
-	if (!rsargs)
-		rsargs = RS_BOOTARGS;
-	else {
-		tmp = malloc(strlen(rsargs+1));
-		if (!tmp) {
-			printf(LOG_PREFIX "Memory allocation failed\n");
-			return;
-		}
-		strcpy(tmp, rsargs);
-		rsargs = tmp;
-	}
-
-	setenv("bootargs", rsargs);
-
-	if (rsargs == tmp)
-		free(rsargs);
-
-	printf(LOG_PREFIX "Starting update system (bootargs=%s)...\n", rsargs);
-	do_bootm(bcmd, 0, 2, argv);
-}
-
-static int load_rescue_image(ulong addr)
-{
-	disk_partition_t info;
-	int devno;
-	int partno;
-	int i;
-	char fwdir[64];
-	char nxri[128];
-	char *tmp;
-	char dev[7];
-	char addr_str[16];
-	char * const argv[6] = { "fatload", "usb", dev, addr_str, nxri, NULL };
-	struct blk_desc *stor_dev = NULL;
-	cmd_tbl_t *bcmd;
-
-	/* Get name of firmware directory */
-	tmp = getenv("fw-dir");
-
-	/* Copy it into fwdir */
-	strncpy(fwdir, tmp ? tmp : FW_DIR, sizeof(fwdir));
-	fwdir[sizeof(fwdir) - 1] = 0; /* Terminate string */
-
-	printf(LOG_PREFIX "Checking for firmware image directory '%s' on USB"
-		" storage...\n", fwdir);
-	usb_stop();
-	if (usb_init() != 0)
-		return 1;
-
-	/* Check for storage device */
-	if (usb_stor_scan(1) != 0) {
-		usb_stop();
-		return 1;
-	}
-
-	/* Detect storage device */
-	for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) {
-		stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, devno);
-		if (stor_dev->type != DEV_TYPE_UNKNOWN)
-			break;
-	}
-	if (!stor_dev || stor_dev->type == DEV_TYPE_UNKNOWN) {
-		printf(LOG_PREFIX "No valid storage device found...\n");
-		usb_stop();
-		return 1;
-	}
-
-	/* Detect partition */
-	for (partno = -1, i = 0; i < 6; i++) {
-		if (part_get_info(stor_dev, i, &info) == 0) {
-			if (fat_register_device(stor_dev, i) == 0) {
-				/* Check if rescue image is present */
-				FW_DEBUG("Looking for firmware directory '%s'"
-					" on partition %d\n", fwdir, i);
-				if (!fat_exists(fwdir)) {
-					FW_DEBUG("No NX rescue image on "
-						"partition %d.\n", i);
-					partno = -2;
-				} else {
-					partno = i;
-					FW_DEBUG("Partition %d contains "
-						"firmware directory\n", partno);
-					break;
-				}
-			}
-		}
-	}
-
-	if (partno < 0) {
-		switch (partno) {
-		case -1:
-			printf(LOG_PREFIX "Error: No valid (FAT) partition "
-				"detected\n");
-			break;
-		case -2:
-			printf(LOG_PREFIX "Error: No NX rescue image on FAT "
-				"partition\n");
-			break;
-		default:
-			printf(LOG_PREFIX "Error: Failed with code %d\n",
-				partno);
-		}
-		usb_stop();
-		return 1;
-	}
-
-	/* Load the rescue image */
-	bcmd = find_cmd("fatload");
-	if (!bcmd) {
-		printf(LOG_PREFIX "Error - 'fatload' command not present.\n");
-		usb_stop();
-		return 1;
-	}
-
-	tmp = getenv("nx-rescue-image");
-	sprintf(nxri, "%s/%s", fwdir, tmp ? tmp : RESCUE_IMAGE);
-	sprintf(dev, "%d:%d", devno, partno);
-	sprintf(addr_str, "%lx", addr);
-
-	FW_DEBUG("fat_fsload device='%s', addr='%s', file: %s\n",
-		dev, addr_str, nxri);
-
-	if (do_fat_fsload(bcmd, 0, 5, argv) != 0) {
-		usb_stop();
-		return 1;
-	}
-
-	/* Stop USB */
-	usb_stop();
-	return 0;
-}
diff --git a/board/cm5200/fwupdate.h b/board/cm5200/fwupdate.h
deleted file mode 100644
index 6ddf0ba..0000000
--- a/board/cm5200/fwupdate.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2007 Schindler Lift Inc.
- *
- * Author: Michel Marti <mma@objectxp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __FW_UPDATE_H
-#define __FW_UPDATE_H
-
-/* Default prefix for output messages */
-#define LOG_PREFIX	"CM5200:"
-
-/* Extra debug macro */
-#ifdef CONFIG_FWUPDATE_DEBUG
-#define FW_DEBUG(fmt...) printf(LOG_PREFIX fmt)
-#else
-#define FW_DEBUG(fmt...)
-#endif
-
-/* Name of the directory holding firmware images */
-#define FW_DIR		"nx-fw"
-#define RESCUE_IMAGE	"nxrs.img"
-#define LOAD_ADDR	0x400000
-#define RS_BOOTARGS	"ramdisk_size=8192K"
-
-/* Main function for fwupdate */
-void cm5200_fwupdate(void);
-
-#endif /* __FW_UPDATE_H */
diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c
index 0f3bcc5..0ceaa1f 100644
--- a/board/cobra5272/cobra5272.c
+++ b/board/cobra5272/cobra5272.c
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <asm/immap.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 int checkboard (void)
 {
@@ -16,7 +17,7 @@ int checkboard (void)
 	return 0;
 };
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
 
@@ -26,7 +27,9 @@ phys_size_t initdram (int board_type)
 	/* Dummy write to start SDRAM */
 	*((volatile unsigned long *) 0) = 0;
 
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
 };
 
 int testdram (void)
diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c
index 43931b0..54eef6c 100644
--- a/board/compal/paz00/paz00.c
+++ b/board/compal/paz00/paz00.c
@@ -13,7 +13,7 @@
 #include <asm/arch/pinmux.h>
 #include <asm/gpio.h>
 
-#ifdef CONFIG_TEGRA_MMC
+#ifdef CONFIG_MMC_SDHCI_TEGRA
 /*
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
diff --git a/board/compulab/cl-som-am57x/Kconfig b/board/compulab/cl-som-am57x/Kconfig
new file mode 100644
index 0000000..85fc9a1
--- /dev/null
+++ b/board/compulab/cl-som-am57x/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CL_SOM_AM57X
+
+config SYS_BOARD
+	default "cl-som-am57x"
+
+config SYS_VENDOR
+	default "compulab"
+
+config SYS_CONFIG_NAME
+	default "cl-som-am57x"
+
+endif
diff --git a/board/compulab/cl-som-am57x/MAINTAINERS b/board/compulab/cl-som-am57x/MAINTAINERS
new file mode 100644
index 0000000..e0195f4
--- /dev/null
+++ b/board/compulab/cl-som-am57x/MAINTAINERS
@@ -0,0 +1,6 @@
+CL-SOM-AM57x BOARD
+M:	Uri Mashiach <uri.mashiach@compulab.co.il>
+S:	Maintained
+F:	board/compulab/cl-som-am57x/
+F:	include/configs/cl-som-am57x.h
+F:	configs/cl-som-am57x_defconfig
diff --git a/board/compulab/cl-som-am57x/Makefile b/board/compulab/cl-som-am57x/Makefile
new file mode 100644
index 0000000..566366b
--- /dev/null
+++ b/board/compulab/cl-som-am57x/Makefile
@@ -0,0 +1,17 @@
+#
+# Makefile
+#
+# (C) Copyright 2016 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	+= spl.o mux.o
+else
+obj-y	+= cl-som-am57x.o mux.o
+endif
+
+obj-$(CONFIG_DRIVER_TI_CPSW)	+= eth.o
diff --git a/board/compulab/cl-som-am57x/cl-som-am57x.c b/board/compulab/cl-som-am57x/cl-som-am57x.c
new file mode 100644
index 0000000..389eebb
--- /dev/null
+++ b/board/compulab/cl-som-am57x/cl-som-am57x.c
@@ -0,0 +1,66 @@
+/*
+ * Board functions for CompuLab cl_som_am57x board
+ *
+ * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
+ *
+ * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <palmas.h>
+#include <usb.h>
+#include <asm/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include "../common/common.h"
+#include "../common/eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+	"Board: CL-SOM-AM57x\n"
+};
+
+int board_init(void)
+{
+	/* Disable PMIC Powerhold feature, DEV_CTRL.DEV_ON = 1 */
+	palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_MMC
+#define SB_SOM_CD_GPIO 187
+#define SB_SOM_WP_GPIO 188
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret0, ret1;
+
+	ret0 = omap_mmc_init(0, 0, 0, SB_SOM_CD_GPIO, SB_SOM_WP_GPIO);
+	if (ret0)
+		printf("cl-som-am57x: failed to initialize mmc0\n");
+
+	ret1 = omap_mmc_init(1, 0, 0, -1, -1);
+	if (ret1)
+		printf("cl-som-am57x: failed to initialize mmc1\n");
+
+	return ret0 && ret1;
+}
+#endif /* CONFIG_MMC */
+
+int misc_init_r(void)
+{
+	cl_print_pcb_info();
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
+}
diff --git a/board/compulab/cl-som-am57x/eth.c b/board/compulab/cl-som-am57x/eth.c
new file mode 100644
index 0000000..0c4bf91
--- /dev/null
+++ b/board/compulab/cl-som-am57x/eth.c
@@ -0,0 +1,198 @@
+/*
+ * Ethernet specific code for CompuLab CL-SOM-AM57x module
+ *
+ * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <cpsw.h>
+#include <miiphy.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include "../common/eeprom.h"
+
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+}
+
+static struct cpsw_slave_data cl_som_am57x_cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+		.phy_if         = PHY_INTERFACE_MODE_RMII,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+		.phy_if         = PHY_INTERFACE_MODE_RMII,
+
+	},
+};
+
+static struct cpsw_platform_data cl_som_am57_cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 2,
+	.slave_data		= cl_som_am57x_cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+/*
+ * cl_som_am57x_efuse_read_mac_addr() - read Ethernet port MAC address.
+ *       The information is retrieved from the SOC's registers.
+ * @buff: read buffer.
+ * @port_num: port number.
+ */
+static void cl_som_am57x_efuse_read_mac_addr(uchar *buff, uint port_num)
+{
+	uint32_t mac_hi, mac_lo;
+
+	if (port_num) {
+		mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
+		mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
+	} else {
+		mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
+		mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
+	}
+
+	buff[0] = (mac_hi & 0xFF0000) >> 16;
+	buff[1] = (mac_hi & 0xFF00) >> 8;
+	buff[2] = mac_hi & 0xFF;
+	buff[3] = (mac_lo & 0xFF0000) >> 16;
+	buff[4] = (mac_lo & 0xFF00) >> 8;
+	buff[5] = mac_lo & 0xFF;
+}
+
+/*
+ * cl_som_am57x_handle_mac_address() - set MAC address in the U-Boot
+ *	environment.
+ *      The address is retrieved retrieved from an EEPROM field or from the
+ *	SOC's registers.
+ * @env_name: U-Boot environment name.
+ * @field_name: EEPROM field name.
+ * @port_num: SOC's port number.
+ */
+static int cl_som_am57x_handle_mac_address(char *env_name, uint port_num)
+{
+	int ret;
+	uint8_t enetaddr[6];
+
+	ret = eth_getenv_enetaddr(env_name, enetaddr);
+	if (ret)
+		return 0;
+
+	ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
+
+	if (ret || !is_valid_ethaddr(enetaddr))
+		cl_som_am57x_efuse_read_mac_addr(enetaddr, port_num);
+
+	if (!is_valid_ethaddr(enetaddr))
+		return -1;
+
+	ret = eth_setenv_enetaddr(env_name, enetaddr);
+	if (ret)
+		printf("cl-som-am57x: Failed to set Eth port %d MAC address\n",
+		       port_num);
+
+	return ret;
+}
+
+#define CL_SOM_AM57X_PHY_ADDR2			0x01
+#define AR8033_PHY_DEBUG_ADDR_REG		0x1d
+#define AR8033_PHY_DEBUG_DATA_REG		0x1e
+#define AR8033_DEBUG_RGMII_RX_CLK_DLY_REG	0x00
+#define AR8033_DEBUG_RGMII_TX_CLK_DLY_REG	0x05
+#define AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK	(1 << 15)
+#define AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK	(1 << 8)
+
+/*
+ * cl_som_am57x_rgmii_clk_delay() - Set RGMII clock delay.
+ *	Enable RX delay, disable TX delay.
+ */
+static void cl_som_am57x_rgmii_clk_delay(void)
+{
+	uint16_t mii_reg_val;
+	const char *devname;
+
+	devname = miiphy_get_current_dev();
+	/* PHY 2 */
+	miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_ADDR_REG,
+		     AR8033_DEBUG_RGMII_RX_CLK_DLY_REG);
+	miiphy_read(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG,
+		    &mii_reg_val);
+	mii_reg_val |= AR8033_DEBUG_RGMII_RX_CLK_DLY_MASK;
+	miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG,
+		     mii_reg_val);
+
+	miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_ADDR_REG,
+		     AR8033_DEBUG_RGMII_TX_CLK_DLY_REG);
+	miiphy_read(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG,
+		    &mii_reg_val);
+	mii_reg_val &= ~AR8033_DEBUG_RGMII_TX_CLK_DLY_MASK;
+	miiphy_write(devname, CL_SOM_AM57X_PHY_ADDR2, AR8033_PHY_DEBUG_DATA_REG,
+		     mii_reg_val);
+}
+
+#define CL_SOM_AM57X_GPIO_PHY1_RST 92 /* GPIO3_28 */
+#define CL_SOM_AM57X_RGMII_PORT1 1
+
+int board_eth_init(bd_t *bis)
+{
+	int ret;
+	uint32_t ctrl_val;
+	char *cpsw_phy_envval;
+	int cpsw_act_phy = 1;
+
+	/* SB-SOM-AM57x primary Eth (P21) is routed to RGMII1 */
+	ret = cl_som_am57x_handle_mac_address("ethaddr",
+					      CL_SOM_AM57X_RGMII_PORT1);
+
+	if (ret)
+		return -1;
+
+	/* Select RGMII for GMII1_SEL */
+	ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
+	ctrl_val |= 0x22;
+	writel(ctrl_val, (*ctrl)->control_core_control_io1);
+	mdelay(10);
+
+	gpio_request(CL_SOM_AM57X_GPIO_PHY1_RST, "phy1_rst");
+	gpio_direction_output(CL_SOM_AM57X_GPIO_PHY1_RST, 0);
+	mdelay(20);
+
+	gpio_set_value(CL_SOM_AM57X_GPIO_PHY1_RST, 1);
+	mdelay(20);
+
+	cpsw_phy_envval = getenv("cpsw_phy");
+	if (cpsw_phy_envval != NULL)
+		cpsw_act_phy = simple_strtoul(cpsw_phy_envval, NULL, 0);
+
+	cl_som_am57_cpsw_data.active_slave = cpsw_act_phy;
+
+	ret = cpsw_register(&cl_som_am57_cpsw_data);
+	if (ret < 0)
+		printf("Error %d registering CPSW switch\n", ret);
+
+	/* Set RGMII clock delay */
+	cl_som_am57x_rgmii_clk_delay();
+
+	return ret;
+}
diff --git a/board/compulab/cl-som-am57x/mux.c b/board/compulab/cl-som-am57x/mux.c
new file mode 100644
index 0000000..0db0609
--- /dev/null
+++ b/board/compulab/cl-som-am57x/mux.c
@@ -0,0 +1,123 @@
+/*
+ * Pinmux configuration for CompuLab CL-SOM-AM57x board
+ *
+ * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
+ *
+ * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux_dra7xx.h>
+
+/* Serial console */
+static const struct pad_conf_entry cl_som_am57x_padconf_console[] = {
+	{UART3_RXD, (FSC | IEN | PDIS | PTU | M0)}, /* UART3_RXD */
+	{UART3_TXD, (FSC | IEN | PDIS | PTU | M0)}, /* UART3_TXD */
+};
+
+/* PMIC I2C */
+static const struct pad_conf_entry cl_som_am57x_padconf_pmic[] = {
+	{MCASP1_ACLKR, (IEN | PEN | M10)}, /* MCASP1_ACLKR.I2C4_SDA */
+	{MCASP1_FSR,   (IEN | PEN | M10)}, /* MCASP1_FSR.I2C4_SCL */
+};
+
+/* Green GPIO led */
+static const struct pad_conf_entry cl_som_am57x_padconf_green_led[] = {
+	{GPMC_A15, (IDIS | PDIS | PTD | M14)}, /* GPMC_A15.GPIO2_5 */
+};
+
+/* MMC/SD Card */
+static const struct pad_conf_entry cl_som_am57x_padconf_sd_card[] = {
+	{MMC1_CLK,  (IEN | PDIS | PTU | M0) }, /* MMC1_CLK */
+	{MMC1_CMD,  (IEN | PDIS | PTU | M0) }, /* MMC1_CMD */
+	{MMC1_DAT0, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT0 */
+	{MMC1_DAT1, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT1 */
+	{MMC1_DAT2, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT2 */
+	{MMC1_DAT3, (IEN | PDIS | PTU | M0) }, /* MMC1_DAT3 */
+	{MMC1_SDCD, (IEN | PEN  |	M14)}, /* MMC1_SDCD */
+	{MMC1_SDWP, (IEN | PEN  |	M14)}, /* MMC1_SDWP */
+};
+
+/* WiFi - must be in the safe mode on boot */
+static const struct pad_conf_entry cl_som_am57x_padconf_wifi[] = {
+	{UART1_CTSN, (IEN | M15)}, /* UART1_CTSN */
+	{UART1_RTSN, (IEN | M15)}, /* UART1_RTSN */
+	{UART2_RXD,  (IEN | M15)}, /* UART2_RXD */
+	{UART2_TXD,  (IEN | M15)}, /* UART2_TXD */
+	{UART2_CTSN, (IEN | M15)}, /* UART2_CTSN */
+	{UART2_RTSN, (IEN | M15)}, /* UART2_RTSN */
+};
+
+/* QSPI */
+static const struct pad_conf_entry cl_som_am57x_padconf_qspi[] = {
+	{GPMC_A13, (IEN | PEN  |       M1)}, /* GPMC_A13.QSPI1_RTCLK */
+	{GPMC_A18, (IEN | PEN  |       M1)}, /* GPMC_A18.QSPI1_SCLK */
+	{GPMC_A16, (IEN | PEN  |       M1)}, /* GPMC_A16.QSPI1_D0 */
+	{GPMC_A17, (IEN | PEN  |       M1)}, /* GPMC_A17.QSPI1_D1 */
+	{GPMC_CS2, (IEN | PDIS | PTU | M1)}, /* GPMC_CS2.QSPI1_CS0 */
+};
+
+/* GPIO Expander I2C */
+static const struct pad_conf_entry cl_som_am57x_padconf_i2c_gpio[] = {
+	{MCASP1_AXR0, (IEN | PEN | M10)}, /* MCASP1_AXR0.I2C5_SDA */
+	{MCASP1_AXR1, (IEN | PEN | M10)}, /* MCASP1_AXR1.I2C5_SCL */
+};
+
+/* eMMC internal storage */
+static const struct pad_conf_entry cl_som_am57x_padconf_emmc[] = {
+	{GPMC_A19, (IEN | PDIS | PTU | M1)}, /* GPMC_A19.MMC2_DAT4 */
+	{GPMC_A20, (IEN | PDIS | PTU | M1)}, /* GPMC_A20.MMC2_DAT5 */
+	{GPMC_A21, (IEN | PDIS | PTU | M1)}, /* GPMC_A21.MMC2_DAT6 */
+	{GPMC_A22, (IEN | PDIS | PTU | M1)}, /* GPMC_A22.MMC2_DAT7 */
+	{GPMC_A23, (IEN | PDIS | PTU | M1)}, /* GPMC_A23.MMC2_CLK */
+	{GPMC_A24, (IEN | PDIS | PTU | M1)}, /* GPMC_A24.MMC2_DAT0 */
+	{GPMC_A25, (IEN | PDIS | PTU | M1)}, /* GPMC_A25.MMC2_DAT1 */
+	{GPMC_A26, (IEN | PDIS | PTU | M1)}, /* GPMC_A26.MMC2_DAT2 */
+	{GPMC_A27, (IEN | PDIS | PTU | M1)}, /* GPMC_A27.MMC2_DAT3 */
+	{GPMC_CS1, (IEN | PDIS | PTU | M1)}, /* GPMC_CS1.MMC2_CMD */
+};
+
+/* usb1_drvvbus */
+static const struct pad_conf_entry cl_som_am57x_padconf_usb[] = {
+	{USB1_DRVVBUS, (M0 | FSC) }, /* USB1_DRVVBUS.USB1_DRVVBUS */
+};
+
+/* Ethernet */
+static const struct pad_conf_entry cl_som_am57x_padconf_ethernet[] = {
+	/* MDIO bus */
+	{VIN2A_D10,  (PDIS | PTU  |	  M3) }, /* VIN2A_D10.MDIO_MCLK  */
+	{VIN2A_D11,  (IEN  | PDIS | PTU | M3) }, /* VIN2A_D11.MDIO_D  */
+	/* EMAC Slave 1 at addr 0x1 - Default interface */
+	{VIN2A_D12,  (IDIS | PEN  |	  M3) }, /* VIN2A_D12.RGMII1_TXC */
+	{VIN2A_D13,  (IDIS | PEN  |	  M3) }, /* VIN2A_D13.RGMII1_TXCTL */
+	{VIN2A_D14,  (IDIS | PEN  |	  M3) }, /* VIN2A_D14.RGMII1_TXD3 */
+	{VIN2A_D15,  (IDIS | PEN  |	  M3) }, /* VIN2A_D15.RGMII1_TXD2 */
+	{VIN2A_D16,  (IDIS | PEN  |	  M3) }, /* VIN2A_D16.RGMII1_TXD1 */
+	{VIN2A_D17,  (IDIS | PEN  |	  M3) }, /* VIN2A_D17.RGMII1_TXD0 */
+	{VIN2A_D18,  (IEN  | PDIS | PTD | M3) }, /* VIN2A_D18.RGMII1_RXC */
+	{VIN2A_D19,  (IEN  | PDIS | PTD | M3) }, /* VIN2A_D19.RGMII1_RXCTL */
+	{VIN2A_D20,  (IEN  | PDIS | PTD | M3) }, /* VIN2A_D20.RGMII1_RXD3 */
+	{VIN2A_D21,  (IEN  | PDIS | PTD | M3) }, /* VIN2A_D21.RGMII1_RXD2 */
+	{VIN2A_D22,  (IEN  | PDIS | PTD | M3) }, /* VIN2A_D22.RGMII1_RXD1 */
+	{VIN2A_D23,  (IEN  | PDIS | PTD | M3) }, /* VIN2A_D23.RGMII1_RXD0 */
+	/* Eth PHY1 reset GPIOs*/
+	{VIN2A_CLK0, (IDIS | PDIS | PTD | M14)}, /* VIN2A_CLK0.GPIO3_28 */
+};
+
+#define SET_MUX(mux_array) do_set_mux32((*ctrl)->control_padconf_core_base, \
+					mux_array, ARRAY_SIZE(mux_array))
+
+void set_muxconf_regs(void)
+{
+	SET_MUX(cl_som_am57x_padconf_console);
+	SET_MUX(cl_som_am57x_padconf_pmic);
+	SET_MUX(cl_som_am57x_padconf_green_led);
+	SET_MUX(cl_som_am57x_padconf_sd_card);
+	SET_MUX(cl_som_am57x_padconf_wifi);
+	SET_MUX(cl_som_am57x_padconf_qspi);
+	SET_MUX(cl_som_am57x_padconf_i2c_gpio);
+	SET_MUX(cl_som_am57x_padconf_emmc);
+	SET_MUX(cl_som_am57x_padconf_usb);
+	SET_MUX(cl_som_am57x_padconf_ethernet);
+}
diff --git a/board/compulab/cl-som-am57x/spl.c b/board/compulab/cl-som-am57x/spl.c
new file mode 100644
index 0000000..de2dadc
--- /dev/null
+++ b/board/compulab/cl-som-am57x/spl.c
@@ -0,0 +1,239 @@
+/*
+ * SPL data and initialization for CompuLab CL-SOM-AM57x board
+ *
+ * (C) Copyright 2016 CompuLab, Ltd. http://compulab.co.il/
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/emif.h>
+#include <asm/omap_common.h>
+#include <asm/arch/sys_proto.h>
+
+static const struct dmm_lisa_map_regs cl_som_am57x_lisa_regs = {
+	.dmm_lisa_map_3 = 0x80740300,
+	.is_ma_present  = 0x1
+};
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+{
+	/* Disable SDRAM controller EMIF2 for single core SOC */
+	*dmm_lisa_regs = &cl_som_am57x_lisa_regs;
+	if (omap_revision() == DRA722_ES1_0) {
+		((struct dmm_lisa_map_regs *) *dmm_lisa_regs)->dmm_lisa_map_3 =
+		  0x80640100;
+	}
+}
+
+static const struct emif_regs cl_som_am57x_emif1_ddr3_532mhz_emif_regs = {
+	.sdram_config_init	= 0x61852332,
+	.sdram_config		= 0x61852332,
+	.sdram_config2		= 0x00000000,
+	.ref_ctrl		= 0x000040f1,
+	.ref_ctrl_final		= 0x00001040,
+	.sdram_tim1		= 0xeeef36f3,
+	.sdram_tim2		= 0x348f7fda,
+	.sdram_tim3		= 0x027f88a8,
+	.read_idle_ctrl		= 0x00050000,
+	.zq_config		= 0x1007190b,
+	.temp_alert_config	= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init = 0x0034400b,
+	.emif_ddr_phy_ctlr_1	= 0x0e34400b,
+	.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+	.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
+	.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
+	.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
+	.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
+	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
+	.emif_rd_wr_lvl_ctl	= 0x00000000,
+	.emif_rd_wr_exec_thresh	= 0x00000305
+};
+
+/* Ext phy ctrl regs 1-35 */
+static const u32 cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs[] = {
+	0x10040100,
+	0x00740074,
+	0x00780078,
+	0x007c007c,
+	0x007b007b,
+	0x00800080,
+	0x00360036,
+	0x00340034,
+	0x00360036,
+	0x00350035,
+	0x00350035,
+
+	0x01ff01ff,
+	0x01ff01ff,
+	0x01ff01ff,
+	0x01ff01ff,
+	0x01ff01ff,
+
+	0x00430043,
+	0x003e003e,
+	0x004a004a,
+	0x00470047,
+	0x00400040,
+
+	0x00000000,
+	0x00600020,
+	0x40011080,
+	0x08102040,
+
+	0x00400040,
+	0x00400040,
+	0x00400040,
+	0x00400040,
+	0x00400040,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0
+};
+
+static const struct emif_regs cl_som_am57x_emif2_ddr3_532mhz_emif_regs = {
+	.sdram_config_init	= 0x61852332,
+	.sdram_config		= 0x61852332,
+	.sdram_config2		= 0x00000000,
+	.ref_ctrl		= 0x000040f1,
+	.ref_ctrl_final		= 0x00001040,
+	.sdram_tim1		= 0xeeef36f3,
+	.sdram_tim2		= 0x348f7fda,
+	.sdram_tim3		= 0x027f88a8,
+	.read_idle_ctrl		= 0x00050000,
+	.zq_config		= 0x1007190b,
+	.temp_alert_config	= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init = 0x0034400b,
+	.emif_ddr_phy_ctlr_1	= 0x0e34400b,
+	.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+	.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
+	.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
+	.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
+	.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
+	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
+	.emif_rd_wr_lvl_ctl	= 0x00000000,
+	.emif_rd_wr_exec_thresh	= 0x00000305
+};
+
+static const u32 cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs[] = {
+	0x10040100,
+	0x00820082,
+	0x008b008b,
+	0x00800080,
+	0x007e007e,
+	0x00800080,
+	0x00370037,
+	0x00390039,
+	0x00360036,
+	0x00370037,
+	0x00350035,
+	0x01ff01ff,
+	0x01ff01ff,
+	0x01ff01ff,
+	0x01ff01ff,
+	0x01ff01ff,
+	0x00540054,
+	0x00540054,
+	0x004e004e,
+	0x004c004c,
+	0x00400040,
+
+	0x00000000,
+	0x00600020,
+	0x40011080,
+	0x08102040,
+
+	0x00400040,
+	0x00400040,
+	0x00400040,
+	0x00400040,
+	0x00400040,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0
+};
+
+static struct vcores_data cl_som_am57x_volts = {
+	.mpu.value[OPP_NOM]	= VDD_MPU_DRA7_NOM,
+	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+	.mpu.addr		= TPS659038_REG_ADDR_SMPS12,
+	.mpu.pmic		= &tps659038,
+
+	.eve.value[OPP_NOM]	= VDD_EVE_DRA7_NOM,
+	.eve.value[OPP_OD]	= VDD_EVE_DRA7_OD,
+	.eve.value[OPP_HIGH]	= VDD_EVE_DRA7_HIGH,
+	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_DSPEVE_OD,
+	.eve.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
+	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.eve.addr		= TPS659038_REG_ADDR_SMPS45,
+	.eve.pmic		= &tps659038,
+
+	.gpu.value[OPP_NOM]	= VDD_GPU_DRA7_NOM,
+	.gpu.value[OPP_OD]	= VDD_GPU_DRA7_OD,
+	.gpu.value[OPP_HIGH]	= VDD_GPU_DRA7_HIGH,
+	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_GPU_OD,
+	.gpu.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_GPU_HIGH,
+	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.gpu.addr		= TPS659038_REG_ADDR_SMPS6,
+	.gpu.pmic		= &tps659038,
+
+	.core.value[OPP_NOM]	= VDD_CORE_DRA7_NOM,
+	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.core.addr		= TPS659038_REG_ADDR_SMPS7,
+	.core.pmic		= &tps659038,
+
+	.iva.value[OPP_NOM]	= VDD_IVA_DRA7_NOM,
+	.iva.value[OPP_OD]	= VDD_IVA_DRA7_OD,
+	.iva.value[OPP_HIGH]	= VDD_IVA_DRA7_HIGH,
+	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_IVA_OD,
+	.iva.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_IVA_HIGH,
+	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.iva.addr		= TPS659038_REG_ADDR_SMPS8,
+	.iva.pmic		= &tps659038,
+};
+
+void hw_data_init(void)
+{
+	*prcm = &dra7xx_prcm;
+	*dplls_data = &dra7xx_dplls;
+	*omap_vcores = &cl_som_am57x_volts;
+	*ctrl = &dra7xx_ctrl;
+}
+
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+{
+	switch (emif_nr) {
+	case 1:
+		*regs = &cl_som_am57x_emif1_ddr3_532mhz_emif_regs;
+		break;
+	case 2:
+		*regs = &cl_som_am57x_emif2_ddr3_532mhz_emif_regs;
+		break;
+	}
+}
+
+void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
+{
+	switch (emif_nr) {
+	case 1:
+		*regs = cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs;
+		*size = ARRAY_SIZE(cl_som_am57x_emif1_ddr3_ext_phy_ctrl_regs);
+		break;
+	case 2:
+		*regs = cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs;
+		*size = ARRAY_SIZE(cl_som_am57x_emif2_ddr3_ext_phy_ctrl_regs);
+		break;
+	}
+}
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index 28e9a8f..c59884a 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -23,9 +23,9 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mxc_hdmi.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/video.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <dm/platform_data/serial_mxc.h>
@@ -602,7 +602,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	char baseboard_name[16];
 	int err;
 
-	fdt_shrink_to_minimum(blob); /* Make room for new properties */
+	fdt_shrink_to_minimum(blob, 0); /* Make room for new properties */
 
 	/* MAC addr */
 	if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
@@ -688,7 +688,7 @@ int misc_init_r(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
@@ -720,6 +720,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[1].size = 0x7FF00000;
 		break;
 	}
+
+	return 0;
 }
 
 int dram_init(void)
diff --git a/board/compulab/cm_fx6/common.c b/board/compulab/cm_fx6/common.c
index 59c9d1a..19fa5d3 100644
--- a/board/compulab/cm_fx6/common.c
+++ b/board/compulab/cm_fx6/common.c
@@ -11,7 +11,7 @@
 #include <common.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/spi.h>
+#include <asm/mach-imx/spi.h>
 #include <fsl_esdhc.h>
 #include "common.h"
 
diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c
index 9442d09..bba977f 100644
--- a/board/compulab/cm_fx6/spl.c
+++ b/board/compulab/cm_fx6/spl.c
@@ -16,7 +16,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
 #include <fsl_esdhc.h>
 #include "common.h"
 
diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c
index 428aee6..c4506b9 100644
--- a/board/compulab/cm_t335/cm_t335.c
+++ b/board/compulab/cm_t335/cm_t335.c
@@ -31,8 +31,8 @@ int board_init(void)
 
 	gpmc_init();
 
-#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
-	status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
+	status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_OFF);
 #endif
 	return 0;
 }
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index 189d903..da67098 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -24,7 +24,7 @@
 #include <linux/compiler.h>
 
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/mmc_host_def.h>
@@ -92,8 +92,8 @@ int board_init(void)
 	/* boot param addr */
 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
 
-#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
-	status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
+	status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
 #endif
 
 	return 0;
@@ -372,7 +372,7 @@ void set_muxconf_regs(void)
 		cm_t3730_set_muxconf();
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_MMC)
 #define SB_T35_WP_GPIO 59
 
 int board_mmc_getcd(struct mmc *mmc)
@@ -391,14 +391,14 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-#if defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 void board_mmc_power_init(void)
 {
 	twl4030_power_mmc_init(0);
 }
 #endif
 
-#ifdef CONFIG_SYS_I2C_OMAP34XX
+#ifdef CONFIG_SYS_I2C_OMAP24XX
 /*
  * Routine: reset_net_chip
  * Description: reset the Ethernet controller via TPS65930 GPIO
diff --git a/board/compulab/cm_t3517/cm_t3517.c b/board/compulab/cm_t3517/cm_t3517.c
index 8aae248..38eb641 100644
--- a/board/compulab/cm_t3517/cm_t3517.c
+++ b/board/compulab/cm_t3517/cm_t3517.c
@@ -89,8 +89,8 @@ int board_init(void)
 	/* boot param addr */
 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
 
-#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
-	status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
+	status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
 #endif
 
 	cm_t3517_musb_init();
@@ -115,7 +115,7 @@ int misc_init_r(void)
 	return 0;
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_MMC)
 #define SB_T35_CD_GPIO 144
 #define SB_T35_WP_GPIO 59
 
diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c
index b4f5d40..6437718 100644
--- a/board/compulab/cm_t54/cm_t54.c
+++ b/board/compulab/cm_t54/cm_t54.c
@@ -96,7 +96,7 @@ uint mmc_get_env_part(struct mmc *mmc)
 }
 #endif
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_MMC)
 #define SB_T54_CD_GPIO 228
 #define SB_T54_WP_GPIO 229
 
@@ -181,7 +181,7 @@ int board_eth_init(bd_t *bis)
 }
 #endif
 
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
 static struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
 	.port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
diff --git a/board/compulab/common/common.c b/board/compulab/common/common.c
index b25d9a2..bf2ac7b 100644
--- a/board/compulab/common/common.c
+++ b/board/compulab/common/common.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <asm/bootm.h>
 #include <asm/gpio.h>
+#include <asm/setup.h>
 
 #include "common.h"
 #include "eeprom.h"
diff --git a/board/compulab/common/common.h b/board/compulab/common/common.h
index 8f38b79..759ec31 100644
--- a/board/compulab/common/common.h
+++ b/board/compulab/common/common.h
@@ -9,7 +9,7 @@
 #ifndef _CL_COMMON_
 #define _CL_COMMON_
 
-#include <asm/errno.h>
+#include <linux/errno.h>
 
 void cl_print_pcb_info(void);
 
diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c
index b5f1aa6..bb4c9e9 100644
--- a/board/compulab/common/eeprom.c
+++ b/board/compulab/common/eeprom.c
@@ -11,6 +11,7 @@
 #include <i2c.h>
 #include <eeprom_layout.h>
 #include <eeprom_field.h>
+#include <asm/setup.h>
 #include <linux/kernel.h>
 #include "eeprom.h"
 
diff --git a/board/compulab/common/omap3_smc911x.c b/board/compulab/common/omap3_smc911x.c
index 4561661..858ced8 100644
--- a/board/compulab/common/omap3_smc911x.c
+++ b/board/compulab/common/omap3_smc911x.c
@@ -10,7 +10,7 @@
 #include <netdev.h>
 
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/sys_proto.h>
diff --git a/board/comtrend/ar5387un/Kconfig b/board/comtrend/ar5387un/Kconfig
new file mode 100644
index 0000000..45ab7e2
--- /dev/null
+++ b/board/comtrend/ar5387un/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_COMTREND_AR5387UN
+
+config SYS_BOARD
+	default "ar5387un"
+
+config SYS_VENDOR
+	default "comtrend"
+
+config SYS_CONFIG_NAME
+	default "comtrend_ar5387un"
+
+endif
diff --git a/board/comtrend/ar5387un/MAINTAINERS b/board/comtrend/ar5387un/MAINTAINERS
new file mode 100644
index 0000000..bcaac64
--- /dev/null
+++ b/board/comtrend/ar5387un/MAINTAINERS
@@ -0,0 +1,6 @@
+COMTREND AR-5387UN BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/comtrend/ar-5387un/
+F:	include/configs/comtrend_ar5387un.h
+F:	configs/comtrend_ar5387un_ram_defconfig
diff --git a/board/comtrend/ar5387un/Makefile b/board/comtrend/ar5387un/Makefile
new file mode 100644
index 0000000..9de1cd2
--- /dev/null
+++ b/board/comtrend/ar5387un/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ar-5387un.o
diff --git a/board/comtrend/ar5387un/ar-5387un.c b/board/comtrend/ar5387un/ar-5387un.c
new file mode 100644
index 0000000..d181ca6
--- /dev/null
+++ b/board/comtrend/ar5387un/ar-5387un.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
diff --git a/board/comtrend/ct5361/Kconfig b/board/comtrend/ct5361/Kconfig
new file mode 100644
index 0000000..d77d814
--- /dev/null
+++ b/board/comtrend/ct5361/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_COMTREND_CT5361
+
+config SYS_BOARD
+	default "ct5361"
+
+config SYS_VENDOR
+	default "comtrend"
+
+config SYS_CONFIG_NAME
+	default "comtrend_ct5361"
+
+endif
diff --git a/board/comtrend/ct5361/MAINTAINERS b/board/comtrend/ct5361/MAINTAINERS
new file mode 100644
index 0000000..aea737a
--- /dev/null
+++ b/board/comtrend/ct5361/MAINTAINERS
@@ -0,0 +1,6 @@
+COMTREND CT-5361 BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/comtrend/ct-5361/
+F:	include/configs/comtrend_ct5361.h
+F:	configs/comtrend_ct5361_ram_defconfig
diff --git a/board/comtrend/ct5361/Makefile b/board/comtrend/ct5361/Makefile
new file mode 100644
index 0000000..872e80a
--- /dev/null
+++ b/board/comtrend/ct5361/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ct-5361.o
diff --git a/board/comtrend/ct5361/ct-5361.c b/board/comtrend/ct5361/ct-5361.c
new file mode 100644
index 0000000..d181ca6
--- /dev/null
+++ b/board/comtrend/ct5361/ct-5361.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
diff --git a/board/comtrend/vr3032u/Kconfig b/board/comtrend/vr3032u/Kconfig
new file mode 100644
index 0000000..6f552cf
--- /dev/null
+++ b/board/comtrend/vr3032u/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_COMTREND_VR3032U
+
+config SYS_BOARD
+	default "vr3032u"
+
+config SYS_VENDOR
+	default "comtrend"
+
+config SYS_CONFIG_NAME
+	default "comtrend_vr3032u"
+
+endif
diff --git a/board/comtrend/vr3032u/MAINTAINERS b/board/comtrend/vr3032u/MAINTAINERS
new file mode 100644
index 0000000..833d7da
--- /dev/null
+++ b/board/comtrend/vr3032u/MAINTAINERS
@@ -0,0 +1,6 @@
+COMTREND VR-3032U BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/comtrend/vr-3032u/
+F:	include/configs/comtrend_vr-3032u.h
+F:	configs/comtrend_vr3032u_ram_defconfig
diff --git a/board/comtrend/vr3032u/Makefile b/board/comtrend/vr3032u/Makefile
new file mode 100644
index 0000000..9e62031
--- /dev/null
+++ b/board/comtrend/vr3032u/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += vr-3032u.o
diff --git a/board/comtrend/vr3032u/vr-3032u.c b/board/comtrend/vr3032u/vr-3032u.c
new file mode 100644
index 0000000..d181ca6
--- /dev/null
+++ b/board/comtrend/vr3032u/vr-3032u.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
diff --git a/board/congatec/Kconfig b/board/congatec/Kconfig
index 1dc306e..fb341bf 100644
--- a/board/congatec/Kconfig
+++ b/board/congatec/Kconfig
@@ -12,6 +12,8 @@ choice
 
 config TARGET_CONGA_QEVAL20_QA3_E3845
 	bool "congatec QEVAL 2.0 & conga-QA3/E3845"
+	select BOARD_LATE_INIT
+	imply SCSI
 	help
 	  This is the congatec Qseven 2.0 evaluation carrier board
 	  (conga-QEVAL) equipped with the conga-QA3/E3845-4G SoM.
@@ -22,6 +24,17 @@ config TARGET_CONGA_QEVAL20_QA3_E3845
 	  Note that PCIE_ECAM_BASE is set up by the FSP so the value used
 	  by U-Boot matches that value.
 
+config TARGET_THEADORABLE_X86_CONGA_QA3_E3845
+	bool "theadorable-x86 baseboard & conga-QA3/E3845"
+	help
+	  This is the theadorable-x86 baseboard board equipped with the
+	  conga-QA3/E3845-4G SoM. It contains an Atom E3845 with Ethernet,
+	  micro-SD, USB 2, USB 3, SATA, serial console and HDMI 1.3 video
+	  out. It requires some binary blobs - see README.x86 for details.
+
+	  Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+	  by U-Boot matches that value.
+
 endchoice
 
 source "board/congatec/conga-qeval20-qa3-e3845/Kconfig"
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
index a4a6029..5cb97b4 100644
--- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c
+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
@@ -14,10 +14,10 @@
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>
@@ -71,6 +71,7 @@ static iomux_v3_cfg_t const uart2_pads[] = {
 	IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 };
 
+#ifndef CONFIG_SPL_BUILD
 static iomux_v3_cfg_t const usdhc2_pads[] = {
 	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
@@ -94,6 +95,7 @@ static iomux_v3_cfg_t const usdhc3_pads[] = {
 	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 };
+#endif
 
 static iomux_v3_cfg_t const usdhc4_pads[] = {
 	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
@@ -700,7 +702,7 @@ int board_init(void)
 	else
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
 
-#ifdef CONFIG_CMD_SATA
+#ifdef CONFIG_SATA
 	setup_sata();
 #endif
 
diff --git a/board/congatec/conga-qeval20-qa3-e3845/Kconfig b/board/congatec/conga-qeval20-qa3-e3845/Kconfig
index 9f31238..e1fae73 100644
--- a/board/congatec/conga-qeval20-qa3-e3845/Kconfig
+++ b/board/congatec/conga-qeval20-qa3-e3845/Kconfig
@@ -1,5 +1,3 @@
-if TARGET_CONGA_QEVAL20_QA3_E3845
-
 config SYS_BOARD
 	default "conga-qeval20-qa3-e3845"
 
@@ -10,7 +8,8 @@ config SYS_SOC
 	default "baytrail"
 
 config SYS_CONFIG_NAME
-	default "conga-qeval20-qa3-e3845"
+	default "conga-qeval20-qa3-e3845" if TARGET_CONGA_QEVAL20_QA3_E3845
+	default "theadorable-x86-conga-qa3-e3845" if TARGET_THEADORABLE_X86_CONGA_QA3_E3845
 
 config SYS_TEXT_BASE
 	default 0xfff00000 if !EFI_STUB
@@ -21,8 +20,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR if !EFI_STUB
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select BOARD_EARLY_INIT_F
+	select BOARD_LATE_INIT
+	select SPI_FLASH_STMICRO
+	imply SPI_FLASH_SPANSION
+	imply SPI_FLASH_WINBOND
 
 config PCIE_ECAM_BASE
 	default 0xe0000000
-
-endif
diff --git a/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS b/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS
index 3d7e8e2..cceda4f 100644
--- a/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS
+++ b/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS
@@ -3,6 +3,9 @@ M:	Stefan Roese <sr@denx.de>
 S:	Maintained
 F:	board/congatec/conga-qeval20-qa3-e3845
 F:	include/configs/conga-qeval20-qa3-e3845.h
+F:	include/configs/theadorable-x86-conga-qa3-e3845.h
 F:	configs/conga-qeval20-qa3-e3845_defconfig
 F:	configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
+F:	configs/theadorable-x86-conga-qa3-e3845_defconfig
+F:	configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
 F:	arch/x86/dts/conga-qeval20-qa3-e3845.dts
diff --git a/board/congatec/conga-qeval20-qa3-e3845/README b/board/congatec/conga-qeval20-qa3-e3845/README
new file mode 100644
index 0000000..98ff992
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/README
@@ -0,0 +1,23 @@
+------------------------------
+U-Boot console UART selection:
+------------------------------
+
+The U-Boot port for this congatec board currently supports two different
+configurations (defconfig files). The only difference is the UART that
+is used as the U-Boot console UART. The default defconfig file:
+
+conga-qeval20-qa3-e3845_defconfig
+
+provides this console on the UART0 which is provided via a Winbond
+Super-IO chip connected on the congatec Qseven 2.0 evaluation carrier
+board (conga-QEVAL). This UART is the one provided with a SubD9
+connector on the mainboard (the low one). The 2nd defconfig file:
+
+conga-qeval20-qa3-e3845-internal-uart_defconfig
+
+provides the U-Boot console on the BayTrail internal legacy UART,
+which is routed from the QSeven SoM to the X300 connector on the
+baseboard. Here is called COM2. The baseboard already provides the
+RS232 level shifters. So a TTL-USB UART adapter does not work in
+this case. The signals need to get connected directly to the
+RS232 level signals of the PC UART via some adapter cable.
diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
index 7a5b765..1283eeb 100644
--- a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
+++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
@@ -28,11 +28,6 @@ int board_early_init_f(void)
 	return 0;
 }
 
-int arch_early_init_r(void)
-{
-	return 0;
-}
-
 int board_late_init(void)
 {
 	struct udevice *dev;
diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig
index 3ff64f4..cfa1d50 100644
--- a/board/coreboot/coreboot/Kconfig
+++ b/board/coreboot/coreboot/Kconfig
@@ -12,6 +12,17 @@ config SYS_SOC
 config SYS_TEXT_BASE
 	default 0x01110000
 
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	imply SPI_FLASH_ATMEL
+	imply SPI_FLASH_EON
+	imply SPI_FLASH_GIGADEVICE
+	imply SPI_FLASH_MACRONIX
+	imply SPI_FLASH_SPANSION
+	imply SPI_FLASH_STMICRO
+	imply SPI_FLASH_SST
+	imply SPI_FLASH_WINBOND
+
 comment "coreboot-specific options"
 
 config SYS_CONFIG_NAME
diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile
index 27ebe78..4f2ac89 100644
--- a/board/coreboot/coreboot/Makefile
+++ b/board/coreboot/coreboot/Makefile
@@ -12,4 +12,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	+= coreboot_start.o coreboot.o
+obj-y	+= coreboot_start.o
diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c
deleted file mode 100644
index bb7f778..0000000
--- a/board/coreboot/coreboot/coreboot.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2013 Google, Inc
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <cros_ec.h>
-#include <asm/gpio.h>
-
-int arch_early_init_r(void)
-{
-	return 0;
-}
diff --git a/board/corscience/tricorder/led.c b/board/corscience/tricorder/led.c
index 30f2f50..00ffc00 100644
--- a/board/corscience/tricorder/led.c
+++ b/board/corscience/tricorder/led.c
@@ -23,16 +23,16 @@ void __led_init(led_id_t mask, int state)
 void __led_toggle(led_id_t mask)
 {
 	int toggle_gpio = 0;
-#ifdef STATUS_LED_BIT
-	if (!toggle_gpio && STATUS_LED_BIT & mask)
+#ifdef CONFIG_LED_STATUS0
+	if (!toggle_gpio && CONFIG_LED_STATUS_BIT & mask)
 		toggle_gpio = TRICORDER_STATUS_LED_GREEN;
 #endif
-#ifdef STATUS_LED_BIT1
-	if (!toggle_gpio && STATUS_LED_BIT1 & mask)
+#ifdef CONFIG_LED_STATUS1
+	if (!toggle_gpio && CONFIG_LED_STATUS_BIT1 & mask)
 		toggle_gpio = TRICORDER_STATUS_LED_YELLOW;
 #endif
-#ifdef STATUS_LED_BIT2
-	if (!toggle_gpio && STATUS_LED_BIT2 & mask) {
+#ifdef CONFIG_LED_STATUS2
+	if (!toggle_gpio && CONFIG_LED_STATUS_BIT2 & mask) {
 		uint8_t val;
 		twl4030_i2c_read_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN,
 				    &val);
@@ -51,23 +51,23 @@ void __led_toggle(led_id_t mask)
 
 void __led_set(led_id_t mask, int state)
 {
-#ifdef STATUS_LED_BIT
-	if (STATUS_LED_BIT & mask) {
+#ifdef CONFIG_LED_STATUS0
+	if (CONFIG_LED_STATUS_BIT & mask) {
 		gpio_request(TRICORDER_STATUS_LED_GREEN, "");
 		gpio_direction_output(TRICORDER_STATUS_LED_GREEN, 0);
 		gpio_set_value(TRICORDER_STATUS_LED_GREEN, state);
 	}
 #endif
-#ifdef STATUS_LED_BIT1
-	if (STATUS_LED_BIT1 & mask) {
+#ifdef CONFIG_LED_STATUS1
+	if (CONFIG_LED_STATUS_BIT1 & mask) {
 		gpio_request(TRICORDER_STATUS_LED_YELLOW, "");
 		gpio_direction_output(TRICORDER_STATUS_LED_YELLOW, 0);
 		gpio_set_value(TRICORDER_STATUS_LED_YELLOW, state);
 	}
 #endif
-#ifdef STATUS_LED_BIT2
-	if (STATUS_LED_BIT2 & mask) {
-		if (STATUS_LED_OFF == state)
+#ifdef CONFIG_LED_STATUS2
+	if (CONFIG_LED_STATUS_BIT2 & mask) {
+		if (CONFIG_LED_STATUS_OFF == state)
 			twl4030_i2c_write_u8(TWL4030_CHIP_LED,
 					     TWL4030_LED_LEDEN, 0);
 		else
diff --git a/board/corscience/tricorder/tricorder-eeprom.c b/board/corscience/tricorder/tricorder-eeprom.c
index 340a009..aeacd6a 100644
--- a/board/corscience/tricorder/tricorder-eeprom.c
+++ b/board/corscience/tricorder/tricorder-eeprom.c
@@ -190,13 +190,8 @@ int do_tricorder_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (argc == 3) {
 		ulong dev_addr = simple_strtoul(argv[2], NULL, 16);
 
-		if (strcmp(argv[1], "read") == 0) {
-			int rcode;
-
-			rcode = tricorder_eeprom_read(dev_addr);
-
-			return rcode;
-		}
+		if (strcmp(argv[1], "read") == 0)
+			return tricorder_eeprom_read(dev_addr);
 	} else if (argc == 6 || argc == 7) {
 		ulong dev_addr = simple_strtoul(argv[2], NULL, 16);
 		char *name = argv[3];
@@ -207,14 +202,9 @@ int do_tricorder_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		if (argc == 7)
 			interface = argv[6];
 
-		if (strcmp(argv[1], "write") == 0) {
-			int rcode;
-
-			rcode = tricorder_eeprom_write(dev_addr, name, version,
-					serial, interface);
-
-			return rcode;
-		}
+		if (strcmp(argv[1], "write") == 0)
+			return tricorder_eeprom_write(dev_addr, name, version,
+						      serial, interface);
 	}
 
 	return CMD_RET_USAGE;
diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c
index 0009452..730b8ca 100644
--- a/board/corscience/tricorder/tricorder.c
+++ b/board/corscience/tricorder/tricorder.c
@@ -120,9 +120,9 @@ int misc_init_r(void)
 	print_hwversion(&eeprom);
 
 	twl4030_power_init();
-	status_led_set(0, STATUS_LED_ON);
-	status_led_set(1, STATUS_LED_ON);
-	status_led_set(2, STATUS_LED_ON);
+	status_led_set(0, CONFIG_LED_STATUS_ON);
+	status_led_set(1, CONFIG_LED_STATUS_ON);
+	status_led_set(2, CONFIG_LED_STATUS_ON);
 
 	omap_die_id_display();
 
@@ -140,14 +140,14 @@ void set_muxconf_regs(void)
 	MUX_TRICORDER();
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !(defined(CONFIG_SPL_BUILD))
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
 }
 #endif
 
-#if defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 void board_mmc_power_init(void)
 {
 	twl4030_power_mmc_init(0);
diff --git a/board/cssi/MAINTAINERS b/board/cssi/MAINTAINERS
new file mode 100644
index 0000000..cbf1406
--- /dev/null
+++ b/board/cssi/MAINTAINERS
@@ -0,0 +1,6 @@
+BOARDS from CS Systemes d'Information
+M:	Christophe Leroy <christophe.leroy@c-s.fr>
+S:	Maintained
+F:	board/cssi/
+F:	include/configs/MCR3000.h
+F:	configs/MCR3000_defconfig
diff --git a/board/cssi/MCR3000/Kconfig b/board/cssi/MCR3000/Kconfig
new file mode 100644
index 0000000..ecfd90f
--- /dev/null
+++ b/board/cssi/MCR3000/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MCR3000
+
+config SYS_BOARD
+	default "MCR3000"
+
+config SYS_VENDOR
+	default "cssi"
+
+config SYS_CONFIG_NAME
+	default "MCR3000"
+
+config SYS_TEXT_BASE
+	default 0x04000000
+
+endif
diff --git a/board/cssi/MCR3000/MCR3000.c b/board/cssi/MCR3000/MCR3000.c
new file mode 100644
index 0000000..43c4cb7
--- /dev/null
+++ b/board/cssi/MCR3000/MCR3000.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2010-2017 CS Systemes d'Information
+ * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ *
+ * Board specific routines for the MCR3000 board
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <mpc8xx.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const uint cs1_dram_table_66[] = {
+	/* DRAM - single read. (offset 0 in upm RAM) */
+	0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
+	0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* DRAM - burst read. (offset 8 in upm RAM) */
+	0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
+	0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* DRAM - single write. (offset 18 in upm RAM) */
+	0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
+	0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* DRAM - burst write. (offset 20 in upm RAM) */
+	0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
+	0x00FFFC00, 0x00FFFC04,	0x0FFEF804, 0x0FFDF404,
+	0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* refresh  (offset 30 in upm RAM) */
+	0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
+	0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
+
+	/* init */
+	0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
+
+	/* exception. (offset 3c in upm RAM) */
+	0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+};
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	const char *sync = "receive";
+
+	ft_cpu_setup(blob, bd);
+
+	/* BRG */
+	do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
+			     bd->bi_busfreq, 1);
+
+	/* MAC addr */
+	fdt_fixup_ethernet(blob);
+
+	/* Bus Frequency for CPM */
+	do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
+
+	/* E1 interface - Set data rate */
+	do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
+
+	/* E1 interface - Set channel phase to 0 */
+	do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
+
+	/* E1 interface - rising edge sync pulse transmit */
+	do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
+			 sync, strlen(sync), 1);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	serial_puts("BOARD: MCR3000 CSSI\n");
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	memctl8xx_t __iomem *memctl = &immap->im_memctl;
+
+	printf("UPMA init for SDRAM (CAS latency 2), ");
+	printf("init address 0x%08x, size ", (int)dram_init);
+	/* Configure UPMA for cs1 */
+	upmconfig(UPMA, (uint *)cs1_dram_table_66,
+		  sizeof(cs1_dram_table_66) / sizeof(uint));
+	udelay(10);
+	out_be16(&memctl->memc_mptpr, 0x0200);
+	out_be32(&memctl->memc_mamr, 0x14904000);
+	udelay(10);
+	out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
+	out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
+	udelay(10);
+	out_be32(&memctl->memc_mcr, 0x80002830);
+	out_be32(&memctl->memc_mar, 0x00000088);
+	out_be32(&memctl->memc_mcr, 0x80002038);
+	udelay(200);
+
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+				    SDRAM_MAX_SIZE);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	iop8xx_t __iomem *iop = &immr->im_ioport;
+
+	/* Set port C13 as GPIO (BTN_ACQ_AL) */
+	clrbits_be16(&iop->iop_pcpar, 0x4);
+	clrbits_be16(&iop->iop_pcdir, 0x4);
+
+	/* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
+	if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
+		setenv("bootdelay", "60");
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	/*
+	 * Erase FPGA(s) for reboot
+	 */
+	clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */
+	setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */
+	udelay(1);				/* Wait more than 300ns */
+	setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
+
+	return 0;
+}
diff --git a/board/cssi/MCR3000/Makefile b/board/cssi/MCR3000/Makefile
new file mode 100644
index 0000000..401d5aa
--- /dev/null
+++ b/board/cssi/MCR3000/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2010-2017 CS Systemes d'Information
+# Christophe Leroy <christophe.leroy@c-s.fr>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+#
+
+obj-y += MCR3000.o
+obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/board/cssi/MCR3000/nand.c b/board/cssi/MCR3000/nand.c
new file mode 100644
index 0000000..8e5b0d0
--- /dev/null
+++ b/board/cssi/MCR3000/nand.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2010-2017 CS Systemes d'Information
+ * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+
+#define BIT_CLE			((unsigned short)0x0800)
+#define BIT_ALE			((unsigned short)0x0400)
+#define BIT_NCE			((unsigned short)0x1000)
+
+static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this	= mtdinfo->priv;
+	immap_t __iomem *immr	= (immap_t __iomem *)CONFIG_SYS_IMMR;
+	unsigned short pddat	= 0;
+
+	/* The hardware control change */
+	if (ctrl & NAND_CTRL_CHANGE) {
+		pddat = in_be16(&immr->im_ioport.iop_pddat);
+
+		/* Clearing ALE and CLE */
+		pddat &= ~(BIT_CLE | BIT_ALE);
+
+		/* Driving NCE pin */
+		if (ctrl & NAND_NCE)
+			pddat &= ~BIT_NCE;
+		else
+			pddat |= BIT_NCE;
+
+		/* Driving CLE and ALE pin */
+		if (ctrl & NAND_CLE)
+			pddat |= BIT_CLE;
+		if (ctrl & NAND_ALE)
+			pddat |= BIT_ALE;
+
+		out_be16(&immr->im_ioport.iop_pddat, pddat);
+	}
+
+	/* Writing the command */
+	if (cmd != NAND_CMD_NONE)
+		out_8(this->IO_ADDR_W, cmd);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	immap_t __iomem *immr	= (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	/* Set GPIO Port */
+	setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00);
+	clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00);
+	clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000);
+
+	nand->chip_delay	= 60;
+	nand->ecc.mode		= NAND_ECC_SOFT;
+	nand->cmd_ctrl		= nand_hwcontrol;
+
+	return 0;
+}
diff --git a/board/cssi/MCR3000/u-boot.lds b/board/cssi/MCR3000/u-boot.lds
new file mode 100644
index 0000000..cd042ca
--- /dev/null
+++ b/board/cssi/MCR3000/u-boot.lds
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2010-2017 CS Systemes d'Information
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ *
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+	/* Read-only sections, merged into text segment: */
+	. = + SIZEOF_HEADERS;
+	.text          :
+	{
+		arch/powerpc/cpu/mpc8xx/start.o	(.text)
+		arch/powerpc/cpu/mpc8xx/start.o	(.text*)
+		arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
+		arch/powerpc/cpu/mpc8xx/built-in.o	(.text*)
+		arch/powerpc/lib/built-in.o		(.text*)
+		board/cssi/MCR3000/built-in.o	(.text*)
+		disk/built-in.o			(.text*)
+		drivers/net/built-in.o		(.text*)
+
+		*(.text)
+	}
+	_etext = .;
+	PROVIDE (etext = .);
+	.rodata    :
+	{
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	/* Read-write section, merged into data segment: */
+	. = (. + 0x0FFF) & 0xFFFFF000;
+	_erotext = .;
+	PROVIDE (erotext = .);
+	.reloc   :
+	{
+		_GOT2_TABLE_ = .;
+		KEEP(*(.got2))
+		KEEP(*(.got))
+		_FIXUP_TABLE_ = .;
+		KEEP(*(.fixup))
+	}
+	__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+	__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+	.data    :
+	{
+		*(.data*)
+		*(.sdata*)
+	}
+	_edata  =  .;
+	PROVIDE (edata = .);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = .;
+	__start___ex_table = .;
+	__ex_table : { *(__ex_table) }
+	__stop___ex_table = .;
+
+	. = ALIGN(4096);
+	__init_begin = .;
+	.text.init : { *(.text.init) }
+	.data.init : { *(.data.init) }
+	. = ALIGN(4096);
+	__init_end = .;
+
+	__bss_start = .;
+	.bss (NOLOAD)       :
+	{
+		*(.bss*)
+		*(.sbss*)
+		*(COMMON)
+		. = ALIGN(4);
+	}
+	__bss_end = . ;
+	PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/board/davedenx/aria/Kconfig b/board/davedenx/aria/Kconfig
deleted file mode 100644
index 54a86b9..0000000
--- a/board/davedenx/aria/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_ARIA
-
-config SYS_BOARD
-	default "aria"
-
-config SYS_VENDOR
-	default "davedenx"
-
-config SYS_CONFIG_NAME
-	default "aria"
-
-endif
diff --git a/board/davedenx/aria/MAINTAINERS b/board/davedenx/aria/MAINTAINERS
deleted file mode 100644
index a6152c9..0000000
--- a/board/davedenx/aria/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ARIA BOARD
-M:	Wolfgang Denk <wd@denx.de>
-S:	Maintained
-F:	board/davedenx/aria/
-F:	include/configs/aria.h
-F:	configs/aria_defconfig
diff --git a/board/davedenx/aria/Makefile b/board/davedenx/aria/Makefile
deleted file mode 100644
index dd38b7f..0000000
--- a/board/davedenx/aria/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= aria.o
diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c
deleted file mode 100644
index 1b6c40f..0000000
--- a/board/davedenx/aria/aria.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
- * (C) Copyright 2009 Dave Srl www.dave.eu
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mpc512x.h>
-#include <fdt_support.h>
-#ifdef CONFIG_MISC_INIT_R
-#include <i2c.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-phys_size_t initdram (int board_type)
-{
-	return fixed_sdram(NULL, NULL, 0);
-}
-
-int misc_init_r(void)
-{
-	u32 tmp;
-
-	/* we use I2C-2 for on-board eeprom */
-	i2c_set_bus_num(2);
-
-	tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE);
-	printf("FPGA:  %u-%u.%u.%u\n",
-		(tmp & 0xFF000000) >> 24,
-		(tmp & 0x00FF0000) >> 16,
-		(tmp & 0x0000FF00) >>  8,
-		 tmp & 0x000000FF
-	);
-
-	return 0;
-}
-
-static  iopin_t ioregs_init[] = {
-	/*
-	 * FEC
-	 */
-
-	/* FEC on PSCx_x*/
-	{
-		offsetof(struct ioctrl512x, io_control_psc0_0), 5, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	{
-		offsetof(struct ioctrl512x, io_control_psc1_0), 10, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	{
-		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-
-	/*
-	 * DIU
-	 */
-	/* FUNC2=DIU CLK */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIU_HSYNC */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/*
-	 * On board SRAM
-	 */
-	/* FUNC2=/LPC CS6 */
-	{
-		offsetof(struct ioctrl512x, io_control_j1850_rx), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-};
-
-int checkboard (void)
-{
-	puts("Board: ARIA\n");
-
-	/* initialize function mux & slew rate IO inter alia on IO Pins  */
-
-	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/davinci/da8xxevm/Kconfig b/board/davinci/da8xxevm/Kconfig
index 7d0de1d..0935abf 100644
--- a/board/davinci/da8xxevm/Kconfig
+++ b/board/davinci/da8xxevm/Kconfig
@@ -22,4 +22,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "omapl138_lcdk"
 
+source "board/ti/common/Kconfig"
+
 endif
diff --git a/board/davinci/da8xxevm/README.da850 b/board/davinci/da8xxevm/README.da850
index 313a1ef..519267e 100644
--- a/board/davinci/da8xxevm/README.da850
+++ b/board/davinci/da8xxevm/README.da850
@@ -47,6 +47,70 @@ U-Boot > sf erase 0 +320000
 U-Boot > tftp u-boot.ais
 U-Boot > sf write c0700000 0 $filesize
 
+Flashing the images to NAND
+===========================
+The AIS image can be written to NAND using the u-boot "nand" commands.
+
+Example:
+
+OMAPL138_LCDK requires the AIS image to be written to the second block of
+the NAND flash.
+
+From the "nand info" command we see that the second block would start at
+offset 0x20000:
+
+  U-Boot > nand info
+      sector size      128 KiB (0x20000)
+      Page size       2048 b
+
+From the tftp command we see that we need to copy 0x74908 bytes from
+memory address 0xc0700000 (0x75000 if we align a page of 2048):
+
+  U-Boot > tftp u-boot.ais
+      Load address: 0xc0700000
+      Bytes transferred = 477448 (74908 hex)
+
+The commands to write the image from memory to NAND would be:
+
+  U-Boot > nand erase 0x20000 0x75000
+  U-Boot > nand write 0xc0700000 0x20000 0x75000
+
+Alternatively, MTD partitions may be defined. Using "mtdparts" to
+conveniently have a bootloader partition starting at the second block
+(offset 0x20000):
+
+  setenv mtdids nand0=davinci_nand.0
+  setenv mtdparts mtdparts=davinci_nand.0:128k(bootenv),2m(bootloader)
+
+In this case the commands would be simplified to:
+
+  U-Boot > tftp u-boot.ais
+  U-Boot > nand erase.part bootloader
+  U-Boot > nand write 0xc0700000 bootloader
+
+Flashing the images to MMC
+==========================
+If the boot pins are set to boot from mmc, the RBL will try to load the
+next boot stage form the first couple of sectors of an external mmc card.
+As sector 0 is usually used for storing the partition information, the
+AIS image should be written at least after the first sector, but before the
+first partition begins. (e.g: make sure to leave at least 500KB of unallocated
+space at the start of the mmc when creating the partitions)
+
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR is used by SPL, and should
+point to the sector were the u-boot image is located. (eg. After SPL)
+
+There are 2 ways to copy the AIS image to the mmc card:
+
+ 1 - Using the TI tool "uflash"
+	$ uflash -d /dev/mmcblk0  -b ./u-boot.ais -p OMAPL138  -vv
+
+ 2 - using the "dd" command
+	$ dd if=u-boot.ais of=/dev/mmcblk0 seek=117 bs=512 conv=fsync
+
+uflash writes the AIS image at offset 117. For compatibility with uflash,
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR is set to take into account this
+offset, and the dd command is adjusted accordingly.
 
 Recovery
 ========
diff --git a/board/davinci/da8xxevm/README.omapl138-lcdk b/board/davinci/da8xxevm/README.omapl138-lcdk
deleted file mode 100644
index ea0c53d..0000000
--- a/board/davinci/da8xxevm/README.omapl138-lcdk
+++ /dev/null
@@ -1,28 +0,0 @@
-Summary
-=======
-This README assumes you have read README.da850.  It contains some additional
-information specific to building the omapl138-lcdk.  The AIS file as generated
-by the build is, currently, not useable due to differences in the flash
-available on this board, as compared to the da850evm boards.
-
-Flash Differences
-=================
-Refer to the discussion in [1] for more detail - basically the da850evm uses
-SPI flash whereas the lcdk uses NAND flash to store the bootloader, and
-the support isn't there in the SPL code.
-
-It should be possible to add the support in the SPL code should someone be
-sufficiently motivated.
-
-Using the built image
-=====================
-The output image to use is u-boot.bin.  This needs to be converted to an
-AIS file as described in [1] and then flashed using the utitilty linked to
-there and also described in README.da850.  You _may_ be able to write using
-u-boot itself, but the commands in README.da850 won't work as they write to
-SPI rather than NAND.
-
-Links
-=====
-[1]
- http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/386829
\ No newline at end of file
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index b82385a..11ea52f 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -21,10 +21,11 @@
 #include <asm/arch/pinmux_defs.h>
 #include <asm/io.h>
 #include <asm/arch/davinci_misc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <hwconfig.h>
+#include <asm/mach-types.h>
 
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
 #include <mmc.h>
 #include <asm/arch/sdmmc_defs.h>
 #endif
@@ -164,7 +165,7 @@ int misc_init_r(void)
 		    memcmp(env_enetaddr, buff, 6))
 			printf("Warning: MAC address in SPI flash don't match "
 					"with the MAC address in the environment\n");
-			printf("Default using MAC address from environment\n");
+		printf("Default using MAC address from environment\n");
 	}
 #endif
 	uint8_t enetaddr[8];
@@ -190,14 +191,14 @@ int misc_init_r(void)
 		if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
 			printf("Warning: MAC address in EEPROM don't match "
 					"with the MAC address in the environment\n");
-			printf("Default using MAC address from environment\n");
+		printf("Default using MAC address from environment\n");
 	}
 
 #endif
 	return 0;
 }
 
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
 static struct davinci_mmc mmc_sd0 = {
 	.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
 	.host_caps = MMC_MODE_4BIT,     /* DA850 supports only 4-bit SD/MMC */
@@ -219,7 +220,7 @@ static const struct pinmux_config gpio_pins[] = {
 	/* GP0[11] is required for NOR to work on Rev 3 EVMs */
 	{ pinmux(0), 8, 4 },	/* GP0[11] */
 #endif
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
 	/* GP0[11] is required for SD to work on Rev 3 EVMs */
 	{ pinmux(0),  8, 4 },	/* GP0[11] */
 #endif
@@ -250,7 +251,7 @@ const struct pinmux_resource pinmuxes[] = {
 	PINMUX_ITEM(emifa_pins_nor),
 #endif
 	PINMUX_ITEM(gpio_pins),
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
 	PINMUX_ITEM(mmc0_pins),
 #endif
 };
@@ -263,7 +264,7 @@ const struct lpsc_resource lpsc[] = {
 	{ DAVINCI_LPSC_EMAC },	/* image download */
 	{ DAVINCI_LPSC_UART2 },	/* console */
 	{ DAVINCI_LPSC_GPIO },
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
 	{ DAVINCI_LPSC_MMC_SD },
 #endif
 };
@@ -323,9 +324,7 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-#ifndef CONFIG_USE_IRQ
 	irq_init();
-#endif
 
 #ifdef CONFIG_NAND_DAVINCI
 	/*
@@ -368,7 +367,7 @@ int board_init(void)
 	writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR);
 #endif
 
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
 	/* Set the GPIO direction as output */
 	clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
 
diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c
index f69aeb6..52bb736 100644
--- a/board/davinci/da8xxevm/omapl138_lcdk.c
+++ b/board/davinci/da8xxevm/omapl138_lcdk.c
@@ -18,9 +18,10 @@
 #include <asm/arch/hardware.h>
 #include <asm/ti-common/davinci_nand.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
+#include <asm/mach-types.h>
 #include <asm/arch/davinci_misc.h>
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
 #include <mmc.h>
 #include <asm/arch/sdmmc_defs.h>
 #endif
@@ -29,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define pinmux(x)	(&davinci_syscfg_regs->pinmux[x])
 
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
 /* MMC0 pin muxer settings */
 const struct pinmux_config mmc0_pins[] = {
 	/* GP0[11] is required for SD to work on Rev 3 EVMs */
@@ -130,7 +131,7 @@ const struct lpsc_resource lpsc[] = {
 	{ DAVINCI_LPSC_EMAC },	/* image download */
 	{ DAVINCI_LPSC_UART2 },	/* console */
 	{ DAVINCI_LPSC_GPIO },
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
 	{ DAVINCI_LPSC_MMC_SD },
 #endif
 };
@@ -171,9 +172,7 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-#ifndef CONFIG_USE_IRQ
 	irq_init();
-#endif
 
 	/* arch number of the board */
 	gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;
@@ -210,7 +209,7 @@ int board_init(void)
 #endif
 
 
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
 	if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
 		return 1;
 #endif
@@ -333,15 +332,17 @@ int misc_init_r(void)
 			get_mac_addr(addr);
 		}
 
-		if (is_multicast_ethaddr(addr) || is_zero_ethaddr(addr)) {
+		if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) {
+			sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x",
+				addr[0], addr[1], addr[2], addr[3], addr[4],
+				addr[5]);
+
+			setenv("ethaddr", (char *)tmp);
+		} else {
 			printf("Invalid MAC address read.\n");
-			return -EINVAL;
 		}
-		sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x", addr[0],
-				addr[1], addr[2], addr[3], addr[4], addr[5]);
-
-		setenv("ethaddr", (char *)tmp);
 	}
+
 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
 	/* Select RMII fucntion through the expander */
 	if (rmii_hw_init())
@@ -353,7 +354,7 @@ int misc_init_r(void)
 	return 0;
 }
 
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
 static struct davinci_mmc mmc_sd0 = {
 	.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
 	.host_caps = MMC_MODE_4BIT,     /* DA850 supports only 4-bit SD/MMC */
diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
index ab4f50c..85a6be9 100644
--- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds
@@ -34,6 +34,9 @@ SECTIONS
 	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 
 	. = ALIGN(4);
+	.u_boot_list : { KEEP(*(SORT(.u_boot_list*))); } >.sram
+
+	. = ALIGN(4);
 	.rel.dyn : {
 		__rel_dyn_start = .;
 		*(.rel*)
diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
index 66804d7..2a187f1 100644
--- a/board/davinci/ea20/ea20.c
+++ b/board/davinci/ea20/ea20.c
@@ -18,6 +18,7 @@
 #include <i2c.h>
 #include <net.h>
 #include <netdev.h>
+#include <asm/mach-types.h>
 #include <asm/arch/hardware.h>
 #include <asm/ti-common/davinci_nand.h>
 #include <asm/arch/emac_defs.h>
@@ -203,9 +204,7 @@ int board_early_init_f(void)
 	/* Set LCD_B_PWR low to power down LCD Backlight*/
 	gpio_direction_output(102, 0);
 
-#ifndef CONFIG_USE_IRQ
 	irq_init();
-#endif
 
 	/*
 	 * NAND CS setup - cycle counts based on da850evm NAND timings in the
diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c
index 75e6f0e..81285d7 100644
--- a/board/dbau1x00/dbau1x00.c
+++ b/board/dbau1x00/dbau1x00.c
@@ -11,11 +11,15 @@
 #include <asm/mipsregs.h>
 #include <asm/io.h>
 
-phys_size_t initdram(int board_type)
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
 {
 	/* Sdram is setup by assembler code */
 	/* If memory could be changed, we should return the true value here */
-	return MEM_SIZE*1024*1024;
+	gd->ram_size = MEM_SIZE * 1024 * 1024;
+
+	return 0;
 }
 
 #define BCSR_PCMCIA_PC0DRVEN		0x0010
diff --git a/board/denx/m28evk/Kconfig b/board/denx/m28evk/Kconfig
deleted file mode 100644
index dd4dc4d..0000000
--- a/board/denx/m28evk/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_M28EVK
-
-config SYS_BOARD
-	default "m28evk"
-
-config SYS_VENDOR
-	default "denx"
-
-config SYS_SOC
-	default "mxs"
-
-config SYS_CONFIG_NAME
-	default "m28evk"
-
-endif
diff --git a/board/denx/m28evk/MAINTAINERS b/board/denx/m28evk/MAINTAINERS
deleted file mode 100644
index b0535a9..0000000
--- a/board/denx/m28evk/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-M28EVK BOARD
-M:	Marek Vasut <marek.vasut@gmail.com>
-S:	Maintained
-F:	board/denx/m28evk/
-F:	include/configs/m28evk.h
-F:	configs/m28evk_defconfig
diff --git a/board/denx/m28evk/README b/board/denx/m28evk/README
deleted file mode 100644
index cb3ae20..0000000
--- a/board/denx/m28evk/README
+++ /dev/null
@@ -1,13 +0,0 @@
-DENX M28EVK
-===========
-
-Files of the M28/M28EVK port
-----------------------------
-
-arch/arm/cpu/arm926ejs/mxs/	- The CPU support code for the Freescale i.MX28
-arch/arm/include/asm/arch-mxs/	- Header files for the Freescale i.MX28
-board/denx/m28evk/		- M28EVK board specific files
-include/configs/m28evk.h	- M28EVK configuration file
-
-Follow the instructions from doc/README.mxs to generate a bootable SD card or to
-boot from NAND flash.
diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c
deleted file mode 100644
index 33d38cf..0000000
--- a/board/denx/m28evk/m28evk.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * DENX M28 module
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux-mx28.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <linux/mii.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <errno.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Functions
- */
-int board_early_init_f(void)
-{
-	/* IO0 clock at 480MHz */
-	mxs_set_ioclk(MXC_IOCLK0, 480000);
-	/* IO1 clock at 480MHz */
-	mxs_set_ioclk(MXC_IOCLK1, 480000);
-
-	/* SSP0 clock at 96MHz */
-	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
-	/* SSP2 clock at 160MHz */
-	mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
-
-#ifdef	CONFIG_CMD_USB
-	mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
-	mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 |
-			MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
-	gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0);
-
-	mxs_iomux_setup_pad(MX28_PAD_AUART3_RX__GPIO_3_12 |
-			MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
-	gpio_direction_output(MX28_PAD_AUART3_RX__GPIO_3_12, 0);
-#endif
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* Adress of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	return mxs_dram_init();
-}
-
-#ifdef	CONFIG_CMD_MMC
-static int m28_mmc_wp(int id)
-{
-	if (id != 0) {
-		printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
-		return 1;
-	}
-
-	return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10);
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	/* Configure WP as input. */
-	gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
-	/* Turn on the power to the card. */
-	gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
-
-	return mxsmmc_initialize(bis, 0, m28_mmc_wp, NULL);
-}
-#endif
-
-#ifdef	CONFIG_CMD_NET
-
-#define	MII_OPMODE_STRAP_OVERRIDE	0x16
-#define	MII_PHY_CTRL1			0x1e
-#define	MII_PHY_CTRL2			0x1f
-
-int fecmxc_mii_postcall(int phy)
-{
-#if	defined(CONFIG_DENX_M28_V11) || defined(CONFIG_DENX_M28_V10)
-	/* KZ8031 PHY on old boards. */
-	const uint32_t freq = 0x0080;
-#else
-	/* KZ8021 PHY on new boards. */
-	const uint32_t freq = 0x0000;
-#endif
-
-	miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
-	miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
-	if (phy == 3)
-		miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8100 | freq);
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	struct mxs_clkctrl_regs *clkctrl_regs =
-		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
-	struct eth_device *dev;
-	int ret;
-
-	ret = cpu_eth_init(bis);
-	if (ret)
-		return ret;
-
-	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
-		CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
-		CLKCTRL_ENET_TIME_SEL_RMII_CLK);
-
-#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
-	/* Reset the new PHY */
-	gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0);
-	udelay(10000);
-	gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1);
-	udelay(10000);
-#endif
-
-	ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
-	if (ret) {
-		printf("FEC MXS: Unable to init FEC0\n");
-		return ret;
-	}
-
-	ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
-	if (ret) {
-		printf("FEC MXS: Unable to init FEC1\n");
-		return ret;
-	}
-
-	dev = eth_get_dev_by_name("FEC0");
-	if (!dev) {
-		printf("FEC MXS: Unable to get FEC0 device entry\n");
-		return -EINVAL;
-	}
-
-	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
-	if (ret) {
-		printf("FEC MXS: Unable to register FEC0 mii postcall\n");
-		return ret;
-	}
-
-	dev = eth_get_dev_by_name("FEC1");
-	if (!dev) {
-		printf("FEC MXS: Unable to get FEC1 device entry\n");
-		return -EINVAL;
-	}
-
-	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
-	if (ret) {
-		printf("FEC MXS: Unable to register FEC1 mii postcall\n");
-		return ret;
-	}
-
-	return ret;
-}
-
-#endif
diff --git a/board/denx/m28evk/spl_boot.c b/board/denx/m28evk/spl_boot.c
deleted file mode 100644
index 5a1010e..0000000
--- a/board/denx/m28evk/spl_boot.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * DENX M28 Boot setup
- *
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <asm/arch/iomux-mx28.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-
-#define	MUX_CONFIG_LED	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define	MUX_CONFIG_LCD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define	MUX_CONFIG_TSC	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
-#define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
-#define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
-#define	MUX_CONFIG_GPMI	(MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
-#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
-
-const iomux_cfg_t iomux_setup[] = {
-	/* LED */
-	MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED,
-
-	/* framebuffer */
-	MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
-
-	/* UART1 */
-#ifdef	CONFIG_DENX_M28_V10
-	MX28_PAD_AUART0_CTS__DUART_RX,
-	MX28_PAD_AUART0_RTS__DUART_TX,
-#else
-	MX28_PAD_PWM0__DUART_RX,
-	MX28_PAD_PWM1__DUART_TX,
-#endif
-	MX28_PAD_AUART0_TX__DUART_RTS,
-	MX28_PAD_AUART0_RX__DUART_CTS,
-
-	/* UART2 */
-	MX28_PAD_AUART1_RX__AUART1_RX,
-	MX28_PAD_AUART1_TX__AUART1_TX,
-	MX28_PAD_AUART1_RTS__AUART1_RTS,
-	MX28_PAD_AUART1_CTS__AUART1_CTS,
-
-	/* CAN */
-	MX28_PAD_GPMI_RDY2__CAN0_TX,
-	MX28_PAD_GPMI_RDY3__CAN0_RX,
-
-	/* TSC2007 */
-	MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_TSC,
-
-	/* MMC0 */
-	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
-	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
-	MX28_PAD_SSP0_SCK__SSP0_SCK |
-		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
-	MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0 |
-		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),	/* Power */
-	MX28_PAD_AUART2_CTS__GPIO_3_10,	/* WP */
-
-	/* GPMI NAND */
-	MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_RDN__GPMI_RDN |
-		(MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP),
-	MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
-	MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
-
-	/* FEC Ethernet */
-	MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
-	MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
-
-	MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET,
-	MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET,
-#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10)
-	MX28_PAD_AUART2_RTS__GPIO_3_11,	/* PHY reset */
-#endif
-
-	/* I2C */
-	MX28_PAD_I2C0_SCL__I2C0_SCL,
-	MX28_PAD_I2C0_SDA__I2C0_SDA,
-
-	/* EMI */
-	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
-
-	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
-	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
-
-	/* SPI2 (for flash) */
-	MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
-	MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
-	MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
-	MX28_PAD_SSP2_SS0__SSP2_D3 |
-		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
-};
-
-void board_init_ll(const uint32_t arg, const uint32_t *resptr)
-{
-	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
-}
diff --git a/board/denx/m53evk/Kconfig b/board/denx/m53evk/Kconfig
deleted file mode 100644
index 0696ad7..0000000
--- a/board/denx/m53evk/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_M53EVK
-
-config SYS_BOARD
-	default "m53evk"
-
-config SYS_VENDOR
-	default "denx"
-
-config SYS_SOC
-	default "mx5"
-
-config SYS_CONFIG_NAME
-	default "m53evk"
-
-endif
diff --git a/board/denx/m53evk/MAINTAINERS b/board/denx/m53evk/MAINTAINERS
deleted file mode 100644
index 5d8c764..0000000
--- a/board/denx/m53evk/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-M53EVK BOARD
-M:	Marek Vasut <marek.vasut@gmail.com>
-S:	Maintained
-F:	board/denx/m53evk/
-F:	include/configs/m53evk.h
-F:	configs/m53evk_defconfig
diff --git a/board/denx/m53evk/Makefile b/board/denx/m53evk/Makefile
deleted file mode 100644
index 19b8977..0000000
--- a/board/denx/m53evk/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# DENX M53EVK
-# Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= m53evk.o
diff --git a/board/denx/m53evk/imximage.cfg b/board/denx/m53evk/imximage.cfg
deleted file mode 100644
index 4cd002c..0000000
--- a/board/denx/m53evk/imximage.cfg
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * DENX M53 DRAM init values
- * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Refer docs/README.imxmage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-#include <asm/imx-common/imximage.cfg>
-
-/* image version */
-IMAGE_VERSION	2
-
-
-/* Boot Offset 0x400, valid for both SD and NAND boot. */
-BOOT_OFFSET	FLASH_OFFSET_STANDARD
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *	Addr-type register length (1,2 or 4 bytes)
- *	Address	  absolute address of the register
- *	value	  value to be stored in the register
- */
-DATA 4 0x53fa86f4 0x00000000	 /* GRP_DDRMODE_CTL */
-DATA 4 0x53fa8714 0x00000000	 /* GRP_DDRMODE */
-DATA 4 0x53fa86fc 0x00000000	 /* GRP_DDRPKE */
-DATA 4 0x53fa8724 0x04000000	 /* GRP_DDR_TYPE */
-
-DATA 4 0x53fa872c 0x00300000	 /* GRP_B3DS */
-DATA 4 0x53fa8554 0x00300000	 /* DRAM_DQM3 */
-DATA 4 0x53fa8558 0x00300040	 /* DRAM_SDQS3 */
-
-DATA 4 0x53fa8728 0x00300000	 /* GRP_B2DS */
-DATA 4 0x53fa8560 0x00300000	 /* DRAM_DQM2 */
-DATA 4 0x53fa8568 0x00300040	 /* DRAM_SDQS2 */
-
-DATA 4 0x53fa871c 0x00300000	 /* GRP_B1DS */
-DATA 4 0x53fa8594 0x00300000	 /* DRAM_DQM1 */
-DATA 4 0x53fa8590 0x00300040	 /* DRAM_SDQS1 */
-
-DATA 4 0x53fa8718 0x00300000	 /* GRP_B0DS */
-DATA 4 0x53fa8584 0x00300000	 /* DRAM_DQM0 */
-DATA 4 0x53fa857c 0x00300040	 /* DRAM_SDQS0 */
-
-DATA 4 0x53fa8578 0x00300000	 /* DRAM_SDCLK_0 */
-DATA 4 0x53fa8570 0x00300000	 /* DRAM_SDCLK_1 */
-
-DATA 4 0x53fa8574 0x00300000	 /* DRAM_CAS */
-DATA 4 0x53fa8588 0x00300000	 /* DRAM_RAS */
-DATA 4 0x53fa86f0 0x00300000	 /* GRP_ADDDS */
-DATA 4 0x53fa8720 0x00300000	 /* GRP_CTLDS */
-
-DATA 4 0x53fa8564 0x00300040	 /* DRAM_SDODT1 */
-DATA 4 0x53fa8580 0x00300040	 /* DRAM_SDODT0 */
-
-/* ESDCTL */
-DATA 4 0x63fd9088 0x32383535
-DATA 4 0x63fd9090 0x40383538
-DATA 4 0x63fd907c 0x0136014d
-DATA 4 0x63fd9080 0x01510141
-
-DATA 4 0x63fd9018 0x00011740
-DATA 4 0x63fd9000 0xc3190000
-DATA 4 0x63fd900c 0x555952e3
-DATA 4 0x63fd9010 0xb68e8b63
-DATA 4 0x63fd9014 0x01ff00db
-DATA 4 0x63fd902c 0x000026d2
-DATA 4 0x63fd9030 0x009f0e21
-DATA 4 0x63fd9008 0x12273030
-DATA 4 0x63fd9004 0x0002002d
-DATA 4 0x63fd901c 0x00008032
-DATA 4 0x63fd901c 0x00008033
-DATA 4 0x63fd901c 0x00028031
-DATA 4 0x63fd901c 0x092080b0
-DATA 4 0x63fd901c 0x04008040
-DATA 4 0x63fd901c 0x0000803a
-DATA 4 0x63fd901c 0x0000803b
-DATA 4 0x63fd901c 0x00028039
-DATA 4 0x63fd901c 0x09208138
-DATA 4 0x63fd901c 0x04008048
-DATA 4 0x63fd9020 0x00001800
-DATA 4 0x63fd9040 0x04b80003
-DATA 4 0x63fd9058 0x00022227
-DATA 4 0x63fd901c 0x00000000
diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c
deleted file mode 100644
index 934f009..0000000
--- a/board/denx/m53evk/m53evk.c
+++ /dev/null
@@ -1,402 +0,0 @@
-/*
- * DENX M53 module
- *
- * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/iomux-mx53.h>
-#include <asm/imx-common/mx5_video.h>
-#include <asm/spl.h>
-#include <asm/errno.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <mmc.h>
-#include <spl.h>
-#include <fsl_esdhc.h>
-#include <asm/gpio.h>
-#include <usb/ehci-ci.h>
-#include <linux/fb.h>
-#include <ipu_pixfmt.h>
-
-/* Special MXCFB sync flags are here. */
-#include "../drivers/video/mxcfb.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static uint32_t mx53_dram_size[2];
-
-phys_size_t get_effective_memsize(void)
-{
-	/*
-	 * WARNING: We must override get_effective_memsize() function here
-	 * to report only the size of the first DRAM bank. This is to make
-	 * U-Boot relocator place U-Boot into valid memory, that is, at the
-	 * end of the first DRAM bank. If we did not override this function
-	 * like so, U-Boot would be placed at the address of the first DRAM
-	 * bank + total DRAM size - sizeof(uboot), which in the setup where
-	 * each DRAM bank contains 512MiB of DRAM would result in placing
-	 * U-Boot into invalid memory area close to the end of the first
-	 * DRAM bank.
-	 */
-	return mx53_dram_size[0];
-}
-
-int dram_init(void)
-{
-	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
-	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
-
-	gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
-
-	return 0;
-}
-
-void dram_init_banksize(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = mx53_dram_size[0];
-
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[1].size = mx53_dram_size[1];
-}
-
-static void setup_iomux_uart(void)
-{
-	static const iomux_v3_cfg_t uart_pads[] = {
-		MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
-		MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
-	};
-
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-}
-
-#ifdef CONFIG_USB_EHCI_MX5
-int board_ehci_hcd_init(int port)
-{
-	if (port == 0) {
-		/* USB OTG PWRON */
-		imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
-					PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
-		gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
-
-		/* USB OTG Over Current */
-		imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
-	} else if (port == 1) {
-		/* USB Host PWRON */
-		imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
-					PAD_CTL_PKE | PAD_CTL_DSE_HIGH));
-		gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
-
-		/* USB Host Over Current */
-		imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
-	}
-
-	return 0;
-}
-#endif
-
-static void setup_iomux_fec(void)
-{
-	static const iomux_v3_cfg_t fec_pads[] = {
-		/* MDIO pads */
-		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
-			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
-		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
-
-		/* FEC 0 pads */
-		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
-
-		/* FEC 1 pads */
-		NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
-				PAD_CTL_HYS | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-}
-
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg = {
-	MMC_SDHC1_BASE_ADDR,
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
-	gpio_direction_input(IMX_GPIO_NR(1, 1));
-
-	return !gpio_get_value(IMX_GPIO_NR(1, 1));
-}
-
-#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
-				 PAD_CTL_PUS_100K_UP)
-#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
-				 PAD_CTL_DSE_HIGH)
-
-int board_mmc_init(bd_t *bis)
-{
-	static const iomux_v3_cfg_t sd1_pads[] = {
-		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
-		MX53_PAD_EIM_DA13__GPIO3_13,
-
-		MX53_PAD_EIM_EB3__GPIO2_31, /* SD power */
-	};
-
-	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
-	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
-
-	/* GPIO 2_31 is SD power */
-	gpio_direction_output(IMX_GPIO_NR(2, 31), 0);
-
-	return fsl_esdhc_initialize(bis, &esdhc_cfg);
-}
-#endif
-
-#ifdef CONFIG_VIDEO
-static struct fb_videomode const ampire_wvga = {
-	.name		= "Ampire",
-	.refresh	= 60,
-	.xres		= 800,
-	.yres		= 480,
-	.pixclock	= 29851, /* picosecond (33.5 MHz) */
-	.left_margin	= 89,
-	.right_margin	= 164,
-	.upper_margin	= 23,
-	.lower_margin	= 10,
-	.hsync_len	= 10,
-	.vsync_len	= 10,
-	.sync		= FB_SYNC_CLK_LAT_FALL,
-};
-
-int board_video_skip(void)
-{
-	int ret;
-	ret = ipuv3_fb_init(&ampire_wvga, 1, IPU_PIX_FMT_RGB666);
-	if (ret)
-		printf("Ampire LCD cannot be configured: %d\n", ret);
-	return ret;
-}
-#endif
-
-#define I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
-			 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-
-static void setup_iomux_i2c(void)
-{
-	static const iomux_v3_cfg_t i2c_pads[] = {
-		NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
-		NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
-}
-
-static void setup_iomux_video(void)
-{
-	static const iomux_v3_cfg_t lcd_pads[] = {
-		MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0,
-		MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1,
-		MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2,
-		MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3,
-		MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4,
-		MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5,
-		MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6,
-		MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7,
-		MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8,
-		MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9,
-		MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10,
-		MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11,
-		MX53_PAD_EIM_A17__IPU_DISP1_DAT_12,
-		MX53_PAD_EIM_A18__IPU_DISP1_DAT_13,
-		MX53_PAD_EIM_A19__IPU_DISP1_DAT_14,
-		MX53_PAD_EIM_A20__IPU_DISP1_DAT_15,
-		MX53_PAD_EIM_A21__IPU_DISP1_DAT_16,
-		MX53_PAD_EIM_A22__IPU_DISP1_DAT_17,
-		MX53_PAD_EIM_A23__IPU_DISP1_DAT_18,
-		MX53_PAD_EIM_A24__IPU_DISP1_DAT_19,
-		MX53_PAD_EIM_D31__IPU_DISP1_DAT_20,
-		MX53_PAD_EIM_D30__IPU_DISP1_DAT_21,
-		MX53_PAD_EIM_D26__IPU_DISP1_DAT_22,
-		MX53_PAD_EIM_D27__IPU_DISP1_DAT_23,
-		MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK,
-		MX53_PAD_EIM_DA13__IPU_DI1_D0_CS,
-		MX53_PAD_EIM_DA14__IPU_DI1_D1_CS,
-		MX53_PAD_EIM_DA15__IPU_DI1_PIN1,
-		MX53_PAD_EIM_DA11__IPU_DI1_PIN2,
-		MX53_PAD_EIM_DA12__IPU_DI1_PIN3,
-		MX53_PAD_EIM_A25__IPU_DI1_PIN12,
-		MX53_PAD_EIM_DA10__IPU_DI1_PIN15,
-	};
-
-	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
-}
-
-static void setup_iomux_nand(void)
-{
-	static const iomux_v3_cfg_t nand_pads[] = {
-		NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
-				PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
-				PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
-				PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
-				PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
-				PAD_CTL_PUS_100K_UP),
-		NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
-				PAD_CTL_PUS_100K_UP),
-		NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
-				PAD_CTL_DSE_HIGH),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
-				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
-				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
-				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
-				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
-				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
-				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
-				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
-		NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
-				PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
-	};
-
-	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
-}
-
-static void m53_set_clock(void)
-{
-	int ret;
-	const uint32_t ref_clk = MXC_HCLK;
-	const uint32_t dramclk = 400;
-	uint32_t cpuclk;
-
-	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
-					    PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
-	gpio_direction_input(IMX_GPIO_NR(4, 0));
-
-	/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
-	cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
-
-	ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
-	if (ret)
-		printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);
-
-	ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
-	if (ret) {
-		printf("CPU:   Switch peripheral clock to %dMHz failed\n",
-			dramclk);
-	}
-
-	ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
-	if (ret)
-		printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
-}
-
-static void m53_set_nand(void)
-{
-	u32 i;
-
-	/* NAND flash is muxed on ATA pins */
-	setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
-
-	/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
-	for (i = 0x4; i < 0x94; i += 0x18) {
-		clrbits_le32(WEIM_BASE_ADDR + i,
-			     WEIM_GCR2_MUX16_BYP_GRANT_MASK);
-	}
-
-	mxc_set_clock(0, 33, MXC_NFC_CLK);
-	enable_nfc_clk(1);
-}
-
-int board_early_init_f(void)
-{
-	setup_iomux_uart();
-	setup_iomux_fec();
-	setup_iomux_i2c();
-	setup_iomux_nand();
-	setup_iomux_video();
-
-	m53_set_clock();
-
-	mxc_set_sata_internal_clock();
-
-	/* NAND clock @ 33MHz */
-	m53_set_nand();
-
-	return 0;
-}
-
-int board_init(void)
-{
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	puts("Board: DENX M53EVK\n");
-
-	return 0;
-}
-
-/*
- * NAND SPL
- */
-#ifdef CONFIG_SPL_BUILD
-void spl_board_init(void)
-{
-	setup_iomux_nand();
-	m53_set_clock();
-	m53_set_nand();
-}
-
-u32 spl_boot_device(void)
-{
-	return BOOT_DEVICE_NAND;
-}
-#endif
diff --git a/board/denx/ma5d4evk/Kconfig b/board/denx/ma5d4evk/Kconfig
deleted file mode 100644
index b4ef106..0000000
--- a/board/denx/ma5d4evk/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MA5D4EVK
-
-config SYS_BOARD
-	default "ma5d4evk"
-
-config SYS_VENDOR
-	default "denx"
-
-config SYS_CONFIG_NAME
-	default "ma5d4evk"
-
-endif
diff --git a/board/denx/ma5d4evk/MAINTAINERS b/board/denx/ma5d4evk/MAINTAINERS
deleted file mode 100644
index bb25a9c..0000000
--- a/board/denx/ma5d4evk/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DENX MA5D4EVK BOARD
-M:	Marek Vasut <marek.vasut@gmail.com>
-S:	Maintained
-F:	board/denx/ma5d4evk/
-F:	include/configs/ma5d4evk.h
-F:	configs/ma5d4evk_defconfig
diff --git a/board/denx/ma5d4evk/ma5d4evk.c b/board/denx/ma5d4evk/ma5d4evk.c
deleted file mode 100644
index ec0fa28..0000000
--- a/board/denx/ma5d4evk/ma5d4evk.c
+++ /dev/null
@@ -1,412 +0,0 @@
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/atmel_mpddrc.h>
-#include <asm/arch/atmel_usba_udc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/sama5d3_smc.h>
-#include <asm/arch/sama5d4.h>
-#include <atmel_hlcdc.h>
-#include <atmel_mci.h>
-#include <lcd.h>
-#include <mmc.h>
-#include <net.h>
-#include <netdev.h>
-#include <spi.h>
-#include <version.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_ATMEL_SPI
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
-}
-
-static void ma5d4evk_spi0_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* SPI0_SPCK */
-
-	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);	/* SPI0_CS0 */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_SPI0);
-}
-#endif /* CONFIG_ATMEL_SPI */
-
-#ifdef CONFIG_CMD_USB
-static void ma5d4evk_usb_hw_init(void)
-{
-	at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
-	at91_set_pio_output(AT91_PIO_PORTE, 14, 0);
-}
-#endif
-
-#ifdef CONFIG_LCD
-vidinfo_t panel_info = {
-	.vl_col			= 800,
-	.vl_row			= 480,
-	.vl_clk			= 33500000,
-	.vl_bpix		= LCD_BPP,
-	.vl_tft			= 1,
-	.vl_hsync_len		= 10,
-	.vl_left_margin		= 89,
-	.vl_right_margin	= 164,
-	.vl_vsync_len		= 10,
-	.vl_upper_margin	= 23,
-	.vl_lower_margin	= 10,
-	.mmio			= ATMEL_BASE_LCDC,
-};
-
-/* No power up/down pin for the LCD pannel */
-void lcd_enable(void)	{ /* Empty! */ }
-void lcd_disable(void)	{ /* Empty! */ }
-
-unsigned int has_lcdc(void)
-{
-	return 1;
-}
-
-static void ma5d4evk_lcd_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTA, 24, 1);	/* LCDPWM */
-	at91_set_a_periph(AT91_PIO_PORTA, 25, 0);	/* LCDDISP */
-	at91_set_a_periph(AT91_PIO_PORTA, 26, 0);	/* LCDVSYNC */
-	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* LCDHSYNC */
-	at91_set_a_periph(AT91_PIO_PORTA, 28, 0);	/* LCDDOTCK */
-	at91_set_a_periph(AT91_PIO_PORTA, 29, 1);	/* LCDDEN */
-
-	at91_set_a_periph(AT91_PIO_PORTA,  0, 0);	/* LCDD0 */
-	at91_set_a_periph(AT91_PIO_PORTA,  1, 0);	/* LCDD1 */
-	at91_set_a_periph(AT91_PIO_PORTA,  2, 0);	/* LCDD2 */
-	at91_set_a_periph(AT91_PIO_PORTA,  3, 0);	/* LCDD3 */
-	at91_set_a_periph(AT91_PIO_PORTA,  4, 0);	/* LCDD4 */
-	at91_set_a_periph(AT91_PIO_PORTA,  5, 0);	/* LCDD5 */
-	at91_set_a_periph(AT91_PIO_PORTA,  6, 0);	/* LCDD6 */
-	at91_set_a_periph(AT91_PIO_PORTA,  7, 0);	/* LCDD7 */
-
-	at91_set_a_periph(AT91_PIO_PORTA,  8, 0);	/* LCDD9 */
-	at91_set_a_periph(AT91_PIO_PORTA,  9, 0);	/* LCDD8 */
-	at91_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* LCDD10 */
-	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* LCDD11 */
-	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* LCDD12 */
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* LCDD13 */
-	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* LCDD14 */
-	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* LCDD15 */
-
-	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* LCDD16 */
-	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* LCDD17 */
-	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* LCDD18 */
-	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* LCDD19 */
-	at91_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* LCDD20 */
-	at91_set_a_periph(AT91_PIO_PORTA, 21, 0);	/* LCDD21 */
-	at91_set_a_periph(AT91_PIO_PORTA, 22, 0);	/* LCDD22 */
-	at91_set_a_periph(AT91_PIO_PORTA, 23, 0);	/* LCDD23 */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_LCDC);
-}
-
-#endif /* CONFIG_LCD */
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-/* On-SoM eMMC */
-void ma5d4evk_mci0_hw_init(void)
-{
-	at91_set_b_periph(AT91_PIO_PORTC, 5, 1);	/* MCI1 CDA */
-	at91_set_b_periph(AT91_PIO_PORTC, 6, 1);	/* MCI1 DA0 */
-	at91_set_b_periph(AT91_PIO_PORTC, 7, 1);	/* MCI1 DA1 */
-	at91_set_b_periph(AT91_PIO_PORTC, 8, 1);	/* MCI1 DA2 */
-	at91_set_b_periph(AT91_PIO_PORTC, 9, 1);	/* MCI1 DA3 */
-	at91_set_b_periph(AT91_PIO_PORTC, 10, 1);	/* MCI1 DA4 */
-	at91_set_b_periph(AT91_PIO_PORTC, 11, 1);	/* MCI1 DA5 */
-	at91_set_b_periph(AT91_PIO_PORTC, 12, 1);	/* MCI1 DA6 */
-	at91_set_b_periph(AT91_PIO_PORTC, 13, 1);	/* MCI1 DA7 */
-	at91_set_b_periph(AT91_PIO_PORTC, 4, 0);	/* MCI1 CLK */
-
-	/*
-	 * As the mci io internal pull down is too strong, so if the io needs
-	 * external pull up, the pull up resistor will be very small, if so
-	 * the power consumption will increase, so disable the internal pull
-	 * down to save the power.
-	 */
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_MCI0);
-}
-
-/* On-board MicroSD slot */
-void ma5d4evk_mci1_hw_init(void)
-{
-	at91_set_c_periph(AT91_PIO_PORTE, 19, 1);	/* MCI1 CDA */
-	at91_set_c_periph(AT91_PIO_PORTE, 20, 1);	/* MCI1 DA0 */
-	at91_set_c_periph(AT91_PIO_PORTE, 21, 1);	/* MCI1 DA1 */
-	at91_set_c_periph(AT91_PIO_PORTE, 22, 1);	/* MCI1 DA2 */
-	at91_set_c_periph(AT91_PIO_PORTE, 23, 1);	/* MCI1 DA3 */
-	at91_set_c_periph(AT91_PIO_PORTE, 18, 0);	/* MCI1 CLK */
-
-	/*
-	 * As the mci io internal pull down is too strong, so if the io needs
-	 * external pull up, the pull up resistor will be very small, if so
-	 * the power consumption will increase, so disable the internal pull
-	 * down to save the power.
-	 */
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0);
-
-	/* Deal with WP pin on the microSD slot. */
-	at91_set_pio_output(AT91_PIO_PORTE, 16, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 16, 1);
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_MCI1);
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	int ret;
-
-	/* De-assert reset on On-SoM eMMC */
-	at91_set_pio_output(AT91_PIO_PORTE, 15, 1);
-	at91_set_pio_pulldown(AT91_PIO_PORTE, 15, 0);
-
-	ret = atmel_mci_init((void *)ATMEL_BASE_MCI0);
-	if (ret)	/* eMMC init failed, skip it. */
-		at91_set_pio_output(AT91_PIO_PORTE, 15, 0);
-
-	/* Enable the power supply to On-board MicroSD */
-	at91_set_pio_output(AT91_PIO_PORTE, 17, 0);
-
-	ret = atmel_mci_init((void *)ATMEL_BASE_MCI1);
-	if (ret)	/* uSD init failed, power it down. */
-		at91_set_pio_output(AT91_PIO_PORTE, 17, 1);
-
-	return 0;
-}
-#endif /* CONFIG_GENERIC_ATMEL_MCI */
-
-#ifdef CONFIG_MACB
-void ma5d4evk_macb0_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* ETXCK_EREFCK */
-	at91_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* ERXDV */
-	at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* ERX0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* ERX1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* ERXER */
-	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* ETXEN */
-	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* ETX0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* ETX1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* EMDIO */
-	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* EMDC */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_GMAC0);
-}
-#endif
-
-static void ma5d4evk_serial_hw_init(void)
-{
-	/* USART0 */
-	at91_set_a_periph(AT91_PIO_PORTD, 13, 1);	/* TXD */
-	at91_set_a_periph(AT91_PIO_PORTD, 12, 0);	/* RXD */
-	at91_set_a_periph(AT91_PIO_PORTD, 11, 0);	/* RTS */
-	at91_set_a_periph(AT91_PIO_PORTD, 10, 0);	/* CTS */
-	at91_periph_clk_enable(ATMEL_ID_USART0);
-
-	/* USART1 */
-	at91_set_a_periph(AT91_PIO_PORTD, 17, 1);	/* TXD */
-	at91_set_a_periph(AT91_PIO_PORTD, 16, 0);	/* RXD */
-	at91_set_a_periph(AT91_PIO_PORTD, 15, 0);	/* RTS */
-	at91_set_a_periph(AT91_PIO_PORTD, 14, 0);	/* CTS */
-	at91_periph_clk_enable(ATMEL_ID_USART1);
-}
-
-int board_early_init_f(void)
-{
-	at91_periph_clk_enable(ATMEL_ID_PIOA);
-	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	at91_periph_clk_enable(ATMEL_ID_PIOC);
-	at91_periph_clk_enable(ATMEL_ID_PIOD);
-	at91_periph_clk_enable(ATMEL_ID_PIOE);
-
-	/* Configure LEDs as OFF */
-	at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
-	at91_set_pio_output(AT91_PIO_PORTD, 29, 0);
-	at91_set_pio_output(AT91_PIO_PORTD, 30, 0);
-
-	/* Reset CAN controllers */
-	at91_set_pio_output(AT91_PIO_PORTB, 21, 0);
-	udelay(100);
-	at91_set_pio_output(AT91_PIO_PORTB, 21, 1);
-	at91_set_pio_pulldown(AT91_PIO_PORTB, 21, 0);
-
-	ma5d4evk_serial_hw_init();
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-#ifdef CONFIG_ATMEL_SPI
-	ma5d4evk_spi0_hw_init();
-#endif
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-	ma5d4evk_mci0_hw_init();
-	ma5d4evk_mci1_hw_init();
-#endif
-#ifdef CONFIG_MACB
-	ma5d4evk_macb0_hw_init();
-#endif
-#ifdef CONFIG_LCD
-	ma5d4evk_lcd_hw_init();
-#endif
-#ifdef CONFIG_CMD_USB
-	ma5d4evk_usb_hw_init();
-#endif
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-	at91_udp_hw_init();
-#endif
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				    CONFIG_SYS_SDRAM_SIZE);
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-
-#ifdef CONFIG_MACB
-	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
-#endif
-
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-	usba_udc_probe(&pdata);
-#ifdef CONFIG_USB_ETH_RNDIS
-	usb_eth_initialize(bis);
-#endif
-#endif
-
-	return rc;
-}
-
-/* SPL */
-#ifdef CONFIG_SPL_BUILD
-void spl_board_init(void)
-{
-	ma5d4evk_spi0_hw_init();
-}
-
-static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
-{
-	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
-
-	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
-		    ATMEL_MPDDRC_CR_NR_ROW_13 |
-		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
-		    ATMEL_MPDDRC_CR_NB_8BANKS |
-		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
-		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
-		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
-
-	ddr2->rtr = 0x2b0;
-
-	ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
-		      3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
-		      3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
-		      10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
-		      3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
-		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
-		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
-		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
-
-	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
-		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
-		      25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
-		      23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
-
-	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
-		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
-		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
-		      2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
-		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
-}
-
-void mem_init(void)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	struct atmel_mpddrc_config ddr2;
-
-	ddr2_conf(&ddr2);
-
-	/* enable MPDDR clock */
-	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
-	writel(AT91_PMC_DDR, &pmc->scer);
-
-	/* DDRAM2 Controller initialize */
-	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
-}
-
-void at91_pmc_init(void)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	u32 tmp;
-
-	tmp = AT91_PMC_PLLAR_29 |
-	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
-	      AT91_PMC_PLLXR_MUL(87) |
-	      AT91_PMC_PLLXR_DIV(1);
-	at91_plla_init(tmp);
-
-	writel(0x0 << 8, &pmc->pllicpr);
-
-	tmp = AT91_PMC_MCKR_H32MXDIV |
-	      AT91_PMC_MCKR_PLLADIV_2 |
-	      AT91_PMC_MCKR_MDIV_3 |
-	      AT91_PMC_MCKR_CSS_PLLA;
-	at91_mck_init(tmp);
-}
-#endif
diff --git a/board/denx/mcvevk/MAINTAINERS b/board/denx/mcvevk/MAINTAINERS
deleted file mode 100644
index 6787727..0000000
--- a/board/denx/mcvevk/MAINTAINERS
+++ /dev/null
@@ -1,5 +0,0 @@
-SOCKIT BOARD
-M:	Marek Vasut <marex@denx.de>
-S:	Maintained
-F:	include/configs/socfpga_mcvevk.h
-F:	configs/socfpga_mcvevk_defconfig
diff --git a/board/denx/mcvevk/qts/sdram_config.h b/board/denx/mcvevk/qts/sdram_config.h
deleted file mode 100644
index 30c4d7d..0000000
--- a/board/denx/mcvevk/qts/sdram_config.h
+++ /dev/null
@@ -1,341 +0,0 @@
-/*
- * Altera SoCFPGA SDRAM configuration
- *
- * SPDX-License-Identifier:	BSD-3-Clause
- */
-
-#ifndef __SOCFPGA_SDRAM_CONFIG_H__
-#define __SOCFPGA_SDRAM_CONFIG_H__
-
-/* SDRAM configuration */
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			16
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			140
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		1560
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0	0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32	0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64	0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
-
-/* Sequencer auto configuration */
-#define RW_MGR_ACTIVATE_0_AND_1	0x0D
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
-#define RW_MGR_ACTIVATE_1	0x0F
-#define RW_MGR_CLEAR_DQS_ENABLE	0x49
-#define RW_MGR_GUARANTEED_READ	0x4C
-#define RW_MGR_GUARANTEED_READ_CONT	0x54
-#define RW_MGR_GUARANTEED_WRITE	0x18
-#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
-#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
-#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
-#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
-#define RW_MGR_IDLE	0x00
-#define RW_MGR_IDLE_LOOP1	0x7B
-#define RW_MGR_IDLE_LOOP2	0x7A
-#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
-#define RW_MGR_INIT_RESET_1_CKE_0	0x74
-#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
-#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
-#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
-#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
-#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
-#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
-#define RW_MGR_MRS0_DLL_RESET	0x02
-#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
-#define RW_MGR_MRS0_USER	0x07
-#define RW_MGR_MRS0_USER_MIRR	0x0C
-#define RW_MGR_MRS1	0x03
-#define RW_MGR_MRS1_MIRR	0x09
-#define RW_MGR_MRS2	0x04
-#define RW_MGR_MRS2_MIRR	0x0A
-#define RW_MGR_MRS3	0x05
-#define RW_MGR_MRS3_MIRR	0x0B
-#define RW_MGR_PRECHARGE_ALL	0x12
-#define RW_MGR_READ_B2B	0x59
-#define RW_MGR_READ_B2B_WAIT1	0x61
-#define RW_MGR_READ_B2B_WAIT2	0x6B
-#define RW_MGR_REFRESH_ALL	0x14
-#define RW_MGR_RETURN	0x01
-#define RW_MGR_SGLE_READ	0x7D
-#define RW_MGR_ZQCL	0x06
-
-/* Sequencer defines configuration */
-#define AFI_RATE_RATIO	1
-#define CALIB_LFIFO_OFFSET	7
-#define CALIB_VFIFO_OFFSET	5
-#define ENABLE_SUPER_QUICK_CALIBRATION	0
-#define IO_DELAY_PER_DCHAIN_TAP	25
-#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
-#define IO_DELAY_PER_OPA_TAP	312
-#define IO_DLL_CHAIN_LENGTH	8
-#define IO_DQDQS_OUT_PHASE_MAX	0
-#define IO_DQS_EN_DELAY_MAX	31
-#define IO_DQS_EN_DELAY_OFFSET	0
-#define IO_DQS_EN_PHASE_MAX	7
-#define IO_DQS_IN_DELAY_MAX	31
-#define IO_DQS_IN_RESERVE	4
-#define IO_DQS_OUT_RESERVE	4
-#define IO_IO_IN_DELAY_MAX	31
-#define IO_IO_OUT1_DELAY_MAX	31
-#define IO_IO_OUT2_DELAY_MAX	0
-#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
-#define MAX_LATENCY_COUNT_WIDTH	5
-#define READ_VALID_FIFO_SIZE	16
-#define REG_FILE_INIT_SEQ_SIGNATURE	0x55550496
-#define RW_MGR_MEM_ADDRESS_MIRRORING	0
-#define RW_MGR_MEM_DATA_MASK_WIDTH	4
-#define RW_MGR_MEM_DATA_WIDTH	32
-#define RW_MGR_MEM_DQ_PER_READ_DQS	8
-#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
-#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
-#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
-#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
-#define RW_MGR_MEM_NUMBER_OF_RANKS	1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
-#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
-#define TINIT_CNTR0_VAL	99
-#define TINIT_CNTR1_VAL	32
-#define TINIT_CNTR2_VAL	32
-#define TRESET_CNTR0_VAL	99
-#define TRESET_CNTR1_VAL	99
-#define TRESET_CNTR2_VAL	10
-
-/* Sequencer ac_rom_init configuration */
-const u32 ac_rom_init[] = {
-	0x20700000,
-	0x20780000,
-	0x10080421,
-	0x10080520,
-	0x10090044,
-	0x100a0008,
-	0x100b0000,
-	0x10380400,
-	0x10080441,
-	0x100804c0,
-	0x100a0024,
-	0x10090010,
-	0x100b0000,
-	0x30780000,
-	0x38780000,
-	0x30780000,
-	0x10680000,
-	0x106b0000,
-	0x10280400,
-	0x10480000,
-	0x1c980000,
-	0x1c9b0000,
-	0x1c980008,
-	0x1c9b0008,
-	0x38f80000,
-	0x3cf80000,
-	0x38780000,
-	0x18180000,
-	0x18980000,
-	0x13580000,
-	0x135b0000,
-	0x13580008,
-	0x135b0008,
-	0x33780000,
-	0x10580008,
-	0x10780000
-};
-
-/* Sequencer inst_rom_init configuration */
-const u32 inst_rom_init[] = {
-	0x80000,
-	0x80680,
-	0x8180,
-	0x8200,
-	0x8280,
-	0x8300,
-	0x8380,
-	0x8100,
-	0x8480,
-	0x8500,
-	0x8580,
-	0x8600,
-	0x8400,
-	0x800,
-	0x8680,
-	0x880,
-	0xa680,
-	0x80680,
-	0x900,
-	0x80680,
-	0x980,
-	0xa680,
-	0x8680,
-	0x80680,
-	0xb68,
-	0xcce8,
-	0xae8,
-	0x8ce8,
-	0xb88,
-	0xec88,
-	0xa08,
-	0xac88,
-	0x80680,
-	0xce00,
-	0xcd80,
-	0xe700,
-	0xc00,
-	0x20ce0,
-	0x20ce0,
-	0x20ce0,
-	0x20ce0,
-	0xd00,
-	0x680,
-	0x680,
-	0x680,
-	0x680,
-	0x60e80,
-	0x61080,
-	0x61080,
-	0x61080,
-	0xa680,
-	0x8680,
-	0x80680,
-	0xce00,
-	0xcd80,
-	0xe700,
-	0xc00,
-	0x30ce0,
-	0x30ce0,
-	0x30ce0,
-	0x30ce0,
-	0xd00,
-	0x680,
-	0x680,
-	0x680,
-	0x680,
-	0x70e80,
-	0x71080,
-	0x71080,
-	0x71080,
-	0xa680,
-	0x8680,
-	0x80680,
-	0x1158,
-	0x6d8,
-	0x80680,
-	0x1168,
-	0x7e8,
-	0x7e8,
-	0x87e8,
-	0x40fe8,
-	0x410e8,
-	0x410e8,
-	0x410e8,
-	0x1168,
-	0x7e8,
-	0x7e8,
-	0xa7e8,
-	0x80680,
-	0x40e88,
-	0x41088,
-	0x41088,
-	0x41088,
-	0x40f68,
-	0x410e8,
-	0x410e8,
-	0x410e8,
-	0xa680,
-	0x40fe8,
-	0x410e8,
-	0x410e8,
-	0x410e8,
-	0x41008,
-	0x41088,
-	0x41088,
-	0x41088,
-	0x1100,
-	0xc680,
-	0x8680,
-	0xe680,
-	0x80680,
-	0x0,
-	0x8000,
-	0xa000,
-	0xc000,
-	0x80000,
-	0x80,
-	0x8080,
-	0xa080,
-	0xc080,
-	0x80080,
-	0x9180,
-	0x8680,
-	0xa680,
-	0x80680,
-	0x40f08,
-	0x80680
-};
-
-#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/dfi/Kconfig b/board/dfi/Kconfig
index 25d0a11..5488f68 100644
--- a/board/dfi/Kconfig
+++ b/board/dfi/Kconfig
@@ -8,10 +8,10 @@ if VENDOR_DFI
 
 choice
 	prompt "Mainboard model"
-	optional
 
-config TARGET_DFI_BT700
-	bool "DFI BT700 BayTrail"
+config TARGET_Q7X_151_DFI_BT700
+	bool "DFI BT700 BayTrail on DFI Q7X-151 baseboard"
+	imply SCSI
 	help
 	  This is the DFI Q7X-151 baseboard equipped with the
 	  DFI BayTrail Bt700 SoM. It contains an Atom E3845 with
@@ -22,6 +22,19 @@ config TARGET_DFI_BT700
 	  Note that PCIE_ECAM_BASE is set up by the FSP so the value used
 	  by U-Boot matches that value.
 
+config TARGET_THEADORABLE_X86_DFI_BT700
+	bool "DFI BT700 BayTrail on theadorable-x86 baseboard"
+	imply SCSI
+	help
+	  This is the theadorable-x86 baseboard equipped with the
+	  DFI BayTrail Bt700 SoM. It contains an Atom E3845 with
+	  Ethernet (in non-PCIe-x4 configuration), micro-SD, USB 2,
+	  USB 3, SATA, serial console and DisplayPort video out.
+	  It requires some binary blobs - see README.x86 for details.
+
+	  Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+	  by U-Boot matches that value.
+
 endchoice
 
 source "board/dfi/dfi-bt700/Kconfig"
diff --git a/board/dfi/dfi-bt700/Kconfig b/board/dfi/dfi-bt700/Kconfig
index 3f0acb3..4b6c3fc 100644
--- a/board/dfi/dfi-bt700/Kconfig
+++ b/board/dfi/dfi-bt700/Kconfig
@@ -1,5 +1,3 @@
-if TARGET_DFI_BT700
-
 config SYS_BOARD
 	default "dfi-bt700"
 
@@ -10,7 +8,8 @@ config SYS_SOC
 	default "baytrail"
 
 config SYS_CONFIG_NAME
-	default "dfi-bt700"
+	default "dfi-bt700" if TARGET_Q7X_151_DFI_BT700
+	default "theadorable-x86-dfi-bt700" if TARGET_THEADORABLE_X86_DFI_BT700
 
 config SYS_TEXT_BASE
 	default 0xfff00000 if !EFI_STUB
@@ -21,8 +20,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR if !EFI_STUB
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select BOARD_EARLY_INIT_F
+	select BOARD_LATE_INIT
+	select SPI_FLASH_STMICRO
+	imply SPI_FLASH_SPANSION
+	imply SPI_FLASH_WINBOND
 
 config PCIE_ECAM_BASE
 	default 0xe0000000
-
-endif
diff --git a/board/dfi/dfi-bt700/MAINTAINERS b/board/dfi/dfi-bt700/MAINTAINERS
index 6639787..a99a725 100644
--- a/board/dfi/dfi-bt700/MAINTAINERS
+++ b/board/dfi/dfi-bt700/MAINTAINERS
@@ -3,6 +3,7 @@ M:	Stefan Roese <sr@denx.de>
 S:	Maintained
 F:	board/dfi/dfi-bt700
 F:	include/configs/dfi-bt700.h
+F:	include/configs/theadorable-x86-dfi-bt700.h
 F:	configs/dfi-bt700-q7x-151_defconfig
 F:	configs/theadorable-x86-dfi-bt700_defconfig
 F:	arch/x86/dts/dfi-bt700.dtsi
diff --git a/board/dfi/dfi-bt700/dfi-bt700.c b/board/dfi/dfi-bt700/dfi-bt700.c
index 8645bdc..3dd2036 100644
--- a/board/dfi/dfi-bt700/dfi-bt700.c
+++ b/board/dfi/dfi-bt700/dfi-bt700.c
@@ -28,3 +28,30 @@ int board_early_init_f(void)
 
 	return 0;
 }
+
+int board_late_init(void)
+{
+	struct gpio_desc desc;
+	int ret;
+
+	ret = dm_gpio_lookup_name("F10", &desc);
+	if (ret)
+		debug("gpio ret=%d\n", ret);
+	ret = dm_gpio_request(&desc, "xhci_hub_reset");
+	if (ret)
+		debug("gpio_request ret=%d\n", ret);
+	ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+	if (ret)
+		debug("gpio dir ret=%d\n", ret);
+
+	/* Pull xHCI hub reset to low (active low) */
+	dm_gpio_set_value(&desc, 0);
+
+	/* Wait at least 5 ms, so lets choose 10 to be safe */
+	mdelay(10);
+
+	/* Pull xHCI hub reset to high (active low) */
+	dm_gpio_set_value(&desc, 1);
+
+	return 0;
+}
diff --git a/board/dnp5370/Kconfig b/board/dnp5370/Kconfig
deleted file mode 100644
index 797081d..0000000
--- a/board/dnp5370/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_DNP5370
-
-config SYS_BOARD
-	default "dnp5370"
-
-config SYS_CONFIG_NAME
-	default "dnp5370"
-
-endif
diff --git a/board/dnp5370/MAINTAINERS b/board/dnp5370/MAINTAINERS
deleted file mode 100644
index 8333891..0000000
--- a/board/dnp5370/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DNP5370 BOARD
-M:	M.Hasewinkel (MHA) <info@ssv-embedded.de>
-S:	Maintained
-F:	board/dnp5370/
-F:	include/configs/dnp5370.h
-F:	configs/dnp5370_defconfig
diff --git a/board/dnp5370/Makefile b/board/dnp5370/Makefile
deleted file mode 100644
index c0271da..0000000
--- a/board/dnp5370/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= dnp5370.o
diff --git a/board/dnp5370/README b/board/dnp5370/README
deleted file mode 100644
index 0172698..0000000
--- a/board/dnp5370/README
+++ /dev/null
@@ -1,67 +0,0 @@
-This document describes the board support for
-Dil/NetPC DNP/5370 (http://www.dilnetpc.com/dnp0086.htm) module.
-The distributor is SSV (http://www.ssv-embedded.de),
-
-The module used to develop the support files contains:
-
-*   Processor: Blackfin BF537 Rev 0.3 (600 MHz core / 120MHz RAM)
-
-*   RAM: 32 MB SDRAM
-    Hynix HY57V561620FTP-H 810EA
-    Connected to Blackfin via "Expansion Bus"
-    Address range 0x0000.0000 - 0x1fff.ffff
-
-*   NOR flash: 32 MBit (4 MByte)
-    Exel Semiconductor ES29LVS320EB
-    Connected to Blackfin via "Expansion Bus",
-    Chip Selects 0, 1 and 2, each is connected
-    to a 1 MB memory bank at Blackfin, therefore
-    only 3 MB accessible.
-    Address range 0x2000.0000 - 0x202f.ffff
-    CFI compatible
-
-    Exel Semiconductor was bought by Rohm Semiconductor (www.rohm.com).
-
-*   NAND flash: 64 MBit (8 MByte)
-    Atmel 45DB642D-CNU
-    Connected to Blackfin via SPI
-    CFI compatible
-
-*   Davicom DM9161EP Ethernet PHY
-
-*   A SD card reader, connected via SPI
-
-*   Hardware watchdog MAX823 or TPS3823
-
-(other devices not listed here)
-
-To run it, the module must be inserted in a 64 pin DIL socket
-on another board, e.g. DNP/EVA13 (together: SSV SK28).
-
-The Blackfin is booted from NOR flash. The NOR flash data begins
-with the U-Boot code and is then followed by the Linux code.
-Finally, the MAC is stored in the last sector.
-You may need to adjust these settings to your needs.
-The memory map used to develop the board support is:
-
-Memory map:
-0x00000000 .. 0x01ffffff SDRAM
-0x20000000 .. 0x202fffff NOR flash
-
-RAM use:
-0x01f9bffc .. 0x01fbbffb U-Boot stack
-0x01f9c000 .. 0x01f9ffff U-Boot global data
-0x01fa0000 .. 0x01fbffff U-Boot malloc() RAM
-0x01fc0000 .. 0x01ffffff U-Boot execution RAM
-
-NOR flash use:
-0x20000000 .. 0x0002ffff U-Boot
-0x20004000 .. 0x20005fff U-Boot environment
-0x20030000 .. 0x202effff Linux kernel image
-0x202f0000 .. 0x202fffff MAC address sector
-
-NOR flash is 0x00300000 (3145728) bytes large (3 MB).
-Max space for compressed kernel in flash is 0x002c0000 (2883584) bytes (2.75 MB)
-Max space for u-boot in flash is 0x00030000 (196608) bytes (192 KB)
-
-The module is hardwired to BYPASS boot mode.
diff --git a/board/dnp5370/dnp5370.c b/board/dnp5370/dnp5370.c
deleted file mode 100644
index 56e3b02..0000000
--- a/board/dnp5370/dnp5370.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * (C) Copyright 2010 3ality Digital Systems
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/blackfin.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/gpio.h>
-
-static void disable_external_watchdog(void)
-{
-#ifdef CONFIG_DNP5370_EXT_WD_DISABLE
-	/* disable external HW watchdog with PH13 = WD1 = 1 */
-	gpio_request(GPIO_PH13, "ext_wd");
-	gpio_direction_output(GPIO_PH13, 1);
-#endif
-}
-
-int checkboard(void)
-{
-	printf("Board: SSV DilNet DNP5370\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-static void board_init_enetaddr(uchar *mac_addr)
-{
-#ifndef CONFIG_SYS_NO_FLASH
-	/* we cram the MAC in the last flash sector */
-	uchar *board_mac_addr = (uchar *)0x202F0000;
-	if (is_valid_ethaddr(board_mac_addr)) {
-		memcpy(mac_addr, board_mac_addr, 6);
-		eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
-#endif
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
-
-/* miscellaneous platform dependent initialisations */
-int misc_init_r(void)
-{
-	disable_external_watchdog();
-
-#ifdef CONFIG_BFIN_MAC
-	uchar enetaddr[6];
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
-		board_init_enetaddr(enetaddr);
-#endif
-
-#ifndef CONFIG_SYS_NO_FLASH
-	/* we use the last sector for the MAC address / POST LDR */
-	extern flash_info_t flash_info[];
-	flash_protect(FLAG_PROTECT_SET, 0x202F0000, 0x202FFFFF, &flash_info[0]);
-#endif
-
-	return 0;
-}
diff --git a/board/ebv/socrates/qts/sdram_config.h b/board/ebv/socrates/qts/sdram_config.h
index cf9d1d3..b4872c2 100644
--- a/board/ebv/socrates/qts/sdram_config.h
+++ b/board/ebv/socrates/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x0
diff --git a/board/efi/efi-x86/efi.c b/board/efi/efi-x86/efi.c
index 1fbe36a..2adc202 100644
--- a/board/efi/efi-x86/efi.c
+++ b/board/efi/efi-x86/efi.c
@@ -5,9 +5,3 @@
  */
 
 #include <common.h>
-#include <asm/gpio.h>
-
-int arch_early_init_r(void)
-{
-	return 0;
-}
diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c
index 2c8e978..d64c345 100644
--- a/board/egnite/ethernut5/ethernut5.c
+++ b/board/egnite/ethernut5/ethernut5.c
@@ -58,8 +58,6 @@
 #include <netdev.h>
 #include <miiphy.h>
 #include <i2c.h>
-#include <spi.h>
-#include <dataflash.h>
 #include <mmc.h>
 #include <atmel_mci.h>
 
@@ -67,7 +65,6 @@
 #include <asm/arch/at91sam9260_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_spi.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
 #include <asm/io.h>
@@ -77,25 +74,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
-
-struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
-	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}
-};
-
-/*
- * In fact we have 7 partitions, but u-boot supports 5 only. This is
- * no big deal, because the first partition is reserved for applications
- * and the last one is used by Nut/OS. Both need not to be visible here.
- */
-dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
-	{ 0x00021000, 0x00041FFF, FLAG_PROTECT_SET, 0, "setup" },
-	{ 0x00042000, 0x000C5FFF, FLAG_PROTECT_SET, 0, "uboot" },
-	{ 0x000C6000, 0x00359FFF, FLAG_PROTECT_SET, 0, "kernel" },
-	{ 0x0035A000, 0x003DDFFF, FLAG_PROTECT_SET, 0, "nutos" },
-	{ 0x003DE000, 0x003FEFFF, FLAG_PROTECT_CLEAR, 0, "env" }
-};
-
 /*
  * This is called last during early initialization. Most of the basic
  * hardware interfaces are up and running.
@@ -158,14 +136,10 @@ int board_init(void)
 	/* Set adress of boot parameters. */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 	/* Initialize UARTs and power management. */
-	at91_seriald_hw_init();
 	ethernut5_power_init();
 #ifdef CONFIG_CMD_NAND
 	ethernut5_nand_hw_init();
 #endif
-#ifdef CONFIG_HAS_DATAFLASH
-	at91_spi0_hw_init(1 << 0);
-#endif
 	return 0;
 }
 
@@ -221,31 +195,3 @@ int board_mmc_getcd(struct mmc *mmc)
 	return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN);
 }
 #endif
-
-#ifdef CONFIG_ATMEL_SPI
-/*
-
- * Note, that u-boot uses different code for SPI bus access. While
- * memory routines use automatic chip select control, the serial
- * flash support requires 'manual' GPIO control. Thus, we switch
- * modes.
- */
-void spi_cs_activate(struct spi_slave *slave)
-{
-	/* Enable NPCS0 in GPIO mode. This disables peripheral control. */
-	at91_set_pio_output(AT91_PIO_PORTA, 3, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	/* Disable NPCS0 in GPIO mode. */
-	at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
-	/* Switch back to peripheral chip select control. */
-	at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
-}
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-#endif
diff --git a/board/el/el6x/el6x.c b/board/el/el6x/el6x.c
index 7856b84..cbe355a 100644
--- a/board/el/el6x/el6x.c
+++ b/board/el/el6x/el6x.c
@@ -10,12 +10,12 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c
index ad7a8cf..8674599 100644
--- a/board/embest/mx6boards/mx6boards.c
+++ b/board/embest/mx6boards/mx6boards.c
@@ -18,13 +18,13 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/spi.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
+#include <asm/mach-imx/video.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
diff --git a/board/emulation/Kconfig b/board/emulation/Kconfig
index 36809fd..6d55dca 100644
--- a/board/emulation/Kconfig
+++ b/board/emulation/Kconfig
@@ -18,6 +18,13 @@ config TARGET_QEMU_X86
 	  supported by U-Boot. They are via QEMU '-M pc', an i440FX/PIIX
 	  chipset platform and '-M q35', a Q35/ICH9 chipset platform.
 
+config TARGET_QEMU_X86_64
+	bool "QEMU x86 64-bit"
+	help
+	  This is the QEMU emulated x86 64-bit board. With this config
+	  U-Boot is built as a 64-bit binary. This allows testing while
+	  this feature is being completed.
+
 endchoice
 
 source "board/emulation/qemu-x86/Kconfig"
diff --git a/board/emulation/qemu-x86/Kconfig b/board/emulation/qemu-x86/Kconfig
index c9181fc..a593f8c 100644
--- a/board/emulation/qemu-x86/Kconfig
+++ b/board/emulation/qemu-x86/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_QEMU_X86
+if TARGET_QEMU_X86 || TARGET_QEMU_X86_64
 
 config SYS_BOARD
 	default "qemu-x86"
@@ -13,8 +13,8 @@ config SYS_CONFIG_NAME
 	default "qemu-x86"
 
 config SYS_TEXT_BASE
-	default 0xfff00000 if !EFI_STUB
-	default 0x01110000 if EFI_STUB
+	default 0xfff00000 if !EFI_STUB && !SUPPORT_SPL
+	default 0x01110000 if EFI_STUB || SUPPORT_SPL
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
diff --git a/board/emulation/qemu-x86/MAINTAINERS b/board/emulation/qemu-x86/MAINTAINERS
index 54dc2c5..4cf8ac9 100644
--- a/board/emulation/qemu-x86/MAINTAINERS
+++ b/board/emulation/qemu-x86/MAINTAINERS
@@ -6,3 +6,10 @@ F:	include/configs/qemu-x86.h
 F:	configs/qemu-x86_defconfig
 F:	configs/qemu-x86_efi_payload32_defconfig
 F:	configs/qemu-x86_efi_payload64_defconfig
+
+QEMU X86 64-bit BOARD
+M:	Bin Meng <bmeng.cn@gmail.com>
+S:	Maintained
+F:	board/emulation/qemu-x86/
+F:	include/configs/qemu-x86.h
+F:	configs/qemu-x86_64_defconfig
diff --git a/board/engicam/common/Makefile b/board/engicam/common/Makefile
new file mode 100644
index 0000000..6630fea
--- /dev/null
+++ b/board/engicam/common/Makefile
@@ -0,0 +1,7 @@
+# Copyright (C) 2016 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y := board.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/engicam/common/board.c b/board/engicam/common/board.c
new file mode 100644
index 0000000..e3bb569
--- /dev/null
+++ b/board/engicam/common/board.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+#include <asm/arch/sys_proto.h>
+
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+static void mmc_late_init(void)
+{
+	char cmd[32];
+	char mmcblk[32];
+	u32 dev_no = mmc_get_env_dev();
+
+	setenv_ulong("mmcdev", dev_no);
+
+	/* Set mmcblk env */
+	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
+	setenv("mmcroot", mmcblk);
+
+	sprintf(cmd, "mmc dev %d", dev_no);
+	run_command(cmd, 0);
+}
+#endif
+
+int board_late_init(void)
+{
+	switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
+			IMX6_BMODE_SHIFT) {
+	case IMX6_BMODE_SD:
+	case IMX6_BMODE_ESD:
+	case IMX6_BMODE_MMC:
+	case IMX6_BMODE_EMMC:
+#ifdef CONFIG_ENV_IS_IN_MMC
+		mmc_late_init();
+#endif
+		setenv("modeboot", "mmcboot");
+		break;
+	case IMX6_BMODE_NAND:
+		setenv("modeboot", "nandboot");
+		break;
+	default:
+		setenv("modeboot", "");
+		break;
+	}
+
+	if (is_mx6ul())
+		setenv("console", "ttymxc0");
+	else
+		setenv("console", "ttymxc3");
+
+	setenv_fdt_file();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_VIDEO_IPUV3
+	setup_display();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
diff --git a/board/engicam/common/board.h b/board/engicam/common/board.h
new file mode 100644
index 0000000..f364a23
--- /dev/null
+++ b/board/engicam/common/board.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+void setenv_fdt_file(void);
+void setup_gpmi_nand(void);
+void setup_display(void);
+#endif /* _BOARD_H_ */
diff --git a/board/engicam/common/spl.c b/board/engicam/common/spl.c
new file mode 100644
index 0000000..a8a7cf3
--- /dev/null
+++ b/board/engicam/common/spl.c
@@ -0,0 +1,393 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
+        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+        PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+#ifdef CONFIG_MX6QDL
+        IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+        IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+#elif CONFIG_MX6UL
+	IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)),
+#endif
+};
+
+#ifdef CONFIG_MX6QDL
+/*
+ * Driving strength:
+ *   0x30 == 40 Ohm
+ *   0x28 == 48 Ohm
+ */
+#define IMX6DQ_DRIVE_STRENGTH		0x30
+#define IMX6SDL_DRIVE_STRENGTH		0x28
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
+	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ddr_type = 0x000c0000,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
+	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
+	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* mt41j256 */
+static struct mx6_ddr3_cfg mt41j256 = {
+	.mem_speed = 1066,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 13,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+	.SRT = 0,
+};
+
+static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x000E0009,
+	.p0_mpwldectrl1 = 0x0018000E,
+	.p1_mpwldectrl0 = 0x00000007,
+	.p1_mpwldectrl1 = 0x00000000,
+	.p0_mpdgctrl0 = 0x43280334,
+	.p0_mpdgctrl1 = 0x031C0314,
+	.p1_mpdgctrl0 = 0x4318031C,
+	.p1_mpdgctrl1 = 0x030C0258,
+	.p0_mprddlctl = 0x3E343A40,
+	.p1_mprddlctl = 0x383C3844,
+	.p0_mpwrdlctl = 0x40404440,
+	.p1_mpwrdlctl = 0x4C3E4446,
+};
+
+/* DDR 64bit */
+static struct mx6_ddr_sysinfo mem_q = {
+	.ddr_type	= DDR_TYPE_DDR3,
+	.dsize		= 2,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 2,
+	.rtt_wr		= 2,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x001F0024,
+	.p0_mpwldectrl1 = 0x00110018,
+	.p1_mpwldectrl0 = 0x001F0024,
+	.p1_mpwldectrl1 = 0x00110018,
+	.p0_mpdgctrl0 = 0x4230022C,
+	.p0_mpdgctrl1 = 0x02180220,
+	.p1_mpdgctrl0 = 0x42440248,
+	.p1_mpdgctrl1 = 0x02300238,
+	.p0_mprddlctl = 0x44444A48,
+	.p1_mprddlctl = 0x46484A42,
+	.p0_mpwrdlctl = 0x38383234,
+	.p1_mpwrdlctl = 0x3C34362E,
+};
+
+/* DDR 64bit 1GB */
+static struct mx6_ddr_sysinfo mem_dl = {
+	.dsize		= 2,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 1,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+/* DDR 32bit 512MB */
+static struct mx6_ddr_sysinfo mem_s = {
+	.dsize		= 1,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 1,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+#endif /* CONFIG_MX6QDL */
+
+#ifdef CONFIG_MX6UL
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds = 0x00000030,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_odt0 = 0x00000030,
+	.dram_odt1 = 0x00000030,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdclk_0 = 0x00000008,
+	.dram_sdqs0 = 0x00000038,
+	.dram_sdqs1 = 0x00000030,
+	.dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x00070007,
+	.p0_mpdgctrl0 = 0x41490145,
+	.p0_mprddlctl = 0x40404546,
+	.p0_mpwrdlctl = 0x4040524D,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+	.dsize = 0,
+	.cs_density = 20,
+	.ncs = 1,
+	.cs1_mirror = 0,
+	.rtt_wr = 2,
+	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
+	.walat = 1,		/* Write additional latency */
+	.ralat = 5,		/* Read additional latency */
+	.mif3_mode = 3,		/* Command prediction working mode */
+	.bi_on = 1,		/* Bank interleaving enabled */
+	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.ddr_type = DDR_TYPE_DDR3,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 800,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+#ifdef TARGET_MX6UL_ISIOT
+	.rowaddr = 15,
+#else
+	.rowaddr = 13,
+#endif
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+#endif /* CONFIG_MX6UL */
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+#ifdef CONFIG_MX6QDL
+	writel(0x00003F3F, &ccm->CCGR0);
+	writel(0x0030FC00, &ccm->CCGR1);
+	writel(0x000FC000, &ccm->CCGR2);
+	writel(0x3F300000, &ccm->CCGR3);
+	writel(0xFF00F300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003CC, &ccm->CCGR6);
+#elif CONFIG_MX6UL
+	writel(0x00c03f3f, &ccm->CCGR0);
+	writel(0xfcffff00, &ccm->CCGR1);
+	writel(0x0cffffcc, &ccm->CCGR2);
+	writel(0x3f3c3030, &ccm->CCGR3);
+	writel(0xff00fffc, &ccm->CCGR4);
+	writel(0x033f30ff, &ccm->CCGR5);
+	writel(0x00c00fff, &ccm->CCGR6);
+#endif
+}
+
+static void gpr_init(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* enable AXI cache for VDOA/VPU/IPU */
+	writel(0xF00000CF, &iomux->gpr[4]);
+	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+	writel(0x007F007F, &iomux->gpr[6]);
+	writel(0x007F007F, &iomux->gpr[7]);
+}
+
+static void spl_dram_init(void)
+{
+#ifdef CONFIG_MX6QDL
+	if (is_mx6solo()) {
+		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
+	} else if (is_mx6dl()) {
+		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
+	} else if (is_mx6dq()) {
+		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+		mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
+	}
+#elif CONFIG_MX6UL
+	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+#endif
+
+	udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	gpr_init();
+
+	/* iomux */
+	SETUP_IOMUX_PADS(uart_pads);
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
diff --git a/board/engicam/geam6ul/Kconfig b/board/engicam/geam6ul/Kconfig
new file mode 100644
index 0000000..7f4023e
--- /dev/null
+++ b/board/engicam/geam6ul/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6UL_GEAM
+
+config SYS_BOARD
+	default "geam6ul"
+
+config SYS_VENDOR
+	default "engicam"
+
+config SYS_CONFIG_NAME
+	default "imx6-engicam"
+
+endif
diff --git a/board/engicam/geam6ul/MAINTAINERS b/board/engicam/geam6ul/MAINTAINERS
new file mode 100644
index 0000000..1c31375
--- /dev/null
+++ b/board/engicam/geam6ul/MAINTAINERS
@@ -0,0 +1,8 @@
+GEAM6UL BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	board/engicam/geam6ul
+F:	include/configs/imx6ul_geam.h
+F:	configs/imx6ul_geam_mmc_defconfig
+F:	configs/imx6ul_geam_nand_defconfig
+F:	arch/arm/dts/imx6ul-geam-kit.dts
diff --git a/board/engicam/geam6ul/Makefile b/board/engicam/geam6ul/Makefile
new file mode 100644
index 0000000..0e367e2
--- /dev/null
+++ b/board/engicam/geam6ul/Makefile
@@ -0,0 +1,6 @@
+# Copyright (C) 2016 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := geam6ul.o
diff --git a/board/engicam/geam6ul/README b/board/engicam/geam6ul/README
new file mode 100644
index 0000000..0df6ae4
--- /dev/null
+++ b/board/engicam/geam6ul/README
@@ -0,0 +1,28 @@
+How to use U-Boot on Engicam GEAM6UL Starter Kit:
+-------------------------------------------------
+
+- Configure U-Boot for Engicam GEAM6UL:
+
+$ make mrproper
+$ make imx6ul_geam_mmc_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot-dtb.img image into the micro SD card:
+
+sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+MMC Boot: JM3 Closed
+
+- Connect the Serial cable between the Starter Kit and the PC for the console.
+(J28 is the Linux Serial console connector)
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/board/engicam/geam6ul/geam6ul.c b/board/engicam/geam6ul/geam6ul.c
new file mode 100644
index 0000000..bc36fc7
--- /dev/null
+++ b/board/engicam/geam6ul/geam6ul.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+
+#include "../common/board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_NAND_MXS
+
+#define GPMI_PAD_CTRL0		(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1		(PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+				PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2		(GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+static iomux_v3_cfg_t const nand_pads[] = {
+	IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+};
+
+void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	SETUP_IOMUX_PADS(nand_pads);
+
+	clrbits_le32(&mxc_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+
+	/*
+	 * config gpmi and bch clock to 100 MHz
+	 * bch/gpmi select PLL2 PFD2 400M
+	 * 100M = 400M / 4
+	 */
+	clrbits_le32(&mxc_ccm->cscmr1,
+		     MXC_CCM_CSCMR1_BCH_CLK_SEL |
+		     MXC_CCM_CSCMR1_GPMI_CLK_SEL);
+	clrsetbits_le32(&mxc_ccm->cscdr1,
+			MXC_CCM_CSCDR1_BCH_PODF_MASK |
+			MXC_CCM_CSCDR1_GPMI_PODF_MASK,
+			(3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
+			(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
+
+	/* enable gpmi and bch clock gating */
+	setbits_le32(&mxc_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif /* CONFIG_NAND_MXS */
+
+void setenv_fdt_file(void)
+{
+	if (is_mx6ul())
+		setenv("fdt_file", "imx6ul-geam-kit.dtb");
+}
+
+#ifdef CONFIG_SPL_BUILD
+/* MMC board initialization is needed till adding DM support in SPL */
+#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+
+	/* VSELECT */
+	IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	/* CD */
+	IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* RST_B */
+	IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 1)
+
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC1_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+
+	/*
+	* According to the board_mmc_init() the following map is done:
+	* (U-boot device node)    (Physical Port)
+	* mmc0				USDHC1
+	*/
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc1_pads);
+			gpio_direction_input(USDHC1_CD_GPIO);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		default:
+			printf("Warning - USDHC%d controller not supporting\n",
+			       i + 1);
+			return 0;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/engicam/icorem6/Kconfig b/board/engicam/icorem6/Kconfig
new file mode 100644
index 0000000..4a1c9ac
--- /dev/null
+++ b/board/engicam/icorem6/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6Q_ICORE
+
+config SYS_BOARD
+	default "icorem6"
+
+config SYS_VENDOR
+	default "engicam"
+
+config SYS_CONFIG_NAME
+	default "imx6-engicam"
+
+endif
diff --git a/board/engicam/icorem6/MAINTAINERS b/board/engicam/icorem6/MAINTAINERS
new file mode 100644
index 0000000..26b4b56
--- /dev/null
+++ b/board/engicam/icorem6/MAINTAINERS
@@ -0,0 +1,10 @@
+ICOREM6QDL BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	board/engicam/icorem6
+F:	include/configs/imx6qdl_icore.h
+F:	configs/imx6qdl_icore_mmc_defconfig
+F:	configs/imx6qdl_icore_nand_defconfig
+F:	arch/arm/dts/imx6qdl-icore.dtsi
+F:	arch/arm/dts/imx6q-icore.dts
+F:	arch/arm/dts/imx6dl-icore.dts
diff --git a/board/engicam/icorem6/Makefile b/board/engicam/icorem6/Makefile
new file mode 100644
index 0000000..9ec9ecd
--- /dev/null
+++ b/board/engicam/icorem6/Makefile
@@ -0,0 +1,6 @@
+# Copyright (C) 2016 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := icorem6.o
diff --git a/board/engicam/icorem6/README b/board/engicam/icorem6/README
new file mode 100644
index 0000000..6461c0a
--- /dev/null
+++ b/board/engicam/icorem6/README
@@ -0,0 +1,33 @@
+How to use U-Boot on Engicam i.CoreM6 Solo/DualLite and Quad/Dual Starter Kit:
+-----------------------------------------------------------------------------
+
+$ make mrproper
+
+- Configure U-Boot for Engicam i.CoreM6 Quad/Dual:
+$ make imx6q_icore_mmc_defconfig
+
+- Configure U-Boot for Engicam i.CoreM6 Solo/DualLite:
+$ make imx6dl_icore_mmc_defconfig
+
+- Build U-Boot
+$ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot-dtb.img image into the micro SD card:
+
+sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+MMC Boot: JM3 Closed
+
+- Connect the Serial cable between the Starter Kit and the PC for the console.
+(J28 is the Linux Serial console connector)
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
new file mode 100644
index 0000000..5b2ed06
--- /dev/null
+++ b/board/engicam/icorem6/icorem6.c
@@ -0,0 +1,287 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
+
+#include "../common/board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_NAND_MXS
+
+#define GPMI_PAD_CTRL0	(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1	(PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+			PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2	(GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+iomux_v3_cfg_t gpmi_pads[] = {
+	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
+	IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+};
+
+void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	SETUP_IOMUX_PADS(gpmi_pads);
+
+	/* gate ENFC_CLK_ROOT clock first,before clk source switch */
+	clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+	/* config gpmi and bch clock to 100 MHz */
+	clrsetbits_le32(&mxc_ccm->cs2cdr,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+	/* enable ENFC_CLK_ROOT clock */
+	setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+	/* enable gpmi and bch clock gating */
+	setbits_le32(&mxc_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static iomux_v3_cfg_t const rgb_pads[] = {
+	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
+	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15),
+	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
+	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
+	IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
+	IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
+	IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
+	IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
+	IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
+	IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
+	IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
+	IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
+	IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
+	IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
+	IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
+	IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
+	IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
+	IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
+	IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
+	IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
+	IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
+	IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
+};
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+	SETUP_IOMUX_PADS(rgb_pads);
+}
+
+struct display_info_t const displays[] = {
+	{
+		.bus	= -1,
+		.addr	= 0,
+		.pixfmt	= IPU_PIX_FMT_RGB666,
+		.detect	= NULL,
+		.enable	= enable_rgb,
+		.mode	= {
+			.name           = "Amp-WD",
+			.refresh        = 60,
+			.xres           = 800,
+			.yres           = 480,
+			.pixclock       = 30000,
+			.left_margin    = 30,
+			.right_margin   = 30,
+			.upper_margin   = 5,
+			.lower_margin   = 5,
+			.hsync_len      = 64,
+			.vsync_len      = 20,
+			.sync           = FB_SYNC_EXT,
+			.vmode          = FB_VMODE_NONINTERLACED
+		}
+	},
+};
+
+size_t display_count = ARRAY_SIZE(displays);
+
+void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	enable_ipu_clock();
+
+	/* Turn on LDB0,IPU,IPU DI0 clocks */
+	reg = __raw_readl(&mxc_ccm->CCGR3);
+	reg |=  (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff);
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* set LDB0, LDB1 clk select to 011/011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+		MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+		(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
+		MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
+		IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
+		IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+		IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+		IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
+		IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+		IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+		IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
+		IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
+		(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+		IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+void setenv_fdt_file(void)
+{
+	if (is_mx6dq())
+		setenv("fdt_file", "imx6q-icore.dtb");
+	else if(is_mx6dl() || is_mx6solo())
+		setenv("fdt_file", "imx6dl-icore.dtb");
+}
+
+#ifdef CONFIG_SPL_BUILD
+/* MMC board initialization is needed till adding DM support in SPL */
+#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IOMUX_PADS(PAD_SD1_CLK__SD1_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__SD1_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
+};
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 1)
+
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC1_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+
+	/*
+	* According to the board_mmc_init() the following map is done:
+	* (U-boot device node)    (Physical Port)
+	* mmc0				USDHC1
+	*/
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc1_pads);
+			gpio_direction_input(USDHC1_CD_GPIO);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		default:
+			printf("Warning - USDHC%d controller not supporting\n",
+			       i + 1);
+			return 0;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
+		return 0;
+	else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
+		return 0;
+	else
+		return -1;
+}
+#endif
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/engicam/icorem6_rqs/Kconfig b/board/engicam/icorem6_rqs/Kconfig
new file mode 100644
index 0000000..6dc3a07
--- /dev/null
+++ b/board/engicam/icorem6_rqs/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6Q_ICORE_RQS
+
+config SYS_BOARD
+	default "icorem6_rqs"
+
+config SYS_VENDOR
+	default "engicam"
+
+config SYS_CONFIG_NAME
+	default "imx6-engicam"
+
+endif
diff --git a/board/engicam/icorem6_rqs/MAINTAINERS b/board/engicam/icorem6_rqs/MAINTAINERS
new file mode 100644
index 0000000..6205acb
--- /dev/null
+++ b/board/engicam/icorem6_rqs/MAINTAINERS
@@ -0,0 +1,9 @@
+ICOREM6QDL_RQS BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	board/engicam/icorem6_rqs
+F:	include/configs/imx6qdl_icore_rqs.h
+F:	configs/imx6qdl_icore_rqs_defconfig
+F:	arch/arm/dts/imx6qdl-icore-rqs.dtsi
+F:	arch/arm/dts/imx6q-icore-rqs.dts
+F:	arch/arm/dts/imx6dl-icore-rqs.dts
diff --git a/board/engicam/icorem6_rqs/Makefile b/board/engicam/icorem6_rqs/Makefile
new file mode 100644
index 0000000..2e3933c
--- /dev/null
+++ b/board/engicam/icorem6_rqs/Makefile
@@ -0,0 +1,6 @@
+# Copyright (C) 2016 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := icorem6_rqs.o
diff --git a/board/engicam/icorem6_rqs/README b/board/engicam/icorem6_rqs/README
new file mode 100644
index 0000000..ccce622
--- /dev/null
+++ b/board/engicam/icorem6_rqs/README
@@ -0,0 +1,33 @@
+How to use U-Boot on Engicam i.CoreM6 RQS Solo/DualLite and Quad/Dual Starter Kit:
+----------------------------------------------------------------------------------
+
+$ make mrproper
+
+- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual:
+$ make imx6q_icore_rqs_mmc_defconfig
+
+- Configure U-Boot for Engicam i.CoreM6 RQS Solo/DualLite:
+$ make imx6dl_icore_rqs_mmc_defconfig
+
+- Build U-Boot
+$ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot-dtb.img image into the micro SD card:
+
+sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+MMC Boot: JM3 Closed
+
+- Connect the Serial cable between the Starter Kit and the PC for the console.
+(J28 is the Linux Serial console connector)
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c
new file mode 100644
index 0000000..10a9471
--- /dev/null
+++ b/board/engicam/icorem6_rqs/icorem6_rqs.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+
+#include "../common/board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+int board_mmc_get_env_dev(int devno)
+{
+	/* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
+	return (devno == 3) ? 1 : 0;
+}
+#endif
+
+void setenv_fdt_file(void)
+{
+	if (is_mx6dq())
+		setenv("fdt_file", "imx6q-icore-rqs.dtb");
+	else if(is_mx6dl() || is_mx6solo())
+		setenv("fdt_file", "imx6dl-icore-rqs.dtb");
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+
+/* MMC board initialization is needed till adding DM support in SPL */
+#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_HIGH |               \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC3_BASE_ADDR, 1, 4},
+	{USDHC4_BASE_ADDR, 1, 8},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC3_BASE_ADDR:
+	case USDHC4_BASE_ADDR:
+		ret = 1;
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+
+	/*
+	* According to the board_mmc_init() the following map is done:
+	* (U-boot device node)    (Physical Port)
+	* mmc0			USDHC3
+	* mmc1			USDHC4
+	*/
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc3_pads);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			break;
+		case 1:
+			SETUP_IOMUX_PADS(usdhc4_pads);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+			break;
+		default:
+			printf("Warning - USDHC%d controller not supporting\n",
+			       i + 1);
+			return 0;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+void board_boot_order(u32 *spl_boot_list)
+{
+	u32 bmode = imx6_src_get_boot_mode();
+	u8 boot_dev = BOOT_DEVICE_MMC1;
+
+	switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
+	case IMX6_BMODE_SD:
+	case IMX6_BMODE_ESD:
+		/* SD/eSD - BOOT_DEVICE_MMC1 */
+		break;
+	case IMX6_BMODE_MMC:
+	case IMX6_BMODE_EMMC:
+		/* MMC/eMMC */
+		boot_dev = BOOT_DEVICE_MMC2;
+		break;
+	default:
+		/* Default - BOOT_DEVICE_MMC1 */
+		printf("Wrong board boot order\n");
+		break;
+	}
+
+	spl_boot_list[0] = boot_dev;
+}
+#endif
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs"))
+		return 0;
+	else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs"))
+		return 0;
+	else
+		return -1;
+}
+#endif
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/engicam/isiotmx6ul/Kconfig b/board/engicam/isiotmx6ul/Kconfig
new file mode 100644
index 0000000..10c2c50
--- /dev/null
+++ b/board/engicam/isiotmx6ul/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6UL_ISIOT
+
+config SYS_BOARD
+	default "isiotmx6ul"
+
+config SYS_VENDOR
+	default "engicam"
+
+config SYS_CONFIG_NAME
+	default "imx6-engicam"
+
+endif
diff --git a/board/engicam/isiotmx6ul/MAINTAINERS b/board/engicam/isiotmx6ul/MAINTAINERS
new file mode 100644
index 0000000..c30cfe7
--- /dev/null
+++ b/board/engicam/isiotmx6ul/MAINTAINERS
@@ -0,0 +1,12 @@
+ISIOTMX6UL BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	board/engicam/isiotmx6ul
+F:	include/configs/imx6ul_isiot.h
+F:	configs/imx6ul_isiot_mmc_defconfig
+F:	configs/imx6ul_isiot_emmc_defconfig
+F:	configs/imx6ul_isiot_nand_defconfig
+F:	arch/arm/dts/imx6ul-isiot.dtsi
+F:	arch/arm/dts/imx6ul-isiot-mmc.dts
+F:	arch/arm/dts/imx6ul-isiot-emmc.dts
+F:	arch/arm/dts/imx6ul-isiot-nand.dts
diff --git a/board/engicam/isiotmx6ul/Makefile b/board/engicam/isiotmx6ul/Makefile
new file mode 100644
index 0000000..f4f8c78
--- /dev/null
+++ b/board/engicam/isiotmx6ul/Makefile
@@ -0,0 +1,6 @@
+# Copyright (C) 2016 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := isiotmx6ul.o
diff --git a/board/engicam/isiotmx6ul/README b/board/engicam/isiotmx6ul/README
new file mode 100644
index 0000000..1d177ac
--- /dev/null
+++ b/board/engicam/isiotmx6ul/README
@@ -0,0 +1,28 @@
+How to use U-Boot on Engicam Is.IoT MX6UL Starter Kit:
+-----------------------------------------------------
+
+- Configure U-Boot for Engicam Is.IoT MX6UL
+
+$ make mrproper
+$ make imx6ul_isiot_mmc_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot-dtb.img image into the micro SD card:
+
+sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+MMC Boot: JM3 Closed
+
+- Connect the Serial cable between the Starter Kit and the PC for the console.
+(J28 is the Linux Serial console connector)
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/board/engicam/isiotmx6ul/isiotmx6ul.c b/board/engicam/isiotmx6ul/isiotmx6ul.c
new file mode 100644
index 0000000..4dcc9ea
--- /dev/null
+++ b/board/engicam/isiotmx6ul/isiotmx6ul.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mmc.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/iomux-v3.h>
+
+#include "../common/board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_NAND_MXS
+
+#define GPMI_PAD_CTRL0		(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1		(PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+				PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2		(GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+static iomux_v3_cfg_t const nand_pads[] = {
+	IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+};
+
+void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	SETUP_IOMUX_PADS(nand_pads);
+
+	clrbits_le32(&mxc_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+
+	/*
+	 * config gpmi and bch clock to 100 MHz
+	 * bch/gpmi select PLL2 PFD2 400M
+	 * 100M = 400M / 4
+	 */
+	clrbits_le32(&mxc_ccm->cscmr1,
+		     MXC_CCM_CSCMR1_BCH_CLK_SEL |
+		     MXC_CCM_CSCMR1_GPMI_CLK_SEL);
+	clrsetbits_le32(&mxc_ccm->cscdr1,
+			MXC_CCM_CSCDR1_BCH_PODF_MASK |
+			MXC_CCM_CSCDR1_GPMI_PODF_MASK,
+			(3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
+			(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
+
+	/* enable gpmi and bch clock gating */
+	setbits_le32(&mxc_ccm->CCGR4,
+		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif /* CONFIG_NAND_MXS */
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+int board_mmc_get_env_dev(int devno)
+{
+	/* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
+	return (devno == 0) ? 0 : 1;
+}
+#endif
+
+void setenv_fdt_file(void)
+{
+	if (is_mx6ul()) {
+#ifdef CONFIG_ENV_IS_IN_MMC
+		setenv("fdt_file", "imx6ul-isiot-emmc.dtb");
+#else
+		setenv("fdt_file", "imx6ul-isiot-nand.dtb");
+#endif
+	}
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+
+/* MMC board initialization is needed till adding DM support in SPL */
+#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+
+	/* VSELECT */
+	IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	/* CD */
+	IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* RST_B */
+	IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IOMUX_PADS(PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 19)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(4, 5)
+
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 4},
+	{USDHC2_BASE_ADDR, 0, 8},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+
+	/*
+	* According to the board_mmc_init() the following map is done:
+	* (U-boot device node)    (Physical Port)
+	* mmc0				USDHC1
+	* mmc1				USDHC2
+	*/
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc1_pads);
+			gpio_direction_input(USDHC1_CD_GPIO);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		case 1:
+			SETUP_IOMUX_PADS(usdhc2_pads);
+			gpio_direction_input(USDHC2_CD_GPIO);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			break;
+		default:
+			printf("Warning - USDHC%d controller not supporting\n",
+			       i + 1);
+			return 0;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+void board_boot_order(u32 *spl_boot_list)
+{
+	u32 bmode = imx6_src_get_boot_mode();
+	u8 boot_dev = BOOT_DEVICE_MMC1;
+
+	switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
+	case IMX6_BMODE_SD:
+	case IMX6_BMODE_ESD:
+		/* SD/eSD - BOOT_DEVICE_MMC1 */
+		break;
+	case IMX6_BMODE_MMC:
+	case IMX6_BMODE_EMMC:
+		/* MMC/eMMC */
+		boot_dev = BOOT_DEVICE_MMC2;
+		break;
+	default:
+		/* Default - BOOT_DEVICE_MMC1 */
+		printf("Wrong board boot order\n");
+		break;
+	}
+
+	spl_boot_list[0] = boot_dev;
+}
+#endif
+#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c
deleted file mode 100644
index 9541817..0000000
--- a/board/esd/common/cmd_loadpci.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * (C) Copyright 2005-2008
- * Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <console.h>
-#if !defined(CONFIG_440)
-#include <asm/4xx_pci.h>
-#endif
-
-#if defined(CONFIG_CMD_BSP)
-#define ADDRMASK 0xfffff000
-
-/*
- * Command loadpci: wait for signal from host and boot image.
- */
-int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	u32 *ptr = 0;
-	int count = 0;
-	int count2 = 0;
-	char addr[16];
-	char str[] = "\\|/-";
-	u32 la, ptm1la;
-
-#if defined(CONFIG_440)
-	ptm1la = in32r(PCIL0_PTM1LA);
-#else
-	ptm1la = in32r(PTM1LA);
-#endif
-	while(1) {
-		/*
-		 * Mark sync address
-		 */
-		ptr = (u32 *)ptm1la;
-		memset(ptr, 0, 0x20);
-
-		*ptr = 0xffffffff;
-		puts("\nWaiting for action from pci host -");
-
-		/*
-		 * Wait for host to write the start address
-		 */
-		while (*ptr == 0xffffffff) {
-			count++;
-			if (!(count % 100)) {
-				count2++;
-				putc(0x08); /* backspace */
-				putc(str[count2 % 4]);
-			}
-
-			/* Abort if ctrl-c was pressed */
-			if (ctrlc()) {
-				puts("\nAbort\n");
-				return 0;
-			}
-
-			udelay(1000);
-		}
-
-		printf("\nGot bootcode %08x: ", *ptr);
-		la = ptm1la + (*ptr & ADDRMASK);
-		sprintf(addr, "%08x", la);
-
-		switch (*ptr & ~ADDRMASK) {
-		case 0:
-			/*
-			 * Boot image via bootm
-			 */
-			printf("booting image at addr 0x%s ...\n", addr);
-			setenv("loadaddr", addr);
-			do_bootm(cmdtp, 0, 0, NULL);
-			break;
-
-		case 1:
-			/*
-			 * Boot image via "source" command
-			 */
-			printf("executing script at addr 0x%s ...\n", addr);
-			source(la, NULL);
-			break;
-
-		case 2:
-			/*
-			 * Call run_cmd
-			 */
-			printf("running command at addr 0x%s ...\n", addr);
-			run_command((char *)la, 0);
-			break;
-
-		default:
-			printf("unhandled boot method\n");
-			break;
-		}
-	}
-}
-
-U_BOOT_CMD(
-	loadpci,	1,	1,	do_loadpci,
-	"Wait for pci bootcmd and boot it",
-	""
-);
-
-#endif
diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c
deleted file mode 100644
index 51ac10c..0000000
--- a/board/esd/common/esd405ep_nand.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2007
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#if defined(CONFIG_CMD_NAND)
-#include <asm/io.h>
-#include <nand.h>
-
-/*
- * hardware specific access to control-lines
- */
-static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-	struct nand_chip *this = mtd_to_nand(mtd);
-	if (ctrl & NAND_CTRL_CHANGE) {
-		if ( ctrl & NAND_CLE )
-			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE);
-		else
-			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CLE);
-		if ( ctrl & NAND_ALE )
-			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_ALE);
-		else
-			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_ALE);
-		if ( ctrl & NAND_NCE )
-			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CE);
-		else
-			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
-	}
-
-	if (cmd != NAND_CMD_NONE)
-		writeb(cmd, this->IO_ADDR_W);
-}
-
-
-/*
- * read device ready pin
- */
-static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo)
-{
-	if (in_be32((void *)GPIO0_IR) & CONFIG_SYS_NAND_RDY)
-		return 1;
-	return 0;
-}
-
-
-int board_nand_init(struct nand_chip *nand)
-{
-	/*
-	 * Set NAND-FLASH GPIO signals to defaults
-	 */
-	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
-	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
-
-	/*
-	 * Initialize nand_chip structure
-	 */
-	nand->cmd_ctrl = esd405ep_nand_hwcontrol;
-	nand->dev_ready = esd405ep_nand_device_ready;
-	nand->ecc.mode = NAND_ECC_SOFT;
-	nand->chip_delay = NAND_BIG_DELAY_US;
-	nand->options = NAND_SAMSUNG_LP_OPTIONS;
-	return 0;
-}
-#endif
diff --git a/board/esd/common/flash.c b/board/esd/common/flash.c
deleted file mode 100644
index e3512c7..0000000
--- a/board/esd/common/flash.c
+++ /dev/null
@@ -1,659 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#ifdef __PPC__
-#include <asm/ppc4xx.h>
-#endif
-#include <asm/processor.h>
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-	int i;
-	short n;
-
-	/* set up sector start address table */
-	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
-	    for (i = 0; i < info->sector_count; i++)
-		info->start[i] = base + (i * 0x00010000);
-	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
-		/* set sector offsets for bottom boot block type	*/
-		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
-			info->start[i] = base;
-			base += 8 << 10;
-		}
-		while (i < info->sector_count) {	/* 64k regular sectors	*/
-			info->start[i] = base;
-			base += 64 << 10;
-			++i;
-		}
-	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
-		/* set sector offsets for top boot block type		*/
-		base += info->size;
-		i = info->sector_count;
-		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
-			base -= 8 << 10;
-			--i;
-			info->start[i] = base;
-		}
-		while (i > 0) {			/* 64k regular sectors	*/
-			base -= 64 << 10;
-			--i;
-			info->start[i] = base;
-		}
-	} else {
-	    if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00030000;
-		}
-	    } else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00010000;
-		}
-	    }
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-	int k;
-	int size;
-	int erased;
-	volatile unsigned long *flash;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	case FLASH_MAN_SST:	printf ("SST ");		break;
-	case FLASH_MAN_EXCEL:	printf ("Excel Semiconductor "); break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM320T:	printf ("AM29LV320T (32 M, top sector)\n");
-				break;
-	case FLASH_AM320B:	printf ("AM29LV320B (32 M, bottom sector)\n");
-				break;
-	case FLASH_AMDL322T:	printf ("AM29DL322T (32 M, top sector)\n");
-				break;
-	case FLASH_AMDL322B:	printf ("AM29DL322B (32 M, bottom sector)\n");
-				break;
-	case FLASH_AMDL323T:	printf ("AM29DL323T (32 M, top sector)\n");
-				break;
-	case FLASH_AMDL323B:	printf ("AM29DL323B (32 M, bottom sector)\n");
-				break;
-	case FLASH_AM640U:	printf ("AM29LV640D (64 M, uniform sector)\n");
-				break;
-	case FLASH_SST800A:	printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
-				break;
-	case FLASH_SST160A:	printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
-				break;
-	case FLASH_SST320:	printf ("SST39LF/VF320 (32 Mbit, uniform sector size)\n");
-				break;
-	case FLASH_SST640:	printf ("SST39LF/VF640 (64 Mbit, uniform sector size)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
-		/*
-		 * Check if whole sector is erased
-		 */
-		if (i != (info->sector_count-1))
-		  size = info->start[i+1] - info->start[i];
-		else
-		  size = info->start[0] + info->size - info->start[i];
-		erased = 1;
-		flash = (volatile unsigned long *)info->start[i];
-		size = size >> 2;        /* divide by 4 for longword access */
-		for (k=0; k<size; k++)
-		  {
-		    if (*flash++ != 0xffffffff)
-		      {
-			erased = 0;
-			break;
-		      }
-		  }
-
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		/* print empty and read-only info */
-		printf (" %08lX%s%s",
-			info->start[i],
-			erased ? " E" : "  ",
-			info->protect[i] ? "RO " : "   ");
-#else
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-#endif
-
-	}
-	printf ("\n");
-	return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-	short i;
-	short n;
-	CONFIG_SYS_FLASH_WORD_SIZE value;
-	ulong base = (ulong)addr;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
-
-	value = addr2[CONFIG_SYS_FLASH_READ0];
-
-	switch (value) {
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
-		info->flash_id = FLASH_MAN_SST;
-		break;
-	case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT:
-		info->flash_id = FLASH_MAN_EXCEL;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash	*/
-	}
-
-	value = addr2[CONFIG_SYS_FLASH_READ1];		/* device ID		*/
-
-	switch (value) {
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00080000;
-		break;				/* => 0.5 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00080000;
-		break;				/* => 0.5 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
-		info->flash_id += FLASH_AM320T;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
-		info->flash_id += FLASH_AMDL322T;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
-		info->flash_id += FLASH_AMDL322B;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
-		info->flash_id += FLASH_AMDL323T;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
-		info->flash_id += FLASH_AMDL323B;
-		info->sector_count = 71;
-		info->size = 0x00400000;  break;	/* => 4 MB	*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U:
-		info->flash_id += FLASH_AM640U;
-		info->sector_count = 128;
-		info->size = 0x00800000;  break;	/* => 8 MB	*/
-
-#if !(defined(CONFIG_ADCIOP) || defined(CONFIG_DASA_SIM))
-	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A:
-		info->flash_id += FLASH_SST800A;
-		info->sector_count = 16;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A:
-	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1601:
-	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1602:
-		info->flash_id += FLASH_SST160A;
-		info->sector_count = 32;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3201:
-	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3202:
-		info->flash_id += FLASH_SST320;
-		info->sector_count = 64;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6401:
-	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6402:
-		info->flash_id += FLASH_SST640;
-		info->sector_count = 128;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-#endif
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-
-	}
-
-	/* set up sector start address table */
-	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
-	    for (i = 0; i < info->sector_count; i++)
-		info->start[i] = base + (i * 0x00010000);
-	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
-		/* set sector offsets for bottom boot block type	*/
-		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
-			info->start[i] = base;
-			base += 8 << 10;
-		}
-		while (i < info->sector_count) {	/* 64k regular sectors	*/
-			info->start[i] = base;
-			base += 64 << 10;
-			++i;
-		}
-	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
-		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
-		/* set sector offsets for top boot block type		*/
-		base += info->size;
-		i = info->sector_count;
-		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
-			base -= 8 << 10;
-			--i;
-			info->start[i] = base;
-		}
-		while (i > 0) {			/* 64k regular sectors	*/
-			base -= 64 << 10;
-			--i;
-			info->start[i] = base;
-		}
-	} else {
-	    if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00030000;
-		}
-	    } else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00010000;
-		}
-	    }
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
-		if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
-		  info->protect[i] = 0;
-		else
-		  info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
-		*addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-	int i;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-		    addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
-		    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050;  /* block erase */
-			for (i=0; i<50; i++)
-			  udelay(1000);  /* wait 1 ms */
-		    } else {
-			if (sect == s_first) {
-			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-			    addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
-			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-			    addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-			}
-			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
-		    }
-		    l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
-	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-	}
-
-DONE:
-	/* reset to read mode */
-	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
-	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	ulong *data_ptr = &data;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
-	ulong start;
-	int flag;
-	int i;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data) {
-		return (2);
-	}
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++)
-	  {
-	    addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
-	    addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
-	    addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
-
-	    dest2[i] = data2[i];
-
-	    /* re-enable interrupts if necessary */
-	    if (flag)
-	      enable_interrupts();
-
-	    /* data polling for D7 */
-	    start = get_timer (0);
-	    while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
-		   (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
-	      if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-		return (1);
-	      }
-	    }
-	  }
-
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/esd/common/fpga.c b/board/esd/common/fpga.c
deleted file mode 100644
index 5c70b47..0000000
--- a/board/esd/common/fpga.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef FPGA_DEBUG
-#define DBG(x...) printf(x)
-#else
-#define DBG(x...)
-#endif /* DEBUG */
-
-#define MAX_ONES               226
-
-#ifdef CONFIG_SYS_FPGA_PRG
-# define FPGA_PRG              CONFIG_SYS_FPGA_PRG	/* FPGA program pin (ppc output) */
-# define FPGA_CLK              CONFIG_SYS_FPGA_CLK	/* FPGA clk pin (ppc output)    */
-# define FPGA_DATA             CONFIG_SYS_FPGA_DATA	/* FPGA data pin (ppc output)  */
-# define FPGA_DONE             CONFIG_SYS_FPGA_DONE	/* FPGA done pin (ppc input)   */
-# define FPGA_INIT             CONFIG_SYS_FPGA_INIT	/* FPGA init pin (ppc input)   */
-#else
-# define FPGA_PRG              0x04000000	/* FPGA program pin (ppc output) */
-# define FPGA_CLK              0x02000000	/* FPGA clk pin (ppc output)     */
-# define FPGA_DATA             0x01000000	/* FPGA data pin (ppc output)    */
-# define FPGA_DONE             0x00800000	/* FPGA done pin (ppc input)     */
-# define FPGA_INIT             0x00400000	/* FPGA init pin (ppc input)     */
-#endif
-
-#define ERROR_FPGA_PRG_INIT_LOW  -1	/* Timeout after PRG* asserted   */
-#define ERROR_FPGA_PRG_INIT_HIGH -2	/* Timeout after PRG* deasserted */
-#define ERROR_FPGA_PRG_DONE      -3	/* Timeout after programming     */
-
-#ifndef SET_FPGA
-# define SET_FPGA(data)         out_be32((void *)GPIO0_OR, data)
-#endif
-
-#ifdef FPGA_PROG_ACTIVE_HIGH
-# define FPGA_PRG_LOW           FPGA_PRG
-# define FPGA_PRG_HIGH          0
-#else
-# define FPGA_PRG_LOW           0
-# define FPGA_PRG_HIGH          FPGA_PRG
-#endif
-
-#define FPGA_CLK_LOW            0
-#define FPGA_CLK_HIGH           FPGA_CLK
-
-#define FPGA_DATA_LOW           0
-#define FPGA_DATA_HIGH          FPGA_DATA
-
-#define FPGA_WRITE_1 {                                                                   \
-	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_HIGH);  /* set clock to 0 */  \
-	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_HIGH);  /* set data to 1  */  \
-	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);  /* set clock to 1 */  \
-	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);}	/* set data to 1  */
-
-#define FPGA_WRITE_0 {                                                    \
-	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_HIGH);  /* set clock to 0 */  \
-	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW  | FPGA_DATA_LOW);   /* set data to 0  */  \
-	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_LOW);   /* set clock to 1 */  \
-	SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);}	/* set data to 1  */
-
-#ifndef FPGA_DONE_STATE
-# define FPGA_DONE_STATE (in_be32((void *)GPIO0_IR) & FPGA_DONE)
-#endif
-#ifndef FPGA_INIT_STATE
-# define FPGA_INIT_STATE (in_be32((void *)GPIO0_IR) & FPGA_INIT)
-#endif
-
-
-static int fpga_boot (const unsigned char *fpgadata, int size)
-{
-	int i, index, len;
-	int count;
-	unsigned char b;
-
-#ifdef CONFIG_SYS_FPGA_SPARTAN2
-	int j;
-#else
-	int bit;
-#endif
-
-	/* display infos on fpgaimage */
-	index = 15;
-	for (i = 0; i < 4; i++) {
-		len = fpgadata[index];
-		DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
-		index += len + 3;
-	}
-
-#ifdef CONFIG_SYS_FPGA_SPARTAN2
-	/* search for preamble 0xFFFFFFFF */
-	while (1) {
-		if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
-		    && (fpgadata[index + 2] == 0xff)
-		    && (fpgadata[index + 3] == 0xff))
-			break;	/* preamble found */
-		else
-			index++;
-	}
-#else
-	/* search for preamble 0xFF2X */
-	for (index = 0; index < size - 1; index++) {
-		if ((fpgadata[index] == 0xff)
-		    && ((fpgadata[index + 1] & 0xf0) == 0x30))
-			break;
-	}
-	index += 2;
-#endif
-
-	DBG ("FPGA: configdata starts at position 0x%x\n", index);
-	DBG ("FPGA: length of fpga-data %d\n", size - index);
-
-	/*
-	 * Setup port pins for fpga programming
-	 */
-#ifndef CONFIG_M5249
-	out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
-	/* setup for output */
-	out_be32 ((void *)GPIO0_TCR,
-		  in_be32 ((void *)GPIO0_TCR) |
-		  FPGA_PRG | FPGA_CLK | FPGA_DATA);
-#endif
-	SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);	/* set pins to high */
-
-	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
-	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
-
-	/*
-	 * Init fpga by asserting and deasserting PROGRAM*
-	 */
-	SET_FPGA (FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH);	/* set prog active */
-
-	/* Wait for FPGA init line low */
-	count = 0;
-	while (FPGA_INIT_STATE) {
-		udelay (1000);	/* wait 1ms */
-		/* Check for timeout - 100us max, so use 3ms */
-		if (count++ > 3) {
-			DBG ("FPGA: Booting failed!\n");
-			return ERROR_FPGA_PRG_INIT_LOW;
-		}
-	}
-
-	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
-	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
-
-	/* deassert PROGRAM* */
-	SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);	/* set prog inactive */
-
-	/* Wait for FPGA end of init period .  */
-	count = 0;
-	while (!(FPGA_INIT_STATE)) {
-		udelay (1000);	/* wait 1ms */
-		/* Check for timeout */
-		if (count++ > 3) {
-			DBG ("FPGA: Booting failed!\n");
-			return ERROR_FPGA_PRG_INIT_HIGH;
-		}
-	}
-
-	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
-	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
-
-	DBG ("write configuration data into fpga\n");
-	/* write configuration-data into fpga... */
-
-#ifdef CONFIG_SYS_FPGA_SPARTAN2
-	/*
-	 * Load uncompressed image into fpga
-	 */
-	for (i = index; i < size; i++) {
-		b = fpgadata[i];
-		for (j = 0; j < 8; j++) {
-			if ((b & 0x80) == 0x80) {
-				FPGA_WRITE_1;
-			} else {
-				FPGA_WRITE_0;
-			}
-			b <<= 1;
-		}
-	}
-#else
-	/* send 0xff 0x20 */
-	FPGA_WRITE_1;
-	FPGA_WRITE_1;
-	FPGA_WRITE_1;
-	FPGA_WRITE_1;
-	FPGA_WRITE_1;
-	FPGA_WRITE_1;
-	FPGA_WRITE_1;
-	FPGA_WRITE_1;
-	FPGA_WRITE_0;
-	FPGA_WRITE_0;
-	FPGA_WRITE_1;
-	FPGA_WRITE_0;
-	FPGA_WRITE_0;
-	FPGA_WRITE_0;
-	FPGA_WRITE_0;
-	FPGA_WRITE_0;
-
-	/*
-	 ** Bit_DeCompression
-	 **   Code 1           .. maxOnes     : n                 '1's followed by '0'
-	 **        maxOnes + 1 .. maxOnes + 1 : n - 1             '1's no '0'
-	 **        maxOnes + 2 .. 254         : n - (maxOnes + 2) '0's followed by '1'
-	 **        255                        :                   '1'
-	 */
-
-	for (i = index; i < size; i++) {
-		b = fpgadata[i];
-		if ((b >= 1) && (b <= MAX_ONES)) {
-			for (bit = 0; bit < b; bit++) {
-				FPGA_WRITE_1;
-			}
-			FPGA_WRITE_0;
-		} else if (b == (MAX_ONES + 1)) {
-			for (bit = 1; bit < b; bit++) {
-				FPGA_WRITE_1;
-			}
-		} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
-			for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
-				FPGA_WRITE_0;
-			}
-			FPGA_WRITE_1;
-		} else if (b == 255) {
-			FPGA_WRITE_1;
-		}
-	}
-#endif
-
-	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
-	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");
-
-	/*
-	 * Check if fpga's DONE signal - correctly booted ?
-	 */
-
-	/* Wait for FPGA end of programming period .  */
-	count = 0;
-	while (!(FPGA_DONE_STATE)) {
-		udelay (1000);	/* wait 1ms */
-		/* Check for timeout */
-		if (count++ > 3) {
-			DBG ("FPGA: Booting failed!\n");
-			return ERROR_FPGA_PRG_DONE;
-		}
-	}
-
-	DBG ("FPGA: Booting successful!\n");
-	return 0;
-}
diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c
deleted file mode 100644
index 22a59e4..0000000
--- a/board/esd/common/lcd.c
+++ /dev/null
@@ -1,359 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include "asm/io.h"
-#include "lcd.h"
-
-
-extern int video_display_bitmap (ulong, int, int);
-
-
-int palette_index;
-int palette_value;
-int lcd_depth;
-unsigned char *glob_lcd_reg;
-unsigned char *glob_lcd_mem;
-
-#if defined(CONFIG_SYS_LCD_ENDIAN)
-void lcd_setup(int lcd, int config)
-{
-	if (lcd == 0) {
-		/*
-		 * Set endianess and reset lcd controller 0 (small)
-		 */
-
-		/* set reset to low */
-		out_be32((void*)GPIO0_OR,
-			 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD0_RST);
-		udelay(10); /* wait 10us */
-		if (config == 1) {
-			/* big-endian */
-			out_be32((void*)GPIO0_OR,
-				 in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
-		} else {
-			/* little-endian */
-			out_be32((void*)GPIO0_OR,
-				 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN);
-		}
-		udelay(10); /* wait 10us */
-		/* set reset to high */
-		out_be32((void*)GPIO0_OR,
-			 in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD0_RST);
-	} else {
-		/*
-		 * Set endianess and reset lcd controller 1 (big)
-		 */
-
-		/* set reset to low */
-		out_be32((void*)GPIO0_OR,
-			 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD1_RST);
-		udelay(10); /* wait 10us */
-		if (config == 1) {
-			/* big-endian */
-			out_be32((void*)GPIO0_OR,
-				 in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
-		} else {
-			/* little-endian */
-			out_be32((void*)GPIO0_OR,
-				 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN);
-		}
-		udelay(10); /* wait 10us */
-		/* set reset to high */
-		out_be32((void*)GPIO0_OR,
-			 in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD1_RST);
-	}
-
-	/*
-	 * CONFIG_SYS_LCD_ENDIAN may also be FPGA_RESET, so set inactive
-	 */
-	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
-}
-#endif /* CONFIG_SYS_LCD_ENDIAN */
-
-
-int lcd_bmp(uchar *logo_bmp)
-{
-	int i;
-	uchar *ptr;
-	ushort *ptr2;
-	ushort val;
-	unsigned char *dst = NULL;
-	int x, y;
-	int width, height, bpp, colors, line_size;
-	int header_size;
-	unsigned char *bmp;
-	unsigned char r, g, b;
-	BITMAPINFOHEADER *bm_info;
-	ulong len;
-
-	/*
-	 * Check for bmp mark 'BM'
-	 */
-	if (*(ushort *)logo_bmp != 0x424d) {
-		/*
-		 * Decompress bmp image
-		 */
-		len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
-		dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
-		if (dst == NULL) {
-			printf("Error: malloc for gunzip failed!\n");
-			return 1;
-		}
-		if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE,
-			   (uchar *)logo_bmp, &len) != 0) {
-			free(dst);
-			return 1;
-		}
-		if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) {
-			printf("Image could be truncated"
-			       " (increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n");
-		}
-
-		/*
-		 * Check for bmp mark 'BM'
-		 */
-		if (*(ushort *)dst != 0x424d) {
-			printf("LCD: Unknown image format!\n");
-			free(dst);
-			return 1;
-		}
-	} else {
-		/*
-		 * Uncompressed BMP image, just use this pointer
-		 */
-		dst = (uchar *)logo_bmp;
-	}
-
-	/*
-	 * Get image info from bmp-header
-	 */
-	bm_info = (BITMAPINFOHEADER *)(dst + 14);
-	bpp = LOAD_SHORT(bm_info->biBitCount);
-	width = LOAD_LONG(bm_info->biWidth);
-	height = LOAD_LONG(bm_info->biHeight);
-	switch (bpp) {
-	case 1:
-		colors = 1;
-		line_size = width >> 3;
-		break;
-	case 4:
-		colors = 16;
-		line_size = width >> 1;
-		break;
-	case 8:
-		colors = 256;
-		line_size = width;
-		break;
-	case 24:
-		colors = 0;
-		line_size = width * 3;
-		break;
-	default:
-		printf("LCD: Unknown bpp (%d) im image!\n", bpp);
-		if ((dst != NULL) && (dst != (uchar *)logo_bmp))
-			free(dst);
-		return 1;
-	}
-	printf(" (%d*%d, %dbpp)\n", width, height, bpp);
-
-	/*
-	 * Write color palette
-	 */
-	if ((colors <= 256) && (lcd_depth <= 8)) {
-		ptr = (unsigned char *)(dst + 14 + 40);
-		for (i = 0; i < colors; i++) {
-			b = *ptr++;
-			g = *ptr++;
-			r = *ptr++;
-			ptr++;
-			S1D_WRITE_PALETTE(glob_lcd_reg, i, r, g, b);
-		}
-	}
-
-	/*
-	 * Write bitmap data into framebuffer
-	 */
-	ptr = glob_lcd_mem;
-	ptr2 = (ushort *)glob_lcd_mem;
-	header_size = 14 + 40 + 4*colors;          /* skip bmp header */
-	for (y = 0; y < height; y++) {
-		bmp = &dst[(height-1-y)*line_size + header_size];
-		if (lcd_depth == 16) {
-			if (bpp == 24) {
-				for (x = 0; x < width; x++) {
-					/*
-					 * Generate epson 16bpp fb-format
-					 * from 24bpp image
-					 */
-					b = *bmp++ >> 3;
-					g = *bmp++ >> 2;
-					r = *bmp++ >> 3;
-					val = ((r & 0x1f) << 11) |
-						((g & 0x3f) << 5) |
-						(b & 0x1f);
-					*ptr2++ = val;
-				}
-			} else if (bpp == 8) {
-				for (x = 0; x < line_size; x++) {
-					/* query rgb value from palette */
-					ptr = (unsigned char *)(dst + 14 + 40);
-					ptr += (*bmp++) << 2;
-					b = *ptr++ >> 3;
-					g = *ptr++ >> 2;
-					r = *ptr++ >> 3;
-					val = ((r & 0x1f) << 11) |
-						((g & 0x3f) << 5) |
-						(b & 0x1f);
-					*ptr2++ = val;
-				}
-			}
-		} else {
-			for (x = 0; x < line_size; x++)
-				*ptr++ = *bmp++;
-		}
-	}
-
-	if ((dst != NULL) && (dst != (uchar *)logo_bmp))
-		free(dst);
-	return 0;
-}
-
-
-int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
-	     uchar *logo_bmp, ulong len)
-{
-	int i;
-	ushort s1dReg;
-	uchar s1dValue;
-	int reg_byte_swap;
-
-	/*
-	 * Detect epson
-	 */
-	out_8(&lcd_reg[0], 0x00);
-	out_8(&lcd_reg[1], 0x00);
-
-	if (in_8(&lcd_reg[0]) == 0x1c) {
-		/*
-		 * Big epson detected
-		 */
-		reg_byte_swap = false;
-		palette_index = 0x1e2;
-		palette_value = 0x1e4;
-		lcd_depth = 16;
-		puts("LCD:   S1D13806");
-	} else if (in_8(&lcd_reg[1]) == 0x1c) {
-		/*
-		 * Big epson detected (with register swap bug)
-		 */
-		reg_byte_swap = true;
-		palette_index = 0x1e3;
-		palette_value = 0x1e5;
-		lcd_depth = 16;
-		puts("LCD:   S1D13806S");
-	} else if (in_8(&lcd_reg[0]) == 0x18) {
-		/*
-		 * Small epson detected (704)
-		 */
-		reg_byte_swap = false;
-		palette_index = 0x15;
-		palette_value = 0x17;
-		lcd_depth = 8;
-		puts("LCD:   S1D13704");
-	} else if (in_8(&lcd_reg[0x10000]) == 0x24) {
-		/*
-		 * Small epson detected (705)
-		 */
-		reg_byte_swap = false;
-		palette_index = 0x15;
-		palette_value = 0x17;
-		lcd_depth = 8;
-		lcd_reg += 0x10000; /* add offset for 705 regs */
-		puts("LCD:   S1D13705");
-	} else {
-		out_8(&lcd_reg[0x1a], 0x00);
-		udelay(1000);
-		if (in_8(&lcd_reg[1]) == 0x0c) {
-			/*
-			 * S1D13505 detected
-			 */
-			reg_byte_swap = true;
-			palette_index = 0x25;
-			palette_value = 0x27;
-			lcd_depth = 16;
-
-			puts("LCD:   S1D13505");
-		} else {
-			puts("LCD:   No controller detected!\n");
-			return 1;
-		}
-	}
-
-	/*
-	 * Setup lcd controller regs
-	 */
-	for (i = 0; i < reg_count; i++) {
-		s1dReg = regs[i].Index;
-		if (reg_byte_swap) {
-			if ((s1dReg & 0x0001) == 0)
-				s1dReg |= 0x0001;
-			else
-				s1dReg &= ~0x0001;
-		}
-		s1dValue = regs[i].Value;
-		out_8(&lcd_reg[s1dReg], s1dValue);
-	}
-
-	/*
-	 * Save reg & mem pointer for later usage (e.g. bmp command)
-	 */
-	glob_lcd_reg = lcd_reg;
-	glob_lcd_mem = lcd_mem;
-
-	/*
-	 * Display bmp image
-	 */
-	return lcd_bmp(logo_bmp);
-}
-
-int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong addr;
-#ifdef CONFIG_VIDEO_SM501
-	char *str;
-#endif
-	if (argc != 2)
-		return cmd_usage(cmdtp);
-
-	addr = simple_strtoul(argv[1], NULL, 16);
-
-#ifdef CONFIG_VIDEO_SM501
-	str = getenv("bd_type");
-	if ((strcmp(str, "ppc221") == 0) || (strcmp(str, "ppc231") == 0)) {
-		/*
-		 * SM501 available, use standard bmp command
-		 */
-		return video_display_bitmap(addr, 0, 0);
-	} else {
-		/*
-		 * No SM501 available, use esd epson bmp command
-		 */
-		return lcd_bmp((uchar *)addr);
-	}
-#else
-	return lcd_bmp((uchar *)addr);
-#endif
-}
-
-U_BOOT_CMD(
-	esdbmp,	2,	1,	do_esdbmp,
-	"display BMP image",
-	"<imageAddr> - display image"
-);
diff --git a/board/esd/common/lcd.h b/board/esd/common/lcd.h
deleted file mode 100644
index 5b14bf9..0000000
--- a/board/esd/common/lcd.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Neutralize little endians.
- */
-#define SWAP_LONG(data) ((unsigned long)                                  \
-			 (((unsigned long)(data) >> 24)                 | \
-			  ((unsigned long)(data)  << 24)                | \
-			  (((unsigned long)(data) >> 8) & 0x0000ff00 )  | \
-			   (((unsigned long)(data) << 8) & 0x00ff0000 )))
-#define SWAP_SHORT(data) ((unsigned short)                                \
-			  (((unsigned short)(data) >> 8 )  |              \
-			   ((unsigned short)(data) << 8 )))
-#define LOAD_LONG(data)   SWAP_LONG(data)
-#define LOAD_SHORT(data)  SWAP_SHORT(data)
-
-#define S1D_WRITE_PALETTE(p,i,r,g,b)					\
-	{								\
-		out_8(&((uchar*)(p))[palette_index], (uchar)(i));	\
-		out_8(&((uchar*)(p))[palette_index], (uchar)(r));	\
-		out_8(&((uchar*)(p))[palette_index], (uchar)(g));	\
-		out_8(&((uchar*)(p))[palette_index], (uchar)(b));	\
-	}
-
-typedef struct
-{
-    ushort Index;
-    uchar  Value;
-} S1D_REGS;
-
-typedef struct                       /**** BMP file info structure ****/
-{
-	unsigned int   biSize;           /* Size of info header */
-	int            biWidth;          /* Width of image */
-	int            biHeight;         /* Height of image */
-	unsigned short biPlanes;         /* Number of color planes */
-	unsigned short biBitCount;       /* Number of bits per pixel */
-	unsigned int   biCompression;    /* Type of compression to use */
-	unsigned int   biSizeImage;      /* Size of image data */
-	int            biXPelsPerMeter;  /* X pixels per meter */
-	int            biYPelsPerMeter;  /* Y pixels per meter */
-	unsigned int   biClrUsed;        /* Number of colors used */
-	unsigned int   biClrImportant;   /* Number of important colors */
-} BITMAPINFOHEADER;
diff --git a/board/esd/common/misc.c b/board/esd/common/misc.c
deleted file mode 100644
index 79cd612..0000000
--- a/board/esd/common/misc.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * (C) Copyright 2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#ifdef CONFIG_LXT971_NO_SLEEP
-#include <miiphy.h>
-#endif
-
-
-#ifdef CONFIG_LXT971_NO_SLEEP
-void lxt971_no_sleep(void)
-{
-	unsigned short reg;
-
-	miiphy_read("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, &reg);
-	reg &= ~0x0040;                  /* disable sleep mode */
-	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, reg);
-}
-#endif /* CONFIG_LXT971_NO_SLEEP */
diff --git a/board/esd/common/pci.c b/board/esd/common/pci.c
deleted file mode 100644
index faebdb1..0000000
--- a/board/esd/common/pci.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <pci.h>
-
-
-u_long pci9054_iobase;
-
-
-#define PCI_PRIMARY_CAR	(0x500000dc) /* PCI config address reg */
-#define PCI_PRIMARY_CDR	(0x80000000) /* PCI config data    reg */
-
-
-/*-----------------------------------------------------------------------------+
-|  Subroutine:  pci9054_read_config_dword
-|  Description: Read a PCI configuration register
-|  Inputs:
-|               hose            PCI Controller
-|               dev             PCI Bus+Device+Function number
-|               offset          Configuration register number
-|               value           Address of the configuration register value
-|  Return value:
-|               0               Successful
-+-----------------------------------------------------------------------------*/
-int pci9054_read_config_dword(struct pci_controller *hose,
-			      pci_dev_t dev, int offset, u32* value)
-{
-  unsigned long      conAdrVal;
-  unsigned long      val;
-
-  /* generate coded value for CON_ADR register */
-  conAdrVal = dev | (offset & 0xfc) | 0x80000000;
-
-  /* Load the CON_ADR (CAR) value first, then read from CON_DATA (CDR) */
-  *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
-
-  /* Note: *pResult comes back as -1 if machine check happened */
-  val = in32r(PCI_PRIMARY_CDR);
-
-  *value = (unsigned long) val;
-
-  out32r(PCI_PRIMARY_CAR, 0);
-
-  if ((*(unsigned long *)0x50000304) & 0x60000000)
-    {
-      /* clear pci master/target abort bits */
-      *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
-    }
-
-  return 0;
-}
-
-/*-----------------------------------------------------------------------------+
-|  Subroutine:  pci9054_write_config_dword
-|  Description: Write a PCI configuration register.
-|  Inputs:
-|               hose            PCI Controller
-|               dev             PCI Bus+Device+Function number
-|               offset          Configuration register number
-|               Value           Configuration register value
-|  Return value:
-|               0               Successful
-| Updated for pass2 errata #6. Need to disable interrupts and clear the
-| PCICFGADR reg after writing the PCICFGDATA reg.
-+-----------------------------------------------------------------------------*/
-int pci9054_write_config_dword(struct pci_controller *hose,
-			       pci_dev_t dev, int offset, u32 value)
-{
-  unsigned long      conAdrVal;
-
-  conAdrVal = dev | (offset & 0xfc) | 0x80000000;
-
-  *(unsigned long *)PCI_PRIMARY_CAR = conAdrVal;
-
-  out32r(PCI_PRIMARY_CDR, value);
-
-  out32r(PCI_PRIMARY_CAR, 0);
-
-  /* clear pci master/target abort bits */
-  *(unsigned long *)0x50000304 = *(unsigned long *)0x50000304;
-
-  return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-#ifdef CONFIG_DASA_SIM
-static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t dev,
-					struct pci_config_table *_)
-{
-  unsigned int iobase;
-  unsigned short status = 0;
-  unsigned char timer;
-
-  /*
-   * Configure PLX PCI9054
-   */
-  pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status);
-  status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
-  pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status);
-
-  /* Check the latency timer for values >= 0x60.
-   */
-  pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
-  if (timer < 0x60)
-    {
-      pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
-    }
-
-  /* Set I/O base register.
-   */
-  pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE);
-  pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
-
-  pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
-
-  if (pci9054_iobase == 0xffffffff)
-    {
-      printf("Error: Can not set I/O base register.\n");
-      return;
-    }
-}
-#endif
-
-static struct pci_config_table pci9054_config_table[] = {
-#ifndef CONFIG_PCI_PNP
-  { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-    PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN),
-    pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE,
-				 CONFIG_SYS_ETH_IOBASE,
-				 PCI_COMMAND_IO | PCI_COMMAND_MASTER }},
-#ifdef CONFIG_DASA_SIM
-  { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-    PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN),
-    pci_dasa_sim_config_pci9054 },
-#endif
-#endif
-  { }
-};
-
-static struct pci_controller pci9054_hose = {
-  config_table: pci9054_config_table,
-};
-
-void pci_init_board(void)
-{
-  struct pci_controller *hose = &pci9054_hose;
-
-  /*
-   * Register the hose
-   */
-  hose->first_busno = 0;
-  hose->last_busno = 0xff;
-
-  /* System memory space */
-  pci_set_region(hose->regions + 0,
-		 0x00000000, 0x00000000, 0x01000000,
-		 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
-  /* PCI Memory space */
-  pci_set_region(hose->regions + 1,
-		 0x00000000, 0xc0000000, 0x10000000,
-		 PCI_REGION_MEM);
-
-  pci_set_ops(hose,
-	      pci_hose_read_config_byte_via_dword,
-	      pci_hose_read_config_word_via_dword,
-	      pci9054_read_config_dword,
-	      pci_hose_write_config_byte_via_dword,
-	      pci_hose_write_config_word_via_dword,
-	      pci9054_write_config_dword);
-
-  hose->region_count = 2;
-
-  pci_register_hose(hose);
-
-  hose->last_busno = pci_hose_scan(hose);
-}
diff --git a/board/esd/common/s1d13505_640_480_16bpp.h b/board/esd/common/s1d13505_640_480_16bpp.h
deleted file mode 100644
index ca11683..0000000
--- a/board/esd/common/s1d13505_640_480_16bpp.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * (C) Copyright 2008
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * Panel:  640x480 50Hz TFT Single 18-bit (PCLK=20.000 MHz)
- * Memory:  DRAM (MCLK=40.000 MHz)
- */
-static S1D_REGS regs_13505_640_480_16bpp[] =
-{
-	{0x1B,0x00},   /* Miscellaneous Register */
-	{0x23,0x20},   /* Performance Enhancement Register 1 */
-	{0x01,0x30},   /* Memory Configuration Register */
-	{0x22,0x24},   /* Performance Enhancement Register 0 */
-	{0x02,0x25},   /* Panel Type Register */
-	{0x03,0x00},   /* MOD Rate Register */
-	{0x04,0x4F},   /* Horizontal Display Width Register */
-	{0x05,0x0c},   /* Horizontal Non-Display Period Register */
-	{0x06,0x00},   /* HRTC/FPLINE Start Position Register */
-	{0x07,0x01},   /* HRTC/FPLINE Pulse Width Register */
-	{0x08,0xDF},   /* Vertical Display Height Register 0 */
-	{0x09,0x01},   /* Vertical Display Height Register 1 */
-	{0x0A,0x3E},   /* Vertical Non-Display Period Register */
-	{0x0B,0x00},   /* VRTC/FPFRAME Start Position Register */
-	{0x0C,0x01},   /* VRTC/FPFRAME Pulse Width Register */
-	{0x0E,0xFF},   /* Screen 1 Line Compare Register 0 */
-	{0x0F,0x03},   /* Screen 1 Line Compare Register 1 */
-	{0x10,0x00},   /* Screen 1 Display Start Address Register 0 */
-	{0x11,0x00},   /* Screen 1 Display Start Address Register 1 */
-	{0x12,0x00},   /* Screen 1 Display Start Address Register 2 */
-	{0x13,0x00},   /* Screen 2 Display Start Address Register 0 */
-	{0x14,0x00},   /* Screen 2 Display Start Address Register 1 */
-	{0x15,0x00},   /* Screen 2 Display Start Address Register 2 */
-	{0x16,0x80},   /* Memory Address Offset Register 0 */
-	{0x17,0x02},   /* Memory Address Offset Register 1 */
-	{0x18,0x00},   /* Pixel Panning Register */
-	{0x19,0x01},   /* Clock Configuration Register */
-	{0x1A,0x00},   /* Power Save Configuration Register */
-	{0x1C,0x00},   /* MD Configuration Readback Register 0 */
-	{0x1E,0x06},   /* General IO Pins Configuration Register 0 */
-	{0x1F,0x00},   /* General IO Pins Configuration Register 1 */
-	{0x20,0x00},   /* General IO Pins Control Register 0 */
-	{0x21,0x00},   /* General IO Pins Control Register 1 */
-	{0x23,0x20},   /* Performance Enhancement Register 1 */
-	{0x0D,0x15},   /* Display Mode Register */
-};
diff --git a/board/esd/common/s1d13704_320_240_4bpp.h b/board/esd/common/s1d13704_320_240_4bpp.h
deleted file mode 100644
index bd910e8..0000000
--- a/board/esd/common/s1d13704_320_240_4bpp.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Generic Header information generated by 13704CFG.EXE (Build 10)
- * Panel: 320x240x4bpp 78Hz Mono 4-Bit STN, Disabled (PCLK=6.666MHz)
- */
-
-static S1D_REGS regs_13704_320_240_4bpp[] =
-{
-	{ 0x00,             0x00 },       /* Revision Code Register */
-	{ 0x01,             0x04 }, /*00*/      /* Mode Register 0 Register */
-	{ 0x02,             0xA4 }, /*a0*/      /* Mode Register 1 Register */
-	{ 0x03,             0x83 }, /*03*/      /* Mode Register 2 Register - bit7 is LUT bypass */
-	{ 0x04,             0x27 },       /* Horizontal Panel Size Register */
-	{ 0x05,             0xEF },       /* Vertical Panel Size Register (LSB) */
-	{ 0x06,             0x00 },       /* Vertical Panel Size Register (MSB) */
-	{ 0x07,             0x00 },       /* FPLINE Start Position Register */
-	{ 0x08,             0x00 },       /* Horizontal Non-Display Period Register */
-	{ 0x09,             0x00 },       /* FPFRAME Start Position Register */
-	{ 0x0A,             0x02 },       /* Vertical Non-Display Period Register */
-	{ 0x0B,             0x00 },       /* MOD Rate Register */
-	{ 0x0C,             0x00 },       /* Screen 1 Start Address Register (LSB) */
-	{ 0x0D,             0x00 },       /* Screen 1 Start Address Register (MSB) */
-	{ 0x0E,             0x00 },       /* Not Used */
-	{ 0x0F,             0x00 },       /* Screen 2 Start Address Register (LSB) */
-	{ 0x10,             0x00 },       /* Screen 2 Start Address Register (MSB) */
-	{ 0x11,             0x00 },       /* Not Used */
-	{ 0x12,             0x00 },       /* Memory Address Offset Register */
-	{ 0x13,             0xFF },       /* Screen 1 Vertical Size Register (LSB) */
-	{ 0x14,             0x03 },       /* Screen 1 Vertical Size Register (MSB) */
-	{ 0x15,             0x00 },       /* Look-Up Table Address Register */
-	{ 0x16,             0x00 },       /* Look-Up Table Bank Select Register */
-	{ 0x17,             0x00 },       /* Look-Up Table Data Register */
-	{ 0x18,             0x01 },       /* GPIO Configuration Control Register */
-	{ 0x19,             0x01 },       /* GPIO Status/Control Register */
-	{ 0x1A,             0x00 },       /* Scratch Pad Register */
-	{ 0x1B,             0x00 },       /* SwivelView Mode Register */
-	{ 0x1C,             0xA0 },       /* Line Byte Count Register */
-	{ 0x1D,             0x00 },       /* Not Used */
-	{ 0x1E,             0x00 },       /* Not Used */
-	{ 0x1F,             0x00 },       /* Not Used */
-};
diff --git a/board/esd/common/s1d13705_320_240_8bpp.h b/board/esd/common/s1d13705_320_240_8bpp.h
deleted file mode 100644
index 041b4a9..0000000
--- a/board/esd/common/s1d13705_320_240_8bpp.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Generic Header information generated by 13704CFG.EXE (Build 10)
- * Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz)
- */
-
-static S1D_REGS regs_13705_320_240_8bpp[] =
-{
-	{ 0x00,             0x00 },       /* Revision Code Register */
-	{ 0x01,             0x23 },       /* Mode Register 0 Register */
-	{ 0x02,             0xE0 },       /* Mode Register 1 Register */
-	{ 0x03,             0x03 },       /* Mode Register 2 Register - bit7 is LUT bypass */
-	{ 0x04,             0x27 },       /* Horizontal Panel Size Register */
-	{ 0x05,             0xEF },       /* Vertical Panel Size Register (LSB) */
-	{ 0x06,             0x00 },       /* Vertical Panel Size Register (MSB) */
-	{ 0x07,             0x00 },       /* FPLINE Start Position Register */
-	{ 0x08,             0x00 },       /* Horizontal Non-Display Period Register */
-	{ 0x09,             0x01 },       /* FPFRAME Start Position Register */
-	{ 0x0A,             0x02 },       /* Vertical Non-Display Period Register */
-	{ 0x0B,             0x00 },       /* MOD Rate Register */
-	{ 0x0C,             0x00 },       /* Screen 1 Start Address Register (LSB) */
-	{ 0x0D,             0x00 },       /* Screen 1 Start Address Register (MSB) */
-	{ 0x0E,             0x00 },       /* Not Used */
-	{ 0x0F,             0x00 },       /* Screen 2 Start Address Register (LSB) */
-	{ 0x10,             0x00 },       /* Screen 2 Start Address Register (MSB) */
-	{ 0x11,             0x00 },       /* Not Used */
-	{ 0x12,             0x00 },       /* Memory Address Offset Register */
-	{ 0x13,             0xFF },       /* Screen 1 Vertical Size Register (LSB) */
-	{ 0x14,             0x03 },       /* Screen 1 Vertical Size Register (MSB) */
-	{ 0x15,             0x00 },       /* Look-Up Table Address Register */
-	{ 0x16,             0x00 },       /* Look-Up Table Bank Select Register */
-	{ 0x17,             0x00 },       /* Look-Up Table Data Register */
-	{ 0x18,             0x01 },       /* GPIO Configuration Control Register */
-	{ 0x19,             0x01 },       /* GPIO Status/Control Register */
-	{ 0x1A,             0x00 },       /* Scratch Pad Register */
-	{ 0x1B,             0x00 },       /* SwivelView Mode Register */
-	{ 0x1C,             0xFF },       /* Line Byte Count Register */
-	{ 0x1D,             0x00 },       /* Not Used */
-	{ 0x1E,             0x00 },       /* Not Used */
-	{ 0x1F,             0x00 },       /* Not Used */
-};
diff --git a/board/esd/common/s1d13806_1024_768_8bpp.h b/board/esd/common/s1d13806_1024_768_8bpp.h
deleted file mode 100644
index 615fa33..0000000
--- a/board/esd/common/s1d13806_1024_768_8bpp.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * File generated by S1D13806CFG.EXE
- * Panel:  (active)   1024x768 34Hz TFT Single 12-bit (PCLK=BUSCLK=33.333MHz)
- * Memory: Embedded SDRAM (MCLK=CLKI=49.100MHz) (BUSCLK=33.333MHz)
- */
-
-static S1D_REGS regs_13806_1024_768_8bpp[] =
-{
-	{0x0001,0x00},   /* Miscellaneous Register */
-	{0x01FC,0x00},   /* Display Mode Register */
-	{0x0004,0x00},   /* General IO Pins Configuration Register 0 */
-	{0x0005,0x00},   /* General IO Pins Configuration Register 1 */
-	{0x0008,0x00},   /* General IO Pins Control Register 0 */
-	{0x0009,0x00},   /* General IO Pins Control Register 1 */
-	{0x0010,0x00},   /* Memory Clock Configuration Register */
-	{0x0014,0x01},   /* LCD Pixel Clock Configuration Register */
-	{0x0018,0x00},   /* CRT/TV Pixel Clock Configuration Register */
-	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
-	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
-	{0x0021,0x03},   /* DRAM Refresh Rate Register */
-	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
-	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
-	{0x0020,0x80},   /* Memory Configuration Register */
-	{0x0030,0x55},   /* Panel Type Register */
-	{0x0031,0x00},   /* MOD Rate Register */
-	{0x0032,0x7F},   /* LCD Horizontal Display Width Register */
-	{0x0034,0x12},   /* LCD Horizontal Non-Display Period Register */
-	{0x0035,0x01},   /* TFT FPLINE Start Position Register */
-	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
-	{0x0038,0xFF},   /* LCD Vertical Display Height Register 0 */
-	{0x0039,0x02},   /* LCD Vertical Display Height Register 1 */
-	{0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
-	{0x003B,0x0A},   /* TFT FPFRAME Start Position Register */
-	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
-	{0x0040,0x03},   /* LCD Display Mode Register */
-	{0x0041,0x00},   /* LCD Miscellaneous Register */
-	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
-	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
-	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
-	{0x0046,0x00},   /* LCD Memory Address Offset Register 0 */
-	{0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
-	{0x0048,0x00},   /* LCD Pixel Panning Register */
-	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
-	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
-	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
-	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
-	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
-	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
-	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
-	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
-	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
-	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
-	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
-	{0x005B,0x10},   /* TV Output Control Register */
-	{0x0060,0x03},   /* CRT/TV Display Mode Register */
-	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
-	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
-	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
-	{0x0066,0x40},   /* CRT/TV Memory Address Offset Register 0 */
-	{0x0067,0x01},   /* CRT/TV Memory Address Offset Register 1 */
-	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
-	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
-	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
-	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
-	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
-	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
-	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
-	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
-	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
-	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
-	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
-	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
-	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
-	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
-	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
-	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
-	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
-	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
-	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
-	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
-	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
-	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
-	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
-	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
-	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
-	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
-	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
-	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
-	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
-	{0x0100,0x00},   /* BitBlt Control Register 0 */
-	{0x0101,0x00},   /* BitBlt Control Register 1 */
-	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
-	{0x0103,0x00},   /* BitBlt Operation Register */
-	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
-	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
-	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
-	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
-	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
-	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
-	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
-	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
-	{0x0110,0x00},   /* BitBlt Width Register 0 */
-	{0x0111,0x00},   /* BitBlt Width Register 1 */
-	{0x0112,0x00},   /* BitBlt Height Register 0 */
-	{0x0113,0x00},   /* BitBlt Height Register 1 */
-	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
-	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
-	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
-	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
-	{0x01E0,0x00},   /* Look-Up Table Mode Register */
-	{0x01E2,0x00},   /* Look-Up Table Address Register */
-	{0x01F0,0x10},   /* Power Save Configuration Register */
-	{0x01F1,0x00},   /* Power Save Status Register */
-	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
-	{0x01FC,0x01},   /* Display Mode Register */
-};
diff --git a/board/esd/common/s1d13806_320_240_4bpp.h b/board/esd/common/s1d13806_320_240_4bpp.h
deleted file mode 100644
index 2531f47..0000000
--- a/board/esd/common/s1d13806_320_240_4bpp.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * File generated by S1D13806CFG.EXE
- * Panel:  (active)   320x240 62Hz STN Single 4-bit (PCLK=CLKI2/4=6.250MHz)
- * Memory: Embedded SDRAM (MCLK=CLKI=49.500MHz) (BUSCLK=33.333MHz)
- */
-
-static S1D_REGS regs_13806_320_240_4bpp[] =
-{
-	{0x0001,0x00},   /* Miscellaneous Register */
-	{0x01FC,0x00},   /* Display Mode Register */
-	{0x0004,0x08},   /* General IO Pins Configuration Register 0 */
-	{0x0005,0x08},   /* General IO Pins Configuration Register 1 */
-	{0x0008,0x08},   /* General IO Pins Control Register 0 */
-	{0x0009,0x00},   /* General IO Pins Control Register 1 */
-	{0x0010,0x00},   /* Memory Clock Configuration Register */
-	{0x0014,0x32},   /* LCD Pixel Clock Configuration Register */
-	{0x0018,0x00},   /* CRT/TV Pixel Clock Configuration Register */
-	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
-	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
-	{0x0021,0x03},   /* DRAM Refresh Rate Register */
-	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
-	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
-	{0x0020,0x80},   /* Memory Configuration Register */
-	{0x0030,0x00},   /* Panel Type Register */
-	{0x0031,0x00},   /* MOD Rate Register */
-	{0x0032,0x27},   /* LCD Horizontal Display Width Register */
-	{0x0034,0x03},   /* LCD Horizontal Non-Display Period Register */
-	{0x0035,0x01},   /* TFT FPLINE Start Position Register */
-	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
-	{0x0038,0xEF},   /* LCD Vertical Display Height Register 0 */
-	{0x0039,0x00},   /* LCD Vertical Display Height Register 1 */
-	{0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
-	{0x003B,0x0A},   /* TFT FPFRAME Start Position Register */
-	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
-	{0x0040,0x02},   /* LCD Display Mode Register */
-	{0x0041,0x00},   /* LCD Miscellaneous Register */
-	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
-	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
-	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
-	{0x0046,0x50},   /* LCD Memory Address Offset Register 0 */
-	{0x0047,0x00},   /* LCD Memory Address Offset Register 1 */
-	{0x0048,0x00},   /* LCD Pixel Panning Register */
-	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
-	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
-	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
-	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
-	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
-	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
-	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
-	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
-	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
-	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
-	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
-	{0x005B,0x10},   /* TV Output Control Register */
-	{0x0060,0x03},   /* CRT/TV Display Mode Register */
-	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
-	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
-	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
-	{0x0066,0x40},   /* CRT/TV Memory Address Offset Register 0 */
-	{0x0067,0x01},   /* CRT/TV Memory Address Offset Register 1 */
-	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
-	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
-	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
-	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
-	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
-	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
-	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
-	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
-	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
-	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
-	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
-	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
-	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
-	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
-	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
-	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
-	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
-	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
-	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
-	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
-	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
-	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
-	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
-	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
-	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
-	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
-	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
-	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
-	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
-	{0x0100,0x00},   /* BitBlt Control Register 0 */
-	{0x0101,0x00},   /* BitBlt Control Register 1 */
-	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
-	{0x0103,0x00},   /* BitBlt Operation Register */
-	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
-	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
-	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
-	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
-	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
-	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
-	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
-	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
-	{0x0110,0x00},   /* BitBlt Width Register 0 */
-	{0x0111,0x00},   /* BitBlt Width Register 1 */
-	{0x0112,0x00},   /* BitBlt Height Register 0 */
-	{0x0113,0x00},   /* BitBlt Height Register 1 */
-	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
-	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
-	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
-	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
-	{0x01E0,0x00},   /* Look-Up Table Mode Register */
-	{0x01E2,0x00},   /* Look-Up Table Address Register */
-	{0x01F0,0x10},   /* Power Save Configuration Register */
-	{0x01F1,0x00},   /* Power Save Status Register */
-	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
-	{0x01FC,0x01},   /* Display Mode Register */
-};
diff --git a/board/esd/common/s1d13806_640_480_16bpp.h b/board/esd/common/s1d13806_640_480_16bpp.h
deleted file mode 100644
index 38fc1a7..0000000
--- a/board/esd/common/s1d13806_640_480_16bpp.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright (c) 2000,2001 Epson Research and Development, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * File generated by S1D13806CFG.EXE
- * Panel:  (active)   640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz)
- * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz)
- */
-
-static S1D_REGS regs_13806_640_480_16bpp[] =
-{
-	{0x0001,0x00},   /* Miscellaneous Register */
-	{0x01FC,0x00},   /* Display Mode Register */
-	{0x0004,0x18},   /* General IO Pins Configuration Register 0 */
-	{0x0005,0x00},   /* General IO Pins Configuration Register 1 */
-	{0x0008,0x18},   /* General IO Pins Control Register 0 */
-	{0x0009,0x00},   /* General IO Pins Control Register 1 */
-	{0x0010,0x00},   /* Memory Clock Configuration Register */
-	{0x0014,0x02},   /* LCD Pixel Clock Configuration Register */
-	{0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
-	{0x001C,0x02},   /* MediaPlug Clock Configuration Register */
-	{0x001E,0x01},   /* CPU To Memory Wait State Select Register */
-	{0x0021,0x03},   /* DRAM Refresh Rate Register */
-	{0x002A,0x00},   /* DRAM Timings Control Register 0 */
-	{0x002B,0x01},   /* DRAM Timings Control Register 1 */
-	{0x0020,0x80},   /* Memory Configuration Register */
-	{0x0030,0x25},   /* Panel Type Register */
-	{0x0031,0x00},   /* MOD Rate Register */
-	{0x0032,0x4F},   /* LCD Horizontal Display Width Register */
-	{0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
-	{0x0035,0x00},   /* TFT FPLINE Start Position Register */
-	{0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
-	{0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
-	{0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
-	{0x003A,0x24},   /* LCD Vertical Non-Display Period Register */
-	{0x003B,0x00},   /* TFT FPFRAME Start Position Register */
-	{0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
-	{0x0040,0x05},   /* LCD Display Mode Register */
-	{0x0041,0x00},   /* LCD Miscellaneous Register */
-	{0x0042,0x00},   /* LCD Display Start Address Register 0 */
-	{0x0043,0x00},   /* LCD Display Start Address Register 1 */
-	{0x0044,0x00},   /* LCD Display Start Address Register 2 */
-	{0x0046,0x80},   /* LCD Memory Address Offset Register 0 */
-	{0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
-	{0x0048,0x00},   /* LCD Pixel Panning Register */
-	{0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
-	{0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
-	{0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
-	{0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
-	{0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
-	{0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
-	{0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
-	{0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
-	{0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
-	{0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
-	{0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
-	{0x005B,0x10},   /* TV Output Control Register */
-	{0x0060,0x05},   /* CRT/TV Display Mode Register */
-	{0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
-	{0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
-	{0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
-	{0x0066,0x80},   /* CRT/TV Memory Address Offset Register 0 */
-	{0x0067,0x02},   /* CRT/TV Memory Address Offset Register 1 */
-	{0x0068,0x00},   /* CRT/TV Pixel Panning Register */
-	{0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
-	{0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
-	{0x0070,0x00},   /* LCD Ink/Cursor Control Register */
-	{0x0071,0x01},   /* LCD Ink/Cursor Start Address Register */
-	{0x0072,0x00},   /* LCD Cursor X Position Register 0 */
-	{0x0073,0x00},   /* LCD Cursor X Position Register 1 */
-	{0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
-	{0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
-	{0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
-	{0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
-	{0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
-	{0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
-	{0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
-	{0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
-	{0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
-	{0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
-	{0x0081,0x01},   /* CRT/TV Ink/Cursor Start Address Register */
-	{0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
-	{0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
-	{0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
-	{0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
-	{0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
-	{0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
-	{0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
-	{0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
-	{0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
-	{0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
-	{0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
-	{0x0100,0x00},   /* BitBlt Control Register 0 */
-	{0x0101,0x00},   /* BitBlt Control Register 1 */
-	{0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
-	{0x0103,0x00},   /* BitBlt Operation Register */
-	{0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
-	{0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
-	{0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
-	{0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
-	{0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
-	{0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
-	{0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
-	{0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
-	{0x0110,0x00},   /* BitBlt Width Register 0 */
-	{0x0111,0x00},   /* BitBlt Width Register 1 */
-	{0x0112,0x00},   /* BitBlt Height Register 0 */
-	{0x0113,0x00},   /* BitBlt Height Register 1 */
-	{0x0114,0x00},   /* BitBlt Background Color Register 0 */
-	{0x0115,0x00},   /* BitBlt Background Color Register 1 */
-	{0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
-	{0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
-	{0x01E0,0x00},   /* Look-Up Table Mode Register */
-	{0x01E2,0x00},   /* Look-Up Table Address Register */
-	{0x01F0,0x10},   /* Power Save Configuration Register */
-	{0x01F1,0x00},   /* Power Save Status Register */
-	{0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
-	{0x01FC,0x01},   /* Display Mode Register */
-};
diff --git a/board/esd/common/xilinx_jtag/lenval.c b/board/esd/common/xilinx_jtag/lenval.c
deleted file mode 100644
index 5405efb..0000000
--- a/board/esd/common/xilinx_jtag/lenval.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*******************************************************/
-/* file: lenval.c                                      */
-/* abstract:  This file contains routines for using    */
-/*            the lenVal data structure.               */
-/*******************************************************/
-
-#include <common.h>
-#include <asm/processor.h>
-
-#include "lenval.h"
-#include "ports.h"
-
-
-/*****************************************************************************
- * Function:     value
- * Description:  Extract the long value from the lenval array.
- * Parameters:   plvValue    - ptr to lenval.
- * Returns:      long        - the extracted value.
- *****************************************************************************/
-long value( lenVal*     plvValue )
-{
-	long    lValue;         /* result to hold the accumulated result */
-	short   sIndex;
-
-	lValue  = 0;
-	for ( sIndex = 0; sIndex < plvValue->len ; ++sIndex )
-	{
-		lValue <<= 8;                       /* shift the accumulated result */
-		lValue |= plvValue->val[ sIndex];   /* get the last byte first */
-	}
-
-	return( lValue );
-}
-
-/*****************************************************************************
- * Function:     initLenVal
- * Description:  Initialize the lenval array with the given value.
- *               Assumes lValue is less than 256.
- * Parameters:   plv         - ptr to lenval.
- *               lValue      - the value to set.
- * Returns:      void.
- *****************************************************************************/
-void initLenVal( lenVal*    plv,
-		 long       lValue )
-{
-	plv->len    = 1;
-	plv->val[0] = (unsigned char)lValue;
-}
-
-/*****************************************************************************
- * Function:     EqualLenVal
- * Description:  Compare two lenval arrays with an optional mask.
- * Parameters:   plvTdoExpected  - ptr to lenval #1.
- *               plvTdoCaptured  - ptr to lenval #2.
- *               plvTdoMask      - optional ptr to mask (=0 if no mask).
- * Returns:      short   - 0 = mismatch; 1 = equal.
- *****************************************************************************/
-short EqualLenVal( lenVal*  plvTdoExpected,
-		   lenVal*  plvTdoCaptured,
-		   lenVal*  plvTdoMask )
-{
-	short           sEqual;
-	short           sIndex;
-	unsigned char   ucByteVal1;
-	unsigned char   ucByteVal2;
-	unsigned char   ucByteMask;
-
-	sEqual  = 1;
-	sIndex  = plvTdoExpected->len;
-
-	while ( sEqual && sIndex-- )
-	{
-		ucByteVal1  = plvTdoExpected->val[ sIndex ];
-		ucByteVal2  = plvTdoCaptured->val[ sIndex ];
-		if ( plvTdoMask )
-		{
-			ucByteMask  = plvTdoMask->val[ sIndex ];
-			ucByteVal1  &= ucByteMask;
-			ucByteVal2  &= ucByteMask;
-		}
-		if ( ucByteVal1 != ucByteVal2 )
-		{
-			sEqual  = 0;
-		}
-	}
-
-	return( sEqual );
-}
-
-
-/*****************************************************************************
- * Function:     RetBit
- * Description:  return the (byte, bit) of lv (reading from left to right).
- * Parameters:   plv     - ptr to lenval.
- *               iByte   - the byte to get the bit from.
- *               iBit    - the bit number (0=msb)
- * Returns:      short   - the bit value.
- *****************************************************************************/
-short RetBit( lenVal*   plv,
-	      int       iByte,
-	      int       iBit )
-{
-	/* assert( ( iByte >= 0 ) && ( iByte < plv->len ) ); */
-	/* assert( ( iBit >= 0 ) && ( iBit < 8 ) ); */
-	return( (short)( ( plv->val[ iByte ] >> ( 7 - iBit ) ) & 0x1 ) );
-}
-
-/*****************************************************************************
- * Function:     SetBit
- * Description:  set the (byte, bit) of lv equal to val
- * Example:      SetBit("00000000",byte, 1) equals "01000000".
- * Parameters:   plv     - ptr to lenval.
- *               iByte   - the byte to get the bit from.
- *               iBit    - the bit number (0=msb).
- *               sVal    - the bit value to set.
- * Returns:      void.
- *****************************************************************************/
-void SetBit( lenVal*    plv,
-	     int        iByte,
-	     int        iBit,
-	     short      sVal )
-{
-	unsigned char   ucByteVal;
-	unsigned char   ucBitMask;
-
-	ucBitMask   = (unsigned char)(1 << ( 7 - iBit ));
-	ucByteVal   = (unsigned char)(plv->val[ iByte ] & (~ucBitMask));
-
-	if ( sVal )
-	{
-		ucByteVal   |= ucBitMask;
-	}
-	plv->val[ iByte ]   = ucByteVal;
-}
-
-/*****************************************************************************
- * Function:     AddVal
- * Description:  add val1 to val2 and store in resVal;
- *               assumes val1 and val2  are of equal length.
- * Parameters:   plvResVal   - ptr to result.
- *               plvVal1     - ptr of addendum.
- *               plvVal2     - ptr of addendum.
- * Returns:      void.
- *****************************************************************************/
-void addVal( lenVal*    plvResVal,
-	     lenVal*    plvVal1,
-	     lenVal*    plvVal2 )
-{
-	unsigned char   ucCarry;
-	unsigned short  usSum;
-	unsigned short  usVal1;
-	unsigned short  usVal2;
-	short           sIndex;
-
-	plvResVal->len  = plvVal1->len;         /* set up length of result */
-
-	/* start at least significant bit and add bytes    */
-	ucCarry = 0;
-	sIndex  = plvVal1->len;
-	while ( sIndex-- )
-	{
-		usVal1  = plvVal1->val[ sIndex ];   /* i'th byte of val1 */
-		usVal2  = plvVal2->val[ sIndex ];   /* i'th byte of val2 */
-
-		/* add the two bytes plus carry from previous addition */
-		usSum   = (unsigned short)( usVal1 + usVal2 + ucCarry );
-
-		/* set up carry for next byte */
-		ucCarry = (unsigned char)( ( usSum > 255 ) ? 1 : 0 );
-
-		/* set the i'th byte of the result */
-		plvResVal->val[ sIndex ]    = (unsigned char)usSum;
-	}
-}
-
-/*****************************************************************************
- * Function:     readVal
- * Description:  read from XSVF numBytes bytes of data into x.
- * Parameters:   plv         - ptr to lenval in which to put the bytes read.
- *               sNumBytes   - the number of bytes to read.
- * Returns:      void.
- *****************************************************************************/
-void readVal( lenVal*   plv,
-	      short     sNumBytes )
-{
-	unsigned char*  pucVal;
-
-	plv->len    = sNumBytes;        /* set the length of the lenVal        */
-	for ( pucVal = plv->val; sNumBytes; --sNumBytes, ++pucVal )
-	{
-		/* read a byte of data into the lenVal */
-		readByte( pucVal );
-	}
-}
diff --git a/board/esd/common/xilinx_jtag/lenval.h b/board/esd/common/xilinx_jtag/lenval.h
deleted file mode 100644
index 3273eec..0000000
--- a/board/esd/common/xilinx_jtag/lenval.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*******************************************************/
-/* file: lenval.h                                      */
-/* abstract:  This file contains a description of the  */
-/*            data structure "lenval".                 */
-/*******************************************************/
-
-#ifndef lenval_dot_h
-#define lenval_dot_h
-
-/* the lenVal structure is a byte oriented type used to store an */
-/* arbitrary length binary value. As an example, the hex value   */
-/* 0x0e3d is represented as a lenVal with len=2 (since 2 bytes   */
-/* and val[0]=0e and val[1]=3d.  val[2-MAX_LEN] are undefined    */
-
-/* maximum length (in bytes) of value to read in        */
-/* this needs to be at least 4, and longer than the     */
-/* length of the longest SDR instruction.  If there is, */
-/* only 1 device in the chain, MAX_LEN must be at least */
-/* ceil(27/8) == 4.  For 6 devices in a chain, MAX_LEN  */
-/* must be 5, for 14 devices MAX_LEN must be 6, for 20  */
-/* devices MAX_LEN must be 7, etc..                     */
-/* You can safely set MAX_LEN to a smaller number if you*/
-/* know how many devices will be in your chain.         */
-#define MAX_LEN 7000
-
-
-typedef struct var_len_byte
-{
-	short len;   /* number of chars in this value */
-	unsigned char val[MAX_LEN+1];  /* bytes of data */
-} lenVal;
-
-
-/* return the long representation of a lenVal */
-extern long value(lenVal *x);
-
-/* set lenVal equal to value */
-extern void initLenVal(lenVal *x, long value);
-
-/* check if expected equals actual (taking the mask into account) */
-extern short EqualLenVal(lenVal *expected, lenVal *actual, lenVal *mask);
-
-/* add val1+val2 and put the result in resVal */
-extern void addVal(lenVal *resVal, lenVal *val1, lenVal *val2);
-
-/* return the (byte, bit) of lv (reading from left to right) */
-extern short RetBit(lenVal *lv, int byte, int bit);
-
-/* set the (byte, bit) of lv equal to val (e.g. SetBit("00000000",byte, 1)
-   equals "01000000" */
-extern void SetBit(lenVal *lv, int byte, int bit, short val);
-
-/* read from XSVF numBytes bytes of data into x */
-extern void  readVal(lenVal *x, short numBytes);
-
-#endif
diff --git a/board/esd/common/xilinx_jtag/micro.c b/board/esd/common/xilinx_jtag/micro.c
deleted file mode 100644
index 556636c..0000000
--- a/board/esd/common/xilinx_jtag/micro.c
+++ /dev/null
@@ -1,1854 +0,0 @@
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*****************************************************************************
- * file:         micro.c
- * abstract:     This file contains the function, xsvfExecute(),
- *               call for interpreting the XSVF commands.
- * Usage:        Call xsvfExecute() to process XSVF data.
- *               The XSVF data is retrieved by readByte() in ports.c
- *               Remove the main function if you already have one.
- * Options:      XSVF_SUPPORT_COMPRESSION
- *                   This define supports the XC9500/XL compression scheme.
- *                   This define adds support for XSDRINC and XSETSDRMASKS.
- *               XSVF_SUPPORT_ERRORCODES
- *                   This define causes the xsvfExecute function to return
- *                   an error code for specific errors.  See error codes below.
- *                   If this is not defined, the return value defaults to the
- *                   legacy values for backward compatibility:
- *                   1 = success;  0 = failure.
- * Debugging:    DEBUG_MODE (Legacy name)
- *               Define DEBUG_MODE to compile with debugging features.
- *               Both micro.c and ports.c must be compiled with the DEBUG_MODE
- *               defined to enable the standalone main implementation in
- *               micro.c that reads XSVF from a file.
- * History:      v2.00   - Original XSVF implementation.
- *               v4.04   - Added delay at end of XSIR for XC18v00 support.
- *                         Added new commands for CoolRunner support:
- *                         XSTATE, XENDIR, XENDDR
- *               v4.05   - Cleanup micro.c but leave ports.c intact.
- *               v4.06   - Fix xsvfGotoTapState for retry transition.
- *               v4.07   - Update example waitTime implementations for
- *                         compatibility with Virtex-II.
- *               v4.10   - Add new XSIR2 command that supports a 2-byte
- *                         IR-length parameter for IR shifts > 255 bits.
- *               v4.11   - No change.  Update version to match SVF2XSVF xlator.
- *               v4.14   - Added XCOMMENT.
- *               v5.00   - Improve XSTATE support.
- *                         Added XWAIT.
- *****************************************************************************/
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-
-#include "micro.h"
-#include "lenval.h"
-#include "ports.h"
-
-const unsigned char *xsvfdata;
-
-/*============================================================================
- * XSVF #define
- ============================================================================*/
-
-#define XSVF_VERSION    "5.00"
-
-/*****************************************************************************
- * Define:       XSVF_SUPPORT_COMPRESSION
- * Description:  Define this to support the XC9500/XL XSVF data compression
- *               scheme.
- *               Code size can be reduced by NOT supporting this feature.
- *               However, you must use the -nc (no compress) option when
- *               translating SVF to XSVF using the SVF2XSVF translator.
- *               Corresponding, uncompressed XSVF may be larger.
- *****************************************************************************/
-#ifndef XSVF_SUPPORT_COMPRESSION
-#define XSVF_SUPPORT_COMPRESSION    1
-#endif
-
-/*****************************************************************************
- * Define:       XSVF_SUPPORT_ERRORCODES
- * Description:  Define this to support the new XSVF error codes.
- *               (The original XSVF player just returned 1 for success and
- *               0 for an unspecified failure.)
- *****************************************************************************/
-#ifndef XSVF_SUPPORT_ERRORCODES
-#define XSVF_SUPPORT_ERRORCODES     1
-#endif
-
-#ifdef  XSVF_SUPPORT_ERRORCODES
-#define XSVF_ERRORCODE(errorCode)   errorCode
-#else   /* Use legacy error code */
-#define XSVF_ERRORCODE(errorCode)   ((errorCode==XSVF_ERROR_NONE)?1:0)
-#endif  /* XSVF_SUPPORT_ERRORCODES */
-
-
-/*============================================================================
- * DEBUG_MODE #define
- ============================================================================*/
-#define DEBUG_MODE
-
-#ifdef  DEBUG_MODE
-#define XSVFDBG_PRINTF(iDebugLevel,pzFormat) \
-		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
-		    printf( pzFormat ); }
-#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) \
-		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
-		    printf( pzFormat, arg1 ); }
-#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) \
-		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
-		    printf( pzFormat, arg1, arg2 ); }
-#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) \
-		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
-		    printf( pzFormat, arg1, arg2, arg3 ); }
-#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) \
-		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
-		    xsvfPrintLenVal(plenVal); }
-#else   /* !DEBUG_MODE */
-#define XSVFDBG_PRINTF(iDebugLevel,pzFormat)
-#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1)
-#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2)
-#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3)
-#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal)
-#endif  /* DEBUG_MODE */
-
-
-/*============================================================================
- * XSVF Type Declarations
- ============================================================================*/
-
-/*****************************************************************************
- * Struct:       SXsvfInfo
- * Description:  This structure contains all of the data used during the
- *               execution of the XSVF.  Some data is persistent, predefined
- *               information (e.g. lRunTestTime).  The bulk of this struct's
- *               size is due to the lenVal structs (defined in lenval.h)
- *               which contain buffers for the active shift data.  The MAX_LEN
- *               #define in lenval.h defines the size of these buffers.
- *               These buffers must be large enough to store the longest
- *               shift data in your XSVF file.  For example:
- *                   MAX_LEN >= ( longest_shift_data_in_bits / 8 )
- *               Because the lenVal struct dominates the space usage of this
- *               struct, the rough size of this struct is:
- *                   sizeof( SXsvfInfo ) ~= MAX_LEN * 7 (number of lenVals)
- *               xsvfInitialize() contains initialization code for the data
- *               in this struct.
- *               xsvfCleanup() contains cleanup code for the data in this
- *               struct.
- *****************************************************************************/
-typedef struct tagSXsvfInfo
-{
-	/* XSVF status information */
-	unsigned char   ucComplete;         /* 0 = running; 1 = complete */
-	unsigned char   ucCommand;          /* Current XSVF command byte */
-	long            lCommandCount;      /* Number of commands processed */
-	int             iErrorCode;         /* An error code. 0 = no error. */
-
-	/* TAP state/sequencing information */
-	unsigned char   ucTapState;         /* Current TAP state */
-	unsigned char   ucEndIR;            /* ENDIR TAP state (See SVF) */
-	unsigned char   ucEndDR;            /* ENDDR TAP state (See SVF) */
-
-	/* RUNTEST information */
-	unsigned char   ucMaxRepeat;        /* Max repeat loops (for xc9500/xl) */
-	long            lRunTestTime;       /* Pre-specified RUNTEST time (usec) */
-
-	/* Shift Data Info and Buffers */
-	long            lShiftLengthBits;   /* Len. current shift data in bits */
-	short           sShiftLengthBytes;  /* Len. current shift data in bytes */
-
-	lenVal          lvTdi;              /* Current TDI shift data */
-	lenVal          lvTdoExpected;      /* Expected TDO shift data */
-	lenVal          lvTdoCaptured;      /* Captured TDO shift data */
-	lenVal          lvTdoMask;          /* TDO mask: 0=dontcare; 1=compare */
-
-#ifdef  XSVF_SUPPORT_COMPRESSION
-	/* XSDRINC Data Buffers */
-	lenVal          lvAddressMask;      /* Address mask for XSDRINC */
-	lenVal          lvDataMask;         /* Data mask for XSDRINC */
-	lenVal          lvNextData;         /* Next data for XSDRINC */
-#endif  /* XSVF_SUPPORT_COMPRESSION */
-} SXsvfInfo;
-
-/* Declare pointer to functions that perform XSVF commands */
-typedef int (*TXsvfDoCmdFuncPtr)( SXsvfInfo* );
-
-/*============================================================================
- * XSVF Command Bytes
- ============================================================================*/
-
-/* encodings of xsvf instructions */
-#define XCOMPLETE        0
-#define XTDOMASK         1
-#define XSIR             2
-#define XSDR             3
-#define XRUNTEST         4
-/* Reserved              5 */
-/* Reserved              6 */
-#define XREPEAT          7
-#define XSDRSIZE         8
-#define XSDRTDO          9
-#define XSETSDRMASKS     10
-#define XSDRINC          11
-#define XSDRB            12
-#define XSDRC            13
-#define XSDRE            14
-#define XSDRTDOB         15
-#define XSDRTDOC         16
-#define XSDRTDOE         17
-#define XSTATE           18         /* 4.00 */
-#define XENDIR           19         /* 4.04 */
-#define XENDDR           20         /* 4.04 */
-#define XSIR2            21         /* 4.10 */
-#define XCOMMENT         22         /* 4.14 */
-#define XWAIT            23         /* 5.00 */
-/* Insert new commands here */
-/* and add corresponding xsvfDoCmd function to xsvf_pfDoCmd below. */
-#define XLASTCMD         24         /* Last command marker */
-
-
-/*============================================================================
- * XSVF Command Parameter Values
- ============================================================================*/
-
-#define XSTATE_RESET     0          /* 4.00 parameter for XSTATE */
-#define XSTATE_RUNTEST   1          /* 4.00 parameter for XSTATE */
-
-#define XENDXR_RUNTEST   0          /* 4.04 parameter for XENDIR/DR */
-#define XENDXR_PAUSE     1          /* 4.04 parameter for XENDIR/DR */
-
-/* TAP states */
-#define XTAPSTATE_RESET     0x00
-#define XTAPSTATE_RUNTEST   0x01    /* a.k.a. IDLE */
-#define XTAPSTATE_SELECTDR  0x02
-#define XTAPSTATE_CAPTUREDR 0x03
-#define XTAPSTATE_SHIFTDR   0x04
-#define XTAPSTATE_EXIT1DR   0x05
-#define XTAPSTATE_PAUSEDR   0x06
-#define XTAPSTATE_EXIT2DR   0x07
-#define XTAPSTATE_UPDATEDR  0x08
-#define XTAPSTATE_IRSTATES  0x09    /* All IR states begin here */
-#define XTAPSTATE_SELECTIR  0x09
-#define XTAPSTATE_CAPTUREIR 0x0A
-#define XTAPSTATE_SHIFTIR   0x0B
-#define XTAPSTATE_EXIT1IR   0x0C
-#define XTAPSTATE_PAUSEIR   0x0D
-#define XTAPSTATE_EXIT2IR   0x0E
-#define XTAPSTATE_UPDATEIR  0x0F
-
-/*============================================================================
- * XSVF Function Prototypes
- ============================================================================*/
-
-int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo );   /* Illegal command function */
-int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo );
-int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSIR( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSDR( SXsvfInfo* pXsvfInfo );
-int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo );
-int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo );
-int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo );
-int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo );
-int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo );
-int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo );
-/* Insert new command functions here */
-
-/*============================================================================
- * XSVF Global Variables
- ============================================================================*/
-
-/* Array of XSVF command functions.  Must follow command byte value order! */
-/* If your compiler cannot take this form, then convert to a switch statement*/
-TXsvfDoCmdFuncPtr   xsvf_pfDoCmd[]  =
-{
-	xsvfDoXCOMPLETE,        /*  0 */
-	xsvfDoXTDOMASK,         /*  1 */
-	xsvfDoXSIR,             /*  2 */
-	xsvfDoXSDR,             /*  3 */
-	xsvfDoXRUNTEST,         /*  4 */
-	xsvfDoIllegalCmd,       /*  5 */
-	xsvfDoIllegalCmd,       /*  6 */
-	xsvfDoXREPEAT,          /*  7 */
-	xsvfDoXSDRSIZE,         /*  8 */
-	xsvfDoXSDRTDO,          /*  9 */
-#ifdef  XSVF_SUPPORT_COMPRESSION
-	xsvfDoXSETSDRMASKS,     /* 10 */
-	xsvfDoXSDRINC,          /* 11 */
-#else
-	xsvfDoIllegalCmd,       /* 10 */
-	xsvfDoIllegalCmd,       /* 11 */
-#endif  /* XSVF_SUPPORT_COMPRESSION */
-	xsvfDoXSDRBCE,          /* 12 */
-	xsvfDoXSDRBCE,          /* 13 */
-	xsvfDoXSDRBCE,          /* 14 */
-	xsvfDoXSDRTDOBCE,       /* 15 */
-	xsvfDoXSDRTDOBCE,       /* 16 */
-	xsvfDoXSDRTDOBCE,       /* 17 */
-	xsvfDoXSTATE,           /* 18 */
-	xsvfDoXENDXR,           /* 19 */
-	xsvfDoXENDXR,           /* 20 */
-	xsvfDoXSIR2,            /* 21 */
-	xsvfDoXCOMMENT,         /* 22 */
-	xsvfDoXWAIT             /* 23 */
-/* Insert new command functions here */
-};
-
-#ifdef  DEBUG_MODE
-char* xsvf_pzCommandName[]  =
-{
-	"XCOMPLETE",
-	"XTDOMASK",
-	"XSIR",
-	"XSDR",
-	"XRUNTEST",
-	"Reserved5",
-	"Reserved6",
-	"XREPEAT",
-	"XSDRSIZE",
-	"XSDRTDO",
-	"XSETSDRMASKS",
-	"XSDRINC",
-	"XSDRB",
-	"XSDRC",
-	"XSDRE",
-	"XSDRTDOB",
-	"XSDRTDOC",
-	"XSDRTDOE",
-	"XSTATE",
-	"XENDIR",
-	"XENDDR",
-	"XSIR2",
-	"XCOMMENT",
-	"XWAIT"
-};
-
-char*   xsvf_pzErrorName[]  =
-{
-	"No error",
-	"ERROR:  Unknown",
-	"ERROR:  TDO mismatch",
-	"ERROR:  TDO mismatch and exceeded max retries",
-	"ERROR:  Unsupported XSVF command",
-	"ERROR:  Illegal state specification",
-	"ERROR:  Data overflows allocated MAX_LEN buffer size"
-};
-
-char*   xsvf_pzTapState[] =
-{
-	"RESET",        /* 0x00 */
-	"RUNTEST/IDLE", /* 0x01 */
-	"DRSELECT",     /* 0x02 */
-	"DRCAPTURE",    /* 0x03 */
-	"DRSHIFT",      /* 0x04 */
-	"DREXIT1",      /* 0x05 */
-	"DRPAUSE",      /* 0x06 */
-	"DREXIT2",      /* 0x07 */
-	"DRUPDATE",     /* 0x08 */
-	"IRSELECT",     /* 0x09 */
-	"IRCAPTURE",    /* 0x0A */
-	"IRSHIFT",      /* 0x0B */
-	"IREXIT1",      /* 0x0C */
-	"IRPAUSE",      /* 0x0D */
-	"IREXIT2",      /* 0x0E */
-	"IRUPDATE"      /* 0x0F */
-};
-#endif  /* DEBUG_MODE */
-
-/*#ifdef DEBUG_MODE	*/
-/*    FILE* in;   /XXX* Legacy DEBUG_MODE file pointer */
-int xsvf_iDebugLevel;
-/*#endif /XXX* DEBUG_MODE */
-
-/*============================================================================
- * Utility Functions
- ============================================================================*/
-
-/*****************************************************************************
- * Function:     xsvfPrintLenVal
- * Description:  Print the lenval value in hex.
- * Parameters:   plv     - ptr to lenval.
- * Returns:      void.
- *****************************************************************************/
-#ifdef  DEBUG_MODE
-void xsvfPrintLenVal( lenVal *plv )
-{
-	int i;
-
-	if ( plv )
-	{
-		printf( "0x" );
-		for ( i = 0; i < plv->len; ++i )
-		{
-			printf( "%02x", ((unsigned int)(plv->val[ i ])) );
-		}
-	}
-}
-#endif  /* DEBUG_MODE */
-
-
-/*****************************************************************************
- * Function:     xsvfInfoInit
- * Description:  Initialize the xsvfInfo data.
- * Parameters:   pXsvfInfo   - ptr to the XSVF info structure.
- * Returns:      int         - 0 = success; otherwise error.
- *****************************************************************************/
-int xsvfInfoInit( SXsvfInfo* pXsvfInfo )
-{
-	XSVFDBG_PRINTF1( 4, "    sizeof( SXsvfInfo ) = %d bytes\n",
-			 sizeof( SXsvfInfo ) );
-
-	pXsvfInfo->ucComplete       = 0;
-	pXsvfInfo->ucCommand        = XCOMPLETE;
-	pXsvfInfo->lCommandCount    = 0;
-	pXsvfInfo->iErrorCode       = XSVF_ERROR_NONE;
-	pXsvfInfo->ucMaxRepeat      = 0;
-	pXsvfInfo->ucTapState       = XTAPSTATE_RESET;
-	pXsvfInfo->ucEndIR          = XTAPSTATE_RUNTEST;
-	pXsvfInfo->ucEndDR          = XTAPSTATE_RUNTEST;
-	pXsvfInfo->lShiftLengthBits = 0L;
-	pXsvfInfo->sShiftLengthBytes= 0;
-	pXsvfInfo->lRunTestTime     = 0L;
-
-	return( 0 );
-}
-
-/*****************************************************************************
- * Function:     xsvfInfoCleanup
- * Description:  Cleanup the xsvfInfo data.
- * Parameters:   pXsvfInfo   - ptr to the XSVF info structure.
- * Returns:      void.
- *****************************************************************************/
-void xsvfInfoCleanup( SXsvfInfo* pXsvfInfo )
-{
-}
-
-/*****************************************************************************
- * Function:     xsvfGetAsNumBytes
- * Description:  Calculate the number of bytes the given number of bits
- *               consumes.
- * Parameters:   lNumBits    - the number of bits.
- * Returns:      short       - the number of bytes to store the number of bits.
- *****************************************************************************/
-short xsvfGetAsNumBytes( long lNumBits )
-{
-	return( (short)( ( lNumBits + 7L ) / 8L ) );
-}
-
-/*****************************************************************************
- * Function:     xsvfTmsTransition
- * Description:  Apply TMS and transition TAP controller by applying one TCK
- *               cycle.
- * Parameters:   sTms    - new TMS value.
- * Returns:      void.
- *****************************************************************************/
-void xsvfTmsTransition( short sTms )
-{
-	setPort( TMS, sTms );
-	setPort( TCK, 0 );
-	setPort( TCK, 1 );
-}
-
-/*****************************************************************************
- * Function:     xsvfGotoTapState
- * Description:  From the current TAP state, go to the named TAP state.
- *               A target state of RESET ALWAYS causes TMS reset sequence.
- *               All SVF standard stable state paths are supported.
- *               All state transitions are supported except for the following
- *               which cause an XSVF_ERROR_ILLEGALSTATE:
- *                   - Target==DREXIT2;  Start!=DRPAUSE
- *                   - Target==IREXIT2;  Start!=IRPAUSE
- * Parameters:   pucTapState     - Current TAP state; returns final TAP state.
- *               ucTargetState   - New target TAP state.
- * Returns:      int             - 0 = success; otherwise error.
- *****************************************************************************/
-int xsvfGotoTapState( unsigned char*   pucTapState,
-		      unsigned char    ucTargetState )
-{
-	int i;
-	int iErrorCode;
-
-	iErrorCode  = XSVF_ERROR_NONE;
-	if ( ucTargetState == XTAPSTATE_RESET )
-	{
-		/* If RESET, always perform TMS reset sequence to reset/sync TAPs */
-		xsvfTmsTransition( 1 );
-		for ( i = 0; i < 5; ++i )
-		{
-			setPort( TCK, 0 );
-			setPort( TCK, 1 );
-		}
-		*pucTapState    = XTAPSTATE_RESET;
-		XSVFDBG_PRINTF( 3, "   TMS Reset Sequence -> Test-Logic-Reset\n" );
-		XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
-				 xsvf_pzTapState[ *pucTapState ] );
-	} else if ( ( ucTargetState != *pucTapState ) &&
-		  ( ( ( ucTargetState == XTAPSTATE_EXIT2DR ) && ( *pucTapState != XTAPSTATE_PAUSEDR ) ) ||
-		    ( ( ucTargetState == XTAPSTATE_EXIT2IR ) && ( *pucTapState != XTAPSTATE_PAUSEIR ) ) ) )
-	{
-		/* Trap illegal TAP state path specification */
-		iErrorCode      = XSVF_ERROR_ILLEGALSTATE;
-	} else {
-		if ( ucTargetState == *pucTapState )
-		{
-			/* Already in target state.  Do nothing except when in DRPAUSE
-			   or in IRPAUSE to comply with SVF standard */
-			if ( ucTargetState == XTAPSTATE_PAUSEDR )
-			{
-				xsvfTmsTransition( 1 );
-				*pucTapState    = XTAPSTATE_EXIT2DR;
-				XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
-						 xsvf_pzTapState[ *pucTapState ] );
-			}
-			else if ( ucTargetState == XTAPSTATE_PAUSEIR )
-			{
-				xsvfTmsTransition( 1 );
-				*pucTapState    = XTAPSTATE_EXIT2IR;
-				XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
-						 xsvf_pzTapState[ *pucTapState ] );
-			}
-		}
-
-		/* Perform TAP state transitions to get to the target state */
-		while ( ucTargetState != *pucTapState )
-		{
-			switch ( *pucTapState )
-			{
-			case XTAPSTATE_RESET:
-				xsvfTmsTransition( 0 );
-				*pucTapState    = XTAPSTATE_RUNTEST;
-				break;
-			case XTAPSTATE_RUNTEST:
-				xsvfTmsTransition( 1 );
-				*pucTapState    = XTAPSTATE_SELECTDR;
-				break;
-			case XTAPSTATE_SELECTDR:
-				if ( ucTargetState >= XTAPSTATE_IRSTATES )
-				{
-					xsvfTmsTransition( 1 );
-					*pucTapState    = XTAPSTATE_SELECTIR;
-				}
-				else
-				{
-					xsvfTmsTransition( 0 );
-					*pucTapState    = XTAPSTATE_CAPTUREDR;
-				}
-				break;
-			case XTAPSTATE_CAPTUREDR:
-				if ( ucTargetState == XTAPSTATE_SHIFTDR )
-				{
-					xsvfTmsTransition( 0 );
-					*pucTapState    = XTAPSTATE_SHIFTDR;
-				}
-				else
-				{
-					xsvfTmsTransition( 1 );
-					*pucTapState    = XTAPSTATE_EXIT1DR;
-				}
-				break;
-			case XTAPSTATE_SHIFTDR:
-				xsvfTmsTransition( 1 );
-				*pucTapState    = XTAPSTATE_EXIT1DR;
-				break;
-			case XTAPSTATE_EXIT1DR:
-				if ( ucTargetState == XTAPSTATE_PAUSEDR )
-				{
-					xsvfTmsTransition( 0 );
-					*pucTapState    = XTAPSTATE_PAUSEDR;
-				}
-				else
-				{
-					xsvfTmsTransition( 1 );
-					*pucTapState    = XTAPSTATE_UPDATEDR;
-				}
-				break;
-			case XTAPSTATE_PAUSEDR:
-				xsvfTmsTransition( 1 );
-				*pucTapState    = XTAPSTATE_EXIT2DR;
-				break;
-			case XTAPSTATE_EXIT2DR:
-				if ( ucTargetState == XTAPSTATE_SHIFTDR )
-				{
-					xsvfTmsTransition( 0 );
-					*pucTapState    = XTAPSTATE_SHIFTDR;
-				}
-				else
-				{
-					xsvfTmsTransition( 1 );
-					*pucTapState    = XTAPSTATE_UPDATEDR;
-				}
-				break;
-			case XTAPSTATE_UPDATEDR:
-				if ( ucTargetState == XTAPSTATE_RUNTEST )
-				{
-					xsvfTmsTransition( 0 );
-					*pucTapState    = XTAPSTATE_RUNTEST;
-				}
-				else
-				{
-					xsvfTmsTransition( 1 );
-					*pucTapState    = XTAPSTATE_SELECTDR;
-				}
-				break;
-			case XTAPSTATE_SELECTIR:
-				xsvfTmsTransition( 0 );
-				*pucTapState    = XTAPSTATE_CAPTUREIR;
-				break;
-			case XTAPSTATE_CAPTUREIR:
-				if ( ucTargetState == XTAPSTATE_SHIFTIR )
-				{
-					xsvfTmsTransition( 0 );
-					*pucTapState    = XTAPSTATE_SHIFTIR;
-				}
-				else
-				{
-					xsvfTmsTransition( 1 );
-					*pucTapState    = XTAPSTATE_EXIT1IR;
-				}
-				break;
-			case XTAPSTATE_SHIFTIR:
-				xsvfTmsTransition( 1 );
-				*pucTapState    = XTAPSTATE_EXIT1IR;
-				break;
-			case XTAPSTATE_EXIT1IR:
-				if ( ucTargetState == XTAPSTATE_PAUSEIR )
-				{
-					xsvfTmsTransition( 0 );
-					*pucTapState    = XTAPSTATE_PAUSEIR;
-				}
-				else
-				{
-					xsvfTmsTransition( 1 );
-					*pucTapState    = XTAPSTATE_UPDATEIR;
-				}
-				break;
-			case XTAPSTATE_PAUSEIR:
-				xsvfTmsTransition( 1 );
-				*pucTapState    = XTAPSTATE_EXIT2IR;
-				break;
-			case XTAPSTATE_EXIT2IR:
-				if ( ucTargetState == XTAPSTATE_SHIFTIR )
-				{
-					xsvfTmsTransition( 0 );
-					*pucTapState    = XTAPSTATE_SHIFTIR;
-				}
-				else
-				{
-					xsvfTmsTransition( 1 );
-					*pucTapState    = XTAPSTATE_UPDATEIR;
-				}
-				break;
-			case XTAPSTATE_UPDATEIR:
-				if ( ucTargetState == XTAPSTATE_RUNTEST )
-				{
-					xsvfTmsTransition( 0 );
-					*pucTapState    = XTAPSTATE_RUNTEST;
-				}
-				else
-				{
-					xsvfTmsTransition( 1 );
-					*pucTapState    = XTAPSTATE_SELECTDR;
-				}
-				break;
-			default:
-				iErrorCode      = XSVF_ERROR_ILLEGALSTATE;
-				*pucTapState    = ucTargetState;    /* Exit while loop */
-				break;
-			}
-			XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
-					 xsvf_pzTapState[ *pucTapState ] );
-		}
-	}
-
-	return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function:     xsvfShiftOnly
- * Description:  Assumes that starting TAP state is SHIFT-DR or SHIFT-IR.
- *               Shift the given TDI data into the JTAG scan chain.
- *               Optionally, save the TDO data shifted out of the scan chain.
- *               Last shift cycle is special:  capture last TDO, set last TDI,
- *               but does not pulse TCK.  Caller must pulse TCK and optionally
- *               set TMS=1 to exit shift state.
- * Parameters:   lNumBits        - number of bits to shift.
- *               plvTdi          - ptr to lenval for TDI data.
- *               plvTdoCaptured  - ptr to lenval for storing captured TDO data.
- *               iExitShift      - 1=exit at end of shift; 0=stay in Shift-DR.
- * Returns:      void.
- *****************************************************************************/
-void xsvfShiftOnly( long    lNumBits,
-		    lenVal* plvTdi,
-		    lenVal* plvTdoCaptured,
-		    int     iExitShift )
-{
-	unsigned char*  pucTdi;
-	unsigned char*  pucTdo;
-	unsigned char   ucTdiByte;
-	unsigned char   ucTdoByte;
-	unsigned char   ucTdoBit;
-	int             i;
-
-	/* assert( ( ( lNumBits + 7 ) / 8 ) == plvTdi->len ); */
-
-	/* Initialize TDO storage len == TDI len */
-	pucTdo  = 0;
-	if ( plvTdoCaptured )
-	{
-		plvTdoCaptured->len = plvTdi->len;
-		pucTdo              = plvTdoCaptured->val + plvTdi->len;
-	}
-
-	/* Shift LSB first.  val[N-1] == LSB.  val[0] == MSB. */
-	pucTdi  = plvTdi->val + plvTdi->len;
-	while ( lNumBits )
-	{
-		/* Process on a byte-basis */
-		ucTdiByte   = (*(--pucTdi));
-		ucTdoByte   = 0;
-		for ( i = 0; ( lNumBits && ( i < 8 ) ); ++i )
-		{
-			--lNumBits;
-			if ( iExitShift && !lNumBits )
-			{
-				/* Exit Shift-DR state */
-				setPort( TMS, 1 );
-			}
-
-			/* Set the new TDI value */
-			setPort( TDI, (short)(ucTdiByte & 1) );
-			ucTdiByte   >>= 1;
-
-			/* Set TCK low */
-			setPort( TCK, 0 );
-
-			if ( pucTdo )
-			{
-				/* Save the TDO value */
-				ucTdoBit    = readTDOBit();
-				ucTdoByte   |= ( ucTdoBit << i );
-			}
-
-			/* Set TCK high */
-			setPort( TCK, 1 );
-		}
-
-		/* Save the TDO byte value */
-		if ( pucTdo )
-		{
-			(*(--pucTdo))   = ucTdoByte;
-		}
-	}
-}
-
-/*****************************************************************************
- * Function:     xsvfShift
- * Description:  Goes to the given starting TAP state.
- *               Calls xsvfShiftOnly to shift in the given TDI data and
- *               optionally capture the TDO data.
- *               Compares the TDO captured data against the TDO expected
- *               data.
- *               If a data mismatch occurs, then executes the exception
- *               handling loop upto ucMaxRepeat times.
- * Parameters:   pucTapState     - Ptr to current TAP state.
- *               ucStartState    - Starting shift state: Shift-DR or Shift-IR.
- *               lNumBits        - number of bits to shift.
- *               plvTdi          - ptr to lenval for TDI data.
- *               plvTdoCaptured  - ptr to lenval for storing TDO data.
- *               plvTdoExpected  - ptr to expected TDO data.
- *               plvTdoMask      - ptr to TDO mask.
- *               ucEndState      - state in which to end the shift.
- *               lRunTestTime    - amount of time to wait after the shift.
- *               ucMaxRepeat     - Maximum number of retries on TDO mismatch.
- * Returns:      int             - 0 = success; otherwise TDO mismatch.
- * Notes:        XC9500XL-only Optimization:
- *               Skip the waitTime() if plvTdoMask->val[0:plvTdoMask->len-1]
- *               is NOT all zeros and sMatch==1.
- *****************************************************************************/
-int xsvfShift( unsigned char*   pucTapState,
-	       unsigned char    ucStartState,
-	       long             lNumBits,
-	       lenVal*          plvTdi,
-	       lenVal*          plvTdoCaptured,
-	       lenVal*          plvTdoExpected,
-	       lenVal*          plvTdoMask,
-	       unsigned char    ucEndState,
-	       long             lRunTestTime,
-	       unsigned char    ucMaxRepeat )
-{
-	int             iErrorCode;
-	int             iMismatch;
-	unsigned char   ucRepeat;
-	int             iExitShift;
-
-	iErrorCode  = XSVF_ERROR_NONE;
-	iMismatch   = 0;
-	ucRepeat    = 0;
-	iExitShift  = ( ucStartState != ucEndState );
-
-	XSVFDBG_PRINTF1( 3, "   Shift Length = %ld\n", lNumBits );
-	XSVFDBG_PRINTF( 4, "    TDI          = ");
-	XSVFDBG_PRINTLENVAL( 4, plvTdi );
-	XSVFDBG_PRINTF( 4, "\n");
-	XSVFDBG_PRINTF( 4, "    TDO Expected = ");
-	XSVFDBG_PRINTLENVAL( 4, plvTdoExpected );
-	XSVFDBG_PRINTF( 4, "\n");
-
-	if ( !lNumBits )
-	{
-		/* Compatibility with XSVF2.00:  XSDR 0 = no shift, but wait in RTI */
-		if ( lRunTestTime )
-		{
-			/* Wait for prespecified XRUNTEST time */
-			xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST );
-			XSVFDBG_PRINTF1( 3, "   Wait = %ld usec\n", lRunTestTime );
-			waitTime( lRunTestTime );
-		}
-	}
-	else
-	{
-		do
-		{
-			/* Goto Shift-DR or Shift-IR */
-			xsvfGotoTapState( pucTapState, ucStartState );
-
-			/* Shift TDI and capture TDO */
-			xsvfShiftOnly( lNumBits, plvTdi, plvTdoCaptured, iExitShift );
-
-			if ( plvTdoExpected )
-			{
-				/* Compare TDO data to expected TDO data */
-				iMismatch   = !EqualLenVal( plvTdoExpected,
-							    plvTdoCaptured,
-							    plvTdoMask );
-			}
-
-			if ( iExitShift )
-			{
-				/* Update TAP state:  Shift->Exit */
-				++(*pucTapState);
-				XSVFDBG_PRINTF1( 3, "   TAP State = %s\n",
-						 xsvf_pzTapState[ *pucTapState ] );
-
-				if ( iMismatch && lRunTestTime && ( ucRepeat < ucMaxRepeat ) )
-				{
-					XSVFDBG_PRINTF( 4, "    TDO Expected = ");
-					XSVFDBG_PRINTLENVAL( 4, plvTdoExpected );
-					XSVFDBG_PRINTF( 4, "\n");
-					XSVFDBG_PRINTF( 4, "    TDO Captured = ");
-					XSVFDBG_PRINTLENVAL( 4, plvTdoCaptured );
-					XSVFDBG_PRINTF( 4, "\n");
-					XSVFDBG_PRINTF( 4, "    TDO Mask     = ");
-					XSVFDBG_PRINTLENVAL( 4, plvTdoMask );
-					XSVFDBG_PRINTF( 4, "\n");
-					XSVFDBG_PRINTF1( 3, "   Retry #%d\n", ( ucRepeat + 1 ) );
-					/* Do exception handling retry - ShiftDR only */
-					xsvfGotoTapState( pucTapState, XTAPSTATE_PAUSEDR );
-					/* Shift 1 extra bit */
-					xsvfGotoTapState( pucTapState, XTAPSTATE_SHIFTDR );
-					/* Increment RUNTEST time by an additional 25% */
-					lRunTestTime    += ( lRunTestTime >> 2 );
-				}
-				else
-				{
-					/* Do normal exit from Shift-XR */
-					xsvfGotoTapState( pucTapState, ucEndState );
-				}
-
-				if ( lRunTestTime )
-				{
-					/* Wait for prespecified XRUNTEST time */
-					xsvfGotoTapState( pucTapState, XTAPSTATE_RUNTEST );
-					XSVFDBG_PRINTF1( 3, "   Wait = %ld usec\n", lRunTestTime );
-					waitTime( lRunTestTime );
-				}
-			}
-		} while ( iMismatch && ( ucRepeat++ < ucMaxRepeat ) );
-	}
-
-	if ( iMismatch )
-	{
-		XSVFDBG_PRINTF( 1, " TDO Expected = ");
-		XSVFDBG_PRINTLENVAL( 1, plvTdoExpected );
-		XSVFDBG_PRINTF( 1, "\n");
-		XSVFDBG_PRINTF( 1, " TDO Captured = ");
-		XSVFDBG_PRINTLENVAL( 1, plvTdoCaptured );
-		XSVFDBG_PRINTF( 1, "\n");
-		XSVFDBG_PRINTF( 1, " TDO Mask     = ");
-		XSVFDBG_PRINTLENVAL( 1, plvTdoMask );
-		XSVFDBG_PRINTF( 1, "\n");
-		if ( ucMaxRepeat && ( ucRepeat > ucMaxRepeat ) )
-		{
-			iErrorCode  = XSVF_ERROR_MAXRETRIES;
-		}
-		else
-		{
-			iErrorCode  = XSVF_ERROR_TDOMISMATCH;
-		}
-	}
-
-	return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function:     xsvfBasicXSDRTDO
- * Description:  Get the XSDRTDO parameters and execute the XSDRTDO command.
- *               This is the common function for all XSDRTDO commands.
- * Parameters:   pucTapState         - Current TAP state.
- *               lShiftLengthBits    - number of bits to shift.
- *               sShiftLengthBytes   - number of bytes to read.
- *               plvTdi              - ptr to lenval for TDI data.
- *               lvTdoCaptured       - ptr to lenval for storing TDO data.
- *               iEndState           - state in which to end the shift.
- *               lRunTestTime        - amount of time to wait after the shift.
- *               ucMaxRepeat         - maximum xc9500/xl retries.
- * Returns:      int                 - 0 = success; otherwise TDO mismatch.
- *****************************************************************************/
-int xsvfBasicXSDRTDO( unsigned char*    pucTapState,
-		      long              lShiftLengthBits,
-		      short             sShiftLengthBytes,
-		      lenVal*           plvTdi,
-		      lenVal*           plvTdoCaptured,
-		      lenVal*           plvTdoExpected,
-		      lenVal*           plvTdoMask,
-		      unsigned char     ucEndState,
-		      long              lRunTestTime,
-		      unsigned char     ucMaxRepeat )
-{
-	readVal( plvTdi, sShiftLengthBytes );
-	if ( plvTdoExpected )
-	{
-		readVal( plvTdoExpected, sShiftLengthBytes );
-	}
-	return( xsvfShift( pucTapState, XTAPSTATE_SHIFTDR, lShiftLengthBits,
-			   plvTdi, plvTdoCaptured, plvTdoExpected, plvTdoMask,
-			   ucEndState, lRunTestTime, ucMaxRepeat ) );
-}
-
-/*****************************************************************************
- * Function:     xsvfDoSDRMasking
- * Description:  Update the data value with the next XSDRINC data and address.
- * Example:      dataVal=0x01ff, nextData=0xab, addressMask=0x0100,
- *               dataMask=0x00ff, should set dataVal to 0x02ab
- * Parameters:   plvTdi          - The current TDI value.
- *               plvNextData     - the next data value.
- *               plvAddressMask  - the address mask.
- *               plvDataMask     - the data mask.
- * Returns:      void.
- *****************************************************************************/
-#ifdef  XSVF_SUPPORT_COMPRESSION
-void xsvfDoSDRMasking( lenVal*  plvTdi,
-		       lenVal*  plvNextData,
-		       lenVal*  plvAddressMask,
-		       lenVal*  plvDataMask )
-{
-	int             i;
-	unsigned char   ucTdi;
-	unsigned char   ucTdiMask;
-	unsigned char   ucDataMask;
-	unsigned char   ucNextData;
-	unsigned char   ucNextMask;
-	short           sNextData;
-
-	/* add the address Mask to dataVal and return as a new dataVal */
-	addVal( plvTdi, plvTdi, plvAddressMask );
-
-	ucNextData  = 0;
-	ucNextMask  = 0;
-	sNextData   = plvNextData->len;
-	for ( i = plvDataMask->len - 1; i >= 0; --i )
-	{
-		/* Go through data mask in reverse order looking for mask (1) bits */
-		ucDataMask  = plvDataMask->val[ i ];
-		if ( ucDataMask )
-		{
-			/* Retrieve the corresponding TDI byte value */
-			ucTdi       = plvTdi->val[ i ];
-
-			/* For each bit in the data mask byte, look for 1's */
-			ucTdiMask   = 1;
-			while ( ucDataMask )
-			{
-				if ( ucDataMask & 1 )
-				{
-					if ( !ucNextMask )
-					{
-						/* Get the next data byte */
-						ucNextData  = plvNextData->val[ --sNextData ];
-						ucNextMask  = 1;
-					}
-
-					/* Set or clear the data bit according to the next data */
-					if ( ucNextData & ucNextMask )
-					{
-						ucTdi   |= ucTdiMask;       /* Set bit */
-					}
-					else
-					{
-						ucTdi   &= ( ~ucTdiMask );  /* Clear bit */
-					}
-
-					/* Update the next data */
-					ucNextMask  <<= 1;
-				}
-				ucTdiMask   <<= 1;
-				ucDataMask  >>= 1;
-			}
-
-			/* Update the TDI value */
-			plvTdi->val[ i ]    = ucTdi;
-		}
-	}
-}
-#endif  /* XSVF_SUPPORT_COMPRESSION */
-
-/*============================================================================
- * XSVF Command Functions (type = TXsvfDoCmdFuncPtr)
- * These functions update pXsvfInfo->iErrorCode only on an error.
- * Otherwise, the error code is left alone.
- * The function returns the error code from the function.
- ============================================================================*/
-
-/*****************************************************************************
- * Function:     xsvfDoIllegalCmd
- * Description:  Function place holder for illegal/unsupported commands.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-int xsvfDoIllegalCmd( SXsvfInfo* pXsvfInfo )
-{
-	XSVFDBG_PRINTF2( 0, "ERROR:  Encountered unsupported command #%d (%s)\n",
-			 ((unsigned int)(pXsvfInfo->ucCommand)),
-			 ((pXsvfInfo->ucCommand < XLASTCMD)
-			  ? (xsvf_pzCommandName[pXsvfInfo->ucCommand])
-			  : "Unknown") );
-	pXsvfInfo->iErrorCode   = XSVF_ERROR_ILLEGALCMD;
-	return( pXsvfInfo->iErrorCode );
-}
-
-/*****************************************************************************
- * Function:     xsvfDoXCOMPLETE
- * Description:  XCOMPLETE (no parameters)
- *               Update complete status for XSVF player.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-int xsvfDoXCOMPLETE( SXsvfInfo* pXsvfInfo )
-{
-	pXsvfInfo->ucComplete   = 1;
-	return( XSVF_ERROR_NONE );
-}
-
-/*****************************************************************************
- * Function:     xsvfDoXTDOMASK
- * Description:  XTDOMASK <lenVal.TdoMask[XSDRSIZE]>
- *               Prespecify the TDO compare mask.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-int xsvfDoXTDOMASK( SXsvfInfo* pXsvfInfo )
-{
-	readVal( &(pXsvfInfo->lvTdoMask), pXsvfInfo->sShiftLengthBytes );
-	XSVFDBG_PRINTF( 4, "    TDO Mask     = ");
-	XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvTdoMask) );
-	XSVFDBG_PRINTF( 4, "\n");
-	return( XSVF_ERROR_NONE );
-}
-
-/*****************************************************************************
- * Function:     xsvfDoXSIR
- * Description:  XSIR <(byte)shiftlen> <lenVal.TDI[shiftlen]>
- *               Get the instruction and shift the instruction into the TAP.
- *               If prespecified XRUNTEST!=0, goto RUNTEST and wait after
- *               the shift for XRUNTEST usec.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-int xsvfDoXSIR( SXsvfInfo* pXsvfInfo )
-{
-	unsigned char   ucShiftIrBits;
-	short           sShiftIrBytes;
-	int             iErrorCode;
-
-	/* Get the shift length and store */
-	readByte( &ucShiftIrBits );
-	sShiftIrBytes   = xsvfGetAsNumBytes( ucShiftIrBits );
-	XSVFDBG_PRINTF1( 3, "   XSIR length = %d\n",
-			 ((unsigned int)ucShiftIrBits) );
-
-	if ( sShiftIrBytes > MAX_LEN )
-	{
-		iErrorCode  = XSVF_ERROR_DATAOVERFLOW;
-	}
-	else
-	{
-		/* Get and store instruction to shift in */
-		readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( ucShiftIrBits ) );
-
-		/* Shift the data */
-		iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR,
-					 ucShiftIrBits, &(pXsvfInfo->lvTdi),
-					 /*plvTdoCaptured*/0, /*plvTdoExpected*/0,
-					 /*plvTdoMask*/0, pXsvfInfo->ucEndIR,
-					 pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 );
-	}
-
-	if ( iErrorCode != XSVF_ERROR_NONE )
-	{
-		pXsvfInfo->iErrorCode   = iErrorCode;
-	}
-	return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function:     xsvfDoXSIR2
- * Description:  XSIR <(2-byte)shiftlen> <lenVal.TDI[shiftlen]>
- *               Get the instruction and shift the instruction into the TAP.
- *               If prespecified XRUNTEST!=0, goto RUNTEST and wait after
- *               the shift for XRUNTEST usec.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-int xsvfDoXSIR2( SXsvfInfo* pXsvfInfo )
-{
-	long            lShiftIrBits;
-	short           sShiftIrBytes;
-	int             iErrorCode;
-
-	/* Get the shift length and store */
-	readVal( &(pXsvfInfo->lvTdi), 2 );
-	lShiftIrBits    = value( &(pXsvfInfo->lvTdi) );
-	sShiftIrBytes   = xsvfGetAsNumBytes( lShiftIrBits );
-	XSVFDBG_PRINTF1( 3, "   XSIR2 length = %d\n", (int)lShiftIrBits);
-
-	if ( sShiftIrBytes > MAX_LEN )
-	{
-		iErrorCode  = XSVF_ERROR_DATAOVERFLOW;
-	}
-	else
-	{
-		/* Get and store instruction to shift in */
-		readVal( &(pXsvfInfo->lvTdi), xsvfGetAsNumBytes( lShiftIrBits ) );
-
-		/* Shift the data */
-		iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTIR,
-					 lShiftIrBits, &(pXsvfInfo->lvTdi),
-					 /*plvTdoCaptured*/0, /*plvTdoExpected*/0,
-					 /*plvTdoMask*/0, pXsvfInfo->ucEndIR,
-					 pXsvfInfo->lRunTestTime, /*ucMaxRepeat*/0 );
-	}
-
-	if ( iErrorCode != XSVF_ERROR_NONE )
-	{
-		pXsvfInfo->iErrorCode   = iErrorCode;
-	}
-	return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function:     xsvfDoXSDR
- * Description:  XSDR <lenVal.TDI[XSDRSIZE]>
- *               Shift the given TDI data into the JTAG scan chain.
- *               Compare the captured TDO with the expected TDO from the
- *               previous XSDRTDO command using the previously specified
- *               XTDOMASK.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-int xsvfDoXSDR( SXsvfInfo* pXsvfInfo )
-{
-	int iErrorCode;
-	readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes );
-	/* use TDOExpected from last XSDRTDO instruction */
-	iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR,
-				 pXsvfInfo->lShiftLengthBits, &(pXsvfInfo->lvTdi),
-				 &(pXsvfInfo->lvTdoCaptured),
-				 &(pXsvfInfo->lvTdoExpected),
-				 &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR,
-				 pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat );
-	if ( iErrorCode != XSVF_ERROR_NONE )
-	{
-		pXsvfInfo->iErrorCode   = iErrorCode;
-	}
-	return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function:     xsvfDoXRUNTEST
- * Description:  XRUNTEST <uint32>
- *               Prespecify the XRUNTEST wait time for shift operations.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-int xsvfDoXRUNTEST( SXsvfInfo* pXsvfInfo )
-{
-	readVal( &(pXsvfInfo->lvTdi), 4 );
-	pXsvfInfo->lRunTestTime = value( &(pXsvfInfo->lvTdi) );
-	XSVFDBG_PRINTF1( 3, "   XRUNTEST = %ld\n", pXsvfInfo->lRunTestTime );
-	return( XSVF_ERROR_NONE );
-}
-
-/*****************************************************************************
- * Function:     xsvfDoXREPEAT
- * Description:  XREPEAT <byte>
- *               Prespecify the maximum number of XC9500/XL retries.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-int xsvfDoXREPEAT( SXsvfInfo* pXsvfInfo )
-{
-	readByte( &(pXsvfInfo->ucMaxRepeat) );
-	XSVFDBG_PRINTF1( 3, "   XREPEAT = %d\n",
-			 ((unsigned int)(pXsvfInfo->ucMaxRepeat)) );
-	return( XSVF_ERROR_NONE );
-}
-
-/*****************************************************************************
- * Function:     xsvfDoXSDRSIZE
- * Description:  XSDRSIZE <uint32>
- *               Prespecify the XRUNTEST wait time for shift operations.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-int xsvfDoXSDRSIZE( SXsvfInfo* pXsvfInfo )
-{
-	int iErrorCode;
-	iErrorCode  = XSVF_ERROR_NONE;
-	readVal( &(pXsvfInfo->lvTdi), 4 );
-	pXsvfInfo->lShiftLengthBits = value( &(pXsvfInfo->lvTdi) );
-	pXsvfInfo->sShiftLengthBytes= xsvfGetAsNumBytes( pXsvfInfo->lShiftLengthBits );
-	XSVFDBG_PRINTF1( 3, "   XSDRSIZE = %ld\n", pXsvfInfo->lShiftLengthBits );
-	if ( pXsvfInfo->sShiftLengthBytes > MAX_LEN )
-	{
-		iErrorCode  = XSVF_ERROR_DATAOVERFLOW;
-		pXsvfInfo->iErrorCode   = iErrorCode;
-	}
-	return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function:     xsvfDoXSDRTDO
- * Description:  XSDRTDO <lenVal.TDI[XSDRSIZE]> <lenVal.TDO[XSDRSIZE]>
- *               Get the TDI and expected TDO values.  Then, shift.
- *               Compare the expected TDO with the captured TDO using the
- *               prespecified XTDOMASK.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-int xsvfDoXSDRTDO( SXsvfInfo* pXsvfInfo )
-{
-	int iErrorCode;
-	iErrorCode  = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
-					pXsvfInfo->lShiftLengthBits,
-					pXsvfInfo->sShiftLengthBytes,
-					&(pXsvfInfo->lvTdi),
-					&(pXsvfInfo->lvTdoCaptured),
-					&(pXsvfInfo->lvTdoExpected),
-					&(pXsvfInfo->lvTdoMask),
-					pXsvfInfo->ucEndDR,
-					pXsvfInfo->lRunTestTime,
-					pXsvfInfo->ucMaxRepeat );
-	if ( iErrorCode != XSVF_ERROR_NONE )
-	{
-		pXsvfInfo->iErrorCode   = iErrorCode;
-	}
-	return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function:     xsvfDoXSETSDRMASKS
- * Description:  XSETSDRMASKS <lenVal.AddressMask[XSDRSIZE]>
- *                            <lenVal.DataMask[XSDRSIZE]>
- *               Get the prespecified address and data mask for the XSDRINC
- *               command.
- *               Used for xc9500/xl compressed XSVF data.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-#ifdef  XSVF_SUPPORT_COMPRESSION
-int xsvfDoXSETSDRMASKS( SXsvfInfo* pXsvfInfo )
-{
-	/* read the addressMask */
-	readVal( &(pXsvfInfo->lvAddressMask), pXsvfInfo->sShiftLengthBytes );
-	/* read the dataMask    */
-	readVal( &(pXsvfInfo->lvDataMask), pXsvfInfo->sShiftLengthBytes );
-
-	XSVFDBG_PRINTF( 4, "    Address Mask = " );
-	XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvAddressMask) );
-	XSVFDBG_PRINTF( 4, "\n" );
-	XSVFDBG_PRINTF( 4, "    Data Mask    = " );
-	XSVFDBG_PRINTLENVAL( 4, &(pXsvfInfo->lvDataMask) );
-	XSVFDBG_PRINTF( 4, "\n" );
-
-	return( XSVF_ERROR_NONE );
-}
-#endif  /* XSVF_SUPPORT_COMPRESSION */
-
-/*****************************************************************************
- * Function:     xsvfDoXSDRINC
- * Description:  XSDRINC <lenVal.firstTDI[XSDRSIZE]> <byte(numTimes)>
- *                       <lenVal.data[XSETSDRMASKS.dataMask.len]> ...
- *               Get the XSDRINC parameters and execute the XSDRINC command.
- *               XSDRINC starts by loading the first TDI shift value.
- *               Then, for numTimes, XSDRINC gets the next piece of data,
- *               replaces the bits from the starting TDI as defined by the
- *               XSETSDRMASKS.dataMask, adds the address mask from
- *               XSETSDRMASKS.addressMask, shifts the new TDI value,
- *               and compares the TDO to the expected TDO from the previous
- *               XSDRTDO command using the XTDOMASK.
- *               Used for xc9500/xl compressed XSVF data.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-#ifdef  XSVF_SUPPORT_COMPRESSION
-int xsvfDoXSDRINC( SXsvfInfo* pXsvfInfo )
-{
-	int             iErrorCode;
-	int             iDataMaskLen;
-	unsigned char   ucDataMask;
-	unsigned char   ucNumTimes;
-	unsigned char   i;
-
-	readVal( &(pXsvfInfo->lvTdi), pXsvfInfo->sShiftLengthBytes );
-	iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState), XTAPSTATE_SHIFTDR,
-				 pXsvfInfo->lShiftLengthBits,
-				 &(pXsvfInfo->lvTdi), &(pXsvfInfo->lvTdoCaptured),
-				 &(pXsvfInfo->lvTdoExpected),
-				 &(pXsvfInfo->lvTdoMask), pXsvfInfo->ucEndDR,
-				 pXsvfInfo->lRunTestTime, pXsvfInfo->ucMaxRepeat );
-	if ( !iErrorCode )
-	{
-		/* Calculate number of data mask bits */
-		iDataMaskLen    = 0;
-		for ( i = 0; i < pXsvfInfo->lvDataMask.len; ++i )
-		{
-			ucDataMask  = pXsvfInfo->lvDataMask.val[ i ];
-			while ( ucDataMask )
-			{
-				iDataMaskLen    += ( ucDataMask & 1 );
-				ucDataMask      >>= 1;
-			}
-		}
-
-		/* Get the number of data pieces, i.e. number of times to shift */
-		readByte( &ucNumTimes );
-
-		/* For numTimes, get data, fix TDI, and shift */
-		for ( i = 0; !iErrorCode && ( i < ucNumTimes ); ++i )
-		{
-			readVal( &(pXsvfInfo->lvNextData),
-				 xsvfGetAsNumBytes( iDataMaskLen ) );
-			xsvfDoSDRMasking( &(pXsvfInfo->lvTdi),
-					  &(pXsvfInfo->lvNextData),
-					  &(pXsvfInfo->lvAddressMask),
-					  &(pXsvfInfo->lvDataMask) );
-			iErrorCode  = xsvfShift( &(pXsvfInfo->ucTapState),
-						 XTAPSTATE_SHIFTDR,
-						 pXsvfInfo->lShiftLengthBits,
-						 &(pXsvfInfo->lvTdi),
-						 &(pXsvfInfo->lvTdoCaptured),
-						 &(pXsvfInfo->lvTdoExpected),
-						 &(pXsvfInfo->lvTdoMask),
-						 pXsvfInfo->ucEndDR,
-						 pXsvfInfo->lRunTestTime,
-						 pXsvfInfo->ucMaxRepeat );
-		}
-	}
-	if ( iErrorCode != XSVF_ERROR_NONE )
-	{
-		pXsvfInfo->iErrorCode   = iErrorCode;
-	}
-	return( iErrorCode );
-}
-#endif  /* XSVF_SUPPORT_COMPRESSION */
-
-/*****************************************************************************
- * Function:     xsvfDoXSDRBCE
- * Description:  XSDRB/XSDRC/XSDRE <lenVal.TDI[XSDRSIZE]>
- *               If not already in SHIFTDR, goto SHIFTDR.
- *               Shift the given TDI data into the JTAG scan chain.
- *               Ignore TDO.
- *               If cmd==XSDRE, then goto ENDDR.  Otherwise, stay in ShiftDR.
- *               XSDRB, XSDRC, and XSDRE are the same implementation.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-int xsvfDoXSDRBCE( SXsvfInfo* pXsvfInfo )
-{
-	unsigned char   ucEndDR;
-	int             iErrorCode;
-	ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRE ) ?
-				  pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR);
-	iErrorCode  = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
-					pXsvfInfo->lShiftLengthBits,
-					pXsvfInfo->sShiftLengthBytes,
-					&(pXsvfInfo->lvTdi),
-					/*plvTdoCaptured*/0, /*plvTdoExpected*/0,
-					/*plvTdoMask*/0, ucEndDR,
-					/*lRunTestTime*/0, /*ucMaxRepeat*/0 );
-	if ( iErrorCode != XSVF_ERROR_NONE )
-	{
-		pXsvfInfo->iErrorCode   = iErrorCode;
-	}
-	return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function:     xsvfDoXSDRTDOBCE
- * Description:  XSDRB/XSDRC/XSDRE <lenVal.TDI[XSDRSIZE]> <lenVal.TDO[XSDRSIZE]>
- *               If not already in SHIFTDR, goto SHIFTDR.
- *               Shift the given TDI data into the JTAG scan chain.
- *               Compare TDO, but do NOT use XTDOMASK.
- *               If cmd==XSDRTDOE, then goto ENDDR.  Otherwise, stay in ShiftDR.
- *               XSDRTDOB, XSDRTDOC, and XSDRTDOE are the same implementation.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-int xsvfDoXSDRTDOBCE( SXsvfInfo* pXsvfInfo )
-{
-	unsigned char   ucEndDR;
-	int             iErrorCode;
-	ucEndDR = (unsigned char)(( pXsvfInfo->ucCommand == XSDRTDOE ) ?
-				  pXsvfInfo->ucEndDR : XTAPSTATE_SHIFTDR);
-	iErrorCode  = xsvfBasicXSDRTDO( &(pXsvfInfo->ucTapState),
-					pXsvfInfo->lShiftLengthBits,
-					pXsvfInfo->sShiftLengthBytes,
-					&(pXsvfInfo->lvTdi),
-					&(pXsvfInfo->lvTdoCaptured),
-					&(pXsvfInfo->lvTdoExpected),
-					/*plvTdoMask*/0, ucEndDR,
-					/*lRunTestTime*/0, /*ucMaxRepeat*/0 );
-	if ( iErrorCode != XSVF_ERROR_NONE )
-	{
-		pXsvfInfo->iErrorCode   = iErrorCode;
-	}
-	return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function:     xsvfDoXSTATE
- * Description:  XSTATE <byte>
- *               <byte> == XTAPSTATE;
- *               Get the state parameter and transition the TAP to that state.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-int xsvfDoXSTATE( SXsvfInfo* pXsvfInfo )
-{
-	unsigned char   ucNextState;
-	int             iErrorCode;
-	readByte( &ucNextState );
-	iErrorCode  = xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucNextState );
-	if ( iErrorCode != XSVF_ERROR_NONE )
-	{
-		pXsvfInfo->iErrorCode   = iErrorCode;
-	}
-	return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function:     xsvfDoXENDXR
- * Description:  XENDIR/XENDDR <byte>
- *               <byte>:  0 = RUNTEST;  1 = PAUSE.
- *               Get the prespecified XENDIR or XENDDR.
- *               Both XENDIR and XENDDR use the same implementation.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-int xsvfDoXENDXR( SXsvfInfo* pXsvfInfo )
-{
-	int             iErrorCode;
-	unsigned char   ucEndState;
-
-	iErrorCode  = XSVF_ERROR_NONE;
-	readByte( &ucEndState );
-	if ( ( ucEndState != XENDXR_RUNTEST ) && ( ucEndState != XENDXR_PAUSE ) )
-	{
-		iErrorCode  = XSVF_ERROR_ILLEGALSTATE;
-	}
-	else
-	{
-
-		if ( pXsvfInfo->ucCommand == XENDIR )
-		{
-			if ( ucEndState == XENDXR_RUNTEST )
-			{
-				pXsvfInfo->ucEndIR  = XTAPSTATE_RUNTEST;
-			}
-			else
-			{
-				pXsvfInfo->ucEndIR  = XTAPSTATE_PAUSEIR;
-			}
-			XSVFDBG_PRINTF1( 3, "   ENDIR State = %s\n",
-					 xsvf_pzTapState[ pXsvfInfo->ucEndIR ] );
-		}
-		else    /* XENDDR */
-		{
-			if ( ucEndState == XENDXR_RUNTEST )
-			{
-				pXsvfInfo->ucEndDR  = XTAPSTATE_RUNTEST;
-			}
-			else
-			{
-				pXsvfInfo->ucEndDR  = XTAPSTATE_PAUSEDR;
-			}
-			XSVFDBG_PRINTF1( 3, "   ENDDR State = %s\n",
-					 xsvf_pzTapState[ pXsvfInfo->ucEndDR ] );
-		}
-	}
-
-	if ( iErrorCode != XSVF_ERROR_NONE )
-	{
-		pXsvfInfo->iErrorCode   = iErrorCode;
-	}
-	return( iErrorCode );
-}
-
-/*****************************************************************************
- * Function:     xsvfDoXCOMMENT
- * Description:  XCOMMENT <text string ending in \0>
- *               <text string ending in \0> == text comment;
- *               Arbitrary comment embedded in the XSVF.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-int xsvfDoXCOMMENT( SXsvfInfo* pXsvfInfo )
-{
-	/* Use the comment for debugging */
-	/* Otherwise, read through the comment to the end '\0' and ignore */
-	unsigned char   ucText;
-
-	if ( xsvf_iDebugLevel > 0 )
-	{
-		putc( ' ' );
-	}
-
-	do
-	{
-		readByte( &ucText );
-		if ( xsvf_iDebugLevel > 0 )
-		{
-			putc( ucText ? ucText : '\n' );
-		}
-	} while ( ucText );
-
-	pXsvfInfo->iErrorCode   = XSVF_ERROR_NONE;
-
-	return( pXsvfInfo->iErrorCode );
-}
-
-/*****************************************************************************
- * Function:     xsvfDoXWAIT
- * Description:  XWAIT <wait_state> <end_state> <wait_time>
- *               If not already in <wait_state>, then go to <wait_state>.
- *               Wait in <wait_state> for <wait_time> microseconds.
- *               Finally, if not already in <end_state>, then goto <end_state>.
- * Parameters:   pXsvfInfo   - XSVF information pointer.
- * Returns:      int         - 0 = success;  non-zero = error.
- *****************************************************************************/
-int xsvfDoXWAIT( SXsvfInfo* pXsvfInfo )
-{
-	unsigned char   ucWaitState;
-	unsigned char   ucEndState;
-	long            lWaitTime;
-
-	/* Get Parameters */
-	/* <wait_state> */
-	readVal( &(pXsvfInfo->lvTdi), 1 );
-	ucWaitState = pXsvfInfo->lvTdi.val[0];
-
-	/* <end_state> */
-	readVal( &(pXsvfInfo->lvTdi), 1 );
-	ucEndState = pXsvfInfo->lvTdi.val[0];
-
-	/* <wait_time> */
-	readVal( &(pXsvfInfo->lvTdi), 4 );
-	lWaitTime = value( &(pXsvfInfo->lvTdi) );
-	XSVFDBG_PRINTF2( 3, "   XWAIT:  state = %s; time = %ld\n",
-			 xsvf_pzTapState[ ucWaitState ], lWaitTime );
-
-	/* If not already in <wait_state>, go to <wait_state> */
-	if ( pXsvfInfo->ucTapState != ucWaitState )
-	{
-		xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucWaitState );
-	}
-
-	/* Wait for <wait_time> microseconds */
-	waitTime( lWaitTime );
-
-	/* If not already in <end_state>, go to <end_state> */
-	if ( pXsvfInfo->ucTapState != ucEndState )
-	{
-		xsvfGotoTapState( &(pXsvfInfo->ucTapState), ucEndState );
-	}
-
-	return( XSVF_ERROR_NONE );
-}
-
-
-/*============================================================================
- * Execution Control Functions
- ============================================================================*/
-
-/*****************************************************************************
- * Function:     xsvfInitialize
- * Description:  Initialize the xsvf player.
- *               Call this before running the player to initialize the data
- *               in the SXsvfInfo struct.
- *               xsvfCleanup is called to clean up the data in SXsvfInfo
- *               after the XSVF is played.
- * Parameters:   pXsvfInfo   - ptr to the XSVF information.
- * Returns:      int - 0 = success; otherwise error.
- *****************************************************************************/
-int xsvfInitialize( SXsvfInfo* pXsvfInfo )
-{
-	/* Initialize values */
-	pXsvfInfo->iErrorCode   = xsvfInfoInit( pXsvfInfo );
-
-	if ( !pXsvfInfo->iErrorCode )
-	{
-		/* Initialize the TAPs */
-		pXsvfInfo->iErrorCode   = xsvfGotoTapState( &(pXsvfInfo->ucTapState),
-							    XTAPSTATE_RESET );
-	}
-
-	return( pXsvfInfo->iErrorCode );
-}
-
-/*****************************************************************************
- * Function:     xsvfRun
- * Description:  Run the xsvf player for a single command and return.
- *               First, call xsvfInitialize.
- *               Then, repeatedly call this function until an error is detected
- *               or until the pXsvfInfo->ucComplete variable is non-zero.
- *               Finally, call xsvfCleanup to cleanup any remnants.
- * Parameters:   pXsvfInfo   - ptr to the XSVF information.
- * Returns:      int         - 0 = success; otherwise error.
- *****************************************************************************/
-int xsvfRun( SXsvfInfo* pXsvfInfo )
-{
-	/* Process the XSVF commands */
-	if ( (!pXsvfInfo->iErrorCode) && (!pXsvfInfo->ucComplete) )
-	{
-		/* read 1 byte for the instruction */
-		readByte( &(pXsvfInfo->ucCommand) );
-		++(pXsvfInfo->lCommandCount);
-
-		if ( pXsvfInfo->ucCommand < XLASTCMD )
-		{
-			/* Execute the command.  Func sets error code. */
-			XSVFDBG_PRINTF1( 2, "  %s\n",
-					 xsvf_pzCommandName[pXsvfInfo->ucCommand] );
-			/* If your compiler cannot take this form,
-			   then convert to a switch statement */
-#if 0 /* test-only */
-			xsvf_pfDoCmd[ pXsvfInfo->ucCommand ]( pXsvfInfo );
-#else
-			switch (pXsvfInfo->ucCommand) {
-			case 0:
-				xsvfDoXCOMPLETE(pXsvfInfo);        /*  0 */
-				break;
-			case 1:
-				xsvfDoXTDOMASK(pXsvfInfo);         /*  1 */
-				break;
-			case 2:
-				xsvfDoXSIR(pXsvfInfo);             /*  2 */
-				break;
-			case 3:
-				xsvfDoXSDR(pXsvfInfo);             /*  3 */
-				break;
-			case 4:
-				xsvfDoXRUNTEST(pXsvfInfo);         /*  4 */
-				break;
-			case 5:
-				xsvfDoIllegalCmd(pXsvfInfo);       /*  5 */
-				break;
-			case 6:
-				xsvfDoIllegalCmd(pXsvfInfo);       /*  6 */
-				break;
-			case 7:
-				xsvfDoXREPEAT(pXsvfInfo);          /*  7 */
-				break;
-			case 8:
-				xsvfDoXSDRSIZE(pXsvfInfo);         /*  8 */
-				break;
-			case 9:
-				xsvfDoXSDRTDO(pXsvfInfo);          /*  9 */
-				break;
-#ifdef  XSVF_SUPPORT_COMPRESSION
-			case 10:
-				xsvfDoXSETSDRMASKS(pXsvfInfo);     /* 10 */
-				break;
-			case 11:
-				xsvfDoXSDRINC(pXsvfInfo);          /* 11 */
-				break;
-#else
-			case 10:
-				xsvfDoIllegalCmd(pXsvfInfo);       /* 10 */
-				break;
-			case 11:
-				xsvfDoIllegalCmd(pXsvfInfo);       /* 11 */
-				break;
-#endif  /* XSVF_SUPPORT_COMPRESSION */
-			case 12:
-				xsvfDoXSDRBCE(pXsvfInfo);          /* 12 */
-				break;
-			case 13:
-				xsvfDoXSDRBCE(pXsvfInfo);          /* 13 */
-				break;
-			case 14:
-				xsvfDoXSDRBCE(pXsvfInfo);          /* 14 */
-				break;
-			case 15:
-				xsvfDoXSDRTDOBCE(pXsvfInfo);       /* 15 */
-				break;
-			case 16:
-				xsvfDoXSDRTDOBCE(pXsvfInfo);       /* 16 */
-				break;
-			case 17:
-				xsvfDoXSDRTDOBCE(pXsvfInfo);       /* 17 */
-				break;
-			case 18:
-				xsvfDoXSTATE(pXsvfInfo);           /* 18 */
-				break;
-			case 19:
-				xsvfDoXENDXR(pXsvfInfo);           /* 19 */
-				break;
-			case 20:
-				xsvfDoXENDXR(pXsvfInfo);           /* 20 */
-				break;
-			case 21:
-				xsvfDoXSIR2(pXsvfInfo);            /* 21 */
-				break;
-			case 22:
-				xsvfDoXCOMMENT(pXsvfInfo);         /* 22 */
-				break;
-			case 23:
-				xsvfDoXWAIT(pXsvfInfo);             /* 23 */
-				break;
-			}
-#endif
-		}
-		else
-		{
-			/* Illegal command value.  Func sets error code. */
-			xsvfDoIllegalCmd( pXsvfInfo );
-		}
-	}
-
-	return( pXsvfInfo->iErrorCode );
-}
-
-/*****************************************************************************
- * Function:     xsvfCleanup
- * Description:  cleanup remnants of the xsvf player.
- * Parameters:   pXsvfInfo   - ptr to the XSVF information.
- * Returns:      void.
- *****************************************************************************/
-void xsvfCleanup( SXsvfInfo* pXsvfInfo )
-{
-	xsvfInfoCleanup( pXsvfInfo );
-}
-
-
-/*============================================================================
- * xsvfExecute() - The primary entry point to the XSVF player
- ============================================================================*/
-
-/*****************************************************************************
- * Function:     xsvfExecute
- * Description:  Process, interpret, and apply the XSVF commands.
- *               See port.c:readByte for source of XSVF data.
- * Parameters:   none.
- * Returns:      int - Legacy result values:  1 == success;  0 == failed.
- *****************************************************************************/
-int xsvfExecute(void)
-{
-	SXsvfInfo   xsvfInfo;
-
-	xsvfInitialize( &xsvfInfo );
-
-	while ( !xsvfInfo.iErrorCode && (!xsvfInfo.ucComplete) )
-	{
-		xsvfRun( &xsvfInfo );
-	}
-
-	if ( xsvfInfo.iErrorCode )
-	{
-		XSVFDBG_PRINTF1( 0, "%s\n", xsvf_pzErrorName[
-					 ( xsvfInfo.iErrorCode < XSVF_ERROR_LAST )
-					 ? xsvfInfo.iErrorCode : XSVF_ERROR_UNKNOWN ] );
-		XSVFDBG_PRINTF2( 0, "ERROR at or near XSVF command #%ld.  See line #%ld in the XSVF ASCII file.\n",
-				 xsvfInfo.lCommandCount, xsvfInfo.lCommandCount );
-	}
-	else
-	{
-		XSVFDBG_PRINTF( 0, "SUCCESS - Completed XSVF execution.\n" );
-	}
-
-	xsvfCleanup( &xsvfInfo );
-
-	return( XSVF_ERRORCODE(xsvfInfo.iErrorCode) );
-}
-
-
-/*****************************************************************************
- * Function:     do_cpld
- * Description:  main function.
- *               Specified here for creating stand-alone debug executable.
- *               Embedded users should call xsvfExecute() directly.
- * Parameters:   iArgc    - number of command-line arguments.
- *               ppzArgv  - array of ptrs to strings (command-line arguments).
- * Returns:      int      - Legacy return value:  1 = success; 0 = error.
- *****************************************************************************/
-int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int     iErrorCode;
-	unsigned long duration;
-	unsigned long long startClock, endClock;
-
-	if (argc == 2)
-		xsvfdata = (unsigned char *)simple_strtoul(argv[1], NULL, 16);
-	else {
-#ifdef CONFIG_SYS_XSVF_DEFAULT_ADDR
-		xsvfdata = (unsigned char *)CONFIG_SYS_XSVF_DEFAULT_ADDR;
-#else
-		printf("Usage:\ncpld %s\n", cmdtp->help);
-		return -1;
-#endif
-	}
-
-	iErrorCode          = XSVF_ERRORCODE( XSVF_ERROR_NONE );
-	xsvf_iDebugLevel    = 0;
-
-	printf("XSVF Player v%s, Xilinx, Inc.\n", XSVF_VERSION);
-	printf("Reading XSVF data @ %p\n", xsvfdata);
-
-	/* Initialize the I/O.  SetPort initializes I/O on first call */
-	setPort( TMS, 1 );
-
-	/* Execute the XSVF in the file */
-	startClock  = get_ticks();
-	iErrorCode  = xsvfExecute();
-	endClock    = get_ticks();
-	duration    = (unsigned long)(endClock - startClock);
-	printf("\nExecution Time = %d seconds\n", (int)(duration/get_tbclk()));
-
-	return( iErrorCode );
-}
-U_BOOT_CMD(
-	cpld,	2,	1,	do_cpld,
-	"program onboard CPLD",
-	"<xsvf-addr>"
-);
diff --git a/board/esd/common/xilinx_jtag/micro.h b/board/esd/common/xilinx_jtag/micro.h
deleted file mode 100644
index e9a7612..0000000
--- a/board/esd/common/xilinx_jtag/micro.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*****************************************************************************
- * File:         micro.h
- * Description:  This header file contains the function prototype to the
- *               primary interface function for the XSVF player.
- * Usage:        FIRST - PORTS.C
- *               Customize the ports.c function implementations to establish
- *               the correct protocol for communicating with your JTAG ports
- *               (setPort() and readTDOBit()) and tune the waitTime() delay
- *               function.  Also, establish access to the XSVF data source
- *               in the readByte() function.
- *               FINALLY - Call xsvfExecute().
- *****************************************************************************/
-#ifndef XSVF_MICRO_H
-#define XSVF_MICRO_H
-
-/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */
-#define XSVF_LEGACY_SUCCESS 1
-#define XSVF_LEGACY_ERROR   0
-
-/* 4.04 [NEW] Error codes for xsvfExecute. */
-/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */
-#define XSVF_ERROR_NONE         0
-#define XSVF_ERROR_UNKNOWN      1
-#define XSVF_ERROR_TDOMISMATCH  2
-#define XSVF_ERROR_MAXRETRIES   3   /* TDO mismatch after max retries */
-#define XSVF_ERROR_ILLEGALCMD   4
-#define XSVF_ERROR_ILLEGALSTATE 5
-#define XSVF_ERROR_DATAOVERFLOW 6   /* Data > lenVal MAX_LEN buffer size*/
-/* Insert new errors here */
-#define XSVF_ERROR_LAST         7
-
-/*****************************************************************************
- * Function:     xsvfExecute
- * Description:  Process, interpret, and apply the XSVF commands.
- *               See port.c:readByte for source of XSVF data.
- * Parameters:   none.
- * Returns:      int - For error codes see above.
- *****************************************************************************/
-int xsvfExecute(void);
-
-#endif  /* XSVF_MICRO_H */
diff --git a/board/esd/common/xilinx_jtag/ports.c b/board/esd/common/xilinx_jtag/ports.c
deleted file mode 100644
index d79dbd1..0000000
--- a/board/esd/common/xilinx_jtag/ports.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*******************************************************/
-/* file: ports.c                                       */
-/* abstract:  This file contains the routines to       */
-/*            output values on the JTAG ports, to read */
-/*            the TDO bit, and to read a byte of data  */
-/*            from the prom                            */
-/*                                                     */
-/*******************************************************/
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#include "ports.h"
-
-static unsigned long output = 0;
-static int filepos = 0;
-static int oldstate = 0;
-static int newstate = 0;
-static int readptr = 0;
-
-extern const unsigned char *xsvfdata;
-
-/* if in debugging mode, then just set the variables */
-void setPort(short p,short val)
-{
-	if (p==TMS) {
-		if (val) {
-			output |= JTAG_TMS;
-		} else {
-			output &= ~JTAG_TMS;
-		}
-	}
-	if (p==TDI) {
-		if (val) {
-			output |= JTAG_TDI;
-		} else {
-			output &= ~JTAG_TDI;
-		}
-	}
-	if (p==TCK) {
-		if (val) {
-			output |= JTAG_TCK;
-		} else {
-			output &= ~JTAG_TCK;
-		}
-		out_be32((void *)GPIO0_OR, output);
-	}
-}
-
-
-/* toggle tck LH */
-void pulseClock(void)
-{
-	setPort(TCK,0);  /* set the TCK port to low  */
-	setPort(TCK,1);  /* set the TCK port to high */
-}
-
-
-/* read in a byte of data from the prom */
-void readByte(unsigned char *data)
-{
-	/* pretend reading using a file */
-	*data = xsvfdata[readptr++];
-	newstate = filepos++ >> 10;
-	if (newstate != oldstate) {
-		printf("%4d kB\r\r\r\r", newstate);
-		oldstate = newstate;
-	}
-}
-
-/* read the TDO bit from port */
-unsigned char readTDOBit(void)
-{
-	unsigned long inputs;
-
-	inputs = in_be32((void *)GPIO0_IR);
-	if (inputs & JTAG_TDO)
-		return 1;
-	else
-		return 0;
-}
-
-
-/* Wait at least the specified number of microsec.                           */
-/* Use a timer if possible; otherwise estimate the number of instructions    */
-/* necessary to be run based on the microcontroller speed.  For this example */
-/* we pulse the TCK port a number of times based on the processor speed.     */
-void waitTime(long microsec)
-{
-	udelay(microsec); /* esd */
-}
diff --git a/board/esd/common/xilinx_jtag/ports.h b/board/esd/common/xilinx_jtag/ports.h
deleted file mode 100644
index 8ee7de9..0000000
--- a/board/esd/common/xilinx_jtag/ports.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*******************************************************/
-/* file: ports.h                                       */
-/* abstract:  This file contains extern declarations   */
-/*            for providing stimulus to the JTAG ports.*/
-/*******************************************************/
-
-#ifndef ports_dot_h
-#define ports_dot_h
-
-/* these constants are used to send the appropriate ports to setPort */
-/* they should be enumerated types, but some of the microcontroller  */
-/* compilers don't like enumerated types */
-#define TCK (short) 0
-#define TMS (short) 1
-#define TDI (short) 2
-
-/*
- * Use CONFIG_SYS_FPGA_xxx defines from board include file.
- */
-#define JTAG_TMS   CONFIG_SYS_FPGA_PRG     /* output */
-#define JTAG_TCK   CONFIG_SYS_FPGA_CLK     /* output */
-#define JTAG_TDI   CONFIG_SYS_FPGA_DATA    /* output */
-#define JTAG_TDO   CONFIG_SYS_FPGA_DONE    /* input */
-
-/* set the port "p" (TCK, TMS, or TDI) to val (0 or 1) */
-void setPort(short p, short val);
-
-/* read the TDO bit and store it in val */
-unsigned char readTDOBit(void);
-
-/* make clock go down->up->down*/
-void pulseClock(void);
-
-/* read the next byte of data from the xsvf file */
-void readByte(unsigned char *data);
-
-void waitTime(long microsec);
-
-#endif
diff --git a/board/esd/cpci2dp/Kconfig b/board/esd/cpci2dp/Kconfig
deleted file mode 100644
index 646e8ff..0000000
--- a/board/esd/cpci2dp/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_CPCI2DP
-
-config SYS_BOARD
-	default "cpci2dp"
-
-config SYS_VENDOR
-	default "esd"
-
-config SYS_CONFIG_NAME
-	default "CPCI2DP"
-
-endif
diff --git a/board/esd/cpci2dp/MAINTAINERS b/board/esd/cpci2dp/MAINTAINERS
deleted file mode 100644
index 660e185..0000000
--- a/board/esd/cpci2dp/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CPCI2DP BOARD
-M:	Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S:	Maintained
-F:	board/esd/cpci2dp/
-F:	include/configs/CPCI2DP.h
-F:	configs/CPCI2DP_defconfig
diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile
deleted file mode 100644
index ce2c6dd..0000000
--- a/board/esd/cpci2dp/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= cpci2dp.o flash.o ../common/misc.o ../common/cmd_loadpci.o
diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c
deleted file mode 100644
index 336c551..0000000
--- a/board/esd/cpci2dp/cpci2dp.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * (C) Copyright 2005
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f (void)
-{
-	unsigned long CPC0_CR0Reg;
-
-	/*
-	 * Setup GPIO pins
-	 */
-	CPC0_CR0Reg = mfdcr(CPC0_CR0);
-	mtdcr(CPC0_CR0, CPC0_CR0Reg |
-	      ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED |
-		CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));
-
-	/* set output pins to high */
-	out_be32((void *)GPIO0_OR,  CONFIG_SYS_EEPROM_WP);
-	/* setup for output (LED=off) */
-	out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED);
-
-	/*
-	 * IRQ 0-15  405GP internally generated; active high; level sensitive
-	 * IRQ 16    405GP internally generated; active low; level sensitive
-	 * IRQ 17-24 RESERVED
-	 * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
-	 * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
-	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
-	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
-	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
-	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
-	 * IRQ 31 (EXT IRQ 6) unused
-	 */
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
-	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical*/
-	mtdcr(UIC0PR, 0xFFFFFF81);	/* set int polarities */
-
-	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
-	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority*/
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-
-	return 0;
-}
-
-int misc_init_r (void)
-{
-	unsigned long CPC0_CR0Reg;
-
-	/* adjust flash start and offset */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-	gd->bd->bi_flashoffset = 0;
-
-	/*
-	 * Select cts (and not dsr) on uart1
-	 */
-	CPC0_CR0Reg = mfdcr(CPC0_CR0);
-	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
-
-	return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
-	char str[64];
-	int i = getenv_f("serial#", str, sizeof(str));
-
-	puts ("Board: ");
-
-	if (i == -1) {
-		puts ("### No HW ID - assuming CPCI2DP");
-	} else {
-		puts(str);
-	}
-
-	printf(" (Ver 1.0)");
-
-	putc ('\n');
-
-	return 0;
-}
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-/* Input: <dev_addr>  I2C address of EEPROM device to enable.
- *	   <state>     -1: deliver current state
- *		       0: disable write
- *		       1: enable write
- *  Returns:	       -1: wrong device address
- *			0: dis-/en- able done
- *		     0/1: current state if <state> was -1.
- */
-int eeprom_write_enable (unsigned dev_addr, int state) {
-	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
-		return -1;
-	} else {
-		switch (state) {
-		case 1:
-			/* Enable write access, clear bit GPIO_SINT2. */
-			out_be32((void *)GPIO0_OR,
-				 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
-			state = 0;
-			break;
-		case 0:
-			/* Disable write access, set bit GPIO_SINT2. */
-			out_be32((void *)GPIO0_OR,
-				 in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
-			state = 0;
-			break;
-		default:
-			/* Read current status back. */
-			state = (0 == (in_be32((void *)GPIO0_OR) &
-				       CONFIG_SYS_EEPROM_WP));
-			break;
-		}
-	}
-	return state;
-}
-#endif
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int query = argc == 1;
-	int state = 0;
-
-	if (query) {
-		/* Query write access state. */
-		state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
-		if (state < 0) {
-			puts ("Query of write access state failed.\n");
-		} else {
-			printf ("Write access for device 0x%0x is %sabled.\n",
-				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
-			state = 0;
-		}
-	} else {
-		if ('0' == argv[1][0]) {
-			/* Disable write access. */
-			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
-		} else {
-			/* Enable write access. */
-			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
-		}
-		if (state < 0) {
-			puts ("Setup of write access state failed.\n");
-		}
-	}
-
-	return state;
-}
-
-U_BOOT_CMD(
-	eepwren,	2,	0,	do_eep_wren,
-	"Enable / disable / query EEPROM write access",
-	""
-);
-#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/esd/cpci2dp/flash.c b/board/esd/cpci2dp/flash.c
deleted file mode 100644
index 34bdc05..0000000
--- a/board/esd/cpci2dp/flash.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	unsigned long size_b0;
-	int i;
-	uint pbcr;
-	unsigned long base_b0;
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
-	}
-
-	/* Setup offsets */
-	flash_get_offsets (-size_b0, &flash_info[0]);
-
-	/* Re-do sizing to get full correct info */
-	mtdcr(EBC0_CFGADDR, PB0CR);
-	pbcr = mfdcr(EBC0_CFGDATA);
-	mtdcr(EBC0_CFGADDR, PB0CR);
-	base_b0 = -size_b0;
-	pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
-	mtdcr(EBC0_CFGDATA, pbcr);
-	/*          printf("PB1CR = %x\n", pbcr); */
-
-	/* Monitor protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    -monitor_flash_len,
-			    0xffffffff,
-			    &flash_info[0]);
-
-	flash_info[0].size = size_b0;
-
-	return (size_b0);
-}
diff --git a/board/esd/cpci405/Kconfig b/board/esd/cpci405/Kconfig
deleted file mode 100644
index 0df2755..0000000
--- a/board/esd/cpci405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_CPCI4052
-
-config SYS_BOARD
-	default "cpci405"
-
-config SYS_VENDOR
-	default "esd"
-
-config SYS_CONFIG_NAME
-	default "CPCI4052"
-
-endif
diff --git a/board/esd/cpci405/MAINTAINERS b/board/esd/cpci405/MAINTAINERS
deleted file mode 100644
index 1da58dc..0000000
--- a/board/esd/cpci405/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-CPCI405 BOARD
-M:	Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S:	Maintained
-F:	board/esd/cpci405/
-F:	include/configs/CPCI405.h
-F:	configs/CPCI405_defconfig
-F:	include/configs/CPCI4052.h
-F:	configs/CPCI4052_defconfig
-F:	include/configs/CPCI405AB.h
-F:	configs/CPCI405AB_defconfig
-F:	include/configs/CPCI405DT.h
-F:	configs/CPCI405DT_defconfig
diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile
deleted file mode 100644
index 7490b78..0000000
--- a/board/esd/cpci405/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= cpci405.o flash.o ../common/misc.o
-obj-y	+= ../common/cmd_loadpci.o
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
deleted file mode 100644
index c510ab1..0000000
--- a/board/esd/cpci405/cpci405.c
+++ /dev/null
@@ -1,496 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <console.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-#include <net.h>
-#include <pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void __ft_board_setup(void *blob, bd_t *bd);
-
-#undef FPGA_DEBUG
-
-/* fpga configuration data - generated by bin2cc */
-const unsigned char fpgadata[] =
-{
-#if defined(CONFIG_CPCI405_VER2)
-# include "fpgadata_cpci4052.c"
-#endif
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-/* Prototypes */
-int cpci405_version(void);
-void lxt971_no_sleep(void);
-
-int board_early_init_f(void)
-{
-#ifndef CONFIG_CPCI405_VER2
-	int index, len, i;
-	int status;
-#endif
-
-#ifdef FPGA_DEBUG
-	/* set up serial port with default baudrate */
-	(void)get_clocks();
-	gd->baudrate = CONFIG_BAUDRATE;
-	serial_init();
-	console_init_f();
-#endif
-
-	/*
-	 * First pull fpga-prg pin low,
-	 * to disable fpga logic (on version 2 board)
-	 */
-	out_be32((void *)GPIO0_ODR, 0x00000000);	     /* no open drain pins	*/
-	out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output	*/
-	out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
-	out_be32((void *)GPIO0_OR, 0);		     /* pull prg low		*/
-
-	/*
-	 * Boot onboard FPGA
-	 */
-#ifndef CONFIG_CPCI405_VER2
-	if (cpci405_version() == 1) {
-		status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
-		if (status != 0) {
-			/* booting FPGA failed */
-#ifndef FPGA_DEBUG
-			/* set up serial port with default baudrate */
-			(void)get_clocks();
-			gd->baudrate = CONFIG_BAUDRATE;
-			serial_init();
-			console_init_f();
-#endif
-			printf("\nFPGA: Booting failed ");
-			switch (status) {
-			case ERROR_FPGA_PRG_INIT_LOW:
-				printf("(Timeout: INIT not low after "
-				       "asserting PROGRAM*)\n ");
-				break;
-			case ERROR_FPGA_PRG_INIT_HIGH:
-				printf("(Timeout: INIT not high after "
-				       "deasserting PROGRAM*)\n ");
-				break;
-			case ERROR_FPGA_PRG_DONE:
-				printf("(Timeout: DONE not high after "
-				       "programming FPGA)\n ");
-				break;
-			}
-
-			/* display infos on fpgaimage */
-			index = 15;
-			for (i = 0; i < 4; i++) {
-				len = fpgadata[index];
-				printf("FPGA: %s\n", &(fpgadata[index + 1]));
-				index += len + 3;
-			}
-			putc('\n');
-			/* delayed reboot */
-			for (i = 20; i > 0; i--) {
-				printf("Rebooting in %2d seconds \r",i);
-				for (index = 0; index < 1000; index++)
-					udelay(1000);
-			}
-			putc('\n');
-			do_reset(NULL, 0, 0, NULL);
-		}
-	}
-#endif /* !CONFIG_CPCI405_VER2 */
-
-	/*
-	 * IRQ 0-15  405GP internally generated; active high; level sensitive
-	 * IRQ 16    405GP internally generated; active low; level sensitive
-	 * IRQ 17-24 RESERVED
-	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
-	 * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
-	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
-	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
-	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
-	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
-	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
-	 */
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
-	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical*/
-#if defined(CONFIG_CPCI405_6U)
-	if (cpci405_version() == 3) {
-		mtdcr(UIC0PR, 0xFFFFFF99);	/* set int polarities */
-	} else {
-		mtdcr(UIC0PR, 0xFFFFFF81);	/* set int polarities */
-	}
-#else
-	mtdcr(UIC0PR, 0xFFFFFF81);	/* set int polarities */
-#endif
-	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
-	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,
-					 * INT0 highest priority */
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-
-	return 0;
-}
-
-int ctermm2(void)
-{
-#if defined(CONFIG_CPCI405_VER2)
-	return 0;			/* no, board is cpci405 */
-#else
-	if ((in_8((void*)0xf0000400) == 0x00) &&
-	    (in_8((void*)0xf0000401) == 0x01))
-		return 0;		/* no, board is cpci405 */
-	else
-		return -1;		/* yes, board is cterm-m2 */
-#endif
-}
-
-int cpci405_host(void)
-{
-	if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
-		return -1;		/* yes, board is cpci405 host */
-	else
-		return 0;		/* no, board is cpci405 adapter */
-}
-
-int cpci405_version(void)
-{
-	unsigned long CPC0_CR0Reg;
-	unsigned long value;
-
-	/*
-	 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
-	 */
-	CPC0_CR0Reg = mfdcr(CPC0_CR0);
-	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
-	out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
-	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
-	udelay(1000); /* wait some time before reading input */
-	value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
-
-	/*
-	 * Restore GPIO settings
-	 */
-	mtdcr(CPC0_CR0, CPC0_CR0Reg);
-
-	switch (value) {
-	case 0x00180000:
-		/* CS2==1 && CS3==1 -> version 1 */
-		return 1;
-	case 0x00080000:
-		/* CS2==0 && CS3==1 -> version 2 */
-		return 2;
-	case 0x00100000:
-		/* CS2==1 && CS3==0 -> version 3 or 6U board */
-		return 3;
-	case 0x00000000:
-		/* CS2==0 && CS3==0 -> version 4 */
-		return 4;
-	default:
-		/* should not be reached! */
-		return 2;
-	}
-}
-
-int misc_init_r (void)
-{
-	unsigned long CPC0_CR0Reg;
-
-	/* adjust flash start and offset */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-	gd->bd->bi_flashoffset = 0;
-
-#if defined(CONFIG_CPCI405_VER2)
-	{
-	unsigned char *dst;
-	ulong len = sizeof(fpgadata);
-	int status;
-	int index;
-	int i;
-
-	/*
-	 * On CPCI-405 version 2 the environment is saved in eeprom!
-	 * FPGA can be gzip compressed (malloc) and booted this late.
-	 */
-	if (cpci405_version() >= 2) {
-		/*
-		 * Setup GPIO pins (CS6+CS7 as GPIO)
-		 */
-		CPC0_CR0Reg = mfdcr(CPC0_CR0);
-		mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
-
-		dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
-		if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
-			   (uchar *)fpgadata, &len) != 0) {
-			printf("GUNZIP ERROR - must RESET board to recover\n");
-			do_reset(NULL, 0, 0, NULL);
-		}
-
-		status = fpga_boot(dst, len);
-		if (status != 0) {
-			printf("\nFPGA: Booting failed ");
-			switch (status) {
-			case ERROR_FPGA_PRG_INIT_LOW:
-				printf("(Timeout: INIT not low after "
-				       "asserting PROGRAM*)\n ");
-				break;
-			case ERROR_FPGA_PRG_INIT_HIGH:
-				printf("(Timeout: INIT not high after "
-				       "deasserting PROGRAM*)\n ");
-				break;
-			case ERROR_FPGA_PRG_DONE:
-				printf("(Timeout: DONE not high after "
-				       "programming FPGA)\n ");
-				break;
-			}
-
-			/* display infos on fpgaimage */
-			index = 15;
-			for (i = 0; i < 4; i++) {
-				len = dst[index];
-				printf("FPGA: %s\n", &(dst[index + 1]));
-				index += len + 3;
-			}
-			putc('\n');
-			/* delayed reboot */
-			for (i = 20; i > 0; i--) {
-				printf("Rebooting in %2d seconds \r", i);
-				for (index = 0; index < 1000; index++)
-					udelay(1000);
-			}
-			putc('\n');
-			do_reset(NULL, 0, 0, NULL);
-		}
-
-		/* restore gpio/cs settings */
-		mtdcr(CPC0_CR0, CPC0_CR0Reg);
-
-		puts("FPGA:  ");
-
-		/* display infos on fpgaimage */
-		index = 15;
-		for (i = 0; i < 4; i++) {
-			len = dst[index];
-			printf("%s ", &(dst[index + 1]));
-			index += len + 3;
-		}
-		putc('\n');
-
-		free(dst);
-
-		/*
-		 * Reset FPGA via FPGA_DATA pin
-		 */
-		SET_FPGA(FPGA_PRG | FPGA_CLK);
-		udelay(1000); /* wait 1ms */
-		SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
-		udelay(1000); /* wait 1ms */
-
-#if defined(CONFIG_CPCI405_6U)
-#error HIER GETH ES WEITER MIT IO ACCESSORS
-		if (cpci405_version() == 3) {
-			/*
-			 * Enable outputs in fpga on version 3 board
-			 */
-			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
-				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
-				 CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
-
-			/*
-			 * Set outputs to 0
-			 */
-			out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
-
-			/*
-			 * Reset external DUART
-			 */
-			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
-				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
-				 CONFIG_SYS_FPGA_MODE_DUART_RESET);
-			udelay(100);
-			out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
-				 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
-				 ~CONFIG_SYS_FPGA_MODE_DUART_RESET);
-		}
-#endif
-	}
-	else {
-		puts("\n*** U-Boot Version does not match Board Version!\n");
-		puts("*** CPCI-405 Version 1.x detected!\n");
-		puts("*** Please use correct U-Boot version "
-		     "(CPCI405 instead of CPCI4052)!\n\n");
-	}
-	}
-#else /* CONFIG_CPCI405_VER2 */
-	if (cpci405_version() >= 2) {
-		puts("\n*** U-Boot Version does not match Board Version!\n");
-		puts("*** CPCI-405 Board Version 2.x detected!\n");
-		puts("*** Please use correct U-Boot version "
-		     "(CPCI4052 instead of CPCI405)!\n\n");
-	}
-#endif /* CONFIG_CPCI405_VER2 */
-
-	/*
-	 * Select cts (and not dsr) on uart1
-	 */
-	CPC0_CR0Reg = mfdcr(CPC0_CR0);
-	mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
-
-	return 0;
-}
-
-/*
- * Check Board Identity:
- */
-
-int checkboard(void)
-{
-#ifndef CONFIG_CPCI405_VER2
-	int index;
-	int len;
-#endif
-	char str[64];
-	int i = getenv_f("serial#", str, sizeof(str));
-	unsigned short ver;
-
-	puts("Board: ");
-
-	if (i == -1)
-		puts("### No HW ID - assuming CPCI405");
-	else
-		puts(str);
-
-	ver = cpci405_version();
-	printf(" (Ver %d.x, ", ver);
-
-	if (ctermm2()) {
-		char str[4];
-
-		/*
-		 * Read board-id and save in env-variable
-		 */
-		sprintf(str, "%d", *(unsigned char *)0xf0000400);
-		setenv("boardid", str);
-		printf("CTERM-M2 - Id=%s)", str);
-	} else {
-		if (cpci405_host())
-			puts("PCI Host Version)");
-		else
-			puts("PCI Adapter Version)");
-	}
-
-#ifndef CONFIG_CPCI405_VER2
-	puts("\nFPGA:	");
-
-	/* display infos on fpgaimage */
-	index = 15;
-	for (i = 0; i < 4; i++) {
-		len = fpgadata[index];
-		printf("%s ", &(fpgadata[index + 1]));
-		index += len + 3;
-	}
-#endif
-
-	putc('\n');
-	return 0;
-}
-
-void reset_phy(void)
-{
-#if defined(CONFIG_LXT971_NO_SLEEP)
-
-	/*
-	 * Disable sleep mode in LXT971
-	 */
-	lxt971_no_sleep();
-#endif
-}
-
-#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
-void ide_set_reset(int on)
-{
-	/*
-	 * Assert or deassert CompactFlash Reset Pin
-	 */
-	if (on) {	/* assert RESET */
-		out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
-			 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
-			 ~CONFIG_SYS_FPGA_MODE_CF_RESET);
-	} else {	/* release RESET */
-		out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
-			 in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
-			 CONFIG_SYS_FPGA_MODE_CF_RESET);
-	}
-}
-
-#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
-
-#if defined(CONFIG_PCI)
-void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
-	unsigned char int_line = 0xff;
-
-	/*
-	 * Write pci interrupt line register (cpci405 specific)
-	 */
-	switch (PCI_DEV(dev) & 0x03) {
-	case 0:
-		int_line = 27 + 2;
-		break;
-	case 1:
-		int_line = 27 + 3;
-		break;
-	case 2:
-		int_line = 27 + 0;
-		break;
-	case 3:
-		int_line = 27 + 1;
-		break;
-	}
-
-	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
-}
-
-int pci_pre_init(struct pci_controller *hose)
-{
-	hose->fixup_irq = cpci405_pci_fixup_irq;
-	return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	int rc;
-
-	__ft_board_setup(blob, bd);
-
-	/*
-	 * Disable PCI in adapter mode.
-	 */
-	if (!cpci405_host()) {
-		rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
-					  "disabled", sizeof("disabled"), 1);
-		if (rc) {
-			printf("Unable to update property status in PCI node, "
-			       "err=%s\n",
-			       fdt_strerror(rc));
-		}
-	}
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c
deleted file mode 100644
index 091652b..0000000
--- a/board/esd/cpci405/flash.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long calc_size(unsigned long size)
-{
-	switch (size) {
-	case 1 << 20:
-		return 0;
-	case 2 << 20:
-		return 1;
-	case 4 << 20:
-		return 2;
-	case 8 << 20:
-		return 3;
-	case 16 << 20:
-		return 4;
-	default:
-		return 0;
-	}
-}
-
-
-unsigned long flash_init (void)
-{
-	unsigned long size_b0, size_b1;
-	int i;
-	uint pbcr;
-	unsigned long base_b0, base_b1;
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	base_b0 = FLASH_BASE0_PRELIM;
-	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-				size_b0, size_b0 << 20);
-	}
-
-	base_b1 = FLASH_BASE1_PRELIM;
-	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
-
-	/* Re-do sizing to get full correct info */
-
-	if (size_b1) {
-		if (size_b1 < (1 << 20)) {
-			/* minimum CS size on PPC405GP is 1MB !!! */
-			size_b1 = 1 << 20;
-		}
-		base_b1 = -size_b1;
-		mtdcr (EBC0_CFGADDR, PB0CR);
-		pbcr = mfdcr (EBC0_CFGDATA);
-		mtdcr (EBC0_CFGADDR, PB0CR);
-		pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17);
-		mtdcr (EBC0_CFGDATA, pbcr);
-#if 0 /* test-only */
-		printf("size_b1=%x base_b1=%x PB1CR = %x\n",
-		       size_b1, base_b1, pbcr); /* test-only */
-#endif
-	}
-
-	if (size_b0) {
-		if (size_b0 < (1 << 20)) {
-			/* minimum CS size on PPC405GP is 1MB !!! */
-			size_b0 = 1 << 20;
-		}
-		base_b0 = base_b1 - size_b0;
-		mtdcr (EBC0_CFGADDR, PB1CR);
-		pbcr = mfdcr (EBC0_CFGDATA);
-		mtdcr (EBC0_CFGADDR, PB1CR);
-		pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17);
-		mtdcr (EBC0_CFGDATA, pbcr);
-#if 0 /* test-only */
-		printf("size_b0=%x base_b0=%x PB0CR = %x\n",
-		       size_b0, base_b0, pbcr); /* test-only */
-#endif
-	}
-
-	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
-
-	flash_get_offsets (base_b0, &flash_info[0]);
-
-	/* monitor protection ON by default */
-	flash_protect (FLAG_PROTECT_SET,
-			base_b0 + size_b0 - monitor_flash_len,
-			base_b0 + size_b0 - 1, &flash_info[0]);
-
-	if (size_b1) {
-		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
-
-		flash_get_offsets (base_b1, &flash_info[1]);
-
-		/* monitor protection ON by default */
-		flash_protect (FLAG_PROTECT_SET,
-				base_b1 + size_b1 - monitor_flash_len,
-				base_b1 + size_b1 - 1, &flash_info[1]);
-		/* monitor protection OFF by default (one is enough) */
-		flash_protect (FLAG_PROTECT_CLEAR,
-				base_b0 + size_b0 - monitor_flash_len,
-				base_b0 + size_b0 - 1, &flash_info[0]);
-	} else {
-		flash_info[1].flash_id = FLASH_UNKNOWN;
-		flash_info[1].sector_count = -1;
-	}
-
-	flash_info[0].size = size_b0;
-	flash_info[1].size = size_b1;
-
-	return (size_b0 + size_b1);
-}
diff --git a/board/esd/cpci405/fpgadata_cpci4052.c b/board/esd/cpci405/fpgadata_cpci4052.c
deleted file mode 100644
index bedbb1f..0000000
--- a/board/esd/cpci405/fpgadata_cpci4052.c
+++ /dev/null
@@ -1,1529 +0,0 @@
-0x1f, 0x8b, 0x08, 0x08, 0xe9, 0xf4, 0x75, 0x3e,
-0x00, 0x03, 0x63, 0x70, 0x63, 0x69, 0x34, 0x30,
-0x35, 0x5f, 0x32, 0x5f, 0x30, 0x34, 0x2e, 0x62,
-0x69, 0x74, 0x00, 0xed, 0x7c, 0x0f, 0x74, 0x14,
-0xd7, 0x79, 0xef, 0x37, 0x77, 0x66, 0xc5, 0x68,
-0x77, 0xa5, 0x1d, 0xad, 0x56, 0xce, 0xda, 0x16,
-0xf2, 0x68, 0x25, 0xc8, 0xa2, 0xae, 0xc4, 0xb2,
-0xc2, 0x58, 0x96, 0xc5, 0x6a, 0xb4, 0x92, 0xe9,
-0xda, 0xe0, 0xb0, 0x26, 0x6e, 0xc3, 0x6b, 0xfd,
-0x92, 0xc5, 0x26, 0xad, 0xfa, 0x0e, 0x71, 0x85,
-0xd3, 0xe6, 0xa9, 0x6e, 0x5f, 0xdf, 0xd5, 0x6a,
-0x31, 0x02, 0x61, 0x58, 0xff, 0x69, 0xa3, 0xb8,
-0x24, 0x59, 0x88, 0xda, 0x28, 0x2e, 0xc9, 0x5b,
-0x04, 0x01, 0x61, 0x1c, 0x7b, 0x50, 0x65, 0x2c,
-0x40, 0x06, 0x85, 0xfa, 0xbc, 0x87, 0x6d, 0x6a,
-0x2f, 0x8e, 0xea, 0xa7, 0x60, 0x99, 0xca, 0x40,
-0x1d, 0xf1, 0xcf, 0x7a, 0xdf, 0x9d, 0x7f, 0xbb,
-0x22, 0x89, 0xdb, 0xd3, 0xd7, 0x73, 0xfa, 0xce,
-0x79, 0x9e, 0xc4, 0xc7, 0xd7, 0xba, 0xba, 0x33,
-0xf7, 0x7e, 0xf3, 0xdd, 0xdf, 0xf7, 0xfb, 0x7d,
-0xdf, 0x1d, 0x41, 0xa1, 0x6b, 0x5a, 0xff, 0x1f,
-0x00, 0xb7, 0x0e, 0x4a, 0x1e, 0xed, 0x78, 0xf4,
-0x0f, 0x96, 0x06, 0xef, 0xfc, 0x4a, 0xe8, 0x2b,
-0xc1, 0xa5, 0x75, 0x8f, 0x3d, 0xba, 0x1e, 0x1e,
-0x01, 0x7b, 0xe8, 0xeb, 0x4b, 0xee, 0xfc, 0xa3,
-0x8d, 0x4b, 0x96, 0x2e, 0x85, 0x47, 0xc1, 0x11,
-0x0a, 0x06, 0xeb, 0x17, 0xe3, 0xff, 0x97, 0xdc,
-0x05, 0xeb, 0xa1, 0x70, 0xc9, 0x5d, 0x8d, 0x4b,
-0x96, 0x35, 0x2e, 0x0d, 0xc2, 0x57, 0x01, 0xe2,
-0x3d, 0xb3, 0x78, 0xbd, 0xf0, 0xad, 0xdf, 0xfa,
-0xbd, 0x20, 0x50, 0x0e, 0x00, 0xe6, 0x05, 0xb9,
-0x38, 0xfb, 0x77, 0x41, 0x90, 0x93, 0x39, 0xa0,
-0xcd, 0xb5, 0x41, 0x50, 0xd9, 0x7f, 0x83, 0xd1,
-0x5f, 0x18, 0x04, 0x39, 0xff, 0xbf, 0xb9, 0x20,
-0x28, 0x10, 0x03, 0xcf, 0xd7, 0xc0, 0x1d, 0x84,
-0x9b, 0x2e, 0x0e, 0x04, 0xaa, 0xb7, 0x3e, 0xad,
-0x8f, 0xdc, 0xdc, 0xc5, 0xae, 0x7f, 0x45, 0x9f,
-0xfb, 0x57, 0x74, 0x09, 0xff, 0xd6, 0x3e, 0xfd,
-0x5f, 0xb3, 0x6e, 0xf0, 0xe0, 0xcc, 0x38, 0x6d,
-0x45, 0x60, 0x63, 0x0d, 0xa9, 0x79, 0x44, 0x1f,
-0xa7, 0xda, 0x2e, 0xc1, 0x58, 0x72, 0x99, 0xbc,
-0x6a, 0x0b, 0xa9, 0x22, 0x63, 0xea, 0x37, 0x82,
-0xae, 0x3e, 0x3e, 0x08, 0x1d, 0xfa, 0x8c, 0xa4,
-0xf7, 0x68, 0xcf, 0x80, 0xcf, 0x27, 0x8a, 0xa4,
-0x1a, 0x7a, 0x40, 0xa6, 0x8e, 0xe7, 0x13, 0x69,
-0xd0, 0xd7, 0xdc, 0x63, 0x9b, 0xa4, 0xbb, 0x64,
-0x19, 0x44, 0x72, 0x9b, 0xd8, 0xd5, 0x93, 0x96,
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-0x19, 0x20, 0x3f, 0x00, 0xec, 0x03, 0xe2, 0xe4,
-0x7a, 0x38, 0x9f, 0xea, 0xa0, 0x24, 0x23, 0xc4,
-0xf5, 0xc9, 0x94, 0xa9, 0x70, 0x1e, 0x0e, 0xa8,
-0x81, 0xdd, 0xbc, 0x0c, 0xc3, 0x64, 0x19, 0xb8,
-0x32, 0xbc, 0x24, 0xe8, 0xe3, 0xb2, 0x5c, 0x1a,
-0xde, 0x81, 0x57, 0x54, 0x57, 0x96, 0xbf, 0x0c,
-0x7f, 0x0e, 0x77, 0x50, 0xd7, 0x34, 0x3f, 0x03,
-0xfa, 0x38, 0x45, 0x1a, 0x80, 0x13, 0x10, 0xca,
-0x16, 0x0d, 0xf0, 0x7e, 0xbc, 0x41, 0x48, 0x71,
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-0xf0, 0x1b, 0x31, 0x5f, 0x56, 0x1c, 0x20, 0x01,
-0x38, 0x2f, 0xf8, 0x54, 0x31, 0xcd, 0x3f, 0x8e,
-0xef, 0x4f, 0xbb, 0xa7, 0xad, 0x0d, 0x7a, 0x14,
-0x19, 0x0a, 0x25, 0x02, 0xb6, 0x5d, 0xd0, 0xce,
-0x89, 0x29, 0x32, 0x84, 0x76, 0x60, 0x97, 0xcc,
-0x2d, 0xa3, 0x7b, 0xd2, 0x95, 0xd5, 0xe2, 0xef,
-0x92, 0x5b, 0x1e, 0xfa, 0x21, 0xad, 0x4c, 0x8b,
-0x6b, 0xc9, 0x5a, 0x63, 0x5c, 0x34, 0xea, 0x4a,
-0x1d, 0x49, 0xef, 0x5e, 0x54, 0x74, 0x9b, 0xc3,
-0x4e, 0xcf, 0xa5, 0x83, 0x71, 0x67, 0x0f, 0x6f,
-0x9a, 0x58, 0x99, 0xbf, 0x47, 0xf9, 0x67, 0x29,
-0x0c, 0xae, 0xf1, 0xd6, 0xeb, 0xb0, 0x44, 0x6a,
-0x3e, 0xb6, 0x78, 0xb4, 0x7e, 0xbc, 0x40, 0x9f,
-0xe7, 0x80, 0x6d, 0x02, 0x8e, 0xc3, 0x8b, 0xaa,
-0x33, 0xc3, 0xfb, 0xe0, 0x44, 0x32, 0x24, 0x07,
-0x32, 0x55, 0x35, 0x86, 0x3d, 0xa3, 0x25, 0xcf,
-0x09, 0x4f, 0x42, 0xa5, 0x2a, 0x4e, 0x47, 0x96,
-0xc2, 0x66, 0xa8, 0xa2, 0xe2, 0x34, 0x71, 0x1b,
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-0xdb, 0xde, 0x59, 0xf0, 0xbc, 0x63, 0x33, 0xad,
-0x8c, 0x17, 0xb6, 0x93, 0x0e, 0xd0, 0xd7, 0x17,
-0xf5, 0x4c, 0x91, 0xc3, 0xd4, 0x77, 0x56, 0xbc,
-0xbb, 0xc0, 0x09, 0xdd, 0x20, 0xab, 0x85, 0x7e,
-0xfb, 0x1a, 0x41, 0x7f, 0x0f, 0x93, 0x65, 0x93,
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-0xbf, 0x70, 0x9c, 0x84, 0x68, 0xd1, 0x0b, 0xfc,
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-0x82, 0x0e, 0xe3, 0x79, 0x97, 0xe1, 0x86, 0x50,
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-0xff, 0x0c, 0x73, 0xe8, 0x2f, 0x8a, 0x18, 0x73,
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-0x36, 0x09, 0xa7, 0xa0, 0x59, 0x15, 0x66, 0xf8,
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-0x2e, 0x95, 0x7e, 0xa2, 0x5c, 0xa3, 0xf5, 0xd9,
-0x3b, 0x66, 0xf8, 0x69, 0x0b, 0x3f, 0x6f, 0x24,
-0x0f, 0x27, 0xea, 0xb2, 0x2b, 0xbf, 0x4e, 0xc6,
-0xe8, 0xe1, 0x17, 0x7c, 0x59, 0xc7, 0x10, 0xc9,
-0x0a, 0x26, 0x7e, 0x8e, 0x29, 0xfb, 0xd0, 0x54,
-0x8e, 0x20, 0xf6, 0xed, 0x13, 0xd2, 0xac, 0xf1,
-0x9e, 0x89, 0x9f, 0x65, 0x7b, 0xe0, 0x30, 0x4e,
-0x7d, 0x65, 0x86, 0x4c, 0xc1, 0x3e, 0xc4, 0x4f,
-0x6c, 0x4c, 0x1b, 0xef, 0x41, 0x29, 0x9b, 0x92,
-0xd0, 0x54, 0xea, 0xea, 0x0c, 0x37, 0x05, 0xd7,
-0x20, 0x84, 0x7d, 0xad, 0xe3, 0x16, 0x7e, 0xbe,
-0x04, 0xaf, 0xa0, 0xa9, 0x5c, 0xd3, 0x55, 0xd7,
-0x61, 0x56, 0x6b, 0xe4, 0xe1, 0xe7, 0x1e, 0xee,
-0x03, 0x1c, 0xe7, 0xcc, 0x94, 0x4e, 0x91, 0x13,
-0xd8, 0xa8, 0xcb, 0xf0, 0xe3, 0x46, 0x7c, 0x18,
-0xb5, 0x35, 0x31, 0x53, 0x4d, 0xd8, 0xa7, 0x49,
-0x40, 0xc4, 0xc6, 0x2f, 0x8a, 0x32, 0xe4, 0xa2,
-0x85, 0x9f, 0xab, 0xe0, 0x7b, 0x10, 0xc8, 0x16,
-0x06, 0xc9, 0x2a, 0x78, 0x56, 0x0e, 0xa8, 0xde,
-0x20, 0x99, 0xb1, 0xfc, 0xb3, 0xa2, 0x67, 0x73,
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-0x4c, 0xd5, 0x66, 0xb9, 0x4e, 0x32, 0x6a, 0xe2,
-0xa7, 0x58, 0x07, 0xdf, 0xa3, 0x4d, 0xef, 0x15,
-0x35, 0x96, 0x7e, 0x61, 0xfc, 0xef, 0xd3, 0x4d,
-0x53, 0xce, 0x7b, 0xf8, 0xd3, 0x86, 0x7f, 0x2a,
-0xf3, 0x7f, 0x08, 0xd7, 0xa4, 0x26, 0xf5, 0x64,
-0x86, 0xdf, 0x00, 0x1f, 0x40, 0x93, 0x8a, 0x31,
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-0xfa, 0xc0, 0x8b, 0x2b, 0x03, 0xda, 0xfa, 0xb0,
-0xef, 0xbc, 0x85, 0x9f, 0x4f, 0x51, 0x74, 0x3d,
-0x55, 0xbc, 0x9c, 0x28, 0x87, 0x83, 0xb0, 0x48,
-0x75, 0x74, 0x90, 0xd3, 0x39, 0xfc, 0xa4, 0x9b,
-0xe9, 0xe2, 0x6c, 0xe1, 0x13, 0x91, 0x0a, 0x38,
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-0x9f, 0xdd, 0x74, 0x7d, 0xe6, 0xf3, 0xbf, 0xae,
-0xef, 0xd7, 0x5f, 0xec, 0x6f, 0x39, 0x12, 0xed,
-0xdf, 0x2d, 0xaf, 0xfd, 0x6b, 0xc7, 0x7c, 0x76,
-0x7d, 0x76, 0x7d, 0x76, 0x7d, 0x76, 0x7d, 0x76,
-0x7d, 0x76, 0xfd, 0xff, 0x72, 0x69, 0x71, 0x92,
-0x68, 0x71, 0x52, 0xfd, 0x8f, 0x9e, 0xcb, 0x67,
-0xd7, 0x67, 0xd7, 0x67, 0xd7, 0x67, 0xd7, 0x67,
-0xd7, 0x67, 0xd7, 0x7f, 0xc4, 0x15, 0x64, 0x65,
-0x00, 0xd8, 0xfb, 0xb2, 0xf1, 0xf7, 0xff, 0xf9,
-0x20, 0x28, 0xf3, 0x3e, 0xfd, 0xf7, 0xb5, 0xdf,
-0xb3, 0x05, 0x21, 0xcd, 0xe5, 0xc6, 0xf7, 0xa7,
-0x6e, 0x9e, 0xeb, 0xff, 0x01, 0x51, 0x16, 0x5f,
-0xd0, 0xd5, 0x60, 0x00, 0x00,
diff --git a/board/esd/mecp5123/Kconfig b/board/esd/mecp5123/Kconfig
deleted file mode 100644
index 3f2a411..0000000
--- a/board/esd/mecp5123/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MECP5123
-
-config SYS_BOARD
-	default "mecp5123"
-
-config SYS_VENDOR
-	default "esd"
-
-config SYS_CONFIG_NAME
-	default "mecp5123"
-
-endif
diff --git a/board/esd/mecp5123/MAINTAINERS b/board/esd/mecp5123/MAINTAINERS
deleted file mode 100644
index ae5fcea..0000000
--- a/board/esd/mecp5123/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MECP5123 BOARD
-M:	Reinhard Arlt <reinhard.arlt@esd-electronics.com>
-S:	Maintained
-F:	board/esd/mecp5123/
-F:	include/configs/mecp5123.h
-F:	configs/mecp5123_defconfig
diff --git a/board/esd/mecp5123/Makefile b/board/esd/mecp5123/Makefile
deleted file mode 100644
index f5ebb01..0000000
--- a/board/esd/mecp5123/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mecp5123.o
diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c
deleted file mode 100644
index 656f0fa..0000000
--- a/board/esd/mecp5123/mecp5123.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
- * (C) Copyright 2009 Dave Srl www.dave.eu
- * (C) Copyright 2009 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mpc512x.h>
-#include <fdt_support.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int eeprom_write_enable(unsigned dev_addr, int state)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	if (dev_addr != CONFIG_SYS_I2C_EEPROM_ADDR)
-		return -1;
-
-	if (state == 0)
-		setbits_be32(&im->gpio.gpdat, 0x00100000);
-	else
-		clrbits_be32(&im->gpio.gpdat, 0x00100000);
-
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	int i;
-
-	/*
-	 * Initialize Local Window for boot access
-	 */
-	out_be32(&im->sysconf.lpbaw,
-		 CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
-	sync_law(&im->sysconf.lpbaw);
-
-	/*
-	 * Configure MSCAN clocks
-	 */
-	for (i=0; i<4; ++i) {
-		out_be32(&im->clk.msccr[i], 0x00300000);
-		out_be32(&im->clk.msccr[i], 0x00310000);
-	}
-
-	/*
-	 * Configure GPIO's
-	 */
-	clrbits_be32(&im->gpio.gpodr, 0x000000e0);
-	clrbits_be32(&im->gpio.gpdir, 0x00ef0000);
-	setbits_be32(&im->gpio.gpdir, 0x001000e0);
-	setbits_be32(&im->gpio.gpdat, 0x00100000);
-
-	return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
-	return get_ram_size(0, fixed_sdram(NULL, NULL, 0));
-}
-
-int misc_init_r(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 val;
-
-	/*
-	 * Optimize access to profibus chip (VPC3) on the local bus
-	 */
-
-	/*
-	 * Select 1:1 for LPC_DIV
-	 */
-	val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK;
-	out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT));
-
-	/*
-	 * Configure LPC Chips Select Deadcycle Control Register
-	 * CS0 - device can drive data 2 clock cycle(s) after CS deassertion
-	 * CS1 - device can drive data 1 clock cycle(s) after CS deassertion
-	 */
-	clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
-	setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
-
-	/*
-	 * Configure LPC Chips Select Holdcycle Control Register
-	 * CS0 - data is valid 2 clock cycle(s) after CS deassertion
-	 * CS1 - data is valid 1 clock cycle(s) after CS deassertion
-	 */
-	clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
-	setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
-
-	return 0;
-}
-
-static iopin_t ioregs_init[] = {
-	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
-	{
-		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
-	{
-		offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=SELECT LPC_CS1 */
-	{
-		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC5_2 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC5_3 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC7_3 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC9_0 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC10_0 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC10_3 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=SELECT PSC11_0 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC0=SELECT IRQ0 */
-	{
-		offsetof(struct ioctrl512x, io_control_irq0), 4, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	}
-};
-
-static iopin_t rev2_silicon_pci_ioregs_init[] = {
-	/* FUNC0=PCI Sets next 54 to PCI pads */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
-	}
-};
-
-int checkboard(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 spridr;
-
-	puts("Board: MECP_5123\n");
-
-	/*
-	 * Initialize function mux & slew rate IO inter alia on IO
-	 * Pins
-	 */
-	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
-
-	spridr = in_be32(&im->sysconf.spridr);
-	if (SVR_MJREV(spridr) >= 2)
-		iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c
index fe781dc..93a02ab 100644
--- a/board/esd/meesc/meesc.c
+++ b/board/esd/meesc/meesc.c
@@ -13,6 +13,8 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/setup.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
@@ -132,10 +134,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
 }
 
 int board_eth_init(bd_t *bis)
@@ -243,13 +247,8 @@ int misc_init_r(void)
 
 int board_early_init_f(void)
 {
-	at91_periph_clk_enable(ATMEL_ID_PIOA);
-	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
 	at91_periph_clk_enable(ATMEL_ID_UHP);
 
-	at91_seriald_hw_init();
-
 	return 0;
 }
 
@@ -264,9 +263,6 @@ int board_init(void)
 #ifdef CONFIG_CMD_NAND
 	meesc_nand_hw_init();
 #endif
-#ifdef CONFIG_HAS_DATAFLASH
-	at91_spi0_hw_init(1 << 0);
-#endif
 #ifdef CONFIG_MACB
 	meesc_macb_hw_init();
 #endif
diff --git a/board/esd/plu405/Kconfig b/board/esd/plu405/Kconfig
deleted file mode 100644
index b3082cb..0000000
--- a/board/esd/plu405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_PLU405
-
-config SYS_BOARD
-	default "plu405"
-
-config SYS_VENDOR
-	default "esd"
-
-config SYS_CONFIG_NAME
-	default "PLU405"
-
-endif
diff --git a/board/esd/plu405/MAINTAINERS b/board/esd/plu405/MAINTAINERS
deleted file mode 100644
index ccb3658..0000000
--- a/board/esd/plu405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PLU405 BOARD
-M:	Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S:	Maintained
-F:	board/esd/plu405/
-F:	include/configs/PLU405.h
-F:	configs/PLU405_defconfig
diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile
deleted file mode 100644
index 6ffae67..0000000
--- a/board/esd/plu405/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= plu405.o flash.o \
-	../common/misc.o \
-	../common/esd405ep_nand.o \
diff --git a/board/esd/plu405/flash.c b/board/esd/plu405/flash.c
deleted file mode 100644
index 23e8164..0000000
--- a/board/esd/plu405/flash.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	unsigned long size_b0;
-	int i;
-	uint pbcr;
-	unsigned long base_b0;
-	int size_val = 0;
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
-	}
-
-	/* Setup offsets */
-	flash_get_offsets (-size_b0, &flash_info[0]);
-
-	/* Re-do sizing to get full correct info */
-	mtdcr(EBC0_CFGADDR, PB0CR);
-	pbcr = mfdcr(EBC0_CFGDATA);
-	mtdcr(EBC0_CFGADDR, PB0CR);
-	base_b0 = -size_b0;
-	switch (size_b0) {
-	case 1 << 20:
-		size_val = 0;
-		break;
-	case 2 << 20:
-		size_val = 1;
-		break;
-	case 4 << 20:
-		size_val = 2;
-		break;
-	case 8 << 20:
-		size_val = 3;
-		break;
-	case 16 << 20:
-		size_val = 4;
-		break;
-	}
-	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
-	mtdcr(EBC0_CFGDATA, pbcr);
-
-	/* Monitor protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CONFIG_SYS_MONITOR_LEN,
-			    0xffffffff,
-			    &flash_info[0]);
-
-	flash_info[0].size = size_b0;
-
-	return (size_b0);
-}
diff --git a/board/esd/plu405/fpgadata.c b/board/esd/plu405/fpgadata.c
deleted file mode 100644
index 485b9a2..0000000
--- a/board/esd/plu405/fpgadata.c
+++ /dev/null
@@ -1,2358 +0,0 @@
-0x1f, 0x8b, 0x08, 0x08, 0x04, 0x44, 0x9f, 0x46,
-0x00, 0x03, 0x70, 0x6c, 0x75, 0x34, 0x30, 0x35,
-0x5f, 0x31, 0x5f, 0x31, 0x2e, 0x62, 0x69, 0x74,
-0x00, 0x94, 0x9a, 0x0f, 0x70, 0x14, 0x55, 0x9e,
-0xc7, 0x7f, 0xfd, 0xba, 0x93, 0x74, 0xa6, 0x3b,
-0xe9, 0x36, 0x7f, 0x30, 0xb7, 0x08, 0xd7, 0x19,
-0x07, 0x76, 0xc4, 0x61, 0x18, 0x42, 0x80, 0x98,
-0x0d, 0x49, 0x33, 0xa4, 0xac, 0x71, 0xc9, 0x1e,
-0xf1, 0xce, 0xbb, 0xe2, 0xf6, 0xbc, 0xdd, 0x11,
-0x71, 0x8f, 0xbb, 0xe2, 0x2c, 0xd6, 0xdd, 0xb3,
-0xb8, 0x3b, 0x4b, 0x5f, 0x66, 0xa2, 0x04, 0x92,
-0x92, 0x01, 0x39, 0x37, 0xba, 0xac, 0x35, 0x40,
-0x6e, 0x8d, 0x4a, 0x59, 0x11, 0x75, 0x8d, 0x82,
-0xbb, 0x4d, 0x0c, 0x3a, 0x60, 0xd4, 0xb9, 0x94,
-0x7b, 0x8b, 0x7f, 0x8e, 0x6d, 0xd8, 0xc0, 0x46,
-0x89, 0x3a, 0xcb, 0xa2, 0x06, 0x65, 0xcd, 0xbd,
-0xd7, 0x3d, 0xdd, 0xd3, 0x99, 0x9e, 0x04, 0x37,
-0x5a, 0xc5, 0x2f, 0xaf, 0x1f, 0x8f, 0xf7, 0xfb,
-0xcd, 0xef, 0xfd, 0x7e, 0x9f, 0xfe, 0xbe, 0x81,
-0x52, 0x29, 0x63, 0xfe, 0x07, 0xc0, 0xdc, 0x06,
-0xd2, 0x96, 0xcd, 0xff, 0x56, 0x1f, 0x5a, 0xfe,
-0xfd, 0xa5, 0xdf, 0x5f, 0x1a, 0xbc, 0xf3, 0xf6,
-0x8d, 0xb0, 0x01, 0x84, 0xba, 0x1f, 0x2d, 0x0f,
-0xdd, 0xf1, 0xe3, 0x1f, 0x2e, 0xad, 0xaf, 0x87,
-0xdb, 0xc9, 0x6f, 0xa1, 0xd0, 0xca, 0x25, 0xe4,
-0xff, 0xa5, 0x37, 0xc0, 0x46, 0x28, 0x5d, 0x5a,
-0xd7, 0xb8, 0xfc, 0x86, 0xc6, 0xa5, 0x2b, 0xe1,
-0x0e, 0x60, 0x96, 0xf5, 0x4d, 0x91, 0x9f, 0x27,
-0x1f, 0xf9, 0xdb, 0x1f, 0x84, 0x00, 0x33, 0x00,
-0x50, 0x12, 0x62, 0xa2, 0xf4, 0x4f, 0x21, 0xc4,
-0x28, 0x0c, 0xe0, 0x96, 0xc5, 0x21, 0xd0, 0xe8,
-0xef, 0x90, 0x7d, 0x5e, 0x1a, 0x02, 0xc5, 0xf9,
-0x3b, 0x13, 0x02, 0x15, 0xda, 0x41, 0xed, 0x81,
-0x0a, 0x19, 0xae, 0xf8, 0xc3, 0xa8, 0x1c, 0xb6,
-0xec, 0x3f, 0x73, 0xfe, 0xd4, 0x09, 0x3c, 0xe3,
-0xb4, 0xdc, 0x4f, 0xcb, 0x85, 0xa4, 0x65, 0xa2,
-0xd0, 0xd7, 0x59, 0x1f, 0xec, 0xf5, 0xdf, 0xfd,
-0x5a, 0xeb, 0x7f, 0x66, 0xad, 0xff, 0xe7, 0xce,
-0x87, 0x8a, 0xaf, 0x31, 0x1d, 0x80, 0xb3, 0xf7,
-0x63, 0x86, 0x87, 0x03, 0x06, 0x43, 0x14, 0x64,
-0x28, 0xa6, 0x86, 0x42, 0x46, 0x10, 0x80, 0x69,
-0x18, 0xeb, 0x0f, 0x5b, 0xf3, 0x87, 0x8a, 0xbe,
-0x82, 0x29, 0xdc, 0xa2, 0x8a, 0x1a, 0x5b, 0x8f,
-0x76, 0xe2, 0x16, 0x5d, 0x4a, 0xb1, 0x75, 0xf0,
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-0x41, 0x39, 0x32, 0x28, 0xe5, 0x63, 0xf8, 0xad,
-0x0e, 0x6b, 0xd6, 0x78, 0x01, 0x9a, 0xe1, 0x57,
-0xa9, 0xb1, 0x11, 0x5d, 0xe4, 0x23, 0xc6, 0xf9,
-0x70, 0xdc, 0x14, 0xf5, 0x10, 0x8b, 0xb7, 0x1e,
-0x1f, 0x4f, 0xb3, 0x74, 0x7c, 0x27, 0x1f, 0x85,
-0x1b, 0xd9, 0x80, 0x2e, 0xa2, 0x7f, 0x6a, 0x02,
-0x34, 0xb8, 0x5f, 0x64, 0xe6, 0xd2, 0xc8, 0x42,
-0x9e, 0x4f, 0x4f, 0x11, 0x0d, 0xce, 0x26, 0x9f,
-0x85, 0xa2, 0x06, 0xab, 0x86, 0x0f, 0x05, 0x45,
-0xca, 0xa6, 0x28, 0x9f, 0x1e, 0x7d, 0xa5, 0x44,
-0x67, 0xf3, 0x86, 0xc6, 0x7a, 0x41, 0x3e, 0x14,
-0xf4, 0x95, 0x3b, 0x6b, 0xb4, 0x31, 0xe0, 0xe4,
-0x73, 0x09, 0x69, 0x50, 0x27, 0xad, 0x18, 0x2e,
-0x21, 0x28, 0xbe, 0x30, 0x58, 0x98, 0xf3, 0x61,
-0x66, 0x54, 0x71, 0x7f, 0x17, 0x4b, 0x72, 0xb5,
-0x3f, 0x9b, 0x9c, 0x09, 0x83, 0xd1, 0x7f, 0x1b,
-0xe7, 0xfa, 0x23, 0x76, 0xae, 0xea, 0x47, 0xc9,
-0x61, 0x4b, 0x83, 0x64, 0x76, 0x8d, 0xf0, 0x44,
-0x66, 0x8d, 0xa9, 0xa4, 0x91, 0x62, 0x7d, 0x8c,
-0x7c, 0xd8, 0x36, 0x58, 0x28, 0x46, 0xa9, 0x99,
-0x19, 0x89, 0xd5, 0xfe, 0x6d, 0x34, 0x17, 0x33,
-0x62, 0x9c, 0xd9, 0x74, 0xea, 0x67, 0x1a, 0xc7,
-0x4c, 0xe4, 0x43, 0x25, 0xd7, 0x45, 0xa2, 0x97,
-0xed, 0x58, 0x3a, 0x87, 0xdb, 0x34, 0xdd, 0xc3,
-0x08, 0xf5, 0x1f, 0xdf, 0xed, 0x3f, 0x0a, 0xcb,
-0xf5, 0x8a, 0x0e, 0x93, 0xda, 0x03, 0xf8, 0x01,
-0xcd, 0xde, 0xa4, 0x16, 0x0a, 0xe4, 0x43, 0xed,
-0x65, 0x26, 0x24, 0x53, 0xac, 0x87, 0x6e, 0x22,
-0xaf, 0xb7, 0xa6, 0xbc, 0xc5, 0x35, 0xd8, 0x90,
-0xc7, 0xc5, 0x3e, 0x1c, 0xd5, 0x82, 0x2d, 0x79,
-0x1d, 0xcd, 0x19, 0xc7, 0x38, 0xf5, 0x2c, 0xbe,
-0x40, 0x1a, 0xf4, 0xa2, 0x0a, 0xce, 0x0b, 0x58,
-0x2d, 0x7b, 0xb0, 0x5a, 0xb0, 0xed, 0x5c, 0x25,
-0x2c, 0xec, 0x89, 0x3b, 0x19, 0x28, 0x3a, 0xf9,
-0x60, 0xfd, 0x34, 0x4d, 0x91, 0xc0, 0x2d, 0xa2,
-0xc1, 0x8d, 0xa5, 0x12, 0x1f, 0xa6, 0xc6, 0xad,
-0x9f, 0x05, 0xa9, 0x86, 0x8d, 0x66, 0xd7, 0xf3,
-0x2b, 0x32, 0xee, 0xfb, 0x68, 0x82, 0x8a, 0x54,
-0xda, 0x6f, 0x76, 0x8c, 0xe9, 0x1b, 0x03, 0xce,
-0xf5, 0xc1, 0xf7, 0xcb, 0xa0, 0x11, 0x4d, 0x78,
-0xf0, 0x4b, 0x13, 0x06, 0x8d, 0x1f, 0x45, 0x5d,
-0x2c, 0x42, 0xac, 0x31, 0x82, 0xa6, 0x19, 0x0f,
-0x8c, 0x51, 0xce, 0xf5, 0xf1, 0xa8, 0xff, 0x10,
-0x1f, 0x82, 0xc2, 0x69, 0x14, 0x70, 0x3e, 0xf5,
-0xe4, 0x82, 0xb0, 0xa0, 0xa8, 0xc6, 0xf8, 0x10,
-0xf3, 0xd9, 0x3f, 0x4d, 0x7c, 0x88, 0xcd, 0x60,
-0x3f, 0x32, 0xd9, 0x7c, 0x0b, 0xf9, 0x10, 0x52,
-0x3e, 0xcc, 0x41, 0xd1, 0xc9, 0x47, 0xec, 0xe8,
-0x3f, 0xa5, 0xb6, 0x93, 0x1b, 0xe7, 0xfa, 0xa8,
-0xca, 0x55, 0x78, 0x08, 0x35, 0xfa, 0xe2, 0x40,
-0x32, 0xf1, 0x30, 0x6b, 0x3b, 0x1e, 0x99, 0xf5,
-0xbc, 0x23, 0x39, 0xf9, 0x24, 0xb8, 0x4d, 0x53,
-0xb8, 0x4d, 0x9a, 0xf6, 0x0b, 0x37, 0x4e, 0xfb,
-0x5b, 0x70, 0x5c, 0xdc, 0xc2, 0x48, 0xbc, 0x95,
-0xfe, 0xcb, 0xe9, 0x3f, 0x31, 0x9e, 0xe0, 0x09,
-0x35, 0xf5, 0x4d, 0xf5, 0x91, 0x7e, 0xba, 0x11,
-0xa9, 0xba, 0x5f, 0x95, 0x30, 0x84, 0x48, 0x79,
-0x64, 0x7e, 0x82, 0x34, 0xe2, 0xd4, 0x33, 0xbe,
-0x53, 0x8f, 0xa9, 0xc9, 0xb8, 0x1a, 0xcb, 0xfb,
-0xd0, 0x3e, 0x3d, 0xa9, 0xaa, 0x0d, 0x5c, 0xd6,
-0x06, 0x2f, 0x46, 0xf3, 0x02, 0xda, 0xaa, 0x4e,
-0x66, 0xd3, 0xc9, 0x67, 0x51, 0x5e, 0x19, 0x86,
-0xd1, 0x52, 0x08, 0xdf, 0xcb, 0x64, 0x80, 0xa6,
-0x1e, 0xa0, 0x19, 0x1a, 0x73, 0x37, 0x33, 0x6e,
-0xff, 0x51, 0xc4, 0x87, 0x83, 0x0a, 0x3d, 0xa7,
-0xdc, 0xf9, 0xd4, 0xd0, 0x89, 0x14, 0xd7, 0xa7,
-0xd7, 0x49, 0xf6, 0x84, 0xb5, 0x25, 0xa1, 0x75,
-0xe7, 0x6b, 0x1f, 0x41, 0xb1, 0x15, 0xdc, 0xcc,
-0xb0, 0xf0, 0x81, 0x1c, 0xe3, 0x43, 0xec, 0x3f,
-0x9d, 0x8b, 0xc1, 0x8c, 0xec, 0x9e, 0xf6, 0xfd,
-0x4e, 0xec, 0x37, 0x64, 0x57, 0x04, 0xca, 0x1a,
-0x08, 0x3a, 0x32, 0x0e, 0x6c, 0xc4, 0xa9, 0x1f,
-0x2a, 0xc0, 0xfc, 0xb9, 0x83, 0xbf, 0x36, 0x81,
-0x25, 0x09, 0xb6, 0x36, 0x45, 0x6e, 0x8a, 0x7a,
-0x00, 0x69, 0xb1, 0x50, 0x95, 0xf9, 0xb0, 0x9f,
-0x19, 0x1b, 0x71, 0xeb, 0x67, 0xa5, 0x7a, 0x41,
-0xdd, 0x7b, 0xde, 0x3a, 0xaa, 0x57, 0x2a, 0x55,
-0xf5, 0xdb, 0xf3, 0x83, 0x47, 0x27, 0x57, 0xc4,
-0x05, 0x34, 0xc7, 0xd0, 0x54, 0x53, 0xe3, 0xe4,
-0x23, 0x90, 0x07, 0x90, 0x0f, 0xf1, 0xa6, 0xff,
-0xf3, 0x1c, 0xdd, 0xfd, 0x2f, 0x37, 0x0b, 0x0c,
-0x78, 0x2b, 0x0f, 0x1c, 0xc9, 0xf8, 0x70, 0xf7,
-0xd9, 0xb3, 0xc4, 0x87, 0xcf, 0xae, 0x1d, 0x31,
-0x7c, 0xf8, 0xc4, 0xf0, 0xe1, 0xef, 0x64, 0x96,
-0x9d, 0xe5, 0x70, 0x2a, 0xe3, 0xc3, 0x93, 0x37,
-0xce, 0x13, 0x1f, 0x6e, 0xbf, 0x3e, 0x65, 0xc0,
-0xec, 0x95, 0xe5, 0xc3, 0x5f, 0xb7, 0x5f, 0x6d,
-0x97, 0x78, 0xec, 0x7d, 0x65, 0xb0, 0xf0, 0xe5,
-0x3a, 0x1e, 0xf6, 0xdf, 0x14, 0x14, 0xe7, 0x1e,
-0x2f, 0x93, 0x31, 0x7c, 0x68, 0x22, 0xdf, 0xba,
-0xeb, 0x0d, 0x16, 0xfe, 0xf3, 0x37, 0xa5, 0x91,
-0x81, 0xe2, 0x0d, 0x63, 0x2c, 0x1f, 0x52, 0xa4,
-0xc4, 0xab, 0x27, 0x33, 0x3e, 0x3c, 0xb0, 0xef,
-0xdc, 0x9f, 0x77, 0xda, 0xb4, 0xfe, 0xbb, 0x73,
-0xa3, 0xcf, 0xe9, 0x85, 0x39, 0x6a, 0x7e, 0x78,
-0xf6, 0x11, 0x8e, 0x58, 0xf8, 0xb6, 0xc6, 0xbf,
-0x8b, 0xf5, 0x0f, 0x3f, 0x0a, 0x8b, 0xc5, 0x62,
-0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0xfa, 0xd4,
-0x65, 0x66, 0x07, 0xc9, 0xb3, 0x03, 0x8b, 0xc5,
-0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x7a,
-0xb7, 0xcc, 0xec, 0x50, 0xe3, 0xd9, 0x81, 0xc5,
-0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62,
-0xbd, 0x5b, 0x66, 0x76, 0xf0, 0xcc, 0xec, 0xf0,
-0xb1, 0x53, 0x61, 0xb1, 0x58, 0x2c, 0x16, 0x8b,
-0xc5, 0x62, 0xb1, 0x58, 0xff, 0xa3, 0x22, 0xfa,
-0x7d, 0x1c, 0x3c, 0xfb, 0x23, 0x02, 0x4d, 0xbf,
-0x5a, 0xa9, 0x46, 0xa0, 0xde, 0xfb, 0xf3, 0x84,
-0xf4, 0xb5, 0x13, 0x11, 0x6c, 0x88, 0xe2, 0x98,
-0x7f, 0x7d, 0xb9, 0x73, 0xdd, 0x1b, 0x3b, 0x1c,
-0x29, 0xc2, 0xf0, 0x33, 0x01, 0x00,
diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c
deleted file mode 100644
index 03bf9c8..0000000
--- a/board/esd/plu405/plu405.c
+++ /dev/null
@@ -1,345 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-#include <sja1000.h>
-
-#undef FPGA_DEBUG
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void lxt971_no_sleep(void);
-
-/* fpga configuration data - gzip compressed and generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-/*
- * generate a short spike on the CAN tx line
- * to bring the couplers in sync
- */
-void init_coupler(u32 addr)
-{
-	struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
-
-	/* reset */
-	out_8(&ctrl->cr, CR_RR);
-
-	/* dominant */
-	out_8(&ctrl->btr0, 0x00); /* btr setup is required */
-	out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
-	out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
-	      OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
-	out_8(&ctrl->cr, 0x00);
-
-	/* delay */
-	in_8(&ctrl->cr);
-	in_8(&ctrl->cr);
-	in_8(&ctrl->cr);
-	in_8(&ctrl->cr);
-
-	/* reset */
-	out_8(&ctrl->cr, CR_RR);
-}
-
-int board_early_init_f(void)
-{
-	/*
-	 * IRQ 0-15  405GP internally generated; active high; level sensitive
-	 * IRQ 16    405GP internally generated; active low; level sensitive
-	 * IRQ 17-24 RESERVED
-	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
-	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
-	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
-	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
-	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
-	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
-	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
-	 */
-	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
-	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(UIC0PR, 0xFFFFFF99);       /* set int polarities */
-	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
-	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest prio */
-	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
-
-	/*
-	 * EBC Configuration Register: set ready timeout to
-	 * 512 ebc-clks -> ca. 15 us
-	 */
-	mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	unsigned char *dst;
-	unsigned char fctr;
-	ulong len = sizeof(fpgadata);
-	int status;
-	int index;
-	int i;
-
-	/* adjust flash start and offset */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-	gd->bd->bi_flashoffset = 0;
-
-	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
-	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
-		   (uchar *)fpgadata, &len) != 0) {
-		printf("GUNZIP ERROR - must RESET board to recover\n");
-		do_reset(NULL, 0, 0, NULL);
-	}
-
-	status = fpga_boot(dst, len);
-	if (status != 0) {
-		printf("\nFPGA: Booting failed ");
-		switch (status) {
-		case ERROR_FPGA_PRG_INIT_LOW:
-			printf("(Timeout: INIT not low "
-			       "after asserting PROGRAM*)\n");
-			break;
-		case ERROR_FPGA_PRG_INIT_HIGH:
-			printf("(Timeout: INIT not high "
-			       "after deasserting PROGRAM*)\n");
-			break;
-		case ERROR_FPGA_PRG_DONE:
-			printf("(Timeout: DONE not high "
-			       "after programming FPGA)\n");
-			break;
-		}
-
-		/* display infos on fpgaimage */
-		index = 15;
-		for (i=0; i<4; i++) {
-			len = dst[index];
-			printf("FPGA: %s\n", &(dst[index+1]));
-			index += len+3;
-		}
-		putc ('\n');
-		/* delayed reboot */
-		for (i=20; i>0; i--) {
-			printf("Rebooting in %2d seconds \r",i);
-			for (index=0;index<1000;index++)
-				udelay(1000);
-		}
-		putc('\n');
-		do_reset(NULL, 0, 0, NULL);
-	}
-
-	puts("FPGA:  ");
-
-	/* display infos on fpgaimage */
-	index = 15;
-	for (i=0; i<4; i++) {
-		len = dst[index];
-		printf("%s ", &(dst[index+1]));
-		index += len+3;
-	}
-	putc('\n');
-
-	free(dst);
-
-	/*
-	 * Reset FPGA via FPGA_DATA pin
-	 */
-	SET_FPGA(FPGA_PRG | FPGA_CLK);
-	udelay(1000); /* wait 1ms */
-	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
-	udelay(1000); /* wait 1ms */
-
-	/*
-	 * Reset external DUARTs
-	 */
-	out_be32((void*)GPIO0_OR,
-		 in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
-	udelay(10);
-	out_be32((void*)GPIO0_OR,
-		 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
-	udelay(1000);
-
-	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out_be32((void*)GPIO0_OR,
-		 in_be32((void*)GPIO0_OR) &
-		 ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
-	out_be32((void*)GPIO0_OR,
-		 in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
-
-	/*
-	 * Setup EEPROM write protection
-	 */
-	out_be32((void*)GPIO0_OR,
-		 in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
-	out_be32((void*)GPIO0_TCR,
-		 in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
-
-	/*
-	 * Enable interrupts in exar duart mcr[3]
-	 */
-	out_8((void *)DUART0_BA + 4, 0x08);
-	out_8((void *)DUART1_BA + 4, 0x08);
-
-	/*
-	 * Enable auto RS485 mode in 2nd external uart
-	 */
-	out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
-	fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
-	fctr |= 0x08;                       /* enable RS485 mode */
-	out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
-	out_8((void *)DUART1_BA + 3, 0);    /* write LCR */
-
-	/*
-	 * Init magnetic couplers
-	 */
-	if (!getenv("noinitcoupler")) {
-		init_coupler(CAN0_BA);
-		init_coupler(CAN1_BA);
-	}
-	return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
-	char str[64];
-	int i = getenv_f("serial#", str, sizeof(str));
-
-	puts("Board: ");
-
-	if (i == -1)
-		puts("### No HW ID - assuming PLU405");
-	else
-		puts(str);
-
-	putc('\n');
-	return 0;
-}
-
-#ifdef CONFIG_IDE_RESET
-#define FPGA_CTRL (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
-void ide_set_reset(int on)
-{
-	/*
-	 * Assert or deassert CompactFlash Reset Pin
-	 */
-	if (on) {		/* assert RESET */
-		out_be16((void *)FPGA_CTRL,
-			 in_be16((void *)FPGA_CTRL) &
-			 ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
-	} else {		/* release RESET */
-		out_be16((void *)FPGA_CTRL,
-			 in_be16((void *)FPGA_CTRL) |
-			 CONFIG_SYS_FPGA_CTRL_CF_RESET);
-	}
-}
-#endif /* CONFIG_IDE_RESET */
-
-void reset_phy(void)
-{
-#ifdef CONFIG_LXT971_NO_SLEEP
-
-	/*
-	 * Disable sleep mode in LXT971
-	 */
-	lxt971_no_sleep();
-#endif
-}
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-/* Input: <dev_addr>  I2C address of EEPROM device to enable.
- *	       <state> -1: deliver current state
- *			0: disable write
- *			1: enable write
- *  Returns:	       -1: wrong device address
- *			0: dis-/en- able done
- *		      0/1: current state if <state> was -1.
- */
-int eeprom_write_enable(unsigned dev_addr, int state)
-{
-	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
-		return -1;
-	} else {
-		switch (state) {
-		case 1:
-			/* Enable write access, clear bit GPIO0. */
-			out_be32((void*)GPIO0_OR,
-				 in_be32((void*)GPIO0_OR) &
-				 ~CONFIG_SYS_EEPROM_WP);
-			state = 0;
-			break;
-		case 0:
-			/* Disable write access, set bit GPIO0. */
-			out_be32((void*)GPIO0_OR,
-				 in_be32((void*)GPIO0_OR) |
-				 CONFIG_SYS_EEPROM_WP);
-			state = 0;
-			break;
-		default:
-			/* Read current status back. */
-			state = ((in_be32((void*)GPIO0_OR) &
-				       CONFIG_SYS_EEPROM_WP) == 0);
-			break;
-		}
-	}
-	return state;
-}
-
-int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int query = argc == 1;
-	int state = 0;
-
-	if (query) {
-		/* Query write access state. */
-		state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
-		if (state < 0) {
-			puts("Query of write access state failed.\n");
-		} else {
-			printf("Write access for device 0x%0x is %sabled.\n",
-			       CONFIG_SYS_I2C_EEPROM_ADDR,
-			       state ? "en" : "dis");
-			state = 0;
-		}
-	} else {
-		if (argv[1][0] == '0') {
-			/* Disable write access. */
-			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
-						    0);
-		} else {
-			/* Enable write access. */
-			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR,
-						    1);
-		}
-		if (state < 0)
-			puts("Setup of write access state failed.\n");
-	}
-
-	return state;
-}
-
-U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
-	"Enable / disable / query EEPROM write access",
-	""
-);
-#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/esd/pmc405de/Kconfig b/board/esd/pmc405de/Kconfig
deleted file mode 100644
index 4b05787..0000000
--- a/board/esd/pmc405de/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_PMC405DE
-
-config SYS_BOARD
-	default "pmc405de"
-
-config SYS_VENDOR
-	default "esd"
-
-config SYS_CONFIG_NAME
-	default "PMC405DE"
-
-endif
diff --git a/board/esd/pmc405de/MAINTAINERS b/board/esd/pmc405de/MAINTAINERS
deleted file mode 100644
index a891e23..0000000
--- a/board/esd/pmc405de/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PMC405DE BOARD
-M:	Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S:	Maintained
-F:	board/esd/pmc405de/
-F:	include/configs/PMC405DE.h
-F:	configs/PMC405DE_defconfig
diff --git a/board/esd/pmc405de/Makefile b/board/esd/pmc405de/Makefile
deleted file mode 100644
index b3f6dcd..0000000
--- a/board/esd/pmc405de/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= pmc405de.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-obj-y += ../common/cmd_loadpci.o
diff --git a/board/esd/pmc405de/chip_config.c b/board/esd/pmc405de/chip_config.c
deleted file mode 100644
index c06a6ae..0000000
--- a/board/esd/pmc405de/chip_config.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * (C) Copyright 2008-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-struct ppc4xx_config ppc4xx_config_val[] = {
-	{
-		"133",
-		"CPU: 133 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66",
-		{
-			0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-			0x00, 0x40, 0x12, 0x12, 0x42, 0x3e, 0x00, 0x00
-		}
-	},
-	{
-		"266",
-		"CPU: 266 PLB: 133 OPB: 66 EBC: 44 PCI: 44/66",
-		{
-			0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-			0x00, 0x50, 0x22, 0x2d, 0x42, 0x3e, 0x00, 0x00
-		}
-	},
-	{
-		"333",
-		"CPU: 333 PLB: 111 OPB: 55 EBC: 55 PCI: 55/111",
-		{
-			0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-			0x00, 0x60, 0x29, 0x2d, 0x42, 0xbe, 0x00, 0x00
-		}
-	},
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c
deleted file mode 100644
index 31ac728..0000000
--- a/board/esd/pmc405de/pmc405de.c
+++ /dev/null
@@ -1,507 +0,0 @@
-/*
- * (C) Copyright 2009
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <console.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/4xx_pci.h>
-#include <command.h>
-#include <malloc.h>
-
-/*
- * PMC405-DE cpld registers
- * - all registers are 8 bit
- * - all registers are on 32 bit addesses
- */
-struct pmc405de_cpld {
-	/* cpld design version */
-	u8 version;
-	u8 reserved0[3];
-
-	/* misc. status lines */
-	u8 status;
-	u8 reserved1[3];
-
-	/*
-	 * gated control flags
-	 * gate bit(s) must be written with '1' to
-	 * access control flag
-	 */
-	u8 control;
-	u8 reserved2[3];
-};
-
-#define CPLD_VERSION_MASK		0x0f
-#define CPLD_CONTROL_POSTLED_N		0x01
-#define CPLD_CONTROL_POSTLED_GATE	0x02
-#define CPLD_CONTROL_RESETOUT_N		0x40
-#define CPLD_CONTROL_RESETOUT_N_GATE	0x80
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void __ft_board_setup(void *blob, bd_t *bd);
-extern void pll_write(u32 a, u32 b);
-
-static int wait_for_pci_ready_done;
-
-static int is_monarch(void);
-static int pci_is_66mhz(void);
-static int board_revision(void);
-static int cpld_revision(void);
-static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div);
-
-int board_early_init_f(void)
-{
-	u32 pllmr0, pllmr1;
-
-	/*
-	 * check M66EN and patch PLB:PCI divider for 66MHz PCI
-	 *
-	 * fCPU==333MHz && fPCI==66MHz (PLBDiv==3 && M66EN==1): PLB/PCI=1
-	 * fCPU==333MHz && fPCI==33MHz (PLBDiv==3 && M66EN==0): PLB/PCI=2
-	 * fCPU==133|266MHz && fPCI==66MHz (PLBDiv==1|2 && M66EN==1): PLB/PCI=2
-	 * fCPU==133|266MHz && fPCI==33MHz (PLBDiv==1|2 && M66EN==0): PLB/PCI=3
-	 *
-	 * calling upd_plb_pci_div() may end in calling pll_write() which will
-	 * do a chip reset and never return.
-	 */
-	pllmr0 = mfdcr(CPC0_PLLMR0);
-	pllmr1 = mfdcr(CPC0_PLLMR1);
-
-	if ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) == PLLMR0_CPU_PLB_DIV_3) {
-		/* fCPU=333MHz, fPLB=111MHz */
-		if (pci_is_66mhz())
-			upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_1);
-		else
-			upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
-	} else {
-		/* fCPU=133|266MHz, fPLB=133MHz */
-		if (pci_is_66mhz())
-			upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_2);
-		else
-			upd_plb_pci_div(pllmr0, pllmr1, PLLMR0_PCI_PLB_DIV_3);
-	}
-
-	/*
-	 * IRQ 25 (EXT IRQ 0) PCI-INTA#; active low; level sensitive
-	 * IRQ 26 (EXT IRQ 1) PCI-INTB#; active low; level sensitive
-	 * IRQ 27 (EXT IRQ 2) PCI-INTC#; active low; level sensitive
-	 * IRQ 28 (EXT IRQ 3) PCI-INTD#; active low; level sensitive
-	 * IRQ 29 (EXT IRQ 4) ETH0-PHY-IRQ#; active low; level sensitive
-	 * IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive
-	 * IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive
-	 */
-	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
-	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
-	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
-	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0, INT0 highest prio */
-	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
-
-	/*
-	 * EBC Configuration Register:
-	 * - set ready timeout to 512 ebc-clks -> ca. 15 us
-	 * - EBC lines are always driven
-	 */
-	mtebc(EBC0_CFG, 0xa8400000);
-
-	return 0;
-}
-
-static void upd_plb_pci_div(u32 pllmr0, u32 pllmr1, u32 div)
-{
-	if ((pllmr0 & PLLMR0_PCI_TO_PLB_MASK) != div)
-		pll_write((pllmr0 & ~PLLMR0_PCI_TO_PLB_MASK) | div, pllmr1);
-}
-
-int misc_init_r(void)
-{
-	int i;
-	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
-	struct pmc405de_cpld *cpld =
-		(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
-
-	if (!is_monarch()) {
-		/* PCI configuration done: release EREADY */
-		setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EREADY);
-		setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_EREADY);
-	}
-
-	/* turn off POST LED */
-	out_8(&cpld->control,
-	      CPLD_CONTROL_POSTLED_N | CPLD_CONTROL_POSTLED_GATE);
-
-	/* turn on LEDs: RUN, A, B */
-	clrbits_be32(&gpio0->or,
-		     CONFIG_SYS_GPIO_LEDRUN_N |
-		     CONFIG_SYS_GPIO_LEDA_N |
-		     CONFIG_SYS_GPIO_LEDB_N);
-
-	for (i=0; i < 200; i++)
-		udelay(1000);
-
-	/* turn off LEDs: A, B */
-	setbits_be32(&gpio0->or,
-		     CONFIG_SYS_GPIO_LEDA_N |
-		     CONFIG_SYS_GPIO_LEDB_N);
-
-	return (0);
-}
-
-static int is_monarch(void)
-{
-	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
-	return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_MONARCH_N) == 0;
-}
-
-static int pci_is_66mhz(void)
-{
-	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
-	return (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_M66EN);
-}
-
-static int board_revision(void)
-{
-	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
-	return ((in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_HWREV_MASK) >>
-		CONFIG_SYS_GPIO_HWREV_SHIFT);
-}
-
-static int cpld_revision(void)
-{
-	struct pmc405de_cpld *cpld =
-		(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
-	return ((in_8(&cpld->version) & CPLD_VERSION_MASK));
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
-	puts("Board: esd GmbH - PMC-CPU/405-DE");
-
-	gd->board_type = board_revision();
-	printf(", Rev 1.%ld, ", gd->board_type);
-
-	if (!is_monarch())
-		puts("non-");
-
-	printf("monarch, PCI=%s MHz, PLD-Rev 1.%d\n",
-	       pci_is_66mhz() ? "66" : "33", cpld_revision());
-
-	return 0;
-}
-
-
-static void wait_for_pci_ready(void)
-{
-	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
-	int i;
-	char *s = getenv("pcidelay");
-
-	/* only wait once */
-	if (wait_for_pci_ready_done)
-		return;
-
-	/*
-	 * We have our own handling of the pcidelay variable.
-	 * Using CONFIG_PCI_BOOTDELAY enables pausing for host
-	 * and adapter devices. For adapter devices we do not
-	 * want this.
-	 */
-	if (s) {
-		int ms = simple_strtoul(s, NULL, 10);
-		printf("PCI:   Waiting for %d ms\n", ms);
-		for (i=0; i<ms; i++)
-			udelay(1000);
-	}
-
-	if (!(in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY)) {
-		printf("PCI:   Waiting for EREADY (CTRL-C to skip) ... ");
-		while (1) {
-			if (ctrlc()) {
-				puts("abort\n");
-				break;
-			}
-			if (in_be32(&gpio0->ir) & CONFIG_SYS_GPIO_EREADY) {
-				printf("done\n");
-				break;
-			}
-		}
-	}
-
-	wait_for_pci_ready_done = 1;
-}
-
-/*
- * Overwrite weak is_pci_host()
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- */
-int is_pci_host(struct pci_controller *hose)
-{
-	char *s;
-
-	if (!is_monarch()) {
-		/*
-		 * Overwrite PCI identification when running in
-		 * non-monarch mode
-		 * This should be moved into pci_target_init()
-		 * when it is sometimes available for 405 CPUs
-		 */
-		pci_write_config_word(PCIDEVID_405GP,
-				      PCI_SUBSYSTEM_ID,
-				      CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
-		pci_write_config_word(PCIDEVID_405GP,
-				      PCI_CLASS_SUB_CODE,
-				      CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
-	}
-
-	s = getenv("pciscan");
-	if (s == NULL) {
-		if (is_monarch()) {
-			wait_for_pci_ready();
-			return 1;
-		} else {
-			return 0;
-		}
-	} else {
-		if (!strcmp(s, "yes"))
-			return 1;
-	}
-
-	return 0;
-}
-
-/*
- * Overwrite weak pci_pre_init()
- *
- * The default implementation enables the 405EP
- * internal PCI arbiter. We do not want that
- * on a PMC module.
- */
-int pci_pre_init(struct pci_controller *hose)
-{
-	return 1;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	int rc;
-
-	__ft_board_setup(blob, bd);
-
-	/*
-	 * Disable PCI in non-monarch mode.
-	 */
-	if (!is_monarch()) {
-		rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
-					  "disabled", sizeof("disabled"), 1);
-		if (rc) {
-			printf("Unable to update property status in PCI node, "
-			       "err=%s\n",
-			       fdt_strerror(rc));
-		}
-	}
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-/* Input: <dev_addr>  I2C address of EEPROM device to enable.
- *         <state>     -1: deliver current state
- *                      0: disable write
- *                      1: enable write
- * Returns:            -1: wrong device address
- *                      0: dis-/en- able done
- *                    0/1: current state if <state> was -1.
- */
-int eeprom_write_enable(unsigned dev_addr, int state)
-{
-	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
-
-	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
-		return -1;
-	} else {
-		switch (state) {
-		case 1:
-			/* Enable write access, clear bit GPIO0. */
-			clrbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
-			state = 0;
-			break;
-		case 0:
-			/* Disable write access, set bit GPIO0. */
-			setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP);
-			state = 0;
-			break;
-		default:
-			/* Read current status back. */
-			state = (0 == (in_be32(&gpio0->or) &
-				       CONFIG_SYS_GPIO_EEPROM_WP));
-			break;
-		}
-	}
-	return state;
-}
-
-int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int query = argc == 1;
-	int state = 0;
-
-	if (query) {
-		/* Query write access state. */
-		state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, - 1);
-		if (state < 0) {
-			puts("Query of write access state failed.\n");
-		} else {
-			printf("Write access for device 0x%0x is %sabled.\n",
-				CONFIG_SYS_I2C_EEPROM_ADDR,
-				state ? "en" : "dis");
-			state = 0;
-		}
-	} else {
-		if ('0' == argv[1][0]) {
-			/* Disable write access. */
-			state = eeprom_write_enable(
-				CONFIG_SYS_I2C_EEPROM_ADDR, 0);
-		} else {
-			/* Enable write access. */
-			state = eeprom_write_enable(
-				CONFIG_SYS_I2C_EEPROM_ADDR, 1);
-		}
-		if (state < 0)
-			puts ("Setup of write access state failed.\n");
-	}
-
-	return state;
-}
-
-U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
-	"Enable / disable / query EEPROM write access",
-	""
-);
-#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
-
-#if defined(CONFIG_PRAM)
-#include <environment.h>
-
-int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	u32 pram, nextbase, base;
-	char *v;
-	u32 param;
-	ulong *lptr;
-
-	v = getenv("pram");
-	if (v)
-		pram = simple_strtoul(v, NULL, 10);
-	else {
-		printf("Error: pram undefined. Please define pram in KiB\n");
-		return 1;
-	}
-
-	base = gd->bd->bi_memsize;
-#if defined(CONFIG_LOGBUFFER)
-	base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
-#endif
-	/*
-	 * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MM_TOP_HIDE
-	 */
-	param = base - (pram << 10);
-	printf("PARAM: @%08x\n", param);
-	debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base);
-
-	/* clear entire PA ram */
-	memset((void*)param, 0, (pram << 10));
-
-	/* reserve 4k for pointer field */
-	nextbase = base - 4096;
-	lptr = (ulong*)(base);
-
-	/*
-	 * *(--lptr) = item_size;
-	 * *(--lptr) = base - item_base = distance from field top;
-	 */
-
-	/* env is first (4k aligned) */
-	nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
-	memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE);
-	*(--lptr) = CONFIG_ENV_SIZE;     /* size */
-	*(--lptr) = base - nextbase;  /* offset | type=0 */
-
-	/* free section */
-	*(--lptr) = nextbase - param; /* size */
-	*(--lptr) = (base - param) | 126; /* offset | type=126 */
-
-	/* terminate pointer field */
-	*(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
-	*(--lptr) = 0;                /* offset=0 -> terminator */
-	return 0;
-}
-U_BOOT_CMD(
-	painit,	1,	1,	do_painit,
-	"prepare PciAccess system",
-	""
-);
-#endif /* CONFIG_PRAM */
-
-int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE;
-	setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_SELFRST_N);
-	return 0;
-}
-U_BOOT_CMD(
-	selfreset,	1,	1,	do_selfreset,
-	"assert self-reset# signal",
-	""
-);
-
-int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	struct pmc405de_cpld *cpld =
-		(struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE;
-
-	if (argc > 1) {
-		if (argv[1][0] == '0') {
-			/* assert */
-			printf("PMC-RESETOUT# asserted\n");
-			out_8(&cpld->control,
-			      CPLD_CONTROL_RESETOUT_N_GATE);
-		} else {
-			/* deassert */
-			printf("PMC-RESETOUT# deasserted\n");
-			out_8(&cpld->control,
-			      CPLD_CONTROL_RESETOUT_N |
-			      CPLD_CONTROL_RESETOUT_N_GATE);
-		}
-	} else {
-		printf("PMC-RESETOUT# is %s\n",
-		       (in_8(&cpld->control) & CPLD_CONTROL_RESETOUT_N) ?
-		       "inactive" : "active");
-	}
-	return 0;
-}
-U_BOOT_CMD(
-	resetout,	2,	1,	do_resetout,
-	"assert PMC-RESETOUT# signal",
-	""
-);
diff --git a/board/esd/pmc440/Kconfig b/board/esd/pmc440/Kconfig
deleted file mode 100644
index df8bd65..0000000
--- a/board/esd/pmc440/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_PMC440
-
-config SYS_BOARD
-	default "pmc440"
-
-config SYS_VENDOR
-	default "esd"
-
-config SYS_CONFIG_NAME
-	default "PMC440"
-
-endif
diff --git a/board/esd/pmc440/MAINTAINERS b/board/esd/pmc440/MAINTAINERS
deleted file mode 100644
index 32fb9ba..0000000
--- a/board/esd/pmc440/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PMC440 BOARD
-M:	Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S:	Maintained
-F:	board/esd/pmc440/
-F:	include/configs/PMC440.h
-F:	configs/PMC440_defconfig
diff --git a/board/esd/pmc440/Makefile b/board/esd/pmc440/Makefile
deleted file mode 100644
index 708e9d1..0000000
--- a/board/esd/pmc440/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= pmc440.o cmd_pmc440.o sdram.o fpga.o \
-	../common/cmd_loadpci.o
-extra-y	+= init.o
diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c
deleted file mode 100644
index b7cd595..0000000
--- a/board/esd/pmc440/cmd_pmc440.c
+++ /dev/null
@@ -1,554 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <command.h>
-#include <console.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/processor.h>
-#if defined(CONFIG_LOGBUFFER)
-#include <logbuff.h>
-#endif
-
-#include "pmc440.h"
-
-int is_monarch(void);
-int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
-			   uchar *buffer, unsigned cnt);
-int eeprom_write_enable(unsigned dev_addr, int state);
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_BSP)
-
-static int got_fifoirq;
-static int got_hcirq;
-
-int fpga_interrupt(u32 arg)
-{
-	pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg;
-	int rc = -1; /* not for us */
-	u32 status = FPGA_IN32(&fpga->status);
-
-	/* check for interrupt from fifo module */
-	if (status & STATUS_FIFO_ISF) {
-		/* disable this int source */
-		FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
-		rc = 0;
-		got_fifoirq = 1; /* trigger backend */
-	}
-
-	if (status & STATUS_HOST_ISF) {
-		FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
-		rc = 0;
-		got_hcirq = 1;
-	}
-
-	return rc;
-}
-
-int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
-	got_hcirq = 0;
-
-	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
-	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
-
-	irq_install_handler(IRQ0_FPGA,
-			    (interrupt_handler_t *)fpga_interrupt,
-			    fpga);
-
-	FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
-
-	while (!got_hcirq) {
-		/* Abort if ctrl-c was pressed */
-		if (ctrlc()) {
-			puts("\nAbort\n");
-			break;
-		}
-	}
-	if (got_hcirq)
-		printf("Got interrupt!\n");
-
-	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
-	irq_free_handler(IRQ0_FPGA);
-	return 0;
-}
-U_BOOT_CMD(
-	waithci,	1,	1,	do_waithci,
-	"Wait for host control interrupt",
-	""
-);
-
-void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
-{
-	u32 ctrl;
-
-	while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
-		printf("%5d  %d    %3d  %08x",
-		       (*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
-		       FPGA_IN32(&fpga->fifo[f].data));
-		if (ctrl & FIFO_OVERFLOW) {
-			printf(" OVERFLOW\n");
-			FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
-		} else
-			printf("\n");
-	}
-}
-
-int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-	int i;
-	int n = 0;
-	u32 ctrl, data, f;
-	char str[] = "\\|/-";
-	int abort = 0;
-	int count = 0;
-	int count2 = 0;
-
-	switch (argc) {
-	case 1:
-		/* print all fifos status information */
-		printf("fifo level status\n");
-		printf("______________________________\n");
-		for (i=0; i<FIFO_COUNT; i++) {
-			ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
-			printf(" %d    %3d  %s%s%s %s\n",
-			       i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
-			       ctrl & FIFO_FULL ? "FULL     " : "",
-			       ctrl & FIFO_EMPTY ? "EMPTY    " : "",
-			       ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
-			       ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
-		}
-		break;
-
-	case 2:
-		/* completely read out fifo 'n' */
-		if (!strcmp(argv[1],"read")) {
-			printf("  #   fifo level data\n");
-			printf("______________________________\n");
-
-			for (i=0; i<FIFO_COUNT; i++)
-				dump_fifo(fpga, i, &n);
-
-		} else if (!strcmp(argv[1],"wait")) {
-			got_fifoirq = 0;
-
-			irq_install_handler(IRQ0_FPGA,
-					    (interrupt_handler_t *)fpga_interrupt,
-					    fpga);
-
-			printf("  #   fifo level data\n");
-			printf("______________________________\n");
-
-			/* enable all fifo interrupts */
-			FPGA_OUT32(&fpga->hostctrl,
-				   HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
-			for (i=0; i<FIFO_COUNT; i++) {
-				/* enable interrupts from all fifos */
-				FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
-			}
-
-			while (1) {
-				/* wait loop */
-				while (!got_fifoirq) {
-					count++;
-					if (!(count % 100)) {
-						count2++;
-						putc(0x08); /* backspace */
-						putc(str[count2 % 4]);
-					}
-
-					/* Abort if ctrl-c was pressed */
-					if ((abort = ctrlc())) {
-						puts("\nAbort\n");
-						break;
-					}
-					udelay(1000);
-				}
-				if (abort)
-					break;
-
-				/* simple fifo backend */
-				if (got_fifoirq) {
-					for (i=0; i<FIFO_COUNT; i++)
-						dump_fifo(fpga, i, &n);
-
-					got_fifoirq = 0;
-					/* unmask global fifo irq */
-					FPGA_OUT32(&fpga->hostctrl,
-						   HOSTCTRL_FIFOIE_GATE |
-						   HOSTCTRL_FIFOIE_FLAG);
-				}
-			}
-
-			/* disable all fifo interrupts */
-			FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
-			for (i=0; i<FIFO_COUNT; i++)
-				FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
-
-			irq_free_handler(IRQ0_FPGA);
-
-		} else {
-			printf("Usage:\nfifo %s\n", cmdtp->help);
-			return 1;
-		}
-		break;
-
-	case 4:
-	case 5:
-		if (!strcmp(argv[1],"write")) {
-			/* get fifo number or fifo address */
-			f = simple_strtoul(argv[2], NULL, 16);
-
-			/* data paramter */
-			data = simple_strtoul(argv[3], NULL, 16);
-
-			/* get optional count parameter */
-			n = 1;
-			if (argc >= 5)
-				n = (int)simple_strtoul(argv[4], NULL, 10);
-
-			if (f < FIFO_COUNT) {
-				printf("writing %d x %08x to fifo %d\n",
-				       n, data, f);
-				for (i=0; i<n; i++)
-					FPGA_OUT32(&fpga->fifo[f].data, data);
-			} else {
-				printf("writing %d x %08x to fifo port at "
-				       "address %08x\n",
-				       n, data, f);
-				for (i=0; i<n; i++)
-					out_be32((void *)f, data);
-			}
-		} else {
-			printf("Usage:\nfifo %s\n", cmdtp->help);
-			return 1;
-		}
-		break;
-
-	default:
-		printf("Usage:\nfifo %s\n", cmdtp->help);
-		return 1;
-	}
-	return 0;
-}
-U_BOOT_CMD(
-	fifo,	5,	1,	do_fifo,
-	"Fifo module operations",
-	"wait\nfifo read\n"
-	"fifo write fifo(0..3) data [cnt=1]\n"
-	"fifo write address(>=4) data [cnt=1]\n"
-	"  - without arguments: print all fifo's status\n"
-	"  - with 'wait' argument: interrupt driven read from all fifos\n"
-	"  - with 'read' argument: read current contents from all fifos\n"
-	"  - with 'write' argument: write 'data' 'cnt' times to "
-	"'fifo' or 'address'"
-);
-
-int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong sdsdp[5];
-	ulong delay;
-	int count=16;
-
-	if (argc < 2) {
-		printf("Usage:\nsbe %s\n", cmdtp->help);
-		return -1;
-	}
-
-	if (argc > 1) {
-		if (!strcmp(argv[1], "400")) {
-			/* PLB=133MHz, PLB/PCI=3 */
-			printf("Bootstrapping for 400MHz\n");
-			sdsdp[0]=0x8678624e;
-			sdsdp[1]=0x095fa030;
-			sdsdp[2]=0x40082350;
-			sdsdp[3]=0x0d050000;
-		} else if (!strcmp(argv[1], "533")) {
-			/* PLB=133MHz, PLB/PCI=3 */
-			printf("Bootstrapping for 533MHz\n");
-			sdsdp[0]=0x87788252;
-			sdsdp[1]=0x095fa030;
-			sdsdp[2]=0x40082350;
-			sdsdp[3]=0x0d050000;
-		} else if (!strcmp(argv[1], "667")) {
-			/* PLB=133MHz, PLB/PCI=3 */
-			printf("Bootstrapping for 667MHz\n");
-			sdsdp[0]=0x8778a256;
-			sdsdp[1]=0x095fa030;
-			sdsdp[2]=0x40082350;
-			sdsdp[3]=0x0d050000;
-		} else {
-			printf("Usage:\nsbe %s\n", cmdtp->help);
-			return -1;
-		}
-	}
-
-	if (argc > 2) {
-		sdsdp[4] = 0;
-		if (argv[2][0]=='1')
-			sdsdp[4]=0x19750100;
-		else if (argv[2][0]=='0')
-			sdsdp[4]=0x19750000;
-		if (sdsdp[4])
-			count += 4;
-	}
-
-	if (argc > 3) {
-		delay = simple_strtoul(argv[3], NULL, 10);
-		if (delay > 20)
-			delay = 20;
-		sdsdp[4] |= delay;
-	}
-
-	printf("Writing boot EEPROM ...\n");
-	if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
-				   0, (uchar*)sdsdp, count) != 0)
-		printf("bootstrap_eeprom_write failed\n");
-	else
-		printf("done (dump via 'i2c md 52 0.1 14')\n");
-
-	return 0;
-}
-U_BOOT_CMD(
-	sbe, 4, 0, do_setup_bootstrap_eeprom,
-	"setup bootstrap eeprom",
-	"<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
-);
-
-#if defined(CONFIG_PRAM)
-#include <environment.h>
-#include <search.h>
-#include <errno.h>
-
-int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	u32 pram, nextbase, base;
-	char *v;
-	u32 param;
-	ulong *lptr;
-
-	env_t *envp;
-	char *res;
-	int len;
-
-	v = getenv("pram");
-	if (v)
-		pram = simple_strtoul(v, NULL, 10);
-	else {
-		printf("Error: pram undefined. Please define pram in KiB\n");
-		return 1;
-	}
-
-	base = (u32)gd->ram_size;
-#if defined(CONFIG_LOGBUFFER)
-	base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
-#endif
-	/*
-	 * gd->ram_size == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
-	 */
-	param = base - (pram << 10);
-	printf("PARAM: @%08x\n", param);
-	debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->ram_size, base);
-
-	/* clear entire PA ram */
-	memset((void*)param, 0, (pram << 10));
-
-	/* reserve 4k for pointer field */
-	nextbase = base - 4096;
-	lptr = (ulong*)(base);
-
-	/*
-	 * *(--lptr) = item_size;
-	 * *(--lptr) = base - item_base = distance from field top;
-	 */
-
-	/* env is first (4k aligned) */
-	nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
-	envp = (env_t *)nextbase;
-	res = (char *)envp->data;
-	len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
-	if (len < 0) {
-		error("Cannot export environment: errno = %d\n", errno);
-		return 1;
-	}
-	envp->crc = crc32(0, envp->data, ENV_SIZE);
-
-	*(--lptr) = CONFIG_ENV_SIZE;     /* size */
-	*(--lptr) = base - nextbase;  /* offset | type=0 */
-
-	/* free section */
-	*(--lptr) = nextbase - param; /* size */
-	*(--lptr) = (base - param) | 126; /* offset | type=126 */
-
-	/* terminate pointer field */
-	*(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
-	*(--lptr) = 0;                /* offset=0 -> terminator */
-	return 0;
-}
-U_BOOT_CMD(
-	painit,	1,	1,	do_painit,
-	"prepare PciAccess system",
-	""
-);
-#endif /* CONFIG_PRAM */
-
-int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	in_be32((void*)CONFIG_SYS_RESET_BASE);
-	return 0;
-}
-U_BOOT_CMD(
-	selfreset,	1,	1,	do_selfreset,
-	"assert self-reset# signal",
-	""
-);
-
-int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
-	/* requiers bootet FPGA and PLD_IOEN_N active */
-	if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
-		printf("Error: resetout requires a bootet FPGA\n");
-		return -1;
-	}
-
-	if (argc > 1) {
-		if (argv[1][0] == '0') {
-			/* assert */
-			printf("PMC-RESETOUT# asserted\n");
-			FPGA_OUT32(&fpga->hostctrl,
-				   HOSTCTRL_PMCRSTOUT_GATE);
-		} else {
-			/* deassert */
-			printf("PMC-RESETOUT# deasserted\n");
-			FPGA_OUT32(&fpga->hostctrl,
-				   HOSTCTRL_PMCRSTOUT_GATE |
-				   HOSTCTRL_PMCRSTOUT_FLAG);
-		}
-	} else {
-		printf("PMC-RESETOUT# is %s\n",
-		       FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
-		       "inactive" : "active");
-	}
-
-	return 0;
-}
-U_BOOT_CMD(
-	resetout,	2,	1,	do_resetout,
-	"assert PMC-RESETOUT# signal",
-	""
-);
-
-int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	if (is_monarch()) {
-		printf("This command is only supported in non-monarch mode\n");
-		return -1;
-	}
-
-	if (argc > 1) {
-		if (argv[1][0] == '0') {
-			/* assert */
-			printf("inta# asserted\n");
-			out_be32((void*)GPIO1_TCR,
-				 in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE);
-		} else {
-			/* deassert */
-			printf("inta# deasserted\n");
-			out_be32((void*)GPIO1_TCR,
-				 in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
-		}
-	} else {
-		printf("inta# is %s\n",
-		       in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
-		       "active" : "inactive");
-	}
-	return 0;
-}
-U_BOOT_CMD(
-	inta,	2,	1,	do_inta,
-	"Assert/Deassert or query INTA# state in non-monarch mode",
-	""
-);
-
-/* test-only */
-int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong pciaddr;
-
-	if (argc > 1) {
-		pciaddr = simple_strtoul(argv[1], NULL, 16);
-
-		pciaddr &= 0xf0000000;
-
-		/* map PCI address at 0xc0000000 in PLB space */
-
-		/* PMM1 Mask/Attribute - disabled b4 setting */
-		out32r(PCIL0_PMM1MA, 0x00000000);
-		/* PMM1 Local Address */
-		out32r(PCIL0_PMM1LA, 0xc0000000);
-		/* PMM1 PCI Low Address */
-		out32r(PCIL0_PMM1PCILA, pciaddr);
-		/* PMM1 PCI High Address */
-		out32r(PCIL0_PMM1PCIHA, 0x00000000);
-		/* 256MB + No prefetching, and enable region */
-		out32r(PCIL0_PMM1MA, 0xf0000001);
-	} else {
-		printf("Usage:\npmm %s\n", cmdtp->help);
-	}
-	return 0;
-}
-U_BOOT_CMD(
-	pmm,	2,	1,	do_pmm,
-	"Setup pmm[1] registers",
-	"<pciaddr> (pciaddr will be aligned to 256MB)"
-);
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int query = argc == 1;
-	int state = 0;
-
-	if (query) {
-		/* Query write access state. */
-		state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
-		if (state < 0) {
-			puts("Query of write access state failed.\n");
-		} else {
-			printf("Write access for device 0x%0x is %sabled.\n",
-			       CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
-			state = 0;
-		}
-	} else {
-		if ('0' == argv[1][0]) {
-			/* Disable write access. */
-			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
-		} else {
-			/* Enable write access. */
-			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
-		}
-		if (state < 0) {
-			puts("Setup of write access state failed.\n");
-		}
-	}
-
-	return state;
-}
-U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
-	"Enable / disable / query EEPROM write access",
-	""
-);
-#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
-
-#endif /* CONFIG_CMD_BSP */
diff --git a/board/esd/pmc440/config.mk b/board/esd/pmc440/config.mk
deleted file mode 100644
index 9cb071e..0000000
--- a/board/esd/pmc440/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2002-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c
deleted file mode 100644
index f876da8..0000000
--- a/board/esd/pmc440/fpga.c
+++ /dev/null
@@ -1,446 +0,0 @@
-/*
- * (C) Copyright 2007
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <spartan2.h>
-#include <spartan3.h>
-#include <command.h>
-#include "fpga.h"
-#include "pmc440.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_FPGA)
-
-#define USE_SP_CODE
-
-#ifdef USE_SP_CODE
-xilinx_spartan3_slave_parallel_fns pmc440_fpga_fns = {
-	fpga_pre_config_fn,
-	fpga_pgm_fn,
-	fpga_init_fn,
-	NULL, /* err */
-	fpga_done_fn,
-	fpga_clk_fn,
-	fpga_cs_fn,
-	fpga_wr_fn,
-	NULL, /* rdata */
-	fpga_wdata_fn,
-	fpga_busy_fn,
-	fpga_abort_fn,
-	fpga_post_config_fn,
-};
-#else
-xilinx_spartan3_slave_serial_fns pmc440_fpga_fns = {
-	fpga_pre_config_fn,
-	fpga_pgm_fn,
-	fpga_clk_fn,
-	fpga_init_fn,
-	fpga_done_fn,
-	fpga_wr_fn,
-	fpga_post_config_fn,
-};
-#endif
-
-xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = {
-	ngcc_fpga_pre_config_fn,
-	ngcc_fpga_pgm_fn,
-	ngcc_fpga_clk_fn,
-	ngcc_fpga_init_fn,
-	ngcc_fpga_done_fn,
-	ngcc_fpga_wr_fn,
-	ngcc_fpga_post_config_fn
-};
-
-xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
-	XILINX_XC3S1200E_DESC(
-#ifdef USE_SP_CODE
-		slave_parallel,
-#else
-		slave_serial,
-#endif
-		(void *)&pmc440_fpga_fns,
-		0),
-	XILINX_XC2S200_DESC(
-		slave_serial,
-		(void *)&ngcc_fpga_fns,
-		0)
-};
-
-
-/*
- * Set the active-low FPGA reset signal.
- */
-void fpga_reset(int assert)
-{
-	debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
-	if (assert) {
-		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
-		debug("asserted\n");
-	} else {
-		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
-		debug("deasserted\n");
-	}
-}
-
-
-/*
- * Initialize the SelectMap interface.  We assume that the mode and the
- * initial state of all of the port pins have already been set!
- */
-void fpga_serialslave_init(void)
-{
-	debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__,
-	      __LINE__);
-	fpga_pgm_fn(false, false, 0);	/* make sure program pin is inactive */
-}
-
-
-/*
- * Set the FPGA's active-low SelectMap program line to the specified level
- */
-int fpga_pgm_fn(int assert, int flush, int cookie)
-{
-	debug("%s:%d: FPGA PROGRAM ",
-	      __FUNCTION__, __LINE__);
-
-	if (assert) {
-		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_PRG);
-		debug("asserted\n");
-	} else {
-		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_PRG);
-		debug("deasserted\n");
-	}
-	return assert;
-}
-
-
-/*
- * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
- * asserted (low).
- */
-int fpga_init_fn(int cookie)
-{
-	if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_INIT)
-		return 0;
-	else
-		return 1;
-}
-
-#ifdef USE_SP_CODE
-int fpga_abort_fn(int cookie)
-{
-	return 0;
-}
-
-
-int fpga_cs_fn(int assert_cs, int flush, int cookie)
-{
-	return assert_cs;
-}
-
-
-int fpga_busy_fn(int cookie)
-{
-	return 1;
-}
-#endif
-
-
-/*
- * Test the state of the active-high FPGA DONE pin
- */
-int fpga_done_fn(int cookie)
-{
-	if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_DONE)
-		return 1;
-	else
-		return 0;
-}
-
-
-/*
- * FPGA pre-configuration function. Just make sure that
- * FPGA reset is asserted to keep the FPGA from starting up after
- * configuration.
- */
-int fpga_pre_config_fn(int cookie)
-{
-	debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
-	fpga_reset(true);
-
-	/* release init# */
-	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT);
-	/* disable PLD IOs */
-	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_IOEN_N);
-	return 0;
-}
-
-
-/*
- * FPGA post configuration function. Blip the FPGA reset line and then see if
- * the FPGA appears to be running.
- */
-int fpga_post_config_fn(int cookie)
-{
-	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-	int rc=0;
-	char *s;
-
-	debug("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
-
-	/* enable PLD0..7 pins */
-	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N);
-
-	fpga_reset(true);
-	udelay (100);
-	fpga_reset(false);
-	udelay (100);
-
-	FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
-
-	/* NGCC/CANDES only: enable ledlink */
-	if ((s = getenv("bd_type")) &&
-	    ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes"))))
-		FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
-
-	return rc;
-}
-
-
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
-	if (assert_clk)
-		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_CLK);
-	else
-		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_CLK);
-
-	return assert_clk;
-}
-
-
-int fpga_wr_fn(int assert_write, int flush, int cookie)
-{
-	if (assert_write)
-		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
-	else
-		out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
-
-	return assert_write;
-}
-
-#ifdef USE_SP_CODE
-int fpga_wdata_fn(uchar data, int flush, int cookie)
-{
-	uchar val = data;
-	ulong or = in_be32((void*)GPIO1_OR);
-	int i = 7;
-	do {
-		/* Write data */
-		if (val & 0x80)
-			or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
-		else
-			or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
-
-		out_be32((void*)GPIO1_OR, or);
-
-		/* Assert the clock */
-		or |= GPIO1_FPGA_CLK;
-		out_be32((void*)GPIO1_OR, or);
-		val <<= 1;
-		i --;
-	} while (i > 0);
-
-	/* Write last data bit (the 8th clock comes from the sp_load() code */
-	if (val & 0x80)
-		or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
-	else
-		or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
-
-	out_be32((void*)GPIO1_OR, or);
-
-	return 0;
-}
-#endif
-
-#define NGCC_FPGA_PRG  CLOCK_EN
-#define NGCC_FPGA_DATA RESET_OUT
-#define NGCC_FPGA_DONE CLOCK_IN
-#define NGCC_FPGA_INIT IRIGB_R_IN
-#define NGCC_FPGA_CLK  CLOCK_OUT
-
-void ngcc_fpga_serialslave_init(void)
-{
-	debug("%s:%d: Initialize serial slave interface\n",
-	      __FUNCTION__, __LINE__);
-
-	/* make sure program pin is inactive */
-	ngcc_fpga_pgm_fn(false, false, 0);
-}
-
-/*
- * Set the active-low FPGA reset signal.
- */
-void ngcc_fpga_reset(int assert)
-{
-	debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
-
-	if (assert) {
-		FPGA_CLRBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
-		debug("asserted\n");
-	} else {
-		FPGA_SETBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
-		debug("deasserted\n");
-	}
-}
-
-
-/*
- * Set the FPGA's active-low SelectMap program line to the specified level
- */
-int ngcc_fpga_pgm_fn(int assert, int flush, int cookie)
-{
-	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
-	debug("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
-
-	if (assert) {
-		FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_PRG);
-		debug("asserted\n");
-	} else {
-		FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_PRG);
-		debug("deasserted\n");
-	}
-
-	return assert;
-}
-
-
-/*
- * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
- * asserted (low).
- */
-int ngcc_fpga_init_fn(int cookie)
-{
-	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
-	debug("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
-	if (FPGA_IN32(&fpga->status) & NGCC_FPGA_INIT) {
-		debug("high\n");
-		return 0;
-	} else {
-		debug("low\n");
-		return 1;
-	}
-}
-
-
-/*
- * Test the state of the active-high FPGA DONE pin
- */
-int ngcc_fpga_done_fn(int cookie)
-{
-	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
-	debug("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
-	if (FPGA_IN32(&fpga->status) & NGCC_FPGA_DONE) {
-		debug("DONE high\n");
-		return 1;
-	} else {
-		debug("low\n");
-		return 0;
-	}
-}
-
-
-/*
- * FPGA pre-configuration function.
- */
-int ngcc_fpga_pre_config_fn(int cookie)
-{
-	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-	debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
-
-	ngcc_fpga_reset(true);
-	FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00);
-
-	ngcc_fpga_reset(true);
-	return 0;
-}
-
-
-/*
- * FPGA post configuration function. Blip the FPGA reset line and then see if
- * the FPGA appears to be running.
- */
-int ngcc_fpga_post_config_fn(int cookie)
-{
-	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
-	debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__);
-
-	udelay (100);
-	ngcc_fpga_reset(false);
-
-	FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
-
-	return 0;
-}
-
-
-int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
-	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
-	if (assert_clk)
-		FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_CLK);
-	else
-		FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_CLK);
-
-	return assert_clk;
-}
-
-
-int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie)
-{
-	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
-
-	if (assert_write)
-		FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_DATA);
-	else
-		FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_DATA);
-
-	return assert_write;
-}
-
-
-/*
- * Initialize the fpga.  Return 1 on success, 0 on failure.
- */
-int pmc440_init_fpga(void)
-{
-	char *s;
-
-	debug("%s:%d: Initialize FPGA interface\n",
-	      __FUNCTION__, __LINE__);
-	fpga_init();
-
-	fpga_serialslave_init ();
-	debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__);
-	fpga_add (fpga_xilinx, &fpga[0]);
-
-	/* NGCC only */
-	if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) {
-		ngcc_fpga_serialslave_init ();
-		debug("%s:%d: Adding fpga 1\n", __FUNCTION__, __LINE__);
-		fpga_add (fpga_xilinx, &fpga[1]);
-	}
-
-	return 0;
-}
-#endif /* CONFIG_FPGA */
diff --git a/board/esd/pmc440/fpga.h b/board/esd/pmc440/fpga.h
deleted file mode 100644
index 3810788..0000000
--- a/board/esd/pmc440/fpga.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2007
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-extern int pmc440_init_fpga(void);
-
-extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int fpga_init_fn(int cookie);
-extern int fpga_err_fn(int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
-extern int fpga_wr_fn(int assert_write, int flush, int cookie);
-extern int fpga_wdata_fn (uchar data, int flush, int cookie);
-extern int fpga_read_data_fn(unsigned char *data, int cookie);
-extern int fpga_write_data_fn(unsigned char data, int flush, int cookie);
-extern int fpga_busy_fn(int cookie);
-extern int fpga_abort_fn(int cookie );
-extern int fpga_pre_config_fn(int cookie );
-extern int fpga_post_config_fn(int cookie );
-
-extern int ngcc_fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int ngcc_fpga_init_fn(int cookie);
-extern int ngcc_fpga_done_fn(int cookie);
-extern int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie);
-extern int ngcc_fpga_pre_config_fn(int cookie );
-extern int ngcc_fpga_post_config_fn(int cookie );
diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S
deleted file mode 100644
index 1f26fad..0000000
--- a/board/esd/pmc440/init.S
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-
-/*
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- */
-    .section .bootpg,"ax"
-    .globl tlbtab
-
-tlbtab:
-	tlbtab_start
-
-	/*
-	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
-	 * speed up boot process. It is patched after relocation to enable SA_I
-	 */
-	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
-
-	/* TLB entries for DDR2 SDRAM are generated dynamically */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
-	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
-#endif
-
-	/* TLB-entry for PCI Memory */
-	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
-	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
-	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
-	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
-
-	/* TLB-entries for EBC */
-	/* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
-	 * tlb entry.
-	 * This dummy entry is only for convinience in order not to modify the
-	 * amount of entries. Currently OS/9 relies on this :-)
-	 */
-	tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_RWX | SA_IG )
-
-	/* TLB-entry for NAND */
-	tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
-
-	/* TLB-entry for Internal Registers & OCM */
-	tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_RWX | SA_I )
-
-	/*TLB-entry PCI registers*/
-	tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG )
-
-	/* TLB-entry for peripherals */
-	tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
-
-	/* TLB-entry PCI IO space */
-	tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
-
-	/* TODO:  what about high IO space */
-	tlbtab_end
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
deleted file mode 100644
index 0d43505..0000000
--- a/board/esd/pmc440/pmc440.c
+++ /dev/null
@@ -1,906 +0,0 @@
-/*
- * (Cg) Copyright 2007-2008
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
- * Based on board/amcc/sequoia/sequoia.c
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <console.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/ppc440.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <i2c.h>
-#ifdef CONFIG_RESET_PHY_R
-#include <miiphy.h>
-#endif
-#include <serial.h>
-#include <asm/4xx_pci.h>
-#include <usb.h>
-
-#include "fpga.h"
-#include "pmc440.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-extern void __ft_board_setup(void *blob, bd_t *bd);
-
-ulong flash_get_size(ulong base, int banknum);
-static int pci_is_66mhz(void);
-int is_monarch(void);
-static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
-				 uchar *buffer, unsigned cnt);
-
-struct serial_device *default_serial_console(void)
-{
-	uchar buf[4];
-	ulong delay;
-	int i;
-	ulong val;
-
-	/*
-	 * Use default console on P4 when strapping jumper
-	 * is installed (bootstrap option != 'H').
-	 */
-	mfsdr(SDR0_PINSTP, val);
-	if (((val & 0xf0000000) >> 29) != 7)
-		return &eserial2_device;
-
-	ulong scratchreg = in_be32((void *)GPIO0_ISR3L);
-	if (!(scratchreg & 0x80)) {
-		/* mark scratchreg valid */
-		scratchreg = (scratchreg & 0xffffff00) | 0x80;
-
-		i2c_init_all();
-
-		i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
-					  0x10, buf, 4);
-		if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
-			scratchreg |= buf[2];
-
-			/* bringup delay for console */
-			for (delay = 0; delay < (1000 * (ulong)buf[3]); delay++)
-				udelay(1000);
-		} else
-			scratchreg |= 0x01;
-		out_be32((void *)GPIO0_ISR3L, scratchreg);
-	}
-
-	if (scratchreg & 0x01)
-		return &eserial2_device;
-	else
-		return &eserial1_device;
-}
-
-int board_early_init_f(void)
-{
-	u32 sdr0_cust0;
-	u32 sdr0_pfc1, sdr0_pfc2;
-	u32 reg;
-
-	/* general EBC configuration (disable EBC timeouts) */
-	mtdcr(EBC0_CFGADDR, EBC0_CFG);
-	mtdcr(EBC0_CFGDATA, 0xf8400000);
-
-	/* Setup the GPIO pins */
-	out_be32((void *)GPIO0_OR,    0x40000102);
-	out_be32((void *)GPIO0_TCR,   0x4c90011f);
-	out_be32((void *)GPIO0_OSRL,  0x28051400);
-	out_be32((void *)GPIO0_OSRH,  0x55005000);
-	out_be32((void *)GPIO0_TSRL,  0x08051400);
-	out_be32((void *)GPIO0_TSRH,  0x55005000);
-	out_be32((void *)GPIO0_ISR1L, 0x54000000);
-	out_be32((void *)GPIO0_ISR1H, 0x00000000);
-	out_be32((void *)GPIO0_ISR2L, 0x44000000);
-	out_be32((void *)GPIO0_ISR2H, 0x00000100);
-	out_be32((void *)GPIO0_ISR3L, 0x00000000);
-	out_be32((void *)GPIO0_ISR3H, 0x00000000);
-
-	out_be32((void *)GPIO1_OR,    0x80002408);
-	out_be32((void *)GPIO1_TCR,   0xd6003c08);
-	out_be32((void *)GPIO1_OSRL,  0x0a5a0000);
-	out_be32((void *)GPIO1_OSRH,  0x00000000);
-	out_be32((void *)GPIO1_TSRL,  0x00000000);
-	out_be32((void *)GPIO1_TSRH,  0x00000000);
-	out_be32((void *)GPIO1_ISR1L, 0x00005555);
-	out_be32((void *)GPIO1_ISR1H, 0x40000000);
-	out_be32((void *)GPIO1_ISR2L, 0x04010000);
-	out_be32((void *)GPIO1_ISR2H, 0x00000000);
-	out_be32((void *)GPIO1_ISR3L, 0x01400000);
-	out_be32((void *)GPIO1_ISR3H, 0x00000000);
-
-	/* patch PLB:PCI divider for 66MHz PCI */
-	mfcpr(CPR0_SPCID, reg);
-	if (pci_is_66mhz() && (reg != 0x02000000)) {
-		mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
-
-		mfcpr(CPR0_ICFG, reg);
-		reg |= CPR0_ICFG_RLI_MASK;
-		mtcpr(CPR0_ICFG, reg);
-
-		mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */
-	}
-
-	/*
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all */
-	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(UIC0PR, 0xfffff7ef);
-	mtdcr(UIC0TR, 0x00000000);
-	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC1ER, 0x00000000);	/* disable all */
-	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC1PR, 0xffffc7f5);
-	mtdcr(UIC1TR, 0x00000000);
-	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC2ER, 0x00000000);	/* disable all */
-	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC2PR, 0x27ffffff);
-	mtdcr(UIC2TR, 0x00000000);
-	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-
-	/* select Ethernet pins */
-	mfsdr(SDR0_PFC1, sdr0_pfc1);
-	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
-		SDR0_PFC1_SELECT_CONFIG_4;
-	mfsdr(SDR0_PFC2, sdr0_pfc2);
-	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
-		SDR0_PFC2_SELECT_CONFIG_4;
-
-	/* enable 2nd IIC */
-	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
-
-	mtsdr(SDR0_PFC2, sdr0_pfc2);
-	mtsdr(SDR0_PFC1, sdr0_pfc1);
-
-	/* setup NAND FLASH */
-	mfsdr(SDR0_CUST0, sdr0_cust0);
-	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
-		SDR0_CUST0_NDFC_ENABLE		|
-		SDR0_CUST0_NDFC_BW_8_BIT	|
-		SDR0_CUST0_NDFC_ARE_MASK	|
-		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
-	mtsdr(SDR0_CUST0, sdr0_cust0);
-
-	return 0;
-}
-
-#if defined(CONFIG_MISC_INIT_F)
-int misc_init_f(void)
-{
-	struct pci_controller hose;
-	hose.first_busno = 0;
-	hose.last_busno = 0;
-	hose.region_count = 0;
-
-	if (getenv("pciearly") && (!is_monarch())) {
-		printf("PCI:   early target init\n");
-		pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA);
-		pci_target_init(&hose);
-	}
-	return 0;
-}
-#endif
-
-/*
- * misc_init_r.
- */
-int misc_init_r(void)
-{
-	uint pbcr;
-	int size_val = 0;
-	u32 reg;
-	unsigned long usb2d0cr = 0;
-	unsigned long usb2phy0cr, usb2h0cr = 0;
-	unsigned long sdr0_pfc1;
-	unsigned long sdr0_srst0, sdr0_srst1;
-	char *act = getenv("usbact");
-
-	/*
-	 * FLASH stuff...
-	 */
-
-	/* Re-do sizing to get full correct info */
-
-	/* adjust flash start and offset */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-	gd->bd->bi_flashoffset = 0;
-
-	mtdcr(EBC0_CFGADDR, PB0CR);
-	pbcr = mfdcr(EBC0_CFGDATA);
-	size_val = ffs(gd->bd->bi_flashsize) - 21;
-	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-	mtdcr(EBC0_CFGADDR, PB0CR);
-	mtdcr(EBC0_CFGDATA, pbcr);
-
-	/*
-	 * Re-check to get correct base address
-	 */
-	flash_get_size(gd->bd->bi_flashstart, 0);
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-	/* Monitor protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CONFIG_SYS_MONITOR_LEN,
-			    0xffffffff,
-			    &flash_info[0]);
-
-	/* Env protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    CONFIG_ENV_ADDR_REDUND,
-			    CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
-			    &flash_info[0]);
-#endif
-
-	/*
-	 * USB suff...
-	 */
-	if ((act == NULL || strcmp(act, "host") == 0) &&
-	    !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
-		/* SDR Setting */
-		mfsdr(SDR0_PFC1, sdr0_pfc1);
-		mfsdr(SDR0_USB2D0CR, usb2d0cr);
-		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-		mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
-
-		/*
-		 * An 8-bit/60MHz interface is the only possible alternative
-		 * when connecting the Device to the PHY
-		 */
-		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
-		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
-
-		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
-		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
-
-		mtsdr(SDR0_PFC1, sdr0_pfc1);
-		mtsdr(SDR0_USB2D0CR, usb2d0cr);
-		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-		mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
-		/*
-		 * Take USB out of reset:
-		 * -Initial status = all cores are in reset
-		 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
-		 * -wait 1 ms
-		 * -deassert reset to PHY
-		 * -wait 1 ms
-		 * -deassert  reset to HOST
-		 * -wait 4 ms
-		 * -deassert all other resets
-		 */
-		mfsdr(SDR0_SRST1, sdr0_srst1);
-		sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 |	\
-				SDR0_SRST1_P4OPB0 |	\
-				SDR0_SRST1_OPBA2 |	\
-				SDR0_SRST1_PLB42OPB1 |	\
-				SDR0_SRST1_OPB2PLB40);
-		mtsdr(SDR0_SRST1, sdr0_srst1);
-		udelay(1000);
-
-		mfsdr(SDR0_SRST1, sdr0_srst1);
-		sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
-		mtsdr(SDR0_SRST1, sdr0_srst1);
-		udelay(1000);
-
-		mfsdr(SDR0_SRST0, sdr0_srst0);
-		sdr0_srst0 &= ~SDR0_SRST0_USB2H;
-		mtsdr(SDR0_SRST0, sdr0_srst0);
-		udelay(4000);
-
-		/* finally all the other resets */
-		mtsdr(SDR0_SRST1, 0x00000000);
-		mtsdr(SDR0_SRST0, 0x00000000);
-
-		if (!(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
-			/* enable power on USB socket */
-			out_be32((void *)GPIO1_OR,
-				 in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
-		}
-
-		printf("USB:   Host\n");
-
-	} else if ((strcmp(act, "dev") == 0) ||
-		   (in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
-		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
-		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-
-		udelay (1000);
-		mtsdr(SDR0_SRST1, 0x672c6000);
-
-		udelay (1000);
-		mtsdr(SDR0_SRST0, 0x00000080);
-
-		udelay (1000);
-		mtsdr(SDR0_SRST1, 0x60206000);
-
-		*(unsigned int *)(0xe0000350) = 0x00000001;
-
-		udelay (1000);
-		mtsdr(SDR0_SRST1, 0x60306000);
-
-		/* SDR Setting */
-		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-		mfsdr(SDR0_USB2H0CR, usb2h0cr);
-		mfsdr(SDR0_USB2D0CR, usb2d0cr);
-		mfsdr(SDR0_PFC1, sdr0_pfc1);
-
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
-		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
-
-		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
-		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
-
-		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
-
-		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
-		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
-
-		mtsdr(SDR0_USB2H0CR, usb2h0cr);
-		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-		mtsdr(SDR0_USB2D0CR, usb2d0cr);
-		mtsdr(SDR0_PFC1, sdr0_pfc1);
-
-		/*clear resets*/
-		udelay(1000);
-		mtsdr(SDR0_SRST1, 0x00000000);
-		udelay(1000);
-		mtsdr(SDR0_SRST0, 0x00000000);
-
-		printf("USB:   Device\n");
-	}
-
-	/*
-	 * Clear PLB4A0_ACR[WRP]
-	 * This fix will make the MAL burst disabling patch for the Linux
-	 * EMAC driver obsolete.
-	 */
-	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
-	mtdcr(PLB4A0_ACR, reg);
-
-#ifdef CONFIG_FPGA
-	pmc440_init_fpga();
-#endif
-
-	/* turn off POST LED */
-	out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) & ~GPIO1_POST_N);
-	/* turn on RUN LED */
-	out_be32((void *)GPIO0_OR,
-		 in_be32((void *)GPIO0_OR) & ~GPIO0_LED_RUN_N);
-	return 0;
-}
-
-int is_monarch(void)
-{
-	if (in_be32((void *)GPIO1_IR) & GPIO1_NONMONARCH)
-		return 0;
-
-	return 1;
-}
-
-static int pci_is_66mhz(void)
-{
-	if (in_be32((void *)GPIO1_IR) & GPIO1_M66EN)
-		return 1;
-	return 0;
-}
-
-static int board_revision(void)
-{
-	return (int)((in_be32((void *)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
-}
-
-int checkboard(void)
-{
-	puts("Board: esd GmbH - PMC440");
-
-	gd->board_type = board_revision();
-	printf(", Rev 1.%ld, ", gd->board_type);
-
-	if (!is_monarch()) {
-		puts("non-");
-	}
-
-	printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
-	return (0);
-}
-
-
-#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
-/*
- * Assign interrupts to PCI devices. Some OSs rely on this.
- */
-void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
-	unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
-
-	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
-				   int_line[PCI_DEV(dev) & 0x03]);
-}
-#endif
-
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
-	char *ptmla_str, *ptmms_str;
-
-	/*
-	 * Set up Direct MMIO registers
-	 */
-	/*
-	 * PowerPC440EPX PCI Master configuration.
-	 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
-	 * PLB address 0x80000000-0xBFFFFFFF
-	 *     ==> PCI address 0x80000000-0xBFFFFFFF
-	 * Use byte reversed out routines to handle endianess.
-	 * Make this region non-prefetchable.
-	 */
-	out32r(PCIL0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
-						/* - disabled b4 setting */
-	out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Addr */
-	out32r(PCIL0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
-	out32r(PCIL0_PMM0MA, 0xc0000001);	/* 1G + No prefetching, */
-						/* and enable region */
-
-	if (!is_monarch()) {
-		ptmla_str = getenv("ptm1la");
-		ptmms_str = getenv("ptm1ms");
-		if(NULL != ptmla_str && NULL != ptmms_str ) {
-			out32r(PCIL0_PTM1MS,
-			       simple_strtoul(ptmms_str, NULL, 16));
-			out32r(PCIL0_PTM1LA,
-			       simple_strtoul(ptmla_str, NULL, 16));
-		} else {
-			/* BAR1: default top 64MB of RAM */
-			out32r(PCIL0_PTM1MS, 0xfc000001);
-			out32r(PCIL0_PTM1LA, 0x0c000000);
-		}
-	} else {
-		/* BAR1: default: complete 256MB RAM */
-		out32r(PCIL0_PTM1MS, 0xf0000001);
-		out32r(PCIL0_PTM1LA, 0x00000000);
-	}
-
-	ptmla_str = getenv("ptm2la");		/* Local Addr. Reg */
-	ptmms_str = getenv("ptm2ms");		/* Memory Size/Attribute */
-	if(NULL != ptmla_str && NULL != ptmms_str ) {
-		out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
-		out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
-	} else {
-		/* BAR2: default: 4MB FPGA */
-		out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
-		out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */
-	}
-
-	if (is_monarch()) {
-		/* BAR2: map FPGA registers behind system memory at 1GB */
-		pci_hose_write_config_dword(hose, 0,
-					    PCI_BASE_ADDRESS_2, 0x40000008);
-	}
-
-	/*
-	 * Set up Configuration registers
-	 */
-
-	/* Program the board's vendor id */
-	pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID,
-				   CONFIG_SYS_PCI_SUBSYS_VENDORID);
-
-	/* disabled for PMC405 backward compatibility */
-	/* Configure command register as bus master */
-	/* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
-
-
-	/* 240nS PCI clock */
-	pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
-
-	/* No error reporting */
-	pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
-
-	if (!is_monarch()) {
-		/* Program the board's subsystem id/classcode */
-		pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
-					   CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
-		pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
-					   CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
-
-		/* PCI configuration done: release ERREADY */
-		out_be32((void *)GPIO1_OR,
-			 in_be32((void *)GPIO1_OR) | GPIO1_PPC_EREADY);
-		out_be32((void *)GPIO1_TCR,
-			 in_be32((void *)GPIO1_TCR) | GPIO1_PPC_EREADY);
-	} else {
-		/* Program the board's subsystem id/classcode */
-		pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
-					   CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
-		pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
-					   CONFIG_SYS_PCI_CLASSCODE_MONARCH);
-	}
-
-	/* enable host configuration */
-	pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*
- * Override weak default pci_master_init()
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
-void pci_master_init(struct pci_controller *hose)
-{
-	/*
-	 * Only configure the master in monach mode
-	 */
-	if (is_monarch())
-		__pci_master_init(hose);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
-
-static void wait_for_pci_ready(void)
-{
-	if (!(in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY)) {
-		printf("PCI:   Waiting for EREADY (CTRL-C to skip) ... ");
-		while (1) {
-			if (ctrlc()) {
-				puts("abort\n");
-				break;
-			}
-			if (in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY) {
-				printf("done\n");
-				break;
-			}
-		}
-	}
-}
-
-/*
- * Override weak is_pci_host()
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- */
-#if defined(CONFIG_PCI)
-int is_pci_host(struct pci_controller *hose)
-{
-	char *s = getenv("pciscan");
-	if (s == NULL)
-		if (is_monarch()) {
-			wait_for_pci_ready();
-			return 1;
-		} else
-			return 0;
-	else if (!strcmp(s, "yes"))
-		return 1;
-
-	return 0;
-}
-#endif /* defined(CONFIG_PCI) */
-
-#ifdef CONFIG_RESET_PHY_R
-static int pmc440_setup_vsc8601(char *devname, int phy_addr,
-				unsigned short behavior, unsigned short method)
-{
-	/* adjust LED behavior */
-	if (miiphy_write(devname, phy_addr, 0x1f, 0x0001) != 0) {
-		printf("Phy%d: register write access failed\n", phy_addr);
-		return -1;
-	}
-
-	miiphy_write(devname, phy_addr, 0x11, 0x0010);
-	miiphy_write(devname, phy_addr, 0x11, behavior);
-	miiphy_write(devname, phy_addr, 0x10, method);
-	miiphy_write(devname, phy_addr, 0x1f, 0x0000);
-
-	return 0;
-}
-
-static int pmc440_setup_ksz9031(char *devname, int phy_addr)
-{
-	unsigned short id1, id2;
-
-	if (miiphy_read(devname, phy_addr, 2, &id1) ||
-	    miiphy_read(devname, phy_addr, 3, &id2)) {
-		printf("Phy%d: cannot read id\n", phy_addr);
-		return -1;
-	}
-
-	if ((id1 != 0x0022) || ((id2 & 0xfff0) != 0x1620)) {
-		printf("Phy%d: unexpected id\n", phy_addr);
-		return -1;
-	}
-
-	/* MMD 2.08: adjust tx_clk pad skew */
-	miiphy_write(devname, phy_addr, 0x0d, 2);
-	miiphy_write(devname, phy_addr, 0x0e, 8);
-	miiphy_write(devname, phy_addr, 0x0d, 0x4002);
-	miiphy_write(devname, phy_addr, 0x0e, 0xf | (0x17 << 5));
-
-	return 0;
-}
-
-void reset_phy(void)
-{
-	char *s;
-	unsigned short val_method, val_behavior;
-
-	if (gd->board_type < 4) {
-		/* special LED setup for NGCC/CANDES */
-		s = getenv("bd_type");
-		if (s && ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
-			val_method   = 0x0e0a;
-			val_behavior = 0x0cf2;
-		} else {
-			/* PMC440 standard type */
-			val_method   = 0x0e10;
-			val_behavior = 0x0cf0;
-		}
-
-		/* boards up to rev. 1.3 use Vitesse VSC8601 phys */
-		pmc440_setup_vsc8601("ppc_4xx_eth0", CONFIG_PHY_ADDR,
-				     val_method, val_behavior);
-		pmc440_setup_vsc8601("ppc_4xx_eth1", CONFIG_PHY1_ADDR,
-				     val_method, val_behavior);
-	} else {
-		/* rev. 1.4 uses a Micrel KSZ9031 */
-		pmc440_setup_ksz9031("ppc_4xx_eth0", CONFIG_PHY_ADDR);
-		pmc440_setup_ksz9031("ppc_4xx_eth1", CONFIG_PHY1_ADDR);
-	}
-}
-#endif
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-/*
- *  Input: <dev_addr> I2C address of EEPROM device to enable.
- *         <state>    -1: deliver current state
- *	               0: disable write
- *		       1: enable write
- *  Returns:          -1: wrong device address
- *                     0: dis-/en- able done
- *		     0/1: current state if <state> was -1.
- */
-int eeprom_write_enable(unsigned dev_addr, int state)
-{
-	if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
-	    (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
-		return -1;
-	} else {
-		switch (state) {
-		case 1:
-			/* Enable write access, clear bit GPIO_SINT2. */
-			out_be32((void *)GPIO0_OR,
-			      in_be32((void *)GPIO0_OR) & ~GPIO0_EP_EEP);
-			state = 0;
-			break;
-		case 0:
-			/* Disable write access, set bit GPIO_SINT2. */
-			out_be32((void *)GPIO0_OR,
-				 in_be32((void *)GPIO0_OR) | GPIO0_EP_EEP);
-			state = 0;
-			break;
-		default:
-			/* Read current status back. */
-			state = (0 == (in_be32((void *)GPIO0_OR)
-				       & GPIO0_EP_EEP));
-			break;
-		}
-	}
-	return state;
-}
-#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
-
-#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
-int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
-			   uchar *buffer, unsigned cnt)
-{
-	unsigned end = offset + cnt;
-	unsigned blk_off;
-	int rcode = 0;
-
-#if defined(CONFIG_SYS_EEPROM_WREN)
-	eeprom_write_enable(dev_addr, 1);
-#endif
-	/*
-	 * Write data until done or would cross a write page boundary.
-	 * We must write the address again when changing pages
-	 * because the address counter only increments within a page.
-	 */
-	while (offset < end) {
-		unsigned alen, len;
-		unsigned maxlen;
-		uchar addr[2];
-
-		blk_off = offset & 0xFF;	/* block offset */
-
-		addr[0] = offset >> 8;		/* block number */
-		addr[1] = blk_off;		/* block offset */
-		alen	= 2;
-		addr[0] |= dev_addr;		/* insert device address */
-
-		len = end - offset;
-
-#define	BOOT_EEPROM_PAGE_SIZE	   (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
-#define	BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
-
-		maxlen = BOOT_EEPROM_PAGE_SIZE -
-			BOOT_EEPROM_PAGE_OFFSET(blk_off);
-		if (maxlen > I2C_RXTX_LEN)
-			maxlen = I2C_RXTX_LEN;
-
-		if (len > maxlen)
-			len = maxlen;
-
-		if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
-			rcode = 1;
-
-		buffer += len;
-		offset += len;
-
-#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
-		udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
-#endif
-	}
-#if defined(CONFIG_SYS_EEPROM_WREN)
-	eeprom_write_enable(dev_addr, 0);
-#endif
-	return rcode;
-}
-
-static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
-				 uchar *buffer, unsigned cnt)
-{
-	unsigned end = offset + cnt;
-	unsigned blk_off;
-	int rcode = 0;
-
-	/*
-	 * Read data until done or would cross a page boundary.
-	 * We must write the address again when changing pages
-	 * because the next page may be in a different device.
-	 */
-	while (offset < end) {
-		unsigned alen, len;
-		unsigned maxlen;
-		uchar addr[2];
-
-		blk_off = offset & 0xFF;	/* block offset */
-
-		addr[0] = offset >> 8;		/* block number */
-		addr[1] = blk_off;		/* block offset */
-		alen	= 2;
-
-		addr[0] |= dev_addr;		/* insert device address */
-
-		len = end - offset;
-
-		maxlen = 0x100 - blk_off;
-		if (maxlen > I2C_RXTX_LEN)
-			maxlen = I2C_RXTX_LEN;
-		if (len > maxlen)
-			len = maxlen;
-
-		if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
-			rcode = 1;
-		buffer += len;
-		offset += len;
-	}
-
-	return rcode;
-}
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
-int board_usb_init(int index, enum usb_init_type init)
-{
-	char *act = getenv("usbact");
-	int i;
-
-	if ((act == NULL || strcmp(act, "host") == 0) &&
-	    !(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT))
-		/* enable power on USB socket */
-		out_be32((void *)GPIO1_OR,
-			 in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
-
-	for (i=0; i<1000; i++)
-		udelay(1000);
-
-	return 0;
-}
-
-int usb_board_stop(void)
-{
-	/* disable power on USB socket */
-	out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) | GPIO1_USB_PWR_N);
-	return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	return usb_board_stop();
-}
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	int rc;
-
-	__ft_board_setup(blob, bd);
-
-	/*
-	 * Disable PCI in non-monarch mode.
-	 */
-	if (!is_monarch()) {
-		rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
-					  "disabled", sizeof("disabled"), 1);
-		if (rc) {
-			printf("Unable to update property status in PCI node, ");
-			printf("err=%s\n", fdt_strerror(rc));
-		}
-	}
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h
deleted file mode 100644
index 84e0b1f..0000000
--- a/board/esd/pmc440/pmc440.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __PMC440_H__
-#define __PMC440_H__
-
-/*
- * GPIOs
- */
-#define GPIO1_INTA_FAKE           (0x80000000 >> (45-32)) /* GPIO45 OD */
-#define GPIO1_NONMONARCH          (0x80000000 >> (63-32)) /* GPIO63 I */
-#define GPIO1_PPC_EREADY          (0x80000000 >> (62-32)) /* GPIO62 I/O */
-#define GPIO1_M66EN               (0x80000000 >> (61-32)) /* GPIO61 I */
-#define GPIO1_POST_N              (0x80000000 >> (60-32)) /* GPIO60 O */
-#define GPIO1_IOEN_N              (0x80000000 >> (50-32)) /* GPIO50 O */
-#define GPIO1_HWID_MASK           (0xf0000000 >> (56-32)) /* GPIO56..59 I */
-
-#define GPIO1_USB_PWR_N           (0x80000000 >> (32-32)) /* GPIO32 I */
-#define GPIO0_LED_RUN_N           (0x80000000 >> 30)      /* GPIO30 O */
-#define GPIO0_EP_EEP              (0x80000000 >> 23)      /* GPIO23 O */
-#define GPIO0_USB_ID              (0x80000000 >> 21)      /* GPIO21 I */
-#define GPIO0_USB_PRSNT           (0x80000000 >> 20)      /* GPIO20 I */
-
-/*
- * FPGA programming pin configuration
- */
-#define GPIO1_FPGA_PRG            (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */
-#define GPIO1_FPGA_CLK            (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output)     */
-#define GPIO1_FPGA_DATA           (0x80000000 >> (52-32)) /* FPGA data pin (ppc output)    */
-#define GPIO1_FPGA_DONE           (0x80000000 >> (55-32)) /* FPGA done pin (ppc input)     */
-#define GPIO1_FPGA_INIT           (0x80000000 >> (54-32)) /* FPGA init pin (ppc input)     */
-#define GPIO0_FPGA_FORCEINIT      (0x80000000 >> 27)      /* low: force INIT# low */
-
-/*
- * FPGA interface
- */
-#define FPGA_BA CONFIG_SYS_FPGA_BASE0
-#define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v))
-#define FPGA_IN32(p) in_be32((void*)(p))
-#define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v))
-#define FPGA_CLRBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) & ~(v))
-
-struct pmc440_fifo_s {
-	u32 data;
-	u32 ctrl;
-};
-
-/* fifo ctrl register */
-#define FIFO_IE              (1 << 15)
-#define FIFO_OVERFLOW        (1 << 10)
-#define FIFO_EMPTY           (1 <<  9)
-#define FIFO_FULL            (1 <<  8)
-#define FIFO_LEVEL_MASK      0x000000ff
-
-#define FIFO_COUNT           4
-
-struct pmc440_fpga_s {
-	u32 ctrla;
-	u32 status;
-	u32 ctrlb;
-	u32 pad1[0x40 / sizeof(u32) - 3];
-	u32 irig_time;                  /* offset: 0x0040 */
-	u32 irig_tod;
-	u32 irig_cf;
-	u32 pad2;
-	u32 irig_rx_time;               /* offset: 0x0050 */
-	u32 pad3[3];
-	u32 hostctrl;                   /* offset: 0x0060 */
-	u32 pad4[0x20 / sizeof(u32) - 1];
-	struct pmc440_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */
-};
-
-typedef struct pmc440_fpga_s pmc440_fpga_t;
-
-/* ctrl register */
-#define CTRL_HOST_IE         (1 <<  8)
-
-/* outputs */
-#define RESET_EN    (1 << 31)
-#define CLOCK_EN    (1 << 30)
-#define RESET_OUT   (1 << 19)
-#define CLOCK_OUT   (1 << 22)
-#define RESET_OUT   (1 << 19)
-#define IRIGB_R_OUT (1 << 14)
-
-/* status register */
-#define STATUS_VERSION_SHIFT 24
-#define STATUS_VERSION_MASK  0xff000000
-#define STATUS_HWREV_SHIFT   20
-#define STATUS_HWREV_MASK    0x00f00000
-
-#define STATUS_CAN_ISF       (1 << 11)
-#define STATUS_CSTM_ISF      (1 << 10)
-#define STATUS_FIFO_ISF      (1 <<  9)
-#define STATUS_HOST_ISF      (1 <<  8)
-
-/* inputs */
-#define RESET_IN    (1 << 0)
-#define CLOCK_IN    (1 << 1)
-#define IRIGB_R_IN  (1 << 5)
-
-/* hostctrl register */
-#define HOSTCTRL_PMCRSTOUT_GATE (1 <<  17)
-#define HOSTCTRL_PMCRSTOUT_FLAG (1 <<  16)
-#define HOSTCTRL_CSTM1IE_GATE (1 <<  7)
-#define HOSTCTRL_CSTM1IW_FLAG (1 <<  6)
-#define HOSTCTRL_CSTM0IE_GATE (1 <<  5)
-#define HOSTCTRL_CSTM0IW_FLAG (1 <<  4)
-#define HOSTCTRL_FIFOIE_GATE (1 <<  3)
-#define HOSTCTRL_FIFOIE_FLAG (1 <<  2)
-#define HOSTCTRL_HCINT_GATE  (1 <<  1)
-#define HOSTCTRL_HCINT_FLAG  (1 <<  0)
-
-#define NGCC_CTRL_BASE         (CONFIG_SYS_FPGA_BASE0 + 0x80000)
-#define NGCC_CTRL_FPGARST_N    (1 <<  2)
-
-/*
- * FPGA to PPC interrupt
- */
-#define IRQ0_FPGA            (32+28) /* UIC1 - FPGA internal */
-#define IRQ1_FPGA            (32+30) /* UIC1 - custom module */
-#define IRQ2_FPGA            (64+ 3) /* UIC2 - custom module / CAN */
-#define IRQ_ETH0             (64+ 4) /* UIC2 */
-#define IRQ_ETH1             (   27) /* UIC0 */
-#define IRQ_RTC              (64+ 0) /* UIC2 */
-#define IRQ_PCIA             (64+ 1) /* UIC2 */
-#define IRQ_PCIB             (32+18) /* UIC1 */
-#define IRQ_PCIC             (32+19) /* UIC1 */
-#define IRQ_PCID             (32+20) /* UIC1 */
-
-#endif /* __PMC440_H__ */
diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c
deleted file mode 100644
index e7f8115..0000000
--- a/board/esd/pmc440/sdram.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * (C) Copyright 2009
- * Matthias Fuchs, esd gmbh, matthias.fuchs@esd.eu
- *
- * (C) Copyright 2006
- * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* define DEBUG for debug output */
-#undef DEBUG
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/ppc440.h>
-
-extern int denali_wait_for_dlllock(void);
-extern void denali_core_search_data_eye(void);
-
-struct sdram_conf_s {
-	ulong size;
-	int rows;
-	int banks;
-};
-
-struct sdram_conf_s sdram_conf[] = {
-	{(1024 << 20), 14, 8}, /* 1GByte: 4x2GBit, 14x10, 8 banks */
-	{(512 << 20),  13, 8}, /* 512MByte: 4x1GBit, 13x10, 8 banks */
-	{(256 << 20),  13, 4}, /* 256MByte: 4x512MBit, 13x10, 4 banks */
-};
-
-/*
- * initdram -- 440EPx's DDR controller is a DENALI Core
- */
-int initdram_by_rb(int rows, int banks)
-{
-	ulong speed = get_bus_freq(0);
-
-	mtsdram(DDR0_02, 0x00000000);
-
-	mtsdram(DDR0_00, 0x0000190A);
-	mtsdram(DDR0_01, 0x01000000);
-	mtsdram(DDR0_03, 0x02030602);
-	mtsdram(DDR0_04, 0x0A020200);
-	mtsdram(DDR0_05, 0x02020308);
-	mtsdram(DDR0_06, 0x0102C812);
-	mtsdram(DDR0_07, 0x000D0100);
-	mtsdram(DDR0_08, 0x02430001);
-	mtsdram(DDR0_09, 0x00011D5F);
-	mtsdram(DDR0_10, 0x00000100);
-	mtsdram(DDR0_11, 0x0027C800);
-	mtsdram(DDR0_12, 0x00000003);
-	mtsdram(DDR0_14, 0x00000000);
-	mtsdram(DDR0_17, 0x19000000);
-	mtsdram(DDR0_18, 0x19191919);
-	mtsdram(DDR0_19, 0x19191919);
-	mtsdram(DDR0_20, 0x0B0B0B0B);
-	mtsdram(DDR0_21, 0x0B0B0B0B);
-	mtsdram(DDR0_22, 0x00267F0B);
-	mtsdram(DDR0_23, 0x00000000);
-	mtsdram(DDR0_24, 0x01010002);
-	if (speed > 133333334)
-		mtsdram(DDR0_26, 0x5B26050C);
-	else
-		mtsdram(DDR0_26, 0x5B260408);
-	mtsdram(DDR0_27, 0x0000682B);
-	mtsdram(DDR0_28, 0x00000000);
-	mtsdram(DDR0_31, 0x00000000);
-
-	mtsdram(DDR0_42,
-		DDR0_42_ADDR_PINS_DECODE(14 - rows) |
-		0x00000006);
-	mtsdram(DDR0_43,
-		DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) |
-		0x030A0200);
-
-	mtsdram(DDR0_44, 0x00000003);
-	mtsdram(DDR0_02, 0x00000001);
-
-	denali_wait_for_dlllock();
-
-#ifdef CONFIG_DDR_DATA_EYE
-	/*
-	 * Perform data eye search if requested.
-	 */
-	denali_core_search_data_eye();
-#endif
-	/*
-	 * Clear possible errors resulting from data-eye-search.
-	 * If not done, then we could get an interrupt later on when
-	 * exceptions are enabled.
-	 */
-	set_mcsr(get_mcsr());
-
-	return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
-	phys_size_t size;
-	int n;
-
-	/* go through supported memory configurations */
-	for (n = 0; n < ARRAY_SIZE(sdram_conf); n++) {
-		size = sdram_conf[n].size;
-
-		/* program TLB entries */
-		program_tlb(0, CONFIG_SYS_SDRAM_BASE, size,
-			    TLB_WORD2_I_ENABLE);
-
-		/*
-		 * setup denali core
-		 */
-		initdram_by_rb(sdram_conf[n].rows,
-			       sdram_conf[n].banks);
-
-		/* check for suitable configuration */
-		if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size)
-			return size;
-
-		/* delete TLB entries */
-		remove_tlb(CONFIG_SYS_SDRAM_BASE, size);
-	}
-
-	return 0;
-}
diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c
index f8f1834..36a5519 100644
--- a/board/esd/vme8349/vme8349.c
+++ b/board/esd/vme8349/vme8349.c
@@ -26,15 +26,17 @@
 #include <i2c.h>
 #include <netdev.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void ddr_enable_ecc(unsigned int dram_size);
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main memory */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
@@ -52,7 +54,9 @@ phys_size_t initdram(int board_type)
 	msize = get_ram_size(0, msize);
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize * 1024 * 1024;
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/esd/vom405/Kconfig b/board/esd/vom405/Kconfig
deleted file mode 100644
index ecdf8c9..0000000
--- a/board/esd/vom405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_VOM405
-
-config SYS_BOARD
-	default "vom405"
-
-config SYS_VENDOR
-	default "esd"
-
-config SYS_CONFIG_NAME
-	default "VOM405"
-
-endif
diff --git a/board/esd/vom405/MAINTAINERS b/board/esd/vom405/MAINTAINERS
deleted file mode 100644
index 385f60a..0000000
--- a/board/esd/vom405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-VOM405 BOARD
-M:	Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S:	Maintained
-F:	board/esd/vom405/
-F:	include/configs/VOM405.h
-F:	configs/VOM405_defconfig
diff --git a/board/esd/vom405/Makefile b/board/esd/vom405/Makefile
deleted file mode 100644
index 7cf5c02..0000000
--- a/board/esd/vom405/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Objects for Xilinx JTAG programming (CPLD)
-CPLD    = ../common/xilinx_jtag/lenval.o \
-	  ../common/xilinx_jtag/micro.o \
-	  ../common/xilinx_jtag/ports.o
-
-obj-y	= vom405.o flash.o ../common/misc.o $(CPLD)
diff --git a/board/esd/vom405/flash.c b/board/esd/vom405/flash.c
deleted file mode 100644
index 23e8164..0000000
--- a/board/esd/vom405/flash.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	unsigned long size_b0;
-	int i;
-	uint pbcr;
-	unsigned long base_b0;
-	int size_val = 0;
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
-	}
-
-	/* Setup offsets */
-	flash_get_offsets (-size_b0, &flash_info[0]);
-
-	/* Re-do sizing to get full correct info */
-	mtdcr(EBC0_CFGADDR, PB0CR);
-	pbcr = mfdcr(EBC0_CFGDATA);
-	mtdcr(EBC0_CFGADDR, PB0CR);
-	base_b0 = -size_b0;
-	switch (size_b0) {
-	case 1 << 20:
-		size_val = 0;
-		break;
-	case 2 << 20:
-		size_val = 1;
-		break;
-	case 4 << 20:
-		size_val = 2;
-		break;
-	case 8 << 20:
-		size_val = 3;
-		break;
-	case 16 << 20:
-		size_val = 4;
-		break;
-	}
-	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
-	mtdcr(EBC0_CFGDATA, pbcr);
-
-	/* Monitor protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CONFIG_SYS_MONITOR_LEN,
-			    0xffffffff,
-			    &flash_info[0]);
-
-	flash_info[0].size = size_b0;
-
-	return (size_b0);
-}
diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c
deleted file mode 100644
index 7de6f66..0000000
--- a/board/esd/vom405/vom405.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-#include <sja1000.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void lxt971_no_sleep(void);
-
-/*
- * generate a short spike on the CAN tx line
- * to bring the couplers in sync
- */
-void init_coupler(u32 addr)
-{
-	struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
-
-	/* reset */
-	out_8(&ctrl->cr, CR_RR);
-
-	/* dominant */
-	out_8(&ctrl->btr0, 0x00); /* btr setup is required */
-	out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
-	out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
-	      OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
-	out_8(&ctrl->cr, 0x00);
-
-	/* delay */
-	in_8(&ctrl->cr);
-	in_8(&ctrl->cr);
-	in_8(&ctrl->cr);
-	in_8(&ctrl->cr);
-
-	/* reset */
-	out_8(&ctrl->cr, CR_RR);
-}
-
-int board_early_init_f (void)
-{
-	/*
-	 * IRQ 0-15  405GP internally generated; active high; level sensitive
-	 * IRQ 16    405GP internally generated; active low; level sensitive
-	 * IRQ 17-24 RESERVED
-	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
-	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
-	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
-	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
-	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
-	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
-	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
-	 */
-	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
-	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
-	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
-	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
-
-	/*
-	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
-	 */
-	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-
-	/*
-	 * Reset CPLD via GPIO12 (CS3) pin
-	 */
-	out_be32((void *)GPIO0_OR,
-		 in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 12));
-	udelay(1000); /* wait 1ms */
-	out_be32((void *)GPIO0_OR,
-		 in_be32((void *)GPIO0_OR) | (0x80000000 >> 12));
-	udelay(1000); /* wait 1ms */
-
-	return 0;
-}
-
-int misc_init_r (void)
-{
-	/* adjust flash start and offset */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-	gd->bd->bi_flashoffset = 0;
-
-	/*
-	 * Init magnetic coupler
-	 */
-	if (!getenv("noinitcoupler"))
-		init_coupler(CAN_BA);
-
-	return (0);
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
-	char str[64];
-	int i = getenv_f("serial#", str, sizeof(str));
-	int flashcnt;
-	int delay;
-	u8 *led_reg = (u8 *)(CAN_BA + 0x1000);
-
-	puts ("Board: ");
-
-	if (i == -1) {
-		puts ("### No HW ID - assuming VOM405");
-	} else {
-		puts(str);
-	}
-
-	printf(" (PLD-Version=%02d)\n", in_8(led_reg));
-
-	/*
-	 * Flash LEDs
-	 */
-	for (flashcnt = 0; flashcnt < 3; flashcnt++) {
-		out_8(led_reg, 0x40);        /* LED_B..D off */
-		for (delay = 0; delay < 100; delay++)
-			udelay(1000);
-		out_8(led_reg, 0x47);        /* LED_B..D on */
-		for (delay = 0; delay < 50; delay++)
-			udelay(1000);
-	}
-	out_8(led_reg, 0x40);
-
-	return 0;
-}
-
-void reset_phy(void)
-{
-#ifdef CONFIG_LXT971_NO_SLEEP
-
-	/*
-	 * Disable sleep mode in LXT971
-	 */
-	lxt971_no_sleep();
-#endif
-}
diff --git a/board/espt/Makefile b/board/espt/Makefile
index 8a8a2c9..f24e9cf 100644
--- a/board/espt/Makefile
+++ b/board/espt/Makefile
@@ -8,4 +8,4 @@
 #
 
 obj-y	:= espt.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/espt/espt.c b/board/espt/espt.c
index ee6e538..9ab71fe 100644
--- a/board/espt/espt.c
+++ b/board/espt/espt.c
@@ -11,8 +11,6 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 int checkboard(void)
 {
 	puts("BOARD: ESPT-GIGA\n");
@@ -24,14 +22,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-	return 0;
-}
-
 void led_set_state(unsigned short value)
 {
 }
diff --git a/board/freescale/b4860qds/Kconfig b/board/freescale/b4860qds/Kconfig
index c7aab75..9bb667a 100644
--- a/board/freescale/b4860qds/Kconfig
+++ b/board/freescale/b4860qds/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_B4860QDS
+if TARGET_B4860QDS || TARGET_B4420QDS
 
 config SYS_BOARD
 	default "b4860qds"
@@ -9,4 +9,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "B4860QDS"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/b4860qds/MAINTAINERS b/board/freescale/b4860qds/MAINTAINERS
index 97304c5..34ac099 100644
--- a/board/freescale/b4860qds/MAINTAINERS
+++ b/board/freescale/b4860qds/MAINTAINERS
@@ -1,5 +1,5 @@
 B4860QDS BOARD
-#M:	-
+M:	Ashish Kumar <ashish.kumar@nxp.com>
 S:	Maintained
 F:	board/freescale/b4860qds/
 F:	include/configs/B4860QDS.h
diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile
index 673d2ea..c032242 100644
--- a/board/freescale/b4860qds/Makefile
+++ b/board/freescale/b4860qds/Makefile
@@ -8,7 +8,8 @@ ifdef CONFIG_SPL_BUILD
 obj-y	+= spl.o
 else
 obj-y	+= b4860qds.o
-obj-$(CONFIG_B4860QDS)	+= eth_b4860qds.o
+obj-$(CONFIG_TARGET_B4860QDS)	+= eth_b4860qds.o
+obj-$(CONFIG_TARGET_B4420QDS)	+= eth_b4860qds.o
 obj-$(CONFIG_PCI)	+= pci.o
 endif
 
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index e582abb..83a7015 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -11,7 +11,7 @@
 #include <linux/compiler.h>
 #include <asm/mmu.h>
 #include <asm/processor.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_law.h>
@@ -437,7 +437,7 @@ int configure_vsc3316_3308(void)
 		}
 		break;
 
-#ifdef CONFIG_PPC_B4420
+#ifdef CONFIG_ARCH_B4420
 	case 0x17:
 	case 0x18:
 			/*
@@ -496,7 +496,7 @@ int configure_vsc3316_3308(void)
 	/* Configure VSC3308 crossbar switch */
 	ret = select_i2c_ch_pca(I2C_CH_VSC3308);
 	switch (serdes2_prtcl) {
-#ifdef CONFIG_PPC_B4420
+#ifdef CONFIG_ARCH_B4420
 	case 0x9d:
 #endif
 	case 0x9E:
@@ -929,7 +929,7 @@ int config_serdes2_refclks(void)
 	 * For this SerDes2's Refclk1 need to be set to 100MHz
 	 */
 	switch (serdes2_prtcl) {
-#ifdef CONFIG_PPC_B4420
+#ifdef CONFIG_ARCH_B4420
 	case 0x9d:
 #endif
 	case 0x9E:
@@ -1209,7 +1209,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_liodn(blob);
 
 #ifdef CONFIG_HAS_FSL_DR_USB
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h
index fcccb8f..901f8b0 100644
--- a/board/freescale/b4860qds/b4860qds_crossbar_con.h
+++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h
@@ -28,7 +28,7 @@ static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
 				{7, 8}, {9, 0}, {5, 14},
 				{4, 15}, {2, 12}, {12, 13} };
 
-#ifdef CONFIG_PPC_B4420
+#ifdef CONFIG_ARCH_B4420
 static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
 		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 #endif
@@ -54,7 +54,7 @@ static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1},
 				{7, 8}, {1, 9}, {14, 11},
 				{15, 10}, {13, 3}, {12, 12} };
 
-#ifdef CONFIG_PPC_B4420
+#ifdef CONFIG_ARCH_B4420
 static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
 		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
 #endif
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index 31b186e..5cc2f73 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -171,9 +171,12 @@ found:
 	/* DHC_EN =1, ODT = 75 Ohm */
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x3e;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -186,7 +189,9 @@ phys_size_t initdram(int board_type)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
@@ -210,7 +215,7 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
 
 		debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
 		      rank_density, ctlr_density);
-		for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
+		for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
 			switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
 			case FSL_DDR_CACHE_LINE_INTERLEAVING:
 			case FSL_DDR_PAGE_INTERLEAVING:
@@ -234,7 +239,7 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
 		 * Simple linear assignment if memory
 		 * controllers are not interleaved.
 		 */
-		for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
+		for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
 			total_ctlr_mem = 0;
 			pinfo->common_timing_params[i].base_address =
 						current_mem_base;
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index 164ec0a..89a1883 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -213,7 +213,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC6,
 				CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
 		break;
-#ifdef CONFIG_PPC_B4420
+#ifdef CONFIG_ARCH_B4420
 	case 0x17:
 	case 0x18:
 		/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c
index fabc783..60d7f0d 100644
--- a/board/freescale/b4860qds/spl.c
+++ b/board/freescale/b4860qds/spl.c
@@ -87,7 +87,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
 	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
-	probecpu();
+	arch_cpu_init();
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
@@ -108,7 +108,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	puts("\n\n");
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	nand_boot();
diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c
index 75e1142..fb8bb39 100644
--- a/board/freescale/bsc9131rdb/bsc9131rdb.c
+++ b/board/freescale/bsc9131rdb/bsc9131rdb.c
@@ -73,7 +73,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 #endif
 
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 
 	return 0;
 }
diff --git a/board/freescale/bsc9132qds/Kconfig b/board/freescale/bsc9132qds/Kconfig
index db3a1f1..e5499e6 100644
--- a/board/freescale/bsc9132qds/Kconfig
+++ b/board/freescale/bsc9132qds/Kconfig
@@ -9,4 +9,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "BSC9132QDS"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
index 71a7bb5..a7772c4 100644
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -151,7 +151,7 @@ void dsp_ddr_configure(void)
 
 int board_early_init_r(void)
 {
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 
@@ -394,7 +394,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 			/* remove dts usb node */
 			fdt_del_node_compat(blob, "fsl-usb2-dr");
 		} else {
-			fdt_fixup_dr_usb(blob, bd);
+			fsl_fdt_fixup_dr_usb(blob, bd);
 			fdt_del_node_and_alias(blob, "serial2");
 		}
 	}
diff --git a/board/freescale/c29xpcie/Kconfig b/board/freescale/c29xpcie/Kconfig
index 17369b8..51e25c3 100644
--- a/board/freescale/c29xpcie/Kconfig
+++ b/board/freescale/c29xpcie/Kconfig
@@ -9,4 +9,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "C29XPCIE"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
index d8d73c7..94093f1 100644
--- a/board/freescale/c29xpcie/spl.c
+++ b/board/freescale/c29xpcie/spl.c
@@ -53,7 +53,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
 	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
 
-	probecpu();
+	arch_cpu_init();
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
@@ -67,7 +67,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("TPL\n");
diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig
new file mode 100644
index 0000000..8a5c456
--- /dev/null
+++ b/board/freescale/common/Kconfig
@@ -0,0 +1,20 @@
+config CHAIN_OF_TRUST
+	depends on !FIT_SIGNATURE && SECURE_BOOT
+	imply CMD_BLOB
+	imply CMD_HASH if ARM
+	select FSL_CAAM
+	select SPL_BOARD_INIT if (ARM && SPL)
+	select SHA_HW_ACCEL
+	select SHA_PROG_HW_ACCEL
+	select ENV_IS_NOWHERE
+	bool
+	default y
+
+config CMD_ESBC_VALIDATE
+	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
+	default y if CHAIN_OF_TRUST
+	help
+	  This option enables two commands used for secure booting:
+
+	    esbc_validate - validate signature using RSA verification
+	    esbc_halt - put the core in spin loop (Secure Boot Only)
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index be114ce..1c53fb6 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -45,31 +45,32 @@ endif
 
 obj-$(CONFIG_FSL_DCU_SII9022A)    += dcu_sii9022a.o
 
-obj-$(CONFIG_MPC8541CDS)	+= cds_pci_ft.o
-obj-$(CONFIG_MPC8548CDS)	+= cds_pci_ft.o
-obj-$(CONFIG_MPC8555CDS)	+= cds_pci_ft.o
+obj-$(CONFIG_TARGET_MPC8541CDS)	+= cds_pci_ft.o
+obj-$(CONFIG_TARGET_MPC8548CDS)	+= cds_pci_ft.o
+obj-$(CONFIG_TARGET_MPC8555CDS)	+= cds_pci_ft.o
 
-obj-$(CONFIG_MPC8536DS)	+= ics307_clk.o
-obj-$(CONFIG_MPC8572DS)	+= ics307_clk.o
-obj-$(CONFIG_P1022DS)		+= ics307_clk.o
+obj-$(CONFIG_TARGET_MPC8536DS)	+= ics307_clk.o
+obj-$(CONFIG_TARGET_MPC8572DS)	+= ics307_clk.o
+obj-$(CONFIG_TARGET_P1022DS)		+= ics307_clk.o
 obj-$(CONFIG_P2020DS)		+= ics307_clk.o
-obj-$(CONFIG_P3041DS)		+= ics307_clk.o
-obj-$(CONFIG_P4080DS)		+= ics307_clk.o
-obj-$(CONFIG_P5020DS)		+= ics307_clk.o
-obj-$(CONFIG_P5040DS)		+= ics307_clk.o
+obj-$(CONFIG_TARGET_P3041DS)		+= ics307_clk.o
+obj-$(CONFIG_TARGET_P4080DS)		+= ics307_clk.o
+obj-$(CONFIG_TARGET_P5020DS)		+= ics307_clk.o
+obj-$(CONFIG_TARGET_P5040DS)		+= ics307_clk.o
 obj-$(CONFIG_VSC_CROSSBAR)    += vsc3316_3308.o
 obj-$(CONFIG_IDT8T49N222A)	+= idt8t49n222a_serdes_clk.o
 obj-$(CONFIG_ZM7300)		+= zm7300.o
 obj-$(CONFIG_POWER_PFUZE100)	+= pfuze.o
+obj-$(CONFIG_POWER_MC34VR500)	+= mc34vr500.o
 
 obj-$(CONFIG_LS102XA_STREAM_ID)	+= ls102xa_stream_id.o
 
 # deal with common files for P-series corenet based devices
-obj-$(CONFIG_P2041RDB)	+= p_corenet/
-obj-$(CONFIG_P3041DS)	+= p_corenet/
-obj-$(CONFIG_P4080DS)	+= p_corenet/
-obj-$(CONFIG_P5020DS)	+= p_corenet/
-obj-$(CONFIG_P5040DS)	+= p_corenet/
+obj-$(CONFIG_TARGET_P2041RDB)	+= p_corenet/
+obj-$(CONFIG_TARGET_P3041DS)	+= p_corenet/
+obj-$(CONFIG_TARGET_P4080DS)	+= p_corenet/
+obj-$(CONFIG_TARGET_P5020DS)	+= p_corenet/
+obj-$(CONFIG_TARGET_P5040DS)	+= p_corenet/
 
 obj-$(CONFIG_LAYERSCAPE_NS_ACCESS)	+= ns_access.o
 
diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c
index 16fd445..6ed5d9e 100644
--- a/board/freescale/common/arm_sleep.c
+++ b/board/freescale/common/arm_sleep.c
@@ -13,7 +13,7 @@
 #endif
 #include <asm/armv7.h>
 
-#if defined(CONFIG_LS102XA)
+#if defined(CONFIG_ARCH_LS1021A)
 #include <asm/arch/immap_ls102xa.h>
 #endif
 
@@ -66,7 +66,7 @@ static void dp_ddr_restore(void)
 		*dst++ = *src++;
 }
 
-#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_LS102XA)
+#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A)
 void ls1_psci_resume_fixup(void)
 {
 	u32 tmp;
@@ -104,7 +104,7 @@ static void dp_resume_prepare(void)
 #ifdef CONFIG_U_QE
 	u_qe_resume();
 #endif
-#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_LS102XA)
+#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A)
 	ls1_psci_resume_fixup();
 #endif
 }
diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index dea231b..dfe5d20 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <fsl_validate.h>
 #include <fsl_secboot_err.h>
 #include <fsl_sfp.h>
@@ -22,7 +23,7 @@
 #include <asm/fsl_pamu.h>
 #endif
 
-#ifdef CONFIG_LS102XA
+#ifdef CONFIG_ARCH_LS1021A
 #include <asm/arch/immap_ls102xa.h>
 #endif
 
@@ -80,7 +81,13 @@ int fsl_setenv_chain_of_trust(void)
 	 * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
 	 */
 	setenv("bootdelay", "0");
+
+#ifdef CONFIG_ARM
+	setenv("secureboot", "y");
+#else
 	setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD);
+#endif
+
 	return 0;
 }
 #endif
@@ -151,7 +158,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 	 * may return back in case of non-fatal failures.
 	 */
 
-	debug("image entry point: 0x%X\n", spl_image->entry_point);
+	debug("image entry point: 0x%lX\n", spl_image->entry_point);
 	image_entry();
 }
 #endif /* ifdef CONFIG_SPL_FRAMEWORK */
diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index 8c171b1..ef93407 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -5,17 +5,17 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <fsl_validate.h>
 #include <fsl_secboot_err.h>
 #include <fsl_sfp.h>
 #include <fsl_sec.h>
 #include <command.h>
 #include <malloc.h>
-#include <dm/uclass.h>
 #include <u-boot/rsa-mod-exp.h>
 #include <hash.h>
 #include <fsl_secboot_err.h>
-#ifdef CONFIG_LS102XA
+#ifdef CONFIG_ARCH_LS1021A
 #include <asm/arch/immap_ls102xa.h>
 #endif
 
@@ -27,6 +27,10 @@
 #define CHECK_KEY_LEN(key_len)	(((key_len) == 2 * KEY_SIZE_BYTES / 4) || \
 				 ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \
 				 ((key_len) == 2 * KEY_SIZE_BYTES))
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+/* Global data structure */
+static struct fsl_secboot_glb glb;
+#endif
 
 /* This array contains DER value for SHA-256 */
 static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
@@ -60,7 +64,7 @@ self:
 #if defined(CONFIG_FSL_ISBC_KEY_EXT)
 static u32 check_ie(struct fsl_secboot_img_priv *img)
 {
-	if (img->hdr.ie_flag)
+	if (img->hdr.ie_flag & IE_FLAG_MASK)
 		return 1;
 
 	return 0;
@@ -119,7 +123,21 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
 }
 #endif
 
-static int get_ie_info_addr(u32 *ie_addr)
+#if defined(CONFIG_ESBC_HDR_LS)
+static int get_ie_info_addr(uintptr_t *ie_addr)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	/* For LS-CH3, the address of IE Table is
+	 * stated in Scratch13 and scratch14 of DCFG.
+	 * Bootrom validates this table while validating uboot.
+	 * DCFG is LE*/
+	*ie_addr = in_le32(&gur->scratchrw[SCRATCH_IE_HIGH_ADR - 1]);
+	*ie_addr = *ie_addr << 32;
+	*ie_addr |= in_le32(&gur->scratchrw[SCRATCH_IE_LOW_ADR - 1]);
+	return 0;
+}
+#else /* CONFIG_ESBC_HDR_LS */
+static int get_ie_info_addr(uintptr_t *ie_addr)
 {
 	struct fsl_secboot_img_hdr *hdr;
 	struct fsl_secboot_sg_table *sg_tbl;
@@ -147,16 +165,17 @@ static int get_ie_info_addr(u32 *ie_addr)
 
 	/* IE Key Table is the first entry in the SG Table */
 #if defined(CONFIG_MPC85xx)
-	*ie_addr = (sg_tbl->src_addr & ~(CONFIG_SYS_PBI_FLASH_BASE)) +
-		   flash_base_addr;
+	*ie_addr = (uintptr_t)((sg_tbl->src_addr &
+			~(CONFIG_SYS_PBI_FLASH_BASE)) +
+			flash_base_addr);
 #else
-	*ie_addr = sg_tbl->src_addr;
+	*ie_addr = (uintptr_t)sg_tbl->src_addr;
 #endif
 
-	debug("IE Table address is %x\n", *ie_addr);
+	debug("IE Table address is %lx\n", *ie_addr);
 	return 0;
 }
-
+#endif /* CONFIG_ESBC_HDR_LS */
 #endif
 
 #ifdef CONFIG_KEY_REVOCATION
@@ -164,7 +183,10 @@ static int get_ie_info_addr(u32 *ie_addr)
 static u32 check_srk(struct fsl_secboot_img_priv *img)
 {
 #ifdef CONFIG_ESBC_HDR_LS
-	/* In LS, No SRK Flag as SRK is always present*/
+	/* In LS, No SRK Flag as SRK is always present if IE not present*/
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+	return !check_ie(img);
+#endif
 	return 1;
 #else
 	if (img->hdr.len_kr.srk_table_flag & SRK_FLAG)
@@ -253,14 +275,29 @@ static u32 read_validate_single_key(struct fsl_secboot_img_priv *img)
 #endif /* CONFIG_ESBC_HDR_LS */
 
 #if defined(CONFIG_FSL_ISBC_KEY_EXT)
+
+static void install_ie_tbl(uintptr_t ie_tbl_addr,
+		struct fsl_secboot_img_priv *img)
+{
+	/* Copy IE tbl to Global Data */
+	memcpy(&glb.ie_tbl, (u8 *)ie_tbl_addr, sizeof(struct ie_key_info));
+	img->ie_addr = (uintptr_t)&glb.ie_tbl;
+	glb.ie_addr = img->ie_addr;
+}
+
 static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img)
 {
 	struct fsl_secboot_img_hdr *hdr = &img->hdr;
 	u32 ie_key_len, ie_revoc_flag, ie_num;
 	struct ie_key_info *ie_info;
 
-	if (get_ie_info_addr(&img->ie_addr))
-		return ERROR_IE_TABLE_NOT_FOUND;
+	if (!img->ie_addr) {
+		if (get_ie_info_addr(&img->ie_addr))
+			return ERROR_IE_TABLE_NOT_FOUND;
+		else
+			install_ie_tbl(img->ie_addr, img);
+		}
+
 	ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr;
 	if (ie_info->num_keys == 0 || ie_info->num_keys > 32)
 		return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY;
@@ -301,27 +338,15 @@ static inline u32 get_key_len(struct fsl_secboot_img_priv *img)
  */
 static void fsl_secboot_header_verification_failure(void)
 {
-	struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
-						(CONFIG_SYS_SEC_MON_ADDR);
 	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
-	u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
 
 	/* 29th bit of OSPR is ITS */
 	u32 its = sfp_in32(&sfp_regs->ospr) >> 2;
 
-	/*
-	 * Read the SEC_MON status register
-	 * Read SSM_ST field
-	 */
-	sts = sec_mon_in32(&sec_mon_regs->hp_stat);
-	if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) {
-		if (its == 1)
-			change_sec_mon_state(HPSR_SSM_ST_TRUST,
-					     HPSR_SSM_ST_SOFT_FAIL);
-		else
-			change_sec_mon_state(HPSR_SSM_ST_TRUST,
-					     HPSR_SSM_ST_NON_SECURE);
-	}
+	if (its == 1)
+		set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL);
+	else
+		set_sec_mon_state(HPSR_SSM_ST_NON_SECURE);
 
 	printf("Generating reset request\n");
 	do_reset(NULL, 0, 0, NULL);
@@ -338,32 +363,20 @@ static void fsl_secboot_header_verification_failure(void)
  */
 static void fsl_secboot_image_verification_failure(void)
 {
-	struct ccsr_sec_mon_regs *sec_mon_regs = (void *)
-						(CONFIG_SYS_SEC_MON_ADDR);
 	struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
-	u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat);
 
 	u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT;
 
-	/*
-	 * Read the SEC_MON status register
-	 * Read SSM_ST field
-	 */
-	sts = sec_mon_in32(&sec_mon_regs->hp_stat);
-	if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) {
-		if (its == 1) {
-			change_sec_mon_state(HPSR_SSM_ST_TRUST,
-					     HPSR_SSM_ST_SOFT_FAIL);
-
-			printf("Generating reset request\n");
-			do_reset(NULL, 0, 0, NULL);
-			/* If reset doesn't coocur, halt execution */
-			do_esbc_halt(NULL, 0, 0, NULL);
-
-		} else {
-			change_sec_mon_state(HPSR_SSM_ST_TRUST,
-					     HPSR_SSM_ST_NON_SECURE);
-		}
+	if (its == 1) {
+		set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL);
+
+		printf("Generating reset request\n");
+		do_reset(NULL, 0, 0, NULL);
+		/* If reset doesn't coocur, halt execution */
+		do_esbc_halt(NULL, 0, 0, NULL);
+
+	} else {
+		set_sec_mon_state(HPSR_SSM_ST_NON_SECURE);
 	}
 }
 
@@ -380,6 +393,7 @@ static void fsl_secboot_bootscript_parse_failure(void)
  */
 void fsl_secboot_handle_error(int error)
 {
+#ifndef CONFIG_SPL_BUILD
 	const struct fsl_secboot_errcode *e;
 
 	for (e = fsl_secboot_errcodes; e->errcode != ERROR_ESBC_CLIENT_MAX;
@@ -387,6 +401,9 @@ void fsl_secboot_handle_error(int error)
 		if (e->errcode == error)
 			printf("ERROR :: %x :: %s\n", error, e->name);
 	}
+#else
+	printf("ERROR :: %x\n", error);
+#endif
 
 	/* If Boot Mode is secure, transition the SNVS state and issue
 	 * reset based on type of failure and ITS setting.
@@ -810,6 +827,26 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img)
 
 	return 0;
 }
+/* Function to initialize img priv and global data structure
+ */
+static int secboot_init(struct fsl_secboot_img_priv **img_ptr)
+{
+	*img_ptr = malloc(sizeof(struct fsl_secboot_img_priv));
+
+	struct fsl_secboot_img_priv *img = *img_ptr;
+
+	if (!img)
+		return -ENOMEM;
+	memset(img, 0, sizeof(struct fsl_secboot_img_priv));
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+	if (glb.ie_addr)
+		img->ie_addr = glb.ie_addr;
+#endif
+	return 0;
+}
+
+
 /* haddr - Address of the header of image to be validated.
  * arg_hash_str - Option hash string. If provided, this
  * overrides the key hash in the SFP fuses.
@@ -863,12 +900,9 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
 		hash_cmd = 1;
 	}
 
-	img = malloc(sizeof(struct fsl_secboot_img_priv));
-
-	if (!img)
-		return -1;
-
-	memset(img, 0, sizeof(struct fsl_secboot_img_priv));
+	ret = secboot_init(&img);
+	if (ret)
+		goto exit;
 
 	/* Update the information in Private Struct */
 	hdr = &img->hdr;
@@ -923,5 +957,7 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
 	}
 
 exit:
+	/* Free Img as it was malloc'ed*/
+	free(img);
 	return ret;
 }
diff --git a/board/freescale/common/mc34vr500.c b/board/freescale/common/mc34vr500.c
new file mode 100644
index 0000000..9c57569
--- /dev/null
+++ b/board/freescale/common/mc34vr500.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/mc34vr500_pmic.h>
+
+static uint8_t swxvolt_addr[4] = { MC34VR500_SW1VOLT,
+				   MC34VR500_SW2VOLT,
+				   MC34VR500_SW3VOLT,
+				   MC34VR500_SW4VOLT };
+
+static uint8_t swx_set_point_base[4] = { 13, 9, 9, 9 };
+
+int mc34vr500_get_sw_volt(uint8_t sw)
+{
+	struct pmic *p;
+	u32 swxvolt;
+	uint8_t spb;
+	int sw_volt;
+	int ret;
+
+	debug("%s: Get SW%u volt from swxvolt_addr = 0x%x\n",
+	      __func__, sw + 1, swxvolt_addr[sw]);
+	if (sw > SW4) {
+		printf("%s: Unsupported SW(sw%d)\n", __func__, sw + 1);
+		return -EINVAL;
+	}
+
+	p = pmic_get("MC34VR500");
+	if (!p) {
+		printf("%s: Did NOT find PMIC MC34VR500\n", __func__);
+		return -ENODEV;
+	}
+
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	ret = pmic_reg_read(p, swxvolt_addr[sw], &swxvolt);
+	if (ret) {
+		printf("%s: Failed to get SW%u volt\n", __func__, sw + 1);
+		return ret;
+	}
+
+	debug("%s: SW%d step point swxvolt = %u\n", __func__, sw + 1, swxvolt);
+	spb = swx_set_point_base[sw];
+	/* The base of SW volt is 625mV and increase by step 25mV */
+	sw_volt = 625 + (swxvolt - spb) * 25;
+
+	debug("%s: SW%u volt = %dmV\n", __func__, sw + 1, sw_volt);
+	return sw_volt;
+}
+
+int mc34vr500_set_sw_volt(uint8_t sw, int sw_volt)
+{
+	struct pmic *p;
+	u32 swxvolt;
+	uint8_t spb;
+	int ret;
+
+	debug("%s: Set SW%u volt to %dmV\n", __func__, sw + 1, sw_volt);
+	/* The least SW volt is 625mV, and only 4 SW outputs */
+	if (sw > SW4 || sw_volt < 625)
+		return -EINVAL;
+
+	p = pmic_get("MC34VR500");
+	if (!p) {
+		printf("%s: Did NOT find PMIC MC34VR500\n", __func__);
+		return -ENODEV;
+	}
+
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	spb = swx_set_point_base[sw];
+	/* The base of SW volt is 625mV and increase by step 25mV */
+	swxvolt = (sw_volt - 625) / 25 + spb;
+	debug("%s: SW%d step point swxvolt = %u\n", __func__, sw + 1, swxvolt);
+	if (swxvolt > 63)
+		return -EINVAL;
+
+	ret = pmic_reg_write(p, swxvolt_addr[sw], swxvolt);
+	if (ret)
+		return ret;
+
+	return 0;
+}
diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c
index 81c9211..0c3a54c 100644
--- a/board/freescale/common/ns_access.c
+++ b/board/freescale/common/ns_access.c
@@ -10,15 +10,15 @@
 #include <asm/arch/ns_access.h>
 #include <asm/arch/fsl_serdes.h>
 
-void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val)
+void set_devices_ns_access(unsigned long index, u16 val)
 {
 	u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
 	u32 *reg;
 	uint32_t tmp;
 
-	reg = base + ns_dev->ind / 2;
+	reg = base + index / 2;
 	tmp = in_be32(reg);
-	if (ns_dev->ind % 2 == 0) {
+	if (index % 2 == 0) {
 		tmp &= 0x0000ffff;
 		tmp |= val << 16;
 	} else {
@@ -34,12 +34,15 @@ static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
 	int i;
 
 	for (i = 0; i < num; i++)
-		set_devices_ns_access(ns_dev + i, ns_dev[i].val);
+		set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val);
 }
 
 void enable_layerscape_ns_access(void)
 {
-	enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#ifdef CONFIG_ARM64
+	if (current_el() == 3)
+#endif
+		enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
 }
 
 void set_pcie_ns_access(int pcie, u16 val)
@@ -47,20 +50,20 @@ void set_pcie_ns_access(int pcie, u16 val)
 	switch (pcie) {
 #ifdef CONFIG_PCIE1
 	case PCIE1:
-		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val);
-		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val);
+		set_devices_ns_access(CSU_CSLX_PCIE1, val);
+		set_devices_ns_access(CSU_CSLX_PCIE1_IO, val);
 		return;
 #endif
 #ifdef CONFIG_PCIE2
 	case PCIE2:
-		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val);
-		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val);
+		set_devices_ns_access(CSU_CSLX_PCIE2, val);
+		set_devices_ns_access(CSU_CSLX_PCIE2_IO, val);
 		return;
 #endif
 #ifdef CONFIG_PCIE3
 	case PCIE3:
-		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val);
-		set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val);
+		set_devices_ns_access(CSU_CSLX_PCIE3, val);
+		set_devices_ns_access(CSU_CSLX_PCIE3_IO, val);
 		return;
 #endif
 	default:
diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h
index 9328404..e6e0f66 100644
--- a/board/freescale/common/pixis.h
+++ b/board/freescale/common/pixis.h
@@ -7,7 +7,7 @@
 #define __PIXIS_H_	1
 
 /* PIXIS register set. */
-#if defined(CONFIG_MPC8536DS)
+#if defined(CONFIG_TARGET_MPC8536DS)
 typedef struct pixis {
 	u8 id;
 	u8 ver;
@@ -46,7 +46,7 @@ typedef struct pixis {
 	u8 res2[4];
 } __attribute__ ((packed)) pixis_t;
 
-#elif defined(CONFIG_MPC8544DS)
+#elif defined(CONFIG_TARGET_MPC8544DS)
 typedef struct pixis {
 	u8 id;
 	u8 ver;
@@ -73,7 +73,7 @@ typedef struct pixis {
 	u8 res2[34];
 } __attribute__ ((packed)) pixis_t;
 
-#elif defined(CONFIG_MPC8572DS)
+#elif defined(CONFIG_TARGET_MPC8572DS)
 typedef struct pixis {
 	u8 id;
 	u8 ver;
@@ -102,7 +102,7 @@ typedef struct pixis {
 	u8 res4[25];
 } __attribute__ ((packed)) pixis_t;
 
-#elif defined(CONFIG_MPC8610HPCD)
+#elif defined(CONFIG_TARGET_MPC8610HPCD)
 typedef struct pixis {
 	u8 id;
 	u8 ver;	/* also called arch */
@@ -132,7 +132,7 @@ typedef struct pixis {
 	u8 res4[33];
 } __attribute__ ((packed)) pixis_t;
 
-#elif defined(CONFIG_MPC8641HPCN)
+#elif defined(CONFIG_TARGET_MPC8641HPCN)
 typedef struct pixis {
 	u8 id;
 	u8 ver;
diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c
index 1eb3786..d152a78 100644
--- a/board/freescale/common/pq-mds-pib.c
+++ b/board/freescale/common/pq-mds-pib.c
@@ -63,7 +63,7 @@ int pib_init(void)
 #endif
 
 #if defined(CONFIG_PQ_MDS_PIB_ATM)
-#if defined(CONFIG_MPC8569MDS)
+#if defined(CONFIG_TARGET_MPC8569MDS)
 	val8 = 0;
 	i2c_write(0x20, 0x6, 1, &val8, 1);
 	i2c_write(0x20, 0x7, 1, &val8, 1);
diff --git a/board/freescale/common/spl.h b/board/freescale/common/spl.h
new file mode 100644
index 0000000..88c987e
--- /dev/null
+++ b/board/freescale/common/spl.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FREESCALE_BOARD_SPL_H
+#define __FREESCALE_BOARD_SPL_H
+
+void fsl_spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
+void fsl_spi_boot(void) __noreturn;
+
+#endif
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 1a50304..9b65c13 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -284,10 +284,170 @@ static int set_voltage(int i2caddress, int vdd)
 	return vdd_last;
 }
 
+#ifdef CONFIG_FSL_LSCH3
 int adjust_vdd(ulong vdd_override)
 {
 	int re_enable = disable_interrupts();
-#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 fusesr;
+	u8 vid, buf;
+	int vdd_target, vdd_current, vdd_last;
+	int ret, i2caddress;
+	unsigned long vdd_string_override;
+	char *vdd_string;
+	static const uint16_t vdd[32] = {
+		10500,
+		0,      /* reserved */
+		9750,
+		0,      /* reserved */
+		9500,
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		10000,  /* 1.0000V */
+		0,      /* reserved */
+		10250,
+		0,      /* reserved */
+		10500,
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+		0,      /* reserved */
+	};
+	struct vdd_drive {
+		u8 vid;
+		unsigned voltage;
+	};
+
+	ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
+	if (ret) {
+		debug("VID: I2C failed to switch channel\n");
+		ret = -1;
+		goto exit;
+	}
+	ret = find_ir_chip_on_i2c();
+	if (ret < 0) {
+		printf("VID: Could not find voltage regulator on I2C.\n");
+		ret = -1;
+		goto exit;
+	} else {
+		i2caddress = ret;
+		debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
+	}
+
+	/* check IR chip work on Intel mode*/
+	ret = i2c_read(i2caddress,
+		       IR36021_INTEL_MODE_OOFSET,
+		       1, (void *)&buf, 1);
+	if (ret) {
+		printf("VID: failed to read IR chip mode.\n");
+		ret = -1;
+		goto exit;
+	}
+	if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
+		printf("VID: IR Chip is not used in Intel mode.\n");
+		ret = -1;
+		goto exit;
+	}
+
+	/* get the voltage ID from fuse status register */
+	fusesr = in_le32(&gur->dcfg_fusesr);
+	vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
+		FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
+	if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
+		vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
+			FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
+	}
+	vdd_target = vdd[vid];
+
+	/* check override variable for overriding VDD */
+	vdd_string = getenv(CONFIG_VID_FLS_ENV);
+	if (vdd_override == 0 && vdd_string &&
+	    !strict_strtoul(vdd_string, 10, &vdd_string_override))
+		vdd_override = vdd_string_override;
+
+	if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) {
+		vdd_target = vdd_override * 10; /* convert to 1/10 mV */
+		debug("VDD override is %lu\n", vdd_override);
+	} else if (vdd_override != 0) {
+		printf("Invalid value.\n");
+	}
+
+	/* divide and round up by 10 to get a value in mV */
+	vdd_target = DIV_ROUND_UP(vdd_target, 10);
+	if (vdd_target == 0) {
+		debug("VID: VID not used\n");
+		ret = 0;
+		goto exit;
+	} else if (vdd_target < VDD_MV_MIN || vdd_target > VDD_MV_MAX) {
+		/* Check vdd_target is in valid range */
+		printf("VID: Target VID %d mV is not in range.\n",
+		       vdd_target);
+		ret = -1;
+		goto exit;
+	} else {
+		debug("VID: vid = %d mV\n", vdd_target);
+	}
+
+	/*
+	 * Read voltage monitor to check real voltage.
+	 */
+	vdd_last = read_voltage(i2caddress);
+	if (vdd_last < 0) {
+		printf("VID: Couldn't read sensor abort VID adjustment\n");
+		ret = -1;
+		goto exit;
+	}
+	vdd_current = vdd_last;
+	debug("VID: Core voltage is currently at %d mV\n", vdd_last);
+	/*
+	  * Adjust voltage to at or one step above target.
+	  * As measurements are less precise than setting the values
+	  * we may run through dummy steps that cancel each other
+	  * when stepping up and then down.
+	  */
+	while (vdd_last > 0 &&
+	       vdd_last < vdd_target) {
+		vdd_current += IR_VDD_STEP_UP;
+		vdd_last = set_voltage(i2caddress, vdd_current);
+	}
+	while (vdd_last > 0 &&
+	       vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) {
+		vdd_current -= IR_VDD_STEP_DOWN;
+		vdd_last = set_voltage(i2caddress, vdd_current);
+	}
+
+	if (vdd_last > 0)
+		printf("VID: Core voltage after adjustment is at %d mV\n",
+		       vdd_last);
+	else
+		ret = -1;
+exit:
+	if (re_enable)
+		enable_interrupts();
+	i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
+	return ret;
+}
+#else /* !CONFIG_FSL_LSCH3 */
+int adjust_vdd(ulong vdd_override)
+{
+	int re_enable = disable_interrupts();
+#if defined(CONFIG_FSL_LSCH2)
 	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 #else
 	ccsr_gur_t __iomem *gur =
@@ -364,11 +524,7 @@ int adjust_vdd(ulong vdd_override)
 	}
 
 	/* get the voltage ID from fuse status register */
-#ifdef CONFIG_FSL_LSCH3
-	fusesr = in_le32(&gur->dcfg_fusesr);
-#else
 	fusesr = in_be32(&gur->dcfg_fusesr);
-#endif
 	/*
 	 * VID is used according to the table below
 	 *                ---------------------------------------
@@ -393,13 +549,6 @@ int adjust_vdd(ulong vdd_override)
 		vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
 			FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
 	}
-#elif defined(CONFIG_FSL_LSCH3)
-	vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
-		FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
-	if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
-		vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
-			FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
-	}
 #else
 	vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
 		FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
@@ -472,6 +621,7 @@ exit:
 
 	return ret;
 }
+#endif
 
 static int print_vdd(void)
 {
diff --git a/board/freescale/common/zm7300.c b/board/freescale/common/zm7300.c
index be5953a..a6c3e69 100644
--- a/board/freescale/common/zm7300.c
+++ b/board/freescale/common/zm7300.c
@@ -140,9 +140,7 @@ int dpm_wrp(u8 r, u8 d)
 /* Uses the DPM command RRP */
 u8 zm_read(uchar reg)
 {
-	u8 d;
-	d = dpm_rrp(reg);
-	return d;
+	return dpm_rrp(reg);
 }
 
 /* ZM_write --
diff --git a/board/freescale/corenet_ds/Kconfig b/board/freescale/corenet_ds/Kconfig
index 433f539..98b1add 100644
--- a/board/freescale/corenet_ds/Kconfig
+++ b/board/freescale/corenet_ds/Kconfig
@@ -9,6 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "P3041DS"
 
+source "board/freescale/common/Kconfig"
+
 endif
 
 if TARGET_P4080DS
@@ -22,6 +24,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "P4080DS"
 
+source "board/freescale/common/Kconfig"
+
 endif
 
 if TARGET_P5020DS
@@ -35,6 +39,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "P5020DS"
 
+source "board/freescale/common/Kconfig"
+
 endif
 
 if TARGET_P5040DS
@@ -48,4 +54,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "P5040DS"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile
index 9ade947..100ba92 100644
--- a/board/freescale/corenet_ds/Makefile
+++ b/board/freescale/corenet_ds/Makefile
@@ -8,11 +8,11 @@
 
 obj-y	+= corenet_ds.o
 obj-y	+= ddr.o
-obj-$(CONFIG_P3041DS)	+= eth_hydra.o
-obj-$(CONFIG_P4080DS)	+= eth_p4080.o
-obj-$(CONFIG_P5020DS)	+= eth_hydra.o
-obj-$(CONFIG_P5040DS)	+= eth_superhydra.o
-obj-$(CONFIG_P3041DS)	+= p3041ds_ddr.o
-obj-$(CONFIG_P4080DS)	+= p4080ds_ddr.o
-obj-$(CONFIG_P5020DS)	+= p5020ds_ddr.o
-obj-$(CONFIG_P5040DS)	+= p5040ds_ddr.o
+obj-$(CONFIG_TARGET_P3041DS)	+= eth_hydra.o
+obj-$(CONFIG_TARGET_P4080DS)	+= eth_p4080.o
+obj-$(CONFIG_TARGET_P5020DS)	+= eth_hydra.o
+obj-$(CONFIG_TARGET_P5040DS)	+= eth_superhydra.o
+obj-$(CONFIG_TARGET_P3041DS)	+= p3041ds_ddr.o
+obj-$(CONFIG_TARGET_P4080DS)	+= p4080ds_ddr.o
+obj-$(CONFIG_TARGET_P5020DS)	+= p5020ds_ddr.o
+obj-$(CONFIG_TARGET_P5040DS)	+= p5040ds_ddr.o
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index f41985d..93e1258 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -26,8 +26,8 @@ int checkboard (void)
 {
 	u8 sw;
 	struct cpu_type *cpu = gd->arch.cpu;
-#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) || \
-	defined(CONFIG_P5040DS)
+#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
+	defined(CONFIG_TARGET_P5040DS)
 	unsigned int i;
 #endif
 	static const char * const freq[] = {"100", "125", "156.25", "212.5" };
@@ -56,15 +56,15 @@ int checkboard (void)
 	 * don't match.
 	 */
 	puts("SERDES Reference Clocks: ");
-#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
-	|| defined(CONFIG_P5040DS)
+#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
+	defined(CONFIG_TARGET_P5040DS)
 	sw = in_8(&PIXIS_SW(5));
 	for (i = 0; i < 3; i++) {
 		unsigned int clock = (sw >> (6 - (2 * i))) & 3;
 
 		printf("Bank%u=%sMhz ", i+1, freq[clock]);
 	}
-#ifdef CONFIG_P5040DS
+#ifdef CONFIG_TARGET_P5040DS
 	/* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
 	sw = in_8(&PIXIS_SW(9));
 	printf("Bank4=%sMhz ", freq[sw & 3]);
@@ -136,8 +136,8 @@ int misc_init_r(void)
 	unsigned int i;
 	u8 sw;
 
-#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
-	|| defined(CONFIG_P5040DS)
+#if defined(CONFIG_TARGET_P3041DS) || defined(CONFIG_TARGET_P5020DS) || \
+	defined(CONFIG_TARGET_P5040DS)
 	sw = in_8(&PIXIS_SW(5));
 	for (i = 0; i < 3; i++) {
 		unsigned int clock = (sw >> (6 - (2 * i))) & 3;
@@ -201,7 +201,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 #endif
 
 	fdt_fixup_liodn(blob);
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_ethernet(blob);
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index f3ba41a..496d841 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
  * Fixed sdram init -- doesn't use serial presence detect.
  */
 extern fixed_ddr_parm_t fixed_ddr_parm_0[];
-#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
 extern fixed_ddr_parm_t fixed_ddr_parm_1[];
 #endif
 
@@ -56,7 +56,7 @@ phys_size_t fixed_sdram(void)
 	ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
 	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
 
-#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
 	memcpy(&ddr_cfg_regs,
 		fixed_ddr_parm_1[i].ddr_settings,
 		sizeof(ddr_cfg_regs));
@@ -76,7 +76,7 @@ phys_size_t fixed_sdram(void)
 			return 0;
 		}
 	} else {
-#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
+#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
 		/* We require both controllers have identical DIMMs */
 		lawbar1_target_id = LAW_TRGT_IF_DDR_1;
 		if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
@@ -260,7 +260,7 @@ found:
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -278,5 +278,7 @@ phys_size_t initdram(int board_type)
 	dram_size *= 0x100000;
 
 	debug("    DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
index a34521c..38bd91b 100644
--- a/board/freescale/ls1012afrdm/Kconfig
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -12,4 +12,6 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls1012afrdm"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index d644e94..25d22d2 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -9,6 +9,10 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
+#ifdef CONFIG_FSL_LS_PPA
+#include <asm/arch/ppa.h>
+#endif
+#include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
 #include <hwconfig.h>
 #include <environment.h>
@@ -26,9 +30,29 @@ int checkboard(void)
 
 int dram_init(void)
 {
-	mmdc_init();
+	static const struct fsl_mmdc_info mparam = {
+		0x04180000,	/* mdctl */
+		0x00030035,	/* mdpdc */
+		0x12554000,	/* mdotc */
+		0xbabf7954,	/* mdcfg0 */
+		0xdb328f64,	/* mdcfg1 */
+		0x01ff00db,	/* mdcfg2 */
+		0x00001680,	/* mdmisc */
+		0x0f3c8000,	/* mdref */
+		0x00002000,	/* mdrwd */
+		0x00bf1023,	/* mdor */
+		0x0000003f,	/* mdasp */
+		0x0000022a,	/* mpodtctrl */
+		0xa1390003,	/* mpzqhwctrl */
+	};
+
+	mmdc_init(&mparam);
 
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+	/* This will break-before-make MMU for DDR */
+	update_early_mmu_table();
+#endif
 
 	return 0;
 }
@@ -58,6 +82,9 @@ int board_init(void)
 	gd->env_addr = (ulong)&default_environment[0];
 #endif
 
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
 	return 0;
 }
 
diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
index 1257ec8..fc9250b 100644
--- a/board/freescale/ls1012aqds/Kconfig
+++ b/board/freescale/ls1012aqds/Kconfig
@@ -12,4 +12,6 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls1012aqds"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 188b6bc..97ab340 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -10,7 +10,11 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
+#ifdef CONFIG_FSL_LS_PPA
+#include <asm/arch/ppa.h>
+#endif
 #include <asm/arch/fdt.h>
+#include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
 #include <ahci.h>
 #include <hwconfig.h>
@@ -54,9 +58,29 @@ int checkboard(void)
 
 int dram_init(void)
 {
-	mmdc_init();
+	static const struct fsl_mmdc_info mparam = {
+		0x05180000,	/* mdctl */
+		0x00030035,	/* mdpdc */
+		0x12554000,	/* mdotc */
+		0xbabf7954,	/* mdcfg0 */
+		0xdb328f64,	/* mdcfg1 */
+		0x01ff00db,	/* mdcfg2 */
+		0x00001680,	/* mdmisc */
+		0x0f3c8000,	/* mdref */
+		0x00002000,	/* mdrwd */
+		0x00bf1023,	/* mdor */
+		0x0000003f,	/* mdasp */
+		0x0000022a,	/* mpodtctrl */
+		0xa1390003,	/* mpzqhwctrl */
+	};
+
+	mmdc_init(&mparam);
 
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+	/* This will break-before-make MMU for DDR */
+	update_early_mmu_table();
+#endif
 
 	return 0;
 }
@@ -97,6 +121,10 @@ int board_init(void)
 #ifdef CONFIG_ENV_IS_NOWHERE
 	gd->env_addr = (ulong)&default_environment[0];
 #endif
+
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
 	return 0;
 }
 
@@ -105,6 +133,34 @@ int board_eth_init(bd_t *bis)
 	return pci_eth_init(bis);
 }
 
+int esdhc_status_fixup(void *blob, const char *compat)
+{
+	char esdhc0_path[] = "/soc/esdhc@1560000";
+	char esdhc1_path[] = "/soc/esdhc@1580000";
+	u8 card_id;
+
+	do_fixup_by_path(blob, esdhc0_path, "status", "okay",
+			 sizeof("okay"), 1);
+
+	/*
+	 * The Presence Detect 2 register detects the installation
+	 * of cards in various PCI Express or SGMII slots.
+	 *
+	 * STAT_PRS2[7:5]: Specifies the type of card installed in the
+	 * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
+	 */
+	card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
+
+	/* If no adapter is installed in SDHC2, disable SDHC2 */
+	if (card_id == 0x7)
+		do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
+				 sizeof("disabled"), 1);
+	else
+		do_fixup_by_path(blob, esdhc1_path, "status", "okay",
+				 sizeof("okay"), 1);
+	return 0;
+}
+
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
index 3f67c28..98231f9 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -12,4 +12,6 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls1012ardb"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS
index 79a2a7d..2cb38e7 100644
--- a/board/freescale/ls1012ardb/MAINTAINERS
+++ b/board/freescale/ls1012ardb/MAINTAINERS
@@ -4,3 +4,7 @@ S:	Maintained
 F:	board/freescale/ls1012ardb/
 F:	include/configs/ls1012ardb.h
 F:	configs/ls1012ardb_qspi_defconfig
+
+M:	Sumit Garg <sumit.garg@nxp.com>
+S:	Maintained
+F:	configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index 50f9187..a21e4c4 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -9,6 +9,10 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
+#ifdef CONFIG_FSL_LS_PPA
+#include <asm/arch/ppa.h>
+#endif
+#include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
 #include <hwconfig.h>
 #include <ahci.h>
@@ -18,6 +22,7 @@
 #include <environment.h>
 #include <fsl_mmdc.h>
 #include <netdev.h>
+#include <fsl_sec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -58,9 +63,29 @@ int checkboard(void)
 
 int dram_init(void)
 {
-	mmdc_init();
+	static const struct fsl_mmdc_info mparam = {
+		0x05180000,	/* mdctl */
+		0x00030035,	/* mdpdc */
+		0x12554000,	/* mdotc */
+		0xbabf7954,	/* mdcfg0 */
+		0xdb328f64,	/* mdcfg1 */
+		0x01ff00db,	/* mdcfg2 */
+		0x00001680,	/* mdmisc */
+		0x0f3c8000,	/* mdref */
+		0x00002000,	/* mdrwd */
+		0x00bf1023,	/* mdor */
+		0x0000003f,	/* mdasp */
+		0x0000022a,	/* mpodtctrl */
+		0xa1390003,	/* mpzqhwctrl */
+	};
+
+	mmdc_init(&mparam);
 
 	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+	/* This will break-before-make MMU for DDR */
+	update_early_mmu_table();
+#endif
 
 	return 0;
 }
@@ -94,6 +119,51 @@ int board_init(void)
 	gd->env_addr = (ulong)&default_environment[0];
 #endif
 
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+	return 0;
+}
+
+int esdhc_status_fixup(void *blob, const char *compat)
+{
+	char esdhc0_path[] = "/soc/esdhc@1560000";
+	char esdhc1_path[] = "/soc/esdhc@1580000";
+	u8 io = 0;
+	u8 mux_sdhc2;
+
+	do_fixup_by_path(blob, esdhc0_path, "status", "okay",
+			 sizeof("okay"), 1);
+
+	i2c_set_bus_num(0);
+
+	/*
+	 * The I2C IO-expander for mux select is used to control the muxing
+	 * of various onboard interfaces.
+	 *
+	 * IO1[3:2] indicates SDHC2 interface demultiplexer select lines.
+	 *	00 - SDIO wifi
+	 *	01 - GPIO (to Arduino)
+	 *	10 - eMMC Memory
+	 *	11 - SPI
+	 */
+	if (i2c_read(I2C_MUX_IO1_ADDR, 0, 1, &io, 1) < 0) {
+		printf("Error reading i2c boot information!\n");
+		return 0; /* Don't want to hang() on this error */
+	}
+
+	mux_sdhc2 = (io & 0x0c) >> 2;
+	/* Enable SDHC2 only when use SDIO wifi and eMMC */
+	if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
+		do_fixup_by_path(blob, esdhc1_path, "status", "okay",
+				 sizeof("okay"), 1);
+	else
+		do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
+				 sizeof("disabled"), 1);
 	return 0;
 }
 
diff --git a/board/freescale/ls1021aiot/Kconfig b/board/freescale/ls1021aiot/Kconfig
new file mode 100644
index 0000000..c6b1606
--- /dev/null
+++ b/board/freescale/ls1021aiot/Kconfig
@@ -0,0 +1,17 @@
+if TARGET_LS1021AIOT
+
+config SYS_BOARD
+	default "ls1021aiot"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "ls102xa"
+
+config SYS_CONFIG_NAME
+	default "ls1021aiot"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/ls1021aiot/MAINTAINERS b/board/freescale/ls1021aiot/MAINTAINERS
new file mode 100644
index 0000000..2dab798
--- /dev/null
+++ b/board/freescale/ls1021aiot/MAINTAINERS
@@ -0,0 +1,7 @@
+LS1021AIOT BOARD
+M:	Feng Li <feng.li_2@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1021aiot/
+F:	include/configs/ls1021aiot.h
+F:	configs/ls1021aiot_sdcard_defconfig
+F:	configs/ls1021aiot_qspi_defconfig
diff --git a/board/freescale/ls1021aiot/Makefile b/board/freescale/ls1021aiot/Makefile
new file mode 100644
index 0000000..6b960aa
--- /dev/null
+++ b/board/freescale/ls1021aiot/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ls1021aiot.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/board/freescale/ls1021aiot/README b/board/freescale/ls1021aiot/README
new file mode 100644
index 0000000..08b0268
--- /dev/null
+++ b/board/freescale/ls1021aiot/README
@@ -0,0 +1,58 @@
+Overview
+--------
+The LS1021A-IOT is a Freescale reference board that hosts
+the LS1021A SoC.
+
+LS1021AIOT board Overview
+-------------------------
+ - DDR Controller
+	- Supports 1GB un-buffered DDR3L SDRAM discrete
+	devices(32-bit bus) with 4 bit ECC
+	- DDR power supplies 1.35V to all devices with
+	automatic tracking of VTT
+	- Soldered DDR chip
+	- Supprot one fixed speed
+ - Ethernet
+	- Two on-board SGMII 10/100/1G ethernet ports
+	- One Gbit Etherent RGMII interface to 4-ports switch
+	with 4x 10/100/1000 RJ145 ports
+ - CPLD
+	- 8-bit registers in CPLD for system configuration
+	- connected to IFC_AD[0:7]
+ - Power Supplies
+	- 12V@5A DC
+ - SDHC
+	- SDHC port connects directly to a full 8-bit SD/MMC slot
+	- Support for SDIO devices
+ - USB
+	- Two on-board USB 3.0
+	- One on-board USB k22
+ - PCIe
+	- Two MiniPCIe Solts
+ - SATA
+	- Support SATA Connector
+ - AUDIO
+	- AUDIO in and out
+ - I/O Expansion
+	- Arduino Shield Connector
+	- Port0 - CAN/GPIO/Flextimer
+	- Port1 - GPIO/CPLD Expansion
+	- Port2 - SPI/I2C/UART
+
+Memory map
+-----------
+The addresses in brackets are physical addresses.
+
+Start Address	End Address		Description			Size
+0x00_0100_0000	0x00_0FFF_FFFF	CCSRBAR				240MB
+0x00_4000_0000	0x00_43FF_FFFF	QSPI(Chip select 0)	64MB
+0x00_4400_0000	0x00_47FF_FFFF	QSPI(Chip select 1)	64MB
+0x00_6000_0000	0x00_6000_FFFF	CPLD				64K
+0x00_8000_0000	0x00_BFFF_FFFF	DDR					1GB
+
+Boot description
+-----------------
+LS1021A-IOT support two ways of boot:
+Qspi boot and SD boot
+The board doesn't support boot from another
+source without changing any switch/jumper.
diff --git a/board/freescale/ls1021aiot/dcu.c b/board/freescale/ls1021aiot/dcu.c
new file mode 100644
index 0000000..e27647f
--- /dev/null
+++ b/board/freescale/ls1021aiot/dcu.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include "div64.h"
+#include "../common/dcu_sii9022a.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+	unsigned long long div;
+
+	div = (unsigned long long)(gd->bus_clk / 1000);
+	div *= (unsigned long long)pixclock;
+	do_div(div, 1000000000);
+
+	return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+		const char *port,
+		struct fb_videomode *dcu_fb_videomode)
+{
+	const char *name;
+	unsigned int pixel_format;
+
+	if (strncmp(port, "twr_lcd", 4) == 0) {
+		name = "TWR_LCD_RGB card";
+	} else {
+		name = "HDMI";
+		dcu_set_dvi_encoder(dcu_fb_videomode);
+	}
+
+	printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
+
+	pixel_format = 32;
+	fsl_dcu_init(xres, yres, pixel_format);
+
+	return 0;
+}
diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c
new file mode 100644
index 0000000..5854e2d
--- /dev/null
+++ b/board/freescale/ls1021aiot/ls1021aiot.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ls102xa_stream_id.h>
+
+#include <asm/arch/ls102xa_devdis.h>
+#include <asm/arch/ls102xa_soc.h>
+#include <asm/arch/ls102xa_sata.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_immap.h>
+#include <netdev.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <spl.h>
+
+#include <fsl_validate.h>
+#include "../common/sleep.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_SIZE		0x40000000
+
+
+int checkboard(void)
+{
+	puts("Board: LS1021AIOT\n");
+
+#ifndef CONFIG_QSPI_BOOT
+	struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
+	u32 cpldrev;
+
+	cpldrev = in_be32(&dcfg->gpporcr1);
+
+	printf("CPLD:  V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) &
+		0xf));
+#endif
+	return 0;
+}
+
+void ddrmc_init(void)
+{
+	struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
+	u32 temp_sdram_cfg, tmp;
+
+	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
+
+	out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
+
+	out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
+	out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
+	out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
+	out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
+	out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
+	out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
+
+	out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
+	out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
+
+	out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
+	out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
+
+	out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
+
+	out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
+
+	out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
+	out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
+
+	out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
+
+	out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
+	out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
+
+	out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
+
+	/* DDR erratum A-009942 */
+	tmp = in_be32(&ddr->debug[28]);
+	out_be32(&ddr->debug[28], tmp | 0x0070006f);
+
+	udelay(500);
+
+	temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
+
+	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
+}
+
+int dram_init(void)
+{
+#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+	ddrmc_init();
+#endif
+
+	gd->ram_size = DDR_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+	{CONFIG_SYS_FSL_ESDHC_ADDR},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+
+#endif
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[4];
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	if (is_serdes_configured(SGMII_TSEC1)) {
+		puts("eTSEC1 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	if (is_serdes_configured(SGMII_TSEC2)) {
+		puts("eTSEC2 is in sgmii mode.\n");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, num);
+
+	return pci_eth_init(bis);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+#ifdef CONFIG_TSEC_ENET
+	/* clear BD & FR bits for BE BD's and frame data */
+	clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+
+#endif
+
+	arch_soc_init();
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+	/* Clear the BSS */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	get_clocks();
+
+	preloader_console_init();
+
+	dram_init();
+
+	/* Allow OCRAM access permission as R/W */
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+	board_init_r(NULL, 0);
+}
+#endif
+
+int board_init(void)
+{
+#ifndef CONFIG_SYS_FSL_NO_SERDES
+	fsl_serdes_init();
+#endif
+
+	ls102xa_smmu_stream_id_init();
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_SCSI_AHCI_PLAT
+	ls1021a_sata_init();
+#endif
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#ifdef CONFIG_FSL_DEVICE_DISABLE
+	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
+
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	return sec_init();
+#endif
+}
+#endif
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+
+	return 0;
+}
+
+void flash_write16(u16 val, void *addr)
+{
+	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+	__raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+	u16 val = __raw_readw(addr);
+
+	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
diff --git a/board/freescale/ls1021aiot/ls102xa_pbi.cfg b/board/freescale/ls1021aiot/ls102xa_pbi.cfg
new file mode 100644
index 0000000..b5ac5e2
--- /dev/null
+++ b/board/freescale/ls1021aiot/ls102xa_pbi.cfg
@@ -0,0 +1,14 @@
+#PBI commands
+
+09570200 ffffffff
+09570158 00000300
+8940007c 21f47300
+
+#Configure Scratch register
+09ee0200 10000000
+#Configure alternate space
+09570158 00001000
+#Flush PBL data
+096100c0 000FFFFF
+
+09ea085c 00502880
diff --git a/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
new file mode 100644
index 0000000..a1984c7
--- /dev/null
+++ b/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
@@ -0,0 +1,27 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+
+#Default with 2 x SGMII (no SATA)
+0608000a 00000000 00000000 00000000
+20000000 08407900 60025a00 21046000
+00000000 00000000 00000000 20038000
+20024800 881b1340 00000000 00000000
+
+#SATA set-up
+#0608000a 00000000 00000000 00000000
+#70000000 08007900 60025a00 21046000
+#00000000 00000000 00000000 20038000
+#20024800 881b1340 00000000 00000000
+
+#HDMI set-up
+#0608000a 00000000 00000000 00000000
+#20000000 08407900 60025a00 21046000
+#00000000 00000000 00000000 20038000
+#00000000 881b1340 00000000 00000000
+
+#QE testing
+#0608000a 00000000 00000000 00000000
+#20000000 08407900 60025a00 21046000
+#00000000 00000000 00000000 00038000
+#20094800 881b1340 00000000 00000000
diff --git a/board/freescale/ls1021aiot/psci.S b/board/freescale/ls1021aiot/psci.S
new file mode 100644
index 0000000..564145c
--- /dev/null
+++ b/board/freescale/ls1021aiot/psci.S
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2016 NXP Semiconductor.
+ * Author: Feng Li <feng.li_2@nxp.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+#include <asm/armv7.h>
+#include <asm/psci.h>
+
+	.pushsection ._secure.text, "ax"
+
+	.arch_extension sec
+
+	.align	5
+
+.globl	psci_system_off
+psci_system_off:
+1:	wfi
+	b	1b
+
+.globl	psci_text_end
+psci_text_end:
+	nop
+	.popsection
diff --git a/board/freescale/ls1021aqds/Kconfig b/board/freescale/ls1021aqds/Kconfig
index 119b955..60b8472 100644
--- a/board/freescale/ls1021aqds/Kconfig
+++ b/board/freescale/ls1021aqds/Kconfig
@@ -12,4 +12,6 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls1021aqds"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile
index f0390c1..1e50e46 100644
--- a/board/freescale/ls1021aqds/Makefile
+++ b/board/freescale/ls1021aqds/Makefile
@@ -7,5 +7,5 @@
 obj-y += ls1021aqds.o
 obj-y += ddr.o
 obj-y += eth.o
-obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/board/freescale/ls1021aqds/README b/board/freescale/ls1021aqds/README
index c561776..6cf7146 100644
--- a/board/freescale/ls1021aqds/README
+++ b/board/freescale/ls1021aqds/README
@@ -110,3 +110,9 @@ Start Address	End Address	Description			Size
 0x00_7E80_0000	0x00_7E80_FFFF	IFC - NAND Flash		64KB
 0x00_7FB0_0000	0x00_7FB0_0FFF	IFC - FPGA			4KB
 0x00_8000_0000	0x00_FFFF_FFFF	DRAM1				2GB
+
+LS1021a rev1.0 Soc specific Options/Settings
+--------------------------------------------
+If the LS1021a Soc is rev1.0, you need modify the configure file.
+Add the following define in include/configs/ls1021aqds.h:
+#define CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
index 6435bf9..2ee8749 100644
--- a/board/freescale/ls1021aqds/ddr.c
+++ b/board/freescale/ls1021aqds/ddr.c
@@ -8,6 +8,7 @@
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
 #include <asm/io.h>
+#include <asm/arch/clock.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -96,6 +97,9 @@ found:
 #else
 	popts->cswl_override = DDR_CSWL_CS0;
 
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x58;
+
 	/* DHC_EN =1, ODT = 75 Ohm */
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
@@ -161,7 +165,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+int fsl_initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -176,11 +180,15 @@ phys_size_t initdram(int board_type)
 	fsl_dp_resume();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 4eb38a7..d81d8ab 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -22,7 +22,7 @@
 #include <spl.h>
 #include <fsl_devdis.h>
 #include <fsl_validate.h>
-
+#include <fsl_ddr.h>
 #include "../common/sleep.h"
 #include "../common/qixis.h"
 #include "ls1021aqds_qixis.h"
@@ -162,9 +162,7 @@ int dram_init(void)
 	 * before accessing DDR SPD.
 	 */
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-	gd->ram_size = initdram(0);
-
-	return 0;
+	return fsl_initdram();
 }
 
 #ifdef CONFIG_FSL_ESDHC
@@ -433,7 +431,9 @@ int board_init(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 	erratum_a010315();
 #endif
-
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+	erratum_a009942_check_cpo();
+#endif
 	major = get_soc_major_rev();
 	if (major == SOC_MAJOR_VER_1_0) {
 		/* Set CCI-400 control override register to
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
index 222c71d..d76e913 100644
--- a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 01ee0100
 # serdes protocol
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
 60000000 00407900 e0106a00 21046000
 00000000 00000000 00000000 00038000
 00000000 001b7200 00000000 00000000
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
index 9d99bd8..f0cf9c2 100644
--- a/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
@@ -2,13 +2,13 @@
 aa55aa55 01ee0100
 
 #enable IFC, disable QSPI and DSPI
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
 60000000 00407900 60040a00 21046000
 00000000 00000000 00000000 00038000
 00000000 001b7200 00000000 00000000
 
 #disable IFC, enable QSPI and DSPI
-#0608000a 00000000 00000000 00000000
+#0608000c 00000000 00000000 00000000
 #60000000 00407900 60040a00 21046000
 #00000000 00000000 00000000 00038000
 #20024800 001b7200 00000000 00000000
diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
index 2bd398c..10cc4a9 100644
--- a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
+++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
@@ -2,13 +2,13 @@
 aa55aa55 01ee0100
 
 #enable IFC, disable QSPI and DSPI
-#0608000a 00000000 00000000 00000000
+#0608000c 00000000 00000000 00000000
 #60000000 00407900 60040a00 21046000
 #00000000 00000000 00000000 00038000
 #00000000 001b7200 00000000 00000000
 
 #disable IFC, enable QSPI and DSPI
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
 60000000 00407900 60040a00 21046000
 00000000 00000000 00000000 00038000
 20024800 001b7200 00000000 00000000
diff --git a/board/freescale/ls1021atwr/Kconfig b/board/freescale/ls1021atwr/Kconfig
index bc50b8d..a4641cb 100644
--- a/board/freescale/ls1021atwr/Kconfig
+++ b/board/freescale/ls1021atwr/Kconfig
@@ -12,4 +12,6 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls1021atwr"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile
index 5238b15..d9a2f52 100644
--- a/board/freescale/ls1021atwr/Makefile
+++ b/board/freescale/ls1021atwr/Makefile
@@ -5,5 +5,5 @@
 #
 
 obj-y += ls1021atwr.o
-obj-$(CONFIG_FSL_DCU_FB) += dcu.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
diff --git a/board/freescale/ls1021atwr/README b/board/freescale/ls1021atwr/README
index d2821cb..896a659 100644
--- a/board/freescale/ls1021atwr/README
+++ b/board/freescale/ls1021atwr/README
@@ -107,3 +107,9 @@ Start Address	End Address	Description			Size
 0x00_4000_0000	0x00_5FFF_FFFF	QSPI				512MB
 0x00_6000_0000	0x00_67FF_FFFF	IFC - NOR Flash			128MB
 0x00_8000_0000	0x00_FFFF_FFFF	DRAM1				2GB
+
+LS1021a rev1.0 Soc specific Options/Settings
+--------------------------------------------
+If the LS1021a Soc is rev1.0, you need modify the configure file.
+Add the following define in include/configs/ls1021atwr.h:
+#define CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index d96fd77..2da0677 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -273,6 +273,7 @@ int board_eth_init(bd_t *bis)
 #endif
 #ifdef CONFIG_TSEC3
 	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
 	num++;
 #endif
 	if (!num) {
@@ -434,7 +435,6 @@ void board_init_f(ulong dummy)
 	/* Allow OCRAM access permission as R/W */
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 	enable_layerscape_ns_access();
-	enable_layerscape_ns_access();
 #endif
 
 	/*
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
index 205606f..f94997d 100644
--- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
+++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
@@ -2,7 +2,7 @@
 aa55aa55 01ee0100
 
 #enable IFC, disable QSPI and DSPI
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
 30000000 00007900 60040a00 21046000
 00000000 00000000 00000000 20000000
 00080000 881b7340 00000000 00000000
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
index 6767e09..541b604 100644
--- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
+++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
@@ -2,7 +2,7 @@
 aa55aa55 01ee0100
 
 #disable IFC, enable QSPI and DSPI
-0608000a 00000000 00000000 00000000
+0608000c 00000000 00000000 00000000
 30000000 00007900 60040a00 21046000
 00000000 00000000 00000000 20000000
 20024800 881b7340 00000000 00000000
diff --git a/board/freescale/ls1043aqds/Kconfig b/board/freescale/ls1043aqds/Kconfig
index 7e27f8f..95d2888 100644
--- a/board/freescale/ls1043aqds/Kconfig
+++ b/board/freescale/ls1043aqds/Kconfig
@@ -12,4 +12,6 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls1043aqds"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/ls1043aqds/Makefile b/board/freescale/ls1043aqds/Makefile
index f727bfd..49d8d7d 100644
--- a/board/freescale/ls1043aqds/Makefile
+++ b/board/freescale/ls1043aqds/Makefile
@@ -5,5 +5,7 @@
 #
 
 obj-y += ddr.o
+ifndef CONFIG_SPL_BUILD
 obj-y += eth.o
+endif
 obj-y += ls1043aqds.o
diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
index d4540d0..f219a77 100644
--- a/board/freescale/ls1043aqds/ddr.c
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -10,6 +10,7 @@
 #ifdef CONFIG_FSL_DEEP_SLEEP
 #include <fsl_sleep.h>
 #endif
+#include <asm/arch/clock.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -96,6 +97,9 @@ found:
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
 			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x59;
 #else
 	popts->cswl_override = DDR_CSWL_CS0;
 
@@ -105,12 +109,14 @@ found:
 #endif
 }
 
-phys_size_t initdram(int board_type)
+int fsl_initdram(void)
 {
 	phys_size_t dram_size;
 
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-	return fsl_ddr_sdram_size();
+	gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
 #else
 	puts("Initializing DDR....using SPD\n");
 
@@ -122,34 +128,7 @@ phys_size_t initdram(int board_type)
 	fsl_dp_ddr_restore();
 #endif
 
-	return dram_size;
-}
+	gd->ram_size = dram_size;
 
-void dram_init_banksize(void)
-{
-	/*
-	 * gd->arch.secure_ram tracks the location of secure memory.
-	 * It was set as if the memory starts from 0.
-	 * The address needs to add the offset of its bank.
-	 */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
-		gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
-		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
-		gd->bd->bi_dram[1].size = gd->ram_size -
-					  CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->arch.secure_ram = gd->bd->bi_dram[1].start +
-				      gd->arch.secure_ram -
-				      CONFIG_SYS_DDR_BLOCK1_SIZE;
-		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
-	} else {
-		gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
-				      gd->arch.secure_ram;
-		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
-	}
+	return 0;
 }
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index 8835a49..8fbd3a7 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -7,10 +7,13 @@
 #include <common.h>
 #include <i2c.h>
 #include <fdt_support.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ppa.h>
 #include <asm/arch/fdt.h>
+#include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
 #include <ahci.h>
 #include <hwconfig.h>
@@ -152,7 +155,11 @@ int dram_init(void)
 	 * before accessing DDR SPD.
 	 */
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-	gd->ram_size = initdram(0);
+	fsl_initdram();
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+	/* This will break-before-make MMU for DDR */
+	update_early_mmu_table();
+#endif
 
 	return 0;
 }
@@ -319,6 +326,10 @@ int board_init(void)
 	config_serdes_mux();
 #endif
 
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+
 	return 0;
 }
 
diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig
index 51818ec..1bab7ca 100644
--- a/board/freescale/ls1043ardb/Kconfig
+++ b/board/freescale/ls1043ardb/Kconfig
@@ -13,4 +13,15 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls1043ardb"
 
+config SYS_HAS_ARMV8_SECURE_BASE
+	bool "Enable secure address for PSCI image"
+	depends on ARMV8_PSCI
+	default n
+	help
+	  PSCI image can be re-located to secure RAM.
+	  If enabled, please also define the value for ARMV8_SECURE_BASE,
+	  for LS1043ARDB, it could be some address in OCRAM.
+
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS
index 0503a3f..87aa006 100644
--- a/board/freescale/ls1043ardb/MAINTAINERS
+++ b/board/freescale/ls1043ardb/MAINTAINERS
@@ -12,3 +12,5 @@ LS1043A_SECURE_BOOT BOARD
 M:	Ruchika Gupta <ruchika.gupta@nxp.com>
 S:	Maintained
 F:	configs/ls1043ardb_SECURE_BOOT_defconfig
+F:	configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+F:	configs/ls1043ardb_nand_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1043ardb/Makefile b/board/freescale/ls1043ardb/Makefile
index 5fe1cc9..930c690 100644
--- a/board/freescale/ls1043ardb/Makefile
+++ b/board/freescale/ls1043ardb/Makefile
@@ -4,7 +4,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += cpld.o
 obj-y += ddr.o
 obj-y += ls1043ardb.o
-obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_NET) += eth.o
+obj-y += cpld.o
+endif
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index 61b1cc4..354b864 100644
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -11,6 +11,7 @@
 #ifdef CONFIG_FSL_DEEP_SLEEP
 #include <fsl_sleep.h>
 #endif
+#include <asm/arch/clock.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -91,6 +92,9 @@ found:
 	/* Enable ZQ calibration */
 	popts->zq_en = 1;
 
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x46;
+
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
 			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */
@@ -167,7 +171,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 }
 #endif
 
-phys_size_t initdram(int board_type)
+int fsl_initdram(void)
 {
 	phys_size_t dram_size;
 
@@ -183,34 +187,7 @@ phys_size_t initdram(int board_type)
 	fsl_dp_ddr_restore();
 #endif
 
-	return dram_size;
-}
+	gd->ram_size = dram_size;
 
-void dram_init_banksize(void)
-{
-	/*
-	 * gd->arch.secure_ram tracks the location of secure memory.
-	 * It was set as if the memory starts from 0.
-	 * The address needs to add the offset of its bank.
-	 */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
-		gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
-		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
-		gd->bd->bi_dram[1].size = gd->ram_size -
-					  CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->arch.secure_ram = gd->bd->bi_dram[1].start +
-				      gd->arch.secure_ram -
-				      CONFIG_SYS_DDR_BLOCK1_SIZE;
-		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
-	} else {
-		gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
-				      gd->arch.secure_ram;
-		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
-	}
+	return 0;
 }
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index e213128..9dc1cbc 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -23,12 +23,19 @@
 #ifdef CONFIG_U_QE
 #include <fsl_qe.h>
 #endif
-#ifdef CONFIG_FSL_LS_PPA
 #include <asm/arch/ppa.h>
-#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+
 int checkboard(void)
 {
 	static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
@@ -67,20 +74,6 @@ int checkboard(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	gd->ram_size = initdram(0);
-
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	fsl_lsch2_early_init_f();
-
-	return 0;
-}
-
 int board_init(void)
 {
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
@@ -222,3 +215,5 @@ u16 flash_read16(void *addr)
 
 	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 }
+
+#endif
diff --git a/board/freescale/ls1046aqds/Kconfig b/board/freescale/ls1046aqds/Kconfig
index 723f4ba..070827d 100644
--- a/board/freescale/ls1046aqds/Kconfig
+++ b/board/freescale/ls1046aqds/Kconfig
@@ -12,4 +12,6 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls1046aqds"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/ls1046aqds/MAINTAINERS b/board/freescale/ls1046aqds/MAINTAINERS
index b4549ae..6737d55 100644
--- a/board/freescale/ls1046aqds/MAINTAINERS
+++ b/board/freescale/ls1046aqds/MAINTAINERS
@@ -8,3 +8,7 @@ F:	configs/ls1046aqds_nand_defconfig
 F:	configs/ls1046aqds_sdcard_ifc_defconfig
 F:	configs/ls1046aqds_sdcard_qspi_defconfig
 F:	configs/ls1046aqds_qspi_defconfig
+
+M:	Sumit Garg <sumit.garg@nxp.com>
+S:	Maintained
+F:	configs/ls1046aqds_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1046aqds/Makefile b/board/freescale/ls1046aqds/Makefile
index df6e546..6267522 100644
--- a/board/freescale/ls1046aqds/Makefile
+++ b/board/freescale/ls1046aqds/Makefile
@@ -5,5 +5,7 @@
 #
 
 obj-y += ddr.o
+ifndef CONFIG_SPL_BUILD
 obj-y += eth.o
+endif
 obj-y += ls1046aqds.o
diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c
index d813965..e1858d6 100644
--- a/board/freescale/ls1046aqds/ddr.c
+++ b/board/freescale/ls1046aqds/ddr.c
@@ -10,6 +10,7 @@
 #ifdef CONFIG_FSL_DEEP_SLEEP
 #include <fsl_sleep.h>
 #endif
+#include <asm/arch/clock.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -87,14 +88,19 @@ found:
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
 			  DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x70;
 }
 
-phys_size_t initdram(int board_type)
+int fsl_initdram(void)
 {
 	phys_size_t dram_size;
 
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-	return fsl_ddr_sdram_size();
+	gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
 #else
 	puts("Initializing DDR....using SPD\n");
 
@@ -107,34 +113,7 @@ phys_size_t initdram(int board_type)
 
 	erratum_a008850_post();
 
-	return dram_size;
-}
+	gd->ram_size = dram_size;
 
-void dram_init_banksize(void)
-{
-	/*
-	 * gd->arch.secure_ram tracks the location of secure memory.
-	 * It was set as if the memory starts from 0.
-	 * The address needs to add the offset of its bank.
-	 */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
-		gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
-		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
-		gd->bd->bi_dram[1].size = gd->ram_size -
-					  CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->arch.secure_ram = gd->bd->bi_dram[1].start +
-				 gd->arch.secure_ram -
-				 CONFIG_SYS_DDR_BLOCK1_SIZE;
-		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
-	} else {
-		gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
-				 gd->arch.secure_ram;
-		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
-	}
+	return 0;
 }
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index 8c18538..883abf7 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -7,10 +7,13 @@
 #include <common.h>
 #include <i2c.h>
 #include <fdt_support.h>
+#include <fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ppa.h>
 #include <asm/arch/fdt.h>
+#include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
 #include <ahci.h>
 #include <hwconfig.h>
@@ -20,6 +23,7 @@
 #include <fsl_csu.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
+#include <fsl_sec.h>
 #include <spl.h>
 
 #include "../common/vid.h"
@@ -120,6 +124,13 @@ unsigned long get_board_ddr_clk(void)
 	return 66666666;
 }
 
+#ifdef CONFIG_LPUART
+u32 get_lpuart_clk(void)
+{
+	return gd->bus_clk;
+}
+#endif
+
 int select_i2c_ch_pca9547(u8 ch)
 {
 	int ret;
@@ -141,7 +152,11 @@ int dram_init(void)
 	 * before accessing DDR SPD.
 	 */
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-	gd->ram_size = initdram(0);
+	fsl_initdram();
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+	/* This will break-before-make MMU for DDR */
+	update_early_mmu_table();
+#endif
 
 	return 0;
 }
@@ -157,6 +172,9 @@ int board_early_init_f(void)
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 	u32 usb_pwrfault;
 #endif
+#ifdef CONFIG_LPUART
+	u8 uart;
+#endif
 
 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 	i2c_early_init_f();
@@ -175,6 +193,14 @@ int board_early_init_f(void)
 	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 #endif
 
+#ifdef CONFIG_LPUART
+	/* We use lpuart0 as system console */
+	uart = QIXIS_READ(brdcfg[14]);
+	uart &= ~CFG_UART_MUX_MASK;
+	uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
+	QIXIS_WRITE(brdcfg[14], uart);
+#endif
+
 	return 0;
 }
 
@@ -235,13 +261,31 @@ int board_init(void)
 	config_serdes_mux();
 #endif
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-	enable_layerscape_ns_access();
-#endif
-
 	if (adjust_vdd(0))
 		printf("Warning: Adjusting core voltage failed.\n");
 
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+
+#ifdef CONFIG_SECURE_BOOT
+	/*
+	 * In case of Secure Boot, the IBR configures the SMMU
+	 * to allow only Secure transactions.
+	 * SMMU must be reset in bypass mode.
+	 * Set the ClientPD bit and Clear the USFCFG Bit
+	 */
+	u32 val;
+	val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+	out_le32(SMMU_SCR0, val);
+	val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+	out_le32(SMMU_NSCR0, val);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
 	return 0;
 }
 
diff --git a/board/freescale/ls1046ardb/Kconfig b/board/freescale/ls1046ardb/Kconfig
index a62255c..b9f2ed7 100644
--- a/board/freescale/ls1046ardb/Kconfig
+++ b/board/freescale/ls1046ardb/Kconfig
@@ -12,5 +12,5 @@ config SYS_SOC
 
 config SYS_CONFIG_NAME
 	default "ls1046ardb"
-
+source "board/freescale/common/Kconfig"
 endif
diff --git a/board/freescale/ls1046ardb/MAINTAINERS b/board/freescale/ls1046ardb/MAINTAINERS
index ff42bef..79a2290 100644
--- a/board/freescale/ls1046ardb/MAINTAINERS
+++ b/board/freescale/ls1046ardb/MAINTAINERS
@@ -7,3 +7,13 @@ F:	include/configs/ls1046ardb.h
 F:	configs/ls1046ardb_qspi_defconfig
 F:	configs/ls1046ardb_sdcard_defconfig
 F:	configs/ls1046ardb_emmc_defconfig
+
+LS1046A_SECURE_BOOT BOARD
+M:	Ruchika Gupta <ruchika.gupta@nxp.com>
+S:	Maintained
+F:	configs/ls1046ardb_SECURE_BOOT_defconfig
+F:	configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+
+M:	Sumit Garg <sumit.garg@nxp.com>
+S:	Maintained
+F:	configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
diff --git a/board/freescale/ls1046ardb/Makefile b/board/freescale/ls1046ardb/Makefile
index 348eb76..4076558 100644
--- a/board/freescale/ls1046ardb/Makefile
+++ b/board/freescale/ls1046ardb/Makefile
@@ -4,7 +4,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += cpld.o
 obj-y += ddr.o
 obj-y += ls1046ardb.o
-obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_NET) += eth.o
+obj-y += cpld.o
+endif
diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README
index 1ef7d47..a38c9d4 100644
--- a/board/freescale/ls1046ardb/README
+++ b/board/freescale/ls1046ardb/README
@@ -59,14 +59,14 @@ Start Address	 End Address	 Description		Size
 QSPI flash map:
 Start Address    End Address     Description		Size
 0x00_4000_0000 - 0x00_400F_FFFF  RCW + PBI		1MB
-0x00_4010_0000 - 0x00_401F_FFFF  U-Boot 		1MB
-0x00_4020_0000 - 0x00_402F_FFFF  U-Boot Env		1MB
-0x00_4030_0000 - 0x00_403F_FFFF  FMan ucode		1MB
-0x00_4040_0000 - 0x00_404F_FFFF  UEFI			1MB
-0x00_4050_0000 - 0x00_406F_FFFF  PPA			2MB
-0x00_4070_0000 - 0x00_408F_FFFF  Secure boot header
-			         + bootscript		2MB
-0x00_4090_0000 - 0x00_40FF_FFFF  Reserved		7MB
+0x00_4010_0000 - 0x00_402F_FFFF  U-Boot 		2MB
+0x00_4030_0000 - 0x00_403F_FFFF  U-Boot Env		1MB
+0x00_4040_0000 - 0x00_405F_FFFF  PPA			2MB
+0x00_4060_0000 - 0x00_408F_FFFF  Secure boot header
+				 + bootscript		3MB
+0x00_4090_0000 - 0x00_4093_FFFF  FMan ucode		256KB
+0x00_4094_0000 - 0x00_4097_FFFF  QE/uQE firmware	256KB
+0x00_4098_0000 - 0x00_40FF_FFFF  Reserved		6MB
 0x00_4100_0000 - 0x00_43FF_FFFF  FIT Image		48MB
 
 Booting Options
diff --git a/board/freescale/ls1046ardb/cpld.c b/board/freescale/ls1046ardb/cpld.c
index 81a646e..c0500f4 100644
--- a/board/freescale/ls1046ardb/cpld.c
+++ b/board/freescale/ls1046ardb/cpld.c
@@ -82,6 +82,15 @@ void cpld_set_sd(void)
 
 	CPLD_WRITE(system_rst, 1);
 }
+
+void cpld_select_core_volt(bool en_0v9)
+{
+	u8 reg17 = en_0v9;
+
+	CPLD_WRITE(vdd_en, 1);
+	CPLD_WRITE(vdd_sel, reg17);
+}
+
 #ifdef DEBUG
 static void cpld_dump_regs(void)
 {
diff --git a/board/freescale/ls1046ardb/cpld.h b/board/freescale/ls1046ardb/cpld.h
index 458da7e..f6a1a61 100644
--- a/board/freescale/ls1046ardb/cpld.h
+++ b/board/freescale/ls1046ardb/cpld.h
@@ -35,6 +35,7 @@ struct cpld_data {
 u8 cpld_read(unsigned int reg);
 void cpld_write(unsigned int reg, u8 value);
 void cpld_rev_bit(unsigned char *value);
+void cpld_select_core_volt(bool en_0v9);
 
 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
 #define CPLD_WRITE(reg, value)  \
diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c
index a9b7dbd..fb4f6ab 100644
--- a/board/freescale/ls1046ardb/ddr.c
+++ b/board/freescale/ls1046ardb/ddr.c
@@ -11,6 +11,7 @@
 #ifdef CONFIG_FSL_DEEP_SLEEP
 #include <fsl_sleep.h>
 #endif
+#include <asm/arch/clock.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -91,14 +92,19 @@ found:
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
 			  DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x70;
 }
 
-phys_size_t initdram(int board_type)
+int fsl_initdram(void)
 {
 	phys_size_t dram_size;
 
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-	return fsl_ddr_sdram_size();
+	gd->ram_size = fsl_ddr_sdram_size();
+
+	return 0;
 #else
 	puts("Initializing DDR....using SPD\n");
 
@@ -107,34 +113,7 @@ phys_size_t initdram(int board_type)
 
 	erratum_a008850_post();
 
-	return dram_size;
-}
+	gd->ram_size = dram_size;
 
-void dram_init_banksize(void)
-{
-	/*
-	 * gd->arch.secure_ram tracks the location of secure memory.
-	 * It was set as if the memory starts from 0.
-	 * The address needs to add the offset of its bank.
-	 */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
-		gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
-		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
-		gd->bd->bi_dram[1].size = gd->ram_size -
-					  CONFIG_SYS_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->arch.secure_ram = gd->bd->bi_dram[1].start +
-				 gd->arch.secure_ram -
-				 CONFIG_SYS_DDR_BLOCK1_SIZE;
-		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
-	} else {
-		gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
-				 gd->arch.secure_ram;
-		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
-	}
+	return 0;
 }
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
index 585c807..33f1afd 100644
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -19,10 +19,20 @@
 #include <fm_eth.h>
 #include <fsl_csu.h>
 #include <fsl_esdhc.h>
+#include <power/mc34vr500_pmic.h>
 #include "cpld.h"
+#include <fsl_sec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
 int checkboard(void)
 {
 	static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
@@ -55,34 +65,67 @@ int checkboard(void)
 	return 0;
 }
 
-int dram_init(void)
+int board_init(void)
 {
-	gd->ram_size = initdram(0);
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+#ifdef CONFIG_SECURE_BOOT
+	/*
+	 * In case of Secure Boot, the IBR configures the SMMU
+	 * to allow only Secure transactions.
+	 * SMMU must be reset in bypass mode.
+	 * Set the ClientPD bit and Clear the USFCFG Bit
+	 */
+	u32 val;
+	val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+	out_le32(SMMU_SCR0, val);
+	val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+	out_le32(SMMU_NSCR0, val);
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+
+	/* invert AQR105 IRQ pins polarity */
+	out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
 
 	return 0;
 }
 
-int board_early_init_f(void)
+int board_setup_core_volt(u32 vdd)
 {
-	fsl_lsch2_early_init_f();
+	bool en_0v9;
+
+	en_0v9 = (vdd == 900) ? true : false;
+	cpld_select_core_volt(en_0v9);
 
 	return 0;
 }
 
-int board_init(void)
+int get_serdes_volt(void)
 {
-	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	return mc34vr500_get_sw_volt(SW4);
+}
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-	enable_layerscape_ns_access();
-#endif
+int set_serdes_volt(int svdd)
+{
+	return mc34vr500_set_sw_volt(SW4, svdd);
+}
 
-#ifdef CONFIG_FSL_LS_PPA
-	ppa_init();
-#endif
+int power_init_board(void)
+{
+	int ret;
 
-	/* invert AQR105 IRQ pins polarity */
-	out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
+	ret = power_mc34vr500_init(0);
+	if (ret)
+		return ret;
+
+	setup_chip_volt();
 
 	return 0;
 }
@@ -134,3 +177,4 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
+#endif
diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
index 6a5076e..ccedf87 100644
--- a/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
+++ b/board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 01ee0100
 # RCW
-0c150010 0e000000 00000000 00000000
+0c150012 0e000000 00000000 00000000
 11335559 40000012 60040000 c1000000
 00000000 00000000 00000000 00238800
 20124000 00003000 00000096 00000001
diff --git a/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg b/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
index d5265b8..d3b1522 100644
--- a/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
+++ b/board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 01ee0100
 # RCW
-0c150010 0e000000 00000000 00000000
+0c150012 0e000000 00000000 00000000
 11335559 40005012 60040000 c1000000
 00000000 00000000 00000000 00238800
 20124000 00003101 00000096 00000001
diff --git a/board/freescale/ls2080a/Kconfig b/board/freescale/ls2080a/Kconfig
index 0b938ff..b503351 100644
--- a/board/freescale/ls2080a/Kconfig
+++ b/board/freescale/ls2080a/Kconfig
@@ -12,6 +12,8 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls2080a_emu"
 
+source "board/freescale/common/Kconfig"
+
 endif
 
 if TARGET_LS2080A_SIMU
@@ -28,4 +30,6 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls2080a_simu"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS
index c8dac99..de137ef 100644
--- a/board/freescale/ls2080a/MAINTAINERS
+++ b/board/freescale/ls2080a/MAINTAINERS
@@ -1,5 +1,5 @@
 LS2080A BOARD
-M:	York Sun <york.sun@nxp.com>
+M:	York Sun <york.sun@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
 F:	board/freescale/ls2080a/
 F:	include/configs/ls2080a_emu.h
diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c
index e6130ec..025e5aa 100644
--- a/board/freescale/ls2080a/ddr.c
+++ b/board/freescale/ls2080a/ddr.c
@@ -8,6 +8,7 @@
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
 #include <asm/arch/soc.h>
+#include <asm/arch/clock.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -158,69 +159,13 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 	return 0;
 }
 #endif
-phys_size_t initdram(int board_type)
-{
-	phys_size_t dram_size;
 
+int fsl_initdram(void)
+{
 	puts("Initializing DDR....");
 
 	puts("using SPD\n");
-	dram_size = fsl_ddr_sdram();
-
-	return dram_size;
-}
-
-void dram_init_banksize(void)
-{
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
-	phys_size_t dp_ddr_size;
-#endif
-
-	/*
-	 * gd->arch.secure_ram tracks the location of secure memory.
-	 * It was set as if the memory starts from 0.
-	 * The address needs to add the offset of its bank.
-	 */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
-		gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
-		gd->bd->bi_dram[1].size = gd->ram_size -
-					  CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->arch.secure_ram = gd->bd->bi_dram[1].start +
-				      gd->arch.secure_ram -
-				      CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
-	} else {
-		gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
-				      gd->arch.secure_ram;
-		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
-	}
+	gd->ram_size = fsl_ddr_sdram();
 
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
-	if (soc_has_dp_ddr()) {
-		/* initialize DP-DDR here */
-		puts("DP-DDR:  ");
-		/*
-		 * DDR controller use 0 as the base address for binding.
-		 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
-		 */
-		dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
-					  CONFIG_DP_DDR_CTRL,
-					  CONFIG_DP_DDR_NUM_CTRLS,
-					  CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
-					  NULL, NULL, NULL);
-		if (dp_ddr_size) {
-			gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
-			gd->bd->bi_dram[2].size = dp_ddr_size;
-		} else {
-			puts("Not detected");
-		}
-	}
-#endif
+	return 0;
 }
diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c
index d0a88d4..41417e9 100644
--- a/board/freescale/ls2080a/ls2080a.c
+++ b/board/freescale/ls2080a/ls2080a.c
@@ -49,13 +49,6 @@ void detail_board_ddr_info(void)
 #endif
 }
 
-int dram_init(void)
-{
-	gd->ram_size = initdram(0);
-
-	return 0;
-}
-
 #if defined(CONFIG_ARCH_MISC_INIT)
 int arch_misc_init(void)
 {
@@ -71,13 +64,13 @@ int board_eth_init(bd_t *bis)
 	error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
 #endif
 
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 	error = cpu_eth_init(bis);
 #endif
 	return error;
 }
 
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 void fdt_fixup_board_enet(void *fdt)
 {
 	int offset;
@@ -102,6 +95,11 @@ void fdt_fixup_board_enet(void *fdt)
 	else
 		fdt_status_fail(fdt, offset);
 }
+
+void board_quiesce_devices(void)
+{
+	fsl_mc_ldpaa_exit(gd->bd);
+}
 #endif
 
 #ifdef CONFIG_OF_BOARD_SETUP
@@ -118,13 +116,28 @@ int ft_board_setup(void *blob, bd_t *bd)
 	base[1] = gd->bd->bi_dram[1].start;
 	size[1] = gd->bd->bi_dram[1].size;
 
+#ifdef CONFIG_RESV_RAM
+	/* reduce size if reserved memory is within this bank */
+	if (gd->arch.resv_ram >= base[0] &&
+	    gd->arch.resv_ram < base[0] + size[0])
+		size[0] = gd->arch.resv_ram - base[0];
+	else if (gd->arch.resv_ram >= base[1] &&
+		 gd->arch.resv_ram < base[1] + size[1])
+		size[1] = gd->arch.resv_ram - base[1];
+#endif
+
 	fdt_fixup_memory_banks(blob, base, size, 2);
 
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 	fdt_fixup_board_enet(blob);
-	fsl_mc_ldpaa_exit(bd);
 #endif
 
 	return 0;
 }
 #endif
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+}
+#endif
diff --git a/board/freescale/ls2080aqds/Kconfig b/board/freescale/ls2080aqds/Kconfig
index 2f997e9..e2b2c8d 100644
--- a/board/freescale/ls2080aqds/Kconfig
+++ b/board/freescale/ls2080aqds/Kconfig
@@ -13,4 +13,6 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls2080aqds"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS
index 8f78b67..62c8fac 100644
--- a/board/freescale/ls2080aqds/MAINTAINERS
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -1,5 +1,5 @@
 LS2080A BOARD
-M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
 F:	board/freescale/ls2080aqds/
 F:	board/freescale/ls2080a/ls2080aqds.c
@@ -7,6 +7,7 @@ F:	include/configs/ls2080aqds.h
 F:	configs/ls2080aqds_defconfig
 F:	configs/ls2080aqds_nand_defconfig
 F:	configs/ls2080aqds_qspi_defconfig
+F:	configs/ls2080aqds_sdcard_defconfig
 
 LS2080A_SECURE_BOOT BOARD
 M:	Saksham Jain <saksham.jain@nxp.freescale.com>
diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index f288750..8e31e9e 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -2,14 +2,14 @@ Overview
 --------
 The LS2080A Development System (QDS) is a high-performance computing,
 evaluation, and development platform that supports the QorIQ LS2080A
-Layerscape Architecture processor. The LS2080AQDS provides validation and
-SW development platform for the Freescale LS2080A processor series, with
-a complete debugging environment.
+and LS2088A Layerscape Architecture processor. The LS2080AQDS provides
+validation and SW development platform for the Freescale LS2080A, LS2088A
+processor series, with a complete debugging environment.
 
-LS2080A SoC Overview
+LS2080A, LS2088A SoC Overview
 --------------------
-Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
-SoC overview.
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
+LS2088A SoC overview.
 
  LS2080AQDS board Overview
  -----------------------
@@ -89,6 +89,32 @@ c) NAND boot
 d) SD boot
 e) QSPI boot
 
+Memory map for NOR boot
+-------------------------
+Image				Flash Offset
+RCW+PBI				0x00000000
+Boot firmware (U-Boot)		0x00100000
+Boot firmware Environment	0x00300000
+PPA firmware			0x00400000
+Secure Headers			0x00600000
+DPAA2 MC			0x00A00000
+DPAA2 DPL			0x00D00000
+DPAA2 DPC			0x00E00000
+Kernel.itb			0x01000000
+
+Memory map for SD boot
+-------------------------
+Image				Flash Offset	SD Card
+						Start Block No.
+RCW+PBI				0x00000000	0x00008
+Boot firmware (U-Boot)		0x00100000	0x00800
+Boot firmware Environment	0x00300000	0x01800
+PPA firmware			0x00400000	0x02000
+DPAA2 MC			0x00A00000	0x05000
+DPAA2 DPL			0x00D00000	0x06800
+DPAA2 DPC			0x00E00000	0x07000
+Kernel.itb			0x01000000	0x08000
+
 Environment Variables
 ---------------------
 - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c
index 9c6f477..20b8c1f 100644
--- a/board/freescale/ls2080aqds/ddr.c
+++ b/board/freescale/ls2080aqds/ddr.c
@@ -8,6 +8,7 @@
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
 #include <asm/arch/soc.h>
+#include <asm/arch/clock.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -155,72 +156,15 @@ found:
 	}
 }
 
-phys_size_t initdram(int board_type)
+int fsl_initdram(void)
 {
-	phys_size_t dram_size;
-
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-	return fsl_ddr_sdram_size();
+	gd->ram_size = fsl_ddr_sdram_size();
 #else
 	puts("Initializing DDR....using SPD\n");
 
-	dram_size = fsl_ddr_sdram();
-#endif
-
-	return dram_size;
-}
-
-void dram_init_banksize(void)
-{
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
-	phys_size_t dp_ddr_size;
+	gd->ram_size = fsl_ddr_sdram();
 #endif
 
-	/*
-	 * gd->arch.secure_ram tracks the location of secure memory.
-	 * It was set as if the memory starts from 0.
-	 * The address needs to add the offset of its bank.
-	 */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
-		gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
-		gd->bd->bi_dram[1].size = gd->ram_size -
-					  CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->arch.secure_ram = gd->bd->bi_dram[1].start +
-				      gd->arch.secure_ram -
-				      CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
-	} else {
-		gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
-				      gd->arch.secure_ram;
-		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
-	}
-
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
-	if (soc_has_dp_ddr()) {
-		/* initialize DP-DDR here */
-		puts("DP-DDR:  ");
-		/*
-		 * DDR controller use 0 as the base address for binding.
-		 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
-		 */
-		dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
-					  CONFIG_DP_DDR_CTRL,
-					  CONFIG_DP_DDR_NUM_CTRLS,
-					  CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
-					  NULL, NULL, NULL);
-		if (dp_ddr_size) {
-			gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
-			gd->bd->bi_dram[2].size = dp_ddr_size;
-		} else {
-			puts("Not detected");
-		}
-	}
-#endif
+	return 0;
 }
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index 95ff68b..defcac5 100644
--- a/board/freescale/ls2080aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -14,6 +14,7 @@
 #include <fm_eth.h>
 #include <i2c.h>
 #include <miiphy.h>
+#include <fsl-mc/fsl_mc.h>
 #include <fsl-mc/ldpaa_wriop.h>
 
 #include "../common/qixis.h"
@@ -22,7 +23,7 @@
 
 #define MC_BOOT_ENV_VAR "mcinitcmd"
 
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
  *   Bank 1 -> Lanes A, B, C, D, E, F, G, H
  *   Bank 2 -> Lanes A,B, C, D, E, F, G, H
@@ -64,7 +65,7 @@ static int sgmii_riser_phy_addr[] = {
 };
 
 /* Slot2 does not have EMI connections */
-#define EMI_NONE	0xFFFFFFFF
+#define EMI_NONE	0xFF
 #define EMI1_SLOT1	0
 #define EMI1_SLOT2	1
 #define EMI1_SLOT3	2
@@ -144,8 +145,10 @@ static void sgmii_configure_repeater(int serdes_port)
 
 		mdelay(10);
 
-		if ((value & 0xfff) == 0x40f) {
+		if ((value & 0xfff) == 0x401) {
 			printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
+			miiphy_write(dev[mii_bus], riser_phy_addr[dpmac],
+				     0x1f, 0);
 			continue;
 		}
 
@@ -181,28 +184,29 @@ static void sgmii_configure_repeater(int serdes_port)
 				if (ret > 0)
 					goto error;
 
-				mdelay(1);
+				mdelay(100);
 				ret = miiphy_read(dev[mii_bus],
 						  riser_phy_addr[dpmac],
 						  0x11, &value);
 				if (ret > 0)
 					goto error;
-				mdelay(10);
 
-				if ((value & 0xfff) == 0x40f) {
+				if ((value & 0xfff) == 0x401) {
 					printf("DPMAC %d :PHY is configured ",
 					       dpmac_id);
 					printf("after setting repeater 0x%x\n",
 					       value);
 					i = 5;
 					j = 5;
-				} else
+				} else {
 					printf("DPMAC %d :PHY is failed to ",
 					       dpmac_id);
 					printf("configure the repeater 0x%x\n",
 					       value);
 				}
+			}
 		}
+		miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0);
 	}
 error:
 	if (ret)
@@ -470,7 +474,49 @@ static void initialize_dpmac_to_slot(void)
 		}
 		break;
 
+	case 0x39:
+		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		if (hwconfig_f("xqsgmii", env_hwconfig)) {
+			lane_to_slot_fsm1[0] = EMI1_SLOT3;
+			lane_to_slot_fsm1[1] = EMI1_SLOT3;
+			lane_to_slot_fsm1[2] = EMI1_SLOT3;
+			lane_to_slot_fsm1[3] = EMI_NONE;
+		} else {
+			lane_to_slot_fsm1[0] = EMI_NONE;
+			lane_to_slot_fsm1[1] = EMI_NONE;
+			lane_to_slot_fsm1[2] = EMI_NONE;
+			lane_to_slot_fsm1[3] = EMI_NONE;
+		}
+		lane_to_slot_fsm1[4] = EMI1_SLOT3;
+		lane_to_slot_fsm1[5] = EMI1_SLOT3;
+		lane_to_slot_fsm1[6] = EMI1_SLOT3;
+		lane_to_slot_fsm1[7] = EMI_NONE;
+		break;
+
+	case 0x4D:
+		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
+		       serdes1_prtcl);
+		if (hwconfig_f("xqsgmii", env_hwconfig)) {
+			lane_to_slot_fsm1[0] = EMI1_SLOT3;
+			lane_to_slot_fsm1[1] = EMI1_SLOT3;
+			lane_to_slot_fsm1[2] = EMI_NONE;
+			lane_to_slot_fsm1[3] = EMI_NONE;
+		} else {
+			lane_to_slot_fsm1[0] = EMI_NONE;
+			lane_to_slot_fsm1[1] = EMI_NONE;
+			lane_to_slot_fsm1[2] = EMI_NONE;
+			lane_to_slot_fsm1[3] = EMI_NONE;
+		}
+		lane_to_slot_fsm1[4] = EMI1_SLOT3;
+		lane_to_slot_fsm1[5] = EMI1_SLOT3;
+		lane_to_slot_fsm1[6] = EMI_NONE;
+		lane_to_slot_fsm1[7] = EMI_NONE;
+		break;
+
 	case 0x2A:
+	case 0x4B:
+	case 0x4C:
 		printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 		       serdes1_prtcl);
 		break;
@@ -505,6 +551,38 @@ static void initialize_dpmac_to_slot(void)
 			lane_to_slot_fsm2[7] = EMI1_SLOT6;
 		}
 		break;
+
+	case 0x47:
+		printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
+		       serdes2_prtcl);
+		lane_to_slot_fsm2[0] = EMI_NONE;
+		lane_to_slot_fsm2[1] = EMI1_SLOT5;
+		lane_to_slot_fsm2[2] = EMI1_SLOT5;
+		lane_to_slot_fsm2[3] = EMI1_SLOT5;
+
+		if (hwconfig_f("xqsgmii", env_hwconfig)) {
+			lane_to_slot_fsm2[4] = EMI_NONE;
+			lane_to_slot_fsm2[5] = EMI1_SLOT5;
+			lane_to_slot_fsm2[6] = EMI1_SLOT5;
+			lane_to_slot_fsm2[7] = EMI1_SLOT5;
+		}
+		break;
+
+	case 0x57:
+		printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
+		       serdes2_prtcl);
+		if (hwconfig_f("xqsgmii", env_hwconfig)) {
+			lane_to_slot_fsm2[0] = EMI_NONE;
+			lane_to_slot_fsm2[1] = EMI_NONE;
+			lane_to_slot_fsm2[2] = EMI_NONE;
+			lane_to_slot_fsm2[3] = EMI_NONE;
+		}
+		lane_to_slot_fsm2[4] = EMI_NONE;
+		lane_to_slot_fsm2[5] = EMI_NONE;
+		lane_to_slot_fsm2[6] = EMI1_SLOT5;
+		lane_to_slot_fsm2[7] = EMI1_SLOT5;
+		break;
+
 	default:
 		printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
 		       __func__ , serdes2_prtcl);
@@ -537,8 +615,10 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
 
 	switch (serdes1_prtcl) {
 	case 0x07:
+	case 0x39:
+	case 0x4D:
+		lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1);
 
-		lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id);
 		slot = lane_to_slot_fsm1[lane];
 
 		switch (++slot) {
@@ -559,6 +639,26 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
 			wriop_set_mdio(dpmac_id, bus);
 			break;
 		case 3:
+			if (slot == EMI_NONE)
+				return;
+			if (serdes1_prtcl == 0x39) {
+				wriop_set_phy_address(dpmac_id,
+					riser_phy_addr[dpmac_id - 2]);
+				if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
+								env_hwconfig))
+					wriop_set_phy_address(dpmac_id,
+						riser_phy_addr[dpmac_id - 3]);
+			} else {
+				wriop_set_phy_address(dpmac_id,
+					riser_phy_addr[dpmac_id - 2]);
+				if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
+								env_hwconfig))
+					wriop_set_phy_address(dpmac_id,
+						riser_phy_addr[dpmac_id - 3]);
+			}
+			dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
+			bus = mii_dev_for_muxval(EMI1_SLOT3);
+			wriop_set_mdio(dpmac_id, bus);
 			break;
 		case 4:
 			break;
@@ -579,6 +679,8 @@ serdes2:
 	case 0x07:
 	case 0x08:
 	case 0x49:
+	case 0x47:
+	case 0x57:
 		lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
 							(dpmac_id - 9));
 		slot = lane_to_slot_fsm2[lane];
@@ -597,7 +699,23 @@ serdes2:
 			wriop_set_mdio(dpmac_id, bus);
 		break;
 		case 5:
-		break;
+			if (slot == EMI_NONE)
+				return;
+			if (serdes2_prtcl == 0x47) {
+				wriop_set_phy_address(dpmac_id,
+					      riser_phy_addr[dpmac_id - 10]);
+				if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
+								 env_hwconfig))
+					wriop_set_phy_address(dpmac_id,
+						riser_phy_addr[dpmac_id - 11]);
+			} else {
+				wriop_set_phy_address(dpmac_id,
+					riser_phy_addr[dpmac_id - 11]);
+			}
+			dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
+			bus = mii_dev_for_muxval(EMI1_SLOT5);
+			wriop_set_mdio(dpmac_id, bus);
+			break;
 		case 6:
 			/* Slot housing a SGMII riser card? */
 			wriop_set_phy_address(dpmac_id,
@@ -691,6 +809,8 @@ void ls2080a_handle_phy_interface_xsgmii(int i)
 
 	switch (serdes1_prtcl) {
 	case 0x2A:
+	case 0x4B:
+	case 0x4C:
 		/*
 		 * XFI does not need a PHY to work, but to avoid U-Boot use
 		 * default PHY address which is zero to a MAC when it found
@@ -715,8 +835,7 @@ void ls2080a_handle_phy_interface_xsgmii(int i)
 int board_eth_init(bd_t *bis)
 {
 	int error;
-	char *mc_boot_env_var;
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 	int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
 				FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
@@ -783,9 +902,6 @@ int board_eth_init(bd_t *bis)
 		}
 	}
 
-	mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
-	if (mc_boot_env_var)
-		run_command_list(mc_boot_env_var, -1, 0);
 	error = cpu_eth_init(bis);
 
 	if (hwconfig_f("xqsgmii", env_hwconfig)) {
@@ -800,6 +916,9 @@ int board_eth_init(bd_t *bis)
 	return error;
 }
 
-#ifdef CONFIG_FSL_MC_ENET
-
-#endif
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+	mc_env_boot();
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index ca4a2e5..f36fb98 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -19,9 +19,12 @@
 #include <asm/arch/soc.h>
 #include <hwconfig.h>
 #include <fsl_sec.h>
+#include <asm/arch/ppa.h>
+
 
 #include "../common/qixis.h"
 #include "ls2080aqds_qixis.h"
+#include "../common/vid.h"
 
 #define PIN_MUX_SEL_SDHC	0x00
 #define PIN_MUX_SEL_DSPI	0x0a
@@ -224,6 +227,14 @@ int board_init(void)
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 	rtc_enable_32khz_output();
 
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
+
 	return 0;
 }
 
@@ -240,6 +251,14 @@ int board_early_init_f(void)
 	return 0;
 }
 
+int misc_init_r(void)
+{
+	if (adjust_vdd(0))
+		printf("Warning: Adjusting core voltage failed.\n");
+
+	return 0;
+}
+
 void detail_board_ddr_info(void)
 {
 	puts("\nDDR    ");
@@ -254,24 +273,14 @@ void detail_board_ddr_info(void)
 #endif
 }
 
-int dram_init(void)
-{
-	gd->ram_size = initdram(0);
-
-	return 0;
-}
-
 #if defined(CONFIG_ARCH_MISC_INIT)
 int arch_misc_init(void)
 {
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
 	return 0;
 }
 #endif
 
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 void fdt_fixup_board_enet(void *fdt)
 {
 	int offset;
@@ -292,14 +301,16 @@ void fdt_fixup_board_enet(void *fdt)
 	else
 		fdt_status_fail(fdt, offset);
 }
+
+void board_quiesce_devices(void)
+{
+	fsl_mc_ldpaa_exit(gd->bd);
+}
 #endif
 
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
-#ifdef CONFIG_FSL_MC_ENET
-	int err;
-#endif
 	u64 base[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
 
@@ -311,15 +322,22 @@ int ft_board_setup(void *blob, bd_t *bd)
 	base[1] = gd->bd->bi_dram[1].start;
 	size[1] = gd->bd->bi_dram[1].size;
 
+#ifdef CONFIG_RESV_RAM
+	/* reduce size if reserved memory is within this bank */
+	if (gd->arch.resv_ram >= base[0] &&
+	    gd->arch.resv_ram < base[0] + size[0])
+		size[0] = gd->arch.resv_ram - base[0];
+	else if (gd->arch.resv_ram >= base[1] &&
+		 gd->arch.resv_ram < base[1] + size[1])
+		size[1] = gd->arch.resv_ram - base[1];
+#endif
+
 	fdt_fixup_memory_banks(blob, base, size, 2);
 
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 	fdt_fixup_board_enet(blob);
-	err = fsl_mc_ldpaa_exit(bd);
-	if (err)
-		return err;
 #endif
 
 	return 0;
diff --git a/board/freescale/ls2080ardb/Kconfig b/board/freescale/ls2080ardb/Kconfig
index fe02575..8f64642 100644
--- a/board/freescale/ls2080ardb/Kconfig
+++ b/board/freescale/ls2080ardb/Kconfig
@@ -13,4 +13,24 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "ls2080ardb"
 
+source "board/freescale/common/Kconfig"
+
+endif
+
+if TARGET_LS2081ARDB
+
+config SYS_BOARD
+	default "ls2080ardb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls2080ardb"
+
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index a20c003..91f13ea 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -1,5 +1,5 @@
 LS2080A BOARD
-M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
 F:	board/freescale/ls2080ardb/
 F:	board/freescale/ls2080a/ls2080ardb.c
@@ -7,6 +7,16 @@ F:	include/configs/ls2080ardb.h
 F:	configs/ls2080ardb_defconfig
 F:	configs/ls2080ardb_nand_defconfig
 
+LS2088A_QSPI-boot BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	configs/ls2088ardb_qspi_defconfig
+
+LS2081ARDB BOARD
+M:	Priyanka Jain <priyanka.jain@nxp.com>
+S:	Maintained
+F:	configs/ls2081ardb_defconfig
+
 LS2080A_SECURE_BOOT BOARD
 M:	Saksham Jain <saksham.jain@nxp.freescale.com>
 S:	Maintained
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index b1613ba..205c45c 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -1,13 +1,17 @@
 Overview
 --------
 The LS2080A Reference Design (RDB) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2080A
+evaluation, and development platform that supports the QorIQ LS2080A, LS2088A
 Layerscape Architecture processor.
 
-LS2080A SoC Overview
---------------------
-Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
-SoC overview.
+The LS2081A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2081A
+Layerscape Architecture processor.More details in below sections
+
+LS2080A, LS2088A, LS2081A SoC Overview
+--------------------------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
+LS2081A, LS2088A SoC overview.
 
  LS2080ARDB board Overview
  -----------------------
@@ -38,11 +42,22 @@ SoC overview.
  - UART
  - ARM JTAG support
 
+ LS2081ARDB board Overview
+ -------------------------
+ LS2081ARDB board is similar to LS2080ARDB board
+ with few differences like
+  - Hosts LS2081A SoC
+  - Default boot source is QSPI-boot
+  - Does not have IFC interface
+  - RTC and QSPI flash devices are different
+  - Provides QIXIS access via I2C
+
 Memory map from core's view
 ----------------------------
 0x00_0000_0000 .. 0x00_000F_FFFF	Boot Rom
 0x00_0100_0000 .. 0x00_0FFF_FFFF	CCSR
 0x00_1800_0000 .. 0x00_181F_FFFF	OCRAM
+0x00_2000_0000 .. 0x00_2FFF_FFFF	QSPI region #1
 0x00_3000_0000 .. 0x00_3FFF_FFFF	IFC region #1
 0x00_8000_0000 .. 0x00_FFFF_FFFF	DDR region #1
 0x05_1000_0000 .. 0x05_FFFF_FFFF	IFC region #2
@@ -68,6 +83,45 @@ Booting Options
 ---------------
 a) NOR boot
 b) NAND boot
+c) QSPI boot
+
+Memory map for NOR boot
+-------------------------
+Image				Flash Offset
+RCW+PBI				0x00000000
+Boot firmware (U-Boot)		0x00100000
+Boot firmware Environment	0x00300000
+PPA firmware			0x00400000
+Secure Headers			0x00600000
+Cortina PHY firmware		0x00980000
+DPAA2 MC			0x00A00000
+DPAA2 DPL			0x00D00000
+DPAA2 DPC			0x00E00000
+Kernel.itb			0x01000000
+
+cfg_rcw_src switches needs to be changed for booting from different option.
+Refer to board documentation for correct switch setting.
+
+QSPI boot details
+===================
+Supported only for
+ LS2088ARDB RevF board with LS2088A SoC.
+
+Images needs to be copied to QSPI flash
+as per memory map given below.
+
+Memory map for QSPI flash
+-------------------------
+Image				Flash Offset
+RCW+PBI				0x00000000
+Boot firmware (U-Boot)		0x00100000
+Boot firmware Environment	0x00300000
+PPA firmware			0x00400000
+Cortina PHY firmware		0x00980000
+DPAA2 MC			0x00A00000
+DPAA2 DPL			0x00D00000
+DPAA2 DPC			0x00E00000
+Kernel.itb			0x01000000
 
 Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
 -------------------------------------------------------------------
diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c
index ecd1e71..01f7d82 100644
--- a/board/freescale/ls2080ardb/ddr.c
+++ b/board/freescale/ls2080ardb/ddr.c
@@ -8,6 +8,7 @@
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
 #include <asm/arch/soc.h>
+#include <asm/arch/clock.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -134,6 +135,9 @@ found:
 	/* Enable ZQ calibration */
 	popts->zq_en = 1;
 
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x6e;
+
 	if (ddr_freq < 2350) {
 		if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
 			/* four chip-selects */
@@ -155,72 +159,15 @@ found:
 	}
 }
 
-phys_size_t initdram(int board_type)
+int fsl_initdram(void)
 {
-	phys_size_t dram_size;
-
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-	return fsl_ddr_sdram_size();
+	gd->ram_size = fsl_ddr_sdram_size();
 #else
 	puts("Initializing DDR....using SPD\n");
 
-	dram_size = fsl_ddr_sdram();
-#endif
-
-	return dram_size;
-}
-
-void dram_init_banksize(void)
-{
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
-	phys_size_t dp_ddr_size;
-#endif
-
-	/*
-	 * gd->arch.secure_ram tracks the location of secure memory.
-	 * It was set as if the memory starts from 0.
-	 * The address needs to add the offset of its bank.
-	 */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
-		gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
-		gd->bd->bi_dram[1].size = gd->ram_size -
-					  CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->arch.secure_ram = gd->bd->bi_dram[1].start +
-				      gd->arch.secure_ram -
-				      CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
-		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-#endif
-	} else {
-		gd->bd->bi_dram[0].size = gd->ram_size;
-#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
-				      gd->arch.secure_ram;
-		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+	gd->ram_size = fsl_ddr_sdram();
 #endif
-	}
 
-#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
-	if (soc_has_dp_ddr()) {
-		/* initialize DP-DDR here */
-		puts("DP-DDR:  ");
-		/*
-		 * DDR controller use 0 as the base address for binding.
-		 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
-		 */
-		dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
-					  CONFIG_DP_DDR_CTRL,
-					  CONFIG_DP_DDR_NUM_CTRLS,
-					  CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
-					  NULL, NULL, NULL);
-		if (dp_ddr_size) {
-			gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
-			gd->bd->bi_dram[2].size = dp_ddr_size;
-		} else {
-			puts("Not detected");
-		}
-	}
-#endif
+	return 0;
 }
diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index 799799c..32677f7 100644
--- a/board/freescale/ls2080ardb/eth_ls2080rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -16,15 +16,14 @@
 #include <asm/io.h>
 #include <exports.h>
 #include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/fsl_mc.h>
 #include <fsl-mc/ldpaa_wriop.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define MC_BOOT_ENV_VAR "mcinitcmd"
 int board_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FSL_MC_ENET)
-	char *mc_boot_env_var;
 	int i, interface;
 	struct memac_mdio_info mdio_info;
 	struct mii_dev *dev;
@@ -62,6 +61,13 @@ int board_eth_init(bd_t *bis)
 		wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
 
 		break;
+	case 0x4B:
+		wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
+		wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
+		wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
+		wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
+
+		break;
 	default:
 		printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
 		       srds_s1);
@@ -91,11 +97,8 @@ int board_eth_init(bd_t *bis)
 		}
 	}
 
-	mc_boot_env_var = getenv(MC_BOOT_ENV_VAR);
-	if (mc_boot_env_var)
-		run_command_list(mc_boot_env_var, -1, 0);
 	cpu_eth_init(bis);
-#endif /* CONFIG_FMAN_ENET */
+#endif /* CONFIG_FSL_MC_ENET */
 
 #ifdef CONFIG_PHY_AQUANTIA
 	/*
@@ -111,3 +114,10 @@ int board_eth_init(bd_t *bis)
 #endif
 	return pci_eth_init(bis);
 }
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+	mc_env_boot();
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 7d8a711..d7122b3 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright (C) 2017 NXP Semiconductors
  * Copyright 2015 Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -15,12 +16,17 @@
 #include <libfdt.h>
 #include <fsl-mc/fsl_mc.h>
 #include <environment.h>
+#include <efi_loader.h>
 #include <i2c.h>
+#include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
+#include <asm/arch/ppa.h>
 #include <fsl_sec.h>
 
+#ifdef CONFIG_FSL_QIXIS
 #include "../common/qixis.h"
 #include "ls2080ardb_qixis.h"
+#endif
 #include "../common/vid.h"
 
 #define PIN_MUX_SEL_SDHC	0x00
@@ -54,12 +60,53 @@ unsigned long long get_qixis_addr(void)
 
 int checkboard(void)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 sw;
+#endif
 	char buf[15];
 
 	cpu_name(buf);
 	printf("Board: %s-RDB, ", buf);
 
+#ifdef CONFIG_TARGET_LS2081ARDB
+#ifdef CONFIG_FSL_QIXIS
+	sw = QIXIS_READ(arch);
+	printf("Board Arch: V%d, ", sw >> 4);
+	printf("Board version: %c, ", (sw & 0xf) + 'A');
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
+	switch (sw) {
+	case 0:
+		puts("boot from QSPI DEV#0\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
+		break;
+	case 1:
+		puts("boot from QSPI DEV#1\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
+		break;
+	case 2:
+		puts("boot from QSPI EMU\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
+		break;
+	case 3:
+		puts("boot from QSPI EMU\n");
+		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
+		break;
+	case 4:
+		puts("boot from QSPI DEV#0\n");
+		puts("QSPI_CSA_1 mapped to QSPI EMU\n");
+		break;
+	default:
+		printf("invalid setting of SW%u\n", sw);
+		break;
+	}
+#endif
+	puts("SERDES1 Reference : ");
+	printf("Clock1 = 100MHz ");
+	printf("Clock2 = 161.13MHz");
+#else
+#ifdef CONFIG_FSL_QIXIS
 	sw = QIXIS_READ(arch);
 	printf("Board Arch: V%d, ", sw >> 4);
 	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
@@ -75,10 +122,11 @@ int checkboard(void)
 		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 
 	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
-
+#endif
 	puts("SERDES1 Reference : ");
 	printf("Clock1 = 156.25MHz ");
 	printf("Clock2 = 156.25MHz");
+#endif
 
 	puts("\nSERDES2 Reference : ");
 	printf("Clock1 = 100MHz ");
@@ -89,6 +137,7 @@ int checkboard(void)
 
 unsigned long get_board_sys_clk(void)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 
 	switch (sysclk_conf & 0x0F) {
@@ -107,7 +156,8 @@ unsigned long get_board_sys_clk(void)
 	case QIXIS_SYSCLK_166:
 		return 166666666;
 	}
-	return 66666666;
+#endif
+	return 100000000;
 }
 
 int select_i2c_ch_pca9547(u8 ch)
@@ -130,6 +180,7 @@ int i2c_multiplexer_select_vid_channel(u8 channel)
 
 int config_board_mux(int ctrl_type)
 {
+#ifdef CONFIG_FSL_QIXIS
 	u8 reg5;
 
 	reg5 = QIXIS_READ(brdcfg[5]);
@@ -147,54 +198,77 @@ int config_board_mux(int ctrl_type)
 	}
 
 	QIXIS_WRITE(brdcfg[5], reg5);
-
+#endif
 	return 0;
 }
 
 int board_init(void)
 {
-	char *env_hwconfig;
-	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 #ifdef CONFIG_FSL_MC_ENET
 	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 #endif
-	u32 val;
 
 	init_final_memctl_regs();
 
-	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
-
-	env_hwconfig = getenv("hwconfig");
-
-	if (hwconfig_f("dspi", env_hwconfig) &&
-	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
-		config_board_mux(MUX_TYPE_DSPI);
-	else
-		config_board_mux(MUX_TYPE_SDHC);
-
 #ifdef CONFIG_ENV_IS_NOWHERE
 	gd->env_addr = (ulong)&default_environment[0];
 #endif
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 
+#ifdef CONFIG_FSL_QIXIS
 	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
+#endif
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
 
 #ifdef CONFIG_FSL_MC_ENET
 	/* invert AQR405 IRQ pins polarity */
 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 #endif
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
 
 	return 0;
 }
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+	i2c_early_init_f();
+#endif
 	fsl_lsch3_early_init_f();
 	return 0;
 }
 
 int misc_init_r(void)
 {
+	char *env_hwconfig;
+	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+	u32 val;
+
+	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
+
+	env_hwconfig = getenv("hwconfig");
+
+	if (hwconfig_f("dspi", env_hwconfig) &&
+	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
+		config_board_mux(MUX_TYPE_DSPI);
+	else
+		config_board_mux(MUX_TYPE_SDHC);
+
+	/*
+	 * LS2081ARDB RevF board has smart voltage translator
+	 * which needs to be programmed to enable high speed SD interface
+	 * by setting GPIO4_10 output to zero
+	 */
+#ifdef CONFIG_TARGET_LS2081ARDB
+		out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
+					    in_le32(GPIO4_GPDIR_ADDR)));
+		out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
+					    in_le32(GPIO4_GPDAT_ADDR)));
+#endif
 	if (hwconfig("sdhc"))
 		config_board_mux(MUX_TYPE_SDHC);
 
@@ -218,19 +292,9 @@ void detail_board_ddr_info(void)
 #endif
 }
 
-int dram_init(void)
-{
-	gd->ram_size = initdram(0);
-
-	return 0;
-}
-
 #if defined(CONFIG_ARCH_MISC_INIT)
 int arch_misc_init(void)
 {
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
 	return 0;
 }
 #endif
@@ -256,14 +320,42 @@ void fdt_fixup_board_enet(void *fdt)
 	else
 		fdt_status_fail(fdt, offset);
 }
+
+void board_quiesce_devices(void)
+{
+	fsl_mc_ldpaa_exit(gd->bd);
+}
 #endif
 
 #ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
+void fsl_fdt_fixup_flash(void *fdt)
 {
-#ifdef CONFIG_FSL_MC_ENET
-	int err;
+	int offset;
+
+/*
+ * IFC and QSPI are muxed on board.
+ * So disable IFC node in dts if QSPI is enabled or
+ * disable QSPI node in dts in case QSPI is not enabled.
+ */
+#ifdef CONFIG_FSL_QSPI
+	offset = fdt_path_offset(fdt, "/soc/ifc");
+
+	if (offset < 0)
+		offset = fdt_path_offset(fdt, "/ifc");
+#else
+	offset = fdt_path_offset(fdt, "/soc/quadspi");
+
+	if (offset < 0)
+		offset = fdt_path_offset(fdt, "/quadspi");
 #endif
+	if (offset < 0)
+		return;
+
+	fdt_status_disabled(fdt, offset);
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
 	u64 base[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
 
@@ -275,15 +367,24 @@ int ft_board_setup(void *blob, bd_t *bd)
 	base[1] = gd->bd->bi_dram[1].start;
 	size[1] = gd->bd->bi_dram[1].size;
 
+#ifdef CONFIG_RESV_RAM
+	/* reduce size if reserved memory is within this bank */
+	if (gd->arch.resv_ram >= base[0] &&
+	    gd->arch.resv_ram < base[0] + size[0])
+		size[0] = gd->arch.resv_ram - base[0];
+	else if (gd->arch.resv_ram >= base[1] &&
+		 gd->arch.resv_ram < base[1] + size[1])
+		size[1] = gd->arch.resv_ram - base[1];
+#endif
+
 	fdt_fixup_memory_banks(blob, base, size, 2);
 
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
+
+	fsl_fdt_fixup_flash(blob);
 
 #ifdef CONFIG_FSL_MC_ENET
 	fdt_fixup_board_enet(blob);
-	err = fsl_mc_ldpaa_exit(bd);
-	if (err)
-		return err;
 #endif
 
 	return 0;
@@ -292,6 +393,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 void qixis_dump_switch(void)
 {
+#ifdef CONFIG_FSL_QIXIS
 	int i, nr_of_cfgsw;
 
 	QIXIS_WRITE(cms[0], 0x00);
@@ -302,6 +404,7 @@ void qixis_dump_switch(void)
 		QIXIS_WRITE(cms[0], i);
 		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 	}
+#endif
 }
 
 /*
@@ -312,6 +415,8 @@ void update_spd_address(unsigned int ctrl_num,
 			unsigned int slot,
 			unsigned int *addr)
 {
+#ifndef CONFIG_TARGET_LS2081ARDB
+#ifdef CONFIG_FSL_QIXIS
 	u8 sw;
 
 	sw = QIXIS_READ(arch);
@@ -321,4 +426,6 @@ void update_spd_address(unsigned int ctrl_num,
 		else if (ctrl_num == 1 && slot == 1)
 			*addr = SPD_EEPROM_ADDRESS3;
 	}
+#endif
+#endif
 }
diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c
index 1df128b..4b841c6 100644
--- a/board/freescale/m5208evbe/m5208evbe.c
+++ b/board/freescale/m5208evbe/m5208evbe.c
@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
@@ -68,7 +68,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m52277evb/README b/board/freescale/m52277evb/README
index 92a8384..89e033e 100644
--- a/board/freescale/m52277evb/README
+++ b/board/freescale/m52277evb/README
@@ -83,7 +83,6 @@ CONFIG_MCFTMR		-- define to use DMA timer
 CONFIG_MCFPIT		-- define to use PIT timer
 
 CONFIG_SYS_I2C_FSL	-- define to use FSL common I2C driver
-CONFIG_HARD_I2C		-- define for I2C hardware support
 CONFIG_SYS_I2C_SOFT	-- define for I2C bit-banged
 CONFIG_SYS_I2C_SPEED		-- define for I2C speed
 CONFIG_SYS_I2C_SLAVE		-- define for I2C slave address
diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c
index a1127e5..e4dfb6f 100644
--- a/board/freescale/m52277evb/m52277evb.c
+++ b/board/freescale/m52277evb/m52277evb.c
@@ -21,7 +21,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	u32 dramsize;
 
@@ -78,7 +78,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 #endif
-	return (dramsize);
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index 68c1631..93403f6 100644
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
@@ -97,7 +97,9 @@ phys_size_t initdram(int board_type)
 		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
 	}
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c
index 7ae842c..7c9b599 100644
--- a/board/freescale/m5249evb/m5249evb.c
+++ b/board/freescale/m5249evb/m5249evb.c
@@ -10,6 +10,8 @@
 #include <malloc.h>
 #include <asm/immap.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard (void) {
 	ulong val;
 	uchar val8;
@@ -29,7 +31,8 @@ int checkboard (void) {
 };
 
 
-phys_size_t initdram (int board_type) {
+int dram_init(void)
+{
 	unsigned long	junk = 0xa5a59696;
 
 	/*
@@ -81,7 +84,9 @@ phys_size_t initdram (int board_type) {
 	mbar_writeLong(MCFSIM_DACR0, 0x0000b364);  /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
 	*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
 
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
 };
 
 
diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c
index 071701d..099deca 100644
--- a/board/freescale/m5253demo/flash.c
+++ b/board/freescale/m5253demo/flash.c
@@ -31,7 +31,7 @@ typedef volatile unsigned short FLASH_PORT_WIDTHV;
 ulong flash_get_size(FPWV * addr, flash_info_t * info);
 int flash_get_offsets(ulong base, flash_info_t * info);
 int write_word(flash_info_t * info, FPWV * dest, u16 data);
-void inline spin_wheel(void);
+static inline void spin_wheel(void);
 
 flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
@@ -439,7 +439,7 @@ int write_word(flash_info_t * info, FPWV * dest, u16 data)
 	return (res);
 }
 
-void inline spin_wheel(void)
+static inline void spin_wheel(void)
 {
 	static int p = 0;
 	static char w[] = "\\/-";
diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c
index 7e516bf..3318368 100644
--- a/board/freescale/m5253demo/m5253demo.c
+++ b/board/freescale/m5253demo/m5253demo.c
@@ -13,6 +13,8 @@
 #include <netdev.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard(void)
 {
 	puts("Board: ");
@@ -20,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	u32 dramsize = 0;
 
@@ -73,7 +75,9 @@ phys_size_t initdram(int board_type)
 		mb();
 	}
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 }
 
 int testdram(void)
@@ -84,7 +88,7 @@ int testdram(void)
 	return (0);
 }
 
-#ifdef CONFIG_CMD_IDE
+#ifdef CONFIG_IDE
 #include <ata.h>
 int ide_preinit(void)
 {
@@ -129,7 +133,7 @@ void ide_set_reset(int idereset)
 		setbits_8(&ata->cr, 0x01);
 	}
 }
-#endif				/* CONFIG_CMD_IDE */
+#endif				/* CONFIG_IDE */
 
 
 #ifdef CONFIG_DRIVER_DM9000
diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c
index 15ff755..2c6afad 100644
--- a/board/freescale/m5253evbe/m5253evbe.c
+++ b/board/freescale/m5253evbe/m5253evbe.c
@@ -12,6 +12,8 @@
 #include <asm/immap.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int checkboard(void)
 {
 	puts("Board: ");
@@ -19,7 +21,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	/*
 	 * Check to see if the SDRAM has already been initialized
@@ -66,7 +68,9 @@ phys_size_t initdram(int board_type)
 		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
 	}
 
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
 }
 
 int testdram(void)
@@ -77,7 +81,7 @@ int testdram(void)
 	return (0);
 }
 
-#ifdef CONFIG_CMD_IDE
+#ifdef CONFIG_IDE
 #include <ata.h>
 int ide_preinit(void)
 {
@@ -122,4 +126,4 @@ void ide_set_reset(int idereset)
 		setbits_8(&ata->cr, 0x01);
 	}
 }
-#endif				/* CONFIG_CMD_IDE */
+#endif				/* CONFIG_IDE */
diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c
index 3ed4a7d..efff465 100644
--- a/board/freescale/m5272c3/m5272c3.c
+++ b/board/freescale/m5272c3/m5272c3.c
@@ -11,6 +11,7 @@
 #include <asm/immap.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 
 int checkboard (void) {
 	puts ("Board: ");
@@ -18,7 +19,8 @@ int checkboard (void) {
 	return 0;
 	};
 
-phys_size_t initdram (int board_type) {
+int dram_init(void)
+{
 	sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
 
 	out_be16(&sdp->sdram_sdtr, 0xf539);
@@ -27,7 +29,9 @@ phys_size_t initdram (int board_type) {
 	/* Dummy write to start SDRAM */
 	*((volatile unsigned long *)0) = 0;
 
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
 	};
 
 int testdram (void) {
diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c
index 16083d1..5a9831d 100644
--- a/board/freescale/m5275evb/m5275evb.c
+++ b/board/freescale/m5275evb/m5275evb.c
@@ -13,6 +13,8 @@
 #include <asm/immap.h>
 #include <asm/io.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define PERIOD		13	/* system bus period in ns */
 #define SDRAM_TREFI	7800	/* in ns */
 
@@ -23,7 +25,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
 	gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
@@ -88,7 +90,9 @@ phys_size_t initdram(int board_type)
 		| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
 		| MCF_SDRAMC_SDCR_DQS_OE(0x3));
 
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c
index 39f12fb..eb618b5 100644
--- a/board/freescale/m5282evb/m5282evb.c
+++ b/board/freescale/m5282evb/m5282evb.c
@@ -16,7 +16,7 @@ int checkboard (void)
 	return 0;
 }
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	u32 dramsize, i, dramclk;
 
@@ -80,5 +80,7 @@ phys_size_t initdram (int board_type)
 		/* Write to the SDRAM Mode Register */
 		*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
 	}
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 }
diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README
index 224e79c..2fca12c 100644
--- a/board/freescale/m53017evb/README
+++ b/board/freescale/m53017evb/README
@@ -91,7 +91,6 @@ CONFIG_MCFTMR			-- define to use DMA timer
 CONFIG_MCFPIT			-- define to use PIT timer
 
 CONFIG_SYS_I2C_FSL		-- define to use FSL common I2C driver
-CONFIG_HARD_I2C			-- define for I2C hardware support
 CONFIG_SYS_I2C_SOFT		-- define for I2C bit-banged
 CONFIG_SYS_I2C_SPEED		-- define for I2C speed
 CONFIG_SYS_I2C_SLAVE		-- define for I2C slave address
diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c
index dbe886b..71cca35 100644
--- a/board/freescale/m53017evb/m53017evb.c
+++ b/board/freescale/m53017evb/m53017evb.c
@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
@@ -68,7 +68,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c
index 1f77adf..4e0b4e4 100644
--- a/board/freescale/m5329evb/m5329evb.c
+++ b/board/freescale/m5329evb/m5329evb.c
@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
@@ -62,7 +62,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README
index 582e0c3..757f0ab 100644
--- a/board/freescale/m5373evb/README
+++ b/board/freescale/m5373evb/README
@@ -90,7 +90,6 @@ CONFIG_MCFTMR		-- define to use DMA timer
 CONFIG_MCFPIT		-- define to use PIT timer
 
 CONFIG_SYS_I2C_FSL	-- define to use FSL common I2C driver
-CONFIG_HARD_I2C		-- define for I2C hardware support
 CONFIG_SYS_I2C_SOFT	-- define for I2C bit-banged
 CONFIG_SYS_I2C_SPEED		-- define for I2C speed
 CONFIG_SYS_I2C_SLAVE		-- define for I2C slave address
diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c
index bfcc4b2..f2ed298 100644
--- a/board/freescale/m5373evb/m5373evb.c
+++ b/board/freescale/m5373evb/m5373evb.c
@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
@@ -62,7 +62,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m54418twr/m54418twr.c b/board/freescale/m54418twr/m54418twr.c
index 5375d16..4335394 100644
--- a/board/freescale/m54418twr/m54418twr.c
+++ b/board/freescale/m54418twr/m54418twr.c
@@ -25,7 +25,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	u32 dramsize;
 
@@ -104,7 +104,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 #endif
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c
index d2ad42c..050624b 100644
--- a/board/freescale/m54451evb/m54451evb.c
+++ b/board/freescale/m54451evb/m54451evb.c
@@ -26,7 +26,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	u32 dramsize;
 #ifdef CONFIG_CF_SBF
@@ -82,7 +82,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 #endif
-	return (dramsize);
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m54455evb/README b/board/freescale/m54455evb/README
index c563ad9..4a87193 100644
--- a/board/freescale/m54455evb/README
+++ b/board/freescale/m54455evb/README
@@ -113,7 +113,6 @@ CONFIG_MCFTMR		-- define to use DMA timer
 CONFIG_MCFPIT		-- define to use PIT timer
 
 CONFIG_SYS_FSL_I2C	-- define to use FSL common I2C driver
-CONFIG_HARD_I2C		-- define for I2C hardware support
 CONFIG_SYS_I2C_SOFT	-- define for I2C bit-banged
 CONFIG_SYS_I2C_SPEED		-- define for I2C speed
 CONFIG_SYS_I2C_SLAVE		-- define for I2C slave address
diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c
index 76b4322..1e35970 100644
--- a/board/freescale/m54455evb/m54455evb.c
+++ b/board/freescale/m54455evb/m54455evb.c
@@ -22,7 +22,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	u32 dramsize;
 #ifdef CONFIG_CF_SBF
@@ -75,7 +75,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 #endif
-	return (dramsize << 1);
+	gd->ram_size = dramsize << 1;
+
+	return 0;
 };
 
 int testdram(void)
@@ -86,7 +88,7 @@ int testdram(void)
 	return (0);
 }
 
-#if defined(CONFIG_CMD_IDE)
+#if defined(CONFIG_IDE)
 #include <ata.h>
 
 int ide_preinit(void)
diff --git a/board/freescale/m547xevb/README b/board/freescale/m547xevb/README
index 30c5ded..ce7b27b 100644
--- a/board/freescale/m547xevb/README
+++ b/board/freescale/m547xevb/README
@@ -98,7 +98,6 @@ CONFIG_DOS_PARTITION	-- enable DOS read/write
 CONFIG_SLTTMR		-- define to use SLT timer
 
 CONFIG_SYS_I2C_FSL	-- define to use FSL common I2C driver
-CONFIG_HARD_I2C		-- define for I2C hardware support
 CONFIG_SYS_I2C_SOFT	-- define for I2C bit-banged
 CONFIG_SYS_I2C_SPEED		-- define for I2C speed
 CONFIG_SYS_I2C_SLAVE		-- define for I2C slave address
diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c
index 1e3cb61..d28f43d 100644
--- a/board/freescale/m547xevb/m547xevb.c
+++ b/board/freescale/m547xevb/m547xevb.c
@@ -23,7 +23,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	siu_t *siu = (siu_t *) (MMAP_SIU);
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
@@ -79,7 +79,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c
index 0536155..56060b6 100644
--- a/board/freescale/m548xevb/m548xevb.c
+++ b/board/freescale/m548xevb/m548xevb.c
@@ -23,7 +23,7 @@ int checkboard(void)
 	return 0;
 };
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	siu_t *siu = (siu_t *) (MMAP_SIU);
 	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
@@ -79,7 +79,9 @@ phys_size_t initdram(int board_type)
 
 	udelay(100);
 
-	return dramsize;
+	gd->ram_size = dramsize;
+
+	return 0;
 };
 
 int testdram(void)
diff --git a/board/freescale/mpc5121ads/Kconfig b/board/freescale/mpc5121ads/Kconfig
deleted file mode 100644
index f125f9e..0000000
--- a/board/freescale/mpc5121ads/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC5121ADS
-
-config SYS_BOARD
-	default "mpc5121ads"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "mpc5121ads"
-
-endif
diff --git a/board/freescale/mpc5121ads/MAINTAINERS b/board/freescale/mpc5121ads/MAINTAINERS
deleted file mode 100644
index d4aab8f..0000000
--- a/board/freescale/mpc5121ads/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MPC5121ADS BOARD
-#M:	-
-S:	Maintained
-F:	board/freescale/mpc5121ads/
-F:	include/configs/mpc5121ads.h
-F:	configs/mpc5121ads_defconfig
-F:	configs/mpc5121ads_rev2_defconfig
diff --git a/board/freescale/mpc5121ads/Makefile b/board/freescale/mpc5121ads/Makefile
deleted file mode 100644
index 67cf555..0000000
--- a/board/freescale/mpc5121ads/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mpc5121ads.o
diff --git a/board/freescale/mpc5121ads/README b/board/freescale/mpc5121ads/README
deleted file mode 100644
index 741bc40..0000000
--- a/board/freescale/mpc5121ads/README
+++ /dev/null
@@ -1,7 +0,0 @@
-To configure for the current (Rev 3.x) ADS5121
-	make mpc5121ads_config
-This will automatically include PCI, the Real Time CLock, add backup flash
-ability and set the correct frequency and memory configuration.
-
-To configure for the older Rev 2 ADS5121 type (this will not have PCI)
-	make mpc5121ads_rev2_config
diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
deleted file mode 100644
index 7c44282..0000000
--- a/board/freescale/mpc5121ads/mpc5121ads.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * (C) Copyright 2007-2009 DENX Software Engineering
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mpc512x.h>
-#include <fdt_support.h>
-#ifdef CONFIG_MISC_INIT_R
-#include <i2c.h>
-#endif
-#include <net.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
-
-/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
-extern int mpc5121_nfc_chip;
-
-/* Control chips select signal on MPC5121ADS board */
-void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
-{
-	unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
-	u8 v;
-
-	v = in_8(csreg);
-	v |= 0x0F;
-
-	if (chip >= 0) {
-		__mpc5121_nfc_select_chip(mtd, 0);
-		v &= ~(1 << mpc5121_nfc_chip);
-	} else {
-		__mpc5121_nfc_select_chip(mtd, -1);
-	}
-
-	out_8(csreg, v);
-}
-
-int board_early_init_f(void)
-{
-	/*
-	 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
-	 *
-	 * Without this the flash identification routine fails, as it needs to issue
-	 * write commands in order to establish the device ID.
-	 */
-
-#ifdef CONFIG_MPC5121ADS_REV2
-	out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
-#else
-	if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
-		out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
-	} else {
-		/* running from Backup flash */
-		out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
-	}
-#endif
-	return 0;
-}
-
-int is_micron(void){
-
-	ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00);
-	uchar macaddr[6];
-	u32 brddate, macchk, ismicron;
-
-	/*
-	 * MAC address has serial number with date of manufacture
-	 * Boards made before Nov-08 #1180 use Micron memory;
-	 * 001e59 is the STx vendor #
-	 * Default is Elpida since it works for both but is slightly slower
-	 */
-	ismicron = 0;
-	if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) {
-		brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
-		macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
-		debug("brddate = %d\n\t", brddate);
-
-		if (macchk == 0x001e59 && brddate <= 8111180)
-			ismicron = 1;
-	} else if (brd_rev < 0x400) {
-		ismicron = 1;
-	}
-	debug("Using %s Memory settings\n\t",
-		ismicron ? "Micron" : "Elpida");
-	return(ismicron);
-}
-
-phys_size_t initdram(int board_type)
-{
-	u32 msize = 0;
-	/*
-	 * Elpida MDDRC and initialization settings are an alternative
-	 * to the Default Micron ones for all but the earliest Rev 4 boards
-	 */
-	ddr512x_config_t elpida_mddrc_config = {
-		.ddr_sys_config   = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
-		.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
-		.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
-		.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
-	};
-
-	u32 elpida_init_sequence[] = {
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_EM2,
-		CONFIG_SYS_DDRCMD_EM3,
-		CONFIG_SYS_DDRCMD_EN_DLL,
-		CONFIG_SYS_ELPIDA_RES_DLL,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_ELPIDA_INIT_DEV_OP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_OCD_DEFAULT,
-		CONFIG_SYS_ELPIDA_OCD_EXIT,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP
-	};
-
-	if (is_micron()) {
-		msize = fixed_sdram(NULL, NULL, 0);
-	} else {
-		msize = fixed_sdram(&elpida_mddrc_config,
-				elpida_init_sequence,
-				sizeof(elpida_init_sequence)/sizeof(u32));
-	}
-
-	return msize;
-}
-
-int misc_init_r(void)
-{
-	u8 tmp_val;
-
-	/* Using this for DIU init before the driver in linux takes over
-	 *  Enable the TFP410 Encoder (I2C address 0x38)
-	 */
-
-	i2c_set_bus_num(2);
-	tmp_val = 0xBF;
-	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
-	/* Verify if enabled */
-	tmp_val = 0;
-	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
-	debug("DVI Encoder Read: 0x%02x\n", tmp_val);
-
-	tmp_val = 0x10;
-	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
-	/* Verify if enabled */
-	tmp_val = 0;
-	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
-	debug("DVI Encoder Read: 0x%02x\n", tmp_val);
-
-	return 0;
-}
-
-static  iopin_t ioregs_init[] = {
-	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
-	{
-		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* Set highest Slew on 9 PATA pins */
-	{
-		offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
-	{
-		offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=SPDIF_TXCLK */
-	{
-		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
-	{
-		offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIU CLK */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIU_HSYNC */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	}
-};
-
-static  iopin_t rev2_silicon_pci_ioregs_init[] = {
-	/* FUNC0=PCI Sets next 54 to PCI pads */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
-	}
-};
-
-int checkboard (void)
-{
-	ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
-	uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 spridr = in_be32(&im->sysconf.spridr);
-
-	printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
-		brd_rev, cpld_rev);
-
-	/* initialize function mux & slew rate IO inter alia on IO Pins  */
-	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
-
-	if (SVR_MJREV (spridr) >= 2)
-		iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c
index 93e1c50..b4a0dd5 100644
--- a/board/freescale/mpc8308rdb/mpc8308rdb.c
+++ b/board/freescale/mpc8308rdb/mpc8308rdb.c
@@ -164,7 +164,7 @@ int misc_init_r(void)
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 	fdt_fixup_esdhc(blob, bd);
 
 	return 0;
diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c
index 89b665e..81e155a 100644
--- a/board/freescale/mpc8308rdb/sdram.c
+++ b/board/freescale/mpc8308rdb/sdram.c
@@ -65,17 +65,19 @@ static long fixed_sdram(void)
 	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;
 
 	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM */
 	msize = fixed_sdram();
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	gd->ram_size = msize;
+
+	return 0;
 }
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index eac193e..8974378 100644
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -133,8 +133,8 @@ void board_init_f(ulong bootflag)
 	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
 		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 	puts("NAND boot... ");
-	init_timebase();
-	initdram(0);
+	timer_init();
+	dram_init();
 	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
 		      CONFIG_SYS_NAND_U_BOOT_RELOC);
 }
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index 6282c3d..a4128cb 100644
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -97,14 +97,14 @@ static long fixed_sdram(void)
 	return msize;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile fsl_lbc_t *lbc = &im->im_lbc;
 	u32 msize;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main SODIMM */
 	msize = fixed_sdram();
@@ -120,5 +120,7 @@ phys_size_t initdram(int board_type)
 #endif
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	gd->ram_size = msize;
+
+	return 0;
 }
diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
index ed611c5..22f1565 100644
--- a/board/freescale/mpc8315erdb/mpc8315erdb.c
+++ b/board/freescale/mpc8315erdb/mpc8315erdb.c
@@ -194,7 +194,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
 #endif
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 	fdt_tsec1_fixup(blob, bd);
 
 	return 0;
@@ -221,8 +221,8 @@ void board_init_f(ulong bootflag)
 	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
 		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 	puts("NAND boot... ");
-	init_timebase();
-	initdram(0);
+	timer_init();
+	dram_init();
 	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
 		      CONFIG_SYS_NAND_U_BOOT_RELOC);
 }
diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c
index 6c94312..b69c86b 100644
--- a/board/freescale/mpc8315erdb/sdram.c
+++ b/board/freescale/mpc8315erdb/sdram.c
@@ -92,13 +92,13 @@ static long fixed_sdram(void)
 }
 #endif /* CONFIG_SYS_RAMBOOT */
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM */
 	msize = fixed_sdram();
@@ -106,6 +106,8 @@ phys_size_t initdram(int board_type)
 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
 		resume_from_sleep();
 
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize;
+
+	return 0;
 }
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
index 0a0152a..f30a151 100644
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ b/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -21,6 +21,8 @@
 #endif
 #include <asm/mmu.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 const qe_iop_conf_t qe_iop_conf_tab[] = {
 	/* UCC3 */
 	{1,  0, 1, 0, 1}, /* TxD0 */
@@ -68,21 +70,23 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 
 int fixed_sdram(void);
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main SODIMM */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 
 	msize = fixed_sdram();
 
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return (msize * 1024 * 1024);
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 /*************************************************************************
diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c
index adf4254..b49e03e 100644
--- a/board/freescale/mpc832xemds/mpc832xemds.c
+++ b/board/freescale/mpc832xemds/mpc832xemds.c
@@ -23,6 +23,8 @@
 #include "../common/pq-mds-pib.h"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 const qe_iop_conf_t qe_iop_conf_tab[] = {
 	/* ETH3 */
 	{1,  0, 1, 0, 1}, /* TxD0 */
@@ -88,21 +90,23 @@ int board_early_init_r(void)
 
 int fixed_sdram(void);
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main SODIMM */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 
 	msize = fixed_sdram();
 
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return (msize * 1024 * 1024);
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 /*************************************************************************
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index 02b5040..5f502e2 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -22,6 +22,8 @@
 #include <libfdt.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int fixed_sdram(void);
 void sdram_init(void);
 
@@ -46,13 +48,13 @@ int board_early_init_f (void)
 
 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	phys_size_t msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main SODIMM */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
@@ -73,8 +75,10 @@ phys_size_t initdram (int board_type)
 	 */
 	sdram_init();
 
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize;
+
+	return 0;
 }
 
 #if !defined(CONFIG_SPD_EEPROM)
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 22a1d99..895e9ff 100644
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -20,6 +20,8 @@
 #include <libfdt.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #ifndef CONFIG_SPD_EEPROM
 /*************************************************************************
  *  fixed sdram init -- doesn't use serial presence detect.
@@ -116,7 +118,7 @@ volatile static struct pci_controller hose[] = {
 };
 #endif				/* CONFIG_PCI */
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
@@ -125,7 +127,7 @@ phys_size_t initdram(int board_type)
 #endif
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM - Main SODIMM */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
@@ -144,7 +146,9 @@ phys_size_t initdram(int board_type)
 #endif
 
 	/* return total bus RAM size(bytes) */
-	return msize * 1024 * 1024;
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
index 572913c..2330492 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -20,6 +20,8 @@
 #include "pci.h"
 #include "../common/pq-mds-pib.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int board_early_init_f(void)
 {
 	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
@@ -216,13 +218,13 @@ extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 int fixed_sdram(void);
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
+		return -ENXIO;
 
 #if defined(CONFIG_SPD_EEPROM)
 	msize = spd_sdram();
@@ -236,7 +238,9 @@ phys_size_t initdram(int board_type)
 #endif
 
 	/* return total bus DDR size(bytes) */
-	return (msize * 1024 * 1024);
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 #if !defined(CONFIG_SPD_EEPROM)
@@ -332,7 +336,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 	ft_tsec_fixup(blob, bd);
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 	fdt_fixup_esdhc(blob, bd);
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index 565f815..319f047 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -16,6 +16,8 @@
 #include <vsc7385.h>
 #include <fsl_esdhc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_SYS_DRAM_TEST)
 int
 testdram(void)
@@ -60,13 +62,13 @@ void ddr_enable_ecc(unsigned int dram_size);
 #endif
 int fixed_sdram(void);
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
+		return -ENXIO;
 
 #if defined(CONFIG_SPD_EEPROM)
 	msize = spd_sdram();
@@ -79,7 +81,9 @@ phys_size_t initdram(int board_type)
 	ddr_enable_ecc(msize * 1024 * 1024);
 #endif
 	/* return total bus DDR size(bytes) */
-	return (msize * 1024 * 1024);
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 #if !defined(CONFIG_SPD_EEPROM)
@@ -210,7 +214,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	ft_pci_setup(blob, bd);
 #endif
 	ft_cpu_setup(blob, bd);
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 	fdt_fixup_esdhc(blob, bd);
 
 	return 0;
diff --git a/board/freescale/mpc8536ds/MAINTAINERS b/board/freescale/mpc8536ds/MAINTAINERS
index 953072c..af221f9 100644
--- a/board/freescale/mpc8536ds/MAINTAINERS
+++ b/board/freescale/mpc8536ds/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8536DS BOARD
-#M:	-
+M:	York Sun <york.sun@nxp.com>
 S:	Maintained
 F:	board/freescale/mpc8536ds/
 F:	include/configs/MPC8536DS.h
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 7b0f461..cede1da 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -282,7 +282,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 #endif
 
 #ifdef CONFIG_HAS_FSL_MPH_USB
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
 	return 0;
diff --git a/board/freescale/mpc8540ads/Kconfig b/board/freescale/mpc8540ads/Kconfig
deleted file mode 100644
index 35a8545..0000000
--- a/board/freescale/mpc8540ads/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8540ADS
-
-config SYS_BOARD
-	default "mpc8540ads"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8540ADS"
-
-endif
diff --git a/board/freescale/mpc8540ads/MAINTAINERS b/board/freescale/mpc8540ads/MAINTAINERS
deleted file mode 100644
index acc4821..0000000
--- a/board/freescale/mpc8540ads/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8540ADS BOARD
-#M:	Kumar Gala <kumar.gala@freescale.com>
-S:	Orphan (since 2014-06)
-F:	board/freescale/mpc8540ads/
-F:	include/configs/MPC8540ADS.h
-F:	configs/MPC8540ADS_defconfig
diff --git a/board/freescale/mpc8540ads/Makefile b/board/freescale/mpc8540ads/Makefile
deleted file mode 100644
index 6f82c7f..0000000
--- a/board/freescale/mpc8540ads/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= mpc8540ads.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c
deleted file mode 100644
index 10fb2b3..0000000
--- a/board/freescale/mpc8540ads/ddr.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 0;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/* 2T timing enable */
-	popts->twot_en = 1;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c
deleted file mode 100644
index 41f2e02..0000000
--- a/board/freescale/mpc8540ads/law.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
- * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
- * 0xe000_0000     0xe000_ffff     CCSR                    1M
- * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
- * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
- * 0xf800_0000     0xf80f_ffff     BCSR                    1M
- * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
- *
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-#ifndef CONFIG_SPD_EEPROM
-	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
-#endif
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	/* This is not so much the SDRAM map as it is the whole localbus map. */
-	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
deleted file mode 100644
index 1069e2c..0000000
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * Copyright 2004 Freescale Semiconductor.
- * (C) Copyright 2002,2003, Motorola Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <fsl_ddr_sdram.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-void local_bus_init(void);
-
-int checkboard (void)
-{
-	puts("Board: ADS\n");
-
-#ifdef CONFIG_PCI
-	printf("PCI1: 32 bit, %d MHz (compiled)\n",
-	       CONFIG_SYS_CLK_FREQ / 1000000);
-#else
-	printf("PCI1: disabled\n");
-#endif
-
-	/*
-	 * Initialize local bus.
-	 */
-	local_bus_init();
-
-	return 0;
-}
-
-/*
- * Initialize Local Bus
- */
-
-void
-local_bus_init(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	uint clkdiv;
-	uint lbc_hz;
-	sys_info_t sysinfo;
-
-	/*
-	 * Errata LBC11.
-	 * Fix Local Bus clock glitch when DLL is enabled.
-	 *
-	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
-	 * If localbus freq is > 133MHz, DLL can be safely enabled.
-	 * Between 66 and 133, the DLL is enabled with an override workaround.
-	 */
-
-	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & LCRR_CLKDIV;
-	lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
-
-	if (lbc_hz < 66) {
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP;	/* DLL Bypass */
-
-	} else if (lbc_hz >= 133) {
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
-
-	} else {
-		/*
-		 * On REV1 boards, need to change CLKDIV before enable DLL.
-		 * Default CLKDIV is 8, change it to 4 temporarily.
-		 */
-		uint pvr = get_pvr();
-		uint temp_lbcdll = 0;
-
-		if (pvr == PVR_85xx_REV1) {
-			/* FIXME: Justify the high bit here. */
-			lbc->lcrr = 0x10000004;
-		}
-
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
-		udelay(200);
-
-		/*
-		 * Sample LBC DLL ctrl reg, upshift it to set the
-		 * override bits.
-		 */
-		temp_lbcdll = gur->lbcdllcr;
-		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
-		asm("sync;isync;msync");
-	}
-}
-
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-void lbc_sdram_init(void)
-{
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-
-	puts("LBC SDRAM: ");
-	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
-		   "\n       ");
-
-	/*
-	 * Setup SDRAM Base and Option Registers
-	 */
-	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
-	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
-	asm("msync");
-
-	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
-	asm("sync");
-
-	/*
-	 * Configure the SDRAM controller.
-	 */
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
-	asm("sync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
-	asm("sync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
-	asm("sync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
-	asm("sync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
-	asm("sync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-phys_size_t fixed_sdram(void)
-{
-  #ifndef CONFIG_SYS_RAMBOOT
-	struct ccsr_ddr __iomem *ddr =
-		(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
-
-	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
-	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
-	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
-	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-    #if defined (CONFIG_DDR_ECC)
-	ddr->err_disable = 0x0000000D;
-	ddr->err_sbe = 0x00ff0000;
-    #endif
-	asm("sync;isync;msync");
-	udelay(500);
-    #if defined (CONFIG_DDR_ECC)
-	/* Enable ECC checking */
-	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
-    #else
-	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
-    #endif
-	asm("sync; isync; msync");
-	udelay(500);
-  #endif
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif	/* !defined(CONFIG_SPD_EEPROM) */
-
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-
-static struct pci_controller hose;
-
-#endif	/* CONFIG_PCI */
-
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
-	pci_mpc85xx_init(&hose);
-#endif /* CONFIG_PCI */
-}
-
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	int node, tmp[2];
-	const char *path;
-
-	ft_cpu_setup(blob, bd);
-
-	node = fdt_path_offset(blob, "/aliases");
-	tmp[0] = 0;
-	if (node >= 0) {
-#ifdef CONFIG_PCI
-		path = fdt_getprop(blob, node, "pci0", NULL);
-		if (path) {
-			tmp[1] = hose.last_busno - hose.first_busno;
-			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
-		}
-#endif
-	}
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c
deleted file mode 100644
index d5ee791..0000000
--- a/board/freescale/mpc8540ads/tlb.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/*
-	 * TLB 0:	16M	Non-cacheable, guarded
-	 * 0xff000000	16M	FLASH
-	 * Out of reset this entry is only 4K.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_16M, 1),
-
-	/*
-	 * TLB 1:	256M	Non-cacheable, guarded
-	 * 0x80000000	256M	PCI1 MEM First half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 2:	256M	Non-cacheable, guarded
-	 * 0x90000000	256M	PCI1 MEM Second half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 3:	256M	Non-cacheable, guarded
-	 * 0xc0000000	256M	Rapid IO MEM First half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 4:	256M	Non-cacheable, guarded
-	 * 0xd0000000	256M	Rapid IO MEM Second half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 5:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe200_0000	16M	PCI1 IO
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLB 6:	64M	Cacheable, non-guarded
-	 * 0xf000_0000	64M	LBC SDRAM
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 6, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLB 7:	16K	Non-cacheable, guarded
-	 * 0xf8000000	16K	BCSR registers
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_16K, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8541cds/MAINTAINERS b/board/freescale/mpc8541cds/MAINTAINERS
index d421b12..1d969f1 100644
--- a/board/freescale/mpc8541cds/MAINTAINERS
+++ b/board/freescale/mpc8541cds/MAINTAINERS
@@ -1,6 +1,6 @@
 MPC8541CDS BOARD
-#M:	Kumar Gala <kumar.gala@freescale.com>
-S:	Orphan (since 2014-06)
+M:	York Sun <york.sun@nxp.com>
+S:	Maintained
 F:	board/freescale/mpc8541cds/
 F:	include/configs/MPC8541CDS.h
 F:	configs/MPC8541CDS_defconfig
diff --git a/board/freescale/mpc8544ds/MAINTAINERS b/board/freescale/mpc8544ds/MAINTAINERS
index 328be7f..3c6f80e 100644
--- a/board/freescale/mpc8544ds/MAINTAINERS
+++ b/board/freescale/mpc8544ds/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8544DS BOARD
-#M:	-
+M:	York Sun <york.sun@nxp.com>
 S:	Maintained
 F:	board/freescale/mpc8544ds/
 F:	include/configs/MPC8544DS.h
diff --git a/board/freescale/mpc8548cds/MAINTAINERS b/board/freescale/mpc8548cds/MAINTAINERS
index 6f22922..a99f84b 100644
--- a/board/freescale/mpc8548cds/MAINTAINERS
+++ b/board/freescale/mpc8548cds/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8548CDS BOARD
-#M:	-
+M:	York Sun <york.sun@nxp.com>
 S:	Maintained
 F:	board/freescale/mpc8548cds/
 F:	include/configs/MPC8548CDS.h
diff --git a/board/freescale/mpc8555cds/MAINTAINERS b/board/freescale/mpc8555cds/MAINTAINERS
index 1ef6690..3be1598 100644
--- a/board/freescale/mpc8555cds/MAINTAINERS
+++ b/board/freescale/mpc8555cds/MAINTAINERS
@@ -1,6 +1,6 @@
 MPC8555CDS BOARD
-#M:	Kumar Gala <kumar.gala@freescale.com>
-S:	Orphan (since 2014-06)
+M:	York Sun <york.sun@nxp.com>
+S:	Maintained
 F:	board/freescale/mpc8555cds/
 F:	include/configs/MPC8555CDS.h
 F:	configs/MPC8555CDS_defconfig
diff --git a/board/freescale/mpc8560ads/Kconfig b/board/freescale/mpc8560ads/Kconfig
deleted file mode 100644
index 828c068..0000000
--- a/board/freescale/mpc8560ads/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8560ADS
-
-config SYS_BOARD
-	default "mpc8560ads"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8560ADS"
-
-endif
diff --git a/board/freescale/mpc8560ads/MAINTAINERS b/board/freescale/mpc8560ads/MAINTAINERS
deleted file mode 100644
index 96e6da2..0000000
--- a/board/freescale/mpc8560ads/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8560ADS BOARD
-#M:	Kumar Gala <kumar.gala@freescale.com>
-S:	Orphan (since 2014-06)
-F:	board/freescale/mpc8560ads/
-F:	include/configs/MPC8560ADS.h
-F:	configs/MPC8560ADS_defconfig
diff --git a/board/freescale/mpc8560ads/Makefile b/board/freescale/mpc8560ads/Makefile
deleted file mode 100644
index 685168e..0000000
--- a/board/freescale/mpc8560ads/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= mpc8560ads.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c
deleted file mode 100644
index 10fb2b3..0000000
--- a/board/freescale/mpc8560ads/ddr.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 0;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/* 2T timing enable */
-	popts->twot_en = 1;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c
deleted file mode 100644
index 41f2e02..0000000
--- a/board/freescale/mpc8560ads/law.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
- * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
- * 0xe000_0000     0xe000_ffff     CCSR                    1M
- * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
- * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
- * 0xf800_0000     0xf80f_ffff     BCSR                    1M
- * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
- *
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-struct law_entry law_table[] = {
-#ifndef CONFIG_SPD_EEPROM
-	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
-#endif
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	/* This is not so much the SDRAM map as it is the whole localbus map. */
-	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
deleted file mode 100644
index f99d639..0000000
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ /dev/null
@@ -1,462 +0,0 @@
-/*
- * Copyright 2004 Freescale Semiconductor.
- * (C) Copyright 2003,Motorola Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <fsl_ddr_sdram.h>
-#include <ioports.h>
-#include <spd_sdram.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_lbc.h>
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
-
-void local_bus_init(void);
-
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A configuration */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
-	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
-	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
-	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
-	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
-	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
-	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
-	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
-	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
-	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
-	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
-	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
-	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
-	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
-	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
-	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
-	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
-	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
-	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
-	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
-	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
-	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
-	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
-	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
-	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
-	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
-	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
-	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
-	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
-	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
-	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
-	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
-    },
-
-    /* Port B configuration */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
-	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
-	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
-	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
-	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
-	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
-	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
-	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
-	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
-	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
-	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
-	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
-	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
-	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
-	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
-	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
-	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
-	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
-	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
-	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    },
-
-    /* Port C */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
-	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
-	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
-	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
-	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
-	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
-	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
-	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
-	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
-	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
-	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
-	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
-	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
-	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
-	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
-	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
-	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
-	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
-	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
-	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
-	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
-	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
-	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
-	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
-	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
-	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
-	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
-	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
-	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
-	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
-	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
-	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
-    },
-
-    /* Port D */
-    {   /*            conf ppar psor pdir podr pdat */
-	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
-	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
-	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
-	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
-	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
-	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
-	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
-	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
-	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
-	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
-	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
-	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
-	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
-	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
-	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
-	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
-	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
-	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
-	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
-	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
-	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
-	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
-	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
-	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
-	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
-	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
-	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    }
-};
-
-
-/*
- * MPC8560ADS Board Status & Control Registers
- */
-typedef struct bcsr_ {
-	volatile unsigned char bcsr0;
-	volatile unsigned char bcsr1;
-	volatile unsigned char bcsr2;
-	volatile unsigned char bcsr3;
-	volatile unsigned char bcsr4;
-	volatile unsigned char bcsr5;
-} bcsr_t;
-
-void reset_phy (void)
-{
-#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
-	volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR;
-#endif
-	/* reset Giga bit Ethernet port if needed here */
-
-	/* reset the CPM FEC port */
-#if (CONFIG_ETHER_INDEX == 2)
-	bcsr->bcsr2 &= ~FETH2_RST;
-	udelay(2);
-	bcsr->bcsr2 |=  FETH2_RST;
-	udelay(1000);
-#elif (CONFIG_ETHER_INDEX == 3)
-	bcsr->bcsr3 &= ~FETH3_RST;
-	udelay(2);
-	bcsr->bcsr3 |=  FETH3_RST;
-	udelay(1000);
-#endif
-#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
-	/* reset PHY */
-	miiphy_reset("FCC1", 0x0);
-
-	/* change PHY address to 0x02 */
-	bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
-
-	bb_miiphy_write(NULL, 0x02, MII_BMCR,
-			BMCR_ANENABLE | BMCR_ANRESTART);
-#endif /* CONFIG_MII */
-}
-
-
-int checkboard (void)
-{
-	puts("Board: ADS\n");
-
-#ifdef CONFIG_PCI
-	printf("PCI1: 32 bit, %d MHz (compiled)\n",
-	       CONFIG_SYS_CLK_FREQ / 1000000);
-#else
-	printf("PCI1: disabled\n");
-#endif
-
-	/*
-	 * Initialize local bus.
-	 */
-	local_bus_init();
-
-	return 0;
-}
-
-/*
- * Initialize Local Bus
- */
-
-void
-local_bus_init(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	uint clkdiv;
-	uint lbc_hz;
-	sys_info_t sysinfo;
-
-	/*
-	 * Errata LBC11.
-	 * Fix Local Bus clock glitch when DLL is enabled.
-	 *
-	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
-	 * If localbus freq is > 133MHz, DLL can be safely enabled.
-	 * Between 66 and 133, the DLL is enabled with an override workaround.
-	 */
-
-	get_sys_info(&sysinfo);
-	clkdiv = lbc->lcrr & LCRR_CLKDIV;
-	lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv;
-
-	if (lbc_hz < 66) {
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP;	/* DLL Bypass */
-
-	} else if (lbc_hz >= 133) {
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
-
-	} else {
-		/*
-		 * On REV1 boards, need to change CLKDIV before enable DLL.
-		 * Default CLKDIV is 8, change it to 4 temporarily.
-		 */
-		uint pvr = get_pvr();
-		uint temp_lbcdll = 0;
-
-		if (pvr == PVR_85xx_REV1) {
-			/* FIXME: Justify the high bit here. */
-			lbc->lcrr = 0x10000004;
-		}
-
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);/* DLL Enabled */
-		udelay(200);
-
-		/*
-		 * Sample LBC DLL ctrl reg, upshift it to set the
-		 * override bits.
-		 */
-		temp_lbcdll = gur->lbcdllcr;
-		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
-		asm("sync;isync;msync");
-	}
-}
-
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-void lbc_sdram_init(void)
-{
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-
-	puts("LBC SDRAM: ");
-	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
-		   "\n       ");
-
-	/*
-	 * Setup SDRAM Base and Option Registers
-	 */
-	set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
-	set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
-	asm("msync");
-
-	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
-	asm("sync");
-
-	/*
-	 * Configure the SDRAM controller.
-	 */
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
-	asm("sync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
-	asm("sync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
-	asm("sync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
-	asm("sync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
-	asm("sync");
-	*sdram_addr = 0xff;
-	ppcDcbf((unsigned long) sdram_addr);
-	udelay(100);
-}
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- *  fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-phys_size_t fixed_sdram(void)
-{
-  #ifndef CONFIG_SYS_RAMBOOT
-	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
-
-	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
-	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
-	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
-	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-    #if defined (CONFIG_DDR_ECC)
-	ddr->err_disable = 0x0000000D;
-	ddr->err_sbe = 0x00ff0000;
-    #endif
-	asm("sync;isync;msync");
-	udelay(500);
-    #if defined (CONFIG_DDR_ECC)
-	/* Enable ECC checking */
-	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
-    #else
-	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
-    #endif
-	asm("sync; isync; msync");
-	udelay(500);
-  #endif
-	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif	/* !defined(CONFIG_SPD_EEPROM) */
-
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc85xxads_config_table[] = {
-    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-      PCI_IDSEL_NUMBER, PCI_ANY_ID,
-      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
-				   PCI_ENET0_MEMADDR,
-				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
-      } },
-    { }
-};
-#endif
-
-
-static struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
-	config_table: pci_mpc85xxads_config_table,
-#endif
-};
-
-#endif	/* CONFIG_PCI */
-
-
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
-	pci_mpc85xx_init(&hose);
-#endif /* CONFIG_PCI */
-}
-
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	int node, tmp[2];
-	const char *path;
-
-	ft_cpu_setup(blob, bd);
-
-	node = fdt_path_offset(blob, "/aliases");
-	tmp[0] = 0;
-	if (node >= 0) {
-#ifdef CONFIG_PCI
-		path = fdt_getprop(blob, node, "pci0", NULL);
-		if (path) {
-			tmp[1] = hose.last_busno - hose.first_busno;
-			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
-		}
-#endif
-	}
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c
deleted file mode 100644
index d5ee791..0000000
--- a/board/freescale/mpc8560ads/tlb.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/*
-	 * TLB 0:	16M	Non-cacheable, guarded
-	 * 0xff000000	16M	FLASH
-	 * Out of reset this entry is only 4K.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_16M, 1),
-
-	/*
-	 * TLB 1:	256M	Non-cacheable, guarded
-	 * 0x80000000	256M	PCI1 MEM First half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 2:	256M	Non-cacheable, guarded
-	 * 0x90000000	256M	PCI1 MEM Second half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 3:	256M	Non-cacheable, guarded
-	 * 0xc0000000	256M	Rapid IO MEM First half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 4:	256M	Non-cacheable, guarded
-	 * 0xd0000000	256M	Rapid IO MEM Second half
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 5:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe200_0000	16M	PCI1 IO
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLB 6:	64M	Cacheable, non-guarded
-	 * 0xf000_0000	64M	LBC SDRAM
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 6, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLB 7:	16K	Non-cacheable, guarded
-	 * 0xf8000000	16K	BCSR registers
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 7, BOOKE_PAGESZ_16K, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8568mds/MAINTAINERS b/board/freescale/mpc8568mds/MAINTAINERS
index 379d8cc..56c5373 100644
--- a/board/freescale/mpc8568mds/MAINTAINERS
+++ b/board/freescale/mpc8568mds/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8568MDS BOARD
-#M:	-
+M:	York Sun <york.sun@nxp.com>
 S:	Maintained
 F:	board/freescale/mpc8568mds/
 F:	include/configs/MPC8568MDS.h
diff --git a/board/freescale/mpc8569mds/MAINTAINERS b/board/freescale/mpc8569mds/MAINTAINERS
index c181407..49a9361 100644
--- a/board/freescale/mpc8569mds/MAINTAINERS
+++ b/board/freescale/mpc8569mds/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8569MDS BOARD
-#M:	-
+M:	York Sun <york.sun@nxp.com>
 S:	Maintained
 F:	board/freescale/mpc8569mds/
 F:	include/configs/MPC8569MDS.h
diff --git a/board/freescale/mpc8610hpcd/MAINTAINERS b/board/freescale/mpc8610hpcd/MAINTAINERS
index de6ab89..8986c11 100644
--- a/board/freescale/mpc8610hpcd/MAINTAINERS
+++ b/board/freescale/mpc8610hpcd/MAINTAINERS
@@ -1,5 +1,5 @@
 MPC8610HPCD BOARD
-#M:	-
+M:	York Sun <york.sun@nxp.com>
 S:	Maintained
 F:	board/freescale/mpc8610hpcd/
 F:	include/configs/MPC8610HPCD.h
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 95e398c..d97562c 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -19,6 +19,8 @@
 #include <spd_sdram.h>
 #include <netdev.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void sdram_init(void);
 phys_size_t fixed_sdram(void);
 int mpc8610hpcd_diu_init(void);
@@ -116,8 +118,7 @@ int checkboard(void)
 }
 
 
-phys_size_t
-initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size = 0;
 
@@ -130,7 +131,9 @@ initdram(int board_type)
 	setup_ddr_bat(dram_size);
 
 	debug(" DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
 
diff --git a/board/freescale/mpc8641hpcn/MAINTAINERS b/board/freescale/mpc8641hpcn/MAINTAINERS
index 9790247..86dcf6b 100644
--- a/board/freescale/mpc8641hpcn/MAINTAINERS
+++ b/board/freescale/mpc8641hpcn/MAINTAINERS
@@ -1,6 +1,6 @@
 MPC8641HPCN BOARD
-#M:	Kumar Gala <kumar.gala@freescale.com>
-S:	Orphan (since 2014-06)
+M:	York Sun <york.sun@nxp.com>
+S:	Maintained
 F:	board/freescale/mpc8641hpcn/
 F:	include/configs/MPC8641HPCN.h
 F:	configs/MPC8641HPCN_defconfig
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 94633b5..2604a51 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -16,6 +16,8 @@
 #include <fdt_support.h>
 #include <netdev.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 phys_size_t fixed_sdram(void);
 
 int checkboard(void)
@@ -37,8 +39,7 @@ int checkboard(void)
 	return 0;
 }
 
-phys_size_t
-initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size = 0;
 
@@ -51,7 +52,9 @@ initdram(int board_type)
 	setup_ddr_bat(dram_size);
 
 	debug("    DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
 
diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c
index 788d3c3..cab769c 100644
--- a/board/freescale/mx25pdk/mx25pdk.c
+++ b/board/freescale/mx25pdk/mx25pdk.c
@@ -175,6 +175,12 @@ int board_mmc_init(bd_t *bis)
 
 	imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
 
+	/*
+	 * Set the eSDHC1 PER clock to the maximum frequency lower than or equal
+	 * to 50 MHz that can be obtained, which requires to use UPLL as the
+	 * clock source. This actually gives 48 MHz.
+	 */
+	imx_set_perclk(MXC_ESDHC1_CLK, true, 50000000);
 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 }
diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c
index 12467a9..ea0bd8f 100644
--- a/board/freescale/mx35pdk/mx35pdk.c
+++ b/board/freescale/mx35pdk/mx35pdk.c
@@ -8,7 +8,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
@@ -24,6 +24,7 @@
 #include <asm/gpio.h>
 #include <asm/arch/sys_proto.h>
 #include <netdev.h>
+#include <asm/mach-types.h>
 
 #ifndef CONFIG_BOARD_LATE_INIT
 #error "CONFIG_BOARD_LATE_INIT must be set for this board"
@@ -47,13 +48,15 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return 0;
 }
 
 #define I2C_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 2ea5346..a88ff8f 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -9,11 +9,11 @@
 #include <asm/gpio.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux-mx51.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <asm/imx-common/mx5_video.h>
+#include <asm/mach-imx/mx5_video.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c
index 8ba2728..eb9f743 100644
--- a/board/freescale/mx53ard/mx53ard.c
+++ b/board/freescale/mx53ard/mx53ard.c
@@ -11,7 +11,7 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/iomux-mx53.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <netdev.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
@@ -32,13 +32,15 @@ int dram_init(void)
 
 	return 0;
 }
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_NAND_MXC
diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
index 6ee6d73..c608de4 100644
--- a/board/freescale/mx53evk/mx53evk.c
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -11,8 +11,8 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/iomux-mx53.h>
-#include <asm/errno.h>
-#include <asm/imx-common/boot_mode.h>
+#include <linux/errno.h>
+#include <asm/mach-imx/boot_mode.h>
 #include <netdev.h>
 #include <i2c.h>
 #include <mmc.h>
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index 1298788..27d606f 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -13,8 +13,8 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/iomux-mx53.h>
 #include <asm/arch/clock.h>
-#include <asm/errno.h>
-#include <asm/imx-common/mx5_video.h>
+#include <linux/errno.h>
+#include <asm/mach-imx/mx5_video.h>
 #include <netdev.h>
 #include <i2c.h>
 #include <mmc.h>
@@ -58,13 +58,15 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = mx53_dram_size[0];
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = mx53_dram_size[1];
+
+	return 0;
 }
 
 u32 get_board_rev(void)
diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c
index 0963fd7..630d671 100644
--- a/board/freescale/mx53smd/mx53smd.c
+++ b/board/freescale/mx53smd/mx53smd.c
@@ -11,7 +11,7 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/iomux-mx53.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <netdev.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
@@ -30,13 +30,15 @@ int dram_init(void)
 
 	return 0;
 }
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+	return 0;
 }
 
 #define UART_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c
index 5aae721..8cb5ac5 100644
--- a/board/freescale/mx6qarm2/mx6qarm2.c
+++ b/board/freescale/mx6qarm2/mx6qarm2.c
@@ -9,9 +9,9 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/clock.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
diff --git a/board/freescale/mx6qsabreauto/Kconfig b/board/freescale/mx6qsabreauto/Kconfig
deleted file mode 100644
index e579c0f..0000000
--- a/board/freescale/mx6qsabreauto/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MX6QSABREAUTO
-
-config SYS_BOARD
-	default "mx6qsabreauto"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "mx6qsabreauto"
-
-endif
diff --git a/board/freescale/mx6qsabreauto/MAINTAINERS b/board/freescale/mx6qsabreauto/MAINTAINERS
deleted file mode 100644
index f148dac..0000000
--- a/board/freescale/mx6qsabreauto/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-MX6QSABREAUTO BOARD
-M:	Fabio Estevam <fabio.estevam@nxp.com>
-M:	Peng Fan <peng.fan@nxp.com>
-S:	Maintained
-F:	board/freescale/mx6qsabreauto/
-F:	include/configs/mx6qsabreauto.h
-F:	configs/mx6dlsabreauto_defconfig
-F:	configs/mx6qsabreauto_defconfig
-F:	configs/mx6qpsabreauto_defconfig
diff --git a/board/freescale/mx6qsabreauto/Makefile b/board/freescale/mx6qsabreauto/Makefile
deleted file mode 100644
index ac5bc81..0000000
--- a/board/freescale/mx6qsabreauto/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
-#
-# (C) Copyright 2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y  := mx6qsabreauto.o
diff --git a/board/freescale/mx6qsabreauto/imximage.cfg b/board/freescale/mx6qsabreauto/imximage.cfg
deleted file mode 100644
index 16bf473..0000000
--- a/board/freescale/mx6qsabreauto/imximage.cfg
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-/* image version */
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM	sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *	Addr-type register length (1,2 or 4 bytes)
- *	Address	  absolute address of the register
- *	value	  value to be stored in the register
- */
-DATA 4 0x020e0798 0x000C0000
-DATA 4 0x020e0758 0x00000000
-DATA 4 0x020e0588 0x00000030
-DATA 4 0x020e0594 0x00000030
-DATA 4 0x020e056c 0x00000030
-DATA 4 0x020e0578 0x00000030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e057c 0x00000030
-DATA 4 0x020e058c 0x00000000
-DATA 4 0x020e059c 0x00000030
-DATA 4 0x020e05a0 0x00000030
-DATA 4 0x020e078c 0x00000030
-DATA 4 0x020e0750 0x00020000
-DATA 4 0x020e05a8 0x00000028
-DATA 4 0x020e05b0 0x00000028
-DATA 4 0x020e0524 0x00000028
-DATA 4 0x020e051c 0x00000028
-DATA 4 0x020e0518 0x00000028
-DATA 4 0x020e050c 0x00000028
-DATA 4 0x020e05b8 0x00000028
-DATA 4 0x020e05c0 0x00000028
-DATA 4 0x020e0774 0x00020000
-DATA 4 0x020e0784 0x00000028
-DATA 4 0x020e0788 0x00000028
-DATA 4 0x020e0794 0x00000028
-DATA 4 0x020e079c 0x00000028
-DATA 4 0x020e07a0 0x00000028
-DATA 4 0x020e07a4 0x00000028
-DATA 4 0x020e07a8 0x00000028
-DATA 4 0x020e0748 0x00000028
-DATA 4 0x020e05ac 0x00000028
-DATA 4 0x020e05b4 0x00000028
-DATA 4 0x020e0528 0x00000028
-DATA 4 0x020e0520 0x00000028
-DATA 4 0x020e0514 0x00000028
-DATA 4 0x020e0510 0x00000028
-DATA 4 0x020e05bc 0x00000028
-DATA 4 0x020e05c4 0x00000028
-DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-DATA 4 0x021b480c 0x001F001F
-DATA 4 0x021b4810 0x001F001F
-DATA 4 0x021b083c 0x43260335
-DATA 4 0x021b0840 0x031A030B
-DATA 4 0x021b483c 0x4323033B
-DATA 4 0x021b4840 0x0323026F
-DATA 4 0x021b0848 0x483D4545
-DATA 4 0x021b4848 0x44433E48
-DATA 4 0x021b0850 0x41444840
-DATA 4 0x021b4850 0x4835483E
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-DATA 4 0x021b0004 0x00020036
-DATA 4 0x021b0008 0x09444040
-DATA 4 0x021b000c 0x8A8F7955
-DATA 4 0x021b0010 0xFF328F64
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b0018 0x00001740
-DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b002c 0x000026d2
-DATA 4 0x021b0030 0x008F1023
-DATA 4 0x021b0040 0x00000047
-DATA 4 0x021b0000 0x841A0000
-DATA 4 0x021b001c 0x04088032
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x00048031
-DATA 4 0x021b001c 0x09408030
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00011117
-DATA 4 0x021b4818 0x00011117
-DATA 4 0x021b0004 0x00025576
-DATA 4 0x021b0404 0x00011006
-DATA 4 0x021b001c 0x00000000
-
-/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0xFFFFF300
-DATA 4 0x020c407c 0x0F0000F3
-DATA 4 0x020c4080 0x00000FFF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
diff --git a/board/freescale/mx6qsabreauto/mx6dl.cfg b/board/freescale/mx6qsabreauto/mx6dl.cfg
deleted file mode 100644
index 89078e5..0000000
--- a/board/freescale/mx6qsabreauto/mx6dl.cfg
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- * Jason Liu <r64343@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-/* image version */
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM	sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *	Addr-type register length (1,2 or 4 bytes)
- *	Address	  absolute address of the register
- *	value	  value to be stored in the register
- */
-DATA 4 0x020e0774 0x000C0000
-DATA 4 0x020e0754 0x00000000
-DATA 4 0x020e04ac 0x00000030
-DATA 4 0x020e04b0 0x00000030
-DATA 4 0x020e0464 0x00000030
-DATA 4 0x020e0490 0x00000030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e0494 0x00000030
-DATA 4 0x020e04a0 0x00000000
-DATA 4 0x020e04b4 0x00000030
-DATA 4 0x020e04b8 0x00000030
-DATA 4 0x020e076c 0x00000030
-DATA 4 0x020e0750 0x00020000
-DATA 4 0x020e04bc 0x00000028
-DATA 4 0x020e04c0 0x00000028
-DATA 4 0x020e04c4 0x00000028
-DATA 4 0x020e04c8 0x00000028
-DATA 4 0x020e04cc 0x00000028
-DATA 4 0x020e04d0 0x00000028
-DATA 4 0x020e04d4 0x00000028
-DATA 4 0x020e04d8 0x00000028
-DATA 4 0x020e0760 0x00020000
-DATA 4 0x020e0764 0x00000028
-DATA 4 0x020e0770 0x00000028
-DATA 4 0x020e0778 0x00000028
-DATA 4 0x020e077c 0x00000028
-DATA 4 0x020e0780 0x00000028
-DATA 4 0x020e0784 0x00000028
-DATA 4 0x020e078c 0x00000028
-DATA 4 0x020e0748 0x00000028
-DATA 4 0x020e0470 0x00000028
-DATA 4 0x020e0474 0x00000028
-DATA 4 0x020e0478 0x00000028
-DATA 4 0x020e047c 0x00000028
-DATA 4 0x020e0480 0x00000028
-DATA 4 0x020e0484 0x00000028
-DATA 4 0x020e0488 0x00000028
-DATA 4 0x020e048c 0x00000028
-DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-DATA 4 0x021b480c 0x001F001F
-DATA 4 0x021b4810 0x001F001F
-DATA 4 0x021b083c 0x42190217
-DATA 4 0x021b0840 0x017B017B
-DATA 4 0x021b483c 0x4176017B
-DATA 4 0x021b4840 0x015F016C
-DATA 4 0x021b0848 0x4C4C4D4C
-DATA 4 0x021b4848 0x4A4D4C48
-DATA 4 0x021b0850 0x3F3F3F40
-DATA 4 0x021b4850 0x3538382E
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-DATA 4 0x021b0004 0x00020025
-DATA 4 0x021b0008 0x00333030
-DATA 4 0x021b000c 0x676B5313
-DATA 4 0x021b0010 0xB66E8B63
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b0018 0x00001740
-DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b002c 0x000026d2
-DATA 4 0x021b0030 0x006B1023
-DATA 4 0x021b0040 0x00000047
-DATA 4 0x021b0000 0x841A0000
-DATA 4 0x021b001c 0x04008032
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x00048031
-DATA 4 0x021b001c 0x05208030
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00011117
-DATA 4 0x021b4818 0x00011117
-DATA 4 0x021b0004 0x00025565
-DATA 4 0x021b0404 0x00011006
-DATA 4 0x021b001c 0x00000000
-
-/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0xFFFFF300
-DATA 4 0x020c407c 0x0F0000C3
-DATA 4 0x020c4080 0x00000FFF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
diff --git a/board/freescale/mx6qsabreauto/mx6qp.cfg b/board/freescale/mx6qsabreauto/mx6qp.cfg
deleted file mode 100644
index 2298c77..0000000
--- a/board/freescale/mx6qsabreauto/mx6qp.cfg
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-/* image version */
-
-#define __ASSEMBLY__
-#include <config.h>
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of spi, sd, eimnor, nand, sata:
- * spinor: flash_offset: 0x0400
- * nand:   flash_offset: 0x0400
- * sata:   flash_offset: 0x0400
- * sd/mmc: flash_offset: 0x0400
- * eimnor: flash_offset: 0x1000
- */
-BOOT_FROM	sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *	Addr-type register length (1,2 or 4 bytes)
- *	Address	  absolute address of the register
- *	value	  value to be stored in the register
- */
-DATA 4 0x020e0798 0x000C0000
-DATA 4 0x020e0758 0x00000000
-DATA 4 0x020e0588 0x00000030
-DATA 4 0x020e0594 0x00000030
-DATA 4 0x020e056c 0x00000030
-DATA 4 0x020e0578 0x00000030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e057c 0x00000030
-DATA 4 0x020e058c 0x00000000
-DATA 4 0x020e059c 0x00000030
-DATA 4 0x020e05a0 0x00000030
-DATA 4 0x020e078c 0x00000030
-DATA 4 0x020e0750 0x00020000
-DATA 4 0x020e05a8 0x00000030
-DATA 4 0x020e05b0 0x00000030
-DATA 4 0x020e0524 0x00000030
-DATA 4 0x020e051c 0x00000030
-DATA 4 0x020e0518 0x00000030
-DATA 4 0x020e050c 0x00000030
-DATA 4 0x020e05b8 0x00000030
-DATA 4 0x020e05c0 0x00000030
-DATA 4 0x020e0774 0x00020000
-DATA 4 0x020e0784 0x00000030
-DATA 4 0x020e0788 0x00000030
-DATA 4 0x020e0794 0x00000030
-DATA 4 0x020e079c 0x00000030
-DATA 4 0x020e07a0 0x00000030
-DATA 4 0x020e07a4 0x00000030
-DATA 4 0x020e07a8 0x00000030
-DATA 4 0x020e0748 0x00000030
-DATA 4 0x020e05ac 0x00000030
-DATA 4 0x020e05b4 0x00000030
-DATA 4 0x020e0528 0x00000030
-DATA 4 0x020e0520 0x00000030
-DATA 4 0x020e0514 0x00000030
-DATA 4 0x020e0510 0x00000030
-DATA 4 0x020e05bc 0x00000030
-DATA 4 0x020e05c4 0x00000030
-DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b080c 0x001b001e
-DATA 4 0x021b0810 0x002e0029
-DATA 4 0x021b480c 0x001b002a
-DATA 4 0x021b4810 0x0019002c
-DATA 4 0x021b083c 0x43240334
-DATA 4 0x021b0840 0x0324031a
-DATA 4 0x021b483c 0x43340344
-DATA 4 0x021b4840 0x03280276
-DATA 4 0x021b0848 0x44383A3E
-DATA 4 0x021b4848 0x3C3C3846
-DATA 4 0x021b0850 0x2e303230
-DATA 4 0x021b4850 0x38283E34
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-DATA 4 0x021b08c0 0x24912492
-DATA 4 0x021b48c0 0x24912492
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-DATA 4 0x021b0004 0x00020036
-DATA 4 0x021b0008 0x09444040
-DATA 4 0x021b000c 0x898E7955
-DATA 4 0x021b0010 0xFF328F64
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b0018 0x00001740
-DATA 4 0x021b001c 0x00008000
-
-DATA 4 0x021b002c 0x000026d2
-DATA 4 0x021b0030 0x008E1023
-DATA 4 0x021b0040 0x00000047
-DATA 4 0x021b0400 0x14420000
-DATA 4 0x021b0000 0x841A0000
-DATA 4 0x00bb0008 0x00000004
-DATA 4 0x00bb000c 0x2891E41A
-DATA 4 0x00bb0038 0x00000564
-DATA 4 0x00bb0014 0x00000040
-DATA 4 0x00bb0028 0x00000020
-DATA 4 0x00bb002c 0x00000020
-DATA 4 0x021b001c 0x04088032
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x00048031
-DATA 4 0x021b001c 0x09408030
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00011117
-DATA 4 0x021b4818 0x00011117
-DATA 4 0x021b0004 0x00025576
-DATA 4 0x021b0404 0x00011006
-DATA 4 0x021b001c 0x00000000
-/* set the default clock gate to save power */
-DATA 4, 0x020c4068, 0x00C03F3F
-DATA 4, 0x020c406c, 0x0030FC03
-DATA 4, 0x020c4070, 0x0FFFC000
-DATA 4, 0x020c4074, 0x3FF00000
-DATA 4, 0x020c4078, 0xFFFFF300
-DATA 4, 0x020c407c, 0x0F0000F3
-DATA 4, 0x020c4080, 0x00000FFF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, 0x020e0010, 0xF00000CF
-/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
-DATA 4, 0x020e0018, 0x77177717
-DATA 4, 0x020e001c, 0x77177717
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
deleted file mode 100644
index a3ed4cd..0000000
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ /dev/null
@@ -1,676 +0,0 @@
-/*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
-#include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/spi.h>
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/sys_proto.h>
-#include <i2c.h>
-#include <asm/arch/mxc_hdmi.h>
-#include <asm/imx-common/video.h>
-#include <asm/arch/crm_regs.h>
-#include <pca953x.h>
-#include <power/pmic.h>
-#include <power/pfuze100_pmic.h>
-#include "../common/pfuze.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
-	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
-	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
-	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
-	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
-#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
-			PAD_CTL_SRE_FAST)
-#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
-	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
-
-#define I2C_PMIC	1
-
-int dram_init(void)
-{
-	gd->ram_size = imx_ddr_size();
-
-	return 0;
-}
-
-static iomux_v3_cfg_t const uart4_pads[] = {
-	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const enet_pads[] = {
-	MX6_PAD_KEY_COL1__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_KEY_COL2__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
-static struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
-		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
-		.gp = IMX_GPIO_NR(2, 30)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
-		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
-		.gp = IMX_GPIO_NR(4, 13)
-	}
-};
-
-#ifndef CONFIG_SYS_FLASH_CFI
-/*
- * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
- * Compass Sensor, Accelerometer, Res Touch
- */
-static struct i2c_pads_info i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
-		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
-		.gp = IMX_GPIO_NR(1, 3)
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
-		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
-		.gp = IMX_GPIO_NR(3, 18)
-	}
-};
-#endif
-
-static iomux_v3_cfg_t const i2c3_pads[] = {
-	MX6_PAD_EIM_A24__GPIO5_IO04		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const port_exp[] = {
-	MX6_PAD_SD2_DAT0__GPIO1_IO15		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-/*Define for building port exp gpio, pin starts from 0*/
-#define PORTEXP_IO_NR(chip, pin) \
-	((chip << 5) + pin)
-
-/*Get the chip addr from a ioexp gpio*/
-#define PORTEXP_IO_TO_CHIP(gpio_nr) \
-	(gpio_nr >> 5)
-
-/*Get the pin number from a ioexp gpio*/
-#define PORTEXP_IO_TO_PIN(gpio_nr) \
-	(gpio_nr & 0x1f)
-
-static int port_exp_direction_output(unsigned gpio, int value)
-{
-	int ret;
-
-	i2c_set_bus_num(2);
-	ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
-	if (ret)
-		return ret;
-
-	ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
-		(1 << PORTEXP_IO_TO_PIN(gpio)),
-		(PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
-
-	if (ret)
-		return ret;
-
-	ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
-		(1 << PORTEXP_IO_TO_PIN(gpio)),
-		(value << PORTEXP_IO_TO_PIN(gpio)));
-
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-static iomux_v3_cfg_t const eimnor_pads[] = {
-	MX6_PAD_EIM_D16__EIM_DATA16	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_D17__EIM_DATA17	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_D18__EIM_DATA18	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_D19__EIM_DATA19	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_D20__EIM_DATA20	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_D21__EIM_DATA21	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_D22__EIM_DATA22	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_D23__EIM_DATA23	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_D24__EIM_DATA24	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_D25__EIM_DATA25	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_D26__EIM_DATA26	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_D27__EIM_DATA27	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_D28__EIM_DATA28	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_D29__EIM_DATA29	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_D30__EIM_DATA30	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_D31__EIM_DATA31	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_DA0__EIM_AD00	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_DA1__EIM_AD01	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_DA2__EIM_AD02	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_DA3__EIM_AD03	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_DA4__EIM_AD04	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_DA5__EIM_AD05	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_DA6__EIM_AD06	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_DA7__EIM_AD07	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_DA8__EIM_AD08	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_DA9__EIM_AD09	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_DA10__EIM_AD10	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_DA11__EIM_AD11	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
-	MX6_PAD_EIM_DA12__EIM_AD12	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_DA13__EIM_AD13	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_DA14__EIM_AD14	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_DA15__EIM_AD15	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_A16__EIM_ADDR16	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_A17__EIM_ADDR17	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_A18__EIM_ADDR18	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_A19__EIM_ADDR19	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_A20__EIM_ADDR20	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_A21__EIM_ADDR21	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_A22__EIM_ADDR22	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_A23__EIM_ADDR23	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
-	MX6_PAD_EIM_OE__EIM_OE_B	| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_EIM_RW__EIM_RW		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_EIM_CS0__EIM_CS0_B	| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void eimnor_cs_setup(void)
-{
-	struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
-
-	writel(0x00020181, &weim_regs->cs0gcr1);
-	writel(0x00000001, &weim_regs->cs0gcr2);
-	writel(0x0a020000, &weim_regs->cs0rcr1);
-	writel(0x0000c000, &weim_regs->cs0rcr2);
-	writel(0x0804a240, &weim_regs->cs0wcr1);
-	writel(0x00000120, &weim_regs->wcr);
-
-	set_chipselect_size(CS0_128);
-}
-
-static void setup_iomux_eimnor(void)
-{
-	imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
-
-	gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
-
-	eimnor_cs_setup();
-}
-
-static void setup_iomux_enet(void)
-{
-	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-}
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__SD3_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__SD3_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__SD3_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__SD3_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__SD3_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__SD3_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT4__SD3_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__SD3_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT6__SD3_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__SD3_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_CS2__GPIO6_IO15   | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static void setup_iomux_uart(void)
-{
-	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
-}
-
-#ifdef CONFIG_FSL_ESDHC
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
-	{USDHC3_BASE_ADDR},
-};
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	gpio_direction_input(IMX_GPIO_NR(6, 15));
-	return !gpio_get_value(IMX_GPIO_NR(6, 15));
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-
-	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-}
-#endif
-
-#ifdef CONFIG_NAND_MXS
-static iomux_v3_cfg_t gpmi_pads[] = {
-	MX6_PAD_NANDF_CLE__NAND_CLE		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NANDF_ALE__NAND_ALE		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NANDF_WP_B__NAND_WP_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NANDF_RB0__NAND_READY_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL0),
-	MX6_PAD_NANDF_CS0__NAND_CE0_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_SD4_CMD__NAND_RE_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_SD4_CLK__NAND_WE_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NANDF_D0__NAND_DATA00	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NANDF_D1__NAND_DATA01	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NANDF_D2__NAND_DATA02	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NANDF_D3__NAND_DATA03	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NANDF_D4__NAND_DATA04	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NANDF_D5__NAND_DATA05	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NANDF_D6__NAND_DATA06	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_NANDF_D7__NAND_DATA07	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
-	MX6_PAD_SD4_DAT0__NAND_DQS		| MUX_PAD_CTRL(GPMI_PAD_CTRL1),
-};
-
-static void setup_gpmi_nand(void)
-{
-	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	/* config gpmi nand iomux */
-	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
-
-	setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
-			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
-			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
-
-	/* enable apbh clock gating */
-	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-}
-#endif
-
-static void setup_fec(void)
-{
-	if (is_mx6dqp()) {
-		/*
-		 * select ENET MAC0 TX clock from PLL
-		 */
-		imx_iomux_set_gpr_register(5, 9, 1, 1);
-		enable_fec_anatop_clock(0, ENET_125MHZ);
-	}
-
-	setup_iomux_enet();
-}
-
-int board_eth_init(bd_t *bis)
-{
-	setup_fec();
-
-	return cpu_eth_init(bis);
-}
-
-#define BOARD_REV_B  0x200
-#define BOARD_REV_A  0x100
-
-static int mx6sabre_rev(void)
-{
-	/*
-	 * Get Board ID information from OCOTP_GP1[15:8]
-	 * i.MX6Q ARD RevA: 0x01
-	 * i.MX6Q ARD RevB: 0x02
-	 */
-	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-	struct fuse_bank *bank = &ocotp->bank[4];
-	struct fuse_bank4_regs *fuse =
-			(struct fuse_bank4_regs *)bank->fuse_regs;
-	int reg = readl(&fuse->gp1);
-	int ret;
-
-	switch (reg >> 8 & 0x0F) {
-	case 0x02:
-		ret = BOARD_REV_B;
-		break;
-	case 0x01:
-	default:
-		ret = BOARD_REV_A;
-		break;
-	}
-
-	return ret;
-}
-
-u32 get_board_rev(void)
-{
-	int rev = mx6sabre_rev();
-
-	return (get_cpu_rev() & ~(0xF << 8)) | rev;
-}
-
-#if defined(CONFIG_VIDEO_IPUV3)
-static void disable_lvds(struct display_info_t const *dev)
-{
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	clrbits_le32(&iomux->gpr[2],
-		     IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
-		     IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
-}
-
-static void do_enable_hdmi(struct display_info_t const *dev)
-{
-	disable_lvds(dev);
-	imx_enable_hdmi_phy();
-}
-
-struct display_info_t const displays[] = {{
-	.bus	= -1,
-	.addr	= 0,
-	.pixfmt	= IPU_PIX_FMT_RGB666,
-	.detect	= NULL,
-	.enable	= NULL,
-	.mode	= {
-		.name           = "Hannstar-XGA",
-		.refresh        = 60,
-		.xres           = 1024,
-		.yres           = 768,
-		.pixclock       = 15385,
-		.left_margin    = 220,
-		.right_margin   = 40,
-		.upper_margin   = 21,
-		.lower_margin   = 7,
-		.hsync_len      = 60,
-		.vsync_len      = 10,
-		.sync           = FB_SYNC_EXT,
-		.vmode          = FB_VMODE_NONINTERLACED
-} }, {
-	.bus	= -1,
-	.addr	= 0,
-	.pixfmt	= IPU_PIX_FMT_RGB24,
-	.detect	= detect_hdmi,
-	.enable	= do_enable_hdmi,
-	.mode	= {
-		.name           = "HDMI",
-		.refresh        = 60,
-		.xres           = 1024,
-		.yres           = 768,
-		.pixclock       = 15385,
-		.left_margin    = 220,
-		.right_margin   = 40,
-		.upper_margin   = 21,
-		.lower_margin   = 7,
-		.hsync_len      = 60,
-		.vsync_len      = 10,
-		.sync           = FB_SYNC_EXT,
-		.vmode          = FB_VMODE_NONINTERLACED,
-} } };
-size_t display_count = ARRAY_SIZE(displays);
-
-iomux_v3_cfg_t const backlight_pads[] = {
-	MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_backlight(void)
-{
-	gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
-	imx_iomux_v3_setup_multiple_pads(backlight_pads,
-					 ARRAY_SIZE(backlight_pads));
-}
-
-static void setup_display(void)
-{
-	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	int reg;
-
-	setup_iomux_backlight();
-	enable_ipu_clock();
-	imx_setup_hdmi();
-
-	/* Turn on LDB_DI0 and LDB_DI1 clocks */
-	reg = readl(&mxc_ccm->CCGR3);
-	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
-	writel(reg, &mxc_ccm->CCGR3);
-
-	/* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
-	reg = readl(&mxc_ccm->cs2cdr);
-	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
-		 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
-	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
-	       (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
-	writel(reg, &mxc_ccm->cs2cdr);
-
-	reg = readl(&mxc_ccm->cscmr2);
-	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
-	writel(reg, &mxc_ccm->cscmr2);
-
-	reg = readl(&mxc_ccm->chsccdr);
-	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
-	reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
-		MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
-	writel(reg, &mxc_ccm->chsccdr);
-
-	reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
-	      IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
-	      IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
-	      IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
-	      IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
-	      IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
-	      IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
-	      IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
-	writel(reg, &iomux->gpr[2]);
-
-	reg = readl(&iomux->gpr[3]);
-	reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
-		 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
-	reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
-		IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
-	       (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
-		IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
-	writel(reg, &iomux->gpr[3]);
-}
-#endif /* CONFIG_VIDEO_IPUV3 */
-
-/*
- * Do not overwrite the console
- * Use always serial for U-Boot console
- */
-int overwrite_console(void)
-{
-	return 1;
-}
-
-int board_early_init_f(void)
-{
-	setup_iomux_uart();
-
-#ifdef CONFIG_NAND_MXS
-	setup_gpmi_nand();
-#endif
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-	/* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	/* I2C 3 Steer */
-	gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
-	imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
-#ifndef CONFIG_SYS_FLASH_CFI
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-#endif
-	gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
-	imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
-
-#ifdef CONFIG_VIDEO_IPUV3
-	setup_display();
-#endif
-	setup_iomux_eimnor();
-	return 0;
-}
-
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
-	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
-}
-#endif
-
-int power_init_board(void)
-{
-	struct pmic *p;
-	unsigned int value;
-
-	p = pfuze_common_init(I2C_PMIC);
-	if (!p)
-		return -ENODEV;
-
-	if (is_mx6dqp()) {
-		/* set SW2 staby volatage 0.975V*/
-		pmic_reg_read(p, PFUZE100_SW2STBY, &value);
-		value &= ~0x3f;
-		value |= 0x17;
-		pmic_reg_write(p, PFUZE100_SW2STBY, value);
-	}
-
-	return pfuze_mode_init(p, APS_PFM);
-}
-
-#ifdef CONFIG_CMD_BMODE
-static const struct boot_mode board_boot_modes[] = {
-	/* 4 bit bus width */
-	{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
-	{NULL,   0},
-};
-#endif
-
-int board_late_init(void)
-{
-#ifdef CONFIG_CMD_BMODE
-	add_board_boot_modes(board_boot_modes);
-#endif
-
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	setenv("board_name", "SABREAUTO");
-
-	if (is_mx6dqp())
-		setenv("board_rev", "MX6QP");
-	else if (is_mx6dq())
-		setenv("board_rev", "MX6Q");
-	else if (is_mx6sdl())
-		setenv("board_rev", "MX6DL");
-#endif
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	int rev = mx6sabre_rev();
-	char *revname;
-
-	switch (rev) {
-	case BOARD_REV_B:
-		revname = "B";
-		break;
-	case BOARD_REV_A:
-	default:
-		revname = "A";
-		break;
-	}
-
-	printf("Board: MX6Q-Sabreauto rev%s\n", revname);
-
-	return 0;
-}
-
-#ifdef CONFIG_USB_EHCI_MX6
-#define USB_HOST1_PWR     PORTEXP_IO_NR(0x32, 7)
-#define USB_OTG_PWR       PORTEXP_IO_NR(0x34, 1)
-
-iomux_v3_cfg_t const usb_otg_pads[] = {
-	MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-int board_ehci_hcd_init(int port)
-{
-	switch (port) {
-	case 0:
-		imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
-			ARRAY_SIZE(usb_otg_pads));
-
-		/*
-		  * Set daisy chain for otg_pin_id on 6q.
-		 *  For 6dl, this bit is reserved.
-		 */
-		imx_iomux_set_gpr_register(1, 13, 1, 0);
-		break;
-	case 1:
-		break;
-	default:
-		printf("MXC USB port %d not yet supported\n", port);
-		return -EINVAL;
-	}
-	return 0;
-}
-
-int board_ehci_power(int port, int on)
-{
-	switch (port) {
-	case 0:
-		if (on)
-			port_exp_direction_output(USB_OTG_PWR, 1);
-		else
-			port_exp_direction_output(USB_OTG_PWR, 0);
-		break;
-	case 1:
-		if (on)
-			port_exp_direction_output(USB_HOST1_PWR, 1);
-		else
-			port_exp_direction_output(USB_HOST1_PWR, 0);
-		break;
-	default:
-		printf("MXC USB port %d not yet supported\n", port);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/mx6sabreauto/Kconfig b/board/freescale/mx6sabreauto/Kconfig
new file mode 100644
index 0000000..5b4faf6
--- /dev/null
+++ b/board/freescale/mx6sabreauto/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6SABREAUTO
+
+config SYS_BOARD
+	default "mx6sabreauto"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6sabreauto"
+
+endif
diff --git a/board/freescale/mx6sabreauto/MAINTAINERS b/board/freescale/mx6sabreauto/MAINTAINERS
new file mode 100644
index 0000000..a89f05a
--- /dev/null
+++ b/board/freescale/mx6sabreauto/MAINTAINERS
@@ -0,0 +1,7 @@
+MX6SABREAUTO BOARD
+M:	Fabio Estevam <fabio.estevam@nxp.com>
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/mx6sabreauto/
+F:	include/configs/mx6sabreauto.h
+F:	configs/mx6sabreauto_defconfig
diff --git a/board/freescale/mx6sabreauto/Makefile b/board/freescale/mx6sabreauto/Makefile
new file mode 100644
index 0000000..87f4ec0
--- /dev/null
+++ b/board/freescale/mx6sabreauto/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx6sabreauto.o
diff --git a/board/freescale/mx6sabreauto/README b/board/freescale/mx6sabreauto/README
new file mode 100644
index 0000000..e8c589b
--- /dev/null
+++ b/board/freescale/mx6sabreauto/README
@@ -0,0 +1,82 @@
+How to use and build U-Boot on mx6sabreauto
+-------------------------------------------
+
+mx6sabreauto_defconfig target supports mx6q/mx6dl/mx6qp sabreauto variants.
+
+In order to build it:
+
+$ make mx6sabreauto_defconfig
+
+$ make
+
+This will generate the SPL and u-boot.img binaries.
+
+- Flash the SPL binary into the SD card:
+
+$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
+
+- Flash the u-boot.img binary into the SD card:
+
+$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync
+
+Booting via Falcon mode
+-----------------------
+
+Write in mx6sabreauto_defconfig the following define below:
+
+CONFIG_SPL_OS_BOOT=y
+
+In order to build it:
+
+$ make mx6sabreauto_defconfig
+
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the SD card:
+
+$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync
+
+- Flash the u-boot.img image into the SD card:
+
+$ sudo dd if=u-boot.img of=/dev/sdb bs=1K seek=69 && sync
+
+Create a FAT16 boot partition to store uImage and the dtb file, then copy the files there:
+
+$ sudo cp uImage /media/boot
+
+$ sudo cp imx6dl-sabreauto.dtb /media/boot
+
+Create a partition for root file system and extract it there:
+
+$ sudo tar xvf rootfs.tar.gz -C /media/root
+
+The SD card must have enough space for raw "args" and "kernel".
+To configure Falcon mode for the first time, on U-Boot do the following commands:
+
+- Load dtb file from boot partition:
+
+# load mmc 0:1 ${fdt_addr} imx6dl-sabreauto.dtb
+
+- Load kernel image from boot partition:
+
+# load mmc 0:1 ${loadaddr} uImage
+
+- Write kernel at 2MB offset:
+
+# mmc write ${loadaddr} 0x1000 0x4000
+
+- Setup kernel bootargs:
+
+# setenv bootargs "console=ttymxc3,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait quiet rw"
+
+- Prepare args:
+
+# spl export fdt ${loadaddr} - ${fdt_addr}
+
+- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
+
+# mmc write 18000000 0x800 0x800
+
+- Restart the board and then SPL binary will launch the kernel directly.
diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c
new file mode 100644
index 0000000..a5703a3
--- /dev/null
+++ b/board/freescale/mx6sabreauto/mx6sabreauto.c
@@ -0,0 +1,1159 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/spi.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/mach-imx/video.h>
+#include <asm/arch/crm_regs.h>
+#include <pca953x.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+			PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define I2C_PMIC	1
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+	IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+	IOMUX_PADS(PAD_KEY_COL1__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_COL2__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+};
+
+/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
+static struct i2c_pads_info mx6q_i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
+		.gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
+		.gp = IMX_GPIO_NR(2, 30)
+	},
+	.sda = {
+		.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
+		.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
+		.gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
+		.gp = IMX_GPIO_NR(2, 30)
+	},
+	.sda = {
+		.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
+		.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+#ifndef CONFIG_SYS_FLASH_CFI
+/*
+ * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
+ * Compass Sensor, Accelerometer, Res Touch
+ */
+static struct i2c_pads_info mx6q_i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		.i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
+		.gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
+		.gp = IMX_GPIO_NR(3, 18)
+	}
+};
+
+static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		.i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
+		.gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
+		.gp = IMX_GPIO_NR(3, 18)
+	}
+};
+#endif
+
+static iomux_v3_cfg_t const i2c3_pads[] = {
+	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const port_exp[] = {
+	IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+/*Define for building port exp gpio, pin starts from 0*/
+#define PORTEXP_IO_NR(chip, pin) \
+	((chip << 5) + pin)
+
+/*Get the chip addr from a ioexp gpio*/
+#define PORTEXP_IO_TO_CHIP(gpio_nr) \
+	(gpio_nr >> 5)
+
+/*Get the pin number from a ioexp gpio*/
+#define PORTEXP_IO_TO_PIN(gpio_nr) \
+	(gpio_nr & 0x1f)
+
+static int port_exp_direction_output(unsigned gpio, int value)
+{
+	int ret;
+
+	i2c_set_bus_num(2);
+	ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
+	if (ret)
+		return ret;
+
+	ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
+		(1 << PORTEXP_IO_TO_PIN(gpio)),
+		(PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
+
+	if (ret)
+		return ret;
+
+	ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
+		(1 << PORTEXP_IO_TO_PIN(gpio)),
+		(value << PORTEXP_IO_TO_PIN(gpio)));
+
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+#ifdef CONFIG_MTD_NOR_FLASH
+static iomux_v3_cfg_t const eimnor_pads[] = {
+	IOMUX_PADS(PAD_EIM_D16__EIM_DATA16	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D17__EIM_DATA17	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D18__EIM_DATA18	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D19__EIM_DATA19	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D20__EIM_DATA20	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D21__EIM_DATA21	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D22__EIM_DATA22	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D23__EIM_DATA23	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D24__EIM_DATA24	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D25__EIM_DATA25	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D26__EIM_DATA26	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D27__EIM_DATA27	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D28__EIM_DATA28	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D29__EIM_DATA29	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D30__EIM_DATA30	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D31__EIM_DATA31	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA0__EIM_AD00	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA1__EIM_AD01	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA2__EIM_AD02	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA3__EIM_AD03	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA4__EIM_AD04	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA5__EIM_AD05	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA6__EIM_AD06	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA7__EIM_AD07	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA8__EIM_AD08	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA9__EIM_AD09	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA10__EIM_AD10	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA11__EIM_AD11	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA12__EIM_AD12	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA13__EIM_AD13	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA14__EIM_AD14	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA15__EIM_AD15	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23	| MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_OE__EIM_OE_B		| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_RW__EIM_RW		| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void eimnor_cs_setup(void)
+{
+	struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+	writel(0x00020181, &weim_regs->cs0gcr1);
+	writel(0x00000001, &weim_regs->cs0gcr2);
+	writel(0x0a020000, &weim_regs->cs0rcr1);
+	writel(0x0000c000, &weim_regs->cs0rcr2);
+	writel(0x0804a240, &weim_regs->cs0wcr1);
+	writel(0x00000120, &weim_regs->wcr);
+
+	set_chipselect_size(CS0_128);
+}
+
+static void eim_clk_setup(void)
+{
+	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int cscmr1, ccgr6;
+
+
+	/* Turn off EIM clock */
+	ccgr6 = readl(&imx_ccm->CCGR6);
+	ccgr6 &= ~(0x3 << 10);
+	writel(ccgr6, &imx_ccm->CCGR6);
+
+	/*
+	 * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
+	 * and aclk_eim_slow_podf = 01 --> divide by 2
+	 * so that we can have EIM at the maximum clock of 132MHz
+	 */
+	cscmr1 = readl(&imx_ccm->cscmr1);
+	cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
+		    MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
+	cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
+	writel(cscmr1, &imx_ccm->cscmr1);
+
+	/* Turn on EIM clock */
+	ccgr6 |= (0x3 << 10);
+	writel(ccgr6, &imx_ccm->CCGR6);
+}
+
+static void setup_iomux_eimnor(void)
+{
+	SETUP_IOMUX_PADS(eimnor_pads);
+
+	gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+
+	eimnor_cs_setup();
+}
+#endif
+
+static void setup_iomux_enet(void)
+{
+	SETUP_IOMUX_PADS(enet_pads);
+}
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart4_pads);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	gpio_direction_input(IMX_GPIO_NR(6, 15));
+	return !gpio_get_value(IMX_GPIO_NR(6, 15));
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	SETUP_IOMUX_PADS(usdhc3_pads);
+
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t gpmi_pads[] = {
+	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
+	IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+	IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS	| MUX_PAD_CTRL(GPMI_PAD_CTRL1)),
+};
+
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	SETUP_IOMUX_PADS(gpmi_pads);
+
+	setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+static void setup_fec(void)
+{
+	if (is_mx6dqp()) {
+		/*
+		 * select ENET MAC0 TX clock from PLL
+		 */
+		imx_iomux_set_gpr_register(5, 9, 1, 1);
+		enable_fec_anatop_clock(0, ENET_125MHZ);
+	}
+
+	setup_iomux_enet();
+}
+
+int board_eth_init(bd_t *bis)
+{
+	setup_fec();
+
+	return cpu_eth_init(bis);
+}
+
+#define BOARD_REV_B  0x200
+#define BOARD_REV_A  0x100
+
+static int mx6sabre_rev(void)
+{
+	/*
+	 * Get Board ID information from OCOTP_GP1[15:8]
+	 * i.MX6Q ARD RevA: 0x01
+	 * i.MX6Q ARD RevB: 0x02
+	 */
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[4];
+	struct fuse_bank4_regs *fuse =
+			(struct fuse_bank4_regs *)bank->fuse_regs;
+	int reg = readl(&fuse->gp1);
+	int ret;
+
+	switch (reg >> 8 & 0x0F) {
+	case 0x02:
+		ret = BOARD_REV_B;
+		break;
+	case 0x01:
+	default:
+		ret = BOARD_REV_A;
+		break;
+	}
+
+	return ret;
+}
+
+u32 get_board_rev(void)
+{
+	int rev = mx6sabre_rev();
+
+	return (get_cpu_rev() & ~(0xF << 8)) | rev;
+}
+
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	ar8031_phy_fixup(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static void disable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	clrbits_le32(&iomux->gpr[2],
+		     IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
+		     IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
+}
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	disable_lvds(dev);
+	imx_enable_hdmi_phy();
+}
+
+struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB666,
+	.detect	= NULL,
+	.enable	= NULL,
+	.mode	= {
+		.name           = "Hannstar-XGA",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED,
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+iomux_v3_cfg_t const backlight_pads[] = {
+	IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+};
+
+static void setup_iomux_backlight(void)
+{
+	gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
+	SETUP_IOMUX_PADS(backlight_pads);
+}
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	setup_iomux_backlight();
+	enable_ipu_clock();
+	imx_setup_hdmi();
+
+	/* Turn on LDB_DI0 and LDB_DI1 clocks */
+	reg = readl(&mxc_ccm->CCGR3);
+	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+		 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+	       (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
+		MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
+	      IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+	      IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+	      IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
+	      IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+	      IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+	      IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
+	      IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+		 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
+	reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+		IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
+	       (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+		IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+	eim_clk_setup();
+#endif
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
+	if (is_mx6dq() || is_mx6dqp())
+		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
+	else
+		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
+	/* I2C 3 Steer */
+	gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
+	SETUP_IOMUX_PADS(i2c3_pads);
+#ifndef CONFIG_SYS_FLASH_CFI
+	if (is_mx6dq() || is_mx6dqp())
+		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
+	else
+		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
+#endif
+	gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
+	SETUP_IOMUX_PADS(port_exp);
+
+#ifdef CONFIG_VIDEO_IPUV3
+	setup_display();
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+	setup_iomux_eimnor();
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
+}
+#endif
+
+int power_init_board(void)
+{
+	struct pmic *p;
+	unsigned int value;
+
+	p = pfuze_common_init(I2C_PMIC);
+	if (!p)
+		return -ENODEV;
+
+	if (is_mx6dqp()) {
+		/* set SW2 staby volatage 0.975V*/
+		pmic_reg_read(p, PFUZE100_SW2STBY, &value);
+		value &= ~0x3f;
+		value |= 0x17;
+		pmic_reg_write(p, PFUZE100_SW2STBY, value);
+	}
+
+	return pfuze_mode_init(p, APS_PFM);
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{NULL,   0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	setenv("board_name", "SABREAUTO");
+
+	if (is_mx6dqp())
+		setenv("board_rev", "MX6QP");
+	else if (is_mx6dq())
+		setenv("board_rev", "MX6Q");
+	else if (is_mx6sdl())
+		setenv("board_rev", "MX6DL");
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	int rev = mx6sabre_rev();
+	char *revname;
+
+	switch (rev) {
+	case BOARD_REV_B:
+		revname = "B";
+		break;
+	case BOARD_REV_A:
+	default:
+		revname = "A";
+		break;
+	}
+
+	printf("Board: MX6Q-Sabreauto rev%s\n", revname);
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_HOST1_PWR     PORTEXP_IO_NR(0x32, 7)
+#define USB_OTG_PWR       PORTEXP_IO_NR(0x34, 1)
+
+iomux_v3_cfg_t const usb_otg_pads[] = {
+	IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+int board_ehci_hcd_init(int port)
+{
+	switch (port) {
+	case 0:
+		SETUP_IOMUX_PADS(usb_otg_pads);
+
+		/*
+		  * Set daisy chain for otg_pin_id on 6q.
+		 *  For 6dl, this bit is reserved.
+		 */
+		imx_iomux_set_gpr_register(1, 13, 1, 0);
+		break;
+	case 1:
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	switch (port) {
+	case 0:
+		if (on)
+			port_exp_direction_output(USB_OTG_PWR, 1);
+		else
+			port_exp_direction_output(USB_OTG_PWR, 0);
+		break;
+	case 1:
+		if (on)
+			port_exp_direction_output(USB_HOST1_PWR, 1);
+		else
+			port_exp_direction_output(USB_HOST1_PWR, 0);
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#include <asm/arch/mx6-ddr.h>
+#include <spl.h>
+#include <libfdt.h>
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	return 0;
+}
+#endif
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* enable AXI cache for VDOA/VPU/IPU */
+	writel(0xF00000CF, &iomux->gpr[4]);
+	if (is_mx6dqp()) {
+		/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+		writel(0x007F007F, &iomux->gpr[6]);
+		writel(0x007F007F, &iomux->gpr[7]);
+	} else {
+		/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+		writel(0x007F007F, &iomux->gpr[6]);
+		writel(0x007F007F, &iomux->gpr[7]);
+	}
+}
+
+static int mx6q_dcd_table[] = {
+	0x020e0798, 0x000C0000,
+	0x020e0758, 0x00000000,
+	0x020e0588, 0x00000030,
+	0x020e0594, 0x00000030,
+	0x020e056c, 0x00000030,
+	0x020e0578, 0x00000030,
+	0x020e074c, 0x00000030,
+	0x020e057c, 0x00000030,
+	0x020e058c, 0x00000000,
+	0x020e059c, 0x00000030,
+	0x020e05a0, 0x00000030,
+	0x020e078c, 0x00000030,
+	0x020e0750, 0x00020000,
+	0x020e05a8, 0x00000028,
+	0x020e05b0, 0x00000028,
+	0x020e0524, 0x00000028,
+	0x020e051c, 0x00000028,
+	0x020e0518, 0x00000028,
+	0x020e050c, 0x00000028,
+	0x020e05b8, 0x00000028,
+	0x020e05c0, 0x00000028,
+	0x020e0774, 0x00020000,
+	0x020e0784, 0x00000028,
+	0x020e0788, 0x00000028,
+	0x020e0794, 0x00000028,
+	0x020e079c, 0x00000028,
+	0x020e07a0, 0x00000028,
+	0x020e07a4, 0x00000028,
+	0x020e07a8, 0x00000028,
+	0x020e0748, 0x00000028,
+	0x020e05ac, 0x00000028,
+	0x020e05b4, 0x00000028,
+	0x020e0528, 0x00000028,
+	0x020e0520, 0x00000028,
+	0x020e0514, 0x00000028,
+	0x020e0510, 0x00000028,
+	0x020e05bc, 0x00000028,
+	0x020e05c4, 0x00000028,
+	0x021b0800, 0xa1390003,
+	0x021b080c, 0x001F001F,
+	0x021b0810, 0x001F001F,
+	0x021b480c, 0x001F001F,
+	0x021b4810, 0x001F001F,
+	0x021b083c, 0x43260335,
+	0x021b0840, 0x031A030B,
+	0x021b483c, 0x4323033B,
+	0x021b4840, 0x0323026F,
+	0x021b0848, 0x483D4545,
+	0x021b4848, 0x44433E48,
+	0x021b0850, 0x41444840,
+	0x021b4850, 0x4835483E,
+	0x021b081c, 0x33333333,
+	0x021b0820, 0x33333333,
+	0x021b0824, 0x33333333,
+	0x021b0828, 0x33333333,
+	0x021b481c, 0x33333333,
+	0x021b4820, 0x33333333,
+	0x021b4824, 0x33333333,
+	0x021b4828, 0x33333333,
+	0x021b08b8, 0x00000800,
+	0x021b48b8, 0x00000800,
+	0x021b0004, 0x00020036,
+	0x021b0008, 0x09444040,
+	0x021b000c, 0x8A8F7955,
+	0x021b0010, 0xFF328F64,
+	0x021b0014, 0x01FF00DB,
+	0x021b0018, 0x00001740,
+	0x021b001c, 0x00008000,
+	0x021b002c, 0x000026d2,
+	0x021b0030, 0x008F1023,
+	0x021b0040, 0x00000047,
+	0x021b0000, 0x841A0000,
+	0x021b001c, 0x04088032,
+	0x021b001c, 0x00008033,
+	0x021b001c, 0x00048031,
+	0x021b001c, 0x09408030,
+	0x021b001c, 0x04008040,
+	0x021b0020, 0x00005800,
+	0x021b0818, 0x00011117,
+	0x021b4818, 0x00011117,
+	0x021b0004, 0x00025576,
+	0x021b0404, 0x00011006,
+	0x021b001c, 0x00000000,
+	0x020c4068, 0x00C03F3F,
+	0x020c406c, 0x0030FC03,
+	0x020c4070, 0x0FFFC000,
+	0x020c4074, 0x3FF00000,
+	0x020c4078, 0xFFFFF300,
+	0x020c407c, 0x0F0000F3,
+	0x020c4080, 0x00000FFF,
+	0x020e0010, 0xF00000CF,
+	0x020e0018, 0x007F007F,
+	0x020e001c, 0x007F007F,
+};
+
+static int mx6qp_dcd_table[] = {
+	0x020e0798, 0x000C0000,
+	0x020e0758, 0x00000000,
+	0x020e0588, 0x00000030,
+	0x020e0594, 0x00000030,
+	0x020e056c, 0x00000030,
+	0x020e0578, 0x00000030,
+	0x020e074c, 0x00000030,
+	0x020e057c, 0x00000030,
+	0x020e058c, 0x00000000,
+	0x020e059c, 0x00000030,
+	0x020e05a0, 0x00000030,
+	0x020e078c, 0x00000030,
+	0x020e0750, 0x00020000,
+	0x020e05a8, 0x00000030,
+	0x020e05b0, 0x00000030,
+	0x020e0524, 0x00000030,
+	0x020e051c, 0x00000030,
+	0x020e0518, 0x00000030,
+	0x020e050c, 0x00000030,
+	0x020e05b8, 0x00000030,
+	0x020e05c0, 0x00000030,
+	0x020e0774, 0x00020000,
+	0x020e0784, 0x00000030,
+	0x020e0788, 0x00000030,
+	0x020e0794, 0x00000030,
+	0x020e079c, 0x00000030,
+	0x020e07a0, 0x00000030,
+	0x020e07a4, 0x00000030,
+	0x020e07a8, 0x00000030,
+	0x020e0748, 0x00000030,
+	0x020e05ac, 0x00000030,
+	0x020e05b4, 0x00000030,
+	0x020e0528, 0x00000030,
+	0x020e0520, 0x00000030,
+	0x020e0514, 0x00000030,
+	0x020e0510, 0x00000030,
+	0x020e05bc, 0x00000030,
+	0x020e05c4, 0x00000030,
+	0x021b0800, 0xa1390003,
+	0x021b080c, 0x001b001e,
+	0x021b0810, 0x002e0029,
+	0x021b480c, 0x001b002a,
+	0x021b4810, 0x0019002c,
+	0x021b083c, 0x43240334,
+	0x021b0840, 0x0324031a,
+	0x021b483c, 0x43340344,
+	0x021b4840, 0x03280276,
+	0x021b0848, 0x44383A3E,
+	0x021b4848, 0x3C3C3846,
+	0x021b0850, 0x2e303230,
+	0x021b4850, 0x38283E34,
+	0x021b081c, 0x33333333,
+	0x021b0820, 0x33333333,
+	0x021b0824, 0x33333333,
+	0x021b0828, 0x33333333,
+	0x021b481c, 0x33333333,
+	0x021b4820, 0x33333333,
+	0x021b4824, 0x33333333,
+	0x021b4828, 0x33333333,
+	0x021b08c0, 0x24912492,
+	0x021b48c0, 0x24912492,
+	0x021b08b8, 0x00000800,
+	0x021b48b8, 0x00000800,
+	0x021b0004, 0x00020036,
+	0x021b0008, 0x09444040,
+	0x021b000c, 0x898E7955,
+	0x021b0010, 0xFF328F64,
+	0x021b0014, 0x01FF00DB,
+	0x021b0018, 0x00001740,
+	0x021b001c, 0x00008000,
+	0x021b002c, 0x000026d2,
+	0x021b0030, 0x008E1023,
+	0x021b0040, 0x00000047,
+	0x021b0400, 0x14420000,
+	0x021b0000, 0x841A0000,
+	0x00bb0008, 0x00000004,
+	0x00bb000c, 0x2891E41A,
+	0x00bb0038, 0x00000564,
+	0x00bb0014, 0x00000040,
+	0x00bb0028, 0x00000020,
+	0x00bb002c, 0x00000020,
+	0x021b001c, 0x04088032,
+	0x021b001c, 0x00008033,
+	0x021b001c, 0x00048031,
+	0x021b001c, 0x09408030,
+	0x021b001c, 0x04008040,
+	0x021b0020, 0x00005800,
+	0x021b0818, 0x00011117,
+	0x021b4818, 0x00011117,
+	0x021b0004, 0x00025576,
+	0x021b0404, 0x00011006,
+	0x021b001c, 0x00000000,
+	0x020c4068, 0x00C03F3F,
+	0x020c406c, 0x0030FC03,
+	0x020c4070, 0x0FFFC000,
+	0x020c4074, 0x3FF00000,
+	0x020c4078, 0xFFFFF300,
+	0x020c407c, 0x0F0000F3,
+	0x020c4080, 0x00000FFF,
+	0x020e0010, 0xF00000CF,
+	0x020e0018, 0x77177717,
+	0x020e001c, 0x77177717,
+};
+
+static int mx6dl_dcd_table[] = {
+	0x020e0774, 0x000C0000,
+	0x020e0754, 0x00000000,
+	0x020e04ac, 0x00000030,
+	0x020e04b0, 0x00000030,
+	0x020e0464, 0x00000030,
+	0x020e0490, 0x00000030,
+	0x020e074c, 0x00000030,
+	0x020e0494, 0x00000030,
+	0x020e04a0, 0x00000000,
+	0x020e04b4, 0x00000030,
+	0x020e04b8, 0x00000030,
+	0x020e076c, 0x00000030,
+	0x020e0750, 0x00020000,
+	0x020e04bc, 0x00000028,
+	0x020e04c0, 0x00000028,
+	0x020e04c4, 0x00000028,
+	0x020e04c8, 0x00000028,
+	0x020e04cc, 0x00000028,
+	0x020e04d0, 0x00000028,
+	0x020e04d4, 0x00000028,
+	0x020e04d8, 0x00000028,
+	0x020e0760, 0x00020000,
+	0x020e0764, 0x00000028,
+	0x020e0770, 0x00000028,
+	0x020e0778, 0x00000028,
+	0x020e077c, 0x00000028,
+	0x020e0780, 0x00000028,
+	0x020e0784, 0x00000028,
+	0x020e078c, 0x00000028,
+	0x020e0748, 0x00000028,
+	0x020e0470, 0x00000028,
+	0x020e0474, 0x00000028,
+	0x020e0478, 0x00000028,
+	0x020e047c, 0x00000028,
+	0x020e0480, 0x00000028,
+	0x020e0484, 0x00000028,
+	0x020e0488, 0x00000028,
+	0x020e048c, 0x00000028,
+	0x021b0800, 0xa1390003,
+	0x021b080c, 0x001F001F,
+	0x021b0810, 0x001F001F,
+	0x021b480c, 0x001F001F,
+	0x021b4810, 0x001F001F,
+	0x021b083c, 0x42190217,
+	0x021b0840, 0x017B017B,
+	0x021b483c, 0x4176017B,
+	0x021b4840, 0x015F016C,
+	0x021b0848, 0x4C4C4D4C,
+	0x021b4848, 0x4A4D4C48,
+	0x021b0850, 0x3F3F3F40,
+	0x021b4850, 0x3538382E,
+	0x021b081c, 0x33333333,
+	0x021b0820, 0x33333333,
+	0x021b0824, 0x33333333,
+	0x021b0828, 0x33333333,
+	0x021b481c, 0x33333333,
+	0x021b4820, 0x33333333,
+	0x021b4824, 0x33333333,
+	0x021b4828, 0x33333333,
+	0x021b08b8, 0x00000800,
+	0x021b48b8, 0x00000800,
+	0x021b0004, 0x00020025,
+	0x021b0008, 0x00333030,
+	0x021b000c, 0x676B5313,
+	0x021b0010, 0xB66E8B63,
+	0x021b0014, 0x01FF00DB,
+	0x021b0018, 0x00001740,
+	0x021b001c, 0x00008000,
+	0x021b002c, 0x000026d2,
+	0x021b0030, 0x006B1023,
+	0x021b0040, 0x00000047,
+	0x021b0000, 0x841A0000,
+	0x021b001c, 0x04008032,
+	0x021b001c, 0x00008033,
+	0x021b001c, 0x00048031,
+	0x021b001c, 0x05208030,
+	0x021b001c, 0x04008040,
+	0x021b0020, 0x00005800,
+	0x021b0818, 0x00011117,
+	0x021b4818, 0x00011117,
+	0x021b0004, 0x00025565,
+	0x021b0404, 0x00011006,
+	0x021b001c, 0x00000000,
+	0x020c4068, 0x00C03F3F,
+	0x020c406c, 0x0030FC03,
+	0x020c4070, 0x0FFFC000,
+	0x020c4074, 0x3FF00000,
+	0x020c4078, 0xFFFFF300,
+	0x020c407c, 0x0F0000C3,
+	0x020c4080, 0x00000FFF,
+	0x020e0010, 0xF00000CF,
+	0x020e0018, 0x007F007F,
+	0x020e001c, 0x007F007F,
+};
+
+static void ddr_init(int *table, int size)
+{
+	int i;
+
+	for (i = 0; i < size / 2 ; i++)
+		writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+	if (is_mx6dq())
+		ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
+	else if (is_mx6dqp())
+		ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
+	else if (is_mx6sdl())
+		ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
+}
+
+void board_init_f(ulong dummy)
+{
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* iomux and setup of i2c */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+#endif
diff --git a/board/freescale/mx6sabresd/MAINTAINERS b/board/freescale/mx6sabresd/MAINTAINERS
index add2314..9575261 100644
--- a/board/freescale/mx6sabresd/MAINTAINERS
+++ b/board/freescale/mx6sabresd/MAINTAINERS
@@ -3,6 +3,4 @@ M:	Fabio Estevam <fabio.estevam@nxp.com>
 S:	Maintained
 F:	board/freescale/mx6sabresd/
 F:	include/configs/mx6sabresd.h
-F:	configs/mx6dlsabresd_defconfig
-F:	configs/mx6qsabresd_defconfig
-F:	configs/mx6sabresd_spl_defconfig
+F:	configs/mx6sabresd_defconfig
diff --git a/board/freescale/mx6sabresd/README b/board/freescale/mx6sabresd/README
new file mode 100644
index 0000000..4b4df06
--- /dev/null
+++ b/board/freescale/mx6sabresd/README
@@ -0,0 +1,114 @@
+How to use and build U-Boot on mx6sabresd
+-----------------------------------------
+
+The following methods can be used for booting mx6sabresd boards:
+
+1. Booting from SD card
+
+2. Booting from eMMC
+
+3. Booting via Falcon mode (SPL launches the kernel directly)
+
+
+1. Booting from SD card via SPL
+-------------------------------
+
+mx6sabresd_defconfig target supports mx6q/mx6dl/mx6qp sabresd variants.
+
+In order to build it:
+
+$ make mx6sabresd_defconfig
+
+$ make
+
+This will generate the SPL and u-boot.img binaries.
+
+- Flash the SPL binary into the SD card:
+
+$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
+
+- Flash the u-boot.img binary into the SD card:
+
+$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync
+
+
+2. Booting from eMMC
+--------------------
+
+$ make mx6sabresd_defconfig
+
+$ make
+
+This will generate the SPL and u-boot.img binaries.
+
+- Boot first from SD card as shown in the previous section
+
+In U-boot change the eMMC partition config:
+
+=> mmc partconf 2 1 0 0
+
+Mount the eMMC in the host PC:
+
+=> ums 0 mmc 2
+
+- Flash SPL and u-boot.img binaries into the eMMC:
+
+$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
+$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync
+
+Set SW6 to eMMC 8-bit boot: 11010110
+
+
+3. Booting via Falcon mode
+--------------------------
+
+$ make mx6sabresd_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the SD card:
+
+$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 oflag=sync status=none && sync
+
+- Flash the u-boot.img image into the SD card:
+
+$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 oflag=sync status=none && sync
+
+Create a partition for root file system and extract it there:
+
+$ sudo tar xvf rootfs.tar.gz -C /media/root
+
+The SD card must have enough space for raw "args" and "kernel".
+To configure Falcon mode for the first time, on U-Boot do the following commands:
+
+- Setup the IP server:
+
+# setenv serverip <server_ip_address>
+
+- Download dtb file:
+
+# dhcp ${fdt_addr} imx6q-sabresd.dtb
+
+- Download kernel image:
+
+# dhcp ${loadaddr} uImage
+
+- Write kernel at 2MB offset:
+
+# mmc write ${loadaddr} 0x1000 0x4000
+
+- Setup kernel bootargs:
+
+# setenv bootargs "console=ttymxc0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait quiet rw"
+
+- Prepare args:
+
+# spl export fdt ${loadaddr} - ${fdt_addr}
+
+- Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
+
+# mmc write 18000000 0x800 0x800
+
+- Press KEY_VOL_UP key, power up the board and then SPL binary will
+launch the kernel directly.
diff --git a/board/freescale/mx6sabresd/mx6dlsabresd.cfg b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
deleted file mode 100644
index f35f22e..0000000
--- a/board/freescale/mx6sabresd/mx6dlsabresd.cfg
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Refer docs/README.imxmage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-
-BOOT_FROM	sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *	Addr-type register length (1,2 or 4 bytes)
- *	Address	  absolute address of the register
- *	value	  value to be stored in the register
- */
-DATA 4	0x020e0774 0x000C0000
-DATA 4	0x020e0754 0x00000000
-DATA 4	0x020e04ac 0x00000030
-DATA 4	0x020e04b0 0x00000030
-DATA 4	0x020e0464 0x00000030
-DATA 4	0x020e0490 0x00000030
-DATA 4	0x020e074c 0x00000030
-DATA 4	0x020e0494 0x00000030
-DATA 4	0x020e04a0 0x00000000
-DATA 4	0x020e04b4 0x00000030
-DATA 4	0x020e04b8 0x00000030
-DATA 4	0x020e076c 0x00000030
-DATA 4	0x020e0750 0x00020000
-DATA 4	0x020e04bc 0x00000030
-DATA 4	0x020e04c0 0x00000030
-DATA 4	0x020e04c4 0x00000030
-DATA 4	0x020e04c8 0x00000030
-DATA 4	0x020e04cc 0x00000030
-DATA 4	0x020e04d0 0x00000030
-DATA 4	0x020e04d4 0x00000030
-DATA 4	0x020e04d8 0x00000030
-DATA 4	0x020e0760 0x00020000
-DATA 4	0x020e0764 0x00000030
-DATA 4	0x020e0770 0x00000030
-DATA 4	0x020e0778 0x00000030
-DATA 4	0x020e077c 0x00000030
-DATA 4	0x020e0780 0x00000030
-DATA 4	0x020e0784 0x00000030
-DATA 4	0x020e078c 0x00000030
-DATA 4	0x020e0748 0x00000030
-DATA 4	0x020e0470 0x00000030
-DATA 4	0x020e0474 0x00000030
-DATA 4	0x020e0478 0x00000030
-DATA 4	0x020e047c 0x00000030
-DATA 4	0x020e0480 0x00000030
-DATA 4	0x020e0484 0x00000030
-DATA 4	0x020e0488 0x00000030
-DATA 4	0x020e048c 0x00000030
-DATA 4	0x021b0800 0xa1390003
-DATA 4	0x021b080c 0x001F001F
-DATA 4	0x021b0810 0x001F001F
-DATA 4	0x021b480c 0x001F001F
-DATA 4	0x021b4810 0x001F001F
-DATA 4	0x021b083c 0x4220021F
-DATA 4	0x021b0840 0x0207017E
-DATA 4	0x021b483c 0x4201020C
-DATA 4	0x021b4840 0x01660172
-DATA 4	0x021b0848 0x4A4D4E4D
-DATA 4	0x021b4848 0x4A4F5049
-DATA 4	0x021b0850 0x3F3C3D31
-DATA 4	0x021b4850 0x3238372B
-DATA 4	0x021b081c 0x33333333
-DATA 4	0x021b0820 0x33333333
-DATA 4	0x021b0824 0x33333333
-DATA 4	0x021b0828 0x33333333
-DATA 4	0x021b481c 0x33333333
-DATA 4	0x021b4820 0x33333333
-DATA 4	0x021b4824 0x33333333
-DATA 4	0x021b4828 0x33333333
-DATA 4	0x021b08b8 0x00000800
-DATA 4	0x021b48b8 0x00000800
-DATA 4	0x021b0004 0x0002002D
-DATA 4	0x021b0008 0x00333030
-DATA 4	0x021b000c 0x3F435313
-DATA 4	0x021b0010 0xB66E8B63
-DATA 4	0x021b0014 0x01FF00DB
-DATA 4	0x021b0018 0x00001740
-DATA 4	0x021b001c 0x00008000
-DATA 4	0x021b002c 0x000026d2
-DATA 4	0x021b0030 0x00431023
-DATA 4	0x021b0040 0x00000027
-DATA 4	0x021b0000 0x831A0000
-DATA 4	0x021b001c 0x04008032
-DATA 4	0x021b001c 0x00008033
-DATA 4	0x021b001c 0x00048031
-DATA 4	0x021b001c 0x05208030
-DATA 4 0x021b001c 0x04008040
-DATA 4	0x021b0020 0x00005800
-DATA 4	0x021b0818 0x00011117
-DATA 4	0x021b4818 0x00011117
-DATA 4	0x021b0004 0x0002556D
-DATA 4	0x021b0404 0x00011006
-DATA 4	0x021b001c 0x00000000
-
-/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0x00FFF300
-DATA 4 0x020c407c 0x0F0000C3
-DATA 4 0x020c4080 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
diff --git a/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
deleted file mode 100644
index bb6c60b..0000000
--- a/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- * Jason Liu <r64343@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM      sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *      Addr-type register length (1,2 or 4 bytes)
- *      Address   absolute address of the register
- *      value     value to be stored in the register
- */
-DATA 4 0x020e05a8 0x00000030
-DATA 4 0x020e05b0 0x00000030
-DATA 4 0x020e0524 0x00000030
-DATA 4 0x020e051c 0x00000030
-
-DATA 4 0x020e0518 0x00000030
-DATA 4 0x020e050c 0x00000030
-DATA 4 0x020e05b8 0x00000030
-DATA 4 0x020e05c0 0x00000030
-
-DATA 4 0x020e05ac 0x00020030
-DATA 4 0x020e05b4 0x00020030
-DATA 4 0x020e0528 0x00020030
-DATA 4 0x020e0520 0x00020030
-
-DATA 4 0x020e0514 0x00020030
-DATA 4 0x020e0510 0x00020030
-DATA 4 0x020e05bc 0x00020030
-DATA 4 0x020e05c4 0x00020030
-
-DATA 4 0x020e056c 0x00020030
-DATA 4 0x020e0578 0x00020030
-DATA 4 0x020e0588 0x00020030
-DATA 4 0x020e0594 0x00020030
-
-DATA 4 0x020e057c 0x00020030
-DATA 4 0x020e0590 0x00003000
-DATA 4 0x020e0598 0x00003000
-DATA 4 0x020e058c 0x00000000
-
-DATA 4 0x020e059c 0x00003030
-DATA 4 0x020e05a0 0x00003030
-DATA 4 0x020e0784 0x00000030
-DATA 4 0x020e0788 0x00000030
-
-DATA 4 0x020e0794 0x00000030
-DATA 4 0x020e079c 0x00000030
-DATA 4 0x020e07a0 0x00000030
-DATA 4 0x020e07a4 0x00000030
-
-DATA 4 0x020e07a8 0x00000030
-DATA 4 0x020e0748 0x00000030
-DATA 4 0x020e074c 0x00000030
-DATA 4 0x020e0750 0x00020000
-
-DATA 4 0x020e0758 0x00000000
-DATA 4 0x020e0774 0x00020000
-DATA 4 0x020e078c 0x00000030
-DATA 4 0x020e0798 0x000C0000
-
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-
-DATA 4 0x021b481c 0x33333333
-DATA 4 0x021b4820 0x33333333
-DATA 4 0x021b4824 0x33333333
-DATA 4 0x021b4828 0x33333333
-
-DATA 4 0x021b0018 0x00081740
-
-DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b000c 0x555A7974
-DATA 4 0x021b0010 0xDB538F64
-DATA 4 0x021b0014 0x01FF00DB
-DATA 4 0x021b002c 0x000026D2
-
-DATA 4 0x021b0030 0x005A1023
-DATA 4 0x021b0008 0x09444040
-DATA 4 0x021b0004 0x00025576
-DATA 4 0x021b0040 0x00000027
-DATA 4 0x021b0000 0x831A0000
-
-DATA 4 0x021b001c 0x04088032
-DATA 4 0x021b001c 0x0408803A
-DATA 4 0x021b001c 0x00008033
-DATA 4 0x021b001c 0x0000803B
-DATA 4 0x021b001c 0x00428031
-DATA 4 0x021b001c 0x00428039
-DATA 4 0x021b001c 0x19308030
-DATA 4 0x021b001c 0x19308038
-
-DATA 4 0x021b001c 0x04008040
-DATA 4 0x021b001c 0x04008048
-DATA 4 0x021b0800 0xA1380003
-DATA 4 0x021b4800 0xA1380003
-DATA 4 0x021b0020 0x00005800
-DATA 4 0x021b0818 0x00022227
-DATA 4 0x021b4818 0x00022227
-
-DATA 4 0x021b083c 0x434B0350
-DATA 4 0x021b0840 0x034C0359
-DATA 4 0x021b483c 0x434B0350
-DATA 4 0x021b4840 0x03650348
-DATA 4 0x021b0848 0x4436383B
-DATA 4 0x021b4848 0x39393341
-DATA 4 0x021b0850 0x35373933
-DATA 4 0x021b4850 0x48254A36
-
-DATA 4 0x021b080c 0x001F001F
-DATA 4 0x021b0810 0x001F001F
-
-DATA 4 0x021b480c 0x00440044
-DATA 4 0x021b4810 0x00440044
-
-DATA 4 0x021b08b8 0x00000800
-DATA 4 0x021b48b8 0x00000800
-
-DATA 4 0x021b001c 0x00000000
-DATA 4 0x021b0404 0x00011006
-
-/* set the default clock gate to save power */
-DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC03
-DATA 4 0x020c4070 0x0FFFC000
-DATA 4 0x020c4074 0x3FF00000
-DATA 4 0x020c4078 0x00FFF300
-DATA 4 0x020c407c 0x0F0000C3
-DATA 4 0x020c4080 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4 0x020e0010 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4 0x020e0018 0x007F007F
-DATA 4 0x020e001c 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en  = 1	   --> CKO1 enabled
- * cko1_div = 111  --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4 0x020c4060 0x000000fb
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index f836ecb..e416042 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -10,12 +10,12 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
@@ -28,7 +28,6 @@
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 #include "../common/pfuze.h"
-#include <asm/arch/mx6-ddr.h>
 #include <usb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -57,6 +56,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define DISP0_PWR_EN	IMX_GPIO_NR(1, 21)
 
+#define KEY_VOL_UP	IMX_GPIO_NR(1, 4)
+
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -64,33 +65,33 @@ int dram_init(void)
 }
 
 static iomux_v3_cfg_t const uart1_pads[] = {
-	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 };
 
 static iomux_v3_cfg_t const enet_pads[] = {
-	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
 	/* AR8031 PHY Reset */
-	MX6_PAD_ENET_CRS_DV__GPIO1_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25	| MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
 static void setup_iomux_enet(void)
 {
-	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+	SETUP_IOMUX_PADS(enet_pads);
 
 	/* Reset AR8031 PHY */
 	gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
@@ -100,98 +101,98 @@ static void setup_iomux_enet(void)
 }
 
 static iomux_v3_cfg_t const usdhc2_pads[] = {
-	MX6_PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D4__SD2_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D5__SD2_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D6__SD2_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D7__SD2_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D2__GPIO2_IO02	| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02	| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
 };
 
 static iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
 };
 
 static iomux_v3_cfg_t const usdhc4_pads[] = {
-	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 };
 
 static iomux_v3_cfg_t const ecspi1_pads[] = {
-	MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
 static iomux_v3_cfg_t const rgb_pads[] = {
-	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
 static iomux_v3_cfg_t const bl_pads[] = {
-	MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
 static void enable_backlight(void)
 {
-	imx_iomux_v3_setup_multiple_pads(bl_pads, ARRAY_SIZE(bl_pads));
+	SETUP_IOMUX_PADS(bl_pads);
 	gpio_direction_output(DISP0_PWR_EN, 1);
 }
 
 static void enable_rgb(struct display_info_t const *dev)
 {
-	imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
+	SETUP_IOMUX_PADS(rgb_pads);
 	enable_backlight();
 }
 
@@ -200,43 +201,56 @@ static void enable_lvds(struct display_info_t const *dev)
 	enable_backlight();
 }
 
-static struct i2c_pads_info i2c_pad_info1 = {
+static struct i2c_pads_info mx6q_i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+		.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+		.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 	.scl = {
-		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
-		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+		.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+		.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 		.gp = IMX_GPIO_NR(4, 12)
 	},
 	.sda = {
-		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
-		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+		.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+		.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 		.gp = IMX_GPIO_NR(4, 13)
 	}
 };
 
 static void setup_spi(void)
 {
-	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+	SETUP_IOMUX_PADS(ecspi1_pads);
 }
 
 iomux_v3_cfg_t const pcie_pads[] = {
-	MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),	/* POWER */
-	MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),	/* RESET */
+	IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),	/* POWER */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),	/* RESET */
 };
 
 static void setup_pcie(void)
 {
-	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+	SETUP_IOMUX_PADS(pcie_pads);
 }
 
 iomux_v3_cfg_t const di0_pads[] = {
-	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,	/* DISP0_CLK */
-	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,		/* DISP0_HSYNC */
-	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,		/* DISP0_VSYNC */
+	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),	/* DISP0_CLK */
+	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),		/* DISP0_HSYNC */
+	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),		/* DISP0_VSYNC */
 };
 
 static void setup_iomux_uart(void)
 {
-	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+	SETUP_IOMUX_PADS(uart1_pads);
 }
 
 #ifdef CONFIG_FSL_ESDHC
@@ -290,20 +304,17 @@ int board_mmc_init(bd_t *bis)
 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 		switch (i) {
 		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			SETUP_IOMUX_PADS(usdhc2_pads);
 			gpio_direction_input(USDHC2_CD_GPIO);
 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 			break;
 		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			SETUP_IOMUX_PADS(usdhc3_pads);
 			gpio_direction_input(USDHC3_CD_GPIO);
 			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 			break;
 		case 2:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+			SETUP_IOMUX_PADS(usdhc4_pads);
 			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 			break;
 		default:
@@ -333,22 +344,19 @@ int board_mmc_init(bd_t *bis)
 
 	switch (reg & 0x3) {
 	case 0x1:
-		imx_iomux_v3_setup_multiple_pads(
-			usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+		SETUP_IOMUX_PADS(usdhc2_pads);
 		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 		break;
 	case 0x2:
-		imx_iomux_v3_setup_multiple_pads(
-			usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+		SETUP_IOMUX_PADS(usdhc3_pads);
 		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 		break;
 	case 0x3:
-		imx_iomux_v3_setup_multiple_pads(
-			usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+		SETUP_IOMUX_PADS(usdhc4_pads);
 		usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
@@ -360,6 +368,39 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	ar8031_phy_fixup(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
 #if defined(CONFIG_VIDEO_IPUV3)
 static void disable_lvds(struct display_info_t const *dev)
 {
@@ -449,7 +490,7 @@ static void setup_display(void)
 	int reg;
 
 	/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
-	imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
+	SETUP_IOMUX_PADS(di0_pads);
 
 	enable_ipu_clock();
 	imx_setup_hdmi();
@@ -520,18 +561,17 @@ int board_eth_init(bd_t *bis)
 #define UCTRL_PWR_POL		(1 << 9)
 
 static iomux_v3_cfg_t const usb_otg_pads[] = {
-	MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+	IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
 static iomux_v3_cfg_t const usb_hc1_pads[] = {
-	MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
 static void setup_usb(void)
 {
-	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
-					 ARRAY_SIZE(usb_otg_pads));
+	SETUP_IOMUX_PADS(usb_otg_pads);
 
 	/*
 	 * set daisy chain for otg_pin_id on 6q.
@@ -539,8 +579,7 @@ static void setup_usb(void)
 	 */
 	imx_iomux_set_gpr_register(1, 13, 1, 0);
 
-	imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
-					 ARRAY_SIZE(usb_hc1_pads));
+	SETUP_IOMUX_PADS(usb_hc1_pads);
 }
 
 int board_ehci_hcd_init(int port)
@@ -596,8 +635,10 @@ int board_init(void)
 #ifdef CONFIG_MXC_SPI
 	setup_spi();
 #endif
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-
+	if (is_mx6dq() || is_mx6dqp())
+		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
+	else
+		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
 #ifdef CONFIG_USB_EHCI_MX6
 	setup_usb();
 #endif
@@ -679,127 +720,19 @@ int checkboard(void)
 }
 
 #ifdef CONFIG_SPL_BUILD
+#include <asm/arch/mx6-ddr.h>
 #include <spl.h>
 #include <libfdt.h>
 
-const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
-	.dram_sdclk_0 =  0x00020030,
-	.dram_sdclk_1 =  0x00020030,
-	.dram_cas =  0x00020030,
-	.dram_ras =  0x00020030,
-	.dram_reset =  0x00020030,
-	.dram_sdcke0 =  0x00003000,
-	.dram_sdcke1 =  0x00003000,
-	.dram_sdba2 =  0x00000000,
-	.dram_sdodt0 =  0x00003030,
-	.dram_sdodt1 =  0x00003030,
-	.dram_sdqs0 =  0x00000030,
-	.dram_sdqs1 =  0x00000030,
-	.dram_sdqs2 =  0x00000030,
-	.dram_sdqs3 =  0x00000030,
-	.dram_sdqs4 =  0x00000030,
-	.dram_sdqs5 =  0x00000030,
-	.dram_sdqs6 =  0x00000030,
-	.dram_sdqs7 =  0x00000030,
-	.dram_dqm0 =  0x00020030,
-	.dram_dqm1 =  0x00020030,
-	.dram_dqm2 =  0x00020030,
-	.dram_dqm3 =  0x00020030,
-	.dram_dqm4 =  0x00020030,
-	.dram_dqm5 =  0x00020030,
-	.dram_dqm6 =  0x00020030,
-	.dram_dqm7 =  0x00020030,
-};
-
-const struct mx6dq_iomux_ddr_regs mx6dqp_ddr_ioregs = {
-	.dram_sdclk_0 =  0x00000030,
-	.dram_sdclk_1 =  0x00000030,
-	.dram_cas =  0x00000030,
-	.dram_ras =  0x00000030,
-	.dram_reset =  0x00000030,
-	.dram_sdcke0 =  0x00003000,
-	.dram_sdcke1 =  0x00003000,
-	.dram_sdba2 =  0x00000000,
-	.dram_sdodt0 =  0x00003030,
-	.dram_sdodt1 =  0x00003030,
-	.dram_sdqs0 =  0x00000030,
-	.dram_sdqs1 =  0x00000030,
-	.dram_sdqs2 =  0x00000030,
-	.dram_sdqs3 =  0x00000030,
-	.dram_sdqs4 =  0x00000030,
-	.dram_sdqs5 =  0x00000030,
-	.dram_sdqs6 =  0x00000030,
-	.dram_sdqs7 =  0x00000030,
-	.dram_dqm0 =  0x00000030,
-	.dram_dqm1 =  0x00000030,
-	.dram_dqm2 =  0x00000030,
-	.dram_dqm3 =  0x00000030,
-	.dram_dqm4 =  0x00000030,
-	.dram_dqm5 =  0x00000030,
-	.dram_dqm6 =  0x00000030,
-	.dram_dqm7 =  0x00000030,
-};
-
-const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
-	.grp_ddr_type =  0x000C0000,
-	.grp_ddrmode_ctl =  0x00020000,
-	.grp_ddrpke =  0x00000000,
-	.grp_addds =  0x00000030,
-	.grp_ctlds =  0x00000030,
-	.grp_ddrmode =  0x00020000,
-	.grp_b0ds =  0x00000030,
-	.grp_b1ds =  0x00000030,
-	.grp_b2ds =  0x00000030,
-	.grp_b3ds =  0x00000030,
-	.grp_b4ds =  0x00000030,
-	.grp_b5ds =  0x00000030,
-	.grp_b6ds =  0x00000030,
-	.grp_b7ds =  0x00000030,
-};
-
-const struct mx6_mmdc_calibration mx6_mmcd_calib = {
-	.p0_mpwldectrl0 =  0x001F001F,
-	.p0_mpwldectrl1 =  0x001F001F,
-	.p1_mpwldectrl0 =  0x00440044,
-	.p1_mpwldectrl1 =  0x00440044,
-	.p0_mpdgctrl0 =  0x434B0350,
-	.p0_mpdgctrl1 =  0x034C0359,
-	.p1_mpdgctrl0 =  0x434B0350,
-	.p1_mpdgctrl1 =  0x03650348,
-	.p0_mprddlctl =  0x4436383B,
-	.p1_mprddlctl =  0x39393341,
-	.p0_mpwrdlctl =  0x35373933,
-	.p1_mpwrdlctl =  0x48254A36,
-};
-
-const struct mx6_mmdc_calibration mx6dqp_mmcd_calib = {
-	.p0_mpwldectrl0 =  0x001B001E,
-	.p0_mpwldectrl1 =  0x002E0029,
-	.p1_mpwldectrl0 =  0x001B002A,
-	.p1_mpwldectrl1 =  0x0019002C,
-	.p0_mpdgctrl0 =  0x43240334,
-	.p0_mpdgctrl1 =  0x0324031A,
-	.p1_mpdgctrl0 =  0x43340344,
-	.p1_mpdgctrl1 =  0x03280276,
-	.p0_mprddlctl =  0x44383A3E,
-	.p1_mprddlctl =  0x3C3C3846,
-	.p0_mpwrdlctl =  0x2E303230,
-	.p1_mpwrdlctl =  0x38283E34,
-};
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	gpio_direction_input(KEY_VOL_UP);
 
-/* MT41K128M16JT-125 */
-static struct mx6_ddr3_cfg mem_ddr = {
-	.mem_speed = 1600,
-	.density = 2,
-	.width = 16,
-	.banks = 8,
-	.rowaddr = 14,
-	.coladdr = 10,
-	.pagesz = 2,
-	.trcd = 1375,
-	.trcmin = 4875,
-	.trasmin = 3500,
-};
+	/* Only enter in Falcon mode if KEY_VOL_UP is pressed */
+	return gpio_get_value(KEY_VOL_UP);
+}
+#endif
 
 static void ccgr_init(void)
 {
@@ -831,44 +764,297 @@ static void gpr_init(void)
 	}
 }
 
-/*
- * This section requires the differentiation between iMX6 Sabre boards, but
- * for now, it will configure only for the mx6q variant.
- */
-static void spl_dram_init(void)
+static int mx6q_dcd_table[] = {
+	0x020e0798, 0x000C0000,
+	0x020e0758, 0x00000000,
+	0x020e0588, 0x00000030,
+	0x020e0594, 0x00000030,
+	0x020e056c, 0x00000030,
+	0x020e0578, 0x00000030,
+	0x020e074c, 0x00000030,
+	0x020e057c, 0x00000030,
+	0x020e058c, 0x00000000,
+	0x020e059c, 0x00000030,
+	0x020e05a0, 0x00000030,
+	0x020e078c, 0x00000030,
+	0x020e0750, 0x00020000,
+	0x020e05a8, 0x00000030,
+	0x020e05b0, 0x00000030,
+	0x020e0524, 0x00000030,
+	0x020e051c, 0x00000030,
+	0x020e0518, 0x00000030,
+	0x020e050c, 0x00000030,
+	0x020e05b8, 0x00000030,
+	0x020e05c0, 0x00000030,
+	0x020e0774, 0x00020000,
+	0x020e0784, 0x00000030,
+	0x020e0788, 0x00000030,
+	0x020e0794, 0x00000030,
+	0x020e079c, 0x00000030,
+	0x020e07a0, 0x00000030,
+	0x020e07a4, 0x00000030,
+	0x020e07a8, 0x00000030,
+	0x020e0748, 0x00000030,
+	0x020e05ac, 0x00000030,
+	0x020e05b4, 0x00000030,
+	0x020e0528, 0x00000030,
+	0x020e0520, 0x00000030,
+	0x020e0514, 0x00000030,
+	0x020e0510, 0x00000030,
+	0x020e05bc, 0x00000030,
+	0x020e05c4, 0x00000030,
+	0x021b0800, 0xa1390003,
+	0x021b080c, 0x001F001F,
+	0x021b0810, 0x001F001F,
+	0x021b480c, 0x001F001F,
+	0x021b4810, 0x001F001F,
+	0x021b083c, 0x43270338,
+	0x021b0840, 0x03200314,
+	0x021b483c, 0x431A032F,
+	0x021b4840, 0x03200263,
+	0x021b0848, 0x4B434748,
+	0x021b4848, 0x4445404C,
+	0x021b0850, 0x38444542,
+	0x021b4850, 0x4935493A,
+	0x021b081c, 0x33333333,
+	0x021b0820, 0x33333333,
+	0x021b0824, 0x33333333,
+	0x021b0828, 0x33333333,
+	0x021b481c, 0x33333333,
+	0x021b4820, 0x33333333,
+	0x021b4824, 0x33333333,
+	0x021b4828, 0x33333333,
+	0x021b08b8, 0x00000800,
+	0x021b48b8, 0x00000800,
+	0x021b0004, 0x00020036,
+	0x021b0008, 0x09444040,
+	0x021b000c, 0x555A7975,
+	0x021b0010, 0xFF538F64,
+	0x021b0014, 0x01FF00DB,
+	0x021b0018, 0x00001740,
+	0x021b001c, 0x00008000,
+	0x021b002c, 0x000026d2,
+	0x021b0030, 0x005A1023,
+	0x021b0040, 0x00000027,
+	0x021b0000, 0x831A0000,
+	0x021b001c, 0x04088032,
+	0x021b001c, 0x00008033,
+	0x021b001c, 0x00048031,
+	0x021b001c, 0x09408030,
+	0x021b001c, 0x04008040,
+	0x021b0020, 0x00005800,
+	0x021b0818, 0x00011117,
+	0x021b4818, 0x00011117,
+	0x021b0004, 0x00025576,
+	0x021b0404, 0x00011006,
+	0x021b001c, 0x00000000,
+};
+
+static int mx6qp_dcd_table[] = {
+	0x020e0798, 0x000c0000,
+	0x020e0758, 0x00000000,
+	0x020e0588, 0x00000030,
+	0x020e0594, 0x00000030,
+	0x020e056c, 0x00000030,
+	0x020e0578, 0x00000030,
+	0x020e074c, 0x00000030,
+	0x020e057c, 0x00000030,
+	0x020e058c, 0x00000000,
+	0x020e059c, 0x00000030,
+	0x020e05a0, 0x00000030,
+	0x020e078c, 0x00000030,
+	0x020e0750, 0x00020000,
+	0x020e05a8, 0x00000030,
+	0x020e05b0, 0x00000030,
+	0x020e0524, 0x00000030,
+	0x020e051c, 0x00000030,
+	0x020e0518, 0x00000030,
+	0x020e050c, 0x00000030,
+	0x020e05b8, 0x00000030,
+	0x020e05c0, 0x00000030,
+	0x020e0774, 0x00020000,
+	0x020e0784, 0x00000030,
+	0x020e0788, 0x00000030,
+	0x020e0794, 0x00000030,
+	0x020e079c, 0x00000030,
+	0x020e07a0, 0x00000030,
+	0x020e07a4, 0x00000030,
+	0x020e07a8, 0x00000030,
+	0x020e0748, 0x00000030,
+	0x020e05ac, 0x00000030,
+	0x020e05b4, 0x00000030,
+	0x020e0528, 0x00000030,
+	0x020e0520, 0x00000030,
+	0x020e0514, 0x00000030,
+	0x020e0510, 0x00000030,
+	0x020e05bc, 0x00000030,
+	0x020e05c4, 0x00000030,
+	0x021b0800, 0xa1390003,
+	0x021b080c, 0x001b001e,
+	0x021b0810, 0x002e0029,
+	0x021b480c, 0x001b002a,
+	0x021b4810, 0x0019002c,
+	0x021b083c, 0x43240334,
+	0x021b0840, 0x0324031a,
+	0x021b483c, 0x43340344,
+	0x021b4840, 0x03280276,
+	0x021b0848, 0x44383A3E,
+	0x021b4848, 0x3C3C3846,
+	0x021b0850, 0x2e303230,
+	0x021b4850, 0x38283E34,
+	0x021b081c, 0x33333333,
+	0x021b0820, 0x33333333,
+	0x021b0824, 0x33333333,
+	0x021b0828, 0x33333333,
+	0x021b481c, 0x33333333,
+	0x021b4820, 0x33333333,
+	0x021b4824, 0x33333333,
+	0x021b4828, 0x33333333,
+	0x021b08c0, 0x24912249,
+	0x021b48c0, 0x24914289,
+	0x021b08b8, 0x00000800,
+	0x021b48b8, 0x00000800,
+	0x021b0004, 0x00020036,
+	0x021b0008, 0x24444040,
+	0x021b000c, 0x555A7955,
+	0x021b0010, 0xFF320F64,
+	0x021b0014, 0x01ff00db,
+	0x021b0018, 0x00001740,
+	0x021b001c, 0x00008000,
+	0x021b002c, 0x000026d2,
+	0x021b0030, 0x005A1023,
+	0x021b0040, 0x00000027,
+	0x021b0400, 0x14420000,
+	0x021b0000, 0x831A0000,
+	0x021b0890, 0x00400C58,
+	0x00bb0008, 0x00000000,
+	0x00bb000c, 0x2891E41A,
+	0x00bb0038, 0x00000564,
+	0x00bb0014, 0x00000040,
+	0x00bb0028, 0x00000020,
+	0x00bb002c, 0x00000020,
+	0x021b001c, 0x04088032,
+	0x021b001c, 0x00008033,
+	0x021b001c, 0x00048031,
+	0x021b001c, 0x09408030,
+	0x021b001c, 0x04008040,
+	0x021b0020, 0x00005800,
+	0x021b0818, 0x00011117,
+	0x021b4818, 0x00011117,
+	0x021b0004, 0x00025576,
+	0x021b0404, 0x00011006,
+	0x021b001c, 0x00000000,
+};
+
+static int mx6dl_dcd_table[] = {
+	0x020e0774, 0x000C0000,
+	0x020e0754, 0x00000000,
+	0x020e04ac, 0x00000030,
+	0x020e04b0, 0x00000030,
+	0x020e0464, 0x00000030,
+	0x020e0490, 0x00000030,
+	0x020e074c, 0x00000030,
+	0x020e0494, 0x00000030,
+	0x020e04a0, 0x00000000,
+	0x020e04b4, 0x00000030,
+	0x020e04b8, 0x00000030,
+	0x020e076c, 0x00000030,
+	0x020e0750, 0x00020000,
+	0x020e04bc, 0x00000030,
+	0x020e04c0, 0x00000030,
+	0x020e04c4, 0x00000030,
+	0x020e04c8, 0x00000030,
+	0x020e04cc, 0x00000030,
+	0x020e04d0, 0x00000030,
+	0x020e04d4, 0x00000030,
+	0x020e04d8, 0x00000030,
+	0x020e0760, 0x00020000,
+	0x020e0764, 0x00000030,
+	0x020e0770, 0x00000030,
+	0x020e0778, 0x00000030,
+	0x020e077c, 0x00000030,
+	0x020e0780, 0x00000030,
+	0x020e0784, 0x00000030,
+	0x020e078c, 0x00000030,
+	0x020e0748, 0x00000030,
+	0x020e0470, 0x00000030,
+	0x020e0474, 0x00000030,
+	0x020e0478, 0x00000030,
+	0x020e047c, 0x00000030,
+	0x020e0480, 0x00000030,
+	0x020e0484, 0x00000030,
+	0x020e0488, 0x00000030,
+	0x020e048c, 0x00000030,
+	0x021b0800, 0xa1390003,
+	0x021b080c, 0x001F001F,
+	0x021b0810, 0x001F001F,
+	0x021b480c, 0x001F001F,
+	0x021b4810, 0x001F001F,
+	0x021b083c, 0x4220021F,
+	0x021b0840, 0x0207017E,
+	0x021b483c, 0x4201020C,
+	0x021b4840, 0x01660172,
+	0x021b0848, 0x4A4D4E4D,
+	0x021b4848, 0x4A4F5049,
+	0x021b0850, 0x3F3C3D31,
+	0x021b4850, 0x3238372B,
+	0x021b081c, 0x33333333,
+	0x021b0820, 0x33333333,
+	0x021b0824, 0x33333333,
+	0x021b0828, 0x33333333,
+	0x021b481c, 0x33333333,
+	0x021b4820, 0x33333333,
+	0x021b4824, 0x33333333,
+	0x021b4828, 0x33333333,
+	0x021b08b8, 0x00000800,
+	0x021b48b8, 0x00000800,
+	0x021b0004, 0x0002002D,
+	0x021b0008, 0x00333030,
+	0x021b000c, 0x3F435313,
+	0x021b0010, 0xB66E8B63,
+	0x021b0014, 0x01FF00DB,
+	0x021b0018, 0x00001740,
+	0x021b001c, 0x00008000,
+	0x021b002c, 0x000026d2,
+	0x021b0030, 0x00431023,
+	0x021b0040, 0x00000027,
+	0x021b0000, 0x831A0000,
+	0x021b001c, 0x04008032,
+	0x021b001c, 0x00008033,
+	0x021b001c, 0x00048031,
+	0x021b001c, 0x05208030,
+	0x021b001c, 0x04008040,
+	0x021b0020, 0x00005800,
+	0x021b0818, 0x00011117,
+	0x021b4818, 0x00011117,
+	0x021b0004, 0x0002556D,
+	0x021b0404, 0x00011006,
+	0x021b001c, 0x00000000,
+};
+
+static void ddr_init(int *table, int size)
 {
-	struct mx6_ddr_sysinfo sysinfo = {
-		/* width of data bus:0=16,1=32,2=64 */
-		.dsize = 2,
-		/* config for full 4GB range so that get_mem_size() works */
-		.cs_density = 32, /* 32Gb per CS */
-		/* single chip select */
-		.ncs = 1,
-		.cs1_mirror = 0,
-		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
-		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
-		.walat = 1,	/* Write additional latency */
-		.ralat = 5,	/* Read additional latency */
-		.mif3_mode = 3,	/* Command prediction working mode */
-		.bi_on = 1,	/* Bank interleaving enabled */
-		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
-		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
-		.ddr_type = DDR_TYPE_DDR3,
-		.refsel = 1,	/* Refresh cycles at 32KHz */
-		.refr = 7,	/* 8 refresh commands per refresh cycle */
-	};
+	int i;
 
-	if (is_mx6dqp()) {
-		mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs);
-		mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr);
-	} else {
-		mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
-		mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
-	}
+	for (i = 0; i < size / 2 ; i++)
+		writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+	if (is_mx6dq())
+		ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
+	else if (is_mx6dqp())
+		ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
+	else if (is_mx6sdl())
+		ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
 }
 
 void board_init_f(ulong dummy)
 {
+	/* DDR initialization */
+	spl_dram_init();
+
 	/* setup AIPS and disable watchdog */
 	arch_cpu_init();
 
@@ -884,9 +1070,6 @@ void board_init_f(ulong dummy)
 	/* UART clocks enabled and gd valid - init serial console */
 	preloader_console_init();
 
-	/* DDR initialization */
-	spl_dram_init();
-
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg
index c77bbde..024de9c 100644
--- a/board/freescale/mx6slevk/imximage.cfg
+++ b/board/freescale/mx6slevk/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 96c0e8c..8afd5da 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -14,9 +14,9 @@
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/spi.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
@@ -47,11 +47,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
 		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
 
-#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
-		      PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
-		      PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
-		      PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
 			PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
 			PAD_CTL_DSE_80ohm | PAD_CTL_HYS |	\
@@ -71,6 +66,7 @@ static iomux_v3_cfg_t const uart1_pads[] = {
 	MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
+#ifdef CONFIG_SPL_BUILD
 static iomux_v3_cfg_t const usdhc1_pads[] = {
 	/* 8 bit SD */
 	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -111,6 +107,7 @@ static iomux_v3_cfg_t const usdhc3_pads[] = {
 	/*CD pin*/
 	MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
+#endif
 
 static iomux_v3_cfg_t const fec_pads[] = {
 	MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
@@ -155,157 +152,55 @@ static void setup_iomux_fec(void)
 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 
 	/* Power up LAN8720 PHY */
+	gpio_request(ETH_PHY_POWER, "eth_pwr");
 	gpio_direction_output(ETH_PHY_POWER , 1);
 	udelay(15000);
 }
 
-#define USDHC1_CD_GPIO	IMX_GPIO_NR(4, 7)
-#define USDHC2_CD_GPIO	IMX_GPIO_NR(5, 0)
-#define USDHC3_CD_GPIO	IMX_GPIO_NR(3, 22)
-
-static struct fsl_esdhc_cfg usdhc_cfg[3] = {
-	{USDHC1_BASE_ADDR},
-	{USDHC2_BASE_ADDR, 0, 4},
-	{USDHC3_BASE_ADDR, 0, 4},
-};
-
 int board_mmc_get_env_dev(int devno)
 {
 	return devno;
 }
 
-int board_mmc_getcd(struct mmc *mmc)
+#ifdef CONFIG_DM_PMIC_PFUZE100
+int power_init_board(void)
 {
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = 0;
+	struct udevice *dev;
+	int ret;
+	u32 dev_id, rev_id, i;
+	u32 switch_num = 6;
+	u32 offset = PFUZE100_SW1CMODE;
 
-	switch (cfg->esdhc_base) {
-	case USDHC1_BASE_ADDR:
-		ret = !gpio_get_value(USDHC1_CD_GPIO);
-		break;
-	case USDHC2_BASE_ADDR:
-		ret = !gpio_get_value(USDHC2_CD_GPIO);
-		break;
-	case USDHC3_BASE_ADDR:
-		ret = !gpio_get_value(USDHC3_CD_GPIO);
-		break;
-	}
+	ret = pmic_get("pfuze100", &dev);
+	if (ret == -ENODEV)
+		return 0;
 
-	return ret;
-}
+	if (ret != 0)
+		return ret;
 
-int board_mmc_init(bd_t *bis)
-{
-#ifndef CONFIG_SPL_BUILD
-	int i, ret;
-
-	/*
-	 * According to the board_mmc_init() the following map is done:
-	 * (U-Boot device node)    (Physical Port)
-	 * mmc0                    USDHC1
-	 * mmc1                    USDHC2
-	 * mmc2                    USDHC3
-	 */
-	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-		switch (i) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
-			gpio_direction_input(USDHC1_CD_GPIO);
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-			gpio_direction_input(USDHC2_CD_GPIO);
-			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-			break;
-		case 2:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-			gpio_direction_input(USDHC3_CD_GPIO);
-			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers"
-				"(%d) than supported by the board\n", i + 1);
-			return -EINVAL;
-		}
-
-		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-		if (ret) {
-			printf("Warning: failed to initialize "
-				"mmc dev %d\n", i);
-			return ret;
-		}
-	}
+	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
 
-	return 0;
-#else
-	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
-	u32 val;
-	u32 port;
+	/* set SW1AB staby volatage 0.975V */
+	pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
 
-	val = readl(&src_regs->sbmr1);
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
 
-	/* Boot from USDHC */
-	port = (val >> 11) & 0x3;
-	switch (port) {
-	case 0:
-		imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
-						 ARRAY_SIZE(usdhc1_pads));
-		gpio_direction_input(USDHC1_CD_GPIO);
-		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
-		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-		break;
-	case 1:
-		imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
-						 ARRAY_SIZE(usdhc2_pads));
-		gpio_direction_input(USDHC2_CD_GPIO);
-		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
-		usdhc_cfg[0].max_bus_width = 4;
-		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-		break;
-	case 2:
-		imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
-						 ARRAY_SIZE(usdhc3_pads));
-		gpio_direction_input(USDHC3_CD_GPIO);
-		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
-		usdhc_cfg[0].max_bus_width = 4;
-		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-		break;
-	}
-
-	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
-	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
-}
+	/* set SW1C staby volatage 0.975V */
+	pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
 
-#ifdef CONFIG_SYS_I2C_MXC
-#define PC	MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C1 for PMIC */
-struct i2c_pads_info i2c_pad_info1 = {
-	.sda = {
-		.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
-		.gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
-		.gp = IMX_GPIO_NR(3, 13),
-	},
-	.scl = {
-		.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
-		.gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
-		.gp = IMX_GPIO_NR(3, 12),
-	},
-};
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
 
-int power_init_board(void)
-{
-	struct pmic *p;
+	/* Init mode to APS_PFM */
+	pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
 
-	p = pfuze_common_init(I2C_PMIC);
-	if (!p)
-		return -ENODEV;
+	for (i = 0; i < switch_num - 1; i++)
+		pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
 
-	return pfuze_mode_init(p, APS_PFM);
+	return 0;
 }
 #endif
 
@@ -374,9 +269,7 @@ int board_ehci_hcd_init(int port)
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
-#ifdef CONFIG_MXC_SPI
-	setup_spi();
-#endif
+
 	return 0;
 }
 
@@ -385,8 +278,9 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-#ifdef CONFIG_SYS_I2C_MXC
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#ifdef CONFIG_MXC_SPI
+	gpio_request(IMX_GPIO_NR(4, 11), "spi_cs");
+	setup_spi();
 #endif
 
 #ifdef	CONFIG_FEC_MXC
@@ -411,6 +305,76 @@ int checkboard(void)
 #include <spl.h>
 #include <libfdt.h>
 
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(4, 7)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(5, 0)
+#define USDHC3_CD_GPIO	IMX_GPIO_NR(3, 22)
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+	{USDHC1_BASE_ADDR},
+	{USDHC2_BASE_ADDR, 0, 4},
+	{USDHC3_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+	u32 val;
+	u32 port;
+
+	val = readl(&src_regs->sbmr1);
+
+	/* Boot from USDHC */
+	port = (val >> 11) & 0x3;
+	switch (port) {
+	case 0:
+		imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+						 ARRAY_SIZE(usdhc1_pads));
+		gpio_direction_input(USDHC1_CD_GPIO);
+		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+		break;
+	case 1:
+		imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+						 ARRAY_SIZE(usdhc2_pads));
+		gpio_direction_input(USDHC2_CD_GPIO);
+		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+		usdhc_cfg[0].max_bus_width = 4;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+		break;
+	case 2:
+		imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
+						 ARRAY_SIZE(usdhc3_pads));
+		gpio_direction_input(USDHC3_CD_GPIO);
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].max_bus_width = 4;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		break;
+	}
+
+	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
 const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
 	.dram_sdqs0 = 0x00003030,
 	.dram_sdqs1 = 0x00003030,
diff --git a/board/freescale/mx6sllevk/Kconfig b/board/freescale/mx6sllevk/Kconfig
new file mode 100644
index 0000000..4ba9bbf
--- /dev/null
+++ b/board/freescale/mx6sllevk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6SLLEVK
+
+config SYS_BOARD
+	default "mx6sllevk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6sllevk"
+
+endif
diff --git a/board/freescale/mx6sllevk/MAINTAINERS b/board/freescale/mx6sllevk/MAINTAINERS
new file mode 100644
index 0000000..b82273c
--- /dev/null
+++ b/board/freescale/mx6sllevk/MAINTAINERS
@@ -0,0 +1,7 @@
+MX6SLLEVK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/mx6sllevk/
+F:	include/configs/mx6sllevk.h
+F:	configs/mx6sllevk_defconfig
+F:	configs/mx6sllevk_plugin_defconfig
diff --git a/board/freescale/mx6sllevk/Makefile b/board/freescale/mx6sllevk/Makefile
new file mode 100644
index 0000000..667fcb0
--- /dev/null
+++ b/board/freescale/mx6sllevk/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx6sllevk.o
diff --git a/board/freescale/mx6sllevk/imximage.cfg b/board/freescale/mx6sllevk/imximage.cfg
new file mode 100644
index 0000000..7d8b323
--- /dev/null
+++ b/board/freescale/mx6sllevk/imximage.cfg
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6sllevk/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E0550 0x00080000
+DATA 4 0x020E0534 0x00000000
+DATA 4 0x020E02AC 0x00000030
+DATA 4 0x020E0548 0x00000030
+DATA 4 0x020E052C 0x00000030
+DATA 4 0x020E0530 0x00020000
+DATA 4 0x020E02B0 0x00003030
+DATA 4 0x020E02B4 0x00003030
+DATA 4 0x020E02B8 0x00003030
+DATA 4 0x020E02BC 0x00003030
+DATA 4 0x020E0540 0x00020000
+DATA 4 0x020E0544 0x00000030
+DATA 4 0x020E054C 0x00000030
+DATA 4 0x020E0554 0x00000030
+DATA 4 0x020E0558 0x00000030
+DATA 4 0x020E0294 0x00000030
+DATA 4 0x020E0298 0x00000030
+DATA 4 0x020E029C 0x00000030
+DATA 4 0x020E02A0 0x00000030
+DATA 4 0x020E02C0 0x00082030
+
+DATA 4 0x021B001C 0x00008000
+
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B085c 0x084700C7
+DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B0848 0x3F393B3C
+DATA 4 0x021B0850 0x262C3826
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B0824 0x33333333
+DATA 4 0x021B0828 0x33333333
+
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B0834 0xf3333333
+DATA 4 0x021B0838 0xf3333333
+DATA 4 0x021B08C0 0x24922492
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B000C 0x53574333
+DATA 4 0x021B0010 0x00100B22
+DATA 4 0x021B0038 0x00170778
+DATA 4 0x021B0014 0x00C700DB
+DATA 4 0x021B0018 0x00201718
+DATA 4 0x021B002C 0x0F9F26D2
+DATA 4 0x021B0030 0x009F0E10
+DATA 4 0x021B0040 0x0000005F
+DATA 4 0x021B0000 0xC4190000
+
+DATA 4 0x021B083C 0x20000000
+
+DATA 4 0x021B001C 0x00008050
+DATA 4 0x021B001C 0x00008058
+DATA 4 0x021B001C 0x003F8030
+DATA 4 0x021B001C 0x003F8038
+DATA 4 0x021B001C 0xFF0A8030
+DATA 4 0x021B001C 0xFF0A8038
+DATA 4 0x021B001C 0x04028030
+DATA 4 0x021B001C 0x04028038
+DATA 4 0x021B001C 0x83018030
+DATA 4 0x021B001C 0x83018038
+DATA 4 0x021B001C 0x01038030
+DATA 4 0x021B001C 0x01038038
+
+DATA 4 0x021B0020 0x00001800
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+#endif
diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c
new file mode 100644
index 0000000..33aada1
--- /dev/null
+++ b/board/freescale/mx6sllevk/mx6sllevk.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/io.h>
+#include <common.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_DM_PMIC_PFUZE100
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+	u32 dev_id, rev_id, i;
+	u32 switch_num = 6;
+	u32 offset = PFUZE100_SW1CMODE;
+
+	ret = pmic_get("pfuze100", &dev);
+	if (ret == -ENODEV)
+		return 0;
+
+	if (ret != 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+
+	/* Init mode to APS_PFM */
+	pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
+
+	for (i = 0; i < switch_num - 1; i++)
+		pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
+
+	/* set SW1AB staby volatage 0.975V */
+	pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
+
+	/* set SW1C staby volatage 0.975V */
+	pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
+
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
+
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: MX6SLL EVK\n");
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int mmc_map_to_kernel_blk(int devno)
+{
+	return devno;
+}
diff --git a/board/freescale/mx6sllevk/plugin.S b/board/freescale/mx6sllevk/plugin.S
new file mode 100644
index 0000000..f9ef35a
--- /dev/null
+++ b/board/freescale/mx6sllevk/plugin.S
@@ -0,0 +1,155 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6sll_evk_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00080000
+	str r1, [r0, #0x550]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x534]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x2AC]
+	str r1, [r0, #0x548]
+	str r1, [r0, #0x52C]
+	ldr r1, =0x00020000
+	str r1, [r0, #0x530]
+	ldr r1, =0x00003030
+	str r1, [r0, #0x2B0]
+	str r1, [r0, #0x2B4]
+	str r1, [r0, #0x2B8]
+	str r1, [r0, #0x2BC]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x540]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x544]
+	str r1, [r0, #0x54C]
+	str r1, [r0, #0x554]
+	str r1, [r0, #0x558]
+	str r1, [r0, #0x294]
+	str r1, [r0, #0x298]
+	str r1, [r0, #0x29C]
+	str r1, [r0, #0x2A0]
+
+	ldr r1, =0x00082030
+	str r1, [r0, #0x2C0]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1C]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x084700C7
+	str r1, [r0, #0x85C]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+
+	ldr r1, =0x3F393B3C
+	str r1, [r0, #0x848]
+	ldr r1, =0x262C3826
+	str r1, [r0, #0x850]
+
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81C]
+	str r1, [r0, #0x820]
+	str r1, [r0, #0x824]
+	str r1, [r0, #0x828]
+
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x82C]
+	str r1, [r0, #0x830]
+	str r1, [r0, #0x834]
+	str r1, [r0, #0x838]
+
+	ldr r1, =0x24922492
+	str r1, [r0, #0x8C0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8B8]
+
+	ldr r1, =0x00020052
+	str r1, [r0, #0x004]
+	ldr r1, =0x53574333
+	str r1, [r0, #0x00C]
+	ldr r1, =0x00100B22
+	str r1, [r0, #0x010]
+	ldr r1, =0x00170778
+	str r1, [r0, #0x038]
+	ldr r1, =0x00C700DB
+	str r1, [r0, #0x014]
+	ldr r1, =0x00201718
+	str r1, [r0, #0x018]
+	ldr r1, =0x0F9F26D2
+	str r1, [r0, #0x02C]
+	ldr r1, =0x009F0E10
+	str r1, [r0, #0x030]
+	ldr r1, =0x0000005F
+	str r1, [r0, #0x040]
+	ldr r1, =0xC4190000
+	str r1, [r0, #0x000]
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83C]
+
+	ldr r1, =0x00008050
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00008058
+	str r1, [r0, #0x01C]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x003F8038
+	str r1, [r0, #0x01C]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0xFF0A8038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04028038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x83018030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x83018038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x01038038
+	str r1, [r0, #0x01C]
+
+	ldr r1, =0x00001800
+	str r1, [r0, #0x020]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00020052
+	str r1, [r0, #0x004]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01C]
+.endm
+
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x068]
+	str r1, [r0, #0x06c]
+	str r1, [r0, #0x070]
+	str r1, [r0, #0x074]
+	str r1, [r0, #0x078]
+	str r1, [r0, #0x07c]
+	str r1, [r0, #0x080]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+	imx6sll_evk_ddr_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
index 44e6a7d..83473d8 100644
--- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
+++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
@@ -13,15 +13,12 @@
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
 #include <asm/io.h>
-#include <asm/imx-common/mxc_i2c.h>
 #include <linux/sizes.h>
 #include <common.h>
 #include <fsl_esdhc.h>
-#include <mmc.h>
-#include <i2c.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <power/pmic.h>
@@ -37,15 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
-	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
-	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
-	PAD_CTL_ODE)
-
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
 	PAD_CTL_SPEED_HIGH   |                                   \
 	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
@@ -56,54 +44,11 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
 	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
 
-#define I2C_PMIC	1
-
 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
 			PAD_CTL_SRE_FAST)
 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
 
-/*Define for building port exp gpio, pin starts from 0*/
-#define PORTEXP_IO_NR(chip, pin) \
-	((chip << 5) + pin)
-
-/*Get the chip addr from a ioexp gpio*/
-#define PORTEXP_IO_TO_CHIP(gpio_nr) \
-	(gpio_nr >> 5)
-
-/*Get the pin number from a ioexp gpio*/
-#define PORTEXP_IO_TO_PIN(gpio_nr) \
-	(gpio_nr & 0x1f)
-
-#define CPU_PER_RST_B	PORTEXP_IO_NR(0x30, 4)
-#define STEER_ENET		PORTEXP_IO_NR(0x32, 2)
-
-static int port_exp_direction_output(unsigned gpio, int value)
-{
-	int ret;
-
-	i2c_set_bus_num(2);
-	ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
-	if (ret)
-		return ret;
-
-	ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
-		(1 << PORTEXP_IO_TO_PIN(gpio)),
-		(PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
-
-	if (ret)
-		return ret;
-
-	ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
-		(1 << PORTEXP_IO_TO_PIN(gpio)),
-		(value << PORTEXP_IO_TO_PIN(gpio)));
-
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -116,41 +61,6 @@ static iomux_v3_cfg_t const uart1_pads[] = {
 	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-static iomux_v3_cfg_t const usdhc3_pads[] = {
-	MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
-	/* CD pin */
-	MX6_PAD_USB_H_DATA__GPIO7_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
-
-	/* RST_B, used for power reset cycle */
-	MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
-	MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
-	/* CD pin */
-	MX6_PAD_USB_H_STROBE__GPIO7_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
 static iomux_v3_cfg_t const fec2_pads[] = {
 	MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
@@ -217,42 +127,43 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }
 
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C2 for PMIC */
-struct i2c_pads_info i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,
-		.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
-		.gp = IMX_GPIO_NR(1, 2),
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,
-		.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
-		.gp = IMX_GPIO_NR(1, 3),
-	},
-};
-
-/* I2C3 for IO Expander */
-struct i2c_pads_info i2c_pad_info3 = {
-	.scl = {
-		.i2c_mode = MX6_PAD_KEY_COL4__I2C3_SCL | PC,
-		.gpio_mode = MX6_PAD_KEY_COL4__GPIO2_IO_14 | PC,
-		.gp = IMX_GPIO_NR(2, 14),
-	},
-	.sda = {
-		.i2c_mode = MX6_PAD_KEY_ROW4__I2C3_SDA | PC,
-		.gpio_mode = MX6_PAD_KEY_ROW4__GPIO2_IO_19 | PC,
-		.gp = IMX_GPIO_NR(2, 19),
-	},
-};
-
 int power_init_board(void)
 {
-	struct pmic *p;
+	struct udevice *dev;
+	int ret;
+	u32 dev_id, rev_id, i;
+	u32 switch_num = 6;
+	u32 offset = PFUZE100_SW1CMODE;
+
+	ret = pmic_get("pfuze100", &dev);
+	if (ret == -ENODEV)
+		return 0;
+
+	if (ret != 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
 
-	p = pfuze_common_init(I2C_PMIC);
-	if (!p)
-		return -ENODEV;
+
+	/* Init mode to APS_PFM */
+	pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
+
+	for (i = 0; i < switch_num - 1; i++)
+		pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
+
+	/* set SW1AB staby volatage 0.975V */
+	pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
+
+	/* set SW1C staby volatage 1.10V */
+	pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20);
+
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
 
 	return 0;
 }
@@ -307,78 +218,6 @@ int board_early_init_f(void)
 	return 0;
 }
 
-static struct fsl_esdhc_cfg usdhc_cfg[3] = {
-	{USDHC3_BASE_ADDR},
-	{USDHC4_BASE_ADDR},
-};
-
-#define USDHC3_CD_GPIO	IMX_GPIO_NR(7, 10)
-#define USDHC3_RST_GPIO	IMX_GPIO_NR(2, 11)
-#define USDHC4_CD_GPIO	IMX_GPIO_NR(7, 11)
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = 0;
-
-	switch (cfg->esdhc_base) {
-	case USDHC3_BASE_ADDR:
-		ret = !gpio_get_value(USDHC3_CD_GPIO);
-		break;
-	case USDHC4_BASE_ADDR:
-		ret = !gpio_get_value(USDHC4_CD_GPIO);
-		break;
-	}
-
-	return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	int i, ret;
-
-	/*
-	 * According to the board_mmc_init() the following map is done:
-	 * (U-Boot device node)    (Physical Port)
-	 * mmc0                    USDHC3
-	 * mmc1                    USDHC4
-	 */
-	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-		switch (i) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-			gpio_direction_input(USDHC3_CD_GPIO);
-
-			/* This starts a power cycle for UHS-I. Need to set steer to B0 to A*/
-			gpio_direction_output(USDHC3_RST_GPIO, 0);
-			udelay(1000); /* need 1ms at least */
-			gpio_direction_output(USDHC3_RST_GPIO, 1);
-
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
-			gpio_direction_input(USDHC4_CD_GPIO);
-			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers"
-				"(%d) than supported by the board\n", i + 1);
-			return -EINVAL;
-			}
-
-			ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-			if (ret) {
-				printf("Warning: failed to initialize mmc dev %d\n", i);
-				return ret;
-			}
-	}
-
-	return 0;
-}
-
 #ifdef CONFIG_FSL_QSPI
 
 #define QSPI_PAD_CTRL1	\
@@ -450,21 +289,36 @@ static void setup_gpmi_nand(void)
 
 int board_init(void)
 {
+	struct gpio_desc desc;
+	int ret;
+
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-#ifdef CONFIG_SYS_I2C_MXC
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
-#endif
+	ret = dm_gpio_lookup_name("gpio@30_4", &desc);
+	if (ret)
+		return ret;
 
+	ret = dm_gpio_request(&desc, "cpu_per_rst_b");
+	if (ret)
+		return ret;
 	/* Reset CPU_PER_RST_B signal for enet phy and PCIE */
-	port_exp_direction_output(CPU_PER_RST_B, 0);
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
 	udelay(500);
-	port_exp_direction_output(CPU_PER_RST_B, 1);
+	dm_gpio_set_value(&desc, 1);
+
+	ret = dm_gpio_lookup_name("gpio@32_2", &desc);
+	if (ret)
+		return ret;
 
+	ret = dm_gpio_request(&desc, "steer_enet");
+	if (ret)
+		return ret;
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+	udelay(500);
 	/* Set steering signal to L for selecting B0 */
-	port_exp_direction_output(STEER_ENET, 0);
+	dm_gpio_set_value(&desc, 0);
 
 #ifdef CONFIG_USB_EHCI_MX6
 	setup_usb();
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 965e511..2aeef61 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -13,9 +13,9 @@
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
 #include <asm/io.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
 #include <linux/sizes.h>
 #include <common.h>
 #include <fsl_esdhc.h>
@@ -504,7 +504,7 @@ static iomux_v3_cfg_t const lcd_pads[] = {
 
 static int setup_lcd(void)
 {
-	enable_lcdif_clock(LCDIF1_BASE_ADDR);
+	enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
 
 	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 399bad2..a30c379 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -12,9 +12,9 @@
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/io.h>
 #include <common.h>
 #include <fsl_esdhc.h>
@@ -225,6 +225,7 @@ static iomux_v3_cfg_t const uart1_pads[] = {
 	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
+#ifndef CONFIG_SPL_BUILD
 static iomux_v3_cfg_t const usdhc1_pads[] = {
 	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -240,6 +241,7 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
 	/* RST_B */
 	MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
+#endif
 
 /*
  * mx6ul_14x14_evk board default supports sd card. If want to use
@@ -600,7 +602,7 @@ static iomux_v3_cfg_t const lcd_pads[] = {
 
 static int setup_lcd(void)
 {
-	enable_lcdif_clock(LCDIF1_BASE_ADDR);
+	enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
 
 	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 
diff --git a/board/freescale/mx6ullevk/Kconfig b/board/freescale/mx6ullevk/Kconfig
new file mode 100644
index 0000000..7eec497
--- /dev/null
+++ b/board/freescale/mx6ullevk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6ULL_14X14_EVK
+
+config SYS_BOARD
+	default "mx6ullevk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6ullevk"
+
+endif
diff --git a/board/freescale/mx6ullevk/MAINTAINERS b/board/freescale/mx6ullevk/MAINTAINERS
new file mode 100644
index 0000000..73031cd
--- /dev/null
+++ b/board/freescale/mx6ullevk/MAINTAINERS
@@ -0,0 +1,7 @@
+MX6ULLEVK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/mx6ullevk/
+F:	include/configs/mx6ullevk.h
+F:	configs/mx6ull_14x14_evk_defconfig
+F:	configs/mx6ull_14x14_evk_plugin_defconfig
diff --git a/board/freescale/mx6ullevk/Makefile b/board/freescale/mx6ullevk/Makefile
new file mode 100644
index 0000000..c64fba4
--- /dev/null
+++ b/board/freescale/mx6ullevk/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx6ullevk.o
diff --git a/board/freescale/mx6ullevk/README b/board/freescale/mx6ullevk/README
new file mode 100644
index 0000000..d5c8770
--- /dev/null
+++ b/board/freescale/mx6ullevk/README
@@ -0,0 +1,36 @@
+How to use U-Boot on Freescale MX6ULL 14x14 EVK
+----------------------------------------------
+
+- First make sure you have installed the dtc package (device tree compiler):
+
+$ sudo apt-get install device-tree-compiler
+
+- Build U-Boot for MX6ULL 14x14 EVK:
+
+$ make mrproper
+$ make mx6ull_14x14_evk_defconfig
+$ make
+
+This generates the u-boot-dtb.imx image in the current directory.
+
+- Flash the u-boot-dtb.imx image into the micro SD card:
+
+$ sudo dd if=u-boot-dtb.imx of=/dev/sdb bs=1K seek=1 && sync
+
+- Jumper settings:
+
+SW601: 0 0 1 0
+Sw602: 1 0
+
+Where 0 means bottom position and 1 means top position (from the switch label
+numbers reference).
+
+Connect the USB cable between the EVK and the PC for the console.
+(The USB console connector is the one close the push buttons)
+
+Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
+
+The link for the board: http://www.nxp.com/products/microcontrollers-and- \
+processors/arm-processors/i.mx-applications-processors/i.mx-6-processors/ \
+i.mx6qp/evaluation-kit-for-the-i.mx-6ull-applications-processor:MCIMX6ULL-EVK
diff --git a/board/freescale/mx6ullevk/imximage.cfg b/board/freescale/mx6ullevk/imximage.cfg
new file mode 100644
index 0000000..80cb038
--- /dev/null
+++ b/board/freescale/mx6ullevk/imximage.cfg
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_QSPI_BOOT
+BOOT_FROM	qspi
+#elif defined(CONFIG_NOR_BOOT)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6ullevk/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E04B4 0x000C0000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x000C0030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000030
+DATA 4 0x020E0264 0x00000030
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00000030
+DATA 4 0x020E0284 0x00000030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B080C 0x00000004
+DATA 4 0x021B083C 0x41640158
+DATA 4 0x021B0848 0x40403237
+DATA 4 0x021B0850 0x40403C33
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B08C0 0x00944009
+DATA 4 0x021B08b8 0x00000800
+DATA 4 0x021B0004 0x0002002D
+DATA 4 0x021B0008 0x1B333030
+DATA 4 0x021B000C 0x676B52F3
+DATA 4 0x021B0010 0xB66D0B63
+DATA 4 0x021B0014 0x01FF00DB
+DATA 4 0x021B0018 0x00201740
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x000026D2
+DATA 4 0x021B0030 0x006B1023
+DATA 4 0x021B0040 0x0000004F
+DATA 4 0x021B0000 0x84180000
+DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B001C 0x02008032
+DATA 4 0x021B001C 0x00008033
+DATA 4 0x021B001C 0x00048031
+DATA 4 0x021B001C 0x15208030
+DATA 4 0x021B001C 0x04008040
+DATA 4 0x021B0020 0x00000800
+DATA 4 0x021B0818 0x00000227
+DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+
+#endif
diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c
new file mode 100644
index 0000000..66b08f8
--- /dev/null
+++ b/board/freescale/mx6ullevk/mx6ullevk.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int mmc_map_to_kernel_blk(int devno)
+{
+	return devno;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
+	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	setenv("board_name", "EVK");
+	setenv("board_rev", "14X14");
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: MX6ULL 14x14 EVK\n");
+
+	return 0;
+}
diff --git a/board/freescale/mx6ullevk/plugin.S b/board/freescale/mx6ullevk/plugin.S
new file mode 100644
index 0000000..65a3c45
--- /dev/null
+++ b/board/freescale/mx6ullevk/plugin.S
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6ull_ddr3_evk_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000C0000
+	str r1, [r0, #0x4B4]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4AC]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x27C]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x250]
+	str r1, [r0, #0x24C]
+	str r1, [r0, #0x490]
+	ldr r1, =0x000C0030
+	str r1, [r0, #0x288]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x270]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x260]
+	str r1, [r0, #0x264]
+	str r1, [r0, #0x4A0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x280]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x284]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x4B0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x498]
+	str r1, [r0, #0x4A4]
+	str r1, [r0, #0x244]
+	str r1, [r0, #0x248]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1C]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00000004
+	str r1, [r0, #0x80C]
+	ldr r1, =0x41640158
+	str r1, [r0, #0x83C]
+	ldr r1, =0x40403237
+	str r1, [r0, #0x848]
+	ldr r1, =0x40403C33
+	str r1, [r0, #0x850]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81C]
+	str r1, [r0, #0x820]
+	ldr r1, =0xF3333333
+	str r1, [r0, #0x82C]
+	str r1, [r0, #0x830]
+	ldr r1, =0x00944009
+	str r1, [r0, #0x8C0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8B8]
+	ldr r1, =0x0002002D
+	str r1, [r0, #0x004]
+	ldr r1, =0x1B333030
+	str r1, [r0, #0x008]
+	ldr r1, =0x676B52F3
+	str r1, [r0, #0x00C]
+	ldr r1, =0xB66D0B63
+	str r1, [r0, #0x010]
+	ldr r1, =0x01FF00DB
+	str r1, [r0, #0x014]
+	ldr r1, =0x00201740
+	str r1, [r0, #0x018]
+	ldr r1, =0x00008000
+	str r1, [r0, #0x01C]
+	ldr r1, =0x000026D2
+	str r1, [r0, #0x02C]
+	ldr r1, =0x006B1023
+	str r1, [r0, #0x030]
+	ldr r1, =0x0000004F
+	str r1, [r0, #0x040]
+	ldr r1, =0x84180000
+	str r1, [r0, #0x000]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+	ldr r1, =0x02008032
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00008033
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00048031
+	str r1, [r0, #0x01C]
+	ldr r1, =0x15208030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04008040
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x020]
+	ldr r1, =0x00000227
+	str r1, [r0, #0x818]
+	ldr r1, =0x0002552D
+	str r1, [r0, #0x004]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01C]
+.endm
+
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #0x68]
+	str r1, [r0, #0x6C]
+	str r1, [r0, #0x70]
+	str r1, [r0, #0x74]
+	str r1, [r0, #0x78]
+	str r1, [r0, #0x7C]
+	str r1, [r0, #0x80]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+	imx6ull_ddr3_evk_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/board/freescale/mx7dsabresd/imximage.cfg b/board/freescale/mx7dsabresd/imximage.cfg
index 76574ff..c2b3a8c 100644
--- a/board/freescale/mx7dsabresd/imximage.cfg
+++ b/board/freescale/mx7dsabresd/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index b936544..a681ece 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -9,7 +9,7 @@
 #include <asm/arch/mx7-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
+#include <asm/mach-imx/iomux-v3.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
@@ -21,27 +21,19 @@
 #include <power/pfuze3000_pmic.h>
 #include "../common/pfuze.h"
 #include <i2c.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/arch/crm_regs.h>
-#include <usb.h>
-#include <usb/ehci-ci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
 	PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
-	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
-
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
 #define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
 
 #define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
 
-#define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
-	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
-
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
 	PAD_CTL_DSE_3P3V_49OHM)
 
@@ -50,22 +42,28 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
 
+#define SPI_PAD_CTRL \
+  (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST)
+
 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
-#ifdef CONFIG_SYS_I2C_MXC
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C1 for PMIC */
-static struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
-		.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
-		.gp = IMX_GPIO_NR(4, 8),
-	},
-	.sda = {
-		.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
-		.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
-		.gp = IMX_GPIO_NR(4, 9),
-	},
+
+#ifdef CONFIG_MXC_SPI
+static iomux_v3_cfg_t const ecspi3_pads[] = {
+    MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+    MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+    MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+    MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+         return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1;
+}
+
+static void setup_spi(void)
+{
+         imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
+}
 #endif
 
 int dram_init(void)
@@ -84,130 +82,6 @@ static iomux_v3_cfg_t const uart1_pads[] = {
 	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-static iomux_v3_cfg_t const usdhc1_pads[] = {
-	MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
-	MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
-	MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_STROBE__SD3_STROBE	 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
-	MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usb_otg1_pads[] = {
-	MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const usb_otg2_pads[] = {
-	MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-#define IOX_SDI IMX_GPIO_NR(1, 9)
-#define IOX_STCP IMX_GPIO_NR(1, 12)
-#define IOX_SHCP IMX_GPIO_NR(1, 13)
-
-static iomux_v3_cfg_t const iox_pads[] = {
-	/* IOX_SDI */
-	MX7D_PAD_GPIO1_IO09__GPIO1_IO9	| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* IOX_STCP */
-	MX7D_PAD_GPIO1_IO12__GPIO1_IO12	| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* IOX_SHCP */
-	MX7D_PAD_GPIO1_IO13__GPIO1_IO13	| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-/*
- * PCIE_DIS_B --> Q0
- * PCIE_RST_B --> Q1
- * HDMI_RST_B --> Q2
- * PERI_RST_B --> Q3
- * SENSOR_RST_B --> Q4
- * ENET_RST_B --> Q5
- * PERI_3V3_EN --> Q6
- * LCD_PWR_EN --> Q7
- */
-enum qn {
-	PCIE_DIS_B,
-	PCIE_RST_B,
-	HDMI_RST_B,
-	PERI_RST_B,
-	SENSOR_RST_B,
-	ENET_RST_B,
-	PERI_3V3_EN,
-	LCD_PWR_EN,
-};
-
-enum qn_func {
-	qn_reset,
-	qn_enable,
-	qn_disable,
-};
-
-enum qn_level {
-	qn_low = 0,
-	qn_high = 1,
-};
-
-static enum qn_level seq[3][2] = {
-	{0, 1}, {1, 1}, {0, 0}
-};
-
-static enum qn_func qn_output[8] = {
-	qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable,
-	qn_disable
-};
-
-static void iox74lv_init(void)
-{
-	int i;
-
-	for (i = 7; i >= 0; i--) {
-		gpio_direction_output(IOX_SHCP, 0);
-		gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]);
-		udelay(500);
-		gpio_direction_output(IOX_SHCP, 1);
-		udelay(500);
-	}
-
-	gpio_direction_output(IOX_STCP, 0);
-	udelay(500);
-	/*
-	  * shift register will be output to pins
-	  */
-	gpio_direction_output(IOX_STCP, 1);
-
-	for (i = 7; i >= 0; i--) {
-		gpio_direction_output(IOX_SHCP, 0);
-		gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]);
-		udelay(500);
-		gpio_direction_output(IOX_SHCP, 1);
-		udelay(500);
-	}
-	gpio_direction_output(IOX_STCP, 0);
-	udelay(500);
-	/*
-	  * shift register will be output to pins
-	  */
-	gpio_direction_output(IOX_STCP, 1);
-};
-
 #ifdef CONFIG_NAND_MXS
 static iomux_v3_cfg_t const gpmi_pads[] = {
 	MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
@@ -286,11 +160,13 @@ static int setup_lcd(void)
 	imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
 
 	/* Reset LCD */
+	gpio_request(IMX_GPIO_NR(3, 4), "lcd reset");
 	gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
 	udelay(500);
 	gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
 
 	/* Set Brightness to high */
+	gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight");
 	gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
 
 	return 0;
@@ -326,17 +202,6 @@ static void setup_iomux_uart(void)
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
-#ifdef CONFIG_FSL_ESDHC
-
-#define USDHC1_CD_GPIO	IMX_GPIO_NR(5, 0)
-#define USDHC1_PWR_GPIO	IMX_GPIO_NR(5, 2)
-#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)
-
-static struct fsl_esdhc_cfg usdhc_cfg[3] = {
-	{USDHC1_BASE_ADDR, 0, 4},
-	{USDHC3_BASE_ADDR},
-};
-
 int board_mmc_get_env_dev(int devno)
 {
 	if (devno == 2)
@@ -345,7 +210,7 @@ int board_mmc_get_env_dev(int devno)
 	return devno;
 }
 
-static int mmc_map_to_kernel_blk(int dev_no)
+int mmc_map_to_kernel_blk(int dev_no)
 {
 	if (dev_no == 1)
 		dev_no++;
@@ -353,106 +218,27 @@ static int mmc_map_to_kernel_blk(int dev_no)
 	return dev_no;
 }
 
-int board_mmc_getcd(struct mmc *mmc)
+#ifdef CONFIG_FEC_MXC
+int board_eth_init(bd_t *bis)
 {
-	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-	int ret = 0;
-
-	switch (cfg->esdhc_base) {
-	case USDHC1_BASE_ADDR:
-		ret = !gpio_get_value(USDHC1_CD_GPIO);
-		break;
-	case USDHC3_BASE_ADDR:
-		ret = 1; /* Assume uSDHC3 emmc is always present */
-		break;
-	}
-
-	return ret;
-}
+	int ret;
+	unsigned int gpio;
 
-int board_mmc_init(bd_t *bis)
-{
-	int i, ret;
-	/*
-	 * According to the board_mmc_init() the following map is done:
-	 * (U-Boot device node)    (Physical Port)
-	 * mmc0                    USDHC1
-	 * mmc2                    USDHC3 (eMMC)
-	 */
-	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
-		switch (i) {
-		case 0:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
-			gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
-			gpio_direction_input(USDHC1_CD_GPIO);
-			gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
-			gpio_direction_output(USDHC1_PWR_GPIO, 0);
-			udelay(500);
-			gpio_direction_output(USDHC1_PWR_GPIO, 1);
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-			break;
-		case 1:
-			imx_iomux_v3_setup_multiple_pads(
-				usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
-			gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");
-			gpio_direction_output(USDHC3_PWR_GPIO, 0);
-			udelay(500);
-			gpio_direction_output(USDHC3_PWR_GPIO, 1);
-			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers"
-				"(%d) than supported by the board\n", i + 1);
-			return -EINVAL;
-			}
-
-			ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
-			if (ret)
-				return ret;
+	ret = gpio_lookup_name("gpio_spi@0_5", NULL, NULL, &gpio);
+	if (ret) {
+		printf("GPIO: 'gpio_spi@0_5' not found\n");
+		return -ENODEV;
 	}
 
-	return 0;
-}
-
-static int check_mmc_autodetect(void)
-{
-	char *autodetect_str = getenv("mmcautodetect");
-
-	if ((autodetect_str != NULL) &&
-		(strcmp(autodetect_str, "yes") == 0)) {
-		return 1;
+	ret = gpio_request(gpio, "fec_rst");
+	if (ret && ret != -EBUSY) {
+		printf("gpio: requesting pin %u failed\n", gpio);
+		return ret;
 	}
 
-	return 0;
-}
-
-static void mmc_late_init(void)
-{
-	char cmd[32];
-	char mmcblk[32];
-	u32 dev_no = mmc_get_env_dev();
-
-	if (!check_mmc_autodetect())
-		return;
-
-	setenv_ulong("mmcdev", dev_no);
-
-	/* Set mmcblk env */
-	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
-		mmc_map_to_kernel_blk(dev_no));
-	setenv("mmcroot", mmcblk);
-
-	sprintf(cmd, "mmc dev %d", dev_no);
-	run_command(cmd, 0);
-}
-
-#endif
-
-#ifdef CONFIG_FEC_MXC
-int board_eth_init(bd_t *bis)
-{
-	int ret;
+	gpio_direction_output(gpio, 0);
+	udelay(500);
+	gpio_direction_output(gpio, 1);
 
 	setup_iomux_fec();
 
@@ -519,12 +305,6 @@ int board_early_init_f(void)
 {
 	setup_iomux_uart();
 
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
-					 ARRAY_SIZE(usb_otg1_pads));
-	imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
-					 ARRAY_SIZE(usb_otg2_pads));
-
 	return 0;
 }
 
@@ -533,10 +313,6 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-	imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads));
-
-	iox74lv_init();
-
 #ifdef CONFIG_FEC_MXC
 	setup_fec();
 #endif
@@ -553,32 +329,36 @@ int board_init(void)
 	board_qspi_init();
 #endif
 
+#ifdef CONFIG_MXC_SPI
+       setup_spi();
+#endif
+
 	return 0;
 }
 
-#ifdef CONFIG_POWER
-#define I2C_PMIC	0
+#ifdef CONFIG_DM_PMIC
 int power_init_board(void)
 {
-	struct pmic *p;
-	int ret;
-	unsigned int reg, rev_id;
+	struct udevice *dev;
+	int ret, dev_id, rev_id;
 
-	ret = power_pfuze3000_init(I2C_PMIC);
-	if (ret)
+	ret = pmic_get("pfuze3000", &dev);
+	if (ret == -ENODEV)
+		return 0;
+	if (ret != 0)
 		return ret;
 
-	p = pmic_get("PFUZE3000");
-	ret = pmic_probe(p);
-	if (ret)
-		return ret;
+	dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
+	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
 
-	pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
-	pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
-	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
+	pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
 
-	/* disable Low Power Mode during standby mode */
-	pmic_reg_write(p, PFUZE3000_LDOGCTL, 0x1);
+	/*
+	 * Set the voltage of VLDO4 output to 2.8V which feeds
+	 * the MIPI DSI and MIPI CSI inputs.
+	 */
+	pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA);
 
 	return 0;
 }
@@ -588,10 +368,6 @@ int board_late_init(void)
 {
 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 
-#ifdef CONFIG_ENV_IS_IN_MMC
-	mmc_late_init();
-#endif
-
 	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 
 	set_wdog_reset(wdog);
@@ -618,13 +394,3 @@ int checkboard(void)
 
 	return 0;
 }
-
-#ifdef CONFIG_USB_EHCI_MX7
-int board_usb_phy_mode(int port)
-{
-	if (port == 0)
-		return USB_INIT_DEVICE;
-	else
-		return USB_INIT_HOST;
-}
-#endif
diff --git a/board/freescale/mx7ulp_evk/Kconfig b/board/freescale/mx7ulp_evk/Kconfig
new file mode 100644
index 0000000..ff44831
--- /dev/null
+++ b/board/freescale/mx7ulp_evk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX7ULP_EVK
+
+config SYS_BOARD
+	default "mx7ulp_evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx7ulp_evk"
+
+endif
diff --git a/board/freescale/mx7ulp_evk/MAINTAINERS b/board/freescale/mx7ulp_evk/MAINTAINERS
new file mode 100644
index 0000000..1aa2644
--- /dev/null
+++ b/board/freescale/mx7ulp_evk/MAINTAINERS
@@ -0,0 +1,7 @@
+MX7ULPEVK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/mx7ulp_evk/
+F:	include/configs/mx7ulp_evk.h
+F:	configs/mx7ulp_evk_defconfig
+F:	configs/mx7ulp_evk_plugin_defconfig
diff --git a/board/freescale/mx7ulp_evk/Makefile b/board/freescale/mx7ulp_evk/Makefile
new file mode 100644
index 0000000..5e19eb4
--- /dev/null
+++ b/board/freescale/mx7ulp_evk/Makefile
@@ -0,0 +1,10 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx7ulp_evk.o
+
+extra-$(CONFIG_USE_PLUGIN) :=  plugin.bin
+$(obj)/plugin.bin: $(obj)/plugin.o
+	$(OBJCOPY) -O binary --gap-fill 0xff $< $@
diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg
new file mode 100644
index 0000000..e4e4cb3
--- /dev/null
+++ b/board/freescale/mx7ulp_evk/imximage.cfg
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7ulp_evk/plugin.bin 0x2F020000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4   0x403f00dc 0x00000000
+DATA 4   0x403e0040 0x01000020
+DATA 4   0x403e0500 0x01000000
+DATA 4   0x403e050c 0x80808080
+DATA 4   0x403e0508 0x00140000
+DATA 4   0x403E0510 0x00000004
+DATA 4   0x403E0514 0x00000002
+DATA 4   0x403e0500 0x00000001
+CHECK_BITS_SET 4 0x403e0500 0x01000000
+DATA 4   0x403e050c 0x8080801E
+CHECK_BITS_SET 4 0x403e050c 0x00000040
+DATA 4   0x403E0030 0x00000001
+DATA 4   0x403e0040 0x11000020
+DATA 4   0x403f00dc 0x42000000
+
+DATA 4   0x40B300AC 0x40000000
+
+DATA 4   0x40AD0128 0x00040000
+DATA 4   0x40AD00F8 0x00000000
+DATA 4   0x40AD00D8 0x00000180
+DATA 4   0x40AD0108 0x00000180
+DATA 4   0x40AD0104 0x00000180
+DATA 4   0x40AD0124 0x00010000
+DATA 4   0x40AD0080 0x0000018C
+DATA 4   0x40AD0084 0x0000018C
+DATA 4   0x40AD0088 0x0000018C
+DATA 4   0x40AD008C 0x0000018C
+
+DATA 4   0x40AD0120 0x00010000
+DATA 4   0x40AD010C 0x00000180
+DATA 4   0x40AD0110 0x00000180
+DATA 4   0x40AD0114 0x00000180
+DATA 4   0x40AD0118 0x00000180
+DATA 4   0x40AD0090 0x00000180
+DATA 4   0x40AD0094 0x00000180
+DATA 4   0x40AD0098 0x00000180
+DATA 4   0x40AD009C 0x00000180
+
+DATA 4   0x40AD00E0 0x00040000
+DATA 4   0x40AD00E4 0x00040000
+
+DATA 4   0x40AB001C 0x00008000
+DATA 4   0x40AB0800 0xA1390003
+DATA 4   0x40AB085C 0x0D3900A0
+DATA 4   0x40AB0890 0x00400000
+
+DATA 4   0x40AB0848 0x40404040
+DATA 4   0x40AB0850 0x40404040
+DATA 4   0x40AB081C 0x33333333
+DATA 4   0x40AB0820 0x33333333
+DATA 4   0x40AB0824 0x33333333
+DATA 4   0x40AB0828 0x33333333
+
+DATA 4   0x40AB082C 0xf3333333
+DATA 4   0x40AB0830 0xf3333333
+DATA 4   0x40AB0834 0xf3333333
+DATA 4   0x40AB0838 0xf3333333
+
+DATA 4   0x40AB08C0 0x24922492
+DATA 4   0x40AB08B8 0x00000800
+
+DATA 4   0x40AB0004 0x00020052
+DATA 4   0x40AB000C 0x292C42F3
+DATA 4   0x40AB0010 0x00100A22
+DATA 4   0x40AB0038 0x00120556
+DATA 4   0x40AB0014 0x00C700DB
+DATA 4   0x40AB0018 0x00211718
+DATA 4   0x40AB002C 0x0F9F26D2
+DATA 4   0x40AB0030 0x009F0E10
+DATA 4   0x40AB0040 0x0000003F
+DATA 4   0x40AB0000 0xC3190000
+
+DATA 4   0x40AB001C 0x00008050
+DATA 4   0x40AB001C 0x00008058
+DATA 4   0x40AB001C 0x003F8030
+DATA 4   0x40AB001C 0x003F8038
+DATA 4   0x40AB001C 0xFF0A8030
+DATA 4   0x40AB001C 0xFF0A8038
+DATA 4   0x40AB001C 0x04028030
+DATA 4   0x40AB001C 0x04028038
+DATA 4   0x40AB001C 0x83018030
+DATA 4   0x40AB001C 0x83018038
+DATA 4   0x40AB001C 0x01038030
+DATA 4   0x40AB001C 0x01038038
+
+DATA 4   0x40AB083C 0x20000000
+
+DATA 4   0x40AB0020 0x00001800
+DATA 4   0x40AB0800 0xA1310000
+DATA 4   0x40AB0004 0x00020052
+DATA 4   0x40AB0404 0x00011006
+DATA 4   0x40AB001C 0x00000000
+#endif
diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c
new file mode 100644
index 0000000..3618715
--- /dev/null
+++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mx7ulp-pins.h>
+#include <asm/arch/iomux.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_PUS_UP)
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_cfg_t const lpuart4_pads[] = {
+	MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	mx7ulp_iomux_setup_multiple_pads(lpuart4_pads,
+					 ARRAY_SIZE(lpuart4_pads));
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S
new file mode 100644
index 0000000..9eab365
--- /dev/null
+++ b/board/freescale/mx7ulp_evk/plugin.S
@@ -0,0 +1,224 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+.macro imx7ulp_ddr_freq_decrease
+	ldr r2, =0x403f0000
+	ldr r3, =0x00000000
+	str r3, [r2, #0xdc]
+
+	ldr r2, =0x403e0000
+	ldr r3, =0x01000020
+	str r3, [r2, #0x40]
+	ldr r3, =0x01000000
+	str r3, [r2, #0x500]
+	ldr r3, =0x80808080
+	str r3, [r2, #0x50c]
+	ldr r3, =0x00140000
+	str r3, [r2, #0x508]
+	ldr r3, =0x00000004
+	str r3, [r2, #0x510]
+	ldr r3, =0x00000002
+	str r3, [r2, #0x514]
+	ldr r3, =0x00000001
+	str r3, [r2, #0x500]
+
+	ldr r3, =0x01000000
+wait1:
+	ldr r4, [r2, #0x500]
+	and r4, r3
+	cmp r4, r3
+	bne wait1
+
+	ldr r3, =0x8080801E
+	str r3, [r2, #0x50c]
+
+	ldr r3, =0x00000040
+wait2:
+	ldr r4, [r2, #0x50c]
+	and r4, r3
+	cmp r4, r3
+	bne wait2
+
+	ldr r3, =0x00000001
+	str r3, [r2, #0x30]
+	ldr r3, =0x11000020
+	str r3, [r2, #0x40]
+
+	ldr r2, =0x403f0000
+	ldr r3, =0x42000000
+	str r3, [r2, #0xdc]
+
+.endm
+
+.macro imx7ulp_evk_ddr_setting
+
+	imx7ulp_ddr_freq_decrease
+
+	/* Enable MMDC PCC clock */
+	ldr r2, =0x40b30000
+	ldr r3, =0x40000000
+	str r3, [r2, #0xac]
+
+	/* Configure DDR pad */
+	ldr r0, =0x40ad0000
+	ldr r1, =0x00040000
+	str r1, [r0, #0x128]
+	ldr r1, =0x0
+	str r1, [r0, #0xf8]
+	ldr r1, =0x00000180
+	str r1, [r0, #0xd8]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x108]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x104]
+	ldr r1, =0x00010000
+	str r1, [r0, #0x124]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x80]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x84]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x88]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x8c]
+
+	ldr r1, =0x00010000
+	str r1, [r0, #0x120]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x10c]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x110]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x114]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x118]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x90]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x94]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x98]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x9c]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe0]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe4]
+
+	ldr r0, =0x40ab0000
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1c]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x0D3900A0
+	str r1, [r0, #0x85c]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+
+	ldr r1, =0x40404040
+	str r1, [r0, #0x848]
+	ldr r1, =0x40404040
+	str r1, [r0, #0x850]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81c]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x820]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x824]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x828]
+
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x82c]
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x830]
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x834]
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x838]
+
+	ldr r1, =0x24922492
+	str r1, [r0, #0x8c0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+
+	ldr r1, =0x00020052
+	str r1, [r0, #0x4]
+	ldr r1, =0x292C42F3
+	str r1, [r0, #0xc]
+	ldr r1, =0x00100A22
+	str r1, [r0, #0x10]
+	ldr r1, =0x00120556
+	str r1, [r0, #0x38]
+	ldr r1, =0x00C700DB
+	str r1, [r0, #0x14]
+	ldr r1, =0x00211718
+	str r1, [r0, #0x18]
+
+	ldr r1, =0x0F9F26D2
+	str r1, [r0, #0x2c]
+	ldr r1, =0x009F0E10
+	str r1, [r0, #0x30]
+	ldr r1, =0x0000003F
+	str r1, [r0, #0x40]
+	ldr r1, =0xC3190000
+	str r1, [r0, #0x0]
+
+	ldr r1, =0x00008050
+	str r1, [r0, #0x1c]
+	ldr r1, =0x00008058
+	str r1, [r0, #0x1c]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x003F8038
+	str r1, [r0, #0x1c]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0xFF0A8038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x04028038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x83018030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x83018038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x01038038
+	str r1, [r0, #0x1c]
+
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83c]
+
+	ldr r1, =0x00001800
+	str r1, [r0, #0x20]
+	ldr r1, =0xA1310000
+	str r1, [r0, #0x800]
+	ldr r1, =0x00020052
+	str r1, [r0, #0x4]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x1c]
+
+.endm
+
+.macro imx7ulp_clock_gating
+.endm
+
+.macro imx7ulp_qos_setting
+.endm
+
+.macro imx7ulp_ddr_setting
+	imx7ulp_evk_ddr_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx7ulp_plugin.S>
diff --git a/board/freescale/p1010rdb/Kconfig b/board/freescale/p1010rdb/Kconfig
index b0a7a8d..3adac4a 100644
--- a/board/freescale/p1010rdb/Kconfig
+++ b/board/freescale/p1010rdb/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_P1010RDB
+if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB
 
 config SYS_BOARD
 	default "p1010rdb"
@@ -9,4 +9,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "P1010RDB"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/p1010rdb/MAINTAINERS b/board/freescale/p1010rdb/MAINTAINERS
index db00143..c9f7fa3 100644
--- a/board/freescale/p1010rdb/MAINTAINERS
+++ b/board/freescale/p1010rdb/MAINTAINERS
@@ -1,5 +1,5 @@
 P1010RDB BOARD
-#M:	-
+M:	Qiang Zhao <qiang.zhao@nxp.com>
 S:	Maintained
 F:	board/freescale/p1010rdb/
 F:	include/configs/P1010RDB.h
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index 1ae1540..65bb575 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -54,7 +54,7 @@ static uint sd_ifc_mux;
 
 struct cpld_data {
 	u8 cpld_ver; /* cpld revision */
-#if defined(CONFIG_P1010RDB_PA)
+#if defined(CONFIG_TARGET_P1010RDB_PA)
 	u8 pcba_ver; /* pcb revision number */
 	u8 twindie_ddr3;
 	u8 res1[6];
@@ -69,7 +69,7 @@ struct cpld_data {
 	u8 por1; /* POR Options */
 	u8 por2; /* POR Options */
 	u8 por3; /* POR Options */
-#elif defined(CONFIG_P1010RDB_PB)
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
 	u8 rom_loc;
 #endif
 };
@@ -135,7 +135,7 @@ int config_board_mux(int ctrl_type)
 	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	u8 tmp;
 
-#if defined(CONFIG_P1010RDB_PA)
+#if defined(CONFIG_TARGET_P1010RDB_PA)
 	struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 
 	switch (ctrl_type) {
@@ -171,7 +171,7 @@ int config_board_mux(int ctrl_type)
 	default:
 		break;
 	}
-#elif defined(CONFIG_P1010RDB_PB)
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
 	uint orig_bus = i2c_get_bus_num();
 	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 
@@ -245,7 +245,7 @@ int config_board_mux(int ctrl_type)
 	return 0;
 }
 
-#ifdef CONFIG_P1010RDB_PB
+#ifdef CONFIG_TARGET_P1010RDB_PB
 int i2c_pca9557_read(int type)
 {
 	u8 val;
@@ -275,9 +275,9 @@ int checkboard(void)
 	u8 val;
 
 	cpu = gd->arch.cpu;
-#if defined(CONFIG_P1010RDB_PA)
+#if defined(CONFIG_TARGET_P1010RDB_PA)
 	printf("Board: %sRDB-PA, ", cpu->name);
-#elif defined(CONFIG_P1010RDB_PB)
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
 	printf("Board: %sRDB-PB, ", cpu->name);
 	i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 	i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
@@ -290,10 +290,10 @@ int checkboard(void)
 	config_board_mux(MUX_TYPE_IFC);
 #endif
 
-#if defined(CONFIG_P1010RDB_PA)
+#if defined(CONFIG_TARGET_P1010RDB_PA)
 	val = (in_8(&cpld_data->pcba_ver) & 0xf);
 	printf("PCB: v%x.0\n", val);
-#elif defined(CONFIG_P1010RDB_PB)
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
 	val = in_8(&cpld_data->cpld_ver);
 	printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
 	printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
@@ -463,7 +463,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
 #if defined(CONFIG_HAS_FSL_DR_USB)
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
        /* P1014 and it's derivatives don't support CAN and eTSEC3 */
@@ -544,7 +544,7 @@ int misc_init_r(void)
 	else if (hwconfig("ifc"))
 		config_board_mux(MUX_TYPE_IFC);
 
-#ifdef CONFIG_P1010RDB_PB
+#ifdef CONFIG_TARGET_P1010RDB_PB
 	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
 #endif
 	return 0;
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index f858408..2cebc2c 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c
@@ -12,6 +12,7 @@
 #include <i2c.h>
 #include <fsl_esdhc.h>
 #include <spi_flash.h>
+#include "../common/spl.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -31,7 +32,7 @@ void board_init_f(ulong bootflag)
 	/* Clock configuration to access CPLD using IFC(GPCM) */
 	setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
 
-#ifdef CONFIG_P1010RDB_PB
+#ifdef CONFIG_TARGET_P1010RDB_PB
 	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
 #endif
 
@@ -68,7 +69,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
 	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
 
-	probecpu();
+	arch_cpu_init();
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
@@ -93,7 +94,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	dram_init();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("\nTertiary program loader running in sram...");
 #else
@@ -103,7 +104,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
 #elif defined(CONFIG_SPL_SPI_BOOT)
-	spi_boot();
+	fsl_spi_boot();
 #elif defined(CONFIG_SPL_NAND_BOOT)
 	nand_boot();
 #endif
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index d7dd478..345feac 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -345,7 +345,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
 #ifdef CONFIG_HAS_FSL_DR_USB
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
 	FT_FSL_PCI_SETUP;
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
index 04db767..a117dc3 100644
--- a/board/freescale/p1022ds/spl.c
+++ b/board/freescale/p1022ds/spl.c
@@ -14,6 +14,7 @@
 #include "../common/ngpixis.h"
 #include <fsl_esdhc.h>
 #include <spi_flash.h>
+#include "../common/spl.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -82,7 +83,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
 	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
 
-	probecpu();
+	arch_cpu_init();
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
@@ -110,7 +111,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-	gd->ram_size = initdram(0);
+	dram_init();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("Tertiary program loader running in sram...");
 #else
@@ -120,7 +121,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
 #elif defined(CONFIG_SPL_SPI_BOOT)
-	spi_boot();
+	fsl_spi_boot();
 #elif defined(CONFIG_SPL_NAND_BOOT)
 	nand_boot();
 #endif
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
index 074b713..0451722 100644
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -143,7 +143,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
 #ifdef CONFIG_HAS_FSL_DR_USB
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
 	fdt_fixup_fman_ethernet(blob);
diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig
index d3352d2..2f9640b 100644
--- a/board/freescale/p1_p2_rdb_pc/Kconfig
+++ b/board/freescale/p1_p2_rdb_pc/Kconfig
@@ -1,4 +1,11 @@
-if TARGET_P1_P2_RDB_PC
+if TARGET_P1020MBG		|| \
+	TARGET_P1020RDB_PC	|| \
+	TARGET_P1020RDB_PD	|| \
+	TARGET_P1020UTM		|| \
+	TARGET_P1021RDB		|| \
+	TARGET_P1024RDB		|| \
+	TARGET_P1025RDB		|| \
+	TARGET_P2020RDB
 
 config SYS_BOARD
 	default "p1_p2_rdb_pc"
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 1f3793b..fc38326 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -15,8 +15,8 @@
 
 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 #if	defined(CONFIG_P1020RDB_PROTO) || \
-	defined(CONFIG_P1021RDB) || \
-	defined(CONFIG_P1020UTM)
+	defined(CONFIG_TARGET_P1021RDB) || \
+	defined(CONFIG_TARGET_P1020UTM)
 /* Micron MT41J256M8_187E */
 dimm_params_t ddr_raw_timing = {
 	.n_ranks = 1,
@@ -47,7 +47,7 @@ dimm_params_t ddr_raw_timing = {
 	.refresh_rate_ps = 7800000,
 	.tfaw_ps = 37500,
 };
-#elif defined(CONFIG_P2020RDB)
+#elif defined(CONFIG_TARGET_P2020RDB)
 /* Micron MT41J128M16_15E */
 dimm_params_t ddr_raw_timing = {
 	.n_ranks = 1,
@@ -78,7 +78,7 @@ dimm_params_t ddr_raw_timing = {
 	.refresh_rate_ps = 7800000,
 	.tfaw_ps = 30000,
 };
-#elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
+#elif (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
 /* Micron MT41J512M8_187E */
 dimm_params_t ddr_raw_timing = {
 	.n_ranks = 2,
@@ -109,7 +109,7 @@ dimm_params_t ddr_raw_timing = {
 	.refresh_rate_ps = 7800000,
 	.tfaw_ps = 37500,
 };
-#elif defined(CONFIG_P1020RDB_PC)
+#elif defined(CONFIG_TARGET_P1020RDB_PC)
 /*
  * Samsung K4B2G0846C-HCF8
  * The following timing are for "downshift"
@@ -146,8 +146,8 @@ dimm_params_t ddr_raw_timing = {
 	.refresh_rate_ps = 7800000,
 	.tfaw_ps = 37500,
 };
-#elif	defined(CONFIG_P1024RDB) || \
-	defined(CONFIG_P1025RDB)
+#elif	defined(CONFIG_TARGET_P1024RDB) || \
+	defined(CONFIG_TARGET_P1025RDB)
 /*
  * Samsung K4B2G0846C-HCH9
  * The following timing are for "downshift"
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 61b7a91..51217c5 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -39,7 +39,7 @@
 #define GPIO_SLIC_PIN		30
 #define GPIO_SLIC_DATA		(1 << (31 - GPIO_SLIC_PIN))
 
-#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
 #define GPIO_DDR_RST_PORT	1
 #define GPIO_DDR_RST_PIN	8
 #define GPIO_DDR_RST_DATA	(1 << (31 - GPIO_DDR_RST_PIN))
@@ -47,7 +47,7 @@
 #define GPIO_2BIT_MASK		(0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
 #endif
 
-#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
+#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
 #define PCA_IOPORT_I2C_ADDR		0x23
 #define PCA_IOPORT_OUTPUT_CMD		0x2
 #define PCA_IOPORT_CFG_CMD		0x6
@@ -58,14 +58,14 @@
 const qe_iop_conf_t qe_iop_conf_tab[] = {
 	/* GPIO */
 	{1,   1, 2, 0, 0}, /* GPIO7/PB1   - LOAD_DEFAULT_N */
-#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
 	{1,   8, 1, 1, 0}, /* GPIO10/PB8  - DDR_RST */
 #endif
 	{0,  15, 1, 0, 0}, /* GPIO11/A15  - WDI */
 	{GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0},	/* RST_GETH_SW_N */
 	{GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0},	/* RST_SLIC_N */
 
-#ifdef CONFIG_P1025RDB
+#ifdef CONFIG_TARGET_P1025RDB
 	/* QE_MUX_MDC */
 	{1,  19, 1, 0, 1}, /* QE_MUX_MDC               */
 
@@ -150,7 +150,7 @@ void board_gpio_init(void)
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
 
-#if defined(CONFIG_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
 	/* reset DDR3 */
 	setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
 	udelay(1000);
@@ -379,7 +379,7 @@ int board_eth_init(bd_t *bis)
 }
 
 #if defined(CONFIG_QE) && \
-	(defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB))
+	(defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
 static void fdt_board_fixup_qe_pins(void *blob)
 {
 	unsigned int oldbus;
@@ -428,7 +428,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 {
 	phys_addr_t base;
 	phys_size_t size;
-#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC)
+#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
 	const char *soc_usb_compat = "fsl-usb2-dr";
 	int usb_err, usb1_off, usb2_off;
 #endif
@@ -448,13 +448,13 @@ int ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_QE
 	do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
 			sizeof("okay"), 0);
-#if defined(CONFIG_P1025RDB) || defined(CONFIG_P1021RDB)
+#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
 	fdt_board_fixup_qe_pins(blob);
 #endif
 #endif
 
 #if defined(CONFIG_HAS_FSL_DR_USB)
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
@@ -478,7 +478,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	}
 #endif
 
-#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC)
+#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
 /* Delete USB2 node as it is muxed with eLBC */
 	usb1_off = fdt_node_offset_by_compatible(blob, -1,
 		soc_usb_compat);
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index 76a3cf4..ca7ba57 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -13,14 +13,10 @@
 #include <i2c.h>
 #include <fsl_esdhc.h>
 #include <spi_flash.h>
+#include "../common/spl.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const u32 sysclk_tbl[] = {
-	66666000, 7499900, 83332500, 8999900,
-	99999000, 11111000, 12499800, 13333200
-};
-
 phys_size_t get_effective_memsize(void)
 {
 	return CONFIG_SYS_L2_SIZE;
@@ -79,7 +75,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
 	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
 
-	probecpu();
+	arch_cpu_init();
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
@@ -107,7 +103,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-	gd->ram_size = initdram(0);
+	dram_init();
 #ifdef CONFIG_SPL_NAND_BOOT
 	puts("Tertiary program loader running in sram...");
 #else
@@ -117,7 +113,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
 #elif defined(CONFIG_SPL_SPI_BOOT)
-	spi_boot();
+	fsl_spi_boot();
 #elif defined(CONFIG_SPL_NAND_BOOT)
 	nand_boot();
 #endif
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 1c0008b..7cba411 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -85,13 +85,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 8, BOOKE_PAGESZ_1G, 1),
 
-#if defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)
+#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)
 	/* 2G DDR on P1020MBG, map the second 1G */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 			CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 9, BOOKE_PAGESZ_1G, 1),
-#endif /* P1020MBG */
+#endif /* TARGET_P1020MBG */
 #endif /* RAMBOOT/SPL */
 
 #ifdef CONFIG_SYS_INIT_L2_ADDR
diff --git a/board/freescale/p1_twr/MAINTAINERS b/board/freescale/p1_twr/MAINTAINERS
index c19d436..0f9f98f 100644
--- a/board/freescale/p1_twr/MAINTAINERS
+++ b/board/freescale/p1_twr/MAINTAINERS
@@ -1,5 +1,5 @@
 P1_TWR BOARD
-#M:	-
+M:	Xiaobo Xie <xiaobo.xie@nxp.com>
 S:	Maintained
 F:	board/freescale/p1_twr/
 F:	include/configs/p1_twr.h
diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c
index a40bea3..f54a6ff 100644
--- a/board/freescale/p1_twr/p1_twr.c
+++ b/board/freescale/p1_twr/p1_twr.c
@@ -282,7 +282,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 #if defined(CONFIG_TWR_P1025)
 	fdt_board_fixup_qe_pins(blob);
 #endif
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 
 	return 0;
 }
diff --git a/board/freescale/p2041rdb/Kconfig b/board/freescale/p2041rdb/Kconfig
index 78e1121..7e187dd 100644
--- a/board/freescale/p2041rdb/Kconfig
+++ b/board/freescale/p2041rdb/Kconfig
@@ -9,4 +9,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "P2041RDB"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c
index b2493e1..1ab98fc 100644
--- a/board/freescale/p2041rdb/ddr.c
+++ b/board/freescale/p2041rdb/ddr.c
@@ -12,6 +12,8 @@
 #include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 struct board_specific_parameters {
 	u32 n_ranks;
 	u32 datarate_mhz_high;
@@ -116,7 +118,7 @@ found:
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size = 0;
 
@@ -127,12 +129,14 @@ phys_size_t initdram(int board_type)
 		dram_size = fsl_ddr_sdram();
 	} else {
 		puts("no SPD and fixed parameters\n");
-		return dram_size;
+		return -ENXIO;
 	}
 
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
 	debug("    DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index c6a7242..21fb66f 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -225,7 +225,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
 #ifdef CONFIG_PCI
diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c
index 6cb5692..0c65ec7 100644
--- a/board/freescale/qemu-ppce500/qemu-ppce500.c
+++ b/board/freescale/qemu-ppce500/qemu-ppce500.c
@@ -50,13 +50,19 @@ uint64_t get_phys_ccsrbar_addr_early(void)
 {
 	void *fdt = get_fdt_virt();
 	uint64_t r;
+	int size, node;
+	u32 naddr;
+	const fdt32_t *prop;
 
 	/*
 	 * To be able to read the FDT we need to create a temporary TLB
 	 * map for it.
 	 */
 	map_fdt_as(10);
-	r = fdt_get_base_address(fdt, fdt_path_offset(fdt, "/soc"));
+	node = fdt_path_offset(fdt, "/soc");
+	naddr = fdt_address_cells(fdt, node);
+	prop = fdt_getprop(fdt, node, "ranges", &size);
+	r = fdt_translate_address(fdt, node, prop + naddr);
 	disable_tlb(10);
 
 	return r;
diff --git a/board/freescale/s32v234evb/clock.c b/board/freescale/s32v234evb/clock.c
index d218c21..e8996e0 100644
--- a/board/freescale/s32v234evb/clock.c
+++ b/board/freescale/s32v234evb/clock.c
@@ -45,7 +45,7 @@ static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq)
 		pll_idx = 1;
 		break;
 	case DDR_PLL:
-		pll_idx = 2;;
+		pll_idx = 2;
 		break;
 	default:
 		pll_idx = pll;
diff --git a/board/freescale/s32v234evb/s32v234evb.cfg b/board/freescale/s32v234evb/s32v234evb.cfg
index 6017a40..6626a12 100644
--- a/board/freescale/s32v234evb/s32v234evb.cfg
+++ b/board/freescale/s32v234evb/s32v234evb.cfg
@@ -5,12 +5,12 @@
  */
 
 /*
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
  */
-#include <asm/imx-common/imximage.cfg>
+#include <asm/mach-imx/imximage.cfg>
 
 /* image version */
 IMAGE_VERSION	2
diff --git a/board/freescale/t102xqds/Kconfig b/board/freescale/t102xqds/Kconfig
index 4d17798..87818a8 100644
--- a/board/freescale/t102xqds/Kconfig
+++ b/board/freescale/t102xqds/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_T102XQDS
+if TARGET_T1024QDS
 
 config SYS_BOARD
 	default "t102xqds"
@@ -9,4 +9,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "T102xQDS"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
index c26f350..d822d3f 100644
--- a/board/freescale/t102xqds/ddr.c
+++ b/board/freescale/t102xqds/ddr.c
@@ -139,6 +139,9 @@ found:
 #else
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x5f;
 #endif
 
 	/* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
@@ -166,7 +169,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -184,5 +187,7 @@ phys_size_t initdram(int board_type)
 	fsl_dp_resume();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/t102xqds/law.c b/board/freescale/t102xqds/law.c
index b1c9d01..b32a162 100644
--- a/board/freescale/t102xqds/law.c
+++ b/board/freescale/t102xqds/law.c
@@ -9,7 +9,7 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
 #endif
 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c
index d59d343..b987ece 100644
--- a/board/freescale/t102xqds/spl.c
+++ b/board/freescale/t102xqds/spl.c
@@ -14,6 +14,7 @@
 #include <spi_flash.h>
 #include "../common/qixis.h"
 #include "t102xqds_qixis.h"
+#include "../common/spl.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -65,7 +66,7 @@ void board_init_f(ulong bootflag)
 	u32 plat_ratio, sys_clk, ccb_clk;
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 
-#if defined(CONFIG_PPC_T1040) && defined(CONFIG_SPL_NAND_BOOT)
+#if defined(CONFIG_ARCH_T1040) && defined(CONFIG_SPL_NAND_BOOT)
 	/*
 	 * There is T1040 SoC issue where NOR, FPGA are inaccessible during
 	 * NAND boot because IFC signals > IFC_AD7 are not enabled.
@@ -116,7 +117,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
 	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
-	probecpu();
+	arch_cpu_init();
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
@@ -132,8 +133,8 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 			   (uchar *)CONFIG_ENV_ADDR);
 #endif
 #ifdef CONFIG_SPL_SPI_BOOT
-	spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			   (uchar *)CONFIG_ENV_ADDR);
+	fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			       (uchar *)CONFIG_ENV_ADDR);
 #endif
 
 	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
@@ -141,12 +142,12 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
 #elif defined(CONFIG_SPL_SPI_BOOT)
-	spi_boot();
+	fsl_spi_boot();
 #elif defined(CONFIG_SPL_NAND_BOOT)
 	nand_boot();
 #endif
diff --git a/board/freescale/t102xqds/t1024_rcw.cfg b/board/freescale/t102xqds/t1024_nand_rcw.cfg
index 4b8f719..4b8f719 100644
--- a/board/freescale/t102xqds/t1024_rcw.cfg
+++ b/board/freescale/t102xqds/t1024_nand_rcw.cfg
diff --git a/board/freescale/t102xqds/t1024_sd_rcw.cfg b/board/freescale/t102xqds/t1024_sd_rcw.cfg
new file mode 100644
index 0000000..3eca275
--- /dev/null
+++ b/board/freescale/t102xqds/t1024_sd_rcw.cfg
@@ -0,0 +1,10 @@
+# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
+# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
+
+# PBL preamble and RCW header for T1024QDS
+aa55aa55 010e0100
+# Serdes protocol 0x6F
+0810000e 00000000 00000000 00000000
+37800001 00000012 68104000 21000000
+00000000 00000000 00000000 00030810
+00000000 036c5a00 00000000 00000006
diff --git a/board/freescale/t102xqds/t1024_spi_rcw.cfg b/board/freescale/t102xqds/t1024_spi_rcw.cfg
new file mode 100644
index 0000000..1601e35
--- /dev/null
+++ b/board/freescale/t102xqds/t1024_spi_rcw.cfg
@@ -0,0 +1,10 @@
+# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
+# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
+
+# PBL preamble and RCW header for T1024QDS
+aa55aa55 010e0100
+# Serdes protocol 0x6F
+0810000e 00000000 00000000 00000000
+37800001 00000012 58104000 21000000
+00000000 00000000 00000000 00030810
+00000000 036c5a00 00000000 00000006
diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c
index 76793a1..1b2f6b2 100644
--- a/board/freescale/t102xqds/t102xqds.c
+++ b/board/freescale/t102xqds/t102xqds.c
@@ -152,7 +152,7 @@ static int board_mux_lane_to_slot(void)
 	return 0;
 }
 
-#ifdef CONFIG_PPC_T1024
+#ifdef CONFIG_ARCH_T1024
 static void board_mux_setup(void)
 {
 	u8 brdcfg15;
@@ -332,7 +332,7 @@ unsigned long get_board_ddr_clk(void)
 #define NUM_SRDS_PLL	2
 int misc_init_r(void)
 {
-#ifdef CONFIG_PPC_T1024
+#ifdef CONFIG_ARCH_T1024
 	board_mux_setup();
 #endif
 	return 0;
@@ -375,7 +375,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_liodn(blob);
 
 #ifdef CONFIG_HAS_FSL_DR_USB
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/board/freescale/t102xrdb/Kconfig b/board/freescale/t102xrdb/Kconfig
index 10d49f5..6deeb24 100644
--- a/board/freescale/t102xrdb/Kconfig
+++ b/board/freescale/t102xrdb/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_T102XRDB
+if TARGET_T1023RDB || TARGET_T1024RDB
 
 config SYS_BOARD
 	default "t102xrdb"
@@ -9,4 +9,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "T102xRDB"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile
index 6452865..ddeb44f 100644
--- a/board/freescale/t102xrdb/Makefile
+++ b/board/freescale/t102xrdb/Makefile
@@ -8,7 +8,7 @@ ifdef CONFIG_SPL_BUILD
 obj-y	+= spl.o
 else
 obj-y   += t102xrdb.o
-obj-$(CONFIG_T1024RDB)   += cpld.o
+obj-$(CONFIG_TARGET_T1024RDB)   += cpld.o
 obj-y   += eth_t102xrdb.o
 obj-$(CONFIG_PCI)       += pci.o
 endif
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index edfbdbf..49460a0 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -136,9 +136,13 @@ found:
 	popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
 #endif
 
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
 	popts->wrlvl_ctl_2 = 0x07070606;
 	popts->half_strength_driver_enable = 1;
+	popts->cpo_sample = 0x43;
+#elif defined(CONFIG_TARGET_T1024RDB)
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x52;
 #endif
 }
 
@@ -225,7 +229,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -245,5 +249,7 @@ phys_size_t initdram(int board_type)
 	fsl_dp_resume();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c
index 02b283d..c06d1b8 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -58,7 +58,7 @@ int board_eth_init(bd_t *bis)
 	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
 
 	switch (srds_s1) {
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
 	case 0x95:
 		/* set the on-board RGMII2  PHY */
 		fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
@@ -73,7 +73,7 @@ int board_eth_init(bd_t *bis)
 	case 0x135:
 		/* set the on-board 2.5G SGMII AQR105 PHY */
 		fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
 		/* set the on-board 1G SGMII RTL8211F PHY */
 		fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
 #endif
@@ -92,9 +92,9 @@ int board_eth_init(bd_t *bis)
 			fm_info_set_mdio(i, dev);
 			break;
 		case PHY_INTERFACE_MODE_SGMII:
-#if defined(CONFIG_T1023RDB)
+#if defined(CONFIG_TARGET_T1023RDB)
 			dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
-#elif defined(CONFIG_T1024RDB)
+#elif defined(CONFIG_TARGET_T1024RDB)
 			dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
 #endif
 			fm_info_set_mdio(i, dev);
@@ -128,7 +128,7 @@ int board_eth_init(bd_t *bis)
 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 			      enum fm_port port, int offset)
 {
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
 	if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
 	     (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
 			(port == FM1_DTSEC3)) {
diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c
index 1c9235f..9fd6d89 100644
--- a/board/freescale/t102xrdb/law.c
+++ b/board/freescale/t102xrdb/law.c
@@ -9,7 +9,7 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
 #endif
 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index bd3cbbf..dc6d9ee 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -13,6 +13,7 @@
 #include <fsl_esdhc.h>
 #include <spi_flash.h>
 #include "../common/sleep.h"
+#include "../common/spl.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -103,7 +104,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
 	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
-	probecpu();
+	arch_cpu_init();
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
@@ -119,8 +120,8 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 			   (uchar *)CONFIG_ENV_ADDR);
 #endif
 #ifdef CONFIG_SPL_SPI_BOOT
-	spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			   (uchar *)CONFIG_ENV_ADDR);
+	fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			       (uchar *)CONFIG_ENV_ADDR);
 #endif
 
 	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
@@ -128,12 +129,12 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
 #elif defined(CONFIG_SPL_SPI_BOOT)
-	spi_boot();
+	fsl_spi_boot();
 #elif defined(CONFIG_SPL_NAND_BOOT)
 	nand_boot();
 #endif
diff --git a/board/freescale/t102xrdb/t1023_rcw.cfg b/board/freescale/t102xrdb/t1023_nand_rcw.cfg
index f8f7282..f8f7282 100644
--- a/board/freescale/t102xrdb/t1023_rcw.cfg
+++ b/board/freescale/t102xrdb/t1023_nand_rcw.cfg
diff --git a/board/freescale/t102xrdb/t1023_sd_rcw.cfg b/board/freescale/t102xrdb/t1023_sd_rcw.cfg
new file mode 100644
index 0000000..dbf8fba
--- /dev/null
+++ b/board/freescale/t102xrdb/t1023_sd_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1023RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x77
+#Default Core=1200MHz, DDR=1600MT/s with single source clock
+0810000c 00000000 00000000 00000000
+3b800003 00000012 68104000 21000000
+00000000 00000000 00000000 00022800
+00000130 04020200 00000000 00000006
diff --git a/board/freescale/t102xrdb/t1023_spi_rcw.cfg b/board/freescale/t102xrdb/t1023_spi_rcw.cfg
new file mode 100644
index 0000000..5edcdb5
--- /dev/null
+++ b/board/freescale/t102xrdb/t1023_spi_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1023RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x77
+#Default Core=1200MHz, DDR=1600MT/s with single source clock
+0810000c 00000000 00000000 00000000
+3b800003 00000012 58104000 21000000
+00000000 00000000 00000000 00022800
+00000130 04020200 00000000 00000006
diff --git a/board/freescale/t102xrdb/t1024_rcw.cfg b/board/freescale/t102xrdb/t1024_nand_rcw.cfg
index cd6f906..cd6f906 100644
--- a/board/freescale/t102xrdb/t1024_rcw.cfg
+++ b/board/freescale/t102xrdb/t1024_nand_rcw.cfg
diff --git a/board/freescale/t102xrdb/t1024_sd_rcw.cfg b/board/freescale/t102xrdb/t1024_sd_rcw.cfg
new file mode 100644
index 0000000..05b3f37
--- /dev/null
+++ b/board/freescale/t102xrdb/t1024_sd_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1024RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x95
+#Core/DDR: 1400Mhz/1600MT/s with single source clock
+0810000c 00000000 00000000 00000000
+4a800003 80000012 6c027000 21000000
+00000000 00000000 00000000 00030810
+00000000 0b005a08 00000000 00000006
diff --git a/board/freescale/t102xrdb/t1024_spi_rcw.cfg b/board/freescale/t102xrdb/t1024_spi_rcw.cfg
new file mode 100644
index 0000000..8b695b4
--- /dev/null
+++ b/board/freescale/t102xrdb/t1024_spi_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header for T1024RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x95
+#Core/DDR: 1400Mhz/1600MT/s with single source clock
+0810000c 00000000 00000000 00000000
+4a800003 80000012 5c027000 21000000
+00000000 00000000 00000000 00030810
+00000000 0b005a08 00000000 00000006
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index 01dbf38..f370f72 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -17,9 +17,9 @@
 #include <asm/fsl_liodn.h>
 #include <fm_eth.h>
 #include "t102xrdb.h"
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
 #include "cpld.h"
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
 #include <i2c.h>
 #include <mmc.h>
 #endif
@@ -27,7 +27,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
 enum {
 	GPIO1_SD_SEL    = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
 	GPIO1_EMMC_SEL,
@@ -51,10 +51,10 @@ int checkboard(void)
 	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
 	printf("Board: %sRDB, ", cpu->name);
-#if defined(CONFIG_T1024RDB)
+#if defined(CONFIG_TARGET_T1024RDB)
 	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
 	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
 	printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
 #endif
 	printf("boot from ");
@@ -63,7 +63,7 @@ int checkboard(void)
 	puts("SD/MMC\n");
 #elif CONFIG_SPIFLASH
 	puts("SPI\n");
-#elif defined(CONFIG_T1024RDB)
+#elif defined(CONFIG_TARGET_T1024RDB)
 	u8 reg;
 
 	reg = CPLD_READ(flash_csr);
@@ -74,7 +74,7 @@ int checkboard(void)
 		reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
 		printf("NOR vBank%d\n", reg);
 	}
-#elif defined(CONFIG_T1023RDB)
+#elif defined(CONFIG_TARGET_T1023RDB)
 #ifdef CONFIG_NAND
 	puts("NAND\n");
 #else
@@ -91,7 +91,7 @@ int checkboard(void)
 	return 0;
 }
 
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
 static void board_mux_lane(void)
 {
 	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -150,7 +150,7 @@ int board_early_init_r(void)
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
 #endif
 
-#ifdef CONFIG_T1024RDB
+#ifdef CONFIG_TARGET_T1024RDB
 	board_mux_lane();
 #endif
 
@@ -167,6 +167,13 @@ unsigned long get_board_ddr_clk(void)
 	return CONFIG_DDR_CLK_FREQ;
 }
 
+#ifdef CONFIG_TARGET_T1024RDB
+void board_reset(void)
+{
+	CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
+}
+#endif
+
 int misc_init_r(void)
 {
 	return 0;
@@ -189,14 +196,14 @@ int ft_board_setup(void *blob, bd_t *bd)
 #endif
 
 	fdt_fixup_liodn(blob);
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_ethernet(blob);
 	fdt_fixup_board_enet(blob);
 #endif
 
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
 	if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
 		fdt_enable_nor(blob);
 #endif
@@ -204,7 +211,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	return 0;
 }
 
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
 /* Enable NOR flash for RevC */
 static void fdt_enable_nor(void *blob)
 {
diff --git a/board/freescale/t102xrdb/t102xrdb.h b/board/freescale/t102xrdb/t102xrdb.h
index ae5c60f..6634e7a 100644
--- a/board/freescale/t102xrdb/t102xrdb.h
+++ b/board/freescale/t102xrdb/t102xrdb.h
@@ -9,7 +9,7 @@
 
 void fdt_fixup_board_enet(void *blob);
 void pci_of_setup(void *blob, bd_t *bd);
-#ifdef CONFIG_T1023RDB
+#ifdef CONFIG_TARGET_T1023RDB
 static u32 t1023rdb_ctrl(u32 ctrl_type);
 static void fdt_enable_nor(void *blob);
 #endif
diff --git a/board/freescale/t1040qds/Kconfig b/board/freescale/t1040qds/Kconfig
index 1bb1684..ec3ff0c 100644
--- a/board/freescale/t1040qds/Kconfig
+++ b/board/freescale/t1040qds/Kconfig
@@ -9,4 +9,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "T1040QDS"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
index 8240240..8f7909d 100644
--- a/board/freescale/t1040qds/ddr.c
+++ b/board/freescale/t1040qds/ddr.c
@@ -95,6 +95,9 @@ found:
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
 			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x69;
 #else
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
@@ -114,7 +117,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -131,5 +134,7 @@ phys_size_t initdram(int board_type)
 	fsl_dp_resume();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/t1040qds/law.c b/board/freescale/t1040qds/law.c
index a2dc027..5d3d94a 100644
--- a/board/freescale/t1040qds/law.c
+++ b/board/freescale/t1040qds/law.c
@@ -9,7 +9,7 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
 #endif
 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
index d7d56b4..5466fbf 100644
--- a/board/freescale/t1040qds/t1040qds.c
+++ b/board/freescale/t1040qds/t1040qds.c
@@ -257,7 +257,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_liodn(blob);
 
 #ifdef CONFIG_HAS_FSL_DR_USB
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/board/freescale/t104xrdb/Kconfig b/board/freescale/t104xrdb/Kconfig
index f28728d..e6e46fa 100644
--- a/board/freescale/t104xrdb/Kconfig
+++ b/board/freescale/t104xrdb/Kconfig
@@ -1,4 +1,6 @@
-if TARGET_T104XRDB
+if TARGET_T1040RDB || TARGET_T1040D4RDB || \
+	TARGET_T1042RDB || TARGET_T1042D4RDB || \
+	TARGET_T1042RDB_PI
 
 config SYS_BOARD
 	default "t104xrdb"
@@ -9,4 +11,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "T104xRDB"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS
index 0578989..8e32679 100644
--- a/board/freescale/t104xrdb/MAINTAINERS
+++ b/board/freescale/t104xrdb/MAINTAINERS
@@ -1,5 +1,5 @@
 T104XRDB BOARD
-M:	Priyanka Jain  <Priyanka.Jain@freescale.com>
+M:	Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
 F:	board/freescale/t104xrdb/
 F:	include/configs/T104xRDB.h
@@ -18,7 +18,7 @@ F:	configs/T1042RDB_PI_NAND_defconfig
 F:	configs/T1042RDB_PI_SPIFLASH_defconfig
 
 T1040RDB_SDCARD BOARD
-#M:	-
+M:	Priyanka Jain <priyanka.jain@nxp.com>
 S:	Maintained
 F:	configs/T1040RDB_SDCARD_defconfig
 F:	configs/T1040D4RDB_SDCARD_defconfig
diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c
index 0ce4e47..95ff6a7 100644
--- a/board/freescale/t104xrdb/cpld.c
+++ b/board/freescale/t104xrdb/cpld.c
@@ -69,7 +69,7 @@ static void cpld_dump_regs(void)
 	printf("int_status	 = 0x%02x\n", CPLD_READ(int_status));
 	printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
 	printf("fan_ctl_status	 = 0x%02x\n", CPLD_READ(fan_ctl_status));
-#if defined(CONFIG_T104XD4RDB)
+#if defined(CONFIG_TARGET_T1040D4D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 	printf("int_mask	 = 0x%02x\n", CPLD_READ(int_mask));
 #else
 	printf("led_ctl_status	 = 0x%02x\n", CPLD_READ(led_ctl_status));
diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h
index 86de26c..7adf5e4 100644
--- a/board/freescale/t104xrdb/cpld.h
+++ b/board/freescale/t104xrdb/cpld.h
@@ -21,7 +21,7 @@ struct cpld_data {
 	u8 int_status;		/* 0x12 - Interrupt status Register */
 	u8 flash_ctl_status;	/* 0x13 - Flash control and status register */
 	u8 fan_ctl_status;	/* 0x14 - Fan control and status register  */
-#if defined(CONFIG_T104XD4RDB)
+#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 	u8 int_mask;		/* 0x15 - Interrupt mask Register */
 #else
 	u8 led_ctl_status;	/* 0x15 - LED control and status register */
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index 22d6a5f..4e55844 100644
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -77,6 +77,8 @@ found:
 	 */
 #ifdef CONFIG_SYS_FSL_DDR4
 	popts->half_strength_driver_enable = 1;
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x59;
 #else
 	popts->half_strength_driver_enable = 0;
 #endif
@@ -118,7 +120,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -135,5 +137,7 @@ phys_size_t initdram(int board_type)
 	fsl_dp_resume();
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index 52cd112..ab8c8bb 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -43,7 +43,7 @@ int board_eth_init(bd_t *bis)
 		int idx = i - FM1_DTSEC1;
 
 		switch (fm_info_get_enet_if(i)) {
-#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
+#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
 		case PHY_INTERFACE_MODE_SGMII:
 			/* T1040RDB & T1040D4RDB only supports SGMII on
 			 * DTSEC3
@@ -52,7 +52,7 @@ int board_eth_init(bd_t *bis)
 						CONFIG_SYS_SGMII1_PHY_ADDR);
 			break;
 #endif
-#ifdef CONFIG_T1042RDB
+#ifdef CONFIG_TARGET_T1042RDB
 		case PHY_INTERFACE_MODE_SGMII:
 			/* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
 			if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
@@ -62,7 +62,7 @@ int board_eth_init(bd_t *bis)
 						CONFIG_SYS_SGMII1_PHY_ADDR);
 			break;
 #endif
-#ifdef CONFIG_T1042D4RDB
+#ifdef CONFIG_TARGET_T1042D4RDB
 		case PHY_INTERFACE_MODE_SGMII:
 			/* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
 			 *  & DTSEC3
diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c
index 2362d43..c847df1 100644
--- a/board/freescale/t104xrdb/law.c
+++ b/board/freescale/t104xrdb/law.c
@@ -9,7 +9,7 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
 #endif
 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index 4b35af6..2e43307 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -13,6 +13,7 @@
 #include <fsl_esdhc.h>
 #include <spi_flash.h>
 #include "../common/sleep.h"
+#include "../common/spl.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -94,7 +95,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
 	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
-	probecpu();
+	arch_cpu_init();
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
@@ -114,8 +115,8 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 			   (uchar *)CONFIG_ENV_ADDR);
 #endif
 #ifdef CONFIG_SPL_SPI_BOOT
-	spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			   (uchar *)CONFIG_ENV_ADDR);
+	fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			       (uchar *)CONFIG_ENV_ADDR);
 #endif
 	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
 	gd->env_valid = 1;
@@ -124,12 +125,12 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	puts("\n\n");
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
 #elif defined(CONFIG_SPL_SPI_BOOT)
-	spi_boot();
+	fsl_spi_boot();
 #elif defined(CONFIG_SPL_NAND_BOOT)
 	nand_boot();
 #endif
diff --git a/board/freescale/t104xrdb/t1040_rcw.cfg b/board/freescale/t104xrdb/t1040_nand_rcw.cfg
index 3300c18..3300c18 100644
--- a/board/freescale/t104xrdb/t1040_rcw.cfg
+++ b/board/freescale/t104xrdb/t1040_nand_rcw.cfg
diff --git a/board/freescale/t104xrdb/t1040_sd_rcw.cfg b/board/freescale/t104xrdb/t1040_sd_rcw.cfg
new file mode 100644
index 0000000..fd3e8c5
--- /dev/null
+++ b/board/freescale/t104xrdb/t1040_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 80000002 68106000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1040_spi_rcw.cfg b/board/freescale/t104xrdb/t1040_spi_rcw.cfg
new file mode 100644
index 0000000..fccde5e
--- /dev/null
+++ b/board/freescale/t104xrdb/t1040_spi_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 80000002 58106000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1040d4_rcw.cfg b/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
index c1034b3..c1034b3 100644
--- a/board/freescale/t104xrdb/t1040d4_rcw.cfg
+++ b/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
diff --git a/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg b/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
new file mode 100644
index 0000000..e6f7585
--- /dev/null
+++ b/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 40000002 6c027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342580f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg b/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
new file mode 100644
index 0000000..cde862d
--- /dev/null
+++ b/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 40000002 5c027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342580f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042_rcw.cfg b/board/freescale/t104xrdb/t1042_nand_rcw.cfg
index db4d52f..db4d52f 100644
--- a/board/freescale/t104xrdb/t1042_rcw.cfg
+++ b/board/freescale/t104xrdb/t1042_nand_rcw.cfg
diff --git a/board/freescale/t104xrdb/t1042_pi_rcw.cfg b/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
index 57de89a..57de89a 100644
--- a/board/freescale/t104xrdb/t1042_pi_rcw.cfg
+++ b/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
diff --git a/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg b/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
new file mode 100644
index 0000000..bbce9a3
--- /dev/null
+++ b/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x06
+0c18000e 0e000000 00000000 00000000
+06000002 00400002 68106000 01000000
+00000000 00000000 00000000 00030810
+00000000 01fe0a06 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg b/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
new file mode 100644
index 0000000..b1d8b4c
--- /dev/null
+++ b/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x06
+0c18000e 0e000000 00000000 00000000
+06000002 00400002 58106000 01000000
+00000000 00000000 00000000 00030810
+00000000 01fe0a06 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042_sd_rcw.cfg b/board/freescale/t104xrdb/t1042_sd_rcw.cfg
new file mode 100644
index 0000000..d77bf18
--- /dev/null
+++ b/board/freescale/t104xrdb/t1042_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 80000002 6c027000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042_spi_rcw.cfg b/board/freescale/t104xrdb/t1042_spi_rcw.cfg
new file mode 100644
index 0000000..e8a3ad1
--- /dev/null
+++ b/board/freescale/t104xrdb/t1042_spi_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 80000002 5c027000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042d4_rcw.cfg b/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
index 9e0ee27..9e0ee27 100644
--- a/board/freescale/t104xrdb/t1042d4_rcw.cfg
+++ b/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
diff --git a/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg b/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
new file mode 100644
index 0000000..9d9046d
--- /dev/null
+++ b/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 40000002 6c027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg b/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
new file mode 100644
index 0000000..f1ec989
--- /dev/null
+++ b/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 40000002 5c027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index ec97677..d4c3d4d 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -29,7 +29,7 @@ int checkboard(void)
 	struct cpu_type *cpu = gd->arch.cpu;
 	u8 sw;
 
-#ifdef CONFIG_T104XD4RDB
+#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
 	printf("Board: %sD4RDB\n", cpu->name);
 #else
 	printf("Board: %sRDB\n", cpu->name);
@@ -105,7 +105,7 @@ int misc_init_r(void)
 		CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
 					 MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
 
-#if defined(CONFIG_T1040D4RDB)
+#if defined(CONFIG_TARGET_T1040D4RDB)
 	if (hwconfig("qe-tdm")) {
 		CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
 			   MISC_MUX_QE_TDM);
@@ -144,7 +144,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_liodn(blob);
 
 #ifdef CONFIG_HAS_FSL_DR_USB
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/board/freescale/t208xqds/Kconfig b/board/freescale/t208xqds/Kconfig
index 4e329dd..5a435c2 100644
--- a/board/freescale/t208xqds/Kconfig
+++ b/board/freescale/t208xqds/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_T208XQDS
+if TARGET_T2080QDS || TARGET_T2081QDS
 
 config SYS_BOARD
 	default "t208xqds"
@@ -9,4 +9,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "T208xQDS"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile
index ef04a26..587903a 100644
--- a/board/freescale/t208xqds/Makefile
+++ b/board/freescale/t208xqds/Makefile
@@ -7,8 +7,8 @@
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
 else
-obj-$(CONFIG_T2080QDS) += t208xqds.o eth_t208xqds.o
-obj-$(CONFIG_T2081QDS) += t208xqds.o eth_t208xqds.o
+obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o
+obj-$(CONFIG_TARGET_T2081QDS) += t208xqds.o eth_t208xqds.o
 obj-$(CONFIG_PCI)      += pci.o
 endif
 
diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c
index f96470f..ba65049 100644
--- a/board/freescale/t208xqds/ddr.c
+++ b/board/freescale/t208xqds/ddr.c
@@ -99,9 +99,12 @@ found:
 	/* DHC_EN =1, ODT = 75 Ohm */
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x64;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -115,5 +118,7 @@ phys_size_t initdram(int board_type)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index e92b5d3..c880294 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -32,13 +32,13 @@
 #define EMI1_RGMII1	0
 #define EMI1_RGMII2     1
 #define EMI1_SLOT1	2
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
 #define EMI1_SLOT2	6
 #define EMI1_SLOT3	3
 #define EMI1_SLOT4	4
 #define EMI1_SLOT5	5
 #define EMI2            7
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
 #define EMI1_SLOT2      3
 #define EMI1_SLOT3      4
 #define EMI1_SLOT5      5
@@ -59,7 +59,7 @@
 static int mdio_mux[NUM_FM_PORTS];
 
 static const char * const mdio_names[] = {
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
 	"T2080QDS_MDIO_RGMII1",
 	"T2080QDS_MDIO_RGMII2",
 	"T2080QDS_MDIO_SLOT1",
@@ -68,7 +68,7 @@ static const char * const mdio_names[] = {
 	"T2080QDS_MDIO_SLOT5",
 	"T2080QDS_MDIO_SLOT2",
 	"T2080QDS_MDIO_10GC",
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
 	"T2081QDS_MDIO_RGMII1",
 	"T2081QDS_MDIO_RGMII2",
 	"T2081QDS_MDIO_SLOT1",
@@ -82,9 +82,9 @@ static const char * const mdio_names[] = {
 };
 
 /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
 static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
 static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
 #endif
 
@@ -204,7 +204,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 	int off;
 
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_T2080QDS
+#ifdef CONFIG_TARGET_T2080QDS
 	serdes_corenet_t *srds_regs =
 		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 	u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
@@ -217,7 +217,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
 		phy = fm_info_get_phy_address(port);
 		switch (port) {
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
 		case FM1_DTSEC1:
 			if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
 				media_type = 1;
@@ -311,7 +311,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 				fdt_status_okay_by_alias(fdt, "emi1_slot2");
 			}
 			break;
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
 		case FM1_DTSEC1:
 		case FM1_DTSEC2:
 		case FM1_DTSEC5:
@@ -454,7 +454,7 @@ static void initialize_lane_to_slot(void)
 	srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 
 	switch (srds_s1) {
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
 	case 0x51:
 	case 0x5f:
 	case 0x65:
@@ -481,7 +481,7 @@ static void initialize_lane_to_slot(void)
 		lane_to_slot[6] = 3;
 		lane_to_slot[7] = 3;
 		break;
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
 	case 0x6b:
 		lane_to_slot[4] = 1;
 		lane_to_slot[5] = 3;
@@ -552,11 +552,11 @@ int board_eth_init(bd_t *bis)
 	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
 	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
 	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
 	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 #endif
 	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
-#if defined(CONFIG_T2081QDS)
+#if defined(CONFIG_TARGET_T2081QDS)
 	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
 	t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
 #endif
@@ -663,7 +663,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 		break;
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
 	case 0xd9:
 	case 0xd3:
 	case 0xcb:
@@ -675,7 +675,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
 		break;
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
 	case 0xca:
 	case 0xcb:
 		/* SGMII in Slot3 */
@@ -731,7 +731,7 @@ int board_eth_init(bd_t *bis)
 				fm_info_set_mdio(i, mii_dev_for_muxval(
 						 mdio_mux[i]));
 				break;
-#if defined(CONFIG_T2081QDS)
+#if defined(CONFIG_TARGET_T2081QDS)
 			case 5:
 				mdio_mux[i] = EMI1_SLOT5;
 				fm_info_set_mdio(i, mii_dev_for_muxval(
diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
index bb02dab..d7d716b 100644
--- a/board/freescale/t208xqds/spl.c
+++ b/board/freescale/t208xqds/spl.c
@@ -14,6 +14,7 @@
 #include <spi_flash.h>
 #include "../common/qixis.h"
 #include "t208xqds_qixis.h"
+#include "../common/spl.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -102,7 +103,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
 	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
-	probecpu();
+	arch_cpu_init();
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
@@ -118,8 +119,8 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 			   (uchar *)CONFIG_ENV_ADDR);
 #endif
 #ifdef CONFIG_SPL_SPI_BOOT
-	spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			   (uchar *)CONFIG_ENV_ADDR);
+	fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			       (uchar *)CONFIG_ENV_ADDR);
 #endif
 
 	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
@@ -127,12 +128,12 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
 #elif defined(CONFIG_SPL_SPI_BOOT)
-	spi_boot();
+	fsl_spi_boot();
 #elif defined(CONFIG_SPL_NAND_BOOT)
 	nand_boot();
 #endif
diff --git a/board/freescale/t208xqds/t2080_rcw.cfg b/board/freescale/t208xqds/t2080_nand_rcw.cfg
index 52a1652..52a1652 100644
--- a/board/freescale/t208xqds/t2080_rcw.cfg
+++ b/board/freescale/t208xqds/t2080_nand_rcw.cfg
diff --git a/board/freescale/t208xqds/t2080_sd_rcw.cfg b/board/freescale/t208xqds/t2080_sd_rcw.cfg
new file mode 100644
index 0000000..73f53fa
--- /dev/null
+++ b/board/freescale/t208xqds/t2080_sd_rcw.cfg
@@ -0,0 +1,16 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
+#12100017 15000000 00000000 00000000
+#66150002 00008400 e8104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
+0c070012 0e000000 00000000 00000000
+66150002 00000000 68104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2080_spi_rcw.cfg b/board/freescale/t208xqds/t2080_spi_rcw.cfg
new file mode 100644
index 0000000..8474c8e
--- /dev/null
+++ b/board/freescale/t208xqds/t2080_spi_rcw.cfg
@@ -0,0 +1,16 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
+#12100017 15000000 00000000 00000000
+#66150002 00008400 e8104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
+0c070012 0e000000 00000000 00000000
+66150002 00000000 58104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2081_rcw.cfg b/board/freescale/t208xqds/t2081_nand_rcw.cfg
index a2d5ecf..a2d5ecf 100644
--- a/board/freescale/t208xqds/t2081_rcw.cfg
+++ b/board/freescale/t208xqds/t2081_nand_rcw.cfg
diff --git a/board/freescale/t208xqds/t2081_sd_rcw.cfg b/board/freescale/t208xqds/t2081_sd_rcw.cfg
new file mode 100644
index 0000000..daced67
--- /dev/null
+++ b/board/freescale/t208xqds/t2081_sd_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#Default SerDes Protocol: 0x6C
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+6c000002 00008000 68104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t2081_spi_rcw.cfg b/board/freescale/t208xqds/t2081_spi_rcw.cfg
new file mode 100644
index 0000000..79ba1f1
--- /dev/null
+++ b/board/freescale/t208xqds/t2081_spi_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#Default SerDes Protocol: 0x6C
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+6c000002 00008000 58104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t208x_pbi.cfg b/board/freescale/t208xqds/t208x_pbi.cfg
index e200d92..43be8a8 100644
--- a/board/freescale/t208xqds/t208x_pbi.cfg
+++ b/board/freescale/t208xqds/t208x_pbi.cfg
@@ -37,5 +37,4 @@
 09000014 ff000000
 09000018 81000000
 #Flush PBL data
-09138000 00000000
-091380c0 00000000
+091380c0 00100000
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
index bfea3a1..26093ea 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -99,7 +99,7 @@ int brd_mux_lane_to_slot(void)
 	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
 				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
 	u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
@@ -109,7 +109,7 @@ int brd_mux_lane_to_slot(void)
 	case 0:
 		/* SerDes1 is not enabled */
 		break;
-#if defined(CONFIG_T2080QDS)
+#if defined(CONFIG_TARGET_T2080QDS)
 	case 0x1b:
 	case 0x1c:
 	case 0xa2:
@@ -191,7 +191,7 @@ int brd_mux_lane_to_slot(void)
 		 */
 		 QIXIS_WRITE(brdcfg[12], 0x1a);
 		 break;
-#elif defined(CONFIG_T2081QDS)
+#elif defined(CONFIG_TARGET_T2081QDS)
 	case 0x50:
 	case 0x51:
 		/* SD1(A:D) => SLOT2 XAUI
@@ -268,7 +268,7 @@ int brd_mux_lane_to_slot(void)
 		return -1;
 	}
 
-#ifdef CONFIG_T2080QDS
+#ifdef CONFIG_TARGET_T2080QDS
 	switch (srds_prtcl_s2) {
 	case 0:
 		/* SerDes2 is not enabled */
@@ -461,7 +461,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 #endif
 
 	fdt_fixup_liodn(blob);
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_ethernet(blob);
diff --git a/board/freescale/t208xrdb/Kconfig b/board/freescale/t208xrdb/Kconfig
index 845af3d..6f0b012 100644
--- a/board/freescale/t208xrdb/Kconfig
+++ b/board/freescale/t208xrdb/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_T208XRDB
+if TARGET_T2080RDB
 
 config SYS_BOARD
 	default "t208xrdb"
@@ -9,4 +9,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "T208xRDB"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile
index cd8fe09..25ea66a 100644
--- a/board/freescale/t208xrdb/Makefile
+++ b/board/freescale/t208xrdb/Makefile
@@ -7,7 +7,7 @@
 ifdef CONFIG_SPL_BUILD
 obj-y	+= spl.o
 else
-obj-$(CONFIG_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
+obj-$(CONFIG_TARGET_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
 obj-$(CONFIG_PCI)      += pci.o
 endif
 
diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c
index f6c8ca3..50dc69a 100644
--- a/board/freescale/t208xrdb/ddr.c
+++ b/board/freescale/t208xrdb/ddr.c
@@ -92,9 +92,12 @@ found:
 	/* DHC_EN =1, ODT = 75 Ohm */
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x54;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -108,5 +111,7 @@ phys_size_t initdram(int board_type)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
index 2ff05a2..b431401 100644
--- a/board/freescale/t208xrdb/spl.c
+++ b/board/freescale/t208xrdb/spl.c
@@ -12,6 +12,7 @@
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <spi_flash.h>
+#include "../common/spl.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -72,7 +73,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
 	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
-	probecpu();
+	arch_cpu_init();
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
@@ -88,8 +89,8 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 			   (uchar *)CONFIG_ENV_ADDR);
 #endif
 #ifdef CONFIG_SPL_SPI_BOOT
-	spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
-			   (uchar *)CONFIG_ENV_ADDR);
+	fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			       (uchar *)CONFIG_ENV_ADDR);
 #endif
 
 	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
@@ -97,12 +98,12 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
 #elif defined(CONFIG_SPL_SPI_BOOT)
-	spi_boot();
+	fsl_spi_boot();
 #elif defined(CONFIG_SPL_NAND_BOOT)
 	nand_boot();
 #endif
diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg b/board/freescale/t208xrdb/t2080_nand_rcw.cfg
index 8096ff9..8096ff9 100644
--- a/board/freescale/t208xrdb/t2080_rcw.cfg
+++ b/board/freescale/t208xrdb/t2080_nand_rcw.cfg
diff --git a/board/freescale/t208xrdb/t2080_pbi.cfg b/board/freescale/t208xrdb/t2080_pbi.cfg
index e200d92..43be8a8 100644
--- a/board/freescale/t208xrdb/t2080_pbi.cfg
+++ b/board/freescale/t208xrdb/t2080_pbi.cfg
@@ -37,5 +37,4 @@
 09000014 ff000000
 09000018 81000000
 #Flush PBL data
-09138000 00000000
-091380c0 00000000
+091380c0 00100000
diff --git a/board/freescale/t208xrdb/t2080_sd_rcw.cfg b/board/freescale/t208xrdb/t2080_sd_rcw.cfg
new file mode 100644
index 0000000..6309b1d
--- /dev/null
+++ b/board/freescale/t208xrdb/t2080_sd_rcw.cfg
@@ -0,0 +1,19 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
+#120c0017 15000000 00000000 00000000
+#66150002 00008400 ec104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
+#1206001b 15000000 00000000 00000000
+
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
+1207001b 15000000 00000000 00000000
+66150002 00000000 68104000 c1000000
+00800000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xrdb/t2080_spi_rcw.cfg b/board/freescale/t208xrdb/t2080_spi_rcw.cfg
new file mode 100644
index 0000000..f167495
--- /dev/null
+++ b/board/freescale/t208xrdb/t2080_spi_rcw.cfg
@@ -0,0 +1,19 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+
+#For T2080 v1.0
+#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
+#120c0017 15000000 00000000 00000000
+#66150002 00008400 ec104000 c1000000
+#00000000 00000000 00000000 000307fc
+#00000000 00000000 00000000 00000004
+
+#For T2080 v1.1
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
+#1206001b 15000000 00000000 00000000
+
+#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
+1207001b 15000000 00000000 00000000
+66150002 00000000 58104000 c1000000
+00800000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index 0cb05aa..1ab05ec 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -128,7 +128,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 #endif
 
 	fdt_fixup_liodn(blob);
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_ethernet(blob);
diff --git a/board/freescale/t4qds/Kconfig b/board/freescale/t4qds/Kconfig
index 27a64b6..f7c1a0c 100644
--- a/board/freescale/t4qds/Kconfig
+++ b/board/freescale/t4qds/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_T4240QDS
+if TARGET_T4160QDS || TARGET_T4240QDS
 
 config SYS_BOARD
 	default "t4qds"
@@ -9,4 +9,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "T4240QDS"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile
index 731ccb0..1eacbcc 100644
--- a/board/freescale/t4qds/Makefile
+++ b/board/freescale/t4qds/Makefile
@@ -7,7 +7,8 @@
 ifdef CONFIG_SPL_BUILD
 obj-y	+= spl.o
 else
-obj-$(CONFIG_T4240QDS)	+= t4240qds.o eth.o
+obj-$(CONFIG_TARGET_T4160QDS)	+= t4240qds.o eth.o
+obj-$(CONFIG_TARGET_T4240QDS)	+= t4240qds.o eth.o
 obj-$(CONFIG_PCI)	+= pci.o
 endif
 
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index d533924..7408970 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -107,9 +107,12 @@ found:
 	/* DHC_EN =1, ODT = 75 Ohm */
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x63;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -124,5 +127,7 @@ phys_size_t initdram(int board_type)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c
index 6ca0f03..9ecdaed 100644
--- a/board/freescale/t4qds/spl.c
+++ b/board/freescale/t4qds/spl.c
@@ -112,7 +112,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
 	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
-	probecpu();
+	arch_cpu_init();
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
@@ -133,7 +133,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_boot();
diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c
index f1393f2..35ad19e 100644
--- a/board/freescale/t4qds/t4240emu.c
+++ b/board/freescale/t4qds/t4240emu.c
@@ -76,7 +76,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
 	fdt_fixup_liodn(blob);
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 
 	return 0;
 }
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index d6df144..8f9e7e8 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -694,7 +694,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 #endif
 
 	fdt_fixup_liodn(blob);
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_ethernet(blob);
diff --git a/board/freescale/t4qds/t4_nand_rcw.cfg b/board/freescale/t4qds/t4_nand_rcw.cfg
new file mode 100644
index 0000000..9386be0
--- /dev/null
+++ b/board/freescale/t4qds/t4_nand_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#serdes protocol  1_27_5_11
+1607001b 18101b16 00000000 00000000
+04362858 30548c00 e8020000 f5000000
+00000000 ee0000ee 00000000 000307fc
+00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/freescale/t4qds/t4_pbi.cfg
index 6126266..8d46003 100644
--- a/board/freescale/t4qds/t4_pbi.cfg
+++ b/board/freescale/t4qds/t4_pbi.cfg
@@ -18,5 +18,4 @@
 09000014 ff000000
 09000018 81000000
 #Flush PBL data
-09138000 00000000
-091380c0 00000000
+091380c0 00100000
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
deleted file mode 100644
index 267494c..0000000
--- a/board/freescale/t4qds/t4_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#serdes protocol  1_27_5_11
-1607001b 18101b16 00000000 00000000
-04362858 30548c00 ec020000 f5000000
-00000000 ee0000ee 00000000 000307fc
-00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4qds/t4_sd_rcw.cfg b/board/freescale/t4qds/t4_sd_rcw.cfg
new file mode 100644
index 0000000..54beb67
--- /dev/null
+++ b/board/freescale/t4qds/t4_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#serdes protocol  1_27_5_11
+1607001b 18101b16 00000000 00000000
+04362858 30548c00 68020000 f5000000
+00000000 ee0000ee 00000000 000307fc
+00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig
index d93e453..a94a57e 100644
--- a/board/freescale/t4rdb/Kconfig
+++ b/board/freescale/t4rdb/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_T4240RDB
+if TARGET_T4160RDB || TARGET_T4240RDB
 
 config SYS_BOARD
 	default "t4rdb"
@@ -9,4 +9,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "T4240RDB"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
index 4f29eea..209983a 100644
--- a/board/freescale/t4rdb/Makefile
+++ b/board/freescale/t4rdb/Makefile
@@ -7,7 +7,8 @@
 ifdef CONFIG_SPL_BUILD
 obj-y	+= spl.o
 else
-obj-$(CONFIG_T4240RDB)	+= t4240rdb.o
+obj-$(CONFIG_TARGET_T4160RDB)	+= t4240rdb.o
+obj-$(CONFIG_TARGET_T4240RDB)	+= t4240rdb.o
 obj-y			+= cpld.o
 obj-y			+= eth.o
 obj-$(CONFIG_PCI)	+= pci.o
diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c
index 230f031..8415527 100644
--- a/board/freescale/t4rdb/ddr.c
+++ b/board/freescale/t4rdb/ddr.c
@@ -100,9 +100,12 @@ found:
 	/* DHC_EN =1, ODT = 75 Ohm */
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x64;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -117,5 +120,7 @@ phys_size_t initdram(int board_type)
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
index b148a7f..5feab1c 100644
--- a/board/freescale/t4rdb/spl.c
+++ b/board/freescale/t4rdb/spl.c
@@ -76,7 +76,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
 	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
-	probecpu();
+	arch_cpu_init();
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
@@ -91,7 +91,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 	i2c_init_all();
 
-	gd->ram_size = initdram(0);
+	dram_init();
 
 	mmc_boot();
 }
diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c
index 406fb13..bdd6f4e 100644
--- a/board/freescale/t4rdb/t4240rdb.c
+++ b/board/freescale/t4rdb/t4240rdb.c
@@ -107,7 +107,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 #endif
 
 	fdt_fixup_liodn(blob);
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_ethernet(blob);
diff --git a/board/freescale/t4rdb/t4_pbi.cfg b/board/freescale/t4rdb/t4_pbi.cfg
index e7bb673..0b326fa 100644
--- a/board/freescale/t4rdb/t4_pbi.cfg
+++ b/board/freescale/t4rdb/t4_pbi.cfg
@@ -24,5 +24,4 @@
 09000014 ff000000
 09000018 81000000
 #Flush PBL data
-09138000 00000000
-091380c0 00000000
+091380c0 00100000
diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg
deleted file mode 100644
index 282fea4..0000000
--- a/board/freescale/t4rdb/t4_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 010e0100
-#serdes protocol  27_55_1_9
-16070019 18101916 00000000 00000000
-6c6e0848 00448c00 ec020000 f5000000
-00000000 ee0000ee 00000000 000307fc
-00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4rdb/t4_sd_rcw.cfg b/board/freescale/t4rdb/t4_sd_rcw.cfg
new file mode 100644
index 0000000..cc2bff6
--- /dev/null
+++ b/board/freescale/t4rdb/t4_sd_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#serdes protocol  27_55_1_9
+16070019 18101916 00000000 00000000
+6c6e0848 00448c00 6c020000 f5000000
+00000000 ee0000ee 00000000 000307fc
+00000000 00000000 00000000 00000028
diff --git a/board/freescale/vf610twr/Kconfig b/board/freescale/vf610twr/Kconfig
index ef091d6..3b90ed6 100644
--- a/board/freescale/vf610twr/Kconfig
+++ b/board/freescale/vf610twr/Kconfig
@@ -6,9 +6,6 @@ config SYS_BOARD
 config SYS_VENDOR
 	default "freescale"
 
-config SYS_SOC
-	default "vf610"
-
 config SYS_CONFIG_NAME
 	default "vf610twr"
 
diff --git a/board/freescale/vf610twr/imximage.cfg b/board/freescale/vf610twr/imximage.cfg
index 9c823c4..70157ed 100644
--- a/board/freescale/vf610twr/imximage.cfg
+++ b/board/freescale/vf610twr/imximage.cfg
@@ -3,12 +3,12 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
  */
-#include <asm/imx-common/imximage.cfg>
+#include <asm/mach-imx/imximage.cfg>
 
 /* image version */
 IMAGE_VERSION	2
diff --git a/board/gaisler/gr_cpci_ax2000/Kconfig b/board/gaisler/gr_cpci_ax2000/Kconfig
deleted file mode 100644
index c12a002..0000000
--- a/board/gaisler/gr_cpci_ax2000/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_GR_CPCI_AX2000
-
-config SYS_BOARD
-	default "gr_cpci_ax2000"
-
-config SYS_CONFIG_NAME
-	default "gr_cpci_ax2000"
-
-endif
diff --git a/board/gaisler/gr_cpci_ax2000/MAINTAINERS b/board/gaisler/gr_cpci_ax2000/MAINTAINERS
deleted file mode 100644
index df55a4c..0000000
--- a/board/gaisler/gr_cpci_ax2000/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-GR_CPCI_AX2000 BOARD
-#M:	-
-S:	Maintained
-F:	board/gaisler/gr_cpci_ax2000/
-F:	include/configs/gr_cpci_ax2000.h
-F:	configs/gr_cpci_ax2000_defconfig
diff --git a/board/gaisler/gr_cpci_ax2000/Makefile b/board/gaisler/gr_cpci_ax2000/Makefile
deleted file mode 100644
index a08e04d..0000000
--- a/board/gaisler/gr_cpci_ax2000/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= gr_cpci_ax2000.o
diff --git a/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c b/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c
deleted file mode 100644
index d26212e..0000000
--- a/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2008
- * Daniel Hellstrom, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <config.h>
-#include <asm/leon.h>
-
-phys_size_t initdram(int board_type)
-{
-	return 1;
-}
-
-int checkboard(void)
-{
-	puts("Board: GR-CPCI-AX2000\n");
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC91111
-	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/board/gaisler/gr_ep2s60/Kconfig b/board/gaisler/gr_ep2s60/Kconfig
deleted file mode 100644
index f49937c..0000000
--- a/board/gaisler/gr_ep2s60/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_GR_EP2S60
-
-config SYS_BOARD
-	default "gr_ep2s60"
-
-config SYS_CONFIG_NAME
-	default "gr_ep2s60"
-
-endif
diff --git a/board/gaisler/gr_ep2s60/MAINTAINERS b/board/gaisler/gr_ep2s60/MAINTAINERS
deleted file mode 100644
index 7acd5f4..0000000
--- a/board/gaisler/gr_ep2s60/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-GR_EP2S60 BOARD
-#M:	-
-S:	Maintained
-F:	board/gaisler/gr_ep2s60/
-F:	include/configs/gr_ep2s60.h
-F:	configs/gr_ep2s60_defconfig
diff --git a/board/gaisler/gr_ep2s60/Makefile b/board/gaisler/gr_ep2s60/Makefile
deleted file mode 100644
index 059a9c0..0000000
--- a/board/gaisler/gr_ep2s60/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= gr_ep2s60.o
diff --git a/board/gaisler/gr_ep2s60/gr_ep2s60.c b/board/gaisler/gr_ep2s60/gr_ep2s60.c
deleted file mode 100644
index 98fb45f..0000000
--- a/board/gaisler/gr_ep2s60/gr_ep2s60.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2008
- * Daniel Hellstrom, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <config.h>
-#include <asm/leon.h>
-
-phys_size_t initdram(int board_type)
-{
-	return 1;
-}
-
-int checkboard(void)
-{
-	puts("Board: EP2S60 GRLIB\n");
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC91111
-	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/board/gaisler/gr_xc3s_1500/Kconfig b/board/gaisler/gr_xc3s_1500/Kconfig
deleted file mode 100644
index e695ba2..0000000
--- a/board/gaisler/gr_xc3s_1500/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_GR_XC3S_1500
-
-config SYS_BOARD
-	default "gr_xc3s_1500"
-
-config SYS_CONFIG_NAME
-	default "gr_xc3s_1500"
-
-endif
diff --git a/board/gaisler/gr_xc3s_1500/MAINTAINERS b/board/gaisler/gr_xc3s_1500/MAINTAINERS
deleted file mode 100644
index c4179d2..0000000
--- a/board/gaisler/gr_xc3s_1500/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-GR_XC3S_1500 BOARD
-#M:	-
-S:	Maintained
-F:	board/gaisler/gr_xc3s_1500/
-F:	include/configs/gr_xc3s_1500.h
-F:	configs/gr_xc3s_1500_defconfig
diff --git a/board/gaisler/gr_xc3s_1500/Makefile b/board/gaisler/gr_xc3s_1500/Makefile
deleted file mode 100644
index 302c461..0000000
--- a/board/gaisler/gr_xc3s_1500/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= gr_xc3s_1500.o
diff --git a/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c b/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c
deleted file mode 100644
index 32fbbe2..0000000
--- a/board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * (C) Copyright 2007
- * Daniel Hellstrom, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/leon.h>
-
-phys_size_t initdram(int board_type)
-{
-	return 1;
-}
-
-int checkboard(void)
-{
-	puts("Board: GR-XC3S-1500\n");
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	return 0;
-}
diff --git a/board/gaisler/grsim/Kconfig b/board/gaisler/grsim/Kconfig
deleted file mode 100644
index 18598d3..0000000
--- a/board/gaisler/grsim/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_GRSIM
-
-config SYS_BOARD
-	default "grsim"
-
-config SYS_CONFIG_NAME
-	default "grsim"
-
-endif
diff --git a/board/gaisler/grsim/MAINTAINERS b/board/gaisler/grsim/MAINTAINERS
deleted file mode 100644
index 4b3312e..0000000
--- a/board/gaisler/grsim/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-GRSIM BOARD
-#M:	-
-S:	Maintained
-F:	board/gaisler/grsim/
-F:	include/configs/grsim.h
-F:	configs/grsim_defconfig
diff --git a/board/gaisler/grsim/Makefile b/board/gaisler/grsim/Makefile
deleted file mode 100644
index 4c93bda..0000000
--- a/board/gaisler/grsim/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= grsim.o
diff --git a/board/gaisler/grsim/grsim.c b/board/gaisler/grsim/grsim.c
deleted file mode 100644
index fd73920..0000000
--- a/board/gaisler/grsim/grsim.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * GRSIM/TSIM board
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/leon.h>
-
-phys_size_t initdram(int board_type)
-{
-	return 1;
-}
-
-int checkboard(void)
-{
-	puts("Board: GRSIM/TSIM\n");
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	return 0;
-}
diff --git a/board/gaisler/grsim_leon2/Kconfig b/board/gaisler/grsim_leon2/Kconfig
deleted file mode 100644
index 0d21a0a..0000000
--- a/board/gaisler/grsim_leon2/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_GRSIM_LEON2
-
-config SYS_BOARD
-	default "grsim_leon2"
-
-config SYS_CONFIG_NAME
-	default "grsim_leon2"
-
-endif
diff --git a/board/gaisler/grsim_leon2/MAINTAINERS b/board/gaisler/grsim_leon2/MAINTAINERS
deleted file mode 100644
index bf4a950..0000000
--- a/board/gaisler/grsim_leon2/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-GRSIM_LEON2 BOARD
-#M:	-
-S:	Maintained
-F:	board/gaisler/grsim_leon2/
-F:	include/configs/grsim_leon2.h
-F:	configs/grsim_leon2_defconfig
diff --git a/board/gaisler/grsim_leon2/Makefile b/board/gaisler/grsim_leon2/Makefile
deleted file mode 100644
index 5468305..0000000
--- a/board/gaisler/grsim_leon2/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= grsim_leon2.o
diff --git a/board/gaisler/grsim_leon2/grsim_leon2.c b/board/gaisler/grsim_leon2/grsim_leon2.c
deleted file mode 100644
index 882b0a4..0000000
--- a/board/gaisler/grsim_leon2/grsim_leon2.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * GRSIM/TSIM board
- *
- * (C) Copyright 2007
- * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/leon.h>
-
-phys_size_t initdram(int board_type)
-{
-	return 1;
-}
-
-int checkboard(void)
-{
-	puts("Board: GRSIM/TSIM LEON2\n");
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	return 0;
-}
diff --git a/board/gateworks/gw_ventana/Kconfig b/board/gateworks/gw_ventana/Kconfig
index ccce98e..5d1bae4 100644
--- a/board/gateworks/gw_ventana/Kconfig
+++ b/board/gateworks/gw_ventana/Kconfig
@@ -9,4 +9,17 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "gw_ventana"
 
+config CMD_EECONFIG
+	bool "Enable the 'econfig' command"
+	help
+	  Provides access to EEPROM configuration on Gateworks Ventana
+
+config CMD_GSC
+	bool "Enable the 'gsc' command"
+	help
+	  Provides access to the GSC configuration:
+
+	     gsc sleep - sleeps for a period of seconds
+	     gsc wd - enables / disables the watchdog
+
 endif
diff --git a/board/gateworks/gw_ventana/MAINTAINERS b/board/gateworks/gw_ventana/MAINTAINERS
index b44fb4d..265ddac 100644
--- a/board/gateworks/gw_ventana/MAINTAINERS
+++ b/board/gateworks/gw_ventana/MAINTAINERS
@@ -3,4 +3,6 @@ M:	Tim Harvey <tharvey@gateworks.com>
 S:	Maintained
 F:	board/gateworks/gw_ventana/
 F:	include/configs/gw_ventana.h
-F:	configs/gwventana_defconfig
+F:	configs/gwventana_nand_defconfig
+F:	configs/gwventana_emmc_defconfig
+F:	configs/gwventana_gw5904_defconfig
diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README
index f3f8998..57c64a1 100644
--- a/board/gateworks/gw_ventana/README
+++ b/board/gateworks/gw_ventana/README
@@ -30,7 +30,12 @@ will build the following artifacts from U-Boot source:
 
 To build U-Boot for the Gateworks Ventana product family:
 
- make gwventana_config
+For NAND FLASH based boards:
+ make gwventana_nand_config
+ make
+
+For EMMC FLASH based boards:
+ make gwventana_emmc_config
  make
 
 
@@ -99,11 +104,11 @@ This information is taken from:
 
 More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
 
-3.1. boot from micro-SD
------------------------
+3.1. boot from MMC (eMMC/microSD)
+---------------------------------
 
 When the IMX6 eFUSE settings have been factory programmed to boot from
-micro-SD the SPL will be loaded from offset 0x400 (1KB). Once the SPL is
+MMC the SPL will be loaded from offset 0x400 (1KB). Once the SPL is
 booted, it will load and execute U-Boot (u-boot.img) from offset 69KB
 on the micro-SD (defined by CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR).
 
@@ -111,11 +116,11 @@ While it is technically possible to enable the SPL to be able to load
 U-Boot from a file on a FAT/EXT filesystem on the micro-SD, we chose to
 use raw micro-SD access to keep the code-size and boot time of the SPL down.
 
-For these reasons a micro-SD that will be used as an IMX6 primary boot
+For these reasons an MMC device that will be used as an IMX6 primary boot
 device must be carefully partitioned and prepared.
 
 The following shell commands are executed on a Linux host (adjust DEV to the
-block storage device of your micro-SD):
+block storage device of your MMC, ie /dev/mmcblk0):
 
  DEV=/dev/sdc
  # zero out 1MB of device
diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c
index 4065c56..46404b4 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -6,10 +6,12 @@
  * SPDX-License-Identifier: GPL-2.0+
  */
 
+#include <asm/arch/clock.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc.h>
 #include <hwconfig.h>
 #include <power/pmic.h>
 #include <power/ltc3676_pmic.h>
@@ -35,6 +37,55 @@ void setup_iomux_uart(void)
 	SETUP_IOMUX_PADS(uart2_pads);
 }
 
+/* MMC */
+static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+/* 4-bit microSD on SD2 */
+static iomux_v3_cfg_t const gw5904_mmc_pads[] = {
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	/* CD */
+	IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+/* 8-bit eMMC on SD2/NAND */
+static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = {
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
 /* I2C1: GSC */
 static struct i2c_pads_info mx6q_i2c_pad_info0 = {
 	.scl = {
@@ -129,39 +180,6 @@ void setup_ventana_i2c(void)
 /*
  * Baseboard specific GPIO
  */
-
-/* common to add baseboards */
-static iomux_v3_cfg_t const gw_gpio_pads[] = {
-	/* SD3_VSELECT */
-	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
-};
-
-/* prototype */
-static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
-	/* RS232_EN# */
-	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
-	/* PANLEDG# */
-	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
-	/* PANLEDR# */
-	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
-	/* LOCLED# */
-	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
-	/* RS485_EN */
-	IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
-	/* IOEXP_PWREN# */
-	IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
-	/* IOEXP_IRQ# */
-	IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
-	/* VID_EN */
-	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
-	/* DIOI2C_DIS# */
-	IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
-	/* PCICK_SSON */
-	IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
-	/* PCI_RST# */
-	IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
-};
-
 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 	/* PANLEDG# */
 	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
@@ -183,6 +201,8 @@ static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 };
 
 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
+	/* SD3_VSELECT */
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
 	/* RS232_EN# */
 	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 	/* MSATA_EN */
@@ -216,6 +236,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
 };
 
 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
+	/* SD3_VSELECT */
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
 	/* RS232_EN# */
 	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 	/* MSATA_EN */
@@ -249,6 +271,8 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 };
 
 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
+	/* SD3_VSELECT */
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
 	/* RS232_EN# */
 	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
 	/* MSATA_EN */
@@ -325,11 +349,12 @@ static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
 };
 
 static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
+	/* SD3_VSELECT */
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
 	/* PANLEDG# */
 	IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
 	/* PANLEDR# */
 	IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 | DIO_PAD_CFG),
-
 	/* VID_PWR */
 	IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
 	/* PCI_RST# */
@@ -338,6 +363,107 @@ static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
 	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
 };
 
+static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
+	/* RS232_EN# */
+	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
+	/* CAN_STBY */
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
+	/* USB_HUBRST# */
+	IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
+	/* PANLEDG# */
+	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+	/* PANLEDR# */
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* IOEXP_PWREN# */
+	IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+	/* IOEXP_IRQ# */
+	IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+	/* DIOI2C_DIS# */
+	IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
+	/* VID_EN */
+	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+	/* PCI_RST# */
+	IOMUX_PADS(PAD_DISP0_DAT10__GPIO4_IO31 | DIO_PAD_CFG),
+	/* RS485_EN */
+	IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
+	/* PCIESKT_WDIS# */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+	/* USBH2_PEN (OTG) */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* 12V0_PWR_EN */
+	IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
+	/* BKLT_12VEN */
+	IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
+	/* EMMY_PDN# */
+	IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | DIO_PAD_CFG),
+	/* EMMY_CFG1# */
+	IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
+	/* EMMY_CFG1# */
+	IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG),
+	/* USBH1_PEN (EHCI) */
+	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+	/* USBH2_PEN (OTG) */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* USBDPC_PEN */
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+	/* TOUCH_RST */
+	IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
+	/* AUDIO_RST# */
+	IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
+	/* UART1_TEN# */
+	IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG),
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
+	/* LVDS_BKLEN # */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
+	/* RGMII_PDWN# */
+	IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | DIO_PAD_CFG),
+	/* TOUCH_IRQ# */
+	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+	/* TOUCH_RST# */
+	IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
+};
+
+static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
+	/* USB_HUBRST# */
+	IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
+	/* PANLEDG# */
+	IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
+	/* PANLEDR# */
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
+	/* MX6_LOCLED# */
+	IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
+	/* IOEXP_PWREN# */
+	IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
+	/* IOEXP_IRQ# */
+	IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+	/* DIOI2C_DIS# */
+	IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
+	/* UART_RS485 */
+	IOMUX_PADS(PAD_DISP0_DAT2__GPIO4_IO23 | DIO_PAD_CFG),
+	/* UART_HALF */
+	IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | DIO_PAD_CFG),
+	/* SKT1_WDIS# */
+	IOMUX_PADS(PAD_DISP0_DAT17__GPIO5_IO11 | DIO_PAD_CFG),
+	/* SKT1_RST# */
+	IOMUX_PADS(PAD_DISP0_DAT18__GPIO5_IO12 | DIO_PAD_CFG),
+	/* SKT2_WDIS# */
+	IOMUX_PADS(PAD_DISP0_DAT19__GPIO5_IO13 | DIO_PAD_CFG),
+	/* SKT2_RST# */
+	IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+	/* M2_OFF# */
+	IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
+	/* M2_WDIS# */
+	IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
+	/* M2_RST# */
+	IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG),
+};
+
 /* Digital I/O */
 struct dio_cfg gw51xx_dio[] = {
 	{
@@ -552,6 +678,111 @@ struct dio_cfg gw553x_dio[] = {
 	},
 };
 
+struct dio_cfg gw560x_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+		IMX_GPIO_NR(1, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+		IMX_GPIO_NR(1, 20),
+		{ 0, 0 },
+		0
+	},
+};
+
+struct dio_cfg gw5903_dio[] = {
+};
+
+struct dio_cfg gw5904_dio[] = {
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+		IMX_GPIO_NR(1, 16),
+		{ 0, 0 },
+		0
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+		IMX_GPIO_NR(1, 19),
+		{ IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+		2
+	},
+	{
+		{ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+		IMX_GPIO_NR(1, 17),
+		{ IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+		3
+	},
+	{
+		{IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+		IMX_GPIO_NR(1, 20),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00) },
+		IMX_GPIO_NR(2, 0),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01) },
+		IMX_GPIO_NR(2, 1),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02) },
+		IMX_GPIO_NR(2, 2),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03) },
+		IMX_GPIO_NR(2, 3),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04) },
+		IMX_GPIO_NR(2, 4),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05) },
+		IMX_GPIO_NR(2, 5),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06) },
+		IMX_GPIO_NR(2, 6),
+		{ 0, 0 },
+		0
+	},
+	{
+		{IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07) },
+		IMX_GPIO_NR(2, 7),
+		{ 0, 0 },
+		0
+	},
+};
+
 /*
  * Board Specific GPIO
  */
@@ -573,6 +804,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.rs485en = IMX_GPIO_NR(3, 24),
 		.dioi2c_en = IMX_GPIO_NR(4,  5),
 		.pcie_sson = IMX_GPIO_NR(1, 20),
+		.otgpwr_en = IMX_GPIO_NR(3, 22),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
 	},
 
 	/* GW51xx */
@@ -591,6 +824,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.gps_shdn = IMX_GPIO_NR(1, 2),
 		.vidin_en = IMX_GPIO_NR(5, 20),
 		.wdis = IMX_GPIO_NR(7, 12),
+		.otgpwr_en = IMX_GPIO_NR(3, 22),
 	},
 
 	/* GW52xx */
@@ -613,6 +847,9 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.wdis = IMX_GPIO_NR(7, 12),
 		.msata_en = GP_MSATA_SEL,
 		.rs232_en = GP_RS232_EN,
+		.otgpwr_en = IMX_GPIO_NR(3, 22),
+		.vsel_pin = IMX_GPIO_NR(6, 14),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
 	},
 
 	/* GW53xx */
@@ -634,6 +871,9 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.wdis = IMX_GPIO_NR(7, 12),
 		.msata_en = GP_MSATA_SEL,
 		.rs232_en = GP_RS232_EN,
+		.otgpwr_en = IMX_GPIO_NR(3, 22),
+		.vsel_pin = IMX_GPIO_NR(6, 14),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
 	},
 
 	/* GW54xx */
@@ -657,6 +897,9 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.wdis = IMX_GPIO_NR(5, 17),
 		.msata_en = GP_MSATA_SEL,
 		.rs232_en = GP_RS232_EN,
+		.otgpwr_en = IMX_GPIO_NR(3, 22),
+		.vsel_pin = IMX_GPIO_NR(6, 14),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
 	},
 
 	/* GW551x */
@@ -702,6 +945,60 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
 		.pcie_rst = IMX_GPIO_NR(1, 0),
 		.vidin_en = IMX_GPIO_NR(5, 20),
 		.wdis = IMX_GPIO_NR(7, 12),
+		.otgpwr_en = IMX_GPIO_NR(3, 22),
+		.vsel_pin = IMX_GPIO_NR(6, 14),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
+	},
+
+	/* GW560x */
+	{
+		.gpio_pads = gw560x_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2,
+		.dio_cfg = gw560x_dio,
+		.dio_num = ARRAY_SIZE(gw560x_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 7),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(4, 31),
+		.mezz_pwren = IMX_GPIO_NR(2, 19),
+		.mezz_irq = IMX_GPIO_NR(2, 18),
+		.rs232_en = GP_RS232_EN,
+		.vidin_en = IMX_GPIO_NR(3, 31),
+		.wdis = IMX_GPIO_NR(7, 12),
+		.otgpwr_en = IMX_GPIO_NR(4, 15),
+		.mmc_cd = IMX_GPIO_NR(7, 0),
+	},
+
+	/* GW5903 */
+	{
+		.gpio_pads = gw5903_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2,
+		.dio_cfg = gw5903_dio,
+		.dio_num = ARRAY_SIZE(gw5903_dio),
+		.leds = {
+			IMX_GPIO_NR(6, 14),
+		},
+		.otgpwr_en = IMX_GPIO_NR(4, 15),
+		.mmc_cd = IMX_GPIO_NR(6, 11),
+	},
+
+	/* GW5904 */
+	{
+		.gpio_pads = gw5904_gpio_pads,
+		.num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
+		.dio_cfg = gw5904_dio,
+		.dio_num = ARRAY_SIZE(gw5904_dio),
+		.leds = {
+			IMX_GPIO_NR(4, 6),
+			IMX_GPIO_NR(4, 7),
+			IMX_GPIO_NR(4, 15),
+		},
+		.pcie_rst = IMX_GPIO_NR(1, 0),
+		.mezz_pwren = IMX_GPIO_NR(2, 19),
+		.mezz_irq = IMX_GPIO_NR(2, 18),
+		.otgpwr_en = IMX_GPIO_NR(3, 22),
 	},
 };
 
@@ -709,13 +1006,6 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
 {
 	int i;
 
-	/* iomux common to all Ventana boards */
-	SETUP_IOMUX_PADS(gw_gpio_pads);
-
-	/* OTG power off */
-	gpio_request(GP_USB_OTG_PWR, "usbotg_pwr");
-	gpio_direction_output(GP_USB_OTG_PWR, 0);
-
 	if (board >= GW_UNKNOWN)
 		return;
 
@@ -725,7 +1015,7 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
 
 	/* RS232_EN# */
 	if (gpio_cfg[board].rs232_en) {
-		gpio_request(gpio_cfg[board].rs232_en, "rs232_en");
+		gpio_request(gpio_cfg[board].rs232_en, "rs232_en#");
 		gpio_direction_output(gpio_cfg[board].rs232_en, 0);
 	}
 
@@ -805,10 +1095,62 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info)
 		gpio_direction_output(gpio_cfg[board].wdis, 1);
 	}
 
+	/* OTG power off */
+	if (gpio_cfg[board].otgpwr_en) {
+		gpio_request(gpio_cfg[board].otgpwr_en, "usbotg_pwr");
+		gpio_direction_output(gpio_cfg[board].otgpwr_en, 0);
+	}
+
 	/* sense vselect pin to see if we support uhs-i */
-	gpio_request(GP_SD3_VSELECT, "sd3_vselect");
-	gpio_direction_input(GP_SD3_VSELECT);
-	gpio_cfg[board].usd_vsel = !gpio_get_value(GP_SD3_VSELECT);
+	if (gpio_cfg[board].vsel_pin) {
+		gpio_request(gpio_cfg[board].vsel_pin, "sd3_vselect");
+		gpio_direction_input(gpio_cfg[board].vsel_pin);
+		gpio_cfg[board].usd_vsel = !gpio_get_value(gpio_cfg[board].vsel_pin);
+	}
+
+	/* microSD CD */
+	if (gpio_cfg[board].mmc_cd) {
+		gpio_request(gpio_cfg[board].mmc_cd, "sd_cd");
+		gpio_direction_input(gpio_cfg[board].mmc_cd);
+	}
+
+	/* Anything else board specific */
+	switch(board) {
+	case GW560x:
+		gpio_request(IMX_GPIO_NR(4, 26), "12p0_en");
+		gpio_direction_output(IMX_GPIO_NR(4, 26), 1);
+		break;
+	case GW5903:
+		gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr");
+		gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
+		gpio_request(IMX_GPIO_NR(4, 15) , "usbh2-otg_pwr");
+		gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
+		gpio_request(IMX_GPIO_NR(4, 7) , "usbdpc_pwr");
+		gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
+		gpio_request(IMX_GPIO_NR(1, 25) , "rgmii_en");
+		gpio_direction_output(IMX_GPIO_NR(1, 25), 1);
+		gpio_request(IMX_GPIO_NR(4, 6) , "touch_irq#");
+		gpio_direction_input(IMX_GPIO_NR(4, 6));
+		gpio_request(IMX_GPIO_NR(4, 8) , "touch_rst");
+		gpio_direction_output(IMX_GPIO_NR(4, 8), 1);
+		gpio_request(IMX_GPIO_NR(1, 7) , "bklt_12ven");
+		gpio_direction_output(IMX_GPIO_NR(1, 7), 1);
+		break;
+	case GW5904:
+		gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#");
+		gpio_direction_output(IMX_GPIO_NR(5, 11), 1);
+		gpio_request(IMX_GPIO_NR(5, 12), "skt1_rst#");
+		gpio_direction_output(IMX_GPIO_NR(5, 12), 1);
+		gpio_request(IMX_GPIO_NR(5, 13), "skt2_wdis#");
+		gpio_direction_output(IMX_GPIO_NR(5, 13), 1);
+		gpio_request(IMX_GPIO_NR(1, 15), "m2_off#");
+		gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
+		gpio_request(IMX_GPIO_NR(1, 14), "m2_wdis#");
+		gpio_direction_output(IMX_GPIO_NR(1, 14), 1);
+		gpio_request(IMX_GPIO_NR(1, 13), "m2_rst#");
+		gpio_direction_output(IMX_GPIO_NR(1, 13), 1);
+		break;
+	}
 }
 
 /* setup GPIO pinmux and default configuration per baseboard and env */
@@ -901,14 +1243,17 @@ void setup_board_gpio(int board, struct ventana_board_info *info)
 void setup_pmic(void)
 {
 	struct pmic *p;
+	struct ventana_board_info ventana_info;
+	int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
+	const int i2c_pmic = 1;
 	u32 reg;
 
-	i2c_set_bus_num(CONFIG_I2C_PMIC);
+	i2c_set_bus_num(i2c_pmic);
 
 	/* configure PFUZE100 PMIC */
 	if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) {
 		debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR);
-		power_pfuze100_init(CONFIG_I2C_PMIC);
+		power_pfuze100_init(i2c_pmic);
 		p = pmic_get("PFUZE100");
 		if (p && !pmic_probe(p)) {
 			pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
@@ -931,25 +1276,42 @@ void setup_pmic(void)
 	/* configure LTC3676 PMIC */
 	else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) {
 		debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR);
-		power_ltc3676_init(CONFIG_I2C_PMIC);
+		power_ltc3676_init(i2c_pmic);
 		p = pmic_get("LTC3676_PMIC");
-		if (p && !pmic_probe(p)) {
-			puts("PMIC:  LTC3676\n");
-			/*
-			 * set board-specific scalar for max CPU frequency
-			 * per CPU based on the LDO enabled Operating Ranges
-			 * defined in the respective IMX6DQ and IMX6SDL
-			 * datasheets. The voltage resulting from the R1/R2
-			 * feedback inputs on Ventana is 1308mV. Note that this
-			 * is a bit shy of the Vmin of 1350mV in the datasheet
-			 * for LDO enabled mode but is as high as we can go.
-			 *
-			 * We will rely on an OS kernel driver to properly
-			 * regulate these per CPU operating point and use LDO
-			 * bypass mode when using the higher frequency
-			 * operating points to compensate as LDO bypass mode
-			 * allows the rails be 125mV lower.
-			 */
+		if (!p || pmic_probe(p))
+			return;
+		puts("PMIC:  LTC3676\n");
+		/*
+		 * set board-specific scalar for max CPU frequency
+		 * per CPU based on the LDO enabled Operating Ranges
+		 * defined in the respective IMX6DQ and IMX6SDL
+		 * datasheets. The voltage resulting from the R1/R2
+		 * feedback inputs on Ventana is 1308mV. Note that this
+		 * is a bit shy of the Vmin of 1350mV in the datasheet
+		 * for LDO enabled mode but is as high as we can go.
+		 */
+		switch (board) {
+		case GW560x:
+			/* mask PGOOD during SW3 transition */
+			pmic_reg_write(p, LTC3676_DVB3B,
+				       0x1f | LTC3676_PGOOD_MASK);
+			/* set SW3 (VDD_ARM) */
+			pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
+			break;
+		case GW5903:
+			/* mask PGOOD during SW1 transition */
+			pmic_reg_write(p, LTC3676_DVB3B,
+				       0x1f | LTC3676_PGOOD_MASK);
+			/* set SW3 (VDD_ARM) */
+			pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
+
+			/* mask PGOOD during SW4 transition */
+			pmic_reg_write(p, LTC3676_DVB4B,
+				       0x1f | LTC3676_PGOOD_MASK);
+			/* set SW4 (VDD_SOC) */
+			pmic_reg_write(p, LTC3676_DVB4A, 0x1f);
+			break;
+		default:
 			/* mask PGOOD during SW1 transition */
 			pmic_reg_write(p, LTC3676_DVB1B,
 				       0x1f | LTC3676_PGOOD_MASK);
@@ -964,3 +1326,98 @@ void setup_pmic(void)
 		}
 	}
 }
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[2];
+
+int board_mmc_init(bd_t *bis)
+{
+	struct ventana_board_info ventana_info;
+	int board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
+	int ret;
+
+	switch (board_type) {
+	case GW52xx:
+	case GW53xx:
+	case GW54xx:
+	case GW553x:
+		/* usdhc3: 4bit microSD */
+		SETUP_IOMUX_PADS(usdhc3_pads);
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		usdhc_cfg[0].max_bus_width = 4;
+		return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+	case GW560x:
+		/* usdhc2: 8-bit eMMC */
+		SETUP_IOMUX_PADS(gw560x_emmc_sd2_pads);
+		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+		usdhc_cfg[0].max_bus_width = 8;
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+		if (ret)
+			return ret;
+		/* usdhc3: 4-bit microSD */
+		SETUP_IOMUX_PADS(usdhc3_pads);
+		usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		usdhc_cfg[1].max_bus_width = 4;
+		return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+	case GW5903:
+		/* usdhc3: 8-bit eMMC */
+		SETUP_IOMUX_PADS(gw5904_emmc_pads);
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		usdhc_cfg[0].max_bus_width = 8;
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+		if (ret)
+			return ret;
+		/* usdhc2: 4-bit microSD */
+		SETUP_IOMUX_PADS(gw5904_mmc_pads);
+		usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR;
+		usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+		usdhc_cfg[1].max_bus_width = 4;
+		return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+	case GW5904:
+		/* usdhc3: 8bit eMMC */
+		SETUP_IOMUX_PADS(gw5904_emmc_pads);
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		usdhc_cfg[0].max_bus_width = 8;
+		return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+	default:
+		/* doesn't have MMC */
+		return -1;
+	}
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct ventana_board_info ventana_info;
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
+	int gpio = gpio_cfg[board].mmc_cd;
+
+	/* Card Detect */
+	switch (board) {
+	case GW560x:
+		/* emmc is always present */
+		if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+			return 1;
+		break;
+	case GW5903:
+	case GW5904:
+		/* emmc is always present */
+		if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+			return 1;
+		break;
+	}
+
+	if (gpio) {
+		debug("%s: gpio%d=%d\n", __func__, gpio, gpio_get_value(gpio));
+		return !gpio_get_value(gpio);
+	}
+
+	return -1;
+}
+
+#endif /* CONFIG_FSL_ESDHC */
diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h
index 3d7aff1..3eb4c59 100644
--- a/board/gateworks/gw_ventana/common.h
+++ b/board/gateworks/gw_ventana/common.h
@@ -13,11 +13,8 @@
 
 /* GPIO's common to all baseboards */
 #define GP_PHY_RST	IMX_GPIO_NR(1, 30)
-#define GP_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
-#define GP_SD3_CD	IMX_GPIO_NR(7, 0)
 #define GP_RS232_EN	IMX_GPIO_NR(2, 11)
 #define GP_MSATA_SEL	IMX_GPIO_NR(2, 8)
-#define GP_SD3_VSELECT	IMX_GPIO_NR(6, 14)
 
 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
@@ -79,6 +76,9 @@ struct ventana {
 	int wdis;
 	int msata_en;
 	int rs232_en;
+	int otgpwr_en;
+	int vsel_pin;
+	int mmc_cd;
 	/* various features */
 	bool usd_vsel;
 };
diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c
index 1382e5d..2c07a84 100644
--- a/board/gateworks/gw_ventana/eeprom.c
+++ b/board/gateworks/gw_ventana/eeprom.c
@@ -64,6 +64,7 @@ read_eeprom(int bus, struct ventana_board_info *info)
 	if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0)
 		baseboard = '0';
 
+	type = GW_UNKNOWN;
 	switch (baseboard) {
 	case '0': /* original GW5400-A prototype */
 		type = GW54proto;
@@ -91,10 +92,16 @@ read_eeprom(int bus, struct ventana_board_info *info)
 			type = GW553x;
 			break;
 		}
-		/* fall through */
-	default:
-		printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
-		type = GW_UNKNOWN;
+		break;
+	case '6':
+		if (info->model[4] == '0')
+			type = GW560x;
+		break;
+	case '9':
+		if (info->model[4] == '0' && info->model[5] == '3')
+			type = GW5903;
+		if (info->model[4] == '0' && info->model[5] == '4')
+			type = GW5904;
 		break;
 	}
 	return type;
diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
index 2ca6d5c..68b1ddb 100644
--- a/board/gateworks/gw_ventana/gsc.c
+++ b/board/gateworks/gw_ventana/gsc.c
@@ -6,7 +6,7 @@
  * SPDX-License-Identifier: GPL-2.0+
  */
 
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <common.h>
 #include <i2c.h>
 #include <linux/ctype.h>
@@ -137,6 +137,10 @@ int gsc_info(int verbose)
 		break;
 	case '5': /* GW55xx */
 		break;
+	case '6': /* GW560x */
+		read_hwmon("VDD_IO4",  GSC_HWMON_VDD_IO4, 3);
+		read_hwmon("VDD_GPS",  GSC_HWMON_VDD_IO3, 3);
+		break;
 	}
 	return 0;
 }
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 5d871ce..89848c8 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -14,11 +14,12 @@
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/spi.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/spi.h>
+#include <asm/mach-imx/video.h>
 #include <asm/io.h>
+#include <asm/setup.h>
 #include <dm.h>
 #include <dm/platform_data/serial_mxc.h>
 #include <hwconfig.h>
@@ -52,17 +53,6 @@ struct ventana_board_info ventana_info;
 
 static int board_type;
 
-/* MMC */
-static iomux_v3_cfg_t const usdhc3_pads[] = {
-	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
 /* ENET */
 static iomux_v3_cfg_t const enet_pads[] = {
 	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
@@ -87,7 +77,7 @@ static iomux_v3_cfg_t const enet_pads[] = {
 	IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
 };
 
-/* NAND */
+#ifdef CONFIG_CMD_NAND
 static iomux_v3_cfg_t const nfc_pads[] = {
 	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 	IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
@@ -106,7 +96,6 @@ static iomux_v3_cfg_t const nfc_pads[] = {
 	IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
-#ifdef CONFIG_CMD_NAND
 static void setup_gpmi_nand(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -143,8 +132,9 @@ static void setup_iomux_enet(int gpio)
 	/* toggle PHY_RST# */
 	gpio_request(gpio, "phy_rst#");
 	gpio_direction_output(gpio, 0);
-	mdelay(2);
+	mdelay(10);
 	gpio_set_value(gpio, 1);
+	mdelay(100);
 }
 
 #ifdef CONFIG_USB_EHCI_MX6
@@ -186,35 +176,15 @@ int board_ehci_hcd_init(int port)
 
 int board_ehci_power(int port, int on)
 {
-	if (port)
-		return 0;
-	gpio_set_value(GP_USB_OTG_PWR, on);
+	/* enable OTG VBUS */
+	if (!port && board_type < GW_UNKNOWN) {
+		if (gpio_cfg[board_type].otgpwr_en)
+			gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
+	}
 	return 0;
 }
 #endif /* CONFIG_USB_EHCI_MX6 */
 
-#ifdef CONFIG_FSL_ESDHC
-static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
-
-int board_mmc_getcd(struct mmc *mmc)
-{
-	/* Card Detect */
-	gpio_request(GP_SD3_CD, "sd_cd");
-	gpio_direction_input(GP_SD3_CD);
-	return !gpio_get_value(GP_SD3_CD);
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	/* Only one USDHC controller on Ventana */
-	SETUP_IOMUX_PADS(usdhc3_pads);
-	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-	usdhc_cfg.max_bus_width = 4;
-
-	return fsl_esdhc_initialize(bis, &usdhc_cfg);
-}
-#endif /* CONFIG_FSL_ESDHC */
-
 #ifdef CONFIG_MXC_SPI
 iomux_v3_cfg_t const ecspi1_pads[] = {
 	/* SS1 */
@@ -257,12 +227,56 @@ int board_phy_config(struct phy_device *phydev)
 		phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 	}
 
+	/* TI DP83867 */
+	else if (phydev->phy_id == 0x2000a231) {
+		/* configure register 0x170 for ref CLKOUT */
+		phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
+		phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
+		phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
+		val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
+		val &= ~0x1f00;
+		val |= 0x0b00; /* chD tx clock*/
+		phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
+	}
+
 	if (phydev->drv->config)
 		phydev->drv->config(phydev);
 
 	return 0;
 }
 
+#ifdef CONFIG_MV88E61XX_SWITCH
+int mv88e61xx_hw_reset(struct phy_device *phydev)
+{
+	struct mii_dev *bus = phydev->bus;
+
+	/* GPIO[0] output, CLK125 */
+	debug("enabling RGMII_REFCLK\n");
+	bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
+		   0x1a /*MV_SCRATCH_MISC*/,
+		   (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
+	bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
+		   0x1a /*MV_SCRATCH_MISC*/,
+		   (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
+
+	/* RGMII delay - Physical Control register bit[15:14] */
+	debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
+	/* forced 1000mbps full-duplex link */
+	bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
+	phydev->autoneg = AUTONEG_DISABLE;
+	phydev->speed = SPEED_1000;
+	phydev->duplex = DUPLEX_FULL;
+
+	/* LED configuration: 7:4-green (8=Activity)  3:0 amber (9=10Link) */
+	bus->write(bus, 0x10, 0, 0x16, 0x8089);
+	bus->write(bus, 0x11, 0, 0x16, 0x8089);
+	bus->write(bus, 0x12, 0, 0x16, 0x8089);
+	bus->write(bus, 0x13, 0, 0x16, 0x8089);
+
+	return 0;
+}
+#endif // CONFIG_MV88E61XX_SWITCH
+
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_FEC_MXC
@@ -619,7 +633,7 @@ int board_init(void)
 #endif
 	setup_ventana_i2c();
 
-#ifdef CONFIG_CMD_SATA
+#ifdef CONFIG_SATA
 	setup_sata();
 #endif
 	/* read Gateworks EEPROM into global struct (used later) */
@@ -692,6 +706,8 @@ int checkboard(void)
 static const struct boot_mode board_boot_modes[] = {
 	/* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
 	{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
+	{ "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
+	{ "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/GW5904 */
 	{ NULL, 0 },
 };
 #endif
@@ -743,7 +759,8 @@ int misc_init_r(void)
 			setenv("fdt_file1", fdt);
 			if (board_type != GW551x &&
 			    board_type != GW552x &&
-			    board_type != GW553x)
+			    board_type != GW553x &&
+			    board_type != GW560x)
 				str[4] = 'x';
 			str[5] = 'x';
 			str[6] = 0;
@@ -772,7 +789,7 @@ int misc_init_r(void)
 
 	/* Set a non-initialized hwconfig based on board configuration */
 	if (!strcmp(getenv("hwconfig"), "_UNKNOWN_")) {
-		sprintf(buf, "hwconfig=");
+		buf[0] = 0;
 		if (gpio_cfg[board_type].rs232_en)
 			strcat(buf, "rs232;");
 		for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
@@ -1074,6 +1091,12 @@ void ft_board_pci_fixup(void *blob, bd_t *bd)
 }
 #endif /* if defined(CONFIG_CMD_PCI) */
 
+void ft_board_wdog_fixup(void *blob, const char *path)
+{
+	ft_delprop_path(blob, path, "ext-reset-output");
+	ft_delprop_path(blob, path, "fsl,ext-reset-output");
+}
+
 /*
  * called prior to booting kernel or by 'fdt boardsetup' command
  *
@@ -1156,8 +1179,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 		/* GW51xx-E adds WDOG1_B external reset */
 		if (rev < 'E')
-			ft_delprop_path(blob, WDOG1_PATH,
-					"fsl,ext-reset-output");
+			ft_board_wdog_fixup(blob, WDOG1_PATH);
 		break;
 
 	case GW52xx:
@@ -1187,23 +1209,19 @@ int ft_board_setup(void *blob, bd_t *bd)
 			    strstr((const char *)info->model, "SP331-B"))
 				gpio_cfg[board_type].usd_vsel = 0;
 
-			/* GW520x-E adds WDOG1_B external reset */
-			if (info->model[4] == '0' && rev < 'E')
-				ft_delprop_path(blob, WDOG1_PATH,
-						"fsl,ext-reset-output");
-
 			/* GW522x-B adds WDOG1_B external reset */
-			if (info->model[4] == '2' && rev < 'B')
-				ft_delprop_path(blob, WDOG1_PATH,
-						"fsl,ext-reset-output");
+			ft_board_wdog_fixup(blob, WDOG1_PATH);
 		}
+
+		/* GW520x-E adds WDOG1_B external reset */
+		else if (info->model[4] == '0' && rev < 'E')
+			ft_board_wdog_fixup(blob, WDOG1_PATH);
 		break;
 
 	case GW53xx:
 		/* GW53xx-E adds WDOG1_B external reset */
 		if (rev < 'E')
-			ft_delprop_path(blob, WDOG1_PATH,
-					"fsl,ext-reset-output");
+			ft_board_wdog_fixup(blob, WDOG1_PATH);
 		break;
 
 	case GW54xx:
@@ -1217,8 +1235,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 		/* GW54xx-E adds WDOG2_B external reset */
 		if (rev < 'E')
-			ft_delprop_path(blob, WDOG2_PATH,
-					"fsl,ext-reset-output");
+			ft_board_wdog_fixup(blob, WDOG2_PATH);
 		break;
 
 	case GW551x:
@@ -1267,8 +1284,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 		/* GW551x-C adds WDOG1_B external reset */
 		if (rev < 'C')
-			ft_delprop_path(blob, WDOG1_PATH,
-					"fsl,ext-reset-output");
+			ft_board_wdog_fixup(blob, WDOG1_PATH);
 		break;
 	}
 
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index b610e06..69a638d 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -11,9 +11,9 @@
 #include <asm/arch/mx6-ddr.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
 #include <environment.h>
 #include <i2c.h>
 #include <spl.h>
@@ -355,6 +355,44 @@ static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
 	.p1_mpwrdlctl = 0X40304239,
 };
 
+static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x0048004A,
+	.p0_mpwldectrl1 = 0x003F004A,
+	.p1_mpwldectrl0 = 0x001E0028,
+	.p1_mpwldectrl1 = 0x002C0043,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x02250219,
+	.p0_mpdgctrl1 = 0x01790202,
+	.p1_mpdgctrl0 = 0x02080208,
+	.p1_mpdgctrl1 = 0x016C0175,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x4A4C4D4C,
+	.p1_mprddlctl = 0x494C4A48,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x403F3437,
+	.p1_mpwrdlctl = 0x383A3930,
+};
+
+static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x001F003F,
+	.p0_mpwldectrl1 = 0x001F001F,
+	.p1_mpwldectrl0 = 0x001F004E,
+	.p1_mpwldectrl1 = 0x0059001F,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0   = 0x42220225,
+	.p0_mpdgctrl1   = 0x0213021F,
+	.p1_mpdgctrl0   = 0x022C0242,
+	.p1_mpdgctrl1   = 0x022C0244,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl   = 0x474A4C4A,
+	.p1_mprddlctl   = 0x48494C45,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl   = 0x3F3F3F36,
+	.p1_mpwrdlctl   = 0x3F36363F,
+};
+
 static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
 	/* write leveling calibration determine */
 	.p0_mpwldectrl0 = 0x002A0025,
@@ -368,6 +406,25 @@ static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
 	.p0_mpwrdlctl = 0x303E3C36,
 };
 
+static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = {
+	/* write leveling calibration determine */
+	.p0_mpwldectrl0 = 0x00230020,
+	.p0_mpwldectrl1 = 0x002F002A,
+	.p1_mpwldectrl0 = 0x001D0027,
+	.p1_mpwldectrl1 = 0x00100023,
+	/* Read DQS Gating calibration */
+	.p0_mpdgctrl0 = 0x03250339,
+	.p0_mpdgctrl1 = 0x031C0316,
+	.p1_mpdgctrl0 = 0x03210331,
+	.p1_mpdgctrl1 = 0x031C025A,
+	/* Read Calibration: DQS delay relative to DQ read access */
+	.p0_mprddlctl = 0x40373C40,
+	.p1_mprddlctl = 0x3A373646,
+	/* Write Calibration: DQ/DM delay relative to DQS write access */
+	.p0_mpwrdlctl = 0x2E353933,
+	.p1_mpwrdlctl = 0x3C2F3F35,
+};
+
 static void spl_dram_init(int width, int size_mb, int board_model)
 {
 	struct mx6_ddr3_cfg *mem = NULL;
@@ -468,7 +525,29 @@ static void spl_dram_init(int width, int size_mb, int board_model)
 		mem = &mt41k256m16ha_125;
 		if (is_cpu_type(MXC_CPU_MX6Q))
 			calib = &mx6dq_256x64_mmdc_calib;
+		else
+			calib = &mx6sdl_256x64_mmdc_calib;
 		debug("4gB density\n");
+	} else if (width == 64 && size_mb == 4096) {
+		switch(board_model) {
+		case GW5903:
+			/* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */
+			mem = &mt41k256m16ha_125;
+			debug("4gB density\n");
+			if (!is_cpu_type(MXC_CPU_MX6Q)) {
+				calib = &mx6sdl_256x64x2_mmdc_calib;
+				sysinfo.ncs = 2;
+				sysinfo.cs_density = 18; /* CS0_END=71 */
+				sysinfo.cs1_mirror = 1; /* mirror enabled */
+			}
+			break;
+		default:
+			mem = &mt41k512m16ha_125;
+			if (is_cpu_type(MXC_CPU_MX6Q))
+				calib = &mx6dq_512x64_mmdc_calib;
+			debug("8gB density\n");
+			break;
+		}
 	}
 
 	if (!(mem && calib)) {
@@ -563,6 +642,20 @@ void board_init_f(ulong dummy)
 	memset(__bss_start, 0, __bss_end - __bss_start);
 }
 
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = spl_boot_device();
+	switch (spl_boot_list[0]) {
+	case BOOT_DEVICE_NAND:
+		spl_boot_list[1] = BOOT_DEVICE_MMC1;
+		spl_boot_list[2] = BOOT_DEVICE_UART;
+		break;
+	case BOOT_DEVICE_MMC1:
+		spl_boot_list[1] = BOOT_DEVICE_UART;
+		break;
+	}
+}
+
 /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
 /* its our chance to print info about boot device */
 void spl_board_init(void)
diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h
index 9ffad58..8a42d67 100644
--- a/board/gateworks/gw_ventana/ventana_eeprom.h
+++ b/board/gateworks/gw_ventana/ventana_eeprom.h
@@ -112,6 +112,9 @@ enum {
 	GW551x,
 	GW552x,
 	GW553x,
+	GW560x,
+	GW5903,
+	GW5904,
 	GW_UNKNOWN,
 	GW_BADCRC,
 };
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
deleted file mode 100644
index 35fa06a..0000000
--- a/board/gdsys/405ep/405ep.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * (C) Copyright 2010
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/global_data.h>
-
-#include "405ep.h"
-#include <gdsys_fpga.h>
-
-#define REFLECTION_TESTPATTERN 0xdede
-#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
-
-#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
-#define REFLECTION_TESTREG reflection_low
-#else
-#define REFLECTION_TESTREG reflection_high
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int get_fpga_state(unsigned dev)
-{
-	return gd->arch.fpga_state[dev];
-}
-
-int board_early_init_f(void)
-{
-	unsigned k;
-
-	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
-		gd->arch.fpga_state[k] = 0;
-
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
-	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
-	mtdcr(UIC0PR, 0xFFFFFF80);	/* set int polarities */
-	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
-	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest prio */
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-
-	/*
-	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
-	 * -> ca. 15 us
-	 */
-	mtebc(EBC0_CFG, 0xa8400000);	/* ebc always driven */
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	unsigned k;
-	unsigned ctr;
-
-	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
-		gd->arch.fpga_state[k] = 0;
-
-	/*
-	 * reset FPGA
-	 */
-	gd405ep_init();
-
-	gd405ep_set_fpga_reset(1);
-
-	gd405ep_setup_hw();
-
-	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
-		ctr = 0;
-		while (!gd405ep_get_fpga_done(k)) {
-			udelay(100000);
-			if (ctr++ > 5) {
-				gd->arch.fpga_state[k] |=
-					FPGA_STATE_DONE_FAILED;
-				break;
-			}
-		}
-	}
-
-	udelay(10);
-
-	gd405ep_set_fpga_reset(0);
-
-	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
-		/*
-		 * wait for fpga out of reset
-		 */
-		ctr = 0;
-		while (1) {
-			u16 val;
-
-			FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
-
-			FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
-			if (val == REFLECTION_TESTPATTERN_INV)
-				break;
-
-			udelay(100000);
-			if (ctr++ > 5) {
-				gd->arch.fpga_state[k] |=
-					FPGA_STATE_REFLECTION_FAILED;
-				break;
-			}
-		}
-	}
-
-	return 0;
-}
diff --git a/board/gdsys/405ep/405ep.h b/board/gdsys/405ep/405ep.h
deleted file mode 100644
index 5647dbc..0000000
--- a/board/gdsys/405ep/405ep.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __405EP_H_
-#define __405EP_H_
-
-/* functions to be provided by board implementation */
-void gd405ep_init(void);
-void gd405ep_set_fpga_reset(unsigned state);
-void gd405ep_setup_hw(void);
-int gd405ep_get_fpga_done(unsigned fpga);
-
-#endif /* __405EP_H_ */
diff --git a/board/gdsys/405ep/Kconfig b/board/gdsys/405ep/Kconfig
deleted file mode 100644
index 20cb80f..0000000
--- a/board/gdsys/405ep/Kconfig
+++ /dev/null
@@ -1,51 +0,0 @@
-if TARGET_DLVISION_10G
-
-config SYS_BOARD
-	default "405ep"
-
-config SYS_VENDOR
-	default "gdsys"
-
-config SYS_CONFIG_NAME
-	default "dlvision-10g"
-
-endif
-
-if TARGET_IO
-
-config SYS_BOARD
-	default "405ep"
-
-config SYS_VENDOR
-	default "gdsys"
-
-config SYS_CONFIG_NAME
-	default "io"
-
-endif
-
-if TARGET_IOCON
-
-config SYS_BOARD
-	default "405ep"
-
-config SYS_VENDOR
-	default "gdsys"
-
-config SYS_CONFIG_NAME
-	default "iocon"
-
-endif
-
-if TARGET_NEO
-
-config SYS_BOARD
-	default "405ep"
-
-config SYS_VENDOR
-	default "gdsys"
-
-config SYS_CONFIG_NAME
-	default "neo"
-
-endif
diff --git a/board/gdsys/405ep/MAINTAINERS b/board/gdsys/405ep/MAINTAINERS
deleted file mode 100644
index 1403880..0000000
--- a/board/gdsys/405ep/MAINTAINERS
+++ /dev/null
@@ -1,12 +0,0 @@
-405EP BOARD
-M:	Dirk Eibach <eibach@gdsys.de>
-S:	Maintained
-F:	board/gdsys/405ep/
-F:	include/configs/dlvision-10g.h
-F:	configs/dlvision-10g_defconfig
-F:	include/configs/io.h
-F:	configs/io_defconfig
-F:	include/configs/iocon.h
-F:	configs/iocon_defconfig
-F:	include/configs/neo.h
-F:	configs/neo_defconfig
diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile
deleted file mode 100644
index 857ec04..0000000
--- a/board/gdsys/405ep/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y := 405ep.o
-obj-$(CONFIG_NEO) += neo.o
-obj-$(CONFIG_IO) += io.o
-obj-$(CONFIG_IOCON) += iocon.o
-obj-$(CONFIG_DLVISION_10G) += dlvision-10g.o
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
deleted file mode 100644
index e400d19..0000000
--- a/board/gdsys/405ep/dlvision-10g.c
+++ /dev/null
@@ -1,313 +0,0 @@
-/*
- * (C) Copyright 2010
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-#include <dtt.h>
-
-#include "405ep.h"
-#include <gdsys_fpga.h>
-
-#include "../common/osd.h"
-
-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
-
-#define LATCH2_MC2_PRESENT_N 0x0080
-
-enum {
-	UNITTYPE_MAIN = 1<<0,
-	UNITTYPE_SERVER = 1<<1,
-	UNITTYPE_DISPLAYPORT = 1<<2,
-};
-
-enum {
-	HWVER_101 = 0,
-	HWVER_110 = 1,
-	HWVER_130 = 2,
-	HWVER_140 = 3,
-	HWVER_150 = 4,
-	HWVER_160 = 5,
-	HWVER_170 = 6,
-};
-
-enum {
-	AUDIO_NONE = 0,
-	AUDIO_TX = 1,
-	AUDIO_RX = 2,
-	AUDIO_RXTX = 3,
-};
-
-enum {
-	SYSCLK_156250 = 2,
-};
-
-enum {
-	RAM_NONE = 0,
-	RAM_DDR2_32 = 1,
-	RAM_DDR2_64 = 2,
-};
-
-struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-
-int misc_init_r(void)
-{
-	/* startup fans */
-	dtt_init();
-
-	return 0;
-}
-
-static unsigned int get_hwver(void)
-{
-	u16 latch3 = in_le16((void *)LATCH3_BASE);
-
-	return latch3 & 0x0003;
-}
-
-static unsigned int get_mc2_present(void)
-{
-	u16 latch2 = in_le16((void *)LATCH2_BASE);
-
-	return !(latch2 & LATCH2_MC2_PRESENT_N);
-}
-
-static void print_fpga_info(unsigned dev)
-{
-	u16 versions;
-	u16 fpga_version;
-	u16 fpga_features;
-	unsigned unit_type;
-	unsigned hardware_version;
-	unsigned feature_rs232;
-	unsigned feature_audio;
-	unsigned feature_sysclock;
-	unsigned feature_ramconfig;
-	unsigned feature_carrier_speed;
-	unsigned feature_carriers;
-	unsigned feature_video_channels;
-	int fpga_state = get_fpga_state(dev);
-
-	printf("FPGA%d: ", dev);
-
-	FPGA_GET_REG(dev, versions, &versions);
-	FPGA_GET_REG(dev, fpga_version, &fpga_version);
-	FPGA_GET_REG(dev, fpga_features, &fpga_features);
-
-	hardware_version = versions & 0x000f;
-
-	if (fpga_state
-	    && !((hardware_version == HWVER_101)
-		 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
-		puts("not available\n");
-		if (fpga_state & FPGA_STATE_DONE_FAILED)
-			puts("       Waiting for FPGA-DONE timed out.\n");
-		if (fpga_state & FPGA_STATE_REFLECTION_FAILED)
-			puts("       FPGA reflection test failed.\n");
-		return;
-	}
-
-	unit_type = (versions >> 4) & 0x000f;
-	hardware_version = versions & 0x000f;
-	feature_rs232 = fpga_features & (1<<11);
-	feature_audio = (fpga_features >> 9) & 0x0003;
-	feature_sysclock = (fpga_features >> 7) & 0x0003;
-	feature_ramconfig = (fpga_features >> 5) & 0x0003;
-	feature_carrier_speed = fpga_features & (1<<4);
-	feature_carriers = (fpga_features >> 2) & 0x0003;
-	feature_video_channels = fpga_features & 0x0003;
-
-	if (unit_type & UNITTYPE_MAIN)
-		printf("Mainchannel ");
-	else
-		printf("Videochannel ");
-
-	if (unit_type & UNITTYPE_SERVER)
-		printf("Serverside ");
-	else
-		printf("Userside ");
-
-	if (unit_type & UNITTYPE_DISPLAYPORT)
-		printf("DisplayPort");
-	else
-		printf("DVI-DL");
-
-	switch (hardware_version) {
-	case HWVER_101:
-		printf(" HW-Ver 1.01\n");
-		break;
-
-	case HWVER_110:
-		printf(" HW-Ver 1.10-1.20\n");
-		break;
-
-	case HWVER_130:
-		printf(" HW-Ver 1.30\n");
-		break;
-
-	case HWVER_140:
-		printf(" HW-Ver 1.40-1.43\n");
-		break;
-
-	case HWVER_150:
-		printf(" HW-Ver 1.50\n");
-		break;
-
-	case HWVER_160:
-		printf(" HW-Ver 1.60-1.61\n");
-		break;
-
-	case HWVER_170:
-		printf(" HW-Ver 1.70\n");
-		break;
-
-	default:
-		printf(" HW-Ver %d(not supported)\n",
-		       hardware_version);
-		break;
-	}
-
-	printf("       FPGA V %d.%02d, features:",
-		fpga_version / 100, fpga_version % 100);
-
-	printf(" %sRS232", feature_rs232 ? "" : "no ");
-
-	switch (feature_audio) {
-	case AUDIO_NONE:
-		printf(", no audio");
-		break;
-
-	case AUDIO_TX:
-		printf(", audio tx");
-		break;
-
-	case AUDIO_RX:
-		printf(", audio rx");
-		break;
-
-	case AUDIO_RXTX:
-		printf(", audio rx+tx");
-		break;
-
-	default:
-		printf(", audio %d(not supported)", feature_audio);
-		break;
-	}
-
-	switch (feature_sysclock) {
-	case SYSCLK_156250:
-		printf(", clock 156.25 MHz");
-		break;
-
-	default:
-		printf(", clock %d(not supported)", feature_sysclock);
-		break;
-	}
-
-	puts(",\n       ");
-
-	switch (feature_ramconfig) {
-	case RAM_NONE:
-		printf("no RAM");
-		break;
-
-	case RAM_DDR2_32:
-		printf("RAM 32 bit DDR2");
-		break;
-
-	case RAM_DDR2_64:
-		printf("RAM 64 bit DDR2");
-		break;
-
-	default:
-		printf("RAM %d(not supported)", feature_ramconfig);
-		break;
-	}
-
-	printf(", %d carrier(s) %s", feature_carriers,
-		feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
-
-	printf(", %d video channel(s)\n", feature_video_channels);
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
-	char *s = getenv("serial#");
-
-	puts("Board: ");
-
-	puts("DLVision 10G");
-
-	if (s != NULL) {
-		puts(", serial# ");
-		puts(s);
-	}
-
-	puts("\n");
-
-	return 0;
-}
-
-int last_stage_init(void)
-{
-	u16 versions;
-
-	FPGA_GET_REG(0, versions, &versions);
-
-	print_fpga_info(0);
-	if (get_mc2_present())
-		print_fpga_info(1);
-
-	if (((versions >> 4) & 0x000f) & UNITTYPE_SERVER)
-		return 0;
-
-	if (!get_fpga_state(0) || (get_hwver() == HWVER_101))
-		osd_probe(0);
-
-	if (get_mc2_present() &&
-	    (!get_fpga_state(1) || (get_hwver() == HWVER_101)))
-		osd_probe(1);
-
-	return 0;
-}
-
-void gd405ep_init(void)
-{
-}
-
-void gd405ep_set_fpga_reset(unsigned state)
-{
-	if (state) {
-		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
-		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
-	} else {
-		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
-		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
-	}
-}
-
-void gd405ep_setup_hw(void)
-{
-	/*
-	 * set "startup-finished"-gpios
-	 */
-	gpio_write_bit(21, 0);
-	gpio_write_bit(22, 1);
-}
-
-int gd405ep_get_fpga_done(unsigned fpga)
-{
-	return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
-}
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
deleted file mode 100644
index 81b4965..0000000
--- a/board/gdsys/405ep/io.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * (C) Copyright 2010
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-#include <dtt.h>
-#include <miiphy.h>
-
-#include "405ep.h"
-#include <gdsys_fpga.h>
-
-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-
-#define PHYREG_CONTROL				0
-#define PHYREG_PAGE_ADDRESS			22
-#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1	16
-#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2	26
-
-enum {
-	UNITTYPE_CCD_SWITCH = 1,
-};
-
-enum {
-	HWVER_100 = 0,
-	HWVER_110 = 1,
-	HWVER_121 = 2,
-	HWVER_122 = 3,
-};
-
-struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-
-int misc_init_r(void)
-{
-	/* startup fans */
-	dtt_init();
-
-	return 0;
-}
-
-int configure_gbit_phy(unsigned char addr)
-{
-	unsigned short value;
-
-	/* select page 2 */
-	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
-		PHYREG_PAGE_ADDRESS, 0x0002))
-		goto err_out;
-	/* disable SGMII autonegotiation */
-	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
-		PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
-		goto err_out;
-	/* select page 0 */
-	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
-		PHYREG_PAGE_ADDRESS, 0x0000))
-		goto err_out;
-	/* switch from powerdown to normal operation */
-	if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
-		PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
-		goto err_out;
-	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
-		PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
-		goto err_out;
-	/* reset phy so settings take effect */
-	if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
-		PHYREG_CONTROL, 0x9140))
-		goto err_out;
-
-	return 0;
-
-err_out:
-	printf("Error writing to the PHY addr=%02x\n", addr);
-	return -1;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
-	char *s = getenv("serial#");
-
-	puts("Board: CATCenter Io");
-
-	if (s != NULL) {
-		puts(", serial# ");
-		puts(s);
-	}
-
-	puts("\n");
-
-	return 0;
-}
-
-static void print_fpga_info(void)
-{
-	u16 versions;
-	u16 fpga_version;
-	u16 fpga_features;
-	unsigned unit_type;
-	unsigned hardware_version;
-	unsigned feature_channels;
-	unsigned feature_expansion;
-
-	FPGA_GET_REG(0, versions, &versions);
-	FPGA_GET_REG(0, fpga_version, &fpga_version);
-	FPGA_GET_REG(0, fpga_features, &fpga_features);
-
-	unit_type = (versions & 0xf000) >> 12;
-	hardware_version = versions & 0x000f;
-	feature_channels = fpga_features & 0x007f;
-	feature_expansion = fpga_features & (1<<15);
-
-	puts("FPGA:  ");
-
-	switch (unit_type) {
-	case UNITTYPE_CCD_SWITCH:
-		printf("CCD-Switch");
-		break;
-
-	default:
-		printf("UnitType %d(not supported)", unit_type);
-		break;
-	}
-
-	switch (hardware_version) {
-	case HWVER_100:
-		printf(" HW-Ver 1.00\n");
-		break;
-
-	case HWVER_110:
-		printf(" HW-Ver 1.10\n");
-		break;
-
-	case HWVER_121:
-		printf(" HW-Ver 1.21\n");
-		break;
-
-	case HWVER_122:
-		printf(" HW-Ver 1.22\n");
-		break;
-
-	default:
-		printf(" HW-Ver %d(not supported)\n",
-		       hardware_version);
-		break;
-	}
-
-	printf("       FPGA V %d.%02d, features:",
-		fpga_version / 100, fpga_version % 100);
-
-	printf(" %d channel(s)", feature_channels);
-
-	printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
-}
-
-/*
- * setup Gbit PHYs
- */
-int last_stage_init(void)
-{
-	unsigned int k;
-
-	print_fpga_info();
-
-	int retval;
-	struct mii_dev *mdiodev = mdio_alloc();
-	if (!mdiodev)
-		return -ENOMEM;
-	strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN);
-	mdiodev->read = bb_miiphy_read;
-	mdiodev->write = bb_miiphy_write;
-
-	retval = mdio_register(mdiodev);
-	if (retval < 0)
-		return retval;
-
-	for (k = 0; k < 32; ++k)
-		configure_gbit_phy(k);
-
-	/* take fpga serdes blocks out of reset */
-	FPGA_SET_REG(0, quad_serdes_reset, 0);
-
-	return 0;
-}
-
-void gd405ep_init(void)
-{
-}
-
-void gd405ep_set_fpga_reset(unsigned state)
-{
-	if (state) {
-		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
-		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
-	} else {
-		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
-		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
-	}
-}
-
-void gd405ep_setup_hw(void)
-{
-	/*
-	 * set "startup-finished"-gpios
-	 */
-	gpio_write_bit(21, 0);
-	gpio_write_bit(22, 1);
-}
-
-int gd405ep_get_fpga_done(unsigned fpga)
-{
-	return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
-}
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
deleted file mode 100644
index 7db0e29..0000000
--- a/board/gdsys/405ep/iocon.c
+++ /dev/null
@@ -1,673 +0,0 @@
-/*
- * (C) Copyright 2010
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <errno.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-#include "405ep.h"
-#include <gdsys_fpga.h>
-
-#include "../common/osd.h"
-#include "../common/mclink.h"
-#include "../common/phy.h"
-
-#include <i2c.h>
-#include <pca953x.h>
-#include <pca9698.h>
-
-#include <miiphy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-
-#define MAX_MUX_CHANNELS 2
-
-enum {
-	UNITTYPE_MAIN_SERVER = 0,
-	UNITTYPE_MAIN_USER = 1,
-	UNITTYPE_VIDEO_SERVER = 2,
-	UNITTYPE_VIDEO_USER = 3,
-};
-
-enum {
-	HWVER_100 = 0,
-	HWVER_104 = 1,
-	HWVER_110 = 2,
-	HWVER_120 = 3,
-	HWVER_200 = 4,
-	HWVER_210 = 5,
-	HWVER_220 = 6,
-	HWVER_230 = 7,
-};
-
-enum {
-	FPGA_HWVER_200 = 0,
-	FPGA_HWVER_210 = 1,
-};
-
-enum {
-	COMPRESSION_NONE = 0,
-	COMPRESSION_TYPE1_DELTA = 1,
-	COMPRESSION_TYPE1_TYPE2_DELTA = 3,
-};
-
-enum {
-	AUDIO_NONE = 0,
-	AUDIO_TX = 1,
-	AUDIO_RX = 2,
-	AUDIO_RXTX = 3,
-};
-
-enum {
-	SYSCLK_147456 = 0,
-};
-
-enum {
-	RAM_DDR2_32 = 0,
-	RAM_DDR3_32 = 1,
-};
-
-enum {
-	CARRIER_SPEED_1G = 0,
-	CARRIER_SPEED_2_5G = 1,
-};
-
-enum {
-	MCFPGA_DONE = 1 << 0,
-	MCFPGA_INIT_N = 1 << 1,
-	MCFPGA_PROGRAM_N = 1 << 2,
-	MCFPGA_UPDATE_ENABLE_N = 1 << 3,
-	MCFPGA_RESET_N = 1 << 4,
-};
-
-enum {
-	GPIO_MDC = 1 << 14,
-	GPIO_MDIO = 1 << 15,
-};
-
-unsigned int mclink_fpgacount;
-struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-
-int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
-{
-	int res;
-
-	switch (fpga) {
-	case 0:
-		out_le16(reg, data);
-		break;
-	default:
-		res = mclink_send(fpga - 1, regoff, data);
-		if (res < 0) {
-			printf("mclink_send reg %02lx data %04x returned %d\n",
-			       regoff, data, res);
-			return res;
-		}
-		break;
-	}
-
-	return 0;
-}
-
-int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
-{
-	int res;
-
-	switch (fpga) {
-	case 0:
-		*data = in_le16(reg);
-		break;
-	default:
-		if (fpga > mclink_fpgacount)
-			return -EINVAL;
-		res = mclink_receive(fpga - 1, regoff, data);
-		if (res < 0) {
-			printf("mclink_receive reg %02lx returned %d\n",
-			       regoff, res);
-			return res;
-		}
-	}
-
-	return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
-	char *s = getenv("serial#");
-
-	puts("Board: ");
-
-	puts("IoCon");
-
-	if (s != NULL) {
-		puts(", serial# ");
-		puts(s);
-	}
-
-	puts("\n");
-
-	return 0;
-}
-
-static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
-{
-	u16 versions;
-	u16 fpga_version;
-	u16 fpga_features;
-	unsigned unit_type;
-	unsigned hardware_version;
-	unsigned feature_compression;
-	unsigned feature_osd;
-	unsigned feature_audio;
-	unsigned feature_sysclock;
-	unsigned feature_ramconfig;
-	unsigned feature_carrier_speed;
-	unsigned feature_carriers;
-	unsigned feature_video_channels;
-
-	int legacy = get_fpga_state(fpga) & FPGA_STATE_PLATFORM;
-
-	FPGA_GET_REG(fpga, versions, &versions);
-	FPGA_GET_REG(fpga, fpga_version, &fpga_version);
-	FPGA_GET_REG(fpga, fpga_features, &fpga_features);
-
-	unit_type = (versions & 0xf000) >> 12;
-	feature_compression = (fpga_features & 0xe000) >> 13;
-	feature_osd = fpga_features & (1<<11);
-	feature_audio = (fpga_features & 0x0600) >> 9;
-	feature_sysclock = (fpga_features & 0x0180) >> 7;
-	feature_ramconfig = (fpga_features & 0x0060) >> 5;
-	feature_carrier_speed = fpga_features & (1<<4);
-	feature_carriers = (fpga_features & 0x000c) >> 2;
-	feature_video_channels = fpga_features & 0x0003;
-
-	if (legacy)
-		printf("legacy ");
-
-	switch (unit_type) {
-	case UNITTYPE_MAIN_USER:
-		printf("Mainchannel");
-		break;
-
-	case UNITTYPE_VIDEO_USER:
-		printf("Videochannel");
-		break;
-
-	default:
-		printf("UnitType %d(not supported)", unit_type);
-		break;
-	}
-
-	if (unit_type == UNITTYPE_MAIN_USER) {
-		if (legacy)
-			hardware_version =
-				(in_le16((void *)LATCH2_BASE)>>8) & 0x0f;
-		else
-			hardware_version =
-				  (!!pca9698_get_value(0x20, 24) << 0)
-				| (!!pca9698_get_value(0x20, 25) << 1)
-				| (!!pca9698_get_value(0x20, 26) << 2)
-				| (!!pca9698_get_value(0x20, 27) << 3);
-		switch (hardware_version) {
-		case HWVER_100:
-			printf(" HW-Ver 1.00,");
-			break;
-
-		case HWVER_104:
-			printf(" HW-Ver 1.04,");
-			break;
-
-		case HWVER_110:
-			printf(" HW-Ver 1.10,");
-			break;
-
-		case HWVER_120:
-			printf(" HW-Ver 1.20-1.21,");
-			break;
-
-		case HWVER_200:
-			printf(" HW-Ver 2.00,");
-			break;
-
-		case HWVER_210:
-			printf(" HW-Ver 2.10,");
-			break;
-
-		case HWVER_220:
-			printf(" HW-Ver 2.20,");
-			break;
-
-		case HWVER_230:
-			printf(" HW-Ver 2.30,");
-			break;
-
-		default:
-			printf(" HW-Ver %d(not supported),",
-			       hardware_version);
-			break;
-		}
-		if (rgmii2_present)
-			printf(" RGMII2,");
-	}
-
-	if (unit_type == UNITTYPE_VIDEO_USER) {
-		hardware_version = versions & 0x000f;
-		switch (hardware_version) {
-		case FPGA_HWVER_200:
-			printf(" HW-Ver 2.00,");
-			break;
-
-		case FPGA_HWVER_210:
-			printf(" HW-Ver 2.10,");
-			break;
-
-		default:
-			printf(" HW-Ver %d(not supported),",
-			       hardware_version);
-			break;
-		}
-	}
-
-	printf(" FPGA V %d.%02d\n       features:",
-	       fpga_version / 100, fpga_version % 100);
-
-
-	switch (feature_compression) {
-	case COMPRESSION_NONE:
-		printf(" no compression");
-		break;
-
-	case COMPRESSION_TYPE1_DELTA:
-		printf(" type1-deltacompression");
-		break;
-
-	case COMPRESSION_TYPE1_TYPE2_DELTA:
-		printf(" type1-deltacompression, type2-inlinecompression");
-		break;
-
-	default:
-		printf(" compression %d(not supported)", feature_compression);
-		break;
-	}
-
-	printf(", %sosd", feature_osd ? "" : "no ");
-
-	switch (feature_audio) {
-	case AUDIO_NONE:
-		printf(", no audio");
-		break;
-
-	case AUDIO_TX:
-		printf(", audio tx");
-		break;
-
-	case AUDIO_RX:
-		printf(", audio rx");
-		break;
-
-	case AUDIO_RXTX:
-		printf(", audio rx+tx");
-		break;
-
-	default:
-		printf(", audio %d(not supported)", feature_audio);
-		break;
-	}
-
-	puts(",\n       ");
-
-	switch (feature_sysclock) {
-	case SYSCLK_147456:
-		printf("clock 147.456 MHz");
-		break;
-
-	default:
-		printf("clock %d(not supported)", feature_sysclock);
-		break;
-	}
-
-	switch (feature_ramconfig) {
-	case RAM_DDR2_32:
-		printf(", RAM 32 bit DDR2");
-		break;
-
-	case RAM_DDR3_32:
-		printf(", RAM 32 bit DDR3");
-		break;
-
-	default:
-		printf(", RAM %d(not supported)", feature_ramconfig);
-		break;
-	}
-
-	printf(", %d carrier(s) %s", feature_carriers,
-	       feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
-
-	printf(", %d video channel(s)\n", feature_video_channels);
-}
-
-int last_stage_init(void)
-{
-	int slaves;
-	unsigned int k;
-	unsigned int mux_ch;
-	unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
-	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
-	u16 fpga_features;
-	int feature_carrier_speed;
-	bool ch0_rgmii2_present = false;
-
-	FPGA_GET_REG(0, fpga_features, &fpga_features);
-	feature_carrier_speed = fpga_features & (1<<4);
-
-	if (!legacy) {
-		/* Turn on Parade DP501 */
-		pca9698_direction_output(0x20, 9, 1);
-
-		ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
-	}
-
-	/* wait for FPGA done; then reset FPGA */
-	for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
-		unsigned int ctr = 0;
-
-		if (i2c_probe(mclink_controllers[k]))
-			continue;
-
-		while (!(pca953x_get_val(mclink_controllers[k])
-		       & MCFPGA_DONE)) {
-			udelay(100000);
-			if (ctr++ > 5) {
-				printf("no done for mclink_controller %d\n", k);
-				break;
-			}
-		}
-
-		pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
-		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
-		udelay(10);
-		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
-				MCFPGA_RESET_N);
-	}
-
-	if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
-		int retval;
-		struct mii_dev *mdiodev = mdio_alloc();
-		if (!mdiodev)
-			return -ENOMEM;
-		strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
-		mdiodev->read = bb_miiphy_read;
-		mdiodev->write = bb_miiphy_write;
-
-		retval = mdio_register(mdiodev);
-		if (retval < 0)
-			return retval;
-		for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
-			if ((mux_ch == 1) && !ch0_rgmii2_present)
-				continue;
-
-			setup_88e1518(bb_miiphy_buses[0].name, mux_ch);
-		}
-	}
-
-	/* give slave-PLLs and Parade DP501 some time to be up and running */
-	udelay(500000);
-
-	mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
-	slaves = mclink_probe();
-	mclink_fpgacount = 0;
-
-	print_fpga_info(0, ch0_rgmii2_present);
-	osd_probe(0);
-
-	if (slaves <= 0)
-		return 0;
-
-	mclink_fpgacount = slaves;
-
-	for (k = 1; k <= slaves; ++k) {
-		FPGA_GET_REG(k, fpga_features, &fpga_features);
-		feature_carrier_speed = fpga_features & (1<<4);
-
-		print_fpga_info(k, false);
-		osd_probe(k);
-		if (feature_carrier_speed == CARRIER_SPEED_1G) {
-			int retval;
-			struct mii_dev *mdiodev = mdio_alloc();
-			if (!mdiodev)
-				return -ENOMEM;
-			strncpy(mdiodev->name, bb_miiphy_buses[k].name,
-				MDIO_NAME_LEN);
-			mdiodev->read = bb_miiphy_read;
-			mdiodev->write = bb_miiphy_write;
-
-			retval = mdio_register(mdiodev);
-			if (retval < 0)
-				return retval;
-			setup_88e1518(bb_miiphy_buses[k].name, 0);
-		}
-	}
-
-	return 0;
-}
-
-/*
- * provide access to fpga gpios (for I2C bitbang)
- * (these may look all too simple but make iocon.h much more readable)
- */
-void fpga_gpio_set(unsigned int bus, int pin)
-{
-	FPGA_SET_REG(bus, gpio.set, pin);
-}
-
-void fpga_gpio_clear(unsigned int bus, int pin)
-{
-	FPGA_SET_REG(bus, gpio.clear, pin);
-}
-
-int fpga_gpio_get(unsigned int bus, int pin)
-{
-	u16 val;
-
-	FPGA_GET_REG(bus, gpio.read, &val);
-
-	return val & pin;
-}
-
-void gd405ep_init(void)
-{
-	unsigned int k;
-
-	if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */
-		for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
-			gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
-	} else {
-		pca9698_direction_output(0x20, 4, 1);
-	}
-}
-
-void gd405ep_set_fpga_reset(unsigned state)
-{
-	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
-
-	if (legacy) {
-		if (state) {
-			out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
-			out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
-		} else {
-			out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
-			out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
-		}
-	} else {
-		pca9698_set_value(0x20, 4, state ? 0 : 1);
-	}
-}
-
-void gd405ep_setup_hw(void)
-{
-	/*
-	 * set "startup-finished"-gpios
-	 */
-	gpio_write_bit(21, 0);
-	gpio_write_bit(22, 1);
-}
-
-int gd405ep_get_fpga_done(unsigned fpga)
-{
-	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
-
-	if (legacy)
-		return in_le16((void *)LATCH2_BASE)
-		       & CONFIG_SYS_FPGA_DONE(fpga);
-	else
-		return pca9698_get_value(0x20, 20);
-}
-
-/*
- * FPGA MII bitbang implementation
- */
-
-struct fpga_mii {
-	unsigned fpga;
-	int mdio;
-} fpga_mii[] = {
-	{ 0, 1},
-	{ 1, 1},
-	{ 2, 1},
-	{ 3, 1},
-};
-
-static int mii_dummy_init(struct bb_miiphy_bus *bus)
-{
-	return 0;
-}
-
-static int mii_mdio_active(struct bb_miiphy_bus *bus)
-{
-	struct fpga_mii *fpga_mii = bus->priv;
-
-	if (fpga_mii->mdio)
-		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
-	else
-		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
-
-	return 0;
-}
-
-static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
-{
-	struct fpga_mii *fpga_mii = bus->priv;
-
-	FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
-
-	return 0;
-}
-
-static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
-{
-	struct fpga_mii *fpga_mii = bus->priv;
-
-	if (v)
-		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
-	else
-		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
-
-	fpga_mii->mdio = v;
-
-	return 0;
-}
-
-static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
-{
-	u16 gpio;
-	struct fpga_mii *fpga_mii = bus->priv;
-
-	FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
-
-	*v = ((gpio & GPIO_MDIO) != 0);
-
-	return 0;
-}
-
-static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
-{
-	struct fpga_mii *fpga_mii = bus->priv;
-
-	if (v)
-		FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
-	else
-		FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
-
-	return 0;
-}
-
-static int mii_delay(struct bb_miiphy_bus *bus)
-{
-	udelay(1);
-
-	return 0;
-}
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
-	{
-		.name = "board0",
-		.init = mii_dummy_init,
-		.mdio_active = mii_mdio_active,
-		.mdio_tristate = mii_mdio_tristate,
-		.set_mdio = mii_set_mdio,
-		.get_mdio = mii_get_mdio,
-		.set_mdc = mii_set_mdc,
-		.delay = mii_delay,
-		.priv = &fpga_mii[0],
-	},
-	{
-		.name = "board1",
-		.init = mii_dummy_init,
-		.mdio_active = mii_mdio_active,
-		.mdio_tristate = mii_mdio_tristate,
-		.set_mdio = mii_set_mdio,
-		.get_mdio = mii_get_mdio,
-		.set_mdc = mii_set_mdc,
-		.delay = mii_delay,
-		.priv = &fpga_mii[1],
-	},
-	{
-		.name = "board2",
-		.init = mii_dummy_init,
-		.mdio_active = mii_mdio_active,
-		.mdio_tristate = mii_mdio_tristate,
-		.set_mdio = mii_set_mdio,
-		.get_mdio = mii_get_mdio,
-		.set_mdc = mii_set_mdc,
-		.delay = mii_delay,
-		.priv = &fpga_mii[2],
-	},
-	{
-		.name = "board3",
-		.init = mii_dummy_init,
-		.mdio_active = mii_mdio_active,
-		.mdio_tristate = mii_mdio_tristate,
-		.set_mdio = mii_set_mdio,
-		.get_mdio = mii_get_mdio,
-		.set_mdc = mii_set_mdc,
-		.delay = mii_delay,
-		.priv = &fpga_mii[3],
-	},
-};
-
-int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
-			  sizeof(bb_miiphy_buses[0]);
diff --git a/board/gdsys/405ep/neo.c b/board/gdsys/405ep/neo.c
deleted file mode 100644
index ff0edb2..0000000
--- a/board/gdsys/405ep/neo.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * (C) Copyright 2011
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-#include <dtt.h>
-
-#include "405ep.h"
-#include <gdsys_fpga.h>
-
-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-
-enum {
-	UNITTYPE_CCX16 = 1,
-	UNITTYPE_CCIP216 = 2,
-};
-
-enum {
-	HWVER_300 = 3,
-};
-
-struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-
-int misc_init_r(void)
-{
-	/* startup fans */
-	dtt_init();
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char *s = getenv("serial#");
-
-	puts("Board: CATCenter Neo");
-
-	if (s != NULL) {
-		puts(", serial# ");
-		puts(s);
-	}
-
-	puts("\n");
-
-	return 0;
-}
-
-static void print_fpga_info(void)
-{
-	u16 versions;
-	u16 fpga_version;
-	u16 fpga_features;
-	int fpga_state = get_fpga_state(0);
-	unsigned unit_type;
-	unsigned hardware_version;
-	unsigned feature_channels;
-
-	puts("FPGA:  ");
-	if (fpga_state & FPGA_STATE_DONE_FAILED) {
-		printf(" done timed out\n");
-		return;
-	}
-
-	if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
-		printf(" refelectione test failed\n");
-		return;
-	}
-
-	FPGA_GET_REG(0, versions, &versions);
-	FPGA_GET_REG(0, fpga_version, &fpga_version);
-	FPGA_GET_REG(0, fpga_features, &fpga_features);
-
-	unit_type = (versions & 0xf000) >> 12;
-	hardware_version = versions & 0x000f;
-	feature_channels = fpga_features & 0x007f;
-
-	switch (unit_type) {
-	case UNITTYPE_CCX16:
-		printf("CCX-Switch");
-		break;
-
-	default:
-		printf("UnitType %d(not supported)", unit_type);
-		break;
-	}
-
-	switch (hardware_version) {
-	case HWVER_300:
-		printf(" HW-Ver 3.00-3.12\n");
-		break;
-
-	default:
-		printf(" HW-Ver %d(not supported)\n",
-		       hardware_version);
-		break;
-	}
-
-	printf("       FPGA V %d.%02d, features:",
-		fpga_version / 100, fpga_version % 100);
-
-	printf(" %d channel(s)\n", feature_channels);
-}
-
-int last_stage_init(void)
-{
-	print_fpga_info();
-
-	return 0;
-}
-
-void gd405ep_init(void)
-{
-}
-
-void gd405ep_set_fpga_reset(unsigned state)
-{
-	if (state) {
-		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
-		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
-	} else {
-		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
-		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
-	}
-}
-
-void gd405ep_setup_hw(void)
-{
-	/*
-	 * set "startup-finished"-gpios
-	 */
-	gpio_write_bit(21, 0);
-	gpio_write_bit(22, 1);
-}
-
-int gd405ep_get_fpga_done(unsigned fpga)
-{
-	/*
-	 * Neo hardware has no FPGA-DONE GPIO
-	 */
-	return 1;
-}
diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c
deleted file mode 100644
index 9e1c57f..0000000
--- a/board/gdsys/405ex/405ex.c
+++ /dev/null
@@ -1,244 +0,0 @@
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc405.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#include <gdsys_fpga.h>
-
-#include "405ex.h"
-
-#define REFLECTION_TESTPATTERN 0xdede
-#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
-
-#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
-#define REFLECTION_TESTREG reflection_low
-#else
-#define REFLECTION_TESTREG reflection_high
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int get_fpga_state(unsigned dev)
-{
-	return gd->arch.fpga_state[dev];
-}
-
-int board_early_init_f(void)
-{
-	u32 val;
-
-	/*--------------------------------------------------------------------+
-	 | Interrupt controller setup
-	 +--------------------------------------------------------------------+
-	+---------------------------------------------------------------------+
-	|Interrupt| Source                            | Pol.  | Sensi.| Crit. |
-	+---------+-----------------------------------+-------+-------+-------+
-	| IRQ 00  | UART0                             | High  | Level | Non   |
-	| IRQ 01  | UART1                             | High  | Level | Non   |
-	| IRQ 02  | IIC0                              | High  | Level | Non   |
-	| IRQ 03  | TBD                               | High  | Level | Non   |
-	| IRQ 04  | TBD                               | High  | Level | Non   |
-	| IRQ 05  | EBM                               | High  | Level | Non   |
-	| IRQ 06  | BGI                               | High  | Level | Non   |
-	| IRQ 07  | IIC1                              | Rising| Edge  | Non   |
-	| IRQ 08  | SPI                               | High  | Lvl/ed| Non   |
-	| IRQ 09  | External IRQ 0 - (PCI-Express)    | pgm H | Pgm   | Non   |
-	| IRQ 10  | MAL TX EOB                        | High  | Level | Non   |
-	| IRQ 11  | MAL RX EOB                        | High  | Level | Non   |
-	| IRQ 12  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
-	| IRQ 13  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
-	| IRQ 14  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
-	| IRQ 15  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
-	| IRQ 16  | PCIE0 AL                          | high  | Level | Non   |
-	| IRQ 17  | PCIE0 VPD access                  | rising| Edge  | Non   |
-	| IRQ 18  | PCIE0 hot reset request           | rising| Edge  | Non   |
-	| IRQ 19  | PCIE0 hot reset request           | faling| Edge  | Non   |
-	| IRQ 20  | PCIE0 TCR                         | High  | Level | Non   |
-	| IRQ 21  | PCIE0 MSI level0                  | High  | Level | Non   |
-	| IRQ 22  | PCIE0 MSI level1                  | High  | Level | Non   |
-	| IRQ 23  | Security EIP-94                   | High  | Level | Non   |
-	| IRQ 24  | EMAC0 interrupt                   | High  | Level | Non   |
-	| IRQ 25  | EMAC1 interrupt                   | High  | Level | Non   |
-	| IRQ 26  | PCIE0 MSI level2                  | High  | Level | Non   |
-	| IRQ 27  | External IRQ 4                    | pgm H | Pgm   | Non   |
-	| IRQ 28  | UIC2 Non-critical Int.            | High  | Level | Non   |
-	| IRQ 29  | UIC2 Critical Interrupt           | High  | Level | Crit. |
-	| IRQ 30  | UIC1 Non-critical Int.            | High  | Level | Non   |
-	| IRQ 31  | UIC1 Critical Interrupt           | High  | Level | Crit. |
-	|----------------------------------------------------------------------
-	| IRQ 32  | MAL Serr                          | High  | Level | Non   |
-	| IRQ 33  | MAL Txde                          | High  | Level | Non   |
-	| IRQ 34  | MAL Rxde                          | High  | Level | Non   |
-	| IRQ 35  | PCIE0 bus master VC0              |falling| Edge  | Non   |
-	| IRQ 36  | PCIE0 DCR Error                   | High  | Level | Non   |
-	| IRQ 37  | EBC                               | High  |Lvl Edg| Non   |
-	| IRQ 38  | NDFC                              | High  | Level | Non   |
-	| IRQ 39  | GPT Compare Timer 8               | Risin | Edge  | Non   |
-	| IRQ 40  | GPT Compare Timer 9               | Risin | Edge  | Non   |
-	| IRQ 41  | PCIE1 AL                          | high  | Level | Non   |
-	| IRQ 42  | PCIE1 VPD access                  | rising| edge  | Non   |
-	| IRQ 43  | PCIE1 hot reset request           | rising| Edge  | Non   |
-	| IRQ 44  | PCIE1 hot reset request           | faling| Edge  | Non   |
-	| IRQ 45  | PCIE1 TCR                         | High  | Level | Non   |
-	| IRQ 46  | PCIE1 bus master VC0              |falling| Edge  | Non   |
-	| IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
-	| IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
-	| IRQ 49  | Ext. IRQ 7                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 50  | Ext. IRQ 8 -                      |pgm (H)|pgm/Lvl| Non   |
-	| IRQ 51  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
-	| IRQ 52  | GPT Compare Timer 5               | high  | Edge  | Non   |
-	| IRQ 53  | GPT Compare Timer 6               | high  | Edge  | Non   |
-	| IRQ 54  | GPT Compare Timer 7               | high  | Edge  | Non   |
-	| IRQ 55  | Serial ROM                        | High  | Level | Non   |
-	| IRQ 56  | GPT Decrement Pulse               | High  | Level | Non   |
-	| IRQ 57  | Ext. IRQ 2                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 58  | Ext. IRQ 5                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 59  | Ext. IRQ 6                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 60  | EMAC0 Wake-up                     | High  | Level | Non   |
-	| IRQ 61  | Ext. IRQ 1                        |pgm/Fal|pgm/Lvl| Non   |
-	| IRQ 62  | EMAC1 Wake-up                     | High  | Level | Non   |
-	|----------------------------------------------------------------------
-	| IRQ 64  | PE0 AL                            | High  | Level | Non   |
-	| IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
-	| IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
-	| IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
-	| IRQ 68  | PE0 TCR                           | High  | Level | Non   |
-	| IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
-	| IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
-	| IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 72  | PE1 AL                            | High  | Level | Non   |
-	| IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
-	| IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
-	| IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
-	| IRQ 76  | PE1 TCR                           | High  | Level | Non   |
-	| IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
-	| IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
-	| IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 80  | PE2 AL                            | High  | Level | Non   |
-	| IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
-	| IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
-	| IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
-	| IRQ 84  | PE2 TCR                           | High  | Level | Non   |
-	| IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
-	| IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
-	| IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
-	| IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
-	| IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
-	| IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
-	| IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
-	|---------------------------------------------------------------------
-	+---------+-----------------------------------+-------+-------+------*/
-	/*--------------------------------------------------------------------+
-	 | Initialise UIC registers.  Clear all interrupts.  Disable all
-	 | interrupts.
-	 | Set critical interrupt values.  Set interrupt polarities.  Set
-	 | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
-	 | interrupts again.
-	 +-------------------------------------------------------------------*/
-
-	mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
-	mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */
-	mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
-	mtdcr(UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
-	mtdcr(UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
-	mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
-	mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */
-	mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
-
-	mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */
-	mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */
-	mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
-	mtdcr(UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
-	mtdcr(UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
-	mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
-	mtdcr(UIC1SR, 0x00000000); /* clear all interrupts */
-	mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */
-
-	mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
-	mtdcr(UIC0ER, 0x0000000a); /* Disable all interrupts */
-				   /* Except cascade UIC0 and UIC1 */
-	mtdcr(UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
-	mtdcr(UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
-	mtdcr(UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
-	mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
-	mtdcr(UIC0SR, 0x00000000); /* clear all interrupts */
-	mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */
-
-	/*
-	 * Note: Some cores are still in reset when the chip starts, so
-	 * take them out of reset
-	 */
-	mtsdr(SDR0_SRST, 0);
-
-	/*
-	 * Configure PFC (Pin Function Control) registers
-	 */
-	val = SDR0_PFC1_GPT_FREQ;
-	mtsdr(SDR0_PFC1, val);
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	unsigned k;
-	unsigned ctr;
-
-	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
-		gd->arch.fpga_state[k] = 0;
-
-	/*
-	 * reset FPGA
-	 */
-	gd405ex_init();
-
-	gd405ex_set_fpga_reset(1);
-
-	gd405ex_setup_hw();
-
-	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
-		ctr = 0;
-		while (!gd405ex_get_fpga_done(k)) {
-			udelay(100000);
-			if (ctr++ > 5) {
-				gd->arch.fpga_state[k] |=
-					FPGA_STATE_DONE_FAILED;
-				break;
-			}
-		}
-	}
-
-	udelay(10);
-
-	gd405ex_set_fpga_reset(0);
-
-	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
-		/*
-		 * wait for fpga out of reset
-		 */
-		ctr = 0;
-		while (1) {
-			u16 val;
-
-			FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
-
-			FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
-			if (val == REFLECTION_TESTPATTERN_INV)
-				break;
-
-			udelay(100000);
-			if (ctr++ > 5) {
-				gd->arch.fpga_state[k] |=
-					FPGA_STATE_REFLECTION_FAILED;
-				break;
-			}
-		}
-	}
-
-	return 0;
-}
diff --git a/board/gdsys/405ex/405ex.h b/board/gdsys/405ex/405ex.h
deleted file mode 100644
index b15623f..0000000
--- a/board/gdsys/405ex/405ex.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __405EX_H_
-#define __405EX_H_
-
-/* functions to be provided by board implementation */
-void gd405ex_init(void);
-void gd405ex_set_fpga_reset(unsigned state);
-void gd405ex_setup_hw(void);
-int gd405ex_get_fpga_done(unsigned fpga);
-
-#endif /* __405EX_H_ */
diff --git a/board/gdsys/405ex/Kconfig b/board/gdsys/405ex/Kconfig
deleted file mode 100644
index 52a8d89..0000000
--- a/board/gdsys/405ex/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_IO64
-
-config SYS_BOARD
-	default "405ex"
-
-config SYS_VENDOR
-	default "gdsys"
-
-config SYS_CONFIG_NAME
-	default "io64"
-
-endif
diff --git a/board/gdsys/405ex/MAINTAINERS b/board/gdsys/405ex/MAINTAINERS
deleted file mode 100644
index 395b1ac..0000000
--- a/board/gdsys/405ex/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-405EX BOARD
-M:	Dirk Eibach <eibach@gdsys.de>
-S:	Maintained
-F:	board/gdsys/405ex/
-F:	include/configs/io64.h
-F:	configs/io64_defconfig
diff --git a/board/gdsys/405ex/Makefile b/board/gdsys/405ex/Makefile
deleted file mode 100644
index a668460..0000000
--- a/board/gdsys/405ex/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y := 405ex.o
-obj-$(CONFIG_IO64) += io64.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
diff --git a/board/gdsys/405ex/chip_config.c b/board/gdsys/405ex/chip_config.c
deleted file mode 100644
index 37e76c4..0000000
--- a/board/gdsys/405ex/chip_config.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */
-
-struct ppc4xx_config ppc4xx_config_val[] = {
-	{
-		"333-nor", "NOR  CPU: 333 PLB: 166 OPB:  83 EBC:  83",
-		{
-			0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
-			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"400-133-nor", "NOR  CPU: 400 PLB: 133 OPB:  66 EBC:  66",
-		{
-			0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
-			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"400-200-66-nor", "NOR  CPU: 400 PLB: 200 OPB:  66 EBC:  66",
-		{
-			0x8e, 0x0e, 0xe8, 0x12, 0xd8, 0x00, 0x0a, 0x00,
-			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"400-nor", "NOR  CPU: 400 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
-			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"533-nor", "NOR  CPU: 533 PLB: 177 OPB:  88 EBC:  88",
-		{
-			0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
-			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"533-nand", "NOR  CPU: 533 PLB: 177 OPB:  88 EBC:  88",
-		{
-			0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00,
-			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"600-nor", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
-			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"600-nand", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00,
-			0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"666-nor", "NOR  CPU: 666 PLB: 222 OPB: 111 EBC: 111",
-		{
-			0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
-			0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
-		}
-	},
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c
deleted file mode 100644
index 848cdde..0000000
--- a/board/gdsys/405ex/io64.c
+++ /dev/null
@@ -1,403 +0,0 @@
-/*
- * (C) Copyright 2010
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * based on kilauea.c
- * by Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc405.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/ppc4xx-gpio.h>
-#include <flash.h>
-
-#include <pca9698.h>
-
-#include "405ex.h"
-#include <gdsys_fpga.h>
-
-#include <miiphy.h>
-#include <i2c.h>
-#include <dtt.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define PHYREG_CONTROL				0
-#define PHYREG_PAGE_ADDRESS			22
-#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1	16
-#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2	26
-#define PHYREG_PG2_MAC_SPECIFIC_STATUS_1	17
-#define PHYREG_PG2_MAC_SPECIFIC_CONTROL		21
-
-#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
-#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
-#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
-#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
-
-enum {
-	UNITTYPE_CCD_SWITCH = 1,
-};
-
-enum {
-	HWVER_100 = 0,
-	HWVER_110 = 1,
-};
-
-struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
-
-static inline void blank_string(int size)
-{
-	int i;
-
-	for (i = 0; i < size; i++)
-		putc('\b');
-	for (i = 0; i < size; i++)
-		putc(' ');
-	for (i = 0; i < size; i++)
-		putc('\b');
-}
-
-/*
- * Board early initialization function
- */
-int misc_init_r(void)
-{
-	/* startup fans */
-	dtt_init();
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-	/* Monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      -CONFIG_SYS_MONITOR_LEN,
-		      0xffffffff,
-		      &flash_info[0]);
-#endif
-
-	return 0;
-}
-
-static void print_fpga_info(unsigned dev)
-{
-	u16 versions;
-	u16 fpga_version;
-	u16 fpga_features;
-	int fpga_state = get_fpga_state(dev);
-
-	unsigned unit_type;
-	unsigned hardware_version;
-	unsigned feature_channels;
-	unsigned feature_expansion;
-
-	FPGA_GET_REG(dev, versions, &versions);
-	FPGA_GET_REG(dev, fpga_version, &fpga_version);
-	FPGA_GET_REG(dev, fpga_features, &fpga_features);
-
-	printf("FPGA%d: ", dev);
-	if (fpga_state & FPGA_STATE_PLATFORM)
-		printf("(legacy) ");
-
-	if (fpga_state & FPGA_STATE_DONE_FAILED) {
-		printf(" done timed out\n");
-		return;
-	}
-
-	if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
-		printf(" refelectione test failed\n");
-		return;
-	}
-
-	unit_type = (versions & 0xf000) >> 12;
-	hardware_version = versions & 0x000f;
-	feature_channels = fpga_features & 0x007f;
-	feature_expansion = fpga_features & (1<<15);
-
-	switch (unit_type) {
-	case UNITTYPE_CCD_SWITCH:
-		printf("CCD-Switch");
-		break;
-
-	default:
-		printf("UnitType %d(not supported)", unit_type);
-		break;
-	}
-
-	switch (hardware_version) {
-	case HWVER_100:
-		printf(" HW-Ver 1.00\n");
-		break;
-
-	case HWVER_110:
-		printf(" HW-Ver 1.10\n");
-		break;
-
-	default:
-		printf(" HW-Ver %d(not supported)\n",
-		       hardware_version);
-		break;
-	}
-
-	printf("       FPGA V %d.%02d, features:",
-		fpga_version / 100, fpga_version % 100);
-
-	printf(" %d channel(s)", feature_channels);
-
-	printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
-}
-
-int checkboard(void)
-{
-	char *s = getenv("serial#");
-
-	printf("Board: CATCenter Io64\n");
-
-	if (s != NULL) {
-		puts(", serial# ");
-		puts(s);
-	}
-
-	return 0;
-}
-
-int configure_gbit_phy(char *bus, unsigned char addr)
-{
-	unsigned short value;
-
-	/* select page 0 */
-	if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
-		goto err_out;
-	/* switch to powerdown */
-	if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
-		&value))
-		goto err_out;
-	if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
-		value | 0x0004))
-		goto err_out;
-	/* select page 2 */
-	if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
-		goto err_out;
-	/* disable SGMII autonegotiation */
-	if (miiphy_write(bus, addr, PHYREG_PG2_MAC_SPECIFIC_CONTROL, 48))
-		goto err_out;
-	/* select page 0 */
-	if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
-		goto err_out;
-	/* switch from powerdown to normal operation */
-	if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
-		&value))
-		goto err_out;
-	if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
-		value & ~0x0004))
-		goto err_out;
-	/* reset phy so settings take effect */
-	if (miiphy_write(bus, addr, PHYREG_CONTROL, 0x9140))
-		goto err_out;
-
-	return 0;
-
-err_out:
-	printf("Error writing to the PHY addr=%02x\n", addr);
-	return -1;
-}
-
-int verify_gbit_phy(char *bus, unsigned char addr)
-{
-	unsigned short value;
-
-	/* select page 2 */
-	if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
-		goto err_out;
-	/* verify SGMII link status */
-	if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value))
-		goto err_out;
-	if (!(value & (1 << 10)))
-		return -2;
-
-	return 0;
-
-err_out:
-	printf("Error writing to the PHY addr=%02x\n", addr);
-	return -1;
-}
-
-int last_stage_init(void)
-{
-	unsigned int k;
-	unsigned int fpga;
-	int failed = 0;
-	char str_phys[] = "Setup PHYs -";
-	char str_serdes[] = "Start SERDES blocks";
-	char str_channels[] = "Start FPGA channels";
-	char str_locks[] = "Verify SERDES locks";
-	char str_hicb[] = "Verify HICB status";
-	char str_status[] = "Verify PHY status -";
-	char slash[] = "\\|/-\\|/-";
-
-	print_fpga_info(0);
-	print_fpga_info(1);
-
-	/* setup Gbit PHYs */
-	puts("TRANS: ");
-	puts(str_phys);
-	int retval;
-	struct mii_dev *mdiodev = mdio_alloc();
-	if (!mdiodev)
-		return -ENOMEM;
-	strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN);
-	mdiodev->read = bb_miiphy_read;
-	mdiodev->write = bb_miiphy_write;
-
-	retval = mdio_register(mdiodev);
-	if (retval < 0)
-		return retval;
-
-	for (k = 0; k < 32; ++k) {
-		configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k);
-		putc('\b');
-		putc(slash[k % 8]);
-	}
-
-	mdiodev = mdio_alloc();
-	if (!mdiodev)
-		return -ENOMEM;
-	strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII1_BUSNAME, MDIO_NAME_LEN);
-	mdiodev->read = bb_miiphy_read;
-	mdiodev->write = bb_miiphy_write;
-
-	retval = mdio_register(mdiodev);
-	if (retval < 0)
-		return retval;
-
-	for (k = 0; k < 32; ++k) {
-		configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k);
-		putc('\b');
-		putc(slash[k % 8]);
-	}
-	blank_string(strlen(str_phys));
-
-	/* take fpga serdes blocks out of reset */
-	puts(str_serdes);
-	udelay(500000);
-	FPGA_SET_REG(0, quad_serdes_reset, 0);
-	FPGA_SET_REG(1, quad_serdes_reset, 0);
-	blank_string(strlen(str_serdes));
-
-	/* take channels out of reset */
-	puts(str_channels);
-	udelay(500000);
-	for (fpga = 0; fpga < 2; ++fpga) {
-		for (k = 0; k < 32; ++k)
-			FPGA_SET_REG(fpga, ch[k].config_int, 0);
-	}
-	blank_string(strlen(str_channels));
-
-	/* verify channels serdes lock */
-	puts(str_locks);
-	udelay(500000);
-	for (fpga = 0; fpga < 2; ++fpga) {
-		for (k = 0; k < 32; ++k) {
-			u16 status;
-			FPGA_GET_REG(fpga, ch[k].status_int, &status);
-			if (!(status & (1 << 4))) {
-				failed = 1;
-				printf("fpga %d channel %d: no serdes lock\n",
-					fpga, k);
-			}
-			/* reset events */
-			FPGA_SET_REG(fpga, ch[k].status_int, 0);
-		}
-	}
-	blank_string(strlen(str_locks));
-
-	/* verify hicb_status */
-	puts(str_hicb);
-	for (fpga = 0; fpga < 2; ++fpga) {
-		for (k = 0; k < 32; ++k) {
-			u16 status;
-			FPGA_GET_REG(fpga, hicb_ch[k].status_int, &status);
-			if (status)
-				printf("fpga %d hicb %d: hicb status %04x\n",
-					fpga, k, status);
-			/* reset events */
-			FPGA_SET_REG(fpga, hicb_ch[k].status_int, 0);
-		}
-	}
-	blank_string(strlen(str_hicb));
-
-	/* verify phy status */
-	puts(str_status);
-	for (k = 0; k < 32; ++k) {
-		if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) {
-			printf("verify baseboard phy %d failed\n", k);
-			failed = 1;
-		}
-		putc('\b');
-		putc(slash[k % 8]);
-	}
-	for (k = 0; k < 32; ++k) {
-		if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) {
-			printf("verify extensionboard phy %d failed\n", k);
-			failed = 1;
-		}
-		putc('\b');
-		putc(slash[k % 8]);
-	}
-	blank_string(strlen(str_status));
-
-	printf("Starting 64 channels %s\n", failed ? "failed" : "ok");
-
-	return 0;
-}
-
-void gd405ex_init(void)
-{
-	unsigned int k;
-
-	if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */
-		for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
-			gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
-	} else {
-		pca9698_direction_output(0x22, 39, 1);
-	}
-}
-
-void gd405ex_set_fpga_reset(unsigned state)
-{
-	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
-
-	if (legacy) {
-		if (state) {
-			out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
-			out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
-		} else {
-			out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
-			out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
-		}
-	} else {
-		pca9698_set_value(0x22, 39, state ? 0 : 1);
-	}
-}
-
-void gd405ex_setup_hw(void)
-{
-	gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0);
-	gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1);
-}
-
-int gd405ex_get_fpga_done(unsigned fpga)
-{
-	int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
-
-	if (legacy)
-		return in_le16((void *)LATCH3_BASE)
-			& CONFIG_SYS_FPGA_DONE(fpga);
-	else
-		return pca9698_get_value(0x22, fpga ? 9 : 8);
-}
diff --git a/board/gdsys/a38x/.gitignore b/board/gdsys/a38x/.gitignore
new file mode 100644
index 0000000..775b934
--- /dev/null
+++ b/board/gdsys/a38x/.gitignore
@@ -0,0 +1 @@
+kwbimage.cfg
diff --git a/board/gdsys/a38x/Kconfig b/board/gdsys/a38x/Kconfig
new file mode 100644
index 0000000..3fdef64
--- /dev/null
+++ b/board/gdsys/a38x/Kconfig
@@ -0,0 +1,36 @@
+if TARGET_CONTROLCENTERDC
+
+config SYS_BOARD
+	default "a38x"
+
+config SYS_VENDOR
+	default "gdsys"
+
+config SYS_SOC
+	default "mvebu"
+
+config SYS_CONFIG_NAME
+	default "controlcenterdc"
+
+menu "Controlcenter DC board options"
+
+choice
+	prompt "Select boot method"
+
+config SPL_BOOT_DEVICE_SPI
+	bool "SPI"
+
+config SPL_BOOT_DEVICE_MMC
+	bool "MMC"
+	select SPL_LIBDISK_SUPPORT
+
+endchoice
+
+#config SPL_BOOT_DEVICE
+#	int
+#	default 1 if SPL_BOOT_DEVICE_SPI
+#	default 2 if SPL_BOOT_DEVICE_MMC
+
+endmenu
+
+endif
diff --git a/board/gdsys/a38x/MAINTAINERS b/board/gdsys/a38x/MAINTAINERS
new file mode 100644
index 0000000..3cb9b63
--- /dev/null
+++ b/board/gdsys/a38x/MAINTAINERS
@@ -0,0 +1,7 @@
+A38X BOARD
+M:	Dirk Eibach <eibach@gdsys.cc>
+M:	Mario Six <six@gdsys.de>
+S:	Maintained
+F:	board/gdsys/a38x/
+F:	include/configs/controlcenterdc.h
+F:	configs/controlcenterdc_defconfig
diff --git a/board/gdsys/a38x/Makefile b/board/gdsys/a38x/Makefile
new file mode 100644
index 0000000..e1f0bd8
--- /dev/null
+++ b/board/gdsys/a38x/Makefile
@@ -0,0 +1,44 @@
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+# Copyright (C) 2015 Reinhard Pfau <reinhard.pfau@gdsys.cc>
+# Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_TARGET_CONTROLCENTERDC) += controlcenterdc.o hre.o spl.o keyprogram.o dt_helpers.o
+
+ifeq ($(CONFIG_SPL_BUILD),)
+
+obj-$(CONFIG_TARGET_CONTROLCENTERDC) += hydra.o ihs_phys.o
+
+extra-$(CONFIG_TARGET_CONTROLCENTERDC) += kwbimage.cfg
+
+KWB_REPLACE += BOOT_FROM
+ifneq ($(CONFIG_SPL_BOOT_DEVICE_SPI),)
+	KWB_CFG_BOOT_FROM=spi
+endif
+ifneq ($(CONFIG_SPL_BOOT_DEVICE_MMC),)
+	KWB_CFG_BOOT_FROM=sdio
+endif
+
+ifneq ($(CONFIG_SECURED_MODE_IMAGE),)
+KWB_REPLACE += CSK_INDEX
+KWB_CFG_CSK_INDEX = $(CONFIG_SECURED_MODE_CSK_INDEX)
+
+KWB_REPLACE += SEC_BOOT_DEV
+KWB_CFG_SEC_BOOT_DEV=$(patsubst "%",%, \
+	$(if $(findstring BOOT_SPI_NOR_FLASH,$(CONFIG_SPL_BOOT_DEVICE)),0x34) \
+	$(if $(findstring BOOT_SDIO_MMC_CARD,$(CONFIG_SPL_BOOT_DEVICE)),0x31) \
+	)
+
+KWB_REPLACE += SEC_FUSE_DUMP
+KWB_CFG_SEC_FUSE_DUMP = a38x
+endif
+
+$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
+		include/config/auto.conf
+	$(Q)sed -ne '$(foreach V,$(KWB_REPLACE),s/^#@$(V)/$(V) $(KWB_CFG_$(V))/;)p' \
+	<$< >$(dir $<)$(@F)
+
+endif
diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c
new file mode 100644
index 0000000..32168d3
--- /dev/null
+++ b/board/gdsys/a38x/controlcenterdc.c
@@ -0,0 +1,280 @@
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <miiphy.h>
+#include <tpm.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm-generic/gpio.h>
+
+#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
+
+#include "keyprogram.h"
+#include "dt_helpers.h"
+#include "hydra.h"
+#include "ihs_phys.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ETH_PHY_CTRL_REG		0
+#define ETH_PHY_CTRL_POWER_DOWN_BIT	11
+#define ETH_PHY_CTRL_POWER_DOWN_MASK	(1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
+
+#define DB_GP_88F68XX_GPP_OUT_ENA_LOW	0x7fffffff
+#define DB_GP_88F68XX_GPP_OUT_ENA_MID	0xffffefff
+
+#define DB_GP_88F68XX_GPP_OUT_VAL_LOW	0x0
+#define DB_GP_88F68XX_GPP_OUT_VAL_MID	0x00001000
+#define DB_GP_88F68XX_GPP_POL_LOW	0x0
+#define DB_GP_88F68XX_GPP_POL_MID	0x0
+
+/*
+ * Define the DDR layout / topology here in the board file. This will
+ * be used by the DDR3 init code in the SPL U-Boot version to configure
+ * the DDR3 controller.
+ */
+static struct hws_topology_map ddr_topology_map = {
+	0x1, /* active interfaces */
+	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
+	{ { { {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0},
+	      {0x1, 0, 0, 0} },
+	    SPEED_BIN_DDR_1600K,	/* speed_bin */
+	    BUS_WIDTH_16,		/* memory_width */
+	    MEM_4G,			/* mem_size */
+	    DDR_FREQ_533,		/* frequency */
+	    0, 0,			/* cas_l cas_wl */
+	    HWS_TEMP_LOW,		/* temperature */
+	    HWS_TIM_DEFAULT} },		/* timing */
+	5,				/* Num Of Bus Per Interface*/
+	BUS_MASK_32BIT			/* Busses mask */
+};
+
+static struct serdes_map serdes_topology_map[] = {
+	{SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	/* SATA tx polarity is inverted */
+	{SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1},
+	{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+	{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+	*serdes_map_array = serdes_topology_map;
+	*count = ARRAY_SIZE(serdes_topology_map);
+	return 0;
+}
+
+void board_pex_config(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	uint k;
+	struct gpio_desc gpio = {};
+
+	if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {
+		/* prepare FPGA reconfiguration */
+		dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
+		dm_gpio_set_value(&gpio, 0);
+
+		/* give lunatic PCIe clock some time to stabilize */
+		mdelay(500);
+
+		/* start FPGA reconfiguration */
+		dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN);
+	}
+
+	/* wait for FPGA done */
+	if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) {
+		for (k = 0; k < 20; ++k) {
+			if (dm_gpio_get_value(&gpio)) {
+				printf("FPGA done after %u rounds\n", k);
+				break;
+			}
+			mdelay(100);
+		}
+	}
+
+	/* disable FPGA reset */
+	if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) {
+		dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
+		dm_gpio_set_value(&gpio, 1);
+	}
+
+	/* wait for FPGA ready */
+	if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) {
+		for (k = 0; k < 2; ++k) {
+			if (!dm_gpio_get_value(&gpio))
+				break;
+			mdelay(100);
+		}
+	}
+#endif
+}
+
+struct hws_topology_map *ddr3_get_topology_map(void)
+{
+	return &ddr_topology_map;
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	/* Configure MPP */
+	writel(0x00111111, MVEBU_MPP_BASE + 0x00);
+	writel(0x40040000, MVEBU_MPP_BASE + 0x04);
+	writel(0x00466444, MVEBU_MPP_BASE + 0x08);
+	writel(0x00043300, MVEBU_MPP_BASE + 0x0c);
+	writel(0x44400000, MVEBU_MPP_BASE + 0x10);
+	writel(0x20000334, MVEBU_MPP_BASE + 0x14);
+	writel(0x40000000, MVEBU_MPP_BASE + 0x18);
+	writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
+
+	/* Set GPP Out value */
+	writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+void init_host_phys(struct mii_dev *bus)
+{
+	uint k;
+
+	for (k = 0; k < 2; ++k) {
+		struct phy_device *phydev;
+
+		phydev = phy_find_by_mask(bus, 1 << k,
+					  PHY_INTERFACE_MODE_SGMII);
+
+		if (phydev)
+			phy_config(phydev);
+	}
+}
+
+int ccdc_eth_init(void)
+{
+	uint k;
+	uint octo_phy_mask = 0;
+	int ret;
+	struct mii_dev *bus;
+
+	/* Init SoC's phys */
+	bus = miiphy_get_dev_by_name("ethernet@34000");
+
+	if (bus)
+		init_host_phys(bus);
+
+	bus = miiphy_get_dev_by_name("ethernet@70000");
+
+	if (bus)
+		init_host_phys(bus);
+
+	/* Init octo phys */
+	octo_phy_mask = calculate_octo_phy_mask();
+
+	printf("IHS PHYS: %08x", octo_phy_mask);
+
+	ret = init_octo_phys(octo_phy_mask);
+
+	if (ret)
+		return ret;
+
+	printf("\n");
+
+	if (!get_fpga()) {
+		puts("fpga was NULL\n");
+		return 1;
+	}
+
+	/* reset all FPGA-QSGMII instances */
+	for (k = 0; k < 80; ++k)
+		writel(1 << 31, get_fpga()->qsgmii_port_state[k]);
+
+	udelay(100);
+
+	for (k = 0; k < 80; ++k)
+		writel(0, get_fpga()->qsgmii_port_state[k]);
+	return 0;
+}
+
+#endif
+
+int board_late_init(void)
+{
+#ifndef CONFIG_SPL_BUILD
+	hydra_initialize();
+#endif
+	return 0;
+}
+
+int board_fix_fdt(void *rw_fdt_blob)
+{
+	struct udevice *bus = NULL;
+	uint k;
+	char name[64];
+	int err;
+
+	err = uclass_get_device_by_name(UCLASS_I2C, "i2c@11000", &bus);
+
+	if (err) {
+		printf("Could not get I2C bus.\n");
+		return err;
+	}
+
+	for (k = 0x21; k <= 0x26; k++) {
+		snprintf(name, 64,
+			 "/soc/internal-regs/i2c@11000/pca9698@%02x", k);
+
+		if (!dm_i2c_simple_probe(bus, k))
+			fdt_disable_by_ofname(rw_fdt_blob, name);
+	}
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+#ifndef CONFIG_SPL_BUILD
+	ccdc_eth_init();
+#endif
+	if (tpm_init() || tpm_startup(TPM_ST_CLEAR) ||
+	    tpm_continue_self_test()) {
+		return 1;
+	}
+
+	mdelay(37);
+
+	flush_keys();
+	load_and_run_keyprog();
+
+	return 0;
+}
diff --git a/board/gdsys/a38x/dt_helpers.c b/board/gdsys/a38x/dt_helpers.c
new file mode 100644
index 0000000..759d82a
--- /dev/null
+++ b/board/gdsys/a38x/dt_helpers.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+
+int fdt_disable_by_ofname(void *rw_fdt_blob, char *ofname)
+{
+	int offset = fdt_path_offset(rw_fdt_blob, ofname);
+
+	return fdt_status_disabled(rw_fdt_blob, offset);
+}
+
+bool dm_i2c_simple_probe(struct udevice *bus, uint chip_addr)
+{
+	struct udevice *dev;
+
+	return !dm_i2c_probe(bus, chip_addr, DM_I2C_CHIP_RD_ADDRESS |
+			     DM_I2C_CHIP_WR_ADDRESS, &dev);
+}
+
+int request_gpio_by_name(struct gpio_desc *gpio, const char *gpio_dev_name,
+			 uint offset, char *gpio_name)
+{
+	struct udevice *gpio_dev = NULL;
+
+	if (uclass_get_device_by_name(UCLASS_GPIO, gpio_dev_name, &gpio_dev))
+		return 1;
+
+	gpio->dev = gpio_dev;
+	gpio->offset = offset;
+	gpio->flags = 0;
+
+	return dm_gpio_request(gpio, gpio_name);
+}
+
diff --git a/board/gdsys/a38x/dt_helpers.h b/board/gdsys/a38x/dt_helpers.h
new file mode 100644
index 0000000..1b95262
--- /dev/null
+++ b/board/gdsys/a38x/dt_helpers.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __DT_HELPERS_H
+#define __DT_HELPERS_H
+
+int fdt_disable_by_ofname(void *rw_fdt_blob, char *ofname);
+bool dm_i2c_simple_probe(struct udevice *bus, uint chip_addr);
+int request_gpio_by_name(struct gpio_desc *gpio, const char *gpio_dev_name,
+			 uint offset, char *gpio_name);
+
+#endif /* __DT_HELPERS_H */
diff --git a/board/gdsys/a38x/hre.c b/board/gdsys/a38x/hre.c
new file mode 100644
index 0000000..1689d44
--- /dev/null
+++ b/board/gdsys/a38x/hre.c
@@ -0,0 +1,516 @@
+/*
+ * (C) Copyright 2013
+ * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <fs.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <tpm.h>
+#include <u-boot/sha1.h>
+#include <asm/byteorder.h>
+#include <asm/unaligned.h>
+#include <pca9698.h>
+
+#include "hre.h"
+
+/* other constants */
+enum {
+	ESDHC_BOOT_IMAGE_SIG_OFS	= 0x40,
+	ESDHC_BOOT_IMAGE_SIZE_OFS	= 0x48,
+	ESDHC_BOOT_IMAGE_ADDR_OFS	= 0x50,
+	ESDHC_BOOT_IMAGE_TARGET_OFS	= 0x58,
+	ESDHC_BOOT_IMAGE_ENTRY_OFS	= 0x60,
+};
+
+enum {
+	I2C_SOC_0 = 0,
+	I2C_SOC_1 = 1,
+};
+
+enum access_mode {
+	HREG_NONE	= 0,
+	HREG_RD		= 1,
+	HREG_WR		= 2,
+	HREG_RDWR	= 3,
+};
+
+/* register constants */
+enum {
+	FIX_HREG_DEVICE_ID_HASH	= 0,
+	FIX_HREG_UNUSED1	= 1,
+	FIX_HREG_UNUSED2	= 2,
+	FIX_HREG_VENDOR		= 3,
+	COUNT_FIX_HREGS
+};
+
+static struct h_reg pcr_hregs[24];
+static struct h_reg fix_hregs[COUNT_FIX_HREGS];
+static struct h_reg var_hregs[8];
+
+/* hre opcodes */
+enum {
+	/* opcodes w/o data */
+	HRE_NOP		= 0x00,
+	HRE_SYNC	= HRE_NOP,
+	HRE_CHECK0	= 0x01,
+	/* opcodes w/o data, w/ sync dst */
+	/* opcodes w/ data */
+	HRE_LOAD	= 0x81,
+	/* opcodes w/data, w/sync dst */
+	HRE_XOR		= 0xC1,
+	HRE_AND		= 0xC2,
+	HRE_OR		= 0xC3,
+	HRE_EXTEND	= 0xC4,
+	HRE_LOADKEY	= 0xC5,
+};
+
+/* hre errors */
+enum {
+	HRE_E_OK	= 0,
+	HRE_E_TPM_FAILURE,
+	HRE_E_INVALID_HREG,
+};
+
+static uint64_t device_id;
+static uint64_t device_cl;
+static uint64_t device_type;
+
+static uint32_t platform_key_handle;
+
+static uint32_t hre_tpm_err;
+static int hre_err = HRE_E_OK;
+
+#define IS_PCR_HREG(spec) ((spec) & 0x20)
+#define IS_FIX_HREG(spec) (((spec) & 0x38) == 0x08)
+#define IS_VAR_HREG(spec) (((spec) & 0x38) == 0x10)
+#define HREG_IDX(spec) ((spec) & (IS_PCR_HREG(spec) ? 0x1f : 0x7))
+
+static const uint8_t vendor[] = "Guntermann & Drunck";
+
+/**
+ * @brief get the size of a given (TPM) NV area
+ * @param index	NV index of the area to get size for
+ * @param size	pointer to the size
+ * @return 0 on success, != 0 on error
+ */
+static int get_tpm_nv_size(uint32_t index, uint32_t *size)
+{
+	uint32_t err;
+	uint8_t info[72];
+	uint8_t *ptr;
+	uint16_t v16;
+
+	err = tpm_get_capability(TPM_CAP_NV_INDEX, index,
+		info, sizeof(info));
+	if (err) {
+		printf("tpm_get_capability(CAP_NV_INDEX, %08x) failed: %u\n",
+		       index, err);
+		return 1;
+	}
+
+	/* skip tag and nvIndex */
+	ptr = info + 6;
+	/* skip 2 pcr info fields */
+	v16 = get_unaligned_be16(ptr);
+	ptr += 2 + v16 + 1 + 20;
+	v16 = get_unaligned_be16(ptr);
+	ptr += 2 + v16 + 1 + 20;
+	/* skip permission and flags */
+	ptr += 6 + 3;
+
+	*size = get_unaligned_be32(ptr);
+	return 0;
+}
+
+/**
+ * @brief search for a key by usage auth and pub key hash.
+ * @param auth	usage auth of the key to search for
+ * @param pubkey_digest	(SHA1) hash of the pub key structure of the key
+ * @param[out] handle	the handle of the key iff found
+ * @return 0 if key was found in TPM; != 0 if not.
+ */
+static int find_key(const uint8_t auth[20], const uint8_t pubkey_digest[20],
+		uint32_t *handle)
+{
+	uint16_t key_count;
+	uint32_t key_handles[10];
+	uint8_t buf[288];
+	uint8_t *ptr;
+	uint32_t err;
+	uint8_t digest[20];
+	size_t buf_len;
+	unsigned int i;
+
+	/* fetch list of already loaded keys in the TPM */
+	err = tpm_get_capability(TPM_CAP_HANDLE, TPM_RT_KEY, buf, sizeof(buf));
+	if (err)
+		return -1;
+	key_count = get_unaligned_be16(buf);
+	ptr = buf + 2;
+	for (i = 0; i < key_count; ++i, ptr += 4)
+		key_handles[i] = get_unaligned_be32(ptr);
+
+	/* now search a(/ the) key which we can access with the given auth */
+	for (i = 0; i < key_count; ++i) {
+		buf_len = sizeof(buf);
+		err = tpm_get_pub_key_oiap(key_handles[i], auth, buf, &buf_len);
+		if (err && err != TPM_AUTHFAIL)
+			return -1;
+		if (err)
+			continue;
+		sha1_csum(buf, buf_len, digest);
+		if (!memcmp(digest, pubkey_digest, 20)) {
+			*handle = key_handles[i];
+			return 0;
+		}
+	}
+	return 1;
+}
+
+/**
+ * @brief read CCDM common data from TPM NV
+ * @return 0 if CCDM common data was found and read, !=0 if something failed.
+ */
+static int read_common_data(void)
+{
+	uint32_t size = 0;
+	uint32_t err;
+	uint8_t buf[256];
+	sha1_context ctx;
+
+	if (get_tpm_nv_size(NV_COMMON_DATA_INDEX, &size) ||
+	    size < NV_COMMON_DATA_MIN_SIZE)
+		return 1;
+	err = tpm_nv_read_value(NV_COMMON_DATA_INDEX,
+		buf, min(sizeof(buf), size));
+	if (err) {
+		printf("tpm_nv_read_value() failed: %u\n", err);
+		return 1;
+	}
+
+	device_id = get_unaligned_be64(buf);
+	device_cl = get_unaligned_be64(buf + 8);
+	device_type = get_unaligned_be64(buf + 16);
+
+	sha1_starts(&ctx);
+	sha1_update(&ctx, buf, 24);
+	sha1_finish(&ctx, fix_hregs[FIX_HREG_DEVICE_ID_HASH].digest);
+	fix_hregs[FIX_HREG_DEVICE_ID_HASH].valid = true;
+
+	platform_key_handle = get_unaligned_be32(buf + 24);
+
+	return 0;
+}
+
+/**
+ * @brief get pointer to  hash register by specification
+ * @param spec	specification of a hash register
+ * @return pointer to hash register or NULL if @a spec does not qualify a
+ * valid hash register; NULL else.
+ */
+static struct h_reg *get_hreg(uint8_t spec)
+{
+	uint8_t idx;
+
+	idx = HREG_IDX(spec);
+	if (IS_FIX_HREG(spec)) {
+		if (idx < ARRAY_SIZE(fix_hregs))
+			return fix_hregs + idx;
+		hre_err = HRE_E_INVALID_HREG;
+	} else if (IS_PCR_HREG(spec)) {
+		if (idx < ARRAY_SIZE(pcr_hregs))
+			return pcr_hregs + idx;
+		hre_err = HRE_E_INVALID_HREG;
+	} else if (IS_VAR_HREG(spec)) {
+		if (idx < ARRAY_SIZE(var_hregs))
+			return var_hregs + idx;
+		hre_err = HRE_E_INVALID_HREG;
+	}
+	return NULL;
+}
+
+/**
+ * @brief get pointer of a hash register by specification and usage.
+ * @param spec	specification of a hash register
+ * @param mode	access mode (read or write or read/write)
+ * @return pointer to hash register if found and valid; NULL else.
+ *
+ * This func uses @a get_reg() to determine the hash register for a given spec.
+ * If a register is found it is validated according to the desired access mode.
+ * The value of automatic registers (PCR register and fixed registers) is
+ * loaded or computed on read access.
+ */
+static struct h_reg *access_hreg(uint8_t spec, enum access_mode mode)
+{
+	struct h_reg *result;
+
+	result = get_hreg(spec);
+	if (!result)
+		return NULL;
+
+	if (mode & HREG_WR) {
+		if (IS_FIX_HREG(spec)) {
+			hre_err = HRE_E_INVALID_HREG;
+			return NULL;
+		}
+	}
+	if (mode & HREG_RD) {
+		if (!result->valid) {
+			if (IS_PCR_HREG(spec)) {
+				hre_tpm_err = tpm_pcr_read(HREG_IDX(spec),
+					result->digest, 20);
+				result->valid = (hre_tpm_err == TPM_SUCCESS);
+			} else if (IS_FIX_HREG(spec)) {
+				switch (HREG_IDX(spec)) {
+				case FIX_HREG_DEVICE_ID_HASH:
+					read_common_data();
+					break;
+				case FIX_HREG_VENDOR:
+					memcpy(result->digest, vendor, 20);
+					result->valid = true;
+					break;
+				}
+			} else {
+				result->valid = true;
+			}
+		}
+		if (!result->valid) {
+			hre_err = HRE_E_INVALID_HREG;
+			return NULL;
+		}
+	}
+
+	return result;
+}
+
+static void *compute_and(void *_dst, const void *_src, size_t n)
+{
+	uint8_t *dst = _dst;
+	const uint8_t *src = _src;
+	size_t i;
+
+	for (i = n; i-- > 0; )
+		*dst++ &= *src++;
+
+	return _dst;
+}
+
+static void *compute_or(void *_dst, const void *_src, size_t n)
+{
+	uint8_t *dst = _dst;
+	const uint8_t *src = _src;
+	size_t i;
+
+	for (i = n; i-- > 0; )
+		*dst++ |= *src++;
+
+	return _dst;
+}
+
+static void *compute_xor(void *_dst, const void *_src, size_t n)
+{
+	uint8_t *dst = _dst;
+	const uint8_t *src = _src;
+	size_t i;
+
+	for (i = n; i-- > 0; )
+		*dst++ ^= *src++;
+
+	return _dst;
+}
+
+static void *compute_extend(void *_dst, const void *_src, size_t n)
+{
+	uint8_t digest[20];
+	sha1_context ctx;
+
+	sha1_starts(&ctx);
+	sha1_update(&ctx, _dst, n);
+	sha1_update(&ctx, _src, n);
+	sha1_finish(&ctx, digest);
+	memcpy(_dst, digest, min(n, sizeof(digest)));
+
+	return _dst;
+}
+
+static int hre_op_loadkey(struct h_reg *src_reg, struct h_reg *dst_reg,
+		const void *key, size_t key_size)
+{
+	uint32_t parent_handle;
+	uint32_t key_handle;
+
+	if (!src_reg || !dst_reg || !src_reg->valid || !dst_reg->valid)
+		return -1;
+	if (find_key(src_reg->digest, dst_reg->digest, &parent_handle))
+		return -1;
+	hre_tpm_err = tpm_load_key2_oiap(parent_handle, key, key_size,
+		src_reg->digest, &key_handle);
+	if (hre_tpm_err) {
+		hre_err = HRE_E_TPM_FAILURE;
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief executes the next opcode on the hash register engine.
+ * @param[in,out] ip	pointer to the opcode (instruction pointer)
+ * @param[in,out] code_size	(remaining) size of the code
+ * @return new instruction pointer on success, NULL on error.
+ */
+static const uint8_t *hre_execute_op(const uint8_t **ip, size_t *code_size)
+{
+	bool dst_modified = false;
+	uint32_t ins;
+	uint8_t opcode;
+	uint8_t src_spec;
+	uint8_t dst_spec;
+	uint16_t data_size;
+	struct h_reg *src_reg, *dst_reg;
+	uint8_t buf[20];
+	const uint8_t *src_buf, *data;
+	uint8_t *ptr;
+	int i;
+	void * (*bin_func)(void *, const void *, size_t);
+
+	if (*code_size < 4)
+		return NULL;
+
+	ins = get_unaligned_be32(*ip);
+	opcode = **ip;
+	data = *ip + 4;
+	src_spec = (ins >> 18) & 0x3f;
+	dst_spec = (ins >> 12) & 0x3f;
+	data_size = (ins & 0x7ff);
+
+	debug("HRE: ins=%08x (op=%02x, s=%02x, d=%02x, L=%d)\n", ins,
+	      opcode, src_spec, dst_spec, data_size);
+
+	if ((opcode & 0x80) && (data_size + 4) > *code_size)
+		return NULL;
+
+	src_reg = access_hreg(src_spec, HREG_RD);
+	if (hre_err || hre_tpm_err)
+		return NULL;
+	dst_reg = access_hreg(dst_spec, (opcode & 0x40) ? HREG_RDWR : HREG_WR);
+	if (hre_err || hre_tpm_err)
+		return NULL;
+
+	switch (opcode) {
+	case HRE_NOP:
+		goto end;
+	case HRE_CHECK0:
+		if (src_reg) {
+			for (i = 0; i < 20; ++i) {
+				if (src_reg->digest[i])
+					return NULL;
+			}
+		}
+		break;
+	case HRE_LOAD:
+		bin_func = memcpy;
+		goto do_bin_func;
+	case HRE_XOR:
+		bin_func = compute_xor;
+		goto do_bin_func;
+	case HRE_AND:
+		bin_func = compute_and;
+		goto do_bin_func;
+	case HRE_OR:
+		bin_func = compute_or;
+		goto do_bin_func;
+	case HRE_EXTEND:
+		bin_func = compute_extend;
+do_bin_func:
+		if (!dst_reg)
+			return NULL;
+		if (src_reg) {
+			src_buf = src_reg->digest;
+		} else {
+			if (!data_size) {
+				memset(buf, 0, 20);
+				src_buf = buf;
+			} else if (data_size == 1) {
+				memset(buf, *data, 20);
+				src_buf = buf;
+			} else if (data_size >= 20) {
+				src_buf = data;
+			} else {
+				src_buf = buf;
+				for (ptr = (uint8_t *)src_buf, i = 20; i > 0;
+					i -= data_size, ptr += data_size)
+					memcpy(ptr, data,
+					       min_t(size_t, i, data_size));
+			}
+		}
+		bin_func(dst_reg->digest, src_buf, 20);
+		dst_reg->valid = true;
+		dst_modified = true;
+		break;
+	case HRE_LOADKEY:
+		if (hre_op_loadkey(src_reg, dst_reg, data, data_size))
+			return NULL;
+		break;
+	default:
+		return NULL;
+	}
+
+	if (dst_reg && dst_modified && IS_PCR_HREG(dst_spec)) {
+		hre_tpm_err = tpm_extend(HREG_IDX(dst_spec), dst_reg->digest,
+			dst_reg->digest);
+		if (hre_tpm_err) {
+			hre_err = HRE_E_TPM_FAILURE;
+			return NULL;
+		}
+	}
+end:
+	*ip += 4;
+	*code_size -= 4;
+	if (opcode & 0x80) {
+		*ip += data_size;
+		*code_size -= data_size;
+	}
+
+	return *ip;
+}
+
+/**
+ * @brief runs a program on the hash register engine.
+ * @param code		pointer to the (HRE) code.
+ * @param code_size	size of the code (in bytes).
+ * @return 0 on success, != 0 on failure.
+ */
+int hre_run_program(const uint8_t *code, size_t code_size)
+{
+	size_t code_left;
+	const uint8_t *ip = code;
+
+	code_left = code_size;
+	hre_tpm_err = 0;
+	hre_err = HRE_E_OK;
+	while (code_left > 0)
+		if (!hre_execute_op(&ip, &code_left))
+			return -1;
+
+	return hre_err;
+}
+
+int hre_verify_program(struct key_program *prg)
+{
+	uint32_t crc;
+
+	crc = crc32(0, prg->code, prg->code_size);
+
+	if (crc != prg->code_crc) {
+		printf("HRC crc mismatch: %08x != %08x\n",
+		       crc, prg->code_crc);
+		return 1;
+	}
+	return 0;
+}
diff --git a/board/gdsys/a38x/hre.h b/board/gdsys/a38x/hre.h
new file mode 100644
index 0000000..84ce279
--- /dev/null
+++ b/board/gdsys/a38x/hre.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2013
+ * Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __HRE_H
+#define __HRE_H
+
+struct key_program {
+	uint32_t magic;
+	uint32_t code_crc;
+	uint32_t code_size;
+	uint8_t code[];
+};
+
+struct h_reg {
+	bool valid;
+	uint8_t digest[20];
+};
+
+/* CCDM specific contants */
+enum {
+	/* NV indices */
+	NV_COMMON_DATA_INDEX	= 0x40000001,
+	/* magics for key blob chains */
+	MAGIC_KEY_PROGRAM	= 0x68726500,
+	MAGIC_HMAC		= 0x68616300,
+	MAGIC_END_OF_CHAIN	= 0x00000000,
+	/* sizes */
+	NV_COMMON_DATA_MIN_SIZE	= 3 * sizeof(uint64_t) + 2 * sizeof(uint16_t),
+};
+
+int hre_verify_program(struct key_program *prg);
+int hre_run_program(const uint8_t *code, size_t code_size);
+
+#endif /* __HRE_H */
diff --git a/board/gdsys/a38x/hydra.c b/board/gdsys/a38x/hydra.c
new file mode 100644
index 0000000..fa50ad2
--- /dev/null
+++ b/board/gdsys/a38x/hydra.c
@@ -0,0 +1,138 @@
+#include <common.h>
+#include <console.h> /* ctrlc */
+#include <asm/io.h>
+
+#include "hydra.h"
+
+enum {
+	HWVER_100 = 0,
+	HWVER_110 = 1,
+	HWVER_120 = 2,
+};
+
+static struct pci_device_id hydra_supported[] = {
+	{ 0x6d5e, 0xcdc1 },
+	{}
+};
+
+static struct ihs_fpga *fpga;
+
+struct ihs_fpga *get_fpga(void)
+{
+	return fpga;
+}
+
+void print_hydra_version(uint index)
+{
+	u32 versions = readl(&fpga->versions);
+	u32 fpga_version = readl(&fpga->fpga_version);
+
+	uint hardware_version = versions & 0xf;
+
+	printf("FPGA%u: mapped to %p\n       ", index, fpga);
+
+	switch (hardware_version) {
+	case HWVER_100:
+		printf("HW-Ver 1.00\n");
+		break;
+
+	case HWVER_110:
+		printf("HW-Ver 1.10\n");
+		break;
+
+	case HWVER_120:
+		printf("HW-Ver 1.20\n");
+		break;
+
+	default:
+		printf("HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d\n",
+	       fpga_version / 100, fpga_version % 100);
+}
+
+void hydra_initialize(void)
+{
+	uint i;
+	pci_dev_t devno;
+
+	/* Find and probe all the matching PCI devices */
+	for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
+		u32 val;
+
+		/* Try to enable I/O accesses and bus-mastering */
+		val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+		pci_write_config_dword(devno, PCI_COMMAND, val);
+
+		/* Make sure it worked */
+		pci_read_config_dword(devno, PCI_COMMAND, &val);
+		if (!(val & PCI_COMMAND_MEMORY)) {
+			puts("Can't enable I/O memory\n");
+			continue;
+		}
+		if (!(val & PCI_COMMAND_MASTER)) {
+			puts("Can't enable bus-mastering\n");
+			continue;
+		}
+
+		/* read FPGA details */
+		fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
+				   PCI_REGION_MEM);
+
+		print_hydra_version(i);
+	}
+}
+
+#define REFL_PATTERN (0xdededede)
+#define REFL_PATTERN_INV (~REFL_PATTERN)
+
+int do_hydrate(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	uint k = 0;
+	void __iomem *pcie2_base = (void __iomem *)(MVEBU_REG_PCIE_BASE +
+						    0x4000);
+
+	if (!fpga)
+		return -1;
+
+	while (1) {
+		u32 res;
+
+		writel(REFL_PATTERN, &fpga->reflection_low);
+		res = readl(&fpga->reflection_low);
+		if (res != REFL_PATTERN_INV)
+			printf("round %u: read %08x, expected %08x\n",
+			       k, res, REFL_PATTERN_INV);
+		writel(REFL_PATTERN_INV, &fpga->reflection_low);
+		res = readl(&fpga->reflection_low);
+		if (res != REFL_PATTERN)
+			printf("round %u: read %08x, expected %08x\n",
+			       k, res, REFL_PATTERN);
+
+		res = readl(pcie2_base + 0x118) & 0x1f;
+		if (res)
+			printf("FrstErrPtr %u\n", res);
+		res = readl(pcie2_base + 0x104);
+		if (res) {
+			printf("Uncorrectable Error Status 0x%08x\n", res);
+			writel(res, pcie2_base + 0x104);
+		}
+
+		if (!(++k % 10000))
+			printf("round %u\n", k);
+
+		if (ctrlc())
+			break;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	hydrate,	1,	0,	do_hydrate,
+	"hydra reflection test",
+	"hydra reflection test"
+);
diff --git a/board/gdsys/a38x/hydra.h b/board/gdsys/a38x/hydra.h
new file mode 100644
index 0000000..26562a5
--- /dev/null
+++ b/board/gdsys/a38x/hydra.h
@@ -0,0 +1,14 @@
+struct ihs_fpga {
+	u32 reflection_low;		/* 0x0000 */
+	u32 versions;			/* 0x0004 */
+	u32 fpga_version;		/* 0x0008 */
+	u32 fpga_features;		/* 0x000c */
+	u32 reserved0[4];		/* 0x0010 */
+	u32 control;			/* 0x0020 */
+	u32 reserved1[375];		/* 0x0024 */
+	u32 qsgmii_port_state[80];	/* 0x0600 */
+};
+
+void print_hydra_version(uint index);
+void hydra_initialize(void);
+struct ihs_fpga *get_fpga(void);
diff --git a/board/gdsys/a38x/ihs_phys.c b/board/gdsys/a38x/ihs_phys.c
new file mode 100644
index 0000000..494de18
--- /dev/null
+++ b/board/gdsys/a38x/ihs_phys.c
@@ -0,0 +1,355 @@
+#include <common.h>
+#include <dm.h>
+#include <miiphy.h>
+#include <asm-generic/gpio.h>
+
+#include "ihs_phys.h"
+#include "dt_helpers.h"
+
+enum {
+	PORTTYPE_MAIN_CAT,
+	PORTTYPE_TOP_CAT,
+	PORTTYPE_16C_16F,
+	PORTTYPE_UNKNOWN
+};
+
+static struct porttype {
+	bool phy_invert_in_pol;
+	bool phy_invert_out_pol;
+} porttypes[] = {
+	{ true, false },
+	{ false, true },
+	{ false, false },
+};
+
+static void ihs_phy_config(struct phy_device *phydev, bool qinpn, bool qoutpn)
+{
+	u16 reg;
+
+	phy_config(phydev);
+
+	/* enable QSGMII autonegotiation with flow control */
+	phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0004);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 16);
+	reg |= (3 << 6);
+	phy_write(phydev, MDIO_DEVAD_NONE, 16, reg);
+
+	/*
+	 * invert QSGMII Q_INP/N and Q_OUTP/N if required
+	 * and perform global reset
+	 */
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 26);
+	if (qinpn)
+		reg |= (1 << 13);
+	if (qoutpn)
+		reg |= (1 << 12);
+	reg |= (1 << 15);
+	phy_write(phydev, MDIO_DEVAD_NONE, 26, reg);
+
+	/* advertise 1000BASE-T full-duplex only  */
+	phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 4);
+	reg &= ~0x1e0;
+	phy_write(phydev, MDIO_DEVAD_NONE, 4, reg);
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 9);
+	reg = (reg & ~0x300) | 0x200;
+	phy_write(phydev, MDIO_DEVAD_NONE, 9, reg);
+
+	/* copper power up */
+	reg = phy_read(phydev, MDIO_DEVAD_NONE, 16);
+	reg &= ~0x0004;
+	phy_write(phydev, MDIO_DEVAD_NONE, 16, reg);
+}
+
+uint calculate_octo_phy_mask(void)
+{
+	uint k;
+	uint octo_phy_mask = 0;
+	struct gpio_desc gpio = {};
+	char gpio_name[64];
+	static const char * const dev_name[] = {"pca9698@23", "pca9698@21",
+						"pca9698@24", "pca9698@25",
+						"pca9698@26"};
+
+	/* mark all octo phys that should be present */
+	for (k = 0; k < 5; ++k) {
+		snprintf(gpio_name, 64, "cat-gpio-%u", k);
+
+		if (request_gpio_by_name(&gpio, dev_name[k], 0x20, gpio_name))
+			continue;
+
+		/* check CAT flag */
+		if (dm_gpio_get_value(&gpio))
+			octo_phy_mask |= (1 << (k * 2));
+		else
+			/* If CAT == 0, there's no second octo phy -> skip */
+			continue;
+
+		snprintf(gpio_name, 64, "second-octo-gpio-%u", k);
+
+		if (request_gpio_by_name(&gpio, dev_name[k], 0x27, gpio_name)) {
+			/* default: second octo phy is present */
+			octo_phy_mask |= (1 << (k * 2 + 1));
+			continue;
+		}
+
+		if (dm_gpio_get_value(&gpio) == 0)
+			octo_phy_mask |= (1 << (k * 2 + 1));
+	}
+
+	return octo_phy_mask;
+}
+
+int register_miiphy_bus(uint k, struct mii_dev **bus)
+{
+	int retval;
+	struct mii_dev *mdiodev = mdio_alloc();
+	char *name = bb_miiphy_buses[k].name;
+
+	if (!mdiodev)
+		return -ENOMEM;
+	strncpy(mdiodev->name,
+		name,
+		MDIO_NAME_LEN);
+	mdiodev->read = bb_miiphy_read;
+	mdiodev->write = bb_miiphy_write;
+
+	retval = mdio_register(mdiodev);
+	if (retval < 0)
+		return retval;
+	*bus = miiphy_get_dev_by_name(name);
+
+	return 0;
+}
+
+struct porttype *get_porttype(uint octo_phy_mask, uint k)
+{
+	uint octo_index = k * 4;
+
+	if (!k) {
+		if (octo_phy_mask & 0x01)
+			return &porttypes[PORTTYPE_MAIN_CAT];
+		else if (!(octo_phy_mask & 0x03))
+			return &porttypes[PORTTYPE_16C_16F];
+	} else {
+		if (octo_phy_mask & (1 << octo_index))
+			return &porttypes[PORTTYPE_TOP_CAT];
+	}
+
+	return NULL;
+}
+
+int init_single_phy(struct porttype *porttype, struct mii_dev *bus,
+		    uint bus_idx, uint m, uint phy_idx)
+{
+	struct phy_device *phydev = phy_find_by_mask(
+		bus, 1 << (m * 8 + phy_idx),
+		PHY_INTERFACE_MODE_MII);
+
+	printf(" %u", bus_idx * 32 + m * 8 + phy_idx);
+
+	if (!phydev)
+		puts("!");
+	else
+		ihs_phy_config(phydev, porttype->phy_invert_in_pol,
+			       porttype->phy_invert_out_pol);
+
+	return 0;
+}
+
+int init_octo_phys(uint octo_phy_mask)
+{
+	uint bus_idx;
+
+	/* there are up to four octo-phys on each mdio bus */
+	for (bus_idx = 0; bus_idx < bb_miiphy_buses_num; ++bus_idx) {
+		uint m;
+		uint octo_index = bus_idx * 4;
+		struct mii_dev *bus = NULL;
+		struct porttype *porttype = NULL;
+		int ret;
+
+		porttype = get_porttype(octo_phy_mask, bus_idx);
+
+		if (!porttype)
+			continue;
+
+		for (m = 0; m < 4; ++m) {
+			uint phy_idx;
+
+			/**
+			 * Register a bus device if there is at least one phy
+			 * on the current bus
+			 */
+			if (!m && octo_phy_mask & (0xf << octo_index)) {
+				ret = register_miiphy_bus(bus_idx, &bus);
+				if (ret)
+					return ret;
+			}
+
+			if (!(octo_phy_mask & BIT(octo_index + m)))
+				continue;
+
+			for (phy_idx = 0; phy_idx < 8; ++phy_idx)
+				init_single_phy(porttype, bus, bus_idx, m,
+						phy_idx);
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * MII GPIO bitbang implementation
+ * MDC MDIO bus
+ * 13  14   PHY1-4
+ * 25  45   PHY5-8
+ * 46  24   PHY9-10
+ */
+
+struct gpio_mii {
+	int index;
+	struct gpio_desc mdc_gpio;
+	struct gpio_desc mdio_gpio;
+	int mdc_num;
+	int mdio_num;
+	int mdio_value;
+} gpio_mii_set[] = {
+	{ 0, {}, {}, 13, 14, 1 },
+	{ 1, {}, {}, 25, 45, 1 },
+	{ 2, {}, {}, 46, 24, 1 },
+};
+
+static int mii_mdio_init(struct bb_miiphy_bus *bus)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+	char name[32] = {};
+	struct udevice *gpio_dev1 = NULL;
+	struct udevice *gpio_dev2 = NULL;
+
+	if (uclass_get_device_by_name(UCLASS_GPIO, "gpio@18100", &gpio_dev1) ||
+	    uclass_get_device_by_name(UCLASS_GPIO, "gpio@18140", &gpio_dev2)) {
+		printf("Could not get GPIO device.\n");
+		return 1;
+	}
+
+	if (gpio_mii->mdc_num > 31) {
+		gpio_mii->mdc_gpio.dev = gpio_dev2;
+		gpio_mii->mdc_gpio.offset = gpio_mii->mdc_num - 32;
+	} else {
+		gpio_mii->mdc_gpio.dev = gpio_dev1;
+		gpio_mii->mdc_gpio.offset = gpio_mii->mdc_num;
+	}
+	gpio_mii->mdc_gpio.flags = 0;
+	snprintf(name, 32, "bb_miiphy_bus-%d-mdc", gpio_mii->index);
+	dm_gpio_request(&gpio_mii->mdc_gpio, name);
+
+	if (gpio_mii->mdio_num > 31) {
+		gpio_mii->mdio_gpio.dev = gpio_dev2;
+		gpio_mii->mdio_gpio.offset = gpio_mii->mdio_num - 32;
+	} else {
+		gpio_mii->mdio_gpio.dev = gpio_dev1;
+		gpio_mii->mdio_gpio.offset = gpio_mii->mdio_num;
+	}
+	gpio_mii->mdio_gpio.flags = 0;
+	snprintf(name, 32, "bb_miiphy_bus-%d-mdio", gpio_mii->index);
+	dm_gpio_request(&gpio_mii->mdio_gpio, name);
+
+	dm_gpio_set_dir_flags(&gpio_mii->mdc_gpio, GPIOD_IS_OUT);
+	dm_gpio_set_value(&gpio_mii->mdc_gpio, 1);
+
+	return 0;
+}
+
+static int mii_mdio_active(struct bb_miiphy_bus *bus)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+
+	dm_gpio_set_value(&gpio_mii->mdc_gpio, gpio_mii->mdio_value);
+
+	return 0;
+}
+
+static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+
+	dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_IN);
+
+	return 0;
+}
+
+static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+
+	dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_OUT);
+	dm_gpio_set_value(&gpio_mii->mdio_gpio, v);
+	gpio_mii->mdio_value = v;
+
+	return 0;
+}
+
+static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+
+	dm_gpio_set_dir_flags(&gpio_mii->mdio_gpio, GPIOD_IS_IN);
+	*v = (dm_gpio_get_value(&gpio_mii->mdio_gpio));
+
+	return 0;
+}
+
+static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
+{
+	struct gpio_mii *gpio_mii = bus->priv;
+
+	dm_gpio_set_value(&gpio_mii->mdc_gpio, v);
+
+	return 0;
+}
+
+static int mii_delay(struct bb_miiphy_bus *bus)
+{
+	udelay(1);
+
+	return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+	{
+		.name = "ihs0",
+		.init = mii_mdio_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &gpio_mii_set[0],
+	},
+	{
+		.name = "ihs1",
+		.init = mii_mdio_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &gpio_mii_set[1],
+	},
+	{
+		.name = "ihs2",
+		.init = mii_mdio_init,
+		.mdio_active = mii_mdio_active,
+		.mdio_tristate = mii_mdio_tristate,
+		.set_mdio = mii_set_mdio,
+		.get_mdio = mii_get_mdio,
+		.set_mdc = mii_set_mdc,
+		.delay = mii_delay,
+		.priv = &gpio_mii_set[2],
+	},
+};
+
+int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
diff --git a/board/gdsys/a38x/ihs_phys.h b/board/gdsys/a38x/ihs_phys.h
new file mode 100644
index 0000000..c4bec4d
--- /dev/null
+++ b/board/gdsys/a38x/ihs_phys.h
@@ -0,0 +1,2 @@
+uint calculate_octo_phy_mask(void);
+int init_octo_phys(uint octo_phy_mask);
diff --git a/board/gdsys/a38x/keyprogram.c b/board/gdsys/a38x/keyprogram.c
new file mode 100644
index 0000000..a4a6f1c
--- /dev/null
+++ b/board/gdsys/a38x/keyprogram.c
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <tpm.h>
+#include <malloc.h>
+#include <linux/ctype.h>
+#include <asm/unaligned.h>
+
+#include "hre.h"
+
+int flush_keys(void)
+{
+	u16 key_count;
+	u8 buf[288];
+	u8 *ptr;
+	u32 err;
+	uint i;
+
+	/* fetch list of already loaded keys in the TPM */
+	err = tpm_get_capability(TPM_CAP_HANDLE, TPM_RT_KEY, buf, sizeof(buf));
+	if (err)
+		return -1;
+	key_count = get_unaligned_be16(buf);
+	ptr = buf + 2;
+	for (i = 0; i < key_count; ++i, ptr += 4) {
+		err = tpm_flush_specific(get_unaligned_be32(ptr), TPM_RT_KEY);
+		if (err && err != TPM_KEY_OWNER_CONTROL)
+			return err;
+	}
+
+	return 0;
+}
+
+int decode_hexstr(char *hexstr, u8 **result)
+{
+	int len = strlen(hexstr);
+	int bytes = len / 2;
+	int i;
+	u8 acc = 0;
+
+	if (len % 2 == 1)
+		return 1;
+
+	*result = (u8 *)malloc(bytes);
+
+	for (i = 0; i < len; i++) {
+		char cur = tolower(hexstr[i]);
+		u8 val;
+
+		if ((cur >= 'a' && cur <= 'f') || (cur >= '0' && cur <= '9')) {
+			val = cur - (cur > '9' ? 87 : 48);
+
+			if (i % 2 == 0)
+				acc = 16 * val;
+			else
+				(*result)[i / 2] = acc + val;
+		} else {
+			free(*result);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+int extract_subprogram(u8 **progdata, u32 expected_magic,
+		       struct key_program **result)
+{
+	struct key_program *prog = *result;
+	u32 magic, code_crc, code_size;
+
+	magic = get_unaligned_be32(*progdata);
+	code_crc = get_unaligned_be32(*progdata + 4);
+	code_size = get_unaligned_be32(*progdata + 8);
+
+	*progdata += 12;
+
+	if (magic != expected_magic)
+		return -1;
+
+	*result = malloc(sizeof(struct key_program) + code_size);
+
+	if (!*result)
+		return -1;
+
+	prog->magic = magic;
+	prog->code_crc = code_crc;
+	prog->code_size = code_size;
+	memcpy(prog->code, *progdata, code_size);
+
+	*progdata += code_size;
+
+	if (hre_verify_program(prog)) {
+		free(prog);
+		return -1;
+	}
+
+	return 0;
+}
+
+struct key_program *parse_and_check_keyprog(u8 *progdata)
+{
+	struct key_program *result = NULL, *hmac = NULL;
+
+	/* Part 1: Load key program */
+
+	if (extract_subprogram(&progdata, MAGIC_KEY_PROGRAM, &result))
+		return NULL;
+
+	/* Part 2: Load hmac program */
+
+	if (extract_subprogram(&progdata, MAGIC_HMAC, &hmac))
+		return NULL;
+
+	free(hmac);
+
+	return result;
+}
+
+int load_and_run_keyprog(void)
+{
+	char *cmd = NULL;
+	u8 *binprog = NULL;
+	char *hexprog;
+	struct key_program *prog;
+
+	cmd = getenv("loadkeyprogram");
+
+	if (!cmd || run_command(cmd, 0))
+		return 1;
+
+	hexprog = getenv("keyprogram");
+
+	if (decode_hexstr(hexprog, &binprog))
+		return 1;
+
+	prog = parse_and_check_keyprog(binprog);
+	free(binprog);
+
+	if (!prog)
+		return 1;
+
+	if (hre_run_program(prog->code, prog->code_size)) {
+		free(prog);
+		return 1;
+	}
+
+	printf("\nSD code ran successfully\n");
+
+	free(prog);
+
+	return 0;
+}
diff --git a/board/gdsys/a38x/keyprogram.h b/board/gdsys/a38x/keyprogram.h
new file mode 100644
index 0000000..a5ea7d3
--- /dev/null
+++ b/board/gdsys/a38x/keyprogram.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __KEYPROGRAM_H
+#define __KEYPROGRAM_H
+
+int load_and_run_keyprog(void);
+int flush_keys(void);
+
+#endif /* __KEYPROGRAM_H */
diff --git a/board/gdsys/a38x/kwbimage.cfg.in b/board/gdsys/a38x/kwbimage.cfg.in
new file mode 100644
index 0000000..72e67d7
--- /dev/null
+++ b/board/gdsys/a38x/kwbimage.cfg.in
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada 38x uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+#@BOOT_FROM
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl.bin 0000005b 00000068
diff --git a/board/gdsys/a38x/spl.c b/board/gdsys/a38x/spl.c
new file mode 100644
index 0000000..2d05a9c
--- /dev/null
+++ b/board/gdsys/a38x/spl.c
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/arch/cpu.h>
+
+void spl_board_init(void)
+{
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
+	u32 *bootrom_save = (u32 *)CONFIG_SPL_BOOTROM_SAVE;
+	u32 *regs = (u32 *)(*bootrom_save);
+
+	printf("Returning to BootROM (return address %08x)...\n", regs[13]);
+	return_to_bootrom();
+#endif
+}
diff --git a/board/gdsys/dlvision/Kconfig b/board/gdsys/dlvision/Kconfig
deleted file mode 100644
index 8db4fbe..0000000
--- a/board/gdsys/dlvision/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DLVISION
-
-config SYS_BOARD
-	default "dlvision"
-
-config SYS_VENDOR
-	default "gdsys"
-
-config SYS_CONFIG_NAME
-	default "dlvision"
-
-endif
diff --git a/board/gdsys/dlvision/MAINTAINERS b/board/gdsys/dlvision/MAINTAINERS
deleted file mode 100644
index e4d40f8..0000000
--- a/board/gdsys/dlvision/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-DLVISION BOARD
-M:	Dirk Eibach <eibach@gdsys.de>
-S:	Maintained
-F:	board/gdsys/dlvision/
-F:	include/configs/dlvision.h
-F:	configs/dlvision_defconfig
diff --git a/board/gdsys/dlvision/Makefile b/board/gdsys/dlvision/Makefile
deleted file mode 100644
index 755eb4c..0000000
--- a/board/gdsys/dlvision/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= dlvision.o
diff --git a/board/gdsys/dlvision/dlvision.c b/board/gdsys/dlvision/dlvision.c
deleted file mode 100644
index 32f7ba3..0000000
--- a/board/gdsys/dlvision/dlvision.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * (C) Copyright 2009
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-enum {
-	HWTYPE_DLVISION_CPU = 0,
-	HWTYPE_DLVISION_CON = 1,
-};
-
-#define HWREV_100	6
-
-int board_early_init_f(void)
-{
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
-	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
-	mtdcr(UIC0PR, 0xFFFFFF80);	/* set int polarities */
-	mtdcr(UIC0TR, 0x10000000);	/* set int trigger levels */
-	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest prio */
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-
-	/*
-	 * EBC Configuration Register: set ready timeout to 512 ebc-clks
-	 * -> ca. 15 us
-	 */
-	mtebc(EBC0_CFG, 0xa8400000);	/* ebc always driven */
-
-	/*
-	 * setup io-latches
-	 */
-	out_le16((void *)CONFIG_SYS_LATCH_BASE, 0x00f0);
-	out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x100), 0x0002);
-	out_le16((void *)(CONFIG_SYS_LATCH_BASE + 0x200), 0x0000);
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	/*
-	 * set "startup-finished"-gpios
-	 */
-	gpio_write_bit(21, 0);
-	gpio_write_bit(22, 1);
-
-	return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-	u8 channel2_msr = in_8((void *)CONFIG_UART_BASE + 0x26);
-	u8 channel3_msr = in_8((void *)CONFIG_UART_BASE + 0x36);
-	u8 channel7_msr = in_8((void *)CONFIG_UART_BASE + 0x76);
-	u8 unit_type;
-	u8 local_con;
-	u8 audio;
-	u8 hardware_version;
-
-	printf("Board: ");
-
-	unit_type = (channel2_msr & 0x80) ? 0x01 : 0x00;
-	local_con = (channel2_msr & 0x20) ? 0x01 : 0x00;
-	audio = (channel3_msr & 0x20) ? 0x01 : 0x00;
-	hardware_version =
-		  ((channel7_msr & 0x20) ? 0x01 : 0x00)
-		| ((channel7_msr & 0x80) ? 0x02 : 0x00)
-		| ((channel7_msr & 0x40) ? 0x04 : 0x00);
-
-	switch (unit_type) {
-	case HWTYPE_DLVISION_CON:
-		printf("DL-Vision-CON");
-		break;
-
-	case HWTYPE_DLVISION_CPU:
-		printf("DL-Vision-CPU");
-		break;
-
-	default:
-		printf("UnitType %d, unsupported", unit_type);
-		break;
-	}
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	puts("\n       ");
-
-	switch (hardware_version) {
-	case HWREV_100:
-		printf("HW-Ver 1.00");
-		break;
-
-	default:
-		printf("HW-Ver %d, unsupported",
-		       hardware_version);
-		break;
-	}
-
-	if (local_con)
-		printf(", local console");
-
-	if (audio)
-		printf(", audio support");
-
-	puts("\n");
-
-	return 0;
-}
diff --git a/board/gdsys/gdppc440etx/Kconfig b/board/gdsys/gdppc440etx/Kconfig
deleted file mode 100644
index 1f21c89..0000000
--- a/board/gdsys/gdppc440etx/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_GDPPC440ETX
-
-config SYS_BOARD
-	default "gdppc440etx"
-
-config SYS_VENDOR
-	default "gdsys"
-
-config SYS_CONFIG_NAME
-	default "gdppc440etx"
-
-endif
diff --git a/board/gdsys/gdppc440etx/MAINTAINERS b/board/gdsys/gdppc440etx/MAINTAINERS
deleted file mode 100644
index cd8d1c6..0000000
--- a/board/gdsys/gdppc440etx/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-GDPPC440ETX BOARD
-M:	Dirk Eibach <eibach@gdsys.de>
-S:	Maintained
-F:	board/gdsys/gdppc440etx/
-F:	include/configs/gdppc440etx.h
-F:	configs/gdppc440etx_defconfig
diff --git a/board/gdsys/gdppc440etx/Makefile b/board/gdsys/gdppc440etx/Makefile
deleted file mode 100644
index 7e3fc38..0000000
--- a/board/gdsys/gdppc440etx/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= gdppc440etx.o
-extra-y	+= init.o
diff --git a/board/gdsys/gdppc440etx/config.mk b/board/gdsys/gdppc440etx/config.mk
deleted file mode 100644
index 73341a5..0000000
--- a/board/gdsys/gdppc440etx/config.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-#
-# G&D 440EP/GR ETX-Module
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c
deleted file mode 100644
index 04191df..0000000
--- a/board/gdsys/gdppc440etx/gdppc440etx.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * (C) Copyright 2008
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * Based on board/amcc/yosemite/yosemite.c
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/4xx_pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* info for FLASH chips */
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-int board_early_init_f(void)
-{
-	register uint reg;
-
-	/*
-	 * Setup the external bus controller/chip selects
-	 */
-	mfebc(EBC0_CFG, reg);
-	mtebc(EBC0_CFG, reg | 0x04000000);		/* Set ATC */
-
-	/*
-	 * Setup the GPIO pins
-	 */
-
-	/* setup Address lines for flash size 64Meg. */
-	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000);
-	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000);
-	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000);
-
-	/* setup emac */
-	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
-	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
-	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
-	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
-	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
-
-	/* UART0 and UART1*/
-	out32(GPIO1_TCR, in32(GPIO1_TCR)     | 0x16000000);
-	out32(GPIO1_OSRL, in32(GPIO1_OSRL)   | 0x02180000);
-	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000);
-	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000);
-
-	/* disable boot-eeprom WP */
-	out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000);
-	out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000);
-	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000);
-	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000);
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000);
-
-	/* external interrupts IRQ0...3 */
-	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
-	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
-	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
-
-
-	/*
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all */
-	mtdcr(UIC0CR, 0x00000009);	/* ATI & UIC1 crit are critical */
-	mtdcr(UIC0PR, 0xfffffe13);	/* per ref-board manual */
-	mtdcr(UIC0TR, 0x01c00008);	/* per ref-board manual */
-	mtdcr(UIC0VR, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC1ER, 0x00000000);	/* disable all */
-	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC1PR, 0xffffe0ff);	/* per ref-board manual */
-	mtdcr(UIC1TR, 0x00ffc000);	/* per ref-board manual */
-	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-
-	/*
-	 * Setup other serial configuration
-	 */
-	mfsdr(SDR0_PCI0, reg);
-	mtsdr(SDR0_PCI0, 0x80000000 | reg);	/* PCI arbiter enabled */
-	mtsdr(SDR0_PFC0, 0x00003e00);	/* Pin function */
-	mtsdr(SDR0_PFC1, 0x00048000);	/* Pin function: UART0 has 4 pins */
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	uint pbcr;
-	int size_val;
-	uint sz;
-
-	/* Re-do sizing to get full correct info */
-	mfebc(PB0CR, pbcr);
-
-	if (gd->bd->bi_flashsize > 0x08000000)
-		panic("Max. flash banksize is 128 MB!\n");
-
-	for (sz = gd->bd->bi_flashsize, size_val = 7;
-	    ((sz & 0x08000000) == 0) && (size_val > 0); --size_val)
-		sz <<= 1;
-
-	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-	mtebc(PB0CR, pbcr);
-
-	/* adjust flash start and offset */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-	gd->bd->bi_flashoffset = 0;
-
-	/* Monitor protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CONFIG_SYS_MONITOR_LEN,
-			    0xffffffff,
-			    &flash_info[0]);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-/*
- * Override weak pci_pre_init()
- */
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller *hose)
-{
-	/* First call common code */
-	__pci_pre_init(hose);
-
-	/* enable 66 MHz ext. Clock */
-	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000);
-	out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000);
-
-	return 1;
-}
-#endif	/* defined(CONFIG_PCI) */
diff --git a/board/gdsys/gdppc440etx/init.S b/board/gdsys/gdppc440etx/init.S
deleted file mode 100644
index 2db84b5..0000000
--- a/board/gdsys/gdppc440etx/init.S
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
-* (C) Copyright 2008
-* Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
-*
-* based on board/amcc/yosemite/init.S
-* original Copyright not specified there
- * SPDX-License-Identifier:	GPL-2.0+
-*/
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-
-    .section .bootpg,"ax"
-    .globl tlbtab
-
-tlbtab:
-    tlbtab_start
-
-    /*
-     * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use
-     * the speed up boot process. It is patched after relocation to enable SA_I
-     */
-    tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR,
-	0, AC_RWX | SA_G/*|SA_I*/)
-
-    /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-    tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR,
-	0, AC_RWX | SA_G )
-
-    tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE,
-	0, AC_RWX | SA_IG )
-    tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE,
-	0, AC_RW | SA_IG )
-
-    /* PCI */
-    tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE,
-	0, AC_RW | SA_IG )
-    tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1,
-	0, AC_RW | SA_IG )
-    tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2,
-	0, AC_RW | SA_IG )
-    tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3,
-	0, AC_RW | SA_IG )
-
-    tlbtab_end
diff --git a/board/gdsys/intip/Kconfig b/board/gdsys/intip/Kconfig
deleted file mode 100644
index 479bb12..0000000
--- a/board/gdsys/intip/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_INTIP
-
-config SYS_BOARD
-	default "intip"
-
-config SYS_VENDOR
-	default "gdsys"
-
-config SYS_CONFIG_NAME
-	default "intip"
-
-endif
diff --git a/board/gdsys/intip/MAINTAINERS b/board/gdsys/intip/MAINTAINERS
deleted file mode 100644
index c99d507..0000000
--- a/board/gdsys/intip/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-INTIP BOARD
-M:	Dirk Eibach <eibach@gdsys.de>
-S:	Maintained
-F:	board/gdsys/intip/
-F:	include/configs/intip.h
-F:	configs/devconcenter_defconfig
-F:	configs/intip_defconfig
diff --git a/board/gdsys/intip/Makefile b/board/gdsys/intip/Makefile
deleted file mode 100644
index 2fbc983..0000000
--- a/board/gdsys/intip/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2008
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= intip.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-extra-y	+= init.o
diff --git a/board/gdsys/intip/chip_config.c b/board/gdsys/intip/chip_config.c
deleted file mode 100644
index ea276a3..0000000
--- a/board/gdsys/intip/chip_config.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * (C) Copyright 2008-2009
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-struct ppc4xx_config ppc4xx_config_val[] = {
-	{
-		"600-nor", "NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"600-nand", "NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x80, 0xce, 0x1f, 0x79, 0x90, 0x01, 0xa0,
-			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"800-nor", "NOR  CPU: 800 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"800-nand", "NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x80, 0xba, 0x14, 0x99, 0x90, 0x01, 0xa0,
-			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"1000-nor", "NOR  CPU:1000 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"1000-nand", "NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x82, 0x96, 0x19, 0xb9, 0x90, 0x01, 0xa0,
-			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"1066-nor", "NOR  CPU:1066 PLB: 266 OPB:  88 EBC:  88",
-		{
-			0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"1066-nand", "NAND CPU:1066 PLB: 266 OPB:  88 EBC:  88",
-		{
-			0x86, 0x80, 0xb3, 0x01, 0x9d, 0x90, 0x01, 0xa0,
-			0xa0, 0xe8, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/gdsys/intip/config.mk b/board/gdsys/intip/config.mk
deleted file mode 100644
index c8c53e2..0000000
--- a/board/gdsys/intip/config.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# (C) Copyright 2008-2010
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-#
-# G&D CompactCenter
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/gdsys/intip/init.S b/board/gdsys/intip/init.S
deleted file mode 100644
index 1fc2a2f..0000000
--- a/board/gdsys/intip/init.S
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2009
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * Based on board/amcc/canyonlands/init.S
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-	.section .bootpg,"ax"
-	.globl tlbtab
-
-tlbtab:
-	tlbtab_start
-
-	/*
-	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
-	 * use the speed up boot process. It is patched after relocation to
-	 * enable SA_I
-	 */
-	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
-		4, AC_RWX | SA_G) /* TLB 0 */
-
-	/*
-	 * TLB entries for SDRAM are not needed on this platform.
-	 * They are dynamically generated in the SPD DDR(2) detection
-	 * routine.
-	 */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
-	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
-		0, AC_RWX | SA_G)
-#endif
-
-	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
-		AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC,
-		AC_RW | SA_IG)
-
-	/* TLB-entry for NVRAM */
-	tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4,
-		AC_RW | SA_IG)
-
-	/* TLB-entry for UART */
-	tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4,
-		AC_RW | SA_IG)
-
-	/* TLB-entry for IO */
-	tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4,
-		AC_RW | SA_IG)
-
-	/* TLB-entry for OCM */
-	tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
-		AC_RWX | SA_I)
-
-	/* TLB-entry for Local Configuration registers => peripherals */
-	tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS,
-		4, AC_RWX | SA_IG)
-
-	/* AHB: Internal USB Peripherals (USB, SATA) */
-	tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4,
-		AC_RWX | SA_IG)
-
-	tlbtab_end
diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c
deleted file mode 100644
index 2d7d789..0000000
--- a/board/gdsys/intip/intip.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * (C) Copyright 2009
- * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * Based on board/amcc/canyonlands/canyonlands.c
- * (C) Copyright 2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc440.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/4xx_pcie.h>
-#include <asm/ppc4xx-gpio.h>
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define CONFIG_SYS_BCSR3_PCIE		0x10
-
-int board_early_init_f(void)
-{
-	/*
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all */
-	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC1ER, 0x00000000);	/* disable all */
-	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC2ER, 0x00000000);	/* disable all */
-	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC3ER, 0x00000000);	/* disable all */
-	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
-
-	/*
-	 * Configure PFC (Pin Function Control) registers
-	 * enable GPIO 49-63
-	 * UART0: 4 pins
-	 */
-	mtsdr(SDR0_PFC0, 0x00007fff);
-	mtsdr(SDR0_PFC1, 0x00040000);
-
-	/* Enable PCI host functionality in SDR0_PCI0 */
-	mtsdr(SDR0_PCI0, 0xe0000000);
-
-	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */
-
-	/* Setup PLB4-AHB bridge based on the system address map */
-	mtdcr(AHB_TOP, 0x8000004B);
-	mtdcr(AHB_BOT, 0x8000004B);
-
-	/*
-	* Configure USB-STP pins as alternate and not GPIO
-	* It seems to be neccessary to configure the STP pins as GPIO
-	* input at powerup (perhaps while USB reset is asserted). So
-	* we configure those pins to their "real" function now.
-	*/
-	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
-	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
-
-	/* Trigger board component reset */
-	out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
-	out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
-	udelay(50);
-	out_le16((void *)CONFIG_SYS_IO_BASE, 0xffbf);
-	out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffbf);
-	udelay(50);
-	out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
-	out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
-
-	return 0;
-}
-
-int get_cpu_num(void)
-{
-	int cpu = NA_OR_UNKNOWN_CPU;
-
-	return cpu;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-#ifdef CONFIG_DEVCONCENTER
-	printf("Board: DevCon-Center");
-#else
-	printf("Board: Intip");
-#endif
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	/*
-	 * CompactCenter has 64MBytes, DevCon-Center 128MBytes of NOR FLASH
-	 * (Spansion 29GL512), but the boot EBC mapping only supports a maximum
-	 * of 16MBytes (4.ff00.0000 - 4.ffff.ffff).
-	 * To solve this problem, the FLASH has to get remapped to another
-	 * EBC address which accepts bigger regions:
-	 *
-	 * 0xfn00.0000 -> 4.cn00.0000
-	 */
-
-	u32 bxcr_bw = (CONFIG_SYS_FLASH_SIZE == 128 << 20) ?
-		EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB;
-
-	/* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */
-	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L
-		| bxcr_bw
-		| EBC_BXCR_BU_RW
-		| EBC_BXCR_BW_16BIT);
-
-	/* Remove TLB entry of boot EBC mapping */
-	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
-
-	/* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
-	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
-			CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
-
-	/*
-	 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
-	 * 0xfc00.0000 is possible
-	 */
-
-	/*
-	 * Clear potential errors resulting from auto-calibration.
-	 * If not done, then we could get an interrupt later on when
-	 * exceptions are enabled.
-	 */
-	set_mcsr(get_mcsr());
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u32 sdr0_srst1 = 0;
-	u32 eth_cfg;
-
-	/*
-	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
-	 * This is board specific, so let's do it here.
-	 */
-	mfsdr(SDR0_ETH_CFG, eth_cfg);
-	/* disable SGMII mode */
-	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
-		     SDR0_ETH_CFG_SGMII1_ENABLE |
-		     SDR0_ETH_CFG_SGMII0_ENABLE);
-	/* Set the for 2 RGMII mode */
-	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
-	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
-	eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
-	mtsdr(SDR0_ETH_CFG, eth_cfg);
-
-	/*
-	 * The AHB Bridge core is held in reset after power-on or reset
-	 * so enable it now
-	 */
-	mfsdr(SDR0_SRST1, sdr0_srst1);
-	sdr0_srst1 &= ~SDR0_SRST1_AHB;
-	mtsdr(SDR0_SRST1, sdr0_srst1);
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-extern void __ft_board_setup(void *blob, bd_t *bd);
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	__ft_board_setup(blob, bd);
-
-	fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
-			     "disabled", sizeof("disabled"), 1);
-
-	fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
-			     "disabled", sizeof("disabled"), 1);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig
index 9a1a3a2..cb29c25 100644
--- a/board/gdsys/mpc8308/Kconfig
+++ b/board/gdsys/mpc8308/Kconfig
@@ -23,3 +23,8 @@ config SYS_CONFIG_NAME
 	default "strider"
 
 endif
+
+config CMD_IOLOOP
+	bool "Enable 'ioloop' and 'ioreflect' commands"
+	help
+	  These commands provide FPGA tests.
diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c
index f55893f..c6566e9 100644
--- a/board/gdsys/mpc8308/hrcon.c
+++ b/board/gdsys/mpc8308/hrcon.c
@@ -358,7 +358,7 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 	fdt_fixup_esdhc(blob, bd);
 
 	return 0;
diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c
index 1b8e035..86b257f 100644
--- a/board/gdsys/mpc8308/mpc8308.c
+++ b/board/gdsys/mpc8308/mpc8308.c
@@ -9,7 +9,6 @@
 #include <command.h>
 #include <asm/processor.h>
 #include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
 #include <asm/global_data.h>
 
 #include "mpc8308.h"
diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c
index 0fce8cf..5d2ec89 100644
--- a/board/gdsys/mpc8308/sdram.c
+++ b/board/gdsys/mpc8308/sdram.c
@@ -66,17 +66,19 @@ static long fixed_sdram(void)
 	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;
 
 	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	/* DDR SDRAM */
 	msize = fixed_sdram();
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	gd->ram_size = msize;
+
+	return 0;
 }
diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c
index b8dde5f..34e9d19 100644
--- a/board/gdsys/mpc8308/strider.c
+++ b/board/gdsys/mpc8308/strider.c
@@ -413,7 +413,7 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 	fdt_fixup_esdhc(blob, bd);
 
 	return 0;
diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c
index 2c6c698..95f11fb 100644
--- a/board/gdsys/p1022/controlcenterd-id.c
+++ b/board/gdsys/p1022/controlcenterd-id.c
@@ -43,15 +43,6 @@
 #define CCDM_AUTO_FIRST_STAGE
 #endif
 
-/* enums from TCG specs */
-enum {
-	/* capability areas */
-	TPM_CAP_NV_INDEX	= 0x00000011,
-	TPM_CAP_HANDLE		= 0x00000014,
-	/* resource types */
-	TPM_RT_KEY	= 0x00000001,
-};
-
 /* CCDM specific contants */
 enum {
 	/* NV indices */
@@ -151,47 +142,8 @@ static int hre_err = HRE_E_OK;
 #define IS_VAR_HREG(spec) (((spec) & 0x38) == 0x10)
 #define HREG_IDX(spec) ((spec) & (IS_PCR_HREG(spec) ? 0x1f : 0x7))
 
-
-static const uint8_t prg_stage1_prepare[] = {
-	0x00, 0x20, 0x00, 0x00, /* opcode: SYNC f0 */
-	0x00, 0x24, 0x00, 0x00, /* opcode: SYNC f1 */
-	0x01, 0x80, 0x00, 0x00, /* opcode: CHECK0 PCR0 */
-	0x81, 0x22, 0x00, 0x00, /* opcode: LOAD PCR0, f0 */
-	0x01, 0x84, 0x00, 0x00, /* opcode: CHECK0 PCR1 */
-	0x81, 0x26, 0x10, 0x00, /* opcode: LOAD PCR1, f1 */
-	0x01, 0x88, 0x00, 0x00, /* opcode: CHECK0 PCR2 */
-	0x81, 0x2a, 0x20, 0x00, /* opcode: LOAD PCR2, f2 */
-	0x01, 0x8c, 0x00, 0x00, /* opcode: CHECK0 PCR3 */
-	0x81, 0x2e, 0x30, 0x00, /* opcode: LOAD PCR3, f3 */
-};
-
-static const uint8_t prg_stage2_prepare[] = {
-	0x00, 0x80, 0x00, 0x00, /* opcode: SYNC PCR0 */
-	0x00, 0x84, 0x00, 0x00, /* opcode: SYNC PCR1 */
-	0x00, 0x88, 0x00, 0x00, /* opcode: SYNC PCR2 */
-	0x00, 0x8c, 0x00, 0x00, /* opcode: SYNC PCR3 */
-	0x00, 0x90, 0x00, 0x00, /* opcode: SYNC PCR4 */
-};
-
-static const uint8_t prg_stage2_success[] = {
-	0x81, 0x02, 0x40, 0x14, /* opcode: LOAD PCR4, #<20B data> */
-	0x48, 0xfd, 0x95, 0x17, 0xe7, 0x54, 0x6b, 0x68, /* data */
-	0x92, 0x31, 0x18, 0x05, 0xf8, 0x58, 0x58, 0x3c, /* data */
-	0xe4, 0xd2, 0x81, 0xe0, /* data */
-};
-
-static const uint8_t prg_stage_fail[] = {
-	0x81, 0x01, 0x00, 0x14, /* opcode: LOAD v0, #<20B data> */
-	0xc0, 0x32, 0xad, 0xc1, 0xff, 0x62, 0x9c, 0x9b, /* data */
-	0x66, 0xf2, 0x27, 0x49, 0xad, 0x66, 0x7e, 0x6b, /* data */
-	0xea, 0xdf, 0x14, 0x4b, /* data */
-	0x81, 0x42, 0x30, 0x00, /* opcode: LOAD PCR3, v0 */
-	0x81, 0x42, 0x40, 0x00, /* opcode: LOAD PCR4, v0 */
-};
-
 static const uint8_t vendor[] = "Guntermann & Drunck";
 
-
 /**
  * @brief read a bunch of data from MMC into memory.
  *
@@ -965,6 +917,19 @@ end:
 #endif
 
 #if defined(CCDM_FIRST_STAGE) || (defined CCDM_AUTO_FIRST_STAGE)
+static const uint8_t prg_stage1_prepare[] = {
+	0x00, 0x20, 0x00, 0x00, /* opcode: SYNC f0 */
+	0x00, 0x24, 0x00, 0x00, /* opcode: SYNC f1 */
+	0x01, 0x80, 0x00, 0x00, /* opcode: CHECK0 PCR0 */
+	0x81, 0x22, 0x00, 0x00, /* opcode: LOAD PCR0, f0 */
+	0x01, 0x84, 0x00, 0x00, /* opcode: CHECK0 PCR1 */
+	0x81, 0x26, 0x10, 0x00, /* opcode: LOAD PCR1, f1 */
+	0x01, 0x88, 0x00, 0x00, /* opcode: CHECK0 PCR2 */
+	0x81, 0x2a, 0x20, 0x00, /* opcode: LOAD PCR2, f2 */
+	0x01, 0x8c, 0x00, 0x00, /* opcode: CHECK0 PCR3 */
+	0x81, 0x2e, 0x30, 0x00, /* opcode: LOAD PCR3, f3 */
+};
+
 static int first_stage_actions(void)
 {
 	int result = 0;
@@ -1022,6 +987,30 @@ static int first_stage_init(void)
 #endif
 
 #ifdef CCDM_SECOND_STAGE
+static const uint8_t prg_stage2_prepare[] = {
+	0x00, 0x80, 0x00, 0x00, /* opcode: SYNC PCR0 */
+	0x00, 0x84, 0x00, 0x00, /* opcode: SYNC PCR1 */
+	0x00, 0x88, 0x00, 0x00, /* opcode: SYNC PCR2 */
+	0x00, 0x8c, 0x00, 0x00, /* opcode: SYNC PCR3 */
+	0x00, 0x90, 0x00, 0x00, /* opcode: SYNC PCR4 */
+};
+
+static const uint8_t prg_stage2_success[] = {
+	0x81, 0x02, 0x40, 0x14, /* opcode: LOAD PCR4, #<20B data> */
+	0x48, 0xfd, 0x95, 0x17, 0xe7, 0x54, 0x6b, 0x68, /* data */
+	0x92, 0x31, 0x18, 0x05, 0xf8, 0x58, 0x58, 0x3c, /* data */
+	0xe4, 0xd2, 0x81, 0xe0, /* data */
+};
+
+static const uint8_t prg_stage_fail[] = {
+	0x81, 0x01, 0x00, 0x14, /* opcode: LOAD v0, #<20B data> */
+	0xc0, 0x32, 0xad, 0xc1, 0xff, 0x62, 0x9c, 0x9b, /* data */
+	0x66, 0xf2, 0x27, 0x49, 0xad, 0x66, 0x7e, 0x6b, /* data */
+	0xea, 0xdf, 0x14, 0x4b, /* data */
+	0x81, 0x42, 0x30, 0x00, /* opcode: LOAD PCR3, v0 */
+	0x81, 0x42, 0x40, 0x00, /* opcode: LOAD PCR4, v0 */
+};
+
 static int second_stage_init(void)
 {
 	static const char mac_suffix[] = ".mac";
diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c
index 2f98e47..01064dc 100644
--- a/board/gdsys/p1022/controlcenterd.c
+++ b/board/gdsys/p1022/controlcenterd.c
@@ -341,7 +341,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
 #ifdef CONFIG_HAS_FSL_DR_USB
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
 	FT_FSL_PCI_SETUP;
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index e9729f8..b25c634 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -10,12 +10,12 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
@@ -103,8 +103,9 @@ static void setup_iomux_enet(void)
 
 	/* Reset AR8033 PHY */
 	gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
-	udelay(500);
+	mdelay(10);
 	gpio_set_value(IMX_GPIO_NR(1, 28), 1);
+	mdelay(1);
 }
 
 static iomux_v3_cfg_t const usdhc2_pads[] = {
@@ -306,7 +307,8 @@ static int mx6_rgmii_rework(struct phy_device *phydev)
 	/* set debug port address: SerDes Test and System Mode Control */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 	/* enable rgmii tx clock delay */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+	/* set the reserved bits to avoid board specific voltage peak issue*/
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 
 	return 0;
 }
@@ -596,6 +598,57 @@ static const struct boot_mode board_boot_modes[] = {
 };
 #endif
 
+void pmic_init(void)
+{
+#define I2C_PMIC                0x2
+#define DA9063_I2C_ADDR         0x58
+#define DA9063_REG_BCORE2_CFG   0x9D
+#define DA9063_REG_BCORE1_CFG   0x9E
+#define DA9063_REG_BPRO_CFG     0x9F
+#define DA9063_REG_BIO_CFG      0xA0
+#define DA9063_REG_BMEM_CFG     0xA1
+#define DA9063_REG_BPERI_CFG    0xA2
+#define DA9063_BUCK_MODE_MASK   0xC0
+#define DA9063_BUCK_MODE_MANUAL 0x00
+#define DA9063_BUCK_MODE_SLEEP  0x40
+#define DA9063_BUCK_MODE_SYNC   0x80
+#define DA9063_BUCK_MODE_AUTO   0xC0
+
+	uchar val;
+
+	i2c_set_bus_num(I2C_PMIC);
+
+	i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
+	val &= ~DA9063_BUCK_MODE_MASK;
+	val |= DA9063_BUCK_MODE_SYNC;
+	i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
+
+	i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
+	val &= ~DA9063_BUCK_MODE_MASK;
+	val |= DA9063_BUCK_MODE_SYNC;
+	i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
+
+	i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
+	val &= ~DA9063_BUCK_MODE_MASK;
+	val |= DA9063_BUCK_MODE_SYNC;
+	i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
+
+	i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
+	val &= ~DA9063_BUCK_MODE_MASK;
+	val |= DA9063_BUCK_MODE_SYNC;
+	i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
+
+	i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
+	val &= ~DA9063_BUCK_MODE_MASK;
+	val |= DA9063_BUCK_MODE_SYNC;
+	i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
+
+	i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
+	val &= ~DA9063_BUCK_MODE_MASK;
+	val |= DA9063_BUCK_MODE_SYNC;
+	i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
+}
+
 int board_late_init(void)
 {
 #ifdef CONFIG_CMD_BMODE
@@ -619,6 +672,9 @@ int board_late_init(void)
 	pwm_enable(0);
 #endif
 
+	/* board specific pmic init */
+	pmic_init();
+
 	return 0;
 }
 
diff --git a/board/geekbuying/geekbox/Kconfig b/board/geekbuying/geekbox/Kconfig
new file mode 100644
index 0000000..41aa8fb
--- /dev/null
+++ b/board/geekbuying/geekbox/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_GEEKBOX
+
+config SYS_BOARD
+	default "geekbox"
+
+config SYS_VENDOR
+	default "geekbuying"
+
+config SYS_CONFIG_NAME
+	default "geekbox"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/geekbuying/geekbox/MAINTAINERS b/board/geekbuying/geekbox/MAINTAINERS
new file mode 100644
index 0000000..7a4989f
--- /dev/null
+++ b/board/geekbuying/geekbox/MAINTAINERS
@@ -0,0 +1,6 @@
+GEEKBOX
+M:	Andreas Färber <afaerber@suse.de>
+S:	Maintained
+F:	board/geekbuying/geekbox
+F:	include/configs/geekbox.h
+F:	configs/geekbox_defconfig
diff --git a/board/geekbuying/geekbox/Makefile b/board/geekbuying/geekbox/Makefile
new file mode 100644
index 0000000..5c1d66c
--- /dev/null
+++ b/board/geekbuying/geekbox/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2016 Andreas Färber
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= geekbox.o
diff --git a/board/geekbuying/geekbox/README b/board/geekbuying/geekbox/README
new file mode 100644
index 0000000..de980f2
--- /dev/null
+++ b/board/geekbuying/geekbox/README
@@ -0,0 +1 @@
+see board/rockchip/sheep_rk3368/README
diff --git a/board/geekbuying/geekbox/geekbox.c b/board/geekbuying/geekbox/geekbox.c
new file mode 100644
index 0000000..88b67f9
--- /dev/null
+++ b/board/geekbuying/geekbox/geekbox.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
diff --git a/board/google/Kconfig b/board/google/Kconfig
index 7ba73a2..e56c026 100644
--- a/board/google/Kconfig
+++ b/board/google/Kconfig
@@ -22,6 +22,13 @@ config TARGET_CHROMEBOOK_LINK
 	  and it provides a 2560x1700 high resolution touch-enabled LCD
 	  display.
 
+config TARGET_CHROMEBOOK_LINK64
+	bool "Chromebook link 64-bit"
+	help
+	  This is the Chromebook Pixel released in 2013. With this config
+	  U-Boot is built as a 64-bit binary. This allows testing while this
+	  feature is being completed.
+
 config TARGET_CHROMEBOX_PANTHER
 	bool "Chromebox panther (not available)"
 	select n
diff --git a/board/google/chromebook_jerry/Kconfig b/board/google/chromebook_jerry/Kconfig
deleted file mode 100644
index 3640513..0000000
--- a/board/google/chromebook_jerry/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_CHROMEBOOK_JERRY
-
-config SYS_BOARD
-	default "chromebook_jerry"
-
-config SYS_VENDOR
-	default "google"
-
-config SYS_CONFIG_NAME
-	default "chromebook_jerry"
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-
-endif
diff --git a/board/google/chromebook_jerry/MAINTAINERS b/board/google/chromebook_jerry/MAINTAINERS
deleted file mode 100644
index b01b6cd..0000000
--- a/board/google/chromebook_jerry/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CHROMEBOOK JERRY BOARD
-M:	Simon Glass <sjg@chromium.org>
-S:	Maintained
-F:	board/google/chromebook_jerry/
-F:	include/configs/chromebook_jerry.h
-F:	configs/chromebook_jerry_defconfig
diff --git a/board/google/chromebook_jerry/Makefile b/board/google/chromebook_jerry/Makefile
deleted file mode 100644
index d29a063..0000000
--- a/board/google/chromebook_jerry/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2015 Google, Inc
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y	+= jerry.o
diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
index fa12f33..944716d 100644
--- a/board/google/chromebook_link/Kconfig
+++ b/board/google/chromebook_link/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_CHROMEBOOK_LINK
+if TARGET_CHROMEBOOK_LINK || TARGET_CHROMEBOOK_LINK64
 
 config SYS_BOARD
 	default "chromebook_link"
@@ -13,7 +13,8 @@ config SYS_CONFIG_NAME
 	default "chromebook_link"
 
 config SYS_TEXT_BASE
-	default 0xfff00000
+	default 0xfff00000 if !SUPPORT_SPL
+	default 0x10000000 if SUPPORT_SPL
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
@@ -21,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
 	select HAVE_INTEL_ME
 	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_WINBOND
 
 config PCIE_ECAM_BASE
 	default 0xf0000000
diff --git a/board/google/chromebook_link/MAINTAINERS b/board/google/chromebook_link/MAINTAINERS
index bc253a2..e7aef53 100644
--- a/board/google/chromebook_link/MAINTAINERS
+++ b/board/google/chromebook_link/MAINTAINERS
@@ -4,3 +4,10 @@ S:	Maintained
 F:	board/google/chromebook_link/
 F:	include/configs/chromebook_link.h
 F:	configs/chromebook_link_defconfig
+
+CHROMEBOOK LINK 64-bit BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/chromebook_link/
+F:	include/configs/chromebook_link.h
+F:	configs/chromebook_link64_defconfig
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
index 42615e1..dc22592 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -5,19 +5,3 @@
  */
 
 #include <common.h>
-#include <cros_ec.h>
-#include <dm.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include <asm/arch/pch.h>
-
-int arch_early_init_r(void)
-{
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	return 0;
-}
diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig
index f2b9481..afbfe53 100644
--- a/board/google/chromebook_samus/Kconfig
+++ b/board/google/chromebook_samus/Kconfig
@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select INTEL_BROADWELL
 	select HAVE_INTEL_ME
 	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_WINBOND
 
 config PCIE_ECAM_BASE
 	default 0xf0000000
diff --git a/board/google/chromebook_samus/samus.c b/board/google/chromebook_samus/samus.c
index 3c3f5d4..5b5eb19 100644
--- a/board/google/chromebook_samus/samus.c
+++ b/board/google/chromebook_samus/samus.c
@@ -5,14 +5,3 @@
  */
 
 #include <common.h>
-#include <asm/cpu.h>
-
-int arch_early_init_r(void)
-{
-	return cpu_run_reference_code();
-}
-
-int board_early_init_f(void)
-{
-	return 0;
-}
diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig
index 2af3aa9..875df9d 100644
--- a/board/google/chromebox_panther/Kconfig
+++ b/board/google/chromebox_panther/Kconfig
@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
 	select HAVE_INTEL_ME
 	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_WINBOND
 
 config SYS_CAR_ADDR
 	hex
diff --git a/board/google/chromebox_panther/panther.c b/board/google/chromebox_panther/panther.c
index e3baf88..2adc202 100644
--- a/board/google/chromebox_panther/panther.c
+++ b/board/google/chromebox_panther/panther.c
@@ -5,14 +5,3 @@
  */
 
 #include <common.h>
-#include <asm/arch/pch.h>
-
-int arch_early_init_r(void)
-{
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	return 0;
-}
diff --git a/board/google/veyron/Kconfig b/board/google/veyron/Kconfig
new file mode 100644
index 0000000..770e9aa
--- /dev/null
+++ b/board/google/veyron/Kconfig
@@ -0,0 +1,47 @@
+if TARGET_CHROMEBOOK_JERRY
+
+config SYS_BOARD
+	default "veyron"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_CONFIG_NAME
+	default "veyron"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
+
+if TARGET_CHROMEBIT_MICKEY
+
+config SYS_BOARD
+	default "veyron"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_CONFIG_NAME
+	default "veyron"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
+
+if TARGET_CHROMEBOOK_MINNIE
+
+config SYS_BOARD
+	default "veyron"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_CONFIG_NAME
+	default "veyron"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/google/veyron/MAINTAINERS b/board/google/veyron/MAINTAINERS
new file mode 100644
index 0000000..246a3e3
--- /dev/null
+++ b/board/google/veyron/MAINTAINERS
@@ -0,0 +1,20 @@
+CHROMEBOOK JERRY BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/veyron/
+F:	include/configs/veyron.h
+F:	configs/chromebook_jerry_defconfig
+
+CHROMEBIT MICKEY BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/veyron/
+F:	include/configs/veyron.h
+F:	configs/chromebit_mickey_defconfig
+
+CHROMEBOOK MINNIE BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/veyron/
+F:	include/configs/veyron.h
+F:	configs/chromebook_minnie_defconfig
diff --git a/board/google/veyron/Makefile b/board/google/veyron/Makefile
new file mode 100644
index 0000000..9868357
--- /dev/null
+++ b/board/google/veyron/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Google, Inc
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= veyron.o
diff --git a/board/google/veyron/veyron.c b/board/google/veyron/veyron.c
new file mode 100644
index 0000000..20297e1
--- /dev/null
+++ b/board/google/veyron/veyron.c
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+
+/*
+ * We should increase the DDR voltage to 1.2V using the PWM regulator.
+ * There is a U-Boot driver for this but it may need to add support for the
+ * 'voltage-table' property.
+ */
diff --git a/board/grinn/chiliboard/Kconfig b/board/grinn/chiliboard/Kconfig
new file mode 100644
index 0000000..20056e8
--- /dev/null
+++ b/board/grinn/chiliboard/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_CHILIBOARD
+
+config SYS_BOARD
+	default "chiliboard"
+
+config SYS_VENDOR
+	default "grinn"
+
+config SYS_CONFIG_NAME
+	default "chiliboard"
+
+config SYS_SOC
+	default "am33xx"
+
+endif
diff --git a/board/grinn/chiliboard/MAINTAINERS b/board/grinn/chiliboard/MAINTAINERS
new file mode 100644
index 0000000..5eaccb2
--- /dev/null
+++ b/board/grinn/chiliboard/MAINTAINERS
@@ -0,0 +1,8 @@
+CHILIBOARD
+M:	Marcin Niestroj <m.niestroj@grinn-global.com>
+S:	Maintained
+F:	arch/arm/include/asm/arch-am33xx/chilisom.h
+F:	arch/arm/mach-omap2/am33xx/chilisom.c
+F:	board/grinn/chiliboard/
+F:	include/configs/chiliboard.h
+F:	configs/chiliboard_defconfig
diff --git a/board/grinn/chiliboard/Makefile b/board/grinn/chiliboard/Makefile
new file mode 100644
index 0000000..865968d
--- /dev/null
+++ b/board/grinn/chiliboard/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2017 Grinn
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := board.o
diff --git a/board/grinn/chiliboard/README b/board/grinn/chiliboard/README
new file mode 100644
index 0000000..cea4c1d
--- /dev/null
+++ b/board/grinn/chiliboard/README
@@ -0,0 +1,31 @@
+How to use U-Boot on Grinn's chiliBoard
+--------------------------------------
+
+- Build U-Boot for chiliBoard:
+
+$ make mrproper
+$ make chiliboard_defconfig
+$ make
+
+This will generate the SPL image called MLO and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=MLO of=/dev/mmcblk0 bs=128k; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=128k seek=3; sync
+
+- Jumper settings:
+
+S2: 1 1 1 0 1 0
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Insert the micro SD card in the board.
+
+- Connect USB cable between chiliBoard and the PC for the power and console.
+
+- U-Boot messages should come up.
diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c
new file mode 100644
index 0000000..e3f82b0
--- /dev/null
+++ b/board/grinn/chiliboard/board.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2017, Grinn - http://grinn-global.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/chilisom.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/emif.h>
+#include <asm/io.h>
+#include <cpsw.h>
+#include <environment.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <serial.h>
+#include <spl.h>
+#include <watchdog.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static __maybe_unused struct ctrl_dev *cdev =
+	(struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{-1},
+};
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRS */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXERR */
+	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_REFCLK */
+	{-1},
+};
+
+static void enable_board_pin_mux(void)
+{
+	chilisom_enable_pin_mux();
+
+	/* chiliboard pinmux */
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+}
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#ifndef CONFIG_DM_SERIAL
+struct serial_device *default_serial_console(void)
+{
+	return &eserial1_device;
+}
+#endif
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+void set_uart_mux_conf(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+void am33xx_spl_board_init(void)
+{
+	chilisom_spl_board_init();
+}
+#endif
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	gpmc_init();
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if !defined(CONFIG_SPL_BUILD)
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("ethaddr")) {
+		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+		if (is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+	}
+
+	mac_lo = readl(&cdev->macid1l);
+	mac_hi = readl(&cdev->macid1h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("eth1addr")) {
+		if (is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("eth1addr", mac_addr);
+	}
+#endif
+
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW) && \
+	!defined(CONFIG_SPL_BUILD)
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+	}
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, n = 0;
+
+	writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+	cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+
+	return n;
+}
+#endif
diff --git a/board/grinn/liteboard/Kconfig b/board/grinn/liteboard/Kconfig
new file mode 100644
index 0000000..e035872
--- /dev/null
+++ b/board/grinn/liteboard/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_LITEBOARD
+
+config SYS_BOARD
+	default "liteboard"
+
+config SYS_VENDOR
+	default "grinn"
+
+config SYS_CONFIG_NAME
+	default "liteboard"
+
+endif
diff --git a/board/grinn/liteboard/MAINTAINERS b/board/grinn/liteboard/MAINTAINERS
new file mode 100644
index 0000000..b4474f1
--- /dev/null
+++ b/board/grinn/liteboard/MAINTAINERS
@@ -0,0 +1,6 @@
+LITEBOARD
+M:	Marcin Niestroj <m.niestroj@grinn-global.com>
+S:	Maintained
+F:	board/grinn/liteboard/
+F:	include/configs/liteboard.h
+F:	configs/liteboard_defconfig
diff --git a/board/grinn/liteboard/Makefile b/board/grinn/liteboard/Makefile
new file mode 100644
index 0000000..e2492d6
--- /dev/null
+++ b/board/grinn/liteboard/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Grinn
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := board.o
diff --git a/board/grinn/liteboard/README b/board/grinn/liteboard/README
new file mode 100644
index 0000000..bee0394
--- /dev/null
+++ b/board/grinn/liteboard/README
@@ -0,0 +1,31 @@
+How to use U-Boot on Grinn's liteBoard
+--------------------------------------
+
+- Build U-Boot for liteBoard:
+
+$ make mrproper
+$ make liteboard_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot.img image into the micro SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+S1: 0 1 0 1 1 1
+
+where 0 means bottom position and 1 means top position (from the
+switch label numbers reference).
+
+- Insert the micro SD card in the board.
+
+- Connect USB cable between liteBoard and the PC for the power and console.
+
+- U-Boot messages should come up.
diff --git a/board/grinn/liteboard/board.c b/board/grinn/liteboard/board.c
new file mode 100644
index 0000000..817e22f
--- /dev/null
+++ b/board/grinn/liteboard/board.c
@@ -0,0 +1,287 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2016 Grinn
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/litesom.h>
+#include <asm/arch/mx6ul_pins.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <linux/sizes.h>
+#include <linux/fb.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <spl.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_SPEED_HIGH   |                                   \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
+
+#define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
+
+#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const sd_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* CD */
+	MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_FEC_MXC
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+}
+#endif
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4};
+
+#define SD_CD_GPIO	IMX_GPIO_NR(1, 19)
+
+static int mmc_get_env_devno(void)
+{
+	u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
+	int dev_no;
+	u32 bootsel;
+
+	bootsel = (soc_sbmr & 0x000000FF) >> 6;
+
+	/* If not boot from sd/mmc, use default value */
+	if (bootsel != 1)
+		return CONFIG_SYS_MMC_ENV_DEV;
+
+	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
+	dev_no = (soc_sbmr & 0x00001800) >> 11;
+
+	return dev_no;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(SD_CD_GPIO);
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = 1;
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	/* SD */
+	imx_iomux_v3_setup_multiple_pads(sd_pads, ARRAY_SIZE(sd_pads));
+	gpio_direction_input(SD_CD_GPIO);
+	sd_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	ret = fsl_esdhc_initialize(bis, &sd_cfg);
+	if (ret) {
+		printf("Warning: failed to initialize mmc dev 0 (SD)\n");
+		return ret;
+	}
+
+	return litesom_mmc_init(bis);
+}
+
+static int check_mmc_autodetect(void)
+{
+	char *autodetect_str = getenv("mmcautodetect");
+
+	if ((autodetect_str != NULL) &&
+	    (strcmp(autodetect_str, "yes") == 0)) {
+		return 1;
+	}
+
+	return 0;
+}
+
+void board_late_mmc_init(void)
+{
+	char cmd[32];
+	char mmcblk[32];
+	u32 dev_no = mmc_get_env_devno();
+
+	if (!check_mmc_autodetect())
+		return;
+
+	setenv_ulong("mmcdev", dev_no);
+
+	/* Set mmcblk env */
+	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
+		dev_no);
+	setenv("mmcroot", mmcblk);
+
+	sprintf(cmd, "mmc dev %d", dev_no);
+	run_command(cmd, 0);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+int board_eth_init(bd_t *bis)
+{
+	setup_iomux_fec();
+
+	return fecmxc_initialize(bis);
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	/* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13],
+	   set gpr1[17]*/
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+
+	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_usb_phy_mode(int port)
+{
+	return USB_INIT_HOST;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef	CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd",   MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+	{"emmc", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_init();
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Grinn liteBoard\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_boot_order(u32 *spl_boot_list)
+{
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
+	unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
+	unsigned port = (reg >> 11) & 0x1;
+
+	if (port == 0) {
+		spl_boot_list[0] = BOOT_DEVICE_MMC1;
+		spl_boot_list[1] = BOOT_DEVICE_MMC2;
+	} else {
+		spl_boot_list[0] = BOOT_DEVICE_MMC2;
+		spl_boot_list[1] = BOOT_DEVICE_MMC1;
+	}
+}
+
+void board_init_f(ulong dummy)
+{
+	litesom_init_f();
+}
+#endif
diff --git a/board/gumstix/duovero/duovero.c b/board/gumstix/duovero/duovero.c
index 3786842..849224e 100644
--- a/board/gumstix/duovero/duovero.c
+++ b/board/gumstix/duovero/duovero.c
@@ -14,6 +14,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
 #include <asm/gpio.h>
+#include <asm/mach-types.h>
 
 #include "duovero_mux_data.h"
 
@@ -24,7 +25,7 @@
 static void setup_net_chip(void);
 #endif
 
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
 #include <usb.h>
 #include <asm/arch/ehci.h>
 #include <asm/ehci-omap.h>
@@ -47,7 +48,7 @@ int board_init(void)
 {
 	gpmc_init();
 
-	gd->bd->bi_arch_number = MACH_TYPE_OMAP4_DUOVERO;
+	gd->bd->bi_arch_number = MACH_TYPE_DUOVERO;
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
 	return 0;
@@ -110,17 +111,19 @@ void set_muxconf_regs(void)
 		   sizeof(struct pad_conf_entry));
 }
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
 }
 
+#if !defined(CONFIG_SPL_BUILD)
 void board_mmc_power_init(void)
 {
 	twl6030_power_mmc_init(0);
 }
 #endif
+#endif
 
 #if defined(CONFIG_CMD_NET)
 
@@ -204,7 +207,7 @@ int board_eth_init(bd_t *bis)
 	return rc;
 }
 
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
 
 static struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
diff --git a/board/h2200/h2200.c b/board/h2200/h2200.c
index 01f8e67..2a2b797 100644
--- a/board/h2200/h2200.c
+++ b/board/h2200/h2200.c
@@ -11,6 +11,7 @@
 #include <asm/arch/pxa-regs.h>
 #include <asm/io.h>
 #include <usb.h>
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/highbank/ahci.c b/board/highbank/ahci.c
index 1578a33..dadfbdd 100644
--- a/board/highbank/ahci.c
+++ b/board/highbank/ahci.c
@@ -172,7 +172,7 @@ static void cphy_override_lane(u8 port)
 
 #define WAIT_MS_LINKUP	4
 
-int ahci_link_up(struct ahci_probe_ent *probe_ent, int port)
+int ahci_link_up(struct ahci_uc_priv *probe_ent, int port)
 {
 	u32 tmp;
 	int j = 0;
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index 55999ed..1af2207 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -67,7 +67,7 @@ void scsi_init(void)
 	cphy_disable_overrides();
 	if (reg & PWRDOM_STAT_SATA) {
 		ahci_init((void __iomem *)HB_AHCI_BASE);
-		scsi_scan(1);
+		scsi_scan(true);
 	}
 }
 #endif
diff --git a/board/hisilicon/hikey/README b/board/hisilicon/hikey/README
index 0f6aab7..4c2021f 100644
--- a/board/hisilicon/hikey/README
+++ b/board/hisilicon/hikey/README
@@ -56,7 +56,7 @@ Compile U-Boot
 Compile ARM Trusted Firmware (ATF)
 ==================================
 
-  > cd ~/hikey/src/atf
+  > cd ~/hikey/src/arm-trusted-firmware
   > make CROSS_COMPILE=aarch64-linux-gnu- all fip \
     BL30=~/hikey/bin/mcuimage.bin \
     BL33=~/hikey/bin/u-boot.bin DEBUG=1 PLAT=hikey
@@ -67,10 +67,10 @@ Copy resulting binaries
 
 Compile l-loader
 ===============
-  > cd ~/hikey/l-loader
+  > cd ~/hikey/src/l-loader
   > make BL1=~/hikey/bin/bl1.bin all
   > cp *.img ~/hikey/bin
-  > cp l-loader.bin ~/hikey.bin
+  > cp l-loader.bin ~/hikey/bin
 
 These instructions are adapted from
 https://github.com/96boards/documentation/wiki/HiKeyUEFI
@@ -82,7 +82,7 @@ FLASHING
 the hisi-idt.py utility.
 
 The command below assumes HiKey enumerated as the first USB serial port
-  > sudo ~/hikey/burn_boot/hisi-idt.py -d /dev/ttyUSB0 --img1=~/hikey/bin/l-loader.bin
+  > sudo ~/hikey/src/burn-boot/hisi-idt.py -d /dev/ttyUSB0 --img1=~/hikey/bin/l-loader.bin
 
 2. Once LED 0 comes on solid, HiKey board should be detected as a fastboot device by plugging a USB A to mini B
    cable from your PC to the USB OTG port of HiKey (on some boards I've found this to be unreliable).
diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
index 72d6334..c513d0a 100644
--- a/board/hisilicon/hikey/hikey.c
+++ b/board/hisilicon/hikey/hikey.c
@@ -341,13 +341,13 @@ int board_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_GENERIC_MMC
+#ifdef CONFIG_MMC
 
 static int init_dwmmc(void)
 {
-	int ret;
+	int ret = 0;
 
-#ifdef CONFIG_DWMMC
+#ifdef CONFIG_MMC_DW
 
 	/* mmc0 clocks are already configured by ATF */
 	ret = hi6220_pinmux_config(PERIPH_ID_SDMMC0);
@@ -410,7 +410,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	/*
 	 * Reserve regions below from DT memory node (which gets generated
@@ -442,6 +442,8 @@ void dram_init_banksize(void)
 
 	gd->bd->bi_dram[5].start = 0x22000000;
 	gd->bd->bi_dram[5].size = 0x1c000000;
+
+	return 0;
 }
 
 void reset_cpu(ulong addr)
diff --git a/board/hisilicon/poplar/Kconfig b/board/hisilicon/poplar/Kconfig
new file mode 100644
index 0000000..3397295
--- /dev/null
+++ b/board/hisilicon/poplar/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_POPLAR
+
+config SYS_BOARD
+	default "poplar"
+
+config SYS_VENDOR
+	default "hisilicon"
+
+config SYS_SOC
+	default "hi3798cv200"
+
+config SYS_CONFIG_NAME
+	default "poplar"
+
+endif
diff --git a/board/hisilicon/poplar/MAINTAINERS b/board/hisilicon/poplar/MAINTAINERS
new file mode 100644
index 0000000..0cc01c8
--- /dev/null
+++ b/board/hisilicon/poplar/MAINTAINERS
@@ -0,0 +1,6 @@
+Poplar BOARD
+M:     Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+S:     Maintained
+F:     board/hisilicon/poplar
+F:     include/configs/poplar.h
+F:     configs/poplar_defconfig
diff --git a/board/hisilicon/poplar/Makefile b/board/hisilicon/poplar/Makefile
new file mode 100644
index 0000000..101545d
--- /dev/null
+++ b/board/hisilicon/poplar/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2017 Linaro
+# Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+obj-y	:= poplar.o
diff --git a/board/hisilicon/poplar/README b/board/hisilicon/poplar/README
new file mode 100644
index 0000000..99ed6ce
--- /dev/null
+++ b/board/hisilicon/poplar/README
@@ -0,0 +1,288 @@
+================================================================================
+			Board Information
+================================================================================
+
+Developed by HiSilicon, the board features the Hi3798C V200 with an
+integrated quad-core 64-bit ARM Cortex A53 processor and high
+performance Mali T720 GPU, making it capable of running any commercial
+set-top solution based on Linux or Android. Its high performance
+specification also supports a premium user experience with up to H.265
+HEVC decoding of 4K video at 60 frames per second.
+
+SOC  Hisilicon Hi3798CV200
+CPU  Quad-core ARM Cortex-A53 64 bit
+DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
+USB  Two USB 2.0 ports One USB 3.0 ports
+CONSOLE  USB-micro port for console support
+ETHERNET  1 GBe Ethernet
+PCIE  One PCIe 2.0 interfaces
+JTAG  8-Pin JTAG
+EXPANSION INTERFACE  Linaro 96Boards Low Speed Expansion slot
+DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor
+WIFI  802.11AC 2*2 with Bluetooth
+CONNECTORS  One connector for Smart Card One connector for TSI
+
+
+================================================================================
+			BUILD INSTRUCTIONS
+================================================================================
+
+Note of warning:
+================
+
+U-boot has a *strong* dependency with the l-loader and the arm trusted firmware
+repositories.
+
+The boot sequence is:
+	l-loader --> arm_trusted_firmware --> u-boot
+
+U-Boot needs to be aware of the BL31 runtime location and size to avoid writing
+over it. Currently, BL31 is being placed below the kernel text offset (check
+poplar.c) but this could change in the future.
+
+The current version of u-boot has been tested with:
+ - https://github.com/Linaro/poplar-l-loader.git
+
+	commit f0988698dcc5c08bd0a8f50aa0457e138a5f438c
+	Author: Alex Elder <elder@linaro.org>
+	Date:   Fri Jun 16 08:57:59 2017 -0500
+
+    l-loader: use external memory region definitions
+
+    The ARM Trusted Firmware code now has a header file that collects
+    all the definitions for the memory regions used for its boot stages.
+    Include that file where needed, and use the definitions found therein
+
+    Signed-off-by: Alex Elder <elder@linaro.org>
+
+
+ - https://github.com/Linaro/poplar-arm-trusted-firmware.git
+
+	commit 6ac42dd3be13c99aa8ce29a15073e2f19d935f68
+	Author: Alex Elder <elder@linaro.org>
+	Date:   Fri Jun 16 09:24:50 2017 -0500
+
+    poplar: define memory regions in a separate file
+
+    Separate the definitions for memory regions used for the BL stage
+    images and FIP into a new file.  The "l-loader" image uses knowledge
+    of the sizes and locations of these memory regions, and it can now
+    include this (external) header to get these definitions, rather than
+    having to make coordinated changes to both code bases.
+
+    The new file has a complete set of definitions (more than may be
+    required by one or the other user).  It also includes a summary of
+    how the boot process works, and how it uses these regions.
+
+    It should now be relatively easy to adjust the sizes and locations
+    of these memory regions, or to add to them (e.g. for TEE).
+
+    Signed-off-by: Alex Elder <elder@linaro.org>
+
+
+Compile from source:
+====================
+
+Get all the sources
+
+  > mkdir -p ~/poplar/src ~/poplar/bin
+  > cd ~/poplar/src
+  > git clone https://github.com/Linaro/poplar-l-loader.git l-loader
+  > git clone https://github.com/Linaro/poplar-arm-trusted-firmware.git atf
+  > git clone https://github.com/Linaro/poplar-u-boot.git u-boot
+
+Make sure you are using the correct branch on each one of these repositories.
+The definition of "correct" might change over time (at this moment in time this
+would be the "latest" branch).
+
+Compile U-Boot:
+===============
+
+  Prerequisite:
+  # sudo apt-get install device-tree-compiler
+
+  > cd ~/poplar/src/u-boot
+  > make CROSS_COMPILE=aarch64-linux-gnu- poplar_defconfig
+  > make CROSS_COMPILE=aarch64-linux-gnu-
+  > cp u-boot.bin ~/poplar/bin
+
+Compile ARM Trusted Firmware (ATF):
+===================================
+
+  > cd ~/poplar/src/atf
+  > make CROSS_COMPILE=aarch64-linux-gnu- all fip \
+		SPD=none BL33=~/poplar/bin/u-boot.bin DEBUG=1 PLAT=poplar
+
+Copy resulting binaries
+  > cp build/hi3798cv200/debug/bl1.bin ~/poplar/src/l-loader/atf/
+  > cp build/hi3798cv200/debug/fip.bin ~/poplar/src/l-loader/atf/
+
+Compile l-loader:
+=================
+
+  > cd ~/poplar/src/l-loader
+  > make clean
+  > make CROSS_COMPILE=arm-linux-gnueabi-
+
+   Due to BootROM requiremets, rename l-loader.bin to fastboot.bin:
+  > cp l-loader.bin ~/poplar/bin/fastboot.bin
+
+
+================================================================================
+			FLASH INSTRUCTIONS
+================================================================================
+
+Two methods:
+
+Using USB debrick support:
+	Copy fastboot.bin to a FAT partition on the USB drive and reboot the
+       poplar board while pressing S3(usb_boot).
+
+       The system will execute the new u-boot and boot into a shell which you
+       can then use to write to eMMC.
+
+Using U-BOOT from shell:
+	1) using AXIS usb ethernet dongle and tftp
+	2) using FAT formated USB drive
+
+
+1. TFTP (USB ethernet dongle)
+=============================
+
+Plug a USB AXIS ethernet dongle on any of the USB2 ports on the Poplar board.
+Copy fastboot.bin to your tftp server.
+In u-boot make sure your network is properly setup.
+
+Then
+
+=> tftp 0x30000000 fastboot.bin
+starting USB...
+USB0:   USB EHCI 1.00
+scanning bus 0 for devices... 1 USB Device(s) found
+USB1:   USB EHCI 1.00
+scanning bus 1 for devices... 3 USB Device(s) found
+       scanning usb for storage devices... 0 Storage Device(s) found
+       scanning usb for ethernet devices... 1 Ethernet Device(s) found
+Waiting for Ethernet connection... done.
+Using asx0 device
+TFTP from server 192.168.1.4; our IP address is 192.168.1.10
+Filename 'poplar/fastboot.bin'.
+Load address: 0x30000000
+Loading: #################################################################
+	 #################################################################
+	 ###############################################################
+	 2 MiB/s
+done
+Bytes transferred = 983040 (f0000 hex)
+
+=> mmc write 0x30000000 0 0x780
+
+MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
+=> reset
+
+
+2. USING USB FAT DRIVE
+=======================
+
+Copy fastboot.bin to any partition on a FAT32 formated usb flash drive.
+Enter the uboot prompt
+
+=> fatls usb 0:2
+   983040   fastboot.bin
+
+1 file(s), 0 dir(s)
+
+=> fatload usb 0:2 0x30000000 fastboot.bin
+reading fastboot.bin
+983040 bytes read in 44 ms (21.3 MiB/s)
+
+=> mmc write 0x30000000 0 0x780
+
+MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK
+
+
+================================================================================
+				BOOT TRACE
+================================================================================
+
+Bootrom start
+Boot Media: eMMC
+Decrypt auxiliary code ...OK
+
+lsadc voltage min: 000000FE, max: 000000FF, aver: 000000FE, index: 00000000
+
+Entry boot auxiliary code
+
+Auxiliary code - v1.00
+DDR code - V1.1.2 20160205
+Build: Mar 24 2016 - 17:09:44
+Reg Version:  v134
+Reg Time:     2016/03/18 09:44:55
+Reg Name:     hi3798cv2dmb_hi3798cv200_ddr3_2gbyte_8bitx4_4layers.reg
+
+Boot auxiliary code success
+Bootrom success
+
+LOADER:  Switched to aarch64 mode
+LOADER:  Entering ARM TRUSTED FIRMWARE
+LOADER:  CPU0 executes at 0x000ce000
+
+INFO:    BL1: 0xe1000 - 0xe7000 [size = 24576]
+NOTICE:  Booting Trusted Firmware
+NOTICE:  BL1: v1.3(debug):v1.3-372-g1ba9c60
+NOTICE:  BL1: Built : 17:51:33, Apr 30 2017
+INFO:    BL1: RAM 0xe1000 - 0xe7000
+INFO:    BL1: Loading BL2
+INFO:    Loading image id=1 at address 0xe9000
+INFO:    Image id=1 loaded at address 0xe9000, size = 0x5008
+NOTICE:  BL1: Booting BL2
+INFO:    Entry point address = 0xe9000
+INFO:    SPSR = 0x3c5
+NOTICE:  BL2: v1.3(debug):v1.3-372-g1ba9c60
+NOTICE:  BL2: Built : 17:51:33, Apr 30 2017
+INFO:    BL2: Loading BL31
+INFO:    Loading image id=3 at address 0x129000
+INFO:    Image id=3 loaded at address 0x129000, size = 0x8038
+INFO:    BL2: Loading BL33
+INFO:    Loading image id=5 at address 0x37000000
+INFO:    Image id=5 loaded at address 0x37000000, size = 0x58f17
+NOTICE:  BL1: Booting BL31
+INFO:    Entry point address = 0x129000
+INFO:    SPSR = 0x3cd
+INFO:    Boot bl33 from 0x37000000 for 364311 Bytes
+NOTICE:  BL31: v1.3(debug):v1.3-372-g1ba9c60
+NOTICE:  BL31: Built : 17:51:33, Apr 30 2017
+INFO:    BL31: Initializing runtime services
+INFO:    BL31: Preparing for EL3 exit to normal world
+INFO:    Entry point address = 0x37000000
+INFO:    SPSR = 0x3c9
+
+
+U-Boot 2017.05-rc2-00130-gd2255b0 (Apr 30 2017 - 17:51:28 +0200)poplar
+
+Model: HiSilicon Poplar Development Board
+BOARD: Hisilicon HI3798cv200 Poplar
+DRAM:  1 GiB
+MMC:   Hisilicon DWMMC: 0
+In:    serial@f8b00000
+Out:   serial@f8b00000
+Err:   serial@f8b00000
+Net:   Net Initialization Skipped
+No ethernet found.
+
+Hit any key to stop autoboot:  0
+starting USB...
+USB0:   USB EHCI 1.00
+scanning bus 0 for devices... 1 USB Device(s) found
+USB1:   USB EHCI 1.00
+scanning bus 1 for devices... 4 USB Device(s) found
+       scanning usb for storage devices... 1 Storage Device(s) found
+       scanning usb for ethernet devices... 1 Ethernet Device(s) found
+
+USB device 0:
+    Device 0: Vendor: SanDisk Rev: 1.00 Prod: Cruzer Blade
+	    Type: Removable Hard Disk
+	    Capacity: 7632.0 MB = 7.4 GB (15630336 x 512)
+... is now current device
+Scanning usb 0:1...
+=>
diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c
new file mode 100644
index 0000000..d542f68
--- /dev/null
+++ b/board/hisilicon/poplar/poplar.c
@@ -0,0 +1,174 @@
+/*
+ * (C) Copyright 2017 Linaro
+ * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dm.h>
+#include <common.h>
+#include <asm/io.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <asm/arch/hi3798cv200.h>
+#include <asm/arch/dwmmc.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region poplar_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		0,
+	}
+};
+
+struct mm_region *mem_map = poplar_mem_map;
+
+static const struct pl01x_serial_platdata serial_platdata = {
+	.base = REG_BASE_UART0,
+	.type = TYPE_PL010,
+	.clock = 75000000,
+};
+
+U_BOOT_DEVICE(poplar_serial) = {
+	.name = "serial_pl01x",
+	.platdata = &serial_platdata,
+};
+
+int checkboard(void)
+{
+	puts("BOARD: Hisilicon HI3798cv200 Poplar\n");
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	psci_system_reset();
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size(NULL, 0x80000000);
+
+	return 0;
+}
+
+/*
+ * Some linux kernel versions don't use memory before its load address, so to
+ * be generic we just pretend it isn't there.  In previous uboot versions we
+ * carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code
+ * could persist in memory and be left alone by the kernel.
+ *
+ * That led to a problem when mapping memory in older kernels.  That PSCI code
+ * now lies in memory below the kernel load offset; it therefore won't be
+ * touched by the kernel, and by not specially reserving it we avoid the mapping
+ * problem as well.
+ *
+ */
+#define KERNEL_TEXT_OFFSET	0x00080000
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET;
+	gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start;
+
+	return 0;
+}
+
+static void usb2_phy_config(void)
+{
+	const u32 config[] = {
+		/* close EOP pre-emphasis. open data pre-emphasis */
+		0xa1001c,
+		/* Rcomp = 150mW, increase DC level */
+		0xa00607,
+		/* keep Rcomp working */
+		0xa10700,
+		/* Icomp = 212mW, increase current drive */
+		0xa00aab,
+		/* EMI fix: rx_active not stay 1 when error packets received */
+		0xa11140,
+		/* Comp mode select */
+		0xa11041,
+		/* adjust eye diagram */
+		0xa0098c,
+		/* adjust eye diagram */
+		0xa10a0a,
+	};
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(config); i++) {
+		writel(config[i], PERI_CTRL_USB0);
+		clrsetbits_le32(PERI_CTRL_USB0, BIT(21), BIT(20) | BIT(22));
+		udelay(20);
+	}
+}
+
+static void usb2_phy_init(void)
+{
+	/* reset usb2 controller bus/utmi/roothub */
+	setbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
+			USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
+	udelay(200);
+
+	/* reset usb2 phy por/utmi */
+	setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1);
+	udelay(200);
+
+	/* open usb2 ref clk */
+	setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN);
+	udelay(300);
+
+	/* cancel usb2 power on reset */
+	clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ);
+	udelay(500);
+
+	usb2_phy_config();
+
+	/* cancel usb2 port reset, wait comp circuit stable */
+	clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1);
+	mdelay(10);
+
+	/* open usb2 controller clk */
+	setbits_le32(PERI_CRG46, USB2_BUS_CKEN | USB2_OHCI48M_CKEN |
+			USB2_OHCI12M_CKEN | USB2_OTG_UTMI_CKEN |
+			USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN);
+	udelay(200);
+
+	/* cancel usb2 control reset */
+	clrbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ |
+			USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ);
+	udelay(200);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	ret = hi6220_dwmci_add_port(0, REG_BASE_MCI, 8);
+	if (ret)
+		printf("mmc init error (%d)\n", ret);
+
+	return ret;
+}
+
+int board_init(void)
+{
+	usb2_phy_init();
+
+	return 0;
+}
+
diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c
index 4330cf0..1deb2bd 100644
--- a/board/htkw/mcx/mcx.c
+++ b/board/htkw/mcx/mcx.c
@@ -17,9 +17,9 @@
 #include <asm/omap_gpio.h>
 #include <asm/arch/dss.h>
 #include <asm/arch/clock.h>
-#include "errno.h"
+#include <errno.h>
 #include <i2c.h>
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
 #include <usb.h>
 #include <asm/ehci-omap.h>
 #endif
@@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Address of the framebuffer in RAM. */
 #define FB_START_ADDRESS 0x88000000
 
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
 static struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
 	.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -100,7 +100,7 @@ void set_muxconf_regs(void)
 	MUX_MCX();
 }
 
-#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_MMC_OMAP_HS)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/huawei/hg556a/Kconfig b/board/huawei/hg556a/Kconfig
new file mode 100644
index 0000000..88622d0
--- /dev/null
+++ b/board/huawei/hg556a/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_HUAWEI_HG556A
+
+config SYS_BOARD
+	default "hg556a"
+
+config SYS_VENDOR
+	default "huawei"
+
+config SYS_CONFIG_NAME
+	default "huawei_hg556a"
+
+endif
diff --git a/board/huawei/hg556a/MAINTAINERS b/board/huawei/hg556a/MAINTAINERS
new file mode 100644
index 0000000..3ead7e4
--- /dev/null
+++ b/board/huawei/hg556a/MAINTAINERS
@@ -0,0 +1,6 @@
+HUAWEI HG556A BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/huawei/hg556a/
+F:	include/configs/huawei_hg556a.h
+F:	configs/huawei_hg556a_ram_defconfig
diff --git a/board/huawei/hg556a/Makefile b/board/huawei/hg556a/Makefile
new file mode 100644
index 0000000..ace0ed3
--- /dev/null
+++ b/board/huawei/hg556a/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += hg556a.o
diff --git a/board/huawei/hg556a/hg556a.c b/board/huawei/hg556a/hg556a.c
new file mode 100644
index 0000000..d181ca6
--- /dev/null
+++ b/board/huawei/hg556a/hg556a.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
diff --git a/board/ibf-dsp561/Kconfig b/board/ibf-dsp561/Kconfig
deleted file mode 100644
index acf5d7c..0000000
--- a/board/ibf-dsp561/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_IBF_DSP561
-
-config SYS_BOARD
-	default "ibf-dsp561"
-
-config SYS_CONFIG_NAME
-	default "ibf-dsp561"
-
-endif
diff --git a/board/ibf-dsp561/MAINTAINERS b/board/ibf-dsp561/MAINTAINERS
deleted file mode 100644
index dfd0f90..0000000
--- a/board/ibf-dsp561/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-IBF-DSP561 BOARD
-M:	I-SYST Micromodule <support@i-syst.com>
-S:	Maintained
-F:	board/ibf-dsp561/
-F:	include/configs/ibf-dsp561.h
-F:	configs/ibf-dsp561_defconfig
diff --git a/board/ibf-dsp561/Makefile b/board/ibf-dsp561/Makefile
deleted file mode 100644
index cbf1612..0000000
--- a/board/ibf-dsp561/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= ibf-dsp561.o
diff --git a/board/ibf-dsp561/config.mk b/board/ibf-dsp561/config.mk
deleted file mode 100644
index 854d7db..0000000
--- a/board/ibf-dsp561/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
diff --git a/board/ibf-dsp561/ibf-dsp561.c b/board/ibf-dsp561/ibf-dsp561.c
deleted file mode 100644
index 8475fda..0000000
--- a/board/ibf-dsp561/ibf-dsp561.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2009 I-SYST.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: I-SYST IBF-DSP561 Micromodule\n");
-	printf("       Support: http://www.i-syst.com/\n");
-	return 0;
-}
-
-#ifdef CONFIG_DRIVER_AX88180
-int board_eth_init(bd_t *bis)
-{
-	return ax88180_initialize(bis);
-}
-#endif
diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c
index e7838dc..4433e8c 100644
--- a/board/ids/ids8313/ids8313.c
+++ b/board/ids/ids8313/ids8313.c
@@ -119,14 +119,14 @@ static int setup_sdram(void)
 	return msize;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	fsl_lbc_t *lbc = &im->im_lbc;
 	u32 msize = 0;
 
 	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	msize = setup_sdram();
 
@@ -134,7 +134,9 @@ phys_size_t initdram(int board_type)
 	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
 	sync();
 
-	return msize;
+	gd->ram_size = msize;
+
+	return 0;
 }
 
 #if defined(CONFIG_OF_BOARD_SETUP)
diff --git a/board/ifm/ac14xx/Kconfig b/board/ifm/ac14xx/Kconfig
deleted file mode 100644
index 97e80d5..0000000
--- a/board/ifm/ac14xx/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_AC14XX
-
-config SYS_BOARD
-	default "ac14xx"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "ac14xx"
-
-endif
diff --git a/board/ifm/ac14xx/MAINTAINERS b/board/ifm/ac14xx/MAINTAINERS
deleted file mode 100644
index 8fd74e5..0000000
--- a/board/ifm/ac14xx/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-AC14XX BOARD
-M:	Anatolij Gustschin <agust@denx.de>
-S:	Maintained
-F:	board/ifm/ac14xx/
-F:	include/configs/ac14xx.h
-F:	configs/ac14xx_defconfig
diff --git a/board/ifm/ac14xx/Makefile b/board/ifm/ac14xx/Makefile
deleted file mode 100644
index 55def60..0000000
--- a/board/ifm/ac14xx/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= ac14xx.o
diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c
deleted file mode 100644
index 75bf1bb..0000000
--- a/board/ifm/ac14xx/ac14xx.c
+++ /dev/null
@@ -1,617 +0,0 @@
-/*
- * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
- * (C) Copyright 2009 Dave Srl www.dave.eu
- * (C) Copyright 2010 ifm ecomatic GmbH
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mpc512x.h>
-#include <fdt_support.h>
-#ifdef CONFIG_MISC_INIT_R
-#include <i2c.h>
-#endif
-
-static int eeprom_diag;
-static int mac_diag;
-static int gpio_diag;
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void gpio_configure(void)
-{
-	immap_t *im;
-	gpio512x_t *gpioregs;
-
-	im = (immap_t *) CONFIG_SYS_IMMR;
-	gpioregs = &im->gpio;
-	out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
-	out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
-
-	/*
-	 * out_be32(&gpioregs->gpdir, 0xC2293020);
-	 * workaround for a hardware effect: configure direction in pieces,
-	 * setting all outputs at once drops the reset line too low and
-	 * makes us lose the MII connection (breaks ethernet for us)
-	 */
-	out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
-	setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
-	udelay(10);
-	setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
-	udelay(10);
-	setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
-	udelay(10);
-	setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
-
-	/* to turn from red to yellow when U-Boot runs */
-	setbits_be32(&gpioregs->gpdat, 0x00002020);
-	out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
-	out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
-	out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
-	out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
-}
-
-/* the physical location of the pins */
-#define GPIOKEY_ROW_BITMASK	0x40000000
-#define GPIOKEY_ROW_UPPER	0
-#define GPIOKEY_ROW_LOWER	1
-
-#define GPIOKEY_COL0_BITMASK	0x20000000
-#define GPIOKEY_COL1_BITMASK	0x10000000
-#define GPIOKEY_COL2_BITMASK	0x08000000
-
-/* the logical presentation of pressed keys */
-#define GPIOKEY_BIT_FNLEFT	(1 << 5)
-#define GPIOKEY_BIT_FNRIGHT	(1 << 4)
-#define GPIOKEY_BIT_DIRUP	(1 << 3)
-#define GPIOKEY_BIT_DIRLEFT	(1 << 2)
-#define GPIOKEY_BIT_DIRRIGHT	(1 << 1)
-#define GPIOKEY_BIT_DIRDOWN	(1 << 0)
-
-/* the hotkey combination which starts recovery */
-#define GPIOKEY_BITS_RECOVERY	(GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
-				 GPIOKEY_BIT_DIRDOWN)
-
-static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
-{
-
-	if (row)
-		setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
-	else
-		clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
-	udelay(10);
-}
-
-static u32 gpio_querykbd(void)
-{
-	immap_t *im;
-	gpio512x_t *gpioregs;
-	u32 keybits;
-	u32 input;
-
-	im = (immap_t *)CONFIG_SYS_IMMR;
-	gpioregs = &im->gpio;
-	keybits = 0;
-
-	/* query upper row */
-	gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
-	input = in_be32(&gpioregs->gpdat);
-	if ((input & GPIOKEY_COL0_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_FNLEFT;
-	if ((input & GPIOKEY_COL1_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_DIRUP;
-	if ((input & GPIOKEY_COL2_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_FNRIGHT;
-
-	/* query lower row */
-	gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
-	input = in_be32(&gpioregs->gpdat);
-	if ((input & GPIOKEY_COL0_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_DIRLEFT;
-	if ((input & GPIOKEY_COL1_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_DIRRIGHT;
-	if ((input & GPIOKEY_COL2_BITMASK) == 0)
-		keybits |= GPIOKEY_BIT_DIRDOWN;
-
-	/* return bit pattern for keys */
-	return keybits;
-}
-
-/* excerpt from the recovery's hw_info.h */
-
-struct __attribute__ ((__packed__)) eeprom_layout {
-	char	magic[3];	/** 'ifm' */
-	u8	len[2];		/** content length without magic/len fields */
-	u8	version[3];	/** structure version */
-	u8	type;		/** type of PCB */
-	u8	reserved[0x37];	/** padding up to offset 0x40 */
-	u8	macaddress[6];	/** ethernet MAC (for the mainboard) @0x40 */
-};
-
-#define HW_COMP_MAINCPU 2
-
-static struct eeprom_layout eeprom_content;
-static int eeprom_was_read;	/* has_been_read */
-static int eeprom_is_valid;
-static int eeprom_version;
-
-#define get_eeprom_field_int(name) ({ \
-	int value; \
-	int idx; \
-	value = 0; \
-	for (idx = 0; idx < sizeof(name); idx++) { \
-		value <<= 8; \
-		value |= name[idx]; \
-	} \
-	value; \
-})
-
-static int read_eeprom(void)
-{
-	int eeprom_datalen;
-	int ret;
-
-	if (eeprom_was_read)
-		return 0;
-
-	eeprom_is_valid = 0;
-	ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
-			CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
-			(uchar *)&eeprom_content, sizeof(eeprom_content));
-	if (eeprom_diag) {
-		printf("DIAG: %s() read rc[%d], size[%d]\n",
-			__func__, ret, sizeof(eeprom_content));
-	}
-
-	if (ret != 0)
-		return -1;
-
-	eeprom_was_read = 1;
-
-	/*
-	 * check validity of EEPROM content
-	 * (check version, length, optionally checksum)
-	 */
-	eeprom_is_valid = 1;
-	eeprom_datalen = get_eeprom_field_int(eeprom_content.len);
-	eeprom_version = get_eeprom_field_int(eeprom_content.version);
-
-	if (eeprom_diag) {
-		printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n",
-			__func__, eeprom_content.magic[0],
-			eeprom_content.magic[1], eeprom_content.magic[2],
-			eeprom_datalen, eeprom_version, eeprom_content.type);
-	}
-	if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0)
-		eeprom_is_valid = 0;
-	if (eeprom_datalen < sizeof(struct eeprom_layout) - 5)
-		eeprom_is_valid = 0;
-	if ((eeprom_version != 1) && (eeprom_version != 2))
-		eeprom_is_valid = 0;
-	if (eeprom_content.type != HW_COMP_MAINCPU)
-		eeprom_is_valid = 0;
-
-	if (eeprom_diag)
-		printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid);
-
-	return ret;
-}
-
-int mac_read_from_eeprom(void)
-{
-	const u8 *mac;
-	const char *mac_txt;
-
-	if (read_eeprom()) {
-		printf("I2C EEPROM read failed.\n");
-		return -1;
-	}
-
-	if (!eeprom_is_valid) {
-		printf("I2C EEPROM content not valid\n");
-		return -1;
-	}
-
-	mac = NULL;
-	switch (eeprom_version) {
-	case 1:
-	case 2:
-		mac = (const u8 *)&eeprom_content.macaddress;
-		break;
-	}
-
-	if (mac && is_valid_ethaddr(mac)) {
-		eth_setenv_enetaddr("ethaddr", mac);
-		if (mac_diag) {
-			mac_txt = getenv("ethaddr");
-			if (mac_txt)
-				printf("DIAG: MAC value [%s]\n", mac_txt);
-			else
-				printf("DIAG: failed to setup MAC env\n");
-		}
-	}
-
-	return 0;
-}
-
-/*
- * BEWARE!
- * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
- * which the ADS, Aria or PDM360NG boards are using
- * (the steps outlined here refer to the Micron datasheet)
- */
-u32 sdram_init_seq[] = {
-	/* item 6, at least one NOP after CKE went high */
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	/* item 7, precharge all; item 8, tRP (20ns) */
-	CONFIG_SYS_DDRCMD_PCHG_ALL,
-	CONFIG_SYS_DDRCMD_NOP,
-	/* item 9, extended mode register; item 10, tMRD 10ns) */
-	CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
-	CONFIG_SYS_DDRCMD_NOP,
-	/*
-	 * item 11, (base) mode register _with_ reset DLL;
-	 * item 12, tMRD (10ns)
-	 */
-	CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
-	CONFIG_SYS_MICRON_BMODE_PARAM,
-	CONFIG_SYS_DDRCMD_NOP,
-	/* item 13, precharge all; item 14, tRP (20ns) */
-	CONFIG_SYS_DDRCMD_PCHG_ALL,
-	CONFIG_SYS_DDRCMD_NOP,
-	/*
-	 * item 15, auto refresh (i.e. refresh with CKE held high);
-	 * item 16, tRFC (70ns)
-	 */
-	CONFIG_SYS_DDRCMD_RFSH,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	/*
-	 * item 17, auto refresh (i.e. refresh with CKE held high);
-	 * item 18, tRFC (70ns)
-	 */
-	CONFIG_SYS_DDRCMD_RFSH,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	CONFIG_SYS_DDRCMD_NOP,
-	/* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
-	CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
-	CONFIG_SYS_DDRCMD_NOP,
-	/*
-	 * item 21, "actually done", but make sure 200 DRAM clock cycles
-	 * have passed after DLL reset before READ requests are issued
-	 * (200 cycles at 160MHz -> 1.25 usec)
-	 */
-	/* EMPTY, optional, we don't do it */
-};
-
-phys_size_t initdram(int board_type)
-{
-	return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
-}
-
-int misc_init_r(void)
-{
-	u32 keys;
-	char *s;
-	int want_recovery;
-
-	/* we use bus I2C-0 for the on-board eeprom */
-	i2c_set_bus_num(0);
-
-	/* setup GPIO directions and initial values */
-	gpio_configure();
-
-	/*
-	 * enforce the start of the recovery system when
-	 * - the appropriate keys were pressed
-	 * - "some" external software told us to
-	 * - a previous installation was aborted or has failed
-	 */
-	want_recovery = 0;
-	keys = gpio_querykbd();
-	if (gpio_diag)
-		printf("GPIO keyboard status [0x%02X]\n", keys);
-	if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
-		printf("detected recovery request (keyboard)\n");
-		want_recovery = 1;
-	}
-	s = getenv("want_recovery");
-	if ((s != NULL) && (*s != '\0')) {
-		printf("detected recovery request (environment)\n");
-		want_recovery = 1;
-	}
-	s = getenv("install_in_progress");
-	if ((s != NULL) && (*s != '\0')) {
-		printf("previous installation has not completed\n");
-		want_recovery = 1;
-	}
-	s = getenv("install_failed");
-	if ((s != NULL) && (*s != '\0')) {
-		printf("previous installation has failed\n");
-		want_recovery = 1;
-	}
-	if (want_recovery) {
-		printf("enforced start of the recovery system\n");
-		setenv("bootcmd", "run recovery");
-	}
-
-	/*
-	 * boot the recovery system without waiting; boot the
-	 * production system without waiting by default, only
-	 * insert a pause (to provide a chance to get a prompt)
-	 * when GPIO keys were pressed during power on
-	 */
-	if (want_recovery)
-		setenv("bootdelay", "0");
-	else if (!keys)
-		setenv("bootdelay", "0");
-	else
-		setenv("bootdelay", "2");
-
-	/* get the ethernet MAC from I2C EEPROM */
-	mac_read_from_eeprom();
-
-	return 0;
-}
-
-/* setup specific IO pad configuration */
-static  iopin_t ioregs_init[] = {
-	{	/* LPC CS3 */
-		offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	{	/* LPC CS1 */
-		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* LPC CS2 */
-		offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* LPC CS4, CS5 */
-		offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	{	/* SDHC CLK, CMD, D0, D1, D2, D3 */
-		offsetof(struct ioctrl512x, io_control_pata_ior), 6,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	{	/* GPIO keyboard */
-		offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO DN1 PF, LCD power, DN2 PF */
-		offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO reset AS-i */
-		offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO reset safety */
-		offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO reset netX */
-		offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO ma2 en */
-		offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO SD CD, SD WP */
-		offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* FEC RX DV */
-		offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(2),
-	},
-	{	/* GPIO AS-i prog, AS-i done, LCD backlight */
-		offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO AS-i wdg */
-		offsetof(struct ioctrl512x, io_control_pci_req2), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO safety wdg */
-		offsetof(struct ioctrl512x, io_control_pci_req1), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO netX wdg */
-		offsetof(struct ioctrl512x, io_control_pci_req0), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO IRQ powerfail */
-		offsetof(struct ioctrl512x, io_control_pci_inta), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO AS-i PWRD */
-		offsetof(struct ioctrl512x, io_control_pci_frame), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO LED0, LED1 */
-		offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
-		offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/* DIU clk */
-		offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(2),
-	},
-	{	/* FEC TX ER, CRS */
-		offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	{	/* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
-		offsetof(struct ioctrl512x, io_control_irq0), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	{	/*
-		 * FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
-		 * rdx 3-0, mdio, rx clk
-		 */
-		offsetof(struct ioctrl512x, io_control_psc0_0), 15,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	/* optional: make sure PSC3 remains the serial console */
-	{	/* LPC CS6 */
-		offsetof(struct ioctrl512x, io_control_psc3_4), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	/* make sure PSC4 remains available for SPI,
-	    *BUT* PSC4_1 is a GPIO kind of SS! */
-	{	/* enforce drive strength on the SPI pin */
-		offsetof(struct ioctrl512x, io_control_psc4_0), 5,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{
-		offsetof(struct ioctrl512x, io_control_psc4_1), 1,
-		IO_PIN_OVER_FMUX,
-		IO_PIN_FMUX(3),
-	},
-	/* optional: make sure PSC5 remains available for SPI */
-	{	/* enforce drive strength on the SPI pin */
-		offsetof(struct ioctrl512x, io_control_psc5_0), 5,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(1),
-	},
-	{	/* LPC TSIZ1 */
-		offsetof(struct ioctrl512x, io_control_psc6_0), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(1) | IO_PIN_DS(2),
-	},
-	{	/* DIU hsync */
-		offsetof(struct ioctrl512x, io_control_psc6_1), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(1),
-	},
-	{	/* DIU vsync */
-		offsetof(struct ioctrl512x, io_control_psc6_4), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(1),
-	},
-	{	/* PSC7, part of DIU RGB */
-		offsetof(struct ioctrl512x, io_control_psc7_0), 2,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(1),
-	},
-	{	/* PSC7, safety UART */
-		offsetof(struct ioctrl512x, io_control_psc7_2), 2,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(0) | IO_PIN_DS(1),
-	},
-	{	/* DIU (part of) RGB[] */
-		offsetof(struct ioctrl512x, io_control_psc8_3), 16,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(1),
-	},
-	{	/* DIU data enable */
-		offsetof(struct ioctrl512x, io_control_psc11_4), 1,
-		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
-		IO_PIN_FMUX(2) | IO_PIN_DS(1),
-	},
-	/* reduce LPB drive strength for improved EMI */
-	{	/* LPC OE, LPC RW */
-		offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* LPC AX03 through LPC AD00 */
-		offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* LPC CS5 */
-		offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* SDHC CLK */
-		offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-	{	/* SDHC DATA */
-		offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
-		IO_PIN_OVER_DRVSTR,
-		IO_PIN_DS(2),
-	},
-};
-
-int checkboard(void)
-{
-	puts("Board: ifm AC14xx\n");
-
-	/* initialize function mux & slew rate IO inter alia on IO Pins  */
-	iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ifm/o2dnt2/Kconfig b/board/ifm/o2dnt2/Kconfig
deleted file mode 100644
index e9d32dd..0000000
--- a/board/ifm/o2dnt2/Kconfig
+++ /dev/null
@@ -1,77 +0,0 @@
-if TARGET_O2D
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o2d"
-
-endif
-
-if TARGET_O2D300
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o2d300"
-
-endif
-
-if TARGET_O2DNT2
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o2dnt2"
-
-endif
-
-if TARGET_O2I
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o2i"
-
-endif
-
-if TARGET_O2MNT
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o2mnt"
-
-endif
-
-if TARGET_O3DNT
-
-config SYS_BOARD
-	default "o2dnt2"
-
-config SYS_VENDOR
-	default "ifm"
-
-config SYS_CONFIG_NAME
-	default "o3dnt"
-
-endif
diff --git a/board/ifm/o2dnt2/MAINTAINERS b/board/ifm/o2dnt2/MAINTAINERS
deleted file mode 100644
index 002f89e..0000000
--- a/board/ifm/o2dnt2/MAINTAINERS
+++ /dev/null
@@ -1,20 +0,0 @@
-O2DNT2 BOARD
-M:	Anatolij Gustschin <agust@denx.de>
-S:	Maintained
-F:	board/ifm/o2dnt2/
-F:	include/configs/o2d.h
-F:	configs/O2D_defconfig
-F:	include/configs/o2d300.h
-F:	configs/O2D300_defconfig
-F:	include/configs/o2dnt2.h
-F:	configs/O2DNT2_defconfig
-F:	configs/O2DNT2_RAMBOOT_defconfig
-F:	include/configs/o2i.h
-F:	configs/O2I_defconfig
-F:	include/configs/o2mnt.h
-F:	configs/O2MNT_defconfig
-F:	configs/O2MNT_O2M110_defconfig
-F:	configs/O2MNT_O2M112_defconfig
-F:	configs/O2MNT_O2M113_defconfig
-F:	include/configs/o3dnt.h
-F:	configs/O3DNT_defconfig
diff --git a/board/ifm/o2dnt2/Makefile b/board/ifm/o2dnt2/Makefile
deleted file mode 100644
index 64d6ba8..0000000
--- a/board/ifm/o2dnt2/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2005-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= o2dnt2.o
diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c
deleted file mode 100644
index 4fc6809..0000000
--- a/board/ifm/o2dnt2/o2dnt2.c
+++ /dev/null
@@ -1,386 +0,0 @@
-/*
- * Partially derived from board code for digsyMTC,
- * (C) Copyright 2009
- * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
- *
- * (C) Copyright 2012
- * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <net.h>
-#include <pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000
-
-enum ifm_sensor_type {
-	O2DNT		= 0x00,	/* !< O2DNT 32MB */
-	O2DNT2		= 0x01,	/* !< O2DNT2 64MB */
-	O3DNT		= 0x02,	/* !< O3DNT 32MB */
-	O3DNT_MIN	= 0x40,	/* !< O3DNT Minerva 32MB */
-	UNKNOWN		= 0xff,	/* !< Unknow sensor */
-};
-
-static enum ifm_sensor_type gt_ifm_sensor_type;
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start(int hi_addr)
-{
-	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-	long control = SDRAM_CONTROL | hi_addr_bit;
-
-	/* unlock mode register */
-	out_be32(&sdram->ctrl, control | 0x80000000);
-
-	/* precharge all banks */
-	out_be32(&sdram->ctrl, control | 0x80000002);
-
-	/* auto refresh */
-	out_be32(&sdram->ctrl, control | 0x80000004);
-
-	/* set mode register */
-	out_be32(&sdram->mode, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32(&sdram->ctrl, control);
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
- *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
- */
-phys_size_t initdram(int board_type)
-{
-	struct mpc5xxx_mmap_ctl *mmap_ctl =
-		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
-	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-
-	if (gt_ifm_sensor_type == O2DNT2) {
-		/* activate SDRAM CS1 */
-		setbits_be32((void *)MPC5XXX_GPS_PORT_CONFIG, 0x80000000);
-	}
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32(&mmap_ctl->sdram0, 0x0000001E); /* 2 GB at 0x0 */
-	out_be32(&mmap_ctl->sdram1, 0x00000000); /* disabled */
-
-	/* setup config registers */
-	out_be32(&sdram->config1, SDRAM_CONFIG1);
-	out_be32(&sdram->config2, SDRAM_CONFIG2);
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32(&mmap_ctl->sdram0,
-			 (0x13 + __builtin_ffs(dramsize >> 20) - 1));
-	} else {
-		out_be32(&mmap_ctl->sdram0, 0); /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 */
-	out_be32(&mmap_ctl->sdram1, dramsize + 0x0000001E); /* 2G */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-
-	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
-					0x80000000);
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
-					0x80000000);
-	}
-
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else {
-		dramsize2 = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20))
-		dramsize2 = 0;
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0) {
-		out_be32(&mmap_ctl->sdram1, (dramsize |
-			 (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
-	} else {
-		out_be32(&mmap_ctl->sdram1, dramsize); /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32(&mmap_ctl->sdram0) & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = in_be32(&mmap_ctl->sdram1) & 0xFF;
-	if (dramsize2 >= 0x13)
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	else
-		dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
-		out_be32(&sdram->sdelay, 0x04);
-
-	return dramsize + dramsize2;
-}
-
-
-#define GPT_GPIO_IN	0x4
-
-int checkboard(void)
-{
-	struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
-	unsigned char board_config = 0;
-	int i;
-
-	/* switch gpt0 - gpt7 to input */
-	for (i = 0; i < 7; i++)
-		out_be32(&gpt[i].emsr, GPT_GPIO_IN);
-
-	/* get configuration byte on timer-port */
-	for (i = 0; i < 7; i++)
-		board_config |= (in_be32(&gpt[i].sr) & 0x100) >> (8 - i);
-
-	puts("Board: ");
-
-	switch (board_config) {
-	case 0:
-		puts("O2DNT\n");
-		gt_ifm_sensor_type = O2DNT;
-		break;
-	case 1:
-		puts("O3DNT\n");
-		gt_ifm_sensor_type = O3DNT;
-		break;
-	case 2:
-		puts("O2DNT2\n");
-		gt_ifm_sensor_type = O2DNT2;
-		break;
-	case 64:
-		puts("O3DNT Minerva\n");
-		gt_ifm_sensor_type = O3DNT_MIN;
-		break;
-	default:
-		puts("Unknown\n");
-		gt_ifm_sensor_type = UNKNOWN;
-		break;
-	}
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	struct mpc5xxx_lpb *lpb_regs = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
-
-	/*
-	 * Now, when we are in RAM, enable flash write access for detection
-	 * process. Note that CS_BOOT cannot be cleared when executing in flash.
-	 */
-	clrbits_be32(&lpb_regs->cs0_cfg, 1); /* clear RO */
-	/* disable CS_BOOT */
-	clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
-	/* enable CS0 */
-	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
-
-	return 0;
-}
-
-#define MIIM_LXT971_LED_CFG_REG		0x14
-#define LXT971_LED_CFG_LINK_STATUS	0x4000
-#define LXT971_LED_CFG_RX_TX_ACTIVITY	0x0700
-#define LXT971_LED_CFG_LINK_ACTIVITY	0x00D0
-#define LXT971_LED_CFG_PULSE_STRETCH	0x0002
-/*
- * Additional PHY intialization after reset in mpc5xxx_fec_init_phy()
- */
-void reset_phy(void)
-{
-	/*
-	 * Set LED configuration bits.
-	 * It can't be done in misc_init_r() since FEC is not
-	 * initialized at this time. Therefore we do it here.
-	 */
-	miiphy_write("FEC", CONFIG_PHY_ADDR, MIIM_LXT971_LED_CFG_REG,
-			LXT971_LED_CFG_LINK_STATUS |
-			LXT971_LED_CFG_RX_TX_ACTIVITY |
-			LXT971_LED_CFG_LINK_ACTIVITY |
-			LXT971_LED_CFG_PULSE_STRETCH);
-}
-
-#if defined(CONFIG_POST)
-/*
- * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
- * is left open, no keypress is detected.
- */
-int post_hotkeys_pressed(void)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
-
-	/*
-	 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
-	 * CODEC or UART mode. Consumer IrDA should still be possible.
-	 */
-	clrbits_be32(&gpio->port_config, 0x07000000);
-	setbits_be32(&gpio->port_config, 0x03000000);
-
-	/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
-	setbits_be32(&gpio->simple_gpioe, 0x20000000);
-
-	/* Configure GPIO_IRDA_1 as input */
-	clrbits_be32(&gpio->simple_ddr, 0x20000000);
-
-	return (in_be32(&gpio->simple_ival) & 0x20000000) ? 0 : 1;
-}
-#endif
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
-static void ft_adapt_flash_base(void *blob)
-{
-	flash_info_t	*dev = &flash_info[0];
-	int off;
-	struct fdt_property *prop;
-	int len;
-	u32 *reg, *reg2;
-
-	off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
-	if (off < 0) {
-		printf("Could not find fsl,mpc5200b-lpb node.\n");
-		return;
-	}
-
-	/* found compatible property */
-	prop = fdt_get_property_w(blob, off, "ranges", &len);
-	if (prop) {
-		reg = reg2 = (u32 *)&prop->data[0];
-
-		reg[2] = dev->start[0];
-		reg[3] = dev->size;
-		fdt_setprop(blob, off, "ranges", reg2, len);
-	} else
-		printf("Could not find ranges\n");
-}
-
-extern ulong flash_get_size(phys_addr_t base, int banknum);
-
-/* Update the flash baseaddr settings */
-int update_flash_size(int flash_size)
-{
-	struct mpc5xxx_mmap_ctl *mm =
-		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
-	flash_info_t *dev;
-	int i;
-	int size = 0;
-	unsigned long base = 0x0;
-	u32 *cs_reg = (u32 *)&mm->cs0_start;
-
-	for (i = 0; i < 2; i++) {
-		dev = &flash_info[i];
-
-		if (dev->size) {
-			/* calculate new base addr for this chipselect */
-			base -= dev->size;
-			out_be32(cs_reg, START_REG(base));
-			cs_reg++;
-			out_be32(cs_reg, STOP_REG(base, dev->size));
-			cs_reg++;
-			/* recalculate the sectoraddr in the cfi driver */
-			size += flash_get_size(base, i);
-		}
-	}
-	flash_protect_default();
-	gd->bd->bi_flashstart = base;
-	return 0;
-}
-#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	int phy_addr = CONFIG_PHY_ADDR;
-	char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
-
-	ft_cpu_setup(blob, bd);
-
-#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
-#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-	/* Update reg property in all nor flash nodes too */
-	fdt_fixup_nor_flash_size(blob);
-#endif
-	ft_adapt_flash_base(blob);
-#endif
-	/* fix up the phy address */
-	do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/imgtec/boston/Kconfig b/board/imgtec/boston/Kconfig
new file mode 100644
index 0000000..ab76a3c
--- /dev/null
+++ b/board/imgtec/boston/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_BOSTON
+
+config SYS_BOARD
+	default "boston"
+
+config SYS_VENDOR
+	default "imgtec"
+
+config SYS_CONFIG_NAME
+	default "boston"
+
+config SYS_TEXT_BASE
+	default 0x9fc00000 if 32BIT
+	default 0xffffffff9fc00000 if 64BIT
+
+endif
diff --git a/board/imgtec/boston/MAINTAINERS b/board/imgtec/boston/MAINTAINERS
new file mode 100644
index 0000000..ec850d2
--- /dev/null
+++ b/board/imgtec/boston/MAINTAINERS
@@ -0,0 +1,9 @@
+BOSTON BOARD
+M:	Paul Burton <paul.burton@imgtec.com>
+S:	Maintained
+F:	board/imgtec/boston/
+F:	include/configs/boston.h
+F:	configs/boston32r2_defconfig
+F:	configs/boston32r2el_defconfig
+F:	configs/boston64r2_defconfig
+F:	configs/boston64r2el_defconfig
diff --git a/board/imgtec/boston/Makefile b/board/imgtec/boston/Makefile
new file mode 100644
index 0000000..d3fd49d
--- /dev/null
+++ b/board/imgtec/boston/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2016 Imagination Technologies
+#
+# SPDX-License-Identifier:	GPL-2.0
+#
+
+obj-y += checkboard.o
+obj-y += ddr.o
+obj-y += dt.o
+obj-y += lowlevel_init.o
diff --git a/board/imgtec/boston/boston-lcd.h b/board/imgtec/boston/boston-lcd.h
new file mode 100644
index 0000000..9f5c1b9
--- /dev/null
+++ b/board/imgtec/boston/boston-lcd.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __BOARD_BOSTON_LCD_H__
+#define __BOARD_BOSTON_LCD_H__
+
+/**
+ * lowlevel_display() - Display a message on Boston's LCD
+ * @msg: The string to display
+ *
+ * Display the string @msg on the 7 character LCD display of the Boston board.
+ * This is typically used for debug or to present some form of status
+ * indication to the user, allowing faults to be identified when things go
+ * wrong early enough that the UART isn't up.
+ */
+void lowlevel_display(const char msg[static 8]);
+
+#endif /* __BOARD_BOSTON_LCD_H__ */
diff --git a/board/imgtec/boston/boston-regs.h b/board/imgtec/boston/boston-regs.h
new file mode 100644
index 0000000..b9dfbb4
--- /dev/null
+++ b/board/imgtec/boston/boston-regs.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __BOARD_BOSTON_REGS_H__
+#define __BOARD_BOSTON_REGS_H__
+
+#include <asm/addrspace.h>
+
+#define BOSTON_PLAT_BASE		CKSEG1ADDR(0x17ffd000)
+#define BOSTON_LCD_BASE			CKSEG1ADDR(0x17fff000)
+
+/*
+ * Platform Register Definitions
+ */
+#define BOSTON_PLAT_CORE_CL		(BOSTON_PLAT_BASE + 0x04)
+
+#define BOSTON_PLAT_DDR3STAT		(BOSTON_PLAT_BASE + 0x14)
+# define BOSTON_PLAT_DDR3STAT_CALIB	(1 << 2)
+
+#define BOSTON_PLAT_DDRCONF0		(BOSTON_PLAT_BASE + 0x38)
+# define BOSTON_PLAT_DDRCONF0_SIZE	(0xf << 0)
+
+#endif /* __BOARD_BOSTON_REGS_H__ */
diff --git a/board/imgtec/boston/checkboard.c b/board/imgtec/boston/checkboard.c
new file mode 100644
index 0000000..93eae7f
--- /dev/null
+++ b/board/imgtec/boston/checkboard.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+
+#include "boston-lcd.h"
+#include "boston-regs.h"
+
+int checkboard(void)
+{
+	u32 changelist;
+
+	lowlevel_display("U-boot  ");
+
+	printf("Board: MIPS Boston\n");
+
+	printf("CPU:   0x%08x", read_c0_prid());
+	changelist = __raw_readl((uint32_t *)BOSTON_PLAT_CORE_CL);
+	if (changelist > 1)
+		printf(" cl%x", changelist);
+	putc('\n');
+
+	return 0;
+}
diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c
new file mode 100644
index 0000000..3479b98
--- /dev/null
+++ b/board/imgtec/boston/ddr.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+
+#include "boston-regs.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	u32 ddrconf0 = __raw_readl((uint32_t *)BOSTON_PLAT_DDRCONF0);
+
+	gd->ram_size = (phys_size_t)(ddrconf0 & BOSTON_PLAT_DDRCONF0_SIZE) <<
+			30;
+
+	return 0;
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) {
+		/* 2GB wrapped around to 0 */
+		return CKSEG0ADDR(256 << 20);
+	}
+
+	return min_t(unsigned long, gd->ram_top, CKSEG0ADDR(256 << 20));
+}
diff --git a/board/imgtec/boston/dt.c b/board/imgtec/boston/dt.c
new file mode 100644
index 0000000..b34f9bc
--- /dev/null
+++ b/board/imgtec/boston/dt.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	u64 mem_start[2], mem_size[2];
+	int mem_regions;
+
+	mem_start[0] = 0;
+	mem_size[0] = min_t(u64, 256llu << 20, gd->ram_size);
+	mem_regions = 1;
+
+	if (gd->ram_size > mem_size[0]) {
+		mem_start[1] = 0x80000000 + mem_size[0];
+		mem_size[1] = gd->ram_size - mem_size[0];
+		mem_regions++;
+	}
+
+	return fdt_fixup_memory_banks(blob, mem_start, mem_size, mem_regions);
+}
diff --git a/board/imgtec/boston/lowlevel_init.S b/board/imgtec/boston/lowlevel_init.S
new file mode 100644
index 0000000..0c01aa9
--- /dev/null
+++ b/board/imgtec/boston/lowlevel_init.S
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <config.h>
+
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+
+#include "boston-regs.h"
+
+.data
+
+msg_ddr_cal:	.ascii "DDR Cal "
+msg_ddr_ok:	.ascii "DDR OK  "
+
+.text
+
+LEAF(lowlevel_init)
+	move	s0, ra
+
+	PTR_LA	a0, msg_ddr_cal
+	bal	lowlevel_display
+
+	PTR_LI	t0, BOSTON_PLAT_DDR3STAT
+1:	lw	t1, 0(t0)
+	andi	t1, t1, BOSTON_PLAT_DDR3STAT_CALIB
+	beqz	t1, 1b
+
+	PTR_LA	a0, msg_ddr_ok
+	bal	lowlevel_display
+
+	move	v0, zero
+	jr	s0
+	END(lowlevel_init)
+
+LEAF(lowlevel_display)
+	.set	push
+	.set	noat
+	PTR_LI	AT, BOSTON_LCD_BASE
+#ifdef CONFIG_64BIT
+	ld	k1, 0(a0)
+	sd	k1, 0(AT)
+#else
+	lw	k1, 0(a0)
+	sw	k1, 0(AT)
+	lw	k1, 4(a0)
+	sw	k1, 4(AT)
+#endif
+	.set	pop
+1:	jr	ra
+	END(lowlevel_display)
diff --git a/board/imgtec/malta/MAINTAINERS b/board/imgtec/malta/MAINTAINERS
index a0b3284..052ec67 100644
--- a/board/imgtec/malta/MAINTAINERS
+++ b/board/imgtec/malta/MAINTAINERS
@@ -3,5 +3,7 @@ M:	Paul Burton <paul.burton@imgtec.com>
 S:	Maintained
 F:	board/imgtec/malta/
 F:	include/configs/malta.h
+F:	configs/malta64_defconfig
+F:	configs/malta64el_defconfig
 F:	configs/malta_defconfig
 F:	configs/maltael_defconfig
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
index 3d48cdc..6df4d9f 100644
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -28,12 +28,6 @@
 
 	.globl	lowlevel_init
 lowlevel_init:
-	/* disable any L2 cache for now */
-	sync
-	mfc0	t0, CP0_CONFIG, 2
-	ori	t0, t0, 0x1 << 12
-	mtc0	t0, CP0_CONFIG, 2
-
 	/* detect the core card */
 	PTR_LI	t0, CKSEG1ADDR(MALTA_REVISION)
 	lw	t0, 0(t0)
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 4955043..de81aa0 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -19,6 +19,8 @@
 
 #include "superio.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 enum core_card {
 	CORE_UNKNOWN,
 	CORE_LV,
@@ -83,9 +85,11 @@ static enum sys_con malta_sys_con(void)
 	}
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
-	return CONFIG_SYS_MEM_SIZE;
+	gd->ram_size = CONFIG_SYS_MEM_SIZE;
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/imgtec/xilfpga/Kconfig b/board/imgtec/xilfpga/Kconfig
new file mode 100644
index 0000000..b078278
--- /dev/null
+++ b/board/imgtec/xilfpga/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_XILFPGA
+
+config SYS_BOARD
+	default "xilfpga"
+
+config SYS_VENDOR
+	default "imgtec"
+
+config SYS_CONFIG_NAME
+	default "imgtec_xilfpga"
+
+config SYS_TEXT_BASE
+	default 0x80C00000
+
+endif
diff --git a/board/imgtec/xilfpga/MAINTAINERS b/board/imgtec/xilfpga/MAINTAINERS
new file mode 100644
index 0000000..aa04532
--- /dev/null
+++ b/board/imgtec/xilfpga/MAINTAINERS
@@ -0,0 +1,6 @@
+XILFPGA BOARD
+M:	Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
+S:	Maintained
+F:	board/imgtec/xilfpga
+F:	include/configs/xilfpga.h
+F:	configs/imgtec_xilfpga_defconfig
diff --git a/board/imgtec/xilfpga/Makefile b/board/imgtec/xilfpga/Makefile
new file mode 100644
index 0000000..9aaf9ce
--- /dev/null
+++ b/board/imgtec/xilfpga/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2016, Imagination Technologies Ltd.
+# Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+obj-y := xilfpga.o
diff --git a/board/imgtec/xilfpga/README b/board/imgtec/xilfpga/README
new file mode 100644
index 0000000..ac19d48
--- /dev/null
+++ b/board/imgtec/xilfpga/README
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2016, Imagination Technologies Ltd.
+ *
+ * Zubair Lutfullah Kakakhel, Zubair.Kakakhel@imgtec.com
+ */
+
+MIPSfpga
+=======================================
+
+MIPSfpga is an FPGA based development platform by Imagination Technologies
+As we are dealing with a MIPS core instantiated on an FPGA, specifications
+are fluid and can be varied in RTL.
+
+The example project provided by IMGTEC runs on the Nexys4DDR board by
+Digilent powered by the ARTIX-7 FPGA by Xilinx. Relevant details about
+the example project and the Nexys4DDR board:
+
+- microAptiv UP core m14Kc
+- 50MHz clock speed
+- 128Mbyte DDR RAM	at 0x0000_0000
+- 8Kbyte RAM		at 0x1000_0000
+- axi_intc		at 0x1020_0000
+- axi_uart16550		at 0x1040_0000
+- axi_gpio		at 0x1060_0000
+- axi_i2c		at 0x10A0_0000
+- custom_gpio		at 0x10C0_0000
+- axi_ethernetlite	at 0x10E0_0000
+- 8Kbyte BootRAM	at 0x1FC0_0000
+- 16Mbyte QPI		at 0x1D00_0000
+
+Boot protocol:
+--------------
+
+The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
+This is for easy reprogrammibility via JTAG.
+
+DDR initialization is already handled by a HW IP block.
+
+When the example project bitstream is loaded, the cpu_reset button
+needs to be pressed.
+
+The bootram initializes the cache and axi_uart
+Then checks if there is anything non 0xffff_ffff at location 0x1D40_0000
+
+If there is, then that is considered as u-boot. u-boot is copied from
+0x1D40_0000 to memory and the bootram jumps into u-boot code.
+
+At this point, the board is ready to load the Linux kernel + buildroot initramfs
+
+This can be done in multiple ways:
+
+1- JTAG load the binary and jump into it.
+2- Load kernel stored in the QSPI flash at 0x1D80_0000
+3- Load uImage via tftp. Ethernet works in u-boot.
+   e.g. env set server ip 192.168.154.45; dhcp uImage; bootm
diff --git a/board/imgtec/xilfpga/xilfpga.c b/board/imgtec/xilfpga/xilfpga.c
new file mode 100644
index 0000000..841d614
--- /dev/null
+++ b/board/imgtec/xilfpga/xilfpga.c
@@ -0,0 +1,24 @@
+/*
+ * Imagination Technologies MIPSfpga platform code
+ *
+ * Copyright (C) 2016, Imagination Technologies Ltd.
+ *
+ * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* initialize the DDR Controller and PHY */
+int dram_init(void)
+{
+	/* MIG IP block is smart and doesn't need SW
+	 * to do any init */
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;	/* in bytes */
+
+	return 0;
+}
diff --git a/board/imx31_phycore/Kconfig b/board/imx31_phycore/Kconfig
index d3d2025..e897ee1 100644
--- a/board/imx31_phycore/Kconfig
+++ b/board/imx31_phycore/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_IMX31_PHYCORE
+if TARGET_IMX31_PHYCORE || TARGET_IMX31_PHYCORE_EET
 
 config SYS_BOARD
 	default "imx31_phycore"
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
index 3f45e4e..6532466 100644
--- a/board/imx31_phycore/imx31_phycore.c
+++ b/board/imx31_phycore/imx31_phycore.c
@@ -11,6 +11,7 @@
 #include <netdev.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/mach-types.h>
 #include <asm/arch/sys_proto.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/in-circuit/grasshopper/Kconfig b/board/in-circuit/grasshopper/Kconfig
deleted file mode 100644
index 30e3855..0000000
--- a/board/in-circuit/grasshopper/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_GRASSHOPPER
-
-config SYS_BOARD
-	default "grasshopper"
-
-config SYS_VENDOR
-	default "in-circuit"
-
-config SYS_SOC
-	default "at32ap700x"
-
-config SYS_CONFIG_NAME
-	default "grasshopper"
-
-endif
diff --git a/board/in-circuit/grasshopper/MAINTAINERS b/board/in-circuit/grasshopper/MAINTAINERS
deleted file mode 100644
index 4abdea8..0000000
--- a/board/in-circuit/grasshopper/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-GRASSHOPPER BOARD
-M:	Andreas Bießmann <andreas@biessmann.org>
-S:	Maintained
-F:	board/in-circuit/grasshopper/
-F:	include/configs/grasshopper.h
-F:	configs/grasshopper_defconfig
diff --git a/board/in-circuit/grasshopper/Makefile b/board/in-circuit/grasshopper/Makefile
deleted file mode 100644
index 0457635..0000000
--- a/board/in-circuit/grasshopper/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2011
-# Corscience GmbH & Co.KG, Andreas Bießmann <biessmann@corscience.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-
-obj-y += grasshopper.o
diff --git a/board/in-circuit/grasshopper/grasshopper.c b/board/in-circuit/grasshopper/grasshopper.c
deleted file mode 100644
index 91b4116..0000000
--- a/board/in-circuit/grasshopper/grasshopper.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (C) 2011
- * Corscience GmbH & Co.KG, Andreas Bießmann <biessmann@corscience.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/sdram.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/hmatrix.h>
-#include <asm/arch/mmu.h>
-#include <asm/arch/portmux.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
-	{
-		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
-				| MMU_VMR_CACHE_NONE,
-	}, {
-		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
-				| MMU_VMR_CACHE_WRBACK,
-	},
-};
-
-static const struct sdram_config sdram_config = {
-	/* Dual MT48LC16M16A2-7E (or equal) */
-	.data_bits		= SDRAM_DATA_32BIT,
-	.row_bits		= 13,
-	.col_bits		= 9,
-	.bank_bits		= 2,
-	.cas			= 2,
-	.twr			= 2,
-	.trc			= 7,
-	.trp			= 2,
-	.trcd			= 2,
-	.tras			= 4,
-	.txsr			= 7,
-	/* 7.81 us */
-	.refresh_period		= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
-};
-
-int board_early_init_f(void)
-{
-	/* Enable SDRAM in the EBI mux */
-	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
-
-	portmux_enable_ebi(SDRAM_DATA_32BIT, 23, 0, PORTMUX_DRIVE_HIGH);
-	sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
-
-	portmux_enable_usart0(PORTMUX_DRIVE_MIN);
-	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
-#if defined(CONFIG_MACB)
-	/* set PHY reset and pwrdown to low */
-	portmux_select_gpio(PORTMUX_PORT_B, (1 << 29) | (1 << 30),
-		PORTMUX_DIR_OUTPUT | PORTMUX_INIT_LOW);
-	udelay(100);
-	/* release PHYs reset */
-	gpio_set_value(GPIO_PIN_PB(29), 1);
-
-	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
-#endif
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	gd->bd->bi_phy_id[0] = 0x00;
-	return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bi)
-{
-	macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
-	return 0;
-}
-#endif
-/* vim: set noet ts=8: */
diff --git a/board/inka4x0/Kconfig b/board/inka4x0/Kconfig
deleted file mode 100644
index 94a41f0..0000000
--- a/board/inka4x0/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_INKA4X0
-
-config SYS_BOARD
-	default "inka4x0"
-
-config SYS_CONFIG_NAME
-	default "inka4x0"
-
-endif
diff --git a/board/inka4x0/MAINTAINERS b/board/inka4x0/MAINTAINERS
deleted file mode 100644
index e8cec73..0000000
--- a/board/inka4x0/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-INKA4X0 BOARD
-M:	Anatolij Gustschin <agust@denx.de>
-S:	Maintained
-F:	board/inka4x0/
-F:	include/configs/inka4x0.h
-F:	configs/inka4x0_defconfig
diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile
deleted file mode 100644
index c9a3540..0000000
--- a/board/inka4x0/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2009
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= inka4x0.o inkadiag.o
diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c
deleted file mode 100644
index 0a32f0e..0000000
--- a/board/inka4x0/inka4x0.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- * (C) Copyright 2008-2009
- * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
- *
- * (C) Copyright 2009
- * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2004
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-
-#if defined(CONFIG_DDR_MT46V16M16)
-#include "mt46v16m16-75.h"
-#elif defined(CONFIG_SDR_MT48LC16M16A2)
-#include "mt48lc16m16a2-75.h"
-#elif defined(CONFIG_DDR_MT46V32M16)
-#include "mt46v32m16.h"
-#elif defined(CONFIG_DDR_HYB25D512160BF)
-#include "hyb25d512160bf.h"
-#elif defined(CONFIG_DDR_K4H511638C)
-#include "k4h511638c.h"
-#else
-#error "INKA4x0 SDRAM: invalid chip type specified!"
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	volatile struct mpc5xxx_sdram *sdram =
-		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
-
-	/* precharge all banks */
-	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	out_be32(&sdram->mode, SDRAM_EMODE);
-
-	/* set mode register: reset DLL */
-	out_be32(&sdram->mode, SDRAM_MODE | 0x04000000);
-#endif
-
-	/* precharge all banks */
-	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
-
-	/* auto refresh */
-	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
-
-	/* set mode register */
-	out_be32(&sdram->mode, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *	      is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
-	volatile struct mpc5xxx_mmap_ctl *mm =
-		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
-	volatile struct mpc5xxx_cdm     *cdm =
-		(struct mpc5xxx_cdm *)      MPC5XXX_CDM;
-	volatile struct mpc5xxx_sdram *sdram =
-		(struct mpc5xxx_sdram *)    MPC5XXX_SDRAM;
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	long test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32(&mm->sdram0, 0x0000001c);	/* 512MB at 0x0 */
-	out_be32(&mm->sdram1, 0x40000000);	/* disabled */
-
-	/* setup config registers */
-	out_be32(&sdram->config1, SDRAM_CONFIG1);
-	out_be32(&sdram->config2, SDRAM_CONFIG2);
-
-#if SDRAM_DDR
-	/* set tap delay */
-	out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32(&mm->sdram0, 0x13 +
-			 __builtin_ffs(dramsize >> 20) - 1);
-	} else {
-		out_be32(&mm->sdram0, 0); /* disabled */
-	}
-
-	out_be32(&mm->sdram1, dramsize); /* disabled */
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32(&mm->sdram0) & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	return dramsize;
-}
-
-int checkboard (void)
-{
-	puts ("Board: INKA 4X0\n");
-	return 0;
-}
-
-void flash_preinit(void)
-{
-	volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
-
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT (CS0) cannot be cleared when
-	 * executing in flash.
-	 */
-	clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
-}
-
-int misc_init_f (void)
-{
-	volatile struct mpc5xxx_gpio	*gpio    =
-		(struct mpc5xxx_gpio *)   MPC5XXX_GPIO;
-	volatile struct mpc5xxx_wu_gpio	*wu_gpio =
-		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-	volatile struct mpc5xxx_gpt	*gpt;
-	char tmp[10];
-	int i, br;
-
-	i = getenv_f("brightness", tmp, sizeof(tmp));
-	br = (i > 0)
-		? (int) simple_strtoul (tmp, NULL, 10)
-		: CONFIG_SYS_BRIGHTNESS;
-	if (br > 255)
-		br = 255;
-
-	/* Initialize GPIO output pins.
-	 */
-	/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
-	for (i = 0; i <= 5; i++) {
-		gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10));
-		out_be32(&gpt->emsr, 0x34);
-	}
-
-	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
-	gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10));
-	out_be32(&gpt->emsr,  0);		/* Disable */
-	out_be32(&gpt->cir,   0x020000fe);
-	out_be32(&gpt->pwmcr, (br << 16));
-	out_be32(&gpt->emsr,  0x3);		/* Enable PWM mode and start */
-
-	/* Configure PSC3_6,7 as GPIO output */
-	setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
-					  MPC5XXX_GPIO_SIMPLE_PSC3_7);
-	setbits_be32(&gpio->simple_ddr,   MPC5XXX_GPIO_SIMPLE_PSC3_6 |
-					  MPC5XXX_GPIO_SIMPLE_PSC3_7);
-
-	/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
-	setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_6 |
-				     MPC5XXX_GPIO_WKUP_7 |
-				     MPC5XXX_GPIO_WKUP_PSC3_9);
-	setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_6 |
-				     MPC5XXX_GPIO_WKUP_7 |
-				     MPC5XXX_GPIO_WKUP_PSC3_9);
-
-	/* Set LR mirror bit because it is low-active */
-	setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_7);
-
-	/* Reset Coral-P graphics controller */
-	setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC3_9);
-
-	/* Enable display backlight */
-	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
-	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
-	setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_8);
-	setbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_8);
-
-	/*
-	 * Configure three wire serial interface to RTC (PSC1_4,
-	 * PSC2_4, PSC3_4, PSC3_5)
-	 */
-	setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_PSC1_4 |
-				     MPC5XXX_GPIO_WKUP_PSC2_4);
-	setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_PSC1_4 |
-				     MPC5XXX_GPIO_WKUP_PSC2_4);
-	clrbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC1_4);
-	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 |
-				     MPC5XXX_GPIO_SINT_PSC3_5);
-	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 |
-				     MPC5XXX_GPIO_SINT_PSC3_5);
-	setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_5);
-	clrbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_5);
-
-	return 0;
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
diff --git a/board/inka4x0/inkadiag.c b/board/inka4x0/inkadiag.c
deleted file mode 100644
index 4c43205..0000000
--- a/board/inka4x0/inkadiag.c
+++ /dev/null
@@ -1,465 +0,0 @@
-/*
- * (C) Copyright 2008, 2009 Andreas Pfefferle,
- *     DENX Software Engineering, ap@denx.de.
- * (C) Copyright 2009 Detlev Zundel,
- *     DENX Software Engineering, dzu@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <common.h>
-#include <config.h>
-#include <console.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-
-#include <command.h>
-
-/* This is needed for the includes in ns16550.h */
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#include <ns16550.h>
-
-#define GPIO_BASE		((u_char *)CONFIG_SYS_CS3_START)
-
-#define DIGIN_TOUCHSCR_MASK	0x00003000	/* Inputs 12-13 */
-#define DIGIN_KEYB_MASK		0x00010000	/* Input 16 */
-
-#define DIGIN_DRAWER_SW1	0x00400000	/* Input 22 */
-#define DIGIN_DRAWER_SW2	0x00800000	/* Input 23 */
-
-#define DIGIO_LED0		0x00000001	/* Output 0 */
-#define DIGIO_LED1		0x00000002	/* Output 1 */
-#define DIGIO_LED2		0x00000004	/* Output 2 */
-#define DIGIO_LED3		0x00000008	/* Output 3 */
-#define DIGIO_LED4		0x00000010	/* Output 4 */
-#define DIGIO_LED5		0x00000020	/* Output 5 */
-
-#define DIGIO_DRAWER1		0x00000100	/* Output 8 */
-#define DIGIO_DRAWER2		0x00000200	/* Output 9 */
-
-#define SERIAL_PORT_BASE	((u_char *)CONFIG_SYS_CS2_START)
-
-#define PSC_OP1_RTS	0x01
-#define PSC_OP0_RTS	0x01
-
-/*
- * Table with supported baudrates (defined in inka4x0.h)
- */
-static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
-#define	N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0]))
-
-static unsigned int inka_digin_get_input(void)
-{
-	return in_8(GPIO_BASE + 0) << 0 | in_8(GPIO_BASE + 1) << 8 |
-		in_8(GPIO_BASE + 2) << 16 | in_8(GPIO_BASE + 3) << 24;
-}
-
-#define LED_HIGH(NUM)							\
-	do {								\
-		setbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \
-	} while (0)
-
-#define LED_LOW(NUM)							\
-	do {								\
-		clrbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \
-	} while (0)
-
-#define CHECK_LED(NUM) \
-    do { \
-	    if (state & (1 << NUM)) {		\
-		    LED_HIGH(NUM);		\
-	    } else {				\
-		    LED_LOW(NUM);		\
-	    }					\
-    } while (0)
-
-static void inka_digio_set_output(unsigned int state, int which)
-{
-	volatile struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
-	if (which == 0) {
-		/* other */
-		CHECK_LED(0);
-		CHECK_LED(1);
-		CHECK_LED(2);
-		CHECK_LED(3);
-		CHECK_LED(4);
-		CHECK_LED(5);
-	} else {
-		if (which == 1) {
-			/* drawer1 */
-			if (state) {
-				clrbits_be32(&gpio->simple_dvo, 0x1000);
-				udelay(1);
-				setbits_be32(&gpio->simple_dvo, 0x1000);
-			} else {
-				setbits_be32(&gpio->simple_dvo, 0x1000);
-				udelay(1);
-				clrbits_be32(&gpio->simple_dvo, 0x1000);
-			}
-		}
-		if (which == 2) {
-			/* drawer 2 */
-			if (state) {
-				clrbits_be32(&gpio->simple_dvo, 0x2000);
-				udelay(1);
-				setbits_be32(&gpio->simple_dvo, 0x2000);
-			} else {
-				setbits_be32(&gpio->simple_dvo, 0x2000);
-				udelay(1);
-				clrbits_be32(&gpio->simple_dvo, 0x2000);
-			}
-		}
-	}
-	udelay(1);
-}
-
-static int do_inkadiag_io(cmd_tbl_t *cmdtp, int flag, int argc,
-			  char * const argv[]) {
-	unsigned int state, val;
-
-	switch (argc) {
-	case 3:
-		/* Write a value */
-		val = simple_strtol(argv[2], NULL, 16);
-
-		if (strcmp(argv[1], "drawer1") == 0) {
-			inka_digio_set_output(val, 1);
-		} else if (strcmp(argv[1], "drawer2") == 0) {
-			inka_digio_set_output(val, 2);
-		} else if (strcmp(argv[1], "other") == 0)
-			inka_digio_set_output(val, 0);
-		else {
-			printf("Invalid argument: %s\n", argv[1]);
-			return -1;
-		}
-		/* fall through */
-	case 2:
-		/* Read a value */
-		state = inka_digin_get_input();
-
-		if (strcmp(argv[1], "drawer1") == 0) {
-			val = (state & DIGIN_DRAWER_SW1) >> (ffs(DIGIN_DRAWER_SW1) - 1);
-		} else if (strcmp(argv[1], "drawer2") == 0) {
-			val = (state & DIGIN_DRAWER_SW2) >> (ffs(DIGIN_DRAWER_SW2) - 1);
-		} else if (strcmp(argv[1], "other") == 0) {
-			val = ((state & DIGIN_KEYB_MASK) >> (ffs(DIGIN_KEYB_MASK) - 1))
-				| (state & DIGIN_TOUCHSCR_MASK) >> (ffs(DIGIN_TOUCHSCR_MASK) - 2);
-		} else {
-			printf("Invalid argument: %s\n", argv[1]);
-			return -1;
-		}
-		printf("exit code: 0x%X\n", val);
-		return 0;
-	default:
-		return cmd_usage(cmdtp);
-	}
-
-	return -1;
-}
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int ser_init(volatile struct mpc5xxx_psc *psc, int baudrate)
-{
-	unsigned long baseclk;
-	int div;
-
-	/* reset PSC */
-	out_8(&psc->command, PSC_SEL_MODE_REG_1);
-
-	/* select clock sources */
-
-	out_be16(&psc->psc_clock_select, 0);
-	baseclk = (gd->arch.ipb_clk + 16) / 32;
-
-	/* switch to UART mode */
-	out_be32(&psc->sicr, 0);
-
-	/* configure parity, bit length and so on */
-
-	out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
-	out_8(&psc->mode, PSC_MODE_ONE_STOP);
-
-	/* set up UART divisor */
-	div = (baseclk + (baudrate / 2)) / baudrate;
-	out_8(&psc->ctur, (div >> 8) & 0xff);
-	out_8(&psc->ctlr, div & 0xff);
-
-	/* disable all interrupts */
-	out_be16(&psc->psc_imr, 0);
-
-	/* reset and enable Rx/Tx */
-	out_8(&psc->command, PSC_RST_RX);
-	out_8(&psc->command, PSC_RST_TX);
-	out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
-
-	return 0;
-}
-
-static void ser_putc(volatile struct mpc5xxx_psc *psc, const char c)
-{
-	/* Wait 1 second for last character to go. */
-	int i = 0;
-
-	while (!(psc->psc_status & PSC_SR_TXEMP) && (i++ < 1000000/10))
-		udelay(10);
-	psc->psc_buffer_8 = c;
-
-}
-
-static int ser_getc(volatile struct mpc5xxx_psc *psc)
-{
-	/* Wait for a character to arrive. */
-	int i = 0;
-
-	while (!(in_be16(&psc->psc_status) & PSC_SR_RXRDY) && (i++ < 1000000/10))
-		udelay(10);
-
-	return in_8(&psc->psc_buffer_8);
-}
-
-static int do_inkadiag_serial(cmd_tbl_t *cmdtp, int flag, int argc,
-			      char * const argv[]) {
-	volatile struct NS16550 *uart;
-	volatile struct mpc5xxx_psc *psc;
-	unsigned int num, mode;
-	int combrd, baudrate, i, j, len;
-	int address;
-
-	if (argc < 5)
-		return cmd_usage(cmdtp);
-
-	argc--;
-	argv++;
-
-	num = simple_strtol(argv[0], NULL, 0);
-	if (num < 0 || num > 11) {
-		printf("invalid argument for num: %d\n", num);
-		return -1;
-	}
-
-	mode = simple_strtol(argv[1], NULL, 0);
-
-	combrd = 0;
-	baudrate = simple_strtoul(argv[2], NULL, 10);
-	for (i=0; i<N_BAUDRATES; ++i) {
-		if (baudrate == baudrate_table[i])
-			break;
-	}
-	if (i == N_BAUDRATES) {
-		printf("## Baudrate %d bps not supported\n",
-		       baudrate);
-		return 1;
-	}
-	combrd = 115200 / baudrate;
-
-	uart = (struct NS16550 *)(SERIAL_PORT_BASE + (num << 3));
-
-	printf("Testing uart %d.\n\n", num);
-
-	if ((num >= 0) && (num <= 7)) {
-		if (mode & 1) {
-			/* turn on 'loopback' mode */
-			out_8(&uart->mcr, UART_MCR_LOOP);
-		} else {
-			/*
-			 * establish the UART's operational parameters
-			 * set DLAB=1, so rbr accesses DLL
-			 */
-			out_8(&uart->lcr, UART_LCR_DLAB);
-			/* set baudrate */
-			out_8(&uart->rbr, combrd);
-			/* set data-format: 8-N-1 */
-			out_8(&uart->lcr, UART_LCR_WLS_8);
-		}
-
-		if (mode & 2) {
-			/* set request to send */
-			out_8(&uart->mcr, UART_MCR_RTS);
-			udelay(10);
-			/* check clear to send */
-			if ((in_8(&uart->msr) & UART_MSR_CTS) == 0x00)
-				return -1;
-		}
-		if (mode & 4) {
-			/* set data terminal ready */
-			out_8(&uart->mcr, UART_MCR_DTR);
-			udelay(10);
-			/* check data set ready and carrier detect */
-			if ((in_8(&uart->msr) & (UART_MSR_DSR | UART_MSR_DCD))
-			    != (UART_MSR_DSR | UART_MSR_DCD))
-				return -1;
-		}
-
-		/* write each message-character, read it back, and display it */
-		for (i = 0, len = strlen(argv[3]); i < len; ++i) {
-			j = 0;
-			while ((in_8(&uart->lsr) & UART_LSR_THRE) ==	0x00) {
-				if (j++ > CONFIG_SYS_HZ)
-					break;
-				udelay(10);
-			}
-			out_8(&uart->rbr, argv[3][i]);
-			j = 0;
-			while ((in_8(&uart->lsr) & UART_LSR_DR) == 0x00) {
-				if (j++ > CONFIG_SYS_HZ)
-					break;
-				udelay(10);
-			}
-			printf("%c", in_8(&uart->rbr));
-		}
-		printf("\n\n");
-		out_8(&uart->mcr, 0x00);
-	} else {
-		address = 0;
-
-		switch (num) {
-		case 8:
-			address = MPC5XXX_PSC6;
-			break;
-		case 9:
-			address = MPC5XXX_PSC3;
-			break;
-		case 10:
-			address = MPC5XXX_PSC2;
-			break;
-		case 11:
-			address = MPC5XXX_PSC1;
-			break;
-		}
-		psc = (struct mpc5xxx_psc *)address;
-		ser_init(psc, simple_strtol(argv[2], NULL, 0));
-		if (mode & 2) {
-			/* set request to send */
-			out_8(&psc->op0, PSC_OP0_RTS);
-			udelay(10);
-			/* check clear to send */
-			if ((in_8(&psc->ip) & PSC_IPCR_CTS) == 0)
-				return -1;
-		}
-		len = strlen(argv[3]);
-		for (i = 0; i < len; ++i) {
-			ser_putc(psc, argv[3][i]);
-			printf("%c", ser_getc(psc));
-		}
-		printf("\n\n");
-	}
-	return 0;
-}
-
-#define BUZZER_GPT	(MPC5XXX_GPT + 0x60)	/* GPT6 */
-static void buzzer_turn_on(unsigned int freq)
-{
-	volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT);
-
-	const u32 prescale = gd->arch.ipb_clk / freq / 128;
-	const u32 count = 128;
-	const u32 width = 64;
-
-	gpt->cir = (prescale << 16) | count;
-	gpt->pwmcr = width << 16;
-	gpt->emsr = 3;		/* Timer enabled for PWM */
-}
-
-static void buzzer_turn_off(void)
-{
-	volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT);
-
-	gpt->emsr = 0;
-}
-
-static int do_inkadiag_buzzer(cmd_tbl_t *cmdtp, int flag, int argc,
-			      char * const argv[]) {
-
-	unsigned int period, freq;
-	int prev, i;
-
-	if (argc != 3)
-		return cmd_usage(cmdtp);
-
-	argc--;
-	argv++;
-
-	period = simple_strtol(argv[0], NULL, 0);
-	if (!period)
-		printf("Zero period is senseless\n");
-	argc--;
-	argv++;
-
-	freq = simple_strtol(argv[0], NULL, 0);
-	/* avoid zero prescale in buzzer_turn_on() */
-	if (freq > gd->arch.ipb_clk / 128) {
-		printf("%dHz exceeds maximum (%ldHz)\n", freq,
-		       gd->arch.ipb_clk / 128);
-	} else if (!freq)
-		printf("Zero frequency is senseless\n");
-	else
-		buzzer_turn_on(freq);
-
-	clear_ctrlc();
-	prev = disable_ctrlc(0);
-
-	printf("Buzzing for %d ms. Type ^C to abort!\n\n", period);
-
-	i = 0;
-	while (!ctrlc() && (i++ < CONFIG_SYS_HZ))
-		udelay(period);
-
-	clear_ctrlc();
-	disable_ctrlc(prev);
-
-	buzzer_turn_off();
-
-	return 0;
-}
-
-static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-cmd_tbl_t cmd_inkadiag_sub[] = {
-	U_BOOT_CMD_MKENT(io, 1, 1, do_inkadiag_io, "read digital input",
-	 "<drawer1|drawer2|other> [value] - get or set specified signal"),
-	U_BOOT_CMD_MKENT(serial, 4, 1, do_inkadiag_serial, "test serial port",
-	 "<num> <mode> <baudrate> <msg>  - test uart num [0..11] in mode\n"
-	 "and baudrate with msg"),
-	U_BOOT_CMD_MKENT(buzzer, 2, 1, do_inkadiag_buzzer, "activate buzzer",
-	 "<period> <freq> - turn buzzer on for period ms with freq hz"),
-	U_BOOT_CMD_MKENT(help, 4, 1, do_inkadiag_help, "get help",
-	 "[command] - get help for command"),
-};
-
-static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag,
-			    int argc, char * const argv[]) {
-	extern int _do_help (cmd_tbl_t *cmd_start, int cmd_items,
-			     cmd_tbl_t *cmdtp, int flag,
-			     int argc, char * const argv[]);
-	/* do_help prints command name - we prepend inkadiag to our subcommands! */
-#ifdef CONFIG_SYS_LONGHELP
-	puts ("inkadiag ");
-#endif
-	return _do_help(&cmd_inkadiag_sub[0],
-		ARRAY_SIZE(cmd_inkadiag_sub), cmdtp, flag, argc, argv);
-}
-
-static int do_inkadiag(cmd_tbl_t *cmdtp, int flag, int argc,
-		       char * const argv[]) {
-	cmd_tbl_t *c;
-
-	c = find_cmd_tbl(argv[1], &cmd_inkadiag_sub[0], ARRAY_SIZE(cmd_inkadiag_sub));
-
-	if (c) {
-		argc--;
-		argv++;
-		return c->cmd(c, flag, argc, argv);
-	} else {
-		/* Unrecognized command */
-		return cmd_usage(cmdtp);
-	}
-}
-
-U_BOOT_CMD(inkadiag, 6, 1, do_inkadiag,
-	   "inkadiag - inka diagnosis\n",
-	   "[inkadiag what ...]\n"
-	   "    - perform a diagnosis on inka hardware\n"
-	   "'inkadiag' performs hardware tests.");
diff --git a/board/inka4x0/k4h511638c.h b/board/inka4x0/k4h511638c.h
deleted file mode 100644
index 054ddaf..0000000
--- a/board/inka4x0/k4h511638c.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2007 Semihalf
- * Written by Marian Balakowicz <m8@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714F0F00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x46770000
-#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/mt46v16m16-75.h b/board/inka4x0/mt46v16m16-75.h
deleted file mode 100644
index 23fc6f0..0000000
--- a/board/inka4x0/mt46v16m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714F0F00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/mt46v32m16-75.h b/board/inka4x0/mt46v32m16-75.h
deleted file mode 100644
index f16f450..0000000
--- a/board/inka4x0/mt46v32m16-75.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2007 Semihalf
- * Written by Marian Balakowicz <m8@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714F0F00
-#define SDRAM_CONFIG1	0x73711930
-#define SDRAM_CONFIG2	0x46770000
-#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h
deleted file mode 100644
index 0133eaa..0000000
--- a/board/inka4x0/mt48lc16m16a2-75.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	0		/* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/intel/Kconfig b/board/intel/Kconfig
index 4d341aa..d7d950e 100644
--- a/board/intel/Kconfig
+++ b/board/intel/Kconfig
@@ -35,6 +35,13 @@ config TARGET_CROWNBAY
 	  Intel Platform Controller Hub EG20T, other system components and
 	  peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
 
+config TARGET_EDISON
+	bool "Edison"
+	help
+	  This is the Intel Edison Compute Module. It contains a dual core Intel
+	  Atom Tangier CPU, 1 GB RAM integrated on package. There is also 4 GB
+	  eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers.
+
 config TARGET_GALILEO
 	bool "Galileo"
 	help
@@ -64,6 +71,7 @@ endchoice
 source "board/intel/bayleybay/Kconfig"
 source "board/intel/cougarcanyon2/Kconfig"
 source "board/intel/crownbay/Kconfig"
+source "board/intel/edison/Kconfig"
 source "board/intel/galileo/Kconfig"
 source "board/intel/minnowmax/Kconfig"
 
diff --git a/board/intel/bayleybay/Kconfig b/board/intel/bayleybay/Kconfig
index 597228f..a622499 100644
--- a/board/intel/bayleybay/Kconfig
+++ b/board/intel/bayleybay/Kconfig
@@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_WINBOND
 
 config PCIE_ECAM_BASE
 	default 0xe0000000
diff --git a/board/intel/cougarcanyon2/Kconfig b/board/intel/cougarcanyon2/Kconfig
index 95a617b..ed76448 100644
--- a/board/intel/cougarcanyon2/Kconfig
+++ b/board/intel/cougarcanyon2/Kconfig
@@ -21,5 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
 	select HAVE_FSP
 	select BOARD_ROMSIZE_KB_2048
+	select BOARD_EARLY_INIT_F
+	select SPI_FLASH_WINBOND
 
 endif
diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig
index b30701a..1eed227 100644
--- a/board/intel/crownbay/Kconfig
+++ b/board/intel/crownbay/Kconfig
@@ -20,5 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR
 	select INTEL_QUEENSBAY
 	select BOARD_ROMSIZE_KB_1024
+	select BOARD_EARLY_INIT_F
+	select SPI_FLASH_SST
 
 endif
diff --git a/board/intel/edison/Kconfig b/board/intel/edison/Kconfig
new file mode 100644
index 0000000..4ff9d5a
--- /dev/null
+++ b/board/intel/edison/Kconfig
@@ -0,0 +1,26 @@
+if TARGET_EDISON
+
+config SYS_BOARD
+	default "edison"
+
+config SYS_VENDOR
+	default "intel"
+
+config SYS_SOC
+	default "tangier"
+
+config SYS_CONFIG_NAME
+	default "edison"
+
+config SYS_TEXT_BASE
+	default 0x01101000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_LOAD_FROM_32_BIT
+	select INTEL_MID
+	select INTEL_TANGIER
+	select BOARD_LATE_INIT
+	select MD5
+
+endif
diff --git a/board/intel/edison/MAINTAINERS b/board/intel/edison/MAINTAINERS
new file mode 100644
index 0000000..4bc4a00
--- /dev/null
+++ b/board/intel/edison/MAINTAINERS
@@ -0,0 +1,6 @@
+Intel Edison Board
+M:	Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+S:	Maintained
+F:	board/intel/edison
+F:	include/configs/edison.h
+F:	configs/edison_defconfig
diff --git a/board/intel/edison/Makefile b/board/intel/edison/Makefile
new file mode 100644
index 0000000..dde1594
--- /dev/null
+++ b/board/intel/edison/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2017 Intel Corporation
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= start.o edison.o
diff --git a/board/intel/edison/config.mk b/board/intel/edison/config.mk
new file mode 100644
index 0000000..465133f
--- /dev/null
+++ b/board/intel/edison/config.mk
@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+# Copyright (c) 2017 Intel Corporation
+#
+# SPDX-License-Identifier:	GPL-2.0	BSD-3-Clause
+#
+
+# Add 4096 bytes of zeroes to u-boot.bin
+quiet_cmd_mkalign_eds = EDSALGN $@
+cmd_mkalign_eds =							\
+	dd if=$^ of=$@ bs=4k seek=1 2>/dev/null &&			\
+	mv $@ $^
+
+ALL-y += u-boot-align.bin
+u-boot-align.bin: u-boot.bin
+	$(call if_changed,mkalign_eds)
+
+HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros
diff --git a/board/intel/edison/edison.c b/board/intel/edison/edison.c
new file mode 100644
index 0000000..a1a7d4d
--- /dev/null
+++ b/board/intel/edison/edison.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <dwc3-uboot.h>
+#include <mmc.h>
+#include <u-boot/md5.h>
+#include <usb.h>
+#include <watchdog.h>
+
+#include <linux/usb/gadget.h>
+
+#include <asm/cache.h>
+#include <asm/scu.h>
+#include <asm/u-boot-x86.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct dwc3_device dwc3_device_data = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = CONFIG_SYS_USB_OTG_BASE,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+};
+
+int usb_gadget_handle_interrupts(int controller_index)
+{
+	dwc3_uboot_handle_interrupt(controller_index);
+	WATCHDOG_RESET();
+	return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	if (index == 0 && init == USB_INIT_DEVICE)
+		return dwc3_uboot_init(&dwc3_device_data);
+	return -EINVAL;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	if (index == 0 && init == USB_INIT_DEVICE) {
+		dwc3_uboot_exit(index);
+		return 0;
+	}
+	return -EINVAL;
+}
+
+static void assign_serial(void)
+{
+	struct mmc *mmc = find_mmc_device(0);
+	unsigned char ssn[16];
+	char usb0addr[18];
+	char serial[33];
+	int i;
+
+	if (!mmc)
+		return;
+
+	md5((unsigned char *)mmc->cid, sizeof(mmc->cid), ssn);
+
+	snprintf(usb0addr, sizeof(usb0addr), "02:00:86:%02x:%02x:%02x",
+		 ssn[13], ssn[14], ssn[15]);
+	setenv("usb0addr", usb0addr);
+
+	for (i = 0; i < 16; i++)
+		snprintf(&serial[2 * i], 3, "%02x", ssn[i]);
+	setenv("serial#", serial);
+
+#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+	saveenv();
+#endif
+}
+
+static void assign_hardware_id(void)
+{
+	struct ipc_ifwi_version v;
+	char hardware_id[4];
+	int ret;
+
+	ret = scu_ipc_command(IPCMSG_GET_FW_REVISION, 1, NULL, 0, (u32 *)&v, 4);
+	if (ret < 0)
+		printf("Can't retrieve hardware revision\n");
+
+	snprintf(hardware_id, sizeof(hardware_id), "%02X", v.hardware_id);
+	setenv("hardware_id", hardware_id);
+
+#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+	saveenv();
+#endif
+}
+
+int board_late_init(void)
+{
+	if (!getenv("serial#"))
+		assign_serial();
+
+	if (!getenv("hardware_id"))
+		assign_hardware_id();
+
+	return 0;
+}
diff --git a/board/intel/edison/start.S b/board/intel/edison/start.S
new file mode 100644
index 0000000..932fe6c
--- /dev/null
+++ b/board/intel/edison/start.S
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* board early intialization */
+.globl early_board_init
+early_board_init:
+	/* No 32-bit board specific initialisation */
+	jmp	early_board_init_ret
diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig
index 87a0ec4..1416c89 100644
--- a/board/intel/galileo/Kconfig
+++ b/board/intel/galileo/Kconfig
@@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR
 	select INTEL_QUARK
 	select BOARD_ROMSIZE_KB_1024
+	select SPI_FLASH_WINBOND
 
 config SMBIOS_PRODUCT_NAME
 	default "GalileoGen2"
diff --git a/board/intel/galileo/galileo.c b/board/intel/galileo/galileo.c
index 568bd4d..2fe1923 100644
--- a/board/intel/galileo/galileo.c
+++ b/board/intel/galileo/galileo.c
@@ -9,11 +9,6 @@
 #include <asm/arch/device.h>
 #include <asm/arch/quark.h>
 
-int board_early_init_f(void)
-{
-	return 0;
-}
-
 /*
  * Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin.
  *
diff --git a/board/intel/minnowmax/Kconfig b/board/intel/minnowmax/Kconfig
index 7e975f9..a8668e4 100644
--- a/board/intel/minnowmax/Kconfig
+++ b/board/intel/minnowmax/Kconfig
@@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select X86_RESET_VECTOR if !EFI_STUB
 	select INTEL_BAYTRAIL
 	select BOARD_ROMSIZE_KB_8192
+	select SPI_FLASH_STMICRO
 
 config PCIE_ECAM_BASE
 	default 0xe0000000
diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c
index 94b22ed..5bdb2fd 100644
--- a/board/intel/minnowmax/minnowmax.c
+++ b/board/intel/minnowmax/minnowmax.c
@@ -5,9 +5,57 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <asm/gpio.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
 
-int arch_early_init_r(void)
+#define GPIO_BANKE_NAME		"gpioe"
+
+int misc_init_r(void)
 {
+	struct udevice *dev;
+	struct gpio_desc desc;
+	int ret;
+
+	/*
+	 * Turn on USB VBUS for the two USB ports on the board.
+	 * Each port's VBUS is controlled by a GPIO pin.
+	 */
+
+	ret = uclass_find_device_by_name(UCLASS_GPIO, GPIO_BANKE_NAME, &dev);
+	if (ret) {
+		debug("%s: GPIO %s device cannot be not found (ret=%d)\n",
+		      __func__, GPIO_BANKE_NAME, ret);
+		return ret;
+	}
+
+	ret = device_probe(dev);
+	if (ret) {
+		debug("%s: GPIO %s device probe failed (ret=%d)\n",
+		      __func__, GPIO_BANKE_NAME, ret);
+		return ret;
+	}
+
+	desc.dev = dev;
+	desc.flags = GPIOD_IS_OUT;
+
+	/* GPIO E8 controls the bottom port */
+	desc.offset = 8;
+
+	ret = dm_gpio_request(&desc, "usb_host_en0");
+	if (ret)
+		return ret;
+	dm_gpio_set_value(&desc, 1);
+
+	/* GPIO E9 controls the upper port */
+	desc.offset = 9;
+
+	ret = dm_gpio_request(&desc, "usb_host_en1");
+	if (ret)
+		return ret;
+
+	dm_gpio_set_value(&desc, 1);
+
 	return 0;
 }
diff --git a/board/intercontrol/digsy_mtc/Kconfig b/board/intercontrol/digsy_mtc/Kconfig
deleted file mode 100644
index 1cf2275..0000000
--- a/board/intercontrol/digsy_mtc/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_DIGSY_MTC
-
-config SYS_BOARD
-	default "digsy_mtc"
-
-config SYS_VENDOR
-	default "intercontrol"
-
-config SYS_CONFIG_NAME
-	default "digsy_mtc"
-
-endif
diff --git a/board/intercontrol/digsy_mtc/MAINTAINERS b/board/intercontrol/digsy_mtc/MAINTAINERS
deleted file mode 100644
index c83ebcd..0000000
--- a/board/intercontrol/digsy_mtc/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-DIGSY_MTC BOARD
-M:	Werner Pfister <Pfister_Werner@intercontrol.de>
-S:	Maintained
-F:	board/intercontrol/digsy_mtc/
-F:	include/configs/digsy_mtc.h
-F:	configs/digsy_mtc_defconfig
-F:	configs/digsy_mtc_RAMBOOT_defconfig
-F:	configs/digsy_mtc_rev5_defconfig
-F:	configs/digsy_mtc_rev5_RAMBOOT_defconfig
diff --git a/board/intercontrol/digsy_mtc/Makefile b/board/intercontrol/digsy_mtc/Makefile
deleted file mode 100644
index fd0c2f9..0000000
--- a/board/intercontrol/digsy_mtc/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Author: Grzegorz Bernacki, Semihalf, gjb@semihalf.com
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= digsy_mtc.o cmd_mtc.o
-obj-$(CONFIG_VIDEO) += cmd_disp.o
diff --git a/board/intercontrol/digsy_mtc/cmd_disp.c b/board/intercontrol/digsy_mtc/cmd_disp.c
deleted file mode 100644
index 2ffa8bf..0000000
--- a/board/intercontrol/digsy_mtc/cmd_disp.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2011 DENX Software Engineering,
- * Anatolij Gustschin <agust@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <mpc5xxx.h>
-#include <asm/io.h>
-
-#define GPIO_USB1_0	0x00010000
-
-static int cmd_disp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
-	if (argc < 2) {
-		printf("%s\n",
-		       in_be32(&gpio->simple_dvo) & GPIO_USB1_0 ? "on" : "off");
-		return 0;
-	}
-
-	if (!strncmp(argv[1], "on", 2)) {
-		setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
-	} else if (!strncmp(argv[1], "off", 3)) {
-		clrbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
-	} else {
-		cmd_usage(cmdtp);
-		return 1;
-	}
-	return 0;
-}
-
-U_BOOT_CMD(disp, 2, 1, cmd_disp,
-		"disp [on/off] - switch display on/off",
-		"\n    - print display on/off status\n"
-		"on\n    - turn on\n"
-		"off\n    - turn off\n"
-);
diff --git a/board/intercontrol/digsy_mtc/cmd_mtc.c b/board/intercontrol/digsy_mtc/cmd_mtc.c
deleted file mode 100644
index f17ec55..0000000
--- a/board/intercontrol/digsy_mtc/cmd_mtc.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- * (C) Copyright 2009
- * Werner Pfister <Pfister_Werner@intercontrol.de>
- *
- * (C) Copyright 2009 Semihalf, Grzegorz Bernacki
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <mpc5xxx.h>
-#include "spi.h"
-#include "cmd_mtc.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static uchar user_out;
-
-static const char *led_names[] = {
-	"diag",
-	"can1",
-	"can2",
-	"can3",
-	"can4",
-	"usbpwr",
-	"usbbusy",
-	"user1",
-	"user2",
-	""
-};
-
-static int msp430_xfer(const void *dout, void *din)
-{
-	int err;
-
-	err = spi_xfer(NULL, MTC_TRANSFER_SIZE, dout, din,
-		       SPI_XFER_BEGIN | SPI_XFER_END);
-
-	/* The MSP chip needs time to ready itself for the next command */
-	udelay(1000);
-
-	return err;
-}
-
-static void mtc_calculate_checksum(tx_msp_cmd *packet)
-{
-	int i;
-	uchar *buff;
-
-	buff = (uchar *) packet;
-
-	for (i = 0; i < 6; i++)
-		packet->cks += buff[i];
-}
-
-static int do_mtc_led(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	tx_msp_cmd pcmd;
-	rx_msp_cmd prx;
-	int err;
-	int i;
-
-	if (argc < 2)
-		return cmd_usage(cmdtp);
-
-	memset(&pcmd, 0, sizeof(pcmd));
-	memset(&prx, 0, sizeof(prx));
-
-	pcmd.cmd = CMD_SET_LED;
-
-	pcmd.cmd_val0 = 0xff;
-	for (i = 0; strlen(led_names[i]) != 0; i++) {
-		if (strncmp(argv[1], led_names[i], strlen(led_names[i])) == 0) {
-			pcmd.cmd_val0 = i;
-			break;
-		}
-	}
-
-	if (pcmd.cmd_val0 == 0xff) {
-		printf("Usage:\n%s\n", cmdtp->help);
-		return -1;
-	}
-
-	if (argc >= 3) {
-		if (strncmp(argv[2], "red", 3) == 0)
-			pcmd.cmd_val1 = 1;
-		else if (strncmp(argv[2], "green", 5) == 0)
-			pcmd.cmd_val1 = 2;
-		else if (strncmp(argv[2], "orange", 6) == 0)
-			pcmd.cmd_val1 = 3;
-		else
-			pcmd.cmd_val1 = 0;
-	}
-
-	if (argc >= 4)
-		pcmd.cmd_val2 = simple_strtol(argv[3], NULL, 10);
-	else
-		pcmd.cmd_val2 = 0;
-
-	pcmd.user_out = user_out;
-
-	mtc_calculate_checksum(&pcmd);
-	err = msp430_xfer(&pcmd, &prx);
-
-	return err;
-}
-
-static int do_mtc_key(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	tx_msp_cmd pcmd;
-	rx_msp_cmd prx;
-	int err;
-
-	memset(&pcmd, 0, sizeof(pcmd));
-	memset(&prx, 0, sizeof(prx));
-
-	pcmd.cmd = CMD_GET_VIM;
-	pcmd.user_out = user_out;
-
-	mtc_calculate_checksum(&pcmd);
-	err = msp430_xfer(&pcmd, &prx);
-
-	if (!err) {
-		/* function returns '0' if key is pressed */
-		err = (prx.input & 0x80) ? 0 : 1;
-	}
-
-	return err;
-}
-
-static int do_mtc_digout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	tx_msp_cmd pcmd;
-	rx_msp_cmd prx;
-	int err;
-	uchar channel_mask = 0;
-
-	if (argc < 3)
-		return cmd_usage(cmdtp);
-
-	if (strncmp(argv[1], "on", 2) == 0)
-		channel_mask |= 1;
-	if (strncmp(argv[2], "on", 2) == 0)
-		channel_mask |= 2;
-
-	memset(&pcmd, 0, sizeof(pcmd));
-	memset(&prx, 0, sizeof(prx));
-
-	pcmd.cmd = CMD_GET_VIM;
-	pcmd.user_out = channel_mask;
-	user_out = channel_mask;
-
-	mtc_calculate_checksum(&pcmd);
-	err = msp430_xfer(&pcmd, &prx);
-
-	return err;
-}
-
-static int do_mtc_digin(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	tx_msp_cmd pcmd;
-	rx_msp_cmd prx;
-	int err;
-	uchar channel_num = 0;
-
-	if (argc < 2)
-		return cmd_usage(cmdtp);
-
-	channel_num = simple_strtol(argv[1], NULL, 10);
-	if ((channel_num != 1) && (channel_num != 2)) {
-		printf("mtc digin: invalid parameter - must be '1' or '2'\n");
-		return -1;
-	}
-
-	memset(&pcmd, 0, sizeof(pcmd));
-	memset(&prx, 0, sizeof(prx));
-
-	pcmd.cmd = CMD_GET_VIM;
-	pcmd.user_out = user_out;
-
-	mtc_calculate_checksum(&pcmd);
-	err = msp430_xfer(&pcmd, &prx);
-
-	if (!err) {
-		/* function returns '0' when digin is on */
-		err = (prx.input & channel_num) ? 0 : 1;
-	}
-
-	return err;
-}
-
-static int do_mtc_appreg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	tx_msp_cmd pcmd;
-	rx_msp_cmd prx;
-	int err;
-	char buf[5];
-	uchar appreg;
-
-	/* read appreg */
-	memset(&pcmd, 0, sizeof(pcmd));
-	memset(&prx, 0, sizeof(prx));
-
-	pcmd.cmd = CMD_WD_PARA;
-	pcmd.cmd_val0 = 5;	/* max. Count */
-	pcmd.cmd_val1 = 5;	/* max. Time */
-	pcmd.cmd_val2 = 0;	/* =0 means read appreg */
-	pcmd.user_out = user_out;
-
-	mtc_calculate_checksum(&pcmd);
-	err = msp430_xfer(&pcmd, &prx);
-
-	/* on success decide between read or write */
-	if (!err) {
-		if (argc == 2) {
-			appreg = simple_strtol(argv[1], NULL, 10);
-			if (appreg == 0) {
-				printf("mtc appreg: invalid parameter - "
-				       "must be between 1 and 255\n");
-				return -1;
-			}
-			memset(&pcmd, 0, sizeof(pcmd));
-			pcmd.cmd = CMD_WD_PARA;
-			pcmd.cmd_val0 = prx.ack3; /* max. Count */
-			pcmd.cmd_val1 = prx.ack0; /* max. Time */
-			pcmd.cmd_val2 = appreg;	  /* !=0 means write appreg */
-			pcmd.user_out = user_out;
-			memset(&prx, 0, sizeof(prx));
-
-			mtc_calculate_checksum(&pcmd);
-			err = msp430_xfer(&pcmd, &prx);
-		} else {
-			sprintf(buf, "%d", prx.ack2);
-			setenv("appreg", buf);
-		}
-	}
-
-	return err;
-}
-
-static int do_mtc_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	tx_msp_cmd pcmd;
-	rx_msp_cmd prx;
-	int err;
-
-	memset(&pcmd, 0, sizeof(pcmd));
-	memset(&prx, 0, sizeof(prx));
-
-	pcmd.cmd = CMD_FW_VERSION;
-	pcmd.user_out = user_out;
-
-	mtc_calculate_checksum(&pcmd);
-	err = msp430_xfer(&pcmd, &prx);
-
-	if (!err) {
-		printf("FW V%d.%d.%d / HW %d\n",
-		       prx.ack0, prx.ack1, prx.ack3, prx.ack2);
-	}
-
-	return err;
-}
-
-static int do_mtc_state(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	tx_msp_cmd pcmd;
-	rx_msp_cmd prx;
-	int err;
-
-	memset(&pcmd, 0, sizeof(pcmd));
-	memset(&prx, 0, sizeof(prx));
-
-	pcmd.cmd = CMD_WD_WDSTATE;
-	pcmd.cmd_val2 = 1;
-	pcmd.user_out = user_out;
-
-	mtc_calculate_checksum(&pcmd);
-	err = msp430_xfer(&pcmd, &prx);
-
-	if (!err) {
-		printf("State     %02Xh\n", prx.state);
-		printf("Input     %02Xh\n", prx.input);
-		printf("UserWD    %02Xh\n", prx.ack2);
-		printf("Sys WD    %02Xh\n", prx.ack3);
-		printf("WD Timout %02Xh\n", prx.ack0);
-		printf("eSysState %02Xh\n", prx.ack1);
-	}
-
-	return err;
-}
-
-static int do_mtc_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-cmd_tbl_t cmd_mtc_sub[] = {
-	U_BOOT_CMD_MKENT(led, 3, 1, do_mtc_led,
-	"set state of leds",
-	"[ledname] [state] [blink]\n"
-	" - lednames: diag can1 can2 can3 can4 usbpwr usbbusy user1 user2\n"
-	" - state: off red green orange\n"
-	" - blink: blink interval in 100ms steps (1 - 10; 0 = static)\n"),
-	U_BOOT_CMD_MKENT(key, 0, 1, do_mtc_key,
-	"returns state of user key", ""),
-	U_BOOT_CMD_MKENT(version, 0, 1, do_mtc_version,
-	"returns firmware version of supervisor uC", ""),
-	U_BOOT_CMD_MKENT(appreg, 1, 1, do_mtc_appreg,
-	"reads or writes appreg value and stores in environment "
-	"variable 'appreg'",
-	"[value] - value (1 - 255) to write to appreg"),
-	U_BOOT_CMD_MKENT(digin, 1, 1, do_mtc_digin,
-	"returns state of digital input",
-	"<channel_num> - get state of digital input (1 or 2)\n"),
-	U_BOOT_CMD_MKENT(digout, 2, 1, do_mtc_digout,
-	"sets digital outputs",
-	"<on|off> <on|off>- set state of digital output 1 and 2\n"),
-	U_BOOT_CMD_MKENT(state, 0, 1, do_mtc_state,
-	"displays state", ""),
-	U_BOOT_CMD_MKENT(help, 4, 1, do_mtc_help, "get help",
-	"[command] - get help for command\n"),
-};
-
-static int do_mtc_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	extern int _do_help(cmd_tbl_t *cmd_start, int cmd_items,
-			    cmd_tbl_t *cmdtp, int flag,
-			    int argc, char * const argv[]);
-#ifdef CONFIG_SYS_LONGHELP
-	puts("mtc ");
-#endif
-	return _do_help(&cmd_mtc_sub[0],
-			ARRAY_SIZE(cmd_mtc_sub), cmdtp, flag, argc, argv);
-}
-
-int cmd_mtc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	cmd_tbl_t *c;
-	int err = 0;
-
-	c = find_cmd_tbl(argv[1], &cmd_mtc_sub[0], ARRAY_SIZE(cmd_mtc_sub));
-	if (c) {
-		argc--;
-		argv++;
-		return c->cmd(c, flag, argc, argv);
-	} else {
-		/* Unrecognized command */
-		return cmd_usage(cmdtp);
-	}
-
-	return err;
-}
-
-U_BOOT_CMD(mtc, 5, 1, cmd_mtc,
-	"special commands for digsyMTC",
-	"[subcommand] [args...]\n"
-	"Subcommands list:\n"
-	"led [ledname] [state] [blink] - set state of leds\n"
-	"  [ledname]: diag can1 can2 can3 can4 usbpwr usbbusy user1 user2\n"
-	"  [state]: off red green orange\n"
-	"  [blink]: blink interval in 100ms steps (1 - 10; 0 = static)\n"
-	"key - returns state of user key\n"
-	"version - returns firmware version of supervisor uC\n"
-	"appreg [value] - reads (in environment variable 'appreg') or writes"
-	" appreg value\n"
-	"  [value]: value (1 - 255) to write to appreg\n"
-	"digin [channel] - returns state of digital input (1 or 2)\n"
-	"digout <on|off> <on|off> - sets state of two digital outputs\n"
-	"state - displays state\n"
-	"help [subcommand] - get help for subcommand\n"
-);
diff --git a/board/intercontrol/digsy_mtc/cmd_mtc.h b/board/intercontrol/digsy_mtc/cmd_mtc.h
deleted file mode 100644
index 4493433..0000000
--- a/board/intercontrol/digsy_mtc/cmd_mtc.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * (C) Copyright 2009
- * Werner Pfister <Pfister_Werner@intercontrol.de>
- *
- * (C) Copyright 2009 Semihalf, Grzegorz Bernacki
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef CMD_MTC_H
-#define CMD_MTC_H
-
-#define	CMD_WD_PARA		0x02
-#define	CMD_WD_WDSTATE		0x04
-#define	CMD_FW_VERSION		0x10
-#define	CMD_GET_VIM		0x30
-#define	CMD_SET_LED		0x40
-
-typedef struct {
-	u8 cmd;
-	u8 sys_in;
-	u8 cmd_val0;
-	u8 cmd_val1;
-	u8 cmd_val2;
-	u8 user_out;
-	u8 cks;
-	u8 dummy1;
-	u8 dummy2;
-} tx_msp_cmd;
-
-typedef struct {
-	u8 input;
-	u8 state;
-	u8 ack2;
-	u8 ack3;
-	u8 ack0;
-	u8 ack1;
-	u8 ack;
-	u8 dummy;
-	u8 cks;
-} rx_msp_cmd;
-
-#define MTC_TRANSFER_SIZE (sizeof(tx_msp_cmd) * 8)
-
-#endif
diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c
deleted file mode 100644
index 2e52d51..0000000
--- a/board/intercontrol/digsy_mtc/digsy_mtc.c
+++ /dev/null
@@ -1,484 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2005-2009
- * Modified for InterControl digsyMTC MPC5200 board by
- * Frank Bodammer, GCD Hard- & Software GmbH,
- *                 frank.bodammer@gcd-solutions.de
- *
- * (C) Copyright 2009
- * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include "eeprom.h"
-#if defined(CONFIG_DIGSY_REV5)
-#include "is45s16800a2.h"
-#include <mtd/cfi_flash.h>
-#include <flash.h>
-#else
-#include "is42s16800a-7t.h"
-#endif
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <mb862xx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern int usb_cpu_init(void);
-
-#if defined(CONFIG_DIGSY_REV5)
-/*
- * The M29W128GH needs a specail reset command function,
- * details see the doc/README.cfi file
- */
-void flash_cmd_reset(flash_info_t *info)
-{
-	flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
-}
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start(int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-	long control = SDRAM_CONTROL | hi_addr_bit;
-
-	/* unlock mode register */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
-
-	/* precharge all banks */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
-
-	/* auto refresh */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
-
-	/* set mode register */
-	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
- *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
- */
-
-phys_size_t initdram(int board_type)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
-	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
-
-	/* setup config registers */
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
-	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
-			(0x13 + __builtin_ffs(dramsize >> 20) - 1));
-	} else {
-		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 */
-	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
-
-	/* find RAM size using SDRAM CS1 only */
-	test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
-			0x08000000);
-		dramsize2 = test1;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20))
-		dramsize2 = 0;
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0) {
-		out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
-			(0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
-	} else {
-		out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
-	if (dramsize2 >= 0x13)
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	else
-		dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
-		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
-
-	return dramsize + dramsize2;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	puts ("Board: InterControl digsyMTC");
-#if defined(CONFIG_DIGSY_REV5)
-	puts (" rev5");
-#endif
-	if (i > 0) {
-		puts(", ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-#if defined(CONFIG_VIDEO)
-
-#define GPIO_USB1_0		0x00010000	/* Power-On pin */
-#define GPIO_USB1_9		0x08		/* PX_~EN pin */
-
-#define GPIO_EE_DO		0x10		/* PSC6_0 (DO) pin */
-#define GPIO_EE_CTS		0x20		/* PSC6_1 (CTS) pin */
-#define GPIO_EE_DI		0x10000000	/* PSC6_2 (DI) pin */
-#define GPIO_EE_CLK		0x20000000	/* PSC6_3 (CLK) pin */
-
-#define GPT_GPIO_ON		0x00000034	/* GPT as simple GPIO, high */
-
-static void exbo_hw_init(void)
-{
-	struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_wu_gpio *wu_gpio =
-				(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-
-	/* configure IrDA pins (PSC6 port) as gpios */
-	gpio->port_config &= 0xFF8FFFFF;
-
-	/* Init for USB1_0, EE_CLK and EE_DI - Low */
-	setbits_be32(&gpio->simple_ddr,
-			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
-	clrbits_be32(&gpio->simple_ode,
-			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
-	clrbits_be32(&gpio->simple_dvo,
-			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
-	setbits_be32(&gpio->simple_gpioe,
-			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
-
-	/* Init for EE_DO, EE_CTS - Input */
-	clrbits_8(&wu_gpio->ddr, GPIO_EE_DO | GPIO_EE_CTS);
-	setbits_8(&wu_gpio->enable, GPIO_EE_DO | GPIO_EE_CTS);
-
-	/* Init for PX_~EN (USB1_9) - High */
-	clrbits_8(&gpio->sint_ode, GPIO_USB1_9);
-	setbits_8(&gpio->sint_ddr, GPIO_USB1_9);
-	clrbits_8(&gpio->sint_inten, GPIO_USB1_9);
-	setbits_8(&gpio->sint_dvo, GPIO_USB1_9);
-	setbits_8(&gpio->sint_gpioe, GPIO_USB1_9);
-
-	/* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */
-	out_be32(&gpt[0].emsr, GPT_GPIO_ON);
-	/* Init for S Switch (GPIO4) - Timer_1 GPIO High */
-	out_be32(&gpt[1].emsr, GPT_GPIO_ON);
-
-	/* Power-On camera supply */
-	setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
-}
-#else
-static inline void exbo_hw_init(void) {}
-#endif /* CONFIG_VIDEO */
-
-int board_early_init_r(void)
-{
-#ifdef CONFIG_MPC52XX_SPI
-	struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt*)MPC5XXX_GPT;
-#endif
-	/*
-	 * Now, when we are in RAM, enable flash write access for detection
-	 * process.  Note that CS_BOOT cannot be cleared when executing in
-	 * flash.
-	 */
-	/* disable CS_BOOT */
-	clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
-	/* enable CS1 */
-	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
-	/* enable CS0 */
-	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-	/* Low level USB init, required for proper kernel operation */
-	usb_cpu_init();
-#endif
-#ifdef CONFIG_MPC52XX_SPI
-	/* GPT 6 Output Enable */
-	out_be32(&gpt[6].emsr, 0x00000034);
-	/* GPT 7 Output Enable */
-	out_be32(&gpt[7].emsr, 0x00000034);
-#endif
-
-	return (0);
-}
-
-void board_get_enetaddr (uchar * enet)
-{
-	ushort read = 0;
-	ushort addr_of_eth_addr = 0;
-	ushort len_sys = 0;
-	ushort len_sys_cfg = 0;
-
-	/* check identification word */
-	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
-	if (read != EEPROM_IDENT)
-		return;
-
-	/* calculate offset of config area */
-	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
-	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
-		(uchar *)&len_sys_cfg, 2);
-	addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
-	if (addr_of_eth_addr >= EEPROM_LEN)
-		return;
-
-	eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
-}
-
-int misc_init_r(void)
-{
-	pci_dev_t devbusfn;
-	uchar enetaddr[6];
-
-	/* check if graphic extension board is present */
-	devbusfn = pci_find_device(PCI_VENDOR_ID_FUJITSU,
-				   PCI_DEVICE_ID_CORAL_PA, 0);
-	if (devbusfn != -1)
-		exbo_hw_init();
-
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
-		board_get_enetaddr(enetaddr);
-		eth_setenv_enetaddr("ethaddr", enetaddr);
-	}
-
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#ifdef CONFIG_CMD_IDE
-
-#ifdef CONFIG_IDE_RESET
-
-void init_ide_reset(void)
-{
-	debug ("init_ide_reset\n");
-
-	/* set gpio output value to 1 */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
-	/* open drain output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
-	/* direction output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
-	/* enable gpio */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
-
-}
-
-void ide_set_reset(int idereset)
-{
-	debug ("ide_reset(%d)\n", idereset);
-
-	/* set gpio output value to 0 */
-	clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
-	/* open drain output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
-	/* direction output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
-	/* enable gpio */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
-
-	udelay(10000);
-
-	/* set gpio output value to 1 */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
-	/* open drain output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
-	/* direction output */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
-	/* enable gpio */
-	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
-}
-#endif /* CONFIG_IDE_RESET */
-#endif /* CONFIG_CMD_IDE */
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static void ft_delete_node(void *fdt, const char *compat)
-{
-	int off = -1;
-	int ret;
-
-	off = fdt_node_offset_by_compatible(fdt, -1, compat);
-	if (off < 0) {
-		printf("Could not find %s node.\n", compat);
-		return;
-	}
-
-	ret = fdt_del_node(fdt, off);
-	if (ret < 0)
-		printf("Could not delete %s node.\n", compat);
-}
-#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
-static void ft_adapt_flash_base(void *blob)
-{
-	flash_info_t	*dev = &flash_info[0];
-	int off;
-	struct fdt_property *prop;
-	int len;
-	u32 *reg, *reg2;
-
-	off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
-	if (off < 0) {
-		printf("Could not find fsl,mpc5200b-lpb node.\n");
-		return;
-	}
-
-	/* found compatible property */
-	prop = fdt_get_property_w(blob, off, "ranges", &len);
-	if (prop) {
-		reg = reg2 = (u32 *)&prop->data[0];
-
-		reg[2] = dev->start[0];
-		reg[3] = dev->size;
-		fdt_setprop(blob, off, "ranges", reg2, len);
-	} else
-		printf("Could not find ranges\n");
-}
-
-extern ulong flash_get_size (phys_addr_t base, int banknum);
-
-/* Update the Flash Baseaddr settings */
-int update_flash_size (int flash_size)
-{
-	volatile struct mpc5xxx_mmap_ctl *mm =
-		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
-	flash_info_t	*dev;
-	int	i;
-	int size = 0;
-	unsigned long base = 0x0;
-	u32 *cs_reg = (u32 *)&mm->cs0_start;
-
-	for (i = 0; i < 2; i++) {
-		dev = &flash_info[i];
-
-		if (dev->size) {
-			/* calculate new base addr for this chipselect */
-			base -= dev->size;
-			out_be32(cs_reg, START_REG(base));
-			cs_reg++;
-			out_be32(cs_reg, STOP_REG(base, dev->size));
-			cs_reg++;
-			/* recalculate the sectoraddr in the cfi driver */
-			size += flash_get_size(base, i);
-		}
-	}
-	flash_protect_default();
-	gd->bd->bi_flashstart = base;
-	return 0;
-}
-#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	int phy_addr = CONFIG_PHY_ADDR;
-	char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
-
-	ft_cpu_setup(blob, bd);
-	/*
-	 * There are 2 RTC nodes in the DTS, so remove
-	 * the unneeded node here.
-	 */
-#if defined(CONFIG_DIGSY_REV5)
-	ft_delete_node(blob, "dallas,ds1339");
-#else
-	ft_delete_node(blob, "mc,rv3029c2");
-#endif
-#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
-#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
-	/* Update reg property in all nor flash nodes too */
-	fdt_fixup_nor_flash_size(blob);
-#endif
-	ft_adapt_flash_base(blob);
-#endif
-	/* fix up the phy address */
-	do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/intercontrol/digsy_mtc/eeprom.h b/board/intercontrol/digsy_mtc/eeprom.h
deleted file mode 100644
index 17bd034..0000000
--- a/board/intercontrol/digsy_mtc/eeprom.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * (C) Copyright 2009 Semihalf.
- * Written by: Grzegorz Bernacki <gjb@semihalf.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef CMD_EEPROM_H
-#define CMD_EEPROM_H
-
-#define EEPROM_ADDR		CONFIG_SYS_I2C_EEPROM_ADDR
-#define EEPROM_LEN		1024	/* eeprom length */
-#define EEPROM_IDENT		2408	/* identification word */
-#define EEPROM_ADDR_IDENT	0	/* identification word offset */
-#define EEPROM_ADDR_LEN_SYS	2	/* system area lenght offset */
-#define EEPROM_ADDR_LEN_SYSCFG	4	/* system config area length offset */
-#define EEPROM_ADDR_ETHADDR	23	/* ethernet address offset */
-
-#endif
diff --git a/board/intercontrol/digsy_mtc/is42s16800a-7t.h b/board/intercontrol/digsy_mtc/is42s16800a-7t.h
deleted file mode 100644
index c555d2d..0000000
--- a/board/intercontrol/digsy_mtc/is42s16800a-7t.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * (C) Copyright 2004-2009
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x505F0000
-#define SDRAM_CONFIG1	0xD2322900
-#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/intercontrol/digsy_mtc/is45s16800a2.h b/board/intercontrol/digsy_mtc/is45s16800a2.h
deleted file mode 100644
index c42ba38..0000000
--- a/board/intercontrol/digsy_mtc/is45s16800a2.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2010
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * based on:
- * (C) Copyright 2004-2009
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x50470000
-#define SDRAM_CONFIG1	0xD2322900
-#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/inversepath/usbarmory/usbarmory.c b/board/inversepath/usbarmory/usbarmory.c
index c875e78..2f6bc3a 100644
--- a/board/inversepath/usbarmory/usbarmory.c
+++ b/board/inversepath/usbarmory/usbarmory.c
@@ -15,7 +15,7 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/iomux-mx53.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
diff --git a/board/ip04/Kconfig b/board/ip04/Kconfig
deleted file mode 100644
index 670bf89..0000000
--- a/board/ip04/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_IP04
-
-config SYS_BOARD
-	default "ip04"
-
-config SYS_CONFIG_NAME
-	default "ip04"
-
-endif
diff --git a/board/ip04/MAINTAINERS b/board/ip04/MAINTAINERS
deleted file mode 100644
index c37b011..0000000
--- a/board/ip04/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-IP04 BOARD
-#M:	Brent Kandetzki <brentk@teleco.com>
-S:	Orphan (since 2014-06)
-F:	board/ip04/
-F:	include/configs/ip04.h
-F:	configs/ip04_defconfig
diff --git a/board/ip04/Makefile b/board/ip04/Makefile
deleted file mode 100644
index 44fa684..0000000
--- a/board/ip04/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2010 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= ip04.o
diff --git a/board/ip04/config.mk b/board/ip04/config.mk
deleted file mode 100644
index ab0fbec..0000000
--- a/board/ip04/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
-LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
diff --git a/board/ip04/ip04.c b/board/ip04/ip04.c
deleted file mode 100644
index c7bc334..0000000
--- a/board/ip04/ip04.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2007 David Rowe,
- *           (c) 2006 Ivan Danov
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-
-int checkboard(void)
-{
-	printf("Board: IP04 IP-PBX\n");
-	printf("       http://www.rowetel.com/ucasterisk/ip04.html\n");
-	return 0;
-}
-
-#ifdef CONFIG_DRIVER_DM9000
-int board_eth_init(bd_t *bis)
-{
-	return dm9000_initialize(bis);
-}
-#endif
diff --git a/board/ipek01/Kconfig b/board/ipek01/Kconfig
deleted file mode 100644
index 34e094d..0000000
--- a/board/ipek01/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_IPEK01
-
-config SYS_BOARD
-	default "ipek01"
-
-config SYS_CONFIG_NAME
-	default "ipek01"
-
-endif
diff --git a/board/ipek01/MAINTAINERS b/board/ipek01/MAINTAINERS
deleted file mode 100644
index 906d39e..0000000
--- a/board/ipek01/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-IPEK01 BOARD
-M:	Anatolij Gustschin <agust@denx.de>
-S:	Maintained
-F:	board/ipek01/
-F:	include/configs/ipek01.h
-F:	configs/ipek01_defconfig
diff --git a/board/ipek01/Makefile b/board/ipek01/Makefile
deleted file mode 100644
index a786ab2..0000000
--- a/board/ipek01/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= ipek01.o
diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c
deleted file mode 100644
index 2e62355..0000000
--- a/board/ipek01/ipek01.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2006
- * MicroSys GmbH
- *
- * (C) Copyright 2009
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <netdev.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <mb862xx.h>
-#include <video_fb.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_OF_LIBFDT
-#include <fdt_support.h>
-#endif /* CONFIG_OF_LIBFDT */
-
-/* mt46v16m16-75 */
-#ifdef CONFIG_MPC5200_DDR
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714f0f00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-#define SDRAM_TAPDELAY	0x10000000
-#else
-#error SDRAM is not supported on this board
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void sdram_start (int hi_addr)
-{
-	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
-
-	/* precharge all banks */
-	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
-
-	/* set mode register: extended mode */
-	out_be32 (&sdram->mode, SDRAM_EMODE);
-
-	/* set mode register: reset DLL */
-	out_be32 (&sdram->mode, SDRAM_MODE | 0x04000000);
-
-	/* precharge all banks */
-	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
-
-	/* auto refresh */
-	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
-
-	/* set mode register */
-	out_be32 (&sdram->mode, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32 (&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
-}
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real
- *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if
- *	      CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
-	struct mpc5xxx_mmap_ctl *mmap_ctl =
-		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
-	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	struct mpc5xxx_cdm *cdm = (struct mpc5xxx_cdm *)MPC5XXX_CDM;
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	out_be32 (&mmap_ctl->sdram0, 0x0000001e);	/* 2G at 0x0 */
-	out_be32 (&mmap_ctl->sdram1, 0x00000000);	/* disabled */
-
-	/* setup config registers */
-	out_be32 (&sdram->config1, SDRAM_CONFIG1);
-	out_be32 (&sdram->config2, SDRAM_CONFIG2);
-
-	/* set tap delay */
-	out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start (0);
-	test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start (1);
-	test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start (0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0)
-		out_be32 (&mmap_ctl->sdram0,
-			  0x13 + __builtin_ffs (dramsize >> 20) - 1);
-	else
-		out_be32 (&mmap_ctl->sdram1, 0);	/* disabled */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	out_be32 (&sdram->sdelay, 0x04);
-
-	return dramsize + dramsize2;
-}
-
-int checkboard (void)
-{
-	puts ("Board: IPEK01 \n");
-	return 0;
-}
-
-void flash_preinit (void)
-{
-	struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
-
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	clrbits_be32 (&lpb->cs0_cfg, 0x1);	/* clear RO */
-}
-
-void flash_afterinit (ulong start, ulong size)
-{
-	struct mpc5xxx_mmap_ctl *mmap_ctl =
-		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
-
-#if defined(CONFIG_BOOT_ROM)
-	/* adjust mapping */
-	out_be32 (&mmap_ctl->cs1_start, START_REG (start));
-	out_be32 (&mmap_ctl->cs1_stop, STOP_REG (start, size));
-#else
-	/* adjust mapping */
-	out_be32 (&mmap_ctl->boot_start, START_REG (start));
-	out_be32 (&mmap_ctl->cs0_start, START_REG (start));
-	out_be32 (&mmap_ctl->boot_stop, STOP_REG (start, size));
-	out_be32 (&mmap_ctl->cs0_stop, STOP_REG (start, size));
-#endif
-}
-
-extern flash_info_t flash_info[];	/* info for FLASH chips */
-
-int misc_init_r (void)
-{
-	/* adjust flash start */
-	gd->bd->bi_flashstart = flash_info[0].start[0];
-	return (0);
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init (struct pci_controller *);
-
-void pci_init_board (void)
-{
-	pci_mpc5xxx_init (&hose);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup (blob, bd);
-	fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-int board_eth_init(bd_t *bis)
-{
-	cpu_eth_init(bis); /* Built in FEC comes first */
-	return pci_eth_init(bis);
-}
-
-#ifdef CONFIG_VIDEO
-extern GraphicDevice mb862xx;
-
-static const gdc_regs init_regs[] = {
-	{0x0100, 0x00000900},
-	{0x0020, 0x80190257},
-	{0x0024, 0x00000000},
-	{0x0028, 0x00000000},
-	{0x002c, 0x00000000},
-	{0x0110, 0x00000000},
-	{0x0114, 0x00000000},
-	{0x0118, 0x02570320},
-	{0x0004, 0x041f0000},
-	{0x0008, 0x031f031f},
-	{0x000c, 0x067f0347},
-	{0x0010, 0x02780000},
-	{0x0014, 0x0257025c},
-	{0x0018, 0x00000000},
-	{0x001c, 0x02570320},
-	{0x0100, 0x80010900},
-	{0x0, 0x0}
-};
-
-const gdc_regs *board_get_regs (void)
-{
-	return init_regs;
-}
-
-/* Returns Lime base address */
-unsigned int board_video_init (void)
-{
-	if (mb862xx_probe (CONFIG_SYS_LIME_BASE) != MB862XX_TYPE_LIME)
-		return 0;
-
-	mb862xx.winSizeX = 800;
-	mb862xx.winSizeY = 600;
-	mb862xx.gdfIndex = GDF_15BIT_555RGB;
-	mb862xx.gdfBytesPP = 2;
-
-	return CONFIG_SYS_LIME_BASE;
-}
-
-#if defined(CONFIG_CONSOLE_EXTRA_INFO)
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str (int line_number, char *info)
-{
-	if (line_number == 1)
-		strcpy (info, " Board: IPEK01");
-	else
-		info[0] = '\0';
-}
-#endif
-#endif /* CONFIG_VIDEO */
diff --git a/board/is1/qts/sdram_config.h b/board/is1/qts/sdram_config.h
index 67ea1ec..8ce3c70 100644
--- a/board/is1/qts/sdram_config.h
+++ b/board/is1/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x777
diff --git a/board/isee/igep0033/Kconfig b/board/isee/igep0033/Kconfig
deleted file mode 100644
index e989e4b..0000000
--- a/board/isee/igep0033/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_AM335X_IGEP0033
-
-config SYS_BOARD
-	default "igep0033"
-
-config SYS_VENDOR
-	default "isee"
-
-config SYS_SOC
-	default "am33xx"
-
-config SYS_CONFIG_NAME
-	default "am335x_igep0033"
-
-endif
diff --git a/board/isee/igep0033/MAINTAINERS b/board/isee/igep0033/MAINTAINERS
deleted file mode 100644
index bd8a1f2..0000000
--- a/board/isee/igep0033/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-IGEP0033 BOARD
-M:	Enric Balletbo i Serra <eballetbo@gmail.com>
-S:	Maintained
-F:	board/isee/igep0033/
-F:	include/configs/am335x_igep0033.h
-F:	configs/am335x_igep0033_defconfig
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
deleted file mode 100644
index 5fea7ff..0000000
--- a/board/isee/igep0033/board.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * Board functions for IGEP COM AQUILA based boards
- *
- * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <spl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
-#include <asm/emif.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <cpsw.h>
-#include "board.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-#ifdef CONFIG_SPL_BUILD
-static const struct ddr_data ddr3_data = {
-	.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
-	.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
-	.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
-	.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
-	.cmd0csratio = K4B2G1646EBIH9_RATIO,
-	.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
-
-	.cmd1csratio = K4B2G1646EBIH9_RATIO,
-	.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
-
-	.cmd2csratio = K4B2G1646EBIH9_RATIO,
-	.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
-	.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
-	.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
-	.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
-	.sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
-	.sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
-	.zq_config = K4B2G1646EBIH9_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
-};
-
-#define OSC    (V_OSCK/1000000)
-const struct dpll_params dpll_ddr = {
-		400, OSC-1, 1, -1, -1, -1, -1};
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
-	return &dpll_ddr;
-}
-
-void set_uart_mux_conf(void)
-{
-	enable_uart0_pin_mux();
-}
-
-void set_mux_conf_regs(void)
-{
-	enable_board_pin_mux();
-}
-
-const struct ctrl_ioregs ioregs = {
-	.cm0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
-	.cm1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
-	.cm2ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
-	.dt0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
-	.dt1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
-};
-
-void sdram_init(void)
-{
-	config_ddr(400, &ioregs, &ddr3_data,
-		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
-#endif
-
-/*
- * Basic board specific setup.  Pinmux has been handled already.
- */
-int board_init(void)
-{
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	gpmc_init();
-
-	return 0;
-}
-
-#if defined(CONFIG_DRIVER_TI_CPSW)
-static void cpsw_control(int enabled)
-{
-	/* VTP can be added here */
-
-	return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
-	{
-		.slave_reg_ofs	= 0x208,
-		.sliver_reg_ofs	= 0xd80,
-		.phy_addr	= 0,
-		.phy_if		= PHY_INTERFACE_MODE_RMII,
-	},
-};
-
-static struct cpsw_platform_data cpsw_data = {
-	.mdio_base		= CPSW_MDIO_BASE,
-	.cpsw_base		= CPSW_BASE,
-	.mdio_div		= 0xff,
-	.channels		= 8,
-	.cpdma_reg_ofs		= 0x800,
-	.slaves			= 1,
-	.slave_data		= cpsw_slaves,
-	.ale_reg_ofs		= 0xd00,
-	.ale_entries		= 1024,
-	.host_port_reg_ofs	= 0x108,
-	.hw_stats_reg_ofs	= 0x900,
-	.bd_ram_ofs		= 0x2000,
-	.mac_control		= (1 << 5),
-	.control		= cpsw_control,
-	.host_port_num		= 0,
-	.version		= CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
-	int rv, ret = 0;
-	uint8_t mac_addr[6];
-	uint32_t mac_hi, mac_lo;
-
-	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
-		/* try reading mac address from efuse */
-		mac_lo = readl(&cdev->macid0l);
-		mac_hi = readl(&cdev->macid0h);
-		mac_addr[0] = mac_hi & 0xFF;
-		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
-		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
-		mac_addr[4] = mac_lo & 0xFF;
-		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-		if (is_valid_ethaddr(mac_addr))
-			eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
-
-	writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
-	       &cdev->miisel);
-
-	rv = cpsw_register(&cpsw_data);
-	if (rv < 0)
-		printf("Error %d registering CPSW switch\n", rv);
-	else
-		ret += rv;
-
-	return ret;
-}
-#endif
diff --git a/board/isee/igep0033/mux.c b/board/isee/igep0033/mux.c
deleted file mode 100644
index e862776..0000000
--- a/board/isee/igep0033/mux.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include <i2c.h>
-#include "board.h"
-
-static struct module_pin_mux uart0_pin_mux[] = {
-	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
-	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
-	{-1},
-};
-
-static struct module_pin_mux mmc0_pin_mux[] = {
-	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
-	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
-	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
-	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
-	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
-	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
-	{OFFSET(mcasp0_aclkx), (MODE(4) | RXACTIVE)},		/* MMC0_CD */
-	{-1},
-};
-
-static struct module_pin_mux nand_pin_mux[] = {
-	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
-	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
-	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
-	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
-	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
-	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
-	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
-	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
-	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
-	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
-	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},		/* NAND_CS0 */
-	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
-	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
-	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
-	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
-	{-1},
-};
-
-static struct module_pin_mux rmii1_pin_mux[] = {
-	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
-	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXERR */
-	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRS_DV */
-	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RXD0 */
-	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RXD1 */
-	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TXD0 */
-	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TXD1 */
-	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_REF_CLK */
-	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},	/* MDIO_DATA */
-	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
-	{-1},
-};
-
-void enable_uart0_pin_mux(void)
-{
-	configure_module_pin_mux(uart0_pin_mux);
-}
-
-/*
- * Do board-specific muxes.
- */
-void enable_board_pin_mux(void)
-{
-	/* NAND Flash */
-	configure_module_pin_mux(nand_pin_mux);
-	/* SD Card */
-	configure_module_pin_mux(mmc0_pin_mux);
-	/* Ethernet pinmux. */
-	configure_module_pin_mux(rmii1_pin_mux);
-}
diff --git a/board/isee/igep003x/Kconfig b/board/isee/igep003x/Kconfig
new file mode 100644
index 0000000..68a68fc
--- /dev/null
+++ b/board/isee/igep003x/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_AM335X_IGEP003X
+
+config SYS_BOARD
+	default "igep003x"
+
+config SYS_VENDOR
+	default "isee"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "am335x_igep003x"
+
+endif
diff --git a/board/isee/igep003x/MAINTAINERS b/board/isee/igep003x/MAINTAINERS
new file mode 100644
index 0000000..748b189
--- /dev/null
+++ b/board/isee/igep003x/MAINTAINERS
@@ -0,0 +1,6 @@
+IGEP003X BOARD
+M:	Enric Balletbo i Serra <eballetbo@gmail.com>
+S:	Maintained
+F:	board/isee/igep003x/
+F:	include/configs/am335x_igep003x.h
+F:	configs/am335x_igep0033_defconfig
diff --git a/board/isee/igep0033/Makefile b/board/isee/igep003x/Makefile
index fc985b4..fc985b4 100644
--- a/board/isee/igep0033/Makefile
+++ b/board/isee/igep003x/Makefile
diff --git a/board/isee/igep003x/board.c b/board/isee/igep003x/board.c
new file mode 100644
index 0000000..e33170d
--- /dev/null
+++ b/board/isee/igep003x/board.c
@@ -0,0 +1,295 @@
+/*
+ * Board functions for IGEP COM AQUILA and SMARC AM335x based boards
+ *
+ * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <fdt_support.h>
+#include <mtd_node.h>
+#include <jffs2/load_kernel.h>
+#include <environment.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
+ * and control IGEP0034 green and red LEDs.
+ * U-boot configures these pins as input pullup to detect board revision:
+ * IGEP0034-LITE = 0b00
+ * IGEP0034 (FULL) = 0b01
+ * IGEP0033 = 0b1X
+ */
+#define GPIO_GREEN_REVISION	27
+#define GPIO_RED_REVISION	26
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/*
+ * Routine: get_board_revision
+ * Description: Returns the board revision
+ */
+static int get_board_revision(void)
+{
+	int revision;
+
+	gpio_request(GPIO_GREEN_REVISION, "green_revision");
+	gpio_direction_input(GPIO_GREEN_REVISION);
+	revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
+	gpio_free(GPIO_GREEN_REVISION);
+
+	gpio_request(GPIO_RED_REVISION, "red_revision");
+	gpio_direction_input(GPIO_RED_REVISION);
+	revision = revision + gpio_get_value(GPIO_RED_REVISION);
+	gpio_free(GPIO_RED_REVISION);
+
+	return revision;
+}
+
+#ifdef CONFIG_SPL_BUILD
+/* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
+static const struct ddr_data ddr3_igep0034_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct ddr_data ddr3_igep0034_lite_data = {
+	.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
+	.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
+	.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
+	.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
+	.cmd0csratio = K4B2G1646EBIH9_RATIO,
+	.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+
+	.cmd1csratio = K4B2G1646EBIH9_RATIO,
+	.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+
+	.cmd2csratio = K4B2G1646EBIH9_RATIO,
+	.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_igep0034_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
+	.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
+	.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
+	.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
+	.sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
+	.sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
+	.zq_config = K4B2G1646EBIH9_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
+};
+
+const struct ctrl_ioregs ioregs_igep0034 = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_igep0034_lite = {
+	.cm0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.cm1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.cm2ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.dt0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.dt1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+};
+
+#define OSC    (V_OSCK/1000000)
+const struct dpll_params dpll_ddr = {
+		400, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr;
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_board_pin_mux();
+}
+
+void sdram_init(void)
+{
+	if (get_board_revision() == 1)
+		config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
+			&ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
+	else
+		config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
+			&ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+#endif
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	gpmc_init();
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	switch (get_board_revision()) {
+		case 0:
+			setenv("board_name", "igep0034-lite");
+			break;
+		case 1:
+			setenv("board_name", "igep0034");
+			break;
+		default:
+			setenv("board_name", "igep0033");
+			break;
+	}
+#endif
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+	static struct node_info nodes[] = {
+		{ "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
+	};
+
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_DRIVER_TI_CPSW)
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+		.phy_if		= PHY_INTERFACE_MODE_RMII,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, ret = 0;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+		/* try reading mac address from efuse */
+		mac_lo = readl(&cdev->macid0l);
+		mac_hi = readl(&cdev->macid0h);
+		mac_addr[0] = mac_hi & 0xFF;
+		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+		mac_addr[4] = mac_lo & 0xFF;
+		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+		if (is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+	}
+
+	writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
+	       &cdev->miisel);
+
+	if (get_board_revision() == 1)
+		cpsw_slaves[0].phy_addr = 1;
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		ret += rv;
+
+	return ret;
+}
+#endif
diff --git a/board/isee/igep0033/board.h b/board/isee/igep003x/board.h
index a11d7ab..a11d7ab 100644
--- a/board/isee/igep0033/board.h
+++ b/board/isee/igep003x/board.h
diff --git a/board/isee/igep003x/mux.c b/board/isee/igep003x/mux.c
new file mode 100644
index 0000000..550e3b3
--- /dev/null
+++ b/board/isee/igep003x/mux.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
+	{-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},		/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(1)},			/* RMII1_TXEN */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* RMII1_RXERR */
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* RMII1_CRS_DV */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* RMII1_RXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* RMII1_RXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* RMII1_TXD0 */
+	{OFFSET(mii1_txd1), MODE(1)},			/* RMII1_TXD1 */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_REF_CLK */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},	/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux gpio_pin_mux[] = {
+	{OFFSET(gpmc_ad10), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* GPIO0_26 */
+	{OFFSET(gpmc_ad11), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* GPIO0_27 */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+/*
+ * Do board-specific muxes.
+ */
+void enable_board_pin_mux(void)
+{
+	/* NAND Flash */
+	configure_module_pin_mux(nand_pin_mux);
+	/* SD Card */
+	configure_module_pin_mux(mmc0_pin_mux);
+	/* Ethernet pinmux. */
+	configure_module_pin_mux(rmii1_pin_mux);
+	/* GPIO pinmux. */
+	configure_module_pin_mux(gpio_pin_mux);
+}
diff --git a/board/isee/igep00x0/MAINTAINERS b/board/isee/igep00x0/MAINTAINERS
index d355c46..720ef2a 100644
--- a/board/isee/igep00x0/MAINTAINERS
+++ b/board/isee/igep00x0/MAINTAINERS
@@ -6,9 +6,3 @@ F:	include/configs/omap3_igep00x0.h
 F:	configs/igep0020_defconfig
 F:	configs/igep0030_defconfig
 F:	configs/igep0032_defconfig
-
-IGEP0020_NAND BOARD
-#M:	-
-S:	Maintained
-F:	configs/igep0020_nand_defconfig
-F:	configs/igep0030_nand_defconfig
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 808955e..843d35e 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -23,32 +23,17 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/onenand.h>
 #include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+#include <fdt_support.h>
 #include "igep00x0.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-const omap3_sysinfo sysinfo = {
-	DDR_STACKED,
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
-	"IGEPv2",
-#endif
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
-	"IGEP COM MODULE/ELECTRON",
-#endif
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
-	"IGEP COM PROTON",
-#endif
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
-	"ONENAND",
-#else
-	"NAND",
-#endif
-};
-
 static const struct ns16550_platdata igep_serial = {
 	.base = OMAP34XX_UART3,
 	.reg_shift = 2,
-	.clock = V_NS16550_CLK
+	.clock = V_NS16550_CLK,
+	.fcr = UART_FCR_DEFVAL,
 };
 
 U_BOOT_DEVICE(igep_uart) = {
@@ -84,8 +69,8 @@ int board_init(void)
 	/* boot param addr */
 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
 
-#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
-	status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
+	status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
 #endif
 
 	return 0;
@@ -102,10 +87,22 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
 	int mfr, id, err = identify_nand_chip(&mfr, &id);
 
 	timings->mr = MICRON_V_MR_165;
-	if (!err && mfr == NAND_MFR_MICRON) {
-		timings->mcfg = MICRON_V_MCFG_200(256 << 20);
-		timings->ctrla = MICRON_V_ACTIMA_200;
-		timings->ctrlb = MICRON_V_ACTIMB_200;
+	if (!err) {
+		switch (mfr) {
+		case NAND_MFR_HYNIX:
+			timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+			timings->ctrla = HYNIX_V_ACTIMA_200;
+			timings->ctrlb = HYNIX_V_ACTIMB_200;
+			break;
+		case NAND_MFR_MICRON:
+			timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+			timings->ctrla = MICRON_V_ACTIMA_200;
+			timings->ctrlb = MICRON_V_ACTIMB_200;
+			break;
+		default:
+			/* Should not happen... */
+			break;
+		}
 		timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 		gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
 	} else {
@@ -202,20 +199,54 @@ int board_eth_init(bd_t *bis)
 static inline void setup_net_chip(void) {}
 #endif
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
 }
 #endif
 
-#if defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 void board_mmc_power_init(void)
 {
 	twl4030_power_mmc_init(0);
 }
 #endif
 
+#ifdef CONFIG_OF_BOARD_SETUP
+static int ft_enable_by_compatible(void *blob, char *compat, int enable)
+{
+	int off = fdt_node_offset_by_compatible(blob, -1, compat);
+	if (off < 0)
+		return off;
+
+	if (enable)
+		fdt_status_okay(blob, off);
+	else
+		fdt_status_disabled(blob, off);
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+	static struct node_info nodes[] = {
+		{ "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
+		{ "ti,omap2-onenand", MTD_DEV_TYPE_ONENAND, },
+	};
+
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+	ft_enable_by_compatible(blob, "ti,omap2-nand",
+				gpmc_cs0_flash == MTD_DEV_TYPE_NAND);
+	ft_enable_by_compatible(blob, "ti,omap2-onenand",
+				gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND);
+
+	return 0;
+}
+#endif
+
 void set_fdt(void)
 {
 	switch (gd->bd->bi_arch_number) {
diff --git a/board/jupiter/Kconfig b/board/jupiter/Kconfig
deleted file mode 100644
index d71acbb..0000000
--- a/board/jupiter/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_JUPITER
-
-config SYS_BOARD
-	default "jupiter"
-
-config SYS_CONFIG_NAME
-	default "jupiter"
-
-endif
diff --git a/board/jupiter/MAINTAINERS b/board/jupiter/MAINTAINERS
deleted file mode 100644
index 5a79a61..0000000
--- a/board/jupiter/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-JUPITER BOARD
-M:	Heiko Schocher <hs@denx.de>
-S:	Maintained
-F:	board/jupiter/
-F:	include/configs/jupiter.h
-F:	configs/jupiter_defconfig
diff --git a/board/jupiter/Makefile b/board/jupiter/Makefile
deleted file mode 100644
index 4d3ef9e..0000000
--- a/board/jupiter/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= jupiter.o
diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c
deleted file mode 100644
index d56902b..0000000
--- a/board/jupiter/jupiter.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- * (C) Copyright 2007
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <libfdt.h>
-
-#define SDRAM_DDR	0
-#if 1
-/* Settings Icecube */
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000
-#else
-/*Settings Jupiter UB 1.0.0 */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_CONTROL	0xD04F0000
-#define SDRAM_CONFIG1	0xf7277f00
-#define SDRAM_CONFIG2	0x88b70004
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-#endif
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *            is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set tap delay */
-	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	}
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else {
-		dramsize2 = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20)) {
-		dramsize2 = 0;
-	}
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
-			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
-	if (dramsize2 >= 0x13) {
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	} else {
-		dramsize2 = 0;
-	}
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
-		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
-		__asm__ volatile ("sync");
-	}
-
-	return dramsize + dramsize2;
-}
-
-int checkboard (void)
-{
-	puts ("Board: Sauter (Jupiter)\n");
-	return 0;
-}
-
-void flash_preinit(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-int board_early_init_r (void)
-{
-	flash_preinit ();
-	return 0;
-}
-
-void flash_afterinit(ulong size)
-{
-	if (size == 0x1000000) { /* adjust mapping */
-		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
-			START_REG(CONFIG_SYS_BOOTCS_START | size);
-		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
-			STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
-	}
-	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
-}
-
-int update_flash_size (int flash_size)
-{
-	flash_afterinit (flash_size);
-	return 0;
-}
-
-int board_early_init_f (void)
-{
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-	return 0;
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset (void)
-{
-	debug ("init_ide_reset\n");
-
-	/* Configure PSC1_4 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
-	/* Deassert reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC1_4;
-}
-
-void ide_set_reset (int idereset)
-{
-	debug ("ide_reset(%d)\n", idereset);
-
-	if (idereset) {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
-		/* Make a delay. MPC5200 spec says 25 usec min */
-		udelay(500000);
-	} else {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
-	}
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index 0829b7f..408079c 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -355,9 +355,6 @@ static int do_checktestboot(cmd_tbl_t *cmdtp, int flag, int argc,
 #if defined(CONFIG_POST)
 	testpin = post_hotkeys_pressed();
 #endif
-#if defined(CONFIG_MGCOGE3NE)
-	testpin = get_testpin();
-#endif
 	s = getenv("test_bank");
 	/* when test_bank is not set, act as if testpin is not asserted */
 	testboot = (testpin != 0) && (s);
diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h
index c74f569..81a0af0 100644
--- a/board/keymile/common/common.h
+++ b/board/keymile/common/common.h
@@ -137,15 +137,6 @@ int toggle_eeprom_spi_bus(void);
 int get_testpin(void);
 
 int set_km_env(void);
-int fdt_set_node_and_value(void *blob,
-			char *nodename,
-			char *regname,
-			void *var,
-			int size);
-int fdt_get_node_and_value(void *blob,
-				char *nodename,
-				char *propname,
-				void **var);
 
 #define DELAY_ABORT_SEQ		62  /* @200kHz 9 clocks = 44us, 62us is ok */
 #define DELAY_HALF_PERIOD	(500 / (CONFIG_SYS_I2C_SPEED / 1000))
diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c
index 42db542..e9e518c 100644
--- a/board/keymile/common/ivm.c
+++ b/board/keymile/common/ivm.c
@@ -189,7 +189,7 @@ static int ivm_check_crc(unsigned char *buf, int block)
 
 /* take care of the possible MAC address offset and the IVM content offset */
 static int process_mac(unsigned char *valbuf, unsigned char *buf,
-				int offset)
+				int offset, bool unique)
 {
 	unsigned char mac[6];
 	unsigned long val = (buf[4] << 16) + (buf[5] << 8) + buf[6];
@@ -199,6 +199,13 @@ static int process_mac(unsigned char *valbuf, unsigned char *buf,
 	 */
 	memcpy(mac, buf+1, 6);
 
+	/* MAC adress can be set to locally administred, this is only allowed
+	 * for interfaces which have now connection to the outside. For these
+	 * addresses we need to set the second bit in the first byte.
+	 */
+	if (!unique)
+		mac[0] |= 0x2;
+
 	if (offset) {
 		val += offset;
 		mac[3] = (val >> 16) & 0xff;
@@ -300,16 +307,24 @@ static int ivm_populate_env(unsigned char *buf, int len)
 		return 0;
 	page2 = &buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN*2];
 
+#ifndef CONFIG_KMTEGR1
 	/* if an offset is defined, add it */
-	process_mac(valbuf, page2, CONFIG_PIGGY_MAC_ADRESS_OFFSET);
-	if (getenv("ethaddr") == NULL)
-		setenv((char *)"ethaddr", (char *)valbuf);
+	process_mac(valbuf, page2, CONFIG_PIGGY_MAC_ADRESS_OFFSET, true);
+	setenv((char *)"ethaddr", (char *)valbuf);
 #ifdef CONFIG_KMVECT1
 /* KMVECT1 has two ethernet interfaces */
-	if (getenv("eth1addr") == NULL) {
-		process_mac(valbuf, page2, 1);
-		setenv((char *)"eth1addr", (char *)valbuf);
-	}
+	process_mac(valbuf, page2, 1, true);
+	setenv((char *)"eth1addr", (char *)valbuf);
+#endif
+#else
+/* KMTEGR1 has a special setup. eth0 has no connection to the outside and
+ * gets an locally administred MAC address, eth1 is the debug interface and
+ * gets the official MAC address from the IVM
+ */
+	process_mac(valbuf, page2, CONFIG_PIGGY_MAC_ADRESS_OFFSET, false);
+	setenv((char *)"ethaddr", (char *)valbuf);
+	process_mac(valbuf, page2, CONFIG_PIGGY_MAC_ADRESS_OFFSET, true);
+	setenv((char *)"eth1addr", (char *)valbuf);
 #endif
 
 	return 0;
diff --git a/board/keymile/km82xx/Kconfig b/board/keymile/km82xx/Kconfig
deleted file mode 100644
index c9a093c..0000000
--- a/board/keymile/km82xx/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_KM82XX
-
-config SYS_BOARD
-	default "km82xx"
-
-config SYS_VENDOR
-	default "keymile"
-
-config SYS_CONFIG_NAME
-	default "km82xx"
-
-endif
diff --git a/board/keymile/km82xx/MAINTAINERS b/board/keymile/km82xx/MAINTAINERS
deleted file mode 100644
index 50e06b2..0000000
--- a/board/keymile/km82xx/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-KM82XX BOARD
-M:	Holger Brunck <holger.brunck@keymile.com>
-S:	Maintained
-F:	board/keymile/km82xx/
-F:	include/configs/km82xx.h
-F:	configs/mgcoge_defconfig
-F:	configs/mgcoge3ne_defconfig
diff --git a/board/keymile/km82xx/Makefile b/board/keymile/km82xx/Makefile
deleted file mode 100644
index 20f193a..0000000
--- a/board/keymile/km82xx/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= km82xx.o ../common/common.o ../common/ivm.o
diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c
deleted file mode 100644
index c2a7a5f..0000000
--- a/board/keymile/km82xx/km82xx.c
+++ /dev/null
@@ -1,464 +0,0 @@
-/*
- * (C) Copyright 2007 - 2008
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8260.h>
-#include <ioports.h>
-#include <malloc.h>
-#include <asm/io.h>
-
-#include <libfdt.h>
-#include <i2c.h>
-#include "../common/common.h"
-
-static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-const iop_conf_t iop_conf_tab[4][32] = {
-
-	/* Port A */
-	{	/*	      conf	ppar psor pdir podr pdat */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA31	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA30	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA29	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA28	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA27	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA26	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA25	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA24	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA23	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA22	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA21	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA20	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA19	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA18	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA17	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA16	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA15	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA14	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA13	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA12	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA11	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA10	     */
-		{ 1,		 1,   0,   1,	0,   0 }, /* PA9 SMC2 TxD    */
-		{ 1,		 1,   0,   0,	0,   0 }, /* PA8 SMC2 RxD    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA7	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA6	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA5	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA4	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA3	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA2	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PA1	     */
-		{ 0,		 0,   0,   0,	0,   0 }  /* PA0	     */
-	},
-
-	/* Port B */
-	{	/*	      conf	ppar psor pdir podr pdat */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PB31	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PB30	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PB29	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PB28	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PB27	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PB26	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PB25	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PB24	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PB23	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PB22	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PB21	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PB20	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PB19	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PB18	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }  /* non-existent    */
-	},
-
-	/* Port C */
-	{	/*	      conf	ppar psor pdir podr pdat */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC31	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC30	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC29	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC28	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC27	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC26	     */
-		{ 1,		 1,   0,   0,	0,   0 }, /* PC25 RxClk      */
-		{ 1,		 1,   0,   0,	0,   0 }, /* PC24 TxClk      */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC23	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC22	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC21	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC20	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC19	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC18	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC17	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC16	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC15	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC14	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC13	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC12	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC11	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC10	     */
-		{ 1,		 1,   0,   0,	0,   0 }, /* PC9  SCC4: CTS  */
-		{ 1,		 1,   0,   0,	0,   0 }, /* PC8  SCC4: CD   */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC7	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC6	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC5	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC4	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC3	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC2	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC1	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PC0	     */
-	},
-
-	/* Port D */
-	{	/*	      conf	ppar psor pdir podr pdat */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD31	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD30	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD29	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD28	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD27	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD26	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD25	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD24	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD23	     */
-		{ 1,		 1,   0,   0,	0,   0 }, /* PD22 SCC4: RXD  */
-		{ 1,		 1,   0,   1,	0,   0 }, /* PD21 SCC4: TXD  */
-		{ 1,		 1,   0,   1,	0,   0 }, /* PD20 SCC4: RTS  */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD19	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD18	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD17	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD16	     */
-#if defined(CONFIG_HARD_I2C)
-		{ 1,		 1,   1,   0,	1,   0 }, /* PD15 I2C SDA    */
-		{ 1,		 1,   1,   0,	1,   0 }, /* PD14 I2C SCL    */
-#else
-		{ 1,		 0,   0,   0,	1,   1 }, /* PD15	     */
-		{ 1,		 0,   0,   1,	1,   1 }, /* PD14	     */
-#endif
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD13	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD12	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD11	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD10	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD9	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD8	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD7	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD6	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD5	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* PD4	     */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
-		{ 0,		 0,   0,   0,	0,   0 }  /* non-existent    */
-	}
-};
-
-/*
- * Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
- *
- * This routine performs standard 8260 initialization sequence
- * and calculates the available memory size. It may be called
- * several times to try different SDRAM configurations on both
- * 60x and local buses.
- */
-static long int try_init(memctl8260_t *memctl, ulong sdmr,
-				  ulong orx, uchar *base)
-{
-	uchar c = 0xff;
-	ulong maxsize, size;
-	int i;
-
-	/*
-	 * We must be able to test a location outsize the maximum legal size
-	 * to find out THAT we are outside; but this address still has to be
-	 * mapped by the controller. That means, that the initial mapping has
-	 * to be (at least) twice as large as the maximum expected size.
-	 */
-	maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
-
-	out_be32(&memctl->memc_or1, orx);
-
-	/*
-	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
-	 *
-	 * "At system reset, initialization software must set up the
-	 *  programmable parameters in the memory controller banks registers
-	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
-	 *  system software should execute the following initialization sequence
-	 *  for each SDRAM device.
-	 *
-	 *  1. Issue a PRECHARGE-ALL-BANKS command
-	 *  2. Issue eight CBR REFRESH commands
-	 *  3. Issue a MODE-SET command to initialize the mode register
-	 *
-	 *  The initial commands are executed by setting P/LSDMR[OP] and
-	 *  accessing the SDRAM with a single-byte transaction."
-	 *
-	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address
-	 * CONFIG_SYS_SDRAM_BASE.
-	 */
-
-	out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA);
-	out_8(base, c);
-
-	out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR);
-	for (i = 0; i < 8; i++)
-		out_8(base, c);
-
-	out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW);
-	/* setting MR on address lines */
-	out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c);
-
-	out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN);
-	out_8(base, c);
-
-	size = get_ram_size((long *)base, maxsize);
-	out_be32(&memctl->memc_or1, orx | ~(size - 1));
-
-	return size;
-}
-
-#ifdef CONFIG_SYS_SDRAM_LIST
-
-/*
- * If CONFIG_SYS_SDRAM_LIST is defined, we cycle through all SDRAM
- * configurations therein (should be from high to lower) to find the
- * one actually matching the current configuration.
- * CONFIG_SYS_PSDMR and CONFIG_SYS_OR1 will contain the base values which are
- * common among all possible configurations; values in CONFIG_SYS_SDRAM_LIST
- * (defined as the initialization value for the array of struct sdram_conf_s)
- * will then be ORed with such base values.
- */
-
-struct sdram_conf_s {
-	ulong size;
-	int or1;
-	int psdmr;
-};
-
-static struct sdram_conf_s sdram_conf[] = CONFIG_SYS_SDRAM_LIST;
-
-static long probe_sdram(memctl8260_t *memctl)
-{
-	int n = 0;
-	long psize = 0;
-
-	for (n = 0; n < ARRAY_SIZE(sdram_conf); psize = 0, n++) {
-		psize = try_init(memctl,
-			CONFIG_SYS_PSDMR | sdram_conf[n].psdmr,
-			CONFIG_SYS_OR1 | sdram_conf[n].or1,
-			(uchar *) CONFIG_SYS_SDRAM_BASE);
-		debug("Probing %ld bytes returned %ld\n",
-			sdram_conf[n].size, psize);
-		if (psize == sdram_conf[n].size)
-			break;
-	}
-	return psize;
-}
-
-#else /* CONFIG_SYS_SDRAM_LIST */
-
-static long probe_sdram(memctl8260_t *memctl)
-{
-	return try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
-					(uchar *) CONFIG_SYS_SDRAM_BASE);
-}
-#endif /* CONFIG_SYS_SDRAM_LIST */
-
-
-phys_size_t initdram(int board_type)
-{
-	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	memctl8260_t *memctl = &immap->im_memctl;
-
-	long psize;
-
-	out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT);
-	out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
-
-	/* 60x SDRAM setup:
-	 */
-	psize = probe_sdram(memctl);
-
-	icache_enable();
-
-	return psize;
-}
-
-int checkboard(void)
-{
-#if defined(CONFIG_MGCOGE)
-	puts("Board: Keymile mgcoge");
-#else
-	puts("Board: Keymile mgcoge3ne");
-#endif
-	if (ethernet_present())
-		puts(" with PIGGY.");
-	puts("\n");
-	return 0;
-}
-
-int last_stage_init(void)
-{
-	struct bfticu_iomap *base =
-		(struct bfticu_iomap *)CONFIG_SYS_FPGA_BASE;
-	u8 dip_switch;
-
-	dip_switch = in_8(&base->mswitch);
-	dip_switch &= BFTICU_DIPSWITCH_MASK;
-	/* dip switch 'full reset' or 'db erase' or 'Local mgmt IP' or any */
-	if (dip_switch != 0) {
-		/* start bootloader */
-		puts("DIP:   Enabled\n");
-		setenv("actual_bank", "0");
-	}
-	set_km_env();
-	return 0;
-}
-
-#ifdef CONFIG_MGCOGE3NE
-static void set_pin(int state, unsigned long mask, int port);
-
-/*
- * For mgcoge3ne boards, the mgcoge3un control is controlled from
- * a GPIO line on the PPC CPU. If bobcatreset is set the line
- * will toggle once what forces the mgocge3un part to restart
- * immediately.
- */
-static void handle_mgcoge3un_reset(void)
-{
-	char *bobcatreset = getenv("bobcatreset");
-	if (bobcatreset) {
-		if (strcmp(bobcatreset, "true") == 0) {
-			puts("Forcing bobcat reset\n");
-			set_pin(0, 0x00000004, 3); /* clear PD29 (reset arm) */
-			udelay(1000);
-			set_pin(1, 0x00000004, 3);
-		} else
-			set_pin(1, 0x00000004, 3); /* don't reset arm */
-	}
-}
-#endif
-
-int ethernet_present(void)
-{
-	struct km_bec_fpga *base =
-		(struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
-
-	return in_8(&base->bprth) & PIGGY_PRESENT;
-}
-
-/*
- * Early board initalization.
- */
-int board_early_init_r(void)
-{
-	struct km_bec_fpga *base =
-		(struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
-
-	/* setup the UPIOx */
-	/* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
-	out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED));
-	/* SCC4 enable, halfduplex, FCC1 powerdown */
-	out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA |
-		H_OPORTS_FCC1_PW_DWN));
-
-#ifdef CONFIG_MGCOGE3NE
-	handle_mgcoge3un_reset();
-#endif
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
-	return 0;
-}
-
-int hush_init_var(void)
-{
-	ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
-	return 0;
-}
-
-#define SDA_MASK	0x00010000
-#define SCL_MASK	0x00020000
-
-static void set_pin(int state, unsigned long mask, int port)
-{
-	ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port);
-
-	if (state)
-		setbits_be32(&iop->pdat, mask);
-	else
-		clrbits_be32(&iop->pdat, mask);
-
-	setbits_be32(&iop->pdir, mask);
-}
-
-static int get_pin(unsigned long mask, int port)
-{
-	ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port);
-
-	clrbits_be32(&iop->pdir, mask);
-	return 0 != (in_be32(&iop->pdat) & mask);
-}
-
-void set_sda(int state)
-{
-	set_pin(state, SDA_MASK, 3);
-}
-
-void set_scl(int state)
-{
-	set_pin(state, SCL_MASK, 3);
-}
-
-int get_sda(void)
-{
-	return get_pin(SDA_MASK, 3);
-}
-
-int get_scl(void)
-{
-	return get_pin(SCL_MASK, 3);
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-
-#if defined(CONFIG_MGCOGE3NE)
-int get_testpin(void)
-{
-	/* Testpin is Port C pin 29 - enable = low */
-	int testpin = !get_pin(0x00000004, 2);
-	return testpin;
-}
-#endif
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index 154f974..8020c37 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -28,6 +28,8 @@
 
 #include "../common/common.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
 
 const qe_iop_conf_t qe_iop_conf_tab[] = {
@@ -328,13 +330,13 @@ static int fixed_sdram(void)
 	return msize;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
-		return -1;
+		return -ENXIO;
 
 	out_be32(&im->sysconf.ddrlaw[0].bar,
 		CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
@@ -348,7 +350,9 @@ phys_size_t initdram(int board_type)
 #endif
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize * 1024 * 1024;
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c
index 51a3cfe..6f8d696 100644
--- a/board/keymile/km_arm/fpga_config.c
+++ b/board/keymile/km_arm/fpga_config.c
@@ -7,7 +7,7 @@
 
 #include <common.h>
 #include <i2c.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 
 /* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
 #define KM_XLX_PROGRAM_B_PIN    39
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 079509c..85785ff 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -76,10 +76,6 @@ static const u32 kwmpp_config[] = {
 	MPP8_GPIO,		/* SDA */
 	MPP9_GPIO,		/* SCL */
 #endif
-#if defined(CONFIG_HARD_I2C)
-	MPP8_TW_SDA,
-	MPP9_TW_SCK,
-#endif
 	MPP10_UART0_TXD,
 	MPP11_UART0_RXD,
 	MPP12_GPO,		/* Reserved */
diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c
index 77af184..6f82e15 100644
--- a/board/keymile/kmp204x/ddr.c
+++ b/board/keymile/kmp204x/ddr.c
@@ -14,6 +14,8 @@
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num)
@@ -48,7 +50,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size = 0;
 
@@ -60,5 +62,7 @@ phys_size_t initdram(int board_type)
 	dram_size *= 0x100000;
 
 	debug("    DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
index eebb47f..abb2019 100644
--- a/board/keymile/kmp204x/kmp204x.c
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -277,7 +277,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
 #ifdef CONFIG_PCI
diff --git a/board/keymile/kmp204x/pci.c b/board/keymile/kmp204x/pci.c
index 2b0b054..b827e43 100644
--- a/board/keymile/kmp204x/pci.c
+++ b/board/keymile/kmp204x/pci.c
@@ -14,7 +14,7 @@
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <asm/fsl_serdes.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 
 #include "kmp204x.h"
 
diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c
index b3159d3..980cd62 100644
--- a/board/kosagi/novena/novena.c
+++ b/board/kosagi/novena/novena.c
@@ -7,7 +7,7 @@
  */
 
 #include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -16,11 +16,11 @@
 #include <asm/arch/iomux.h>
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/video.h>
 #include <fsl_esdhc.h>
 #include <i2c.h>
 #include <input.h>
@@ -167,7 +167,7 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-#ifdef CONFIG_CMD_SATA
+#ifdef CONFIG_SATA
 	setup_sata();
 #endif
 
diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c
index 92c61ae..3645b75 100644
--- a/board/kosagi/novena/novena_spl.c
+++ b/board/kosagi/novena/novena_spl.c
@@ -14,9 +14,9 @@
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/arch/crm_regs.h>
 #include <i2c.h>
 #include <mmc.h>
@@ -605,8 +605,8 @@ void board_init_f(ulong dummy)
 
 	/* Perform DDR DRAM calibration */
 	udelay(100);
-	mmdc_do_write_level_calibration();
-	mmdc_do_dqs_calibration();
+	mmdc_do_write_level_calibration(&novena_ddr_info);
+	mmdc_do_dqs_calibration(&novena_ddr_info);
 
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
diff --git a/board/kosagi/novena/video.c b/board/kosagi/novena/video.c
index 3bb1b71..bd84569 100644
--- a/board/kosagi/novena/video.c
+++ b/board/kosagi/novena/video.c
@@ -11,7 +11,7 @@
  */
 
 #include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -20,9 +20,9 @@
 #include <asm/arch/iomux.h>
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/video.h>
 #include <i2c.h>
 #include <input.h>
 #include <ipu_pixfmt.h>
diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c
index 3d7af09..a938a2c 100644
--- a/board/l+g/vinco/vinco.c
+++ b/board/l+g/vinco/vinco.c
@@ -51,9 +51,9 @@ void spi_cs_deactivate(struct spi_slave *slave)
 
 static void vinco_spi0_hw_init(void)
 {
-	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* SPI0_SPCK */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* SPI0_MISO */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* SPI0_MOSI */
+	at91_pio3_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* SPI0_SPCK */
 
 	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);	/* SPI0_CS0 */
 
@@ -76,16 +76,16 @@ static void vinco_usb_hw_init(void)
 #ifdef CONFIG_GENERIC_ATMEL_MCI
 void vinco_mci0_hw_init(void)
 {
-	at91_set_b_periph(AT91_PIO_PORTC, 5, 1);	/* MCI0 CDA */
-	at91_set_b_periph(AT91_PIO_PORTC, 6, 1);	/* MCI0 DA0 */
-	at91_set_b_periph(AT91_PIO_PORTC, 7, 1);	/* MCI0 DA1 */
-	at91_set_b_periph(AT91_PIO_PORTC, 8, 1);	/* MCI0 DA2 */
-	at91_set_b_periph(AT91_PIO_PORTC, 9, 1);	/* MCI0 DA3 */
-	at91_set_b_periph(AT91_PIO_PORTC, 10, 1);	/* MCI0 DA4 */
-	at91_set_b_periph(AT91_PIO_PORTC, 11, 1);	/* MCI0 DA5 */
-	at91_set_b_periph(AT91_PIO_PORTC, 12, 1);	/* MCI0 DA6 */
-	at91_set_b_periph(AT91_PIO_PORTC, 13, 1);	/* MCI0 DA7 */
-	at91_set_b_periph(AT91_PIO_PORTC, 4, 0);	/* MCI0 CLK */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 5, 1);	/* MCI0 CDA */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 6, 1);	/* MCI0 DA0 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 7, 1);	/* MCI0 DA1 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 8, 1);	/* MCI0 DA2 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 9, 1);	/* MCI0 DA3 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 10, 1);	/* MCI0 DA4 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 11, 1);	/* MCI0 DA5 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 12, 1);	/* MCI0 DA6 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 13, 1);	/* MCI0 DA7 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTC, 4, 0);	/* MCI0 CLK */
 
 	/*
 	 * As the mci io internal pull down is too strong, so if the io needs
@@ -93,16 +93,16 @@ void vinco_mci0_hw_init(void)
 	 * the power consumption will increase, so disable the interanl pull
 	 * down to save the power.
 	 */
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
-	at91_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 4, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 5, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 6, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 7, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 8, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 9, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 10, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 11, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 12, 0);
+	at91_pio3_set_pio_pulldown(AT91_PIO_PORTC, 13, 0);
 
 	/* Enable clock */
 	at91_periph_clk_enable(ATMEL_ID_MCI0);
@@ -120,16 +120,16 @@ int board_mmc_init(bd_t *bis)
 #ifdef CONFIG_MACB
 void vinco_macb0_hw_init(void)
 {
-	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* ETXCK_EREFCK */
-	at91_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* ERXDV */
-	at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* ERX0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* ERX1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* ERXER */
-	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* ETXEN */
-	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* ETX0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* ETX1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* EMDIO */
-	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* EMDC */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* ETXCK_EREFCK */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* ERXDV */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* ERX0 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* ERX1 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* ERXER */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* ETXEN */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* ETX0 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* ETX1 */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* EMDIO */
+	at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* EMDC */
 
 	/* Enable clock */
 	at91_periph_clk_enable(ATMEL_ID_GMAC0);
@@ -141,8 +141,8 @@ void vinco_macb0_hw_init(void)
 
 static void vinco_serial3_hw_init(void)
 {
-	at91_set_b_periph(AT91_PIO_PORTE, 17, 1);	/* TXD3 */
-	at91_set_b_periph(AT91_PIO_PORTE, 16, 0);	/* RXD3 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1);	/* TXD3 */
+	at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0);	/* RXD3 */
 
 	/* Enable clock */
 	at91_periph_clk_enable(ATMEL_ID_USART3);
diff --git a/board/lego/ev3/legoev3.c b/board/lego/ev3/legoev3.c
index a791b97..2653439 100644
--- a/board/lego/ev3/legoev3.c
+++ b/board/lego/ev3/legoev3.c
@@ -23,10 +23,12 @@
 #include <asm/arch/pinmux_defs.h>
 #include <asm/io.h>
 #include <asm/arch/davinci_misc.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <hwconfig.h>
+#include <asm/mach-types.h>
+#include <asm/setup.h>
 
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
 #include <mmc.h>
 #include <asm/arch/sdmmc_defs.h>
 #endif
@@ -39,7 +41,7 @@ u8 board_rev;
 #define EEPROM_REV_OFFSET	0x3F00
 #define EEPROM_MAC_OFFSET	0x3F06
 
-#ifdef CONFIG_DAVINCI_MMC
+#ifdef CONFIG_MMC_DAVINCI
 static struct davinci_mmc mmc_sd0 = {
 	.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
 	.host_caps = MMC_MODE_4BIT,     /* DA850 supports only 4-bit SD/MMC */
@@ -145,9 +147,7 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-#ifndef CONFIG_USE_IRQ
 	irq_init();
-#endif
 
 	/* arch number of the board */
 	/* LEGO didn't register for a unique number and uses da850evm */
diff --git a/board/lg/sniper/sniper.c b/board/lg/sniper/sniper.c
index 0662449..f924645 100644
--- a/board/lg/sniper/sniper.c
+++ b/board/lg/sniper/sniper.c
@@ -31,7 +31,8 @@ const omap3_sysinfo sysinfo = {
 static const struct ns16550_platdata serial_omap_platdata = {
 	.base = OMAP34XX_UART3,
 	.reg_shift = 2,
-	.clock = V_NS16550_CLK
+	.clock = V_NS16550_CLK,
+	.fcr = UART_FCR_DEFVAL,
 };
 
 U_BOOT_DEVICE(sniper_serial) = {
@@ -178,12 +179,10 @@ int fb_set_reboot_flag(void)
 	return omap_reboot_mode_store("b");
 }
 
-#ifndef CONFIG_SPL_BUILD
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(1, 0, 0, -1, -1);
 }
-#endif
 
 void board_mmc_power_init(void)
 {
diff --git a/board/liebherr/lwmon5/Kconfig b/board/liebherr/lwmon5/Kconfig
deleted file mode 100644
index 7f1bb40..0000000
--- a/board/liebherr/lwmon5/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TARGET_LWMON5
-
-config SYS_BOARD
-	default "lwmon5"
-
-config SYS_VENDOR
-	default "liebherr"
-
-config SYS_CONFIG_NAME
-	default "lwmon5"
-
-config DISPLAY_BOARDINFO
-	bool
-	default y
-
-endif
diff --git a/board/liebherr/lwmon5/MAINTAINERS b/board/liebherr/lwmon5/MAINTAINERS
deleted file mode 100644
index df45730..0000000
--- a/board/liebherr/lwmon5/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-LWMON5 BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/liebherr/lwmon5/
-F:	include/configs/lwmon5.h
-F:	configs/lwmon5_defconfig
diff --git a/board/liebherr/lwmon5/Makefile b/board/liebherr/lwmon5/Makefile
deleted file mode 100644
index 02478ca..0000000
--- a/board/liebherr/lwmon5/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= lwmon5.o kbd.o sdram.o
-extra-y	+= init.o
diff --git a/board/liebherr/lwmon5/config.mk b/board/liebherr/lwmon5/config.mk
deleted file mode 100644
index d0348e8..0000000
--- a/board/liebherr/lwmon5/config.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-# lwmon5 (440EPx)
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/liebherr/lwmon5/init.S b/board/liebherr/lwmon5/init.S
deleted file mode 100644
index e5207c2..0000000
--- a/board/liebherr/lwmon5/init.S
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-	.section .bootpg,"ax"
-	.globl tlbtab
-
-tlbtab:
-	tlbtab_start
-
-	/*
-	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
-	 * speed up boot process. It is patched after relocation to enable SA_I
-	 */
-	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G)
-
-	/*
-	 * TLB entries for SDRAM are not needed on this platform.
-	 * They are dynamically generated in the SPD DDR(2) detection
-	 * routine.
-	 */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
-	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
-#endif
-
-	/* TLB-entry for PCI Memory */
-	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG)
-
-	/* TLB-entry for the FPGA Chip select 2 */
-	tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G)
-
-	/* TLB-entry for the FPGA Chip select 3 */
-	tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G)
-
-	/* TLB-entry for the LIME Controller */
-	tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G)
-	tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G)
-	tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G)
-	tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G)
-
-	/* TLB-entry for Internal Registers & OCM */
-	tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0,  AC_RWX | SA_I)
-
-	/*TLB-entry PCI registers*/
-	tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1,  AC_RWX | SA_IG)
-
-	/* TLB-entry for peripherals */
-	tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
-
-	tlbtab_end
diff --git a/board/liebherr/lwmon5/kbd.c b/board/liebherr/lwmon5/kbd.c
deleted file mode 100644
index d6c0a20..0000000
--- a/board/liebherr/lwmon5/kbd.c
+++ /dev/null
@@ -1,491 +0,0 @@
-/*
- * (C) Copyright 2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2001, 2002
- * DENX Software Engineering
- * Wolfgang Denk, wd@denx.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <i2c.h>
-#include <command.h>
-#include <console.h>
-#include <post.h>
-#include <serial.h>
-#include <malloc.h>
-
-#include <linux/types.h>
-#include <linux/string.h>	/* for strdup */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void kbd_init (void);
-static int compare_magic (uchar *kbd_data, uchar *str);
-
-/*--------------------- Local macros and constants --------------------*/
-#define	_NOT_USED_	0xFFFFFFFF
-
-/*------------------------- dspic io expander -----------------------*/
-#define DSPIC_PON_STATUS_REG	0x80A
-#define DSPIC_PON_INV_STATUS_REG 0x80C
-#define DSPIC_PON_KEY_REG	0x810
-/*------------------------- Keyboard controller -----------------------*/
-/* command codes */
-#define	KEYBD_CMD_READ_KEYS	0x01
-#define KEYBD_CMD_READ_VERSION	0x02
-#define KEYBD_CMD_READ_STATUS	0x03
-#define KEYBD_CMD_RESET_ERRORS	0x10
-
-/* status codes */
-#define KEYBD_STATUS_MASK	0x3F
-#define	KEYBD_STATUS_H_RESET	0x20
-#define KEYBD_STATUS_BROWNOUT	0x10
-#define KEYBD_STATUS_WD_RESET	0x08
-#define KEYBD_STATUS_OVERLOAD	0x04
-#define KEYBD_STATUS_ILLEGAL_WR	0x02
-#define KEYBD_STATUS_ILLEGAL_RD	0x01
-
-/* Number of bytes returned from Keyboard Controller */
-#define KEYBD_VERSIONLEN	2	/* version information */
-
-/*
- * This is different from the "old" lwmon dsPIC kbd controller
- * implementation. Now the controller still answers with 9 bytes,
- * but the last 3 bytes are always "0x06 0x07 0x08". So we just
- * set the length to compare to 6 instead of 9.
- */
-#define	KEYBD_DATALEN		6	/* normal key scan data */
-
-/* maximum number of "magic" key codes that can be assigned */
-
-static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
-static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR;
-
-static uchar *key_match (uchar *);
-
-#define	KEYBD_SET_DEBUGMODE	'#'	/* Magic key to enable debug output */
-
-/***********************************************************************
-F* Function:     int board_postclk_init (void) P*A*Z*
- *
-P* Parameters:   none
-P*
-P* Returnvalue:  int
-P*                - 0 is always returned.
- *
-Z* Intention:    This function is the board_postclk_init() method implementation
-Z*               for the lwmon board.
- *
- ***********************************************************************/
-int board_postclk_init (void)
-{
-	kbd_init();
-
-	return (0);
-}
-
-static void kbd_init (void)
-{
-	uchar kbd_data[KEYBD_DATALEN];
-	uchar tmp_data[KEYBD_DATALEN];
-	uchar val, errcd;
-	int i;
-
-	i2c_set_bus_num(0);
-
-	gd->arch.kbd_status = 0;
-
-	/* Forced by PIC. Delays <= 175us loose */
-	udelay(1000);
-
-	/* Read initial keyboard error code */
-	val = KEYBD_CMD_READ_STATUS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, &errcd, 1);
-	/* clear unused bits */
-	errcd &= KEYBD_STATUS_MASK;
-	/* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
-	errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
-	if (errcd) {
-		gd->arch.kbd_status |= errcd << 8;
-	}
-	/* Reset error code and verify */
-	val = KEYBD_CMD_RESET_ERRORS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	udelay(1000);	/* delay NEEDED by keyboard PIC !!! */
-
-	val = KEYBD_CMD_READ_STATUS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, &val, 1);
-
-	val &= KEYBD_STATUS_MASK;	/* clear unused bits */
-	if (val) {			/* permanent error, report it */
-		gd->arch.kbd_status |= val;
-		return;
-	}
-
-	/*
-	 * Read current keyboard state.
-	 *
-	 * After the error reset it may take some time before the
-	 * keyboard PIC picks up a valid keyboard scan - the total
-	 * scan time is approx. 1.6 ms (information by Martin Rajek,
-	 * 28 Sep 2002). We read a couple of times for the keyboard
-	 * to stabilize, using a big enough delay.
-	 * 10 times should be enough. If the data is still changing,
-	 * we use what we get :-(
-	 */
-
-	memset (tmp_data, 0xFF, KEYBD_DATALEN);	/* impossible value */
-	for (i=0; i<10; ++i) {
-		val = KEYBD_CMD_READ_KEYS;
-		i2c_write (kbd_addr, 0, 0, &val, 1);
-		i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
-		if (memcmp(kbd_data, tmp_data, KEYBD_DATALEN) == 0) {
-			/* consistent state, done */
-			break;
-		}
-		/* remeber last state, delay, and retry */
-		memcpy (tmp_data, kbd_data, KEYBD_DATALEN);
-		udelay (5000);
-	}
-}
-
-
-/* Read a register from the dsPIC. */
-int _dspic_read(ushort reg, ushort *data)
-{
-	uchar buf[sizeof(*data)];
-	int rval;
-
-	if (i2c_read(dspic_addr, reg, 2, buf, 2))
-		return -1;
-
-	rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data));
-	*data = (buf[0] << 8) | buf[1];
-
-	return rval;
-}
-
-
-/***********************************************************************
-F* Function:     int misc_init_r (void) P*A*Z*
- *
-P* Parameters:   none
-P*
-P* Returnvalue:  int
-P*                - 0 is always returned, even in the case of a keyboard
-P*                    error.
- *
-Z* Intention:    This function is the misc_init_r() method implementation
-Z*               for the lwmon board.
-Z*               The keyboard controller is initialized and the result
-Z*               of a read copied to the environment variable "keybd".
-Z*               If KEYBD_SET_DEBUGMODE is defined, a check is made for
-Z*               this key, and if found display to the LCD will be enabled.
-Z*               The keys in "keybd" are checked against the magic
-Z*               keycommands defined in the environment.
-Z*               See also key_match().
- *
-D* Design:       wd@denx.de
-C* Coding:       wd@denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-int misc_init_r_kbd (void)
-{
-	uchar kbd_data[KEYBD_DATALEN];
-	char keybd_env[2 * KEYBD_DATALEN + 1];
-	uchar kbd_init_status = gd->arch.kbd_status >> 8;
-	uchar kbd_status = gd->arch.kbd_status;
-	uchar val;
-	ushort data, inv_data;
-	char *str;
-	int i;
-
-	if (kbd_init_status) {
-		printf ("KEYBD: Error %02X\n", kbd_init_status);
-	}
-	if (kbd_status) {		/* permanent error, report it */
-		printf ("*** Keyboard error code %02X ***\n", kbd_status);
-		sprintf (keybd_env, "%02X", kbd_status);
-		setenv ("keybd", keybd_env);
-		return 0;
-	}
-
-	/*
-	 * Now we know that we have a working  keyboard,  so  disable
-	 * all output to the LCD except when a key press is detected.
-	 */
-
-	if ((console_assign (stdout, "serial") < 0) ||
-		(console_assign (stderr, "serial") < 0)) {
-		printf ("Can't assign serial port as output device\n");
-	}
-
-	/* Read Version */
-	val = KEYBD_CMD_READ_VERSION;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_VERSIONLEN);
-	printf ("KEYBD: Version %d.%d\n", kbd_data[0], kbd_data[1]);
-
-	/* Read current keyboard state */
-	val = KEYBD_CMD_READ_KEYS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
-	/* read out start key from bse01 received via can */
-	_dspic_read(DSPIC_PON_STATUS_REG, &data);
-	/* check highbyte from status register */
-	if (data > 0xFF) {
-		_dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data);
-
-		/* check inverse data */
-		if ((data+inv_data) == 0xFFFF) {
-			/* don't overwrite local key */
-			if (kbd_data[1] == 0) {
-				/* read key value */
-				_dspic_read(DSPIC_PON_KEY_REG, &data);
-				str = (char *)&data;
-				/* swap bytes */
-				kbd_data[1] = str[1];
-				kbd_data[2] = str[0];
-				printf("CAN received startkey: 0x%X\n", data);
-			}
-		}
-	}
-
-	for (i = 0; i < KEYBD_DATALEN; ++i) {
-		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
-	}
-
-	setenv ("keybd", keybd_env);
-
-	str = strdup ((char *)key_match (kbd_data));	/* decode keys */
-#ifdef KEYBD_SET_DEBUGMODE
-	if (kbd_data[0] == KEYBD_SET_DEBUGMODE) {	/* set debug mode */
-		if ((console_assign (stdout, "lcd") < 0) ||
-			(console_assign (stderr, "lcd") < 0)) {
-			printf ("Can't assign LCD display as output device\n");
-		}
-	}
-#endif /* KEYBD_SET_DEBUGMODE */
-#ifdef CONFIG_PREBOOT	/* automatically configure "preboot" command on key match */
-	setenv ("preboot", str);	/* set or delete definition */
-#endif /* CONFIG_PREBOOT */
-	if (str != NULL) {
-		free (str);
-	}
-	return (0);
-}
-
-#ifdef CONFIG_PREBOOT
-
-static uchar kbd_magic_prefix[] = "key_magic";
-static uchar kbd_command_prefix[] = "key_cmd";
-
-static int compare_magic (uchar *kbd_data, uchar *str)
-{
-	uchar compare[KEYBD_DATALEN-1];
-	char *nxt;
-	int i;
-
-	/* Don't include modifier byte */
-	memcpy (compare, kbd_data+1, KEYBD_DATALEN-1);
-
-	for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
-		uchar c;
-		int k;
-
-		c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
-
-		if (str == (uchar *)nxt) {	/* invalid character */
-			break;
-		}
-
-		/*
-		 * Check if this key matches the input.
-		 * Set matches to zero, so they match only once
-		 * and we can find duplicates or extra keys
-		 */
-		for (k = 0; k < sizeof(compare); ++k) {
-			if (compare[k] == '\0')	/* only non-zero entries */
-				continue;
-			if (c == compare[k]) {	/* found matching key */
-				compare[k] = '\0';
-				break;
-			}
-		}
-		if (k == sizeof(compare)) {
-			return -1;		/* unmatched key */
-		}
-	}
-
-	/*
-	 * A full match leaves no keys in the `compare' array,
-	 */
-	for (i = 0; i < sizeof(compare); ++i) {
-		if (compare[i])
-		{
-			return -1;
-		}
-	}
-
-	return 0;
-}
-
-/***********************************************************************
-F* Function:     static uchar *key_match (uchar *kbd_data) P*A*Z*
- *
-P* Parameters:   uchar *kbd_data
-P*                - The keys to match against our magic definitions
-P*
-P* Returnvalue:  uchar *
-P*                - != NULL: Pointer to the corresponding command(s)
-P*                     NULL: No magic is about to happen
- *
-Z* Intention:    Check if pressed key(s) match magic sequence,
-Z*               and return the command string associated with that key(s).
-Z*
-Z*               If no key press was decoded, NULL is returned.
-Z*
-Z*               Note: the first character of the argument will be
-Z*                     overwritten with the "magic charcter code" of the
-Z*                     decoded key(s), or '\0'.
-Z*
-Z*               Note: the string points to static environment data
-Z*                     and must be saved before you call any function that
-Z*                     modifies the environment.
- *
-D* Design:       wd@denx.de
-C* Coding:       wd@denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-static uchar *key_match (uchar *kbd_data)
-{
-	char magic[sizeof (kbd_magic_prefix) + 1];
-	uchar *suffix;
-	char *kbd_magic_keys;
-
-	/*
-	 * The following string defines the characters that can pe appended
-	 * to "key_magic" to form the names of environment variables that
-	 * hold "magic" key codes, i. e. such key codes that can cause
-	 * pre-boot actions. If the string is empty (""), then only
-	 * "key_magic" is checked (old behaviour); the string "125" causes
-	 * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
-	 */
-	if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
-		kbd_magic_keys = "";
-
-	/* loop over all magic keys;
-	 * use '\0' suffix in case of empty string
-	 */
-	for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
-		sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
-		debug ("### Check magic \"%s\"\n", magic);
-		if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
-			char cmd_name[sizeof (kbd_command_prefix) + 1];
-			char *cmd;
-
-			sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
-
-			cmd = getenv (cmd_name);
-			debug ("### Set PREBOOT to $(%s): \"%s\"\n",
-					cmd_name, cmd ? cmd : "<<NULL>>");
-			*kbd_data = *suffix;
-			return ((uchar *)cmd);
-		}
-	}
-	debug ("### Delete PREBOOT\n");
-	*kbd_data = '\0';
-	return (NULL);
-}
-#endif /* CONFIG_PREBOOT */
-
-/***********************************************************************
-F* Function:     int do_kbd (cmd_tbl_t *cmdtp, int flag,
-F*                           int argc, char * const argv[]) P*A*Z*
- *
-P* Parameters:   cmd_tbl_t *cmdtp
-P*                - Pointer to our command table entry
-P*               int flag
-P*                - If the CMD_FLAG_REPEAT bit is set, then this call is
-P*                  a repetition
-P*               int argc
-P*                - Argument count
-P*               char * const argv[]
-P*                - Array of the actual arguments
-P*
-P* Returnvalue:  int
-P*                - 0 is always returned.
- *
-Z* Intention:    Implement the "kbd" command.
-Z*               The keyboard status is read.  The result is printed on
-Z*               the console and written into the "keybd" environment
-Z*               variable.
- *
-D* Design:       wd@denx.de
-C* Coding:       wd@denx.de
-V* Verification: dzu@denx.de
- ***********************************************************************/
-int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	uchar kbd_data[KEYBD_DATALEN];
-	char keybd_env[2 * KEYBD_DATALEN + 1];
-	uchar val;
-	int i;
-
-#if 0 /* Done in kbd_init */
-	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
-
-	/* Read keys */
-	val = KEYBD_CMD_READ_KEYS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
-	puts ("Keys:");
-	for (i = 0; i < KEYBD_DATALEN; ++i) {
-		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
-		printf (" %02x", kbd_data[i]);
-	}
-	putc ('\n');
-	setenv ("keybd", keybd_env);
-	return 0;
-}
-
-U_BOOT_CMD(
-	kbd,	1,	1,	do_kbd,
-	"read keyboard status",
-	""
-);
-
-/*----------------------------- Utilities -----------------------------*/
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
-	uchar kbd_data[KEYBD_DATALEN];
-	uchar val;
-
-	/* Read keys */
-	val = KEYBD_CMD_READ_KEYS;
-	i2c_write (kbd_addr, 0, 0, &val, 1);
-	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
-
-	return (compare_magic(kbd_data, (uchar *)CONFIG_POST_KEY_MAGIC) == 0);
-}
-#endif
diff --git a/board/liebherr/lwmon5/lwmon5.c b/board/liebherr/lwmon5/lwmon5.c
deleted file mode 100644
index 8ad6712..0000000
--- a/board/liebherr/lwmon5/lwmon5.c
+++ /dev/null
@@ -1,550 +0,0 @@
-/*
- * (C) Copyright 2007-2013
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/ppc440.h>
-#include <asm/processor.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/io.h>
-#include <post.h>
-#include <flash.h>
-#include <mtd/cfi_flash.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
-
-ulong flash_get_size(ulong base, int banknum);
-int misc_init_r_kbd(void);
-
-int board_early_init_f(void)
-{
-	u32 sdr0_pfc1, sdr0_pfc2;
-	u32 reg;
-
-	/* PLB Write pipelining disabled. Denali Core workaround */
-	mtdcr(PLB4A0_ACR, 0xDE000000);
-	mtdcr(PLB4A1_ACR, 0xDE000000);
-
-	/*--------------------------------------------------------------------
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 *-------------------------------------------------------------------*/
-	mtdcr(UIC0SR, 0xffffffff);  /* clear all. if write with 1 then the status is cleared  */
-	mtdcr(UIC0ER, 0x00000000);  /* disable all */
-	mtdcr(UIC0CR, 0x00000000);  /* we have not critical interrupts at the moment */
-	mtdcr(UIC0PR, 0xFFBFF1EF);  /* Adjustment of the polarity */
-	mtdcr(UIC0TR, 0x00000900);  /* per ref-board manual */
-	mtdcr(UIC0VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
-	mtdcr(UIC0SR, 0xffffffff);  /* clear all */
-
-	mtdcr(UIC1SR, 0xffffffff);  /* clear all */
-	mtdcr(UIC1ER, 0x00000000);  /* disable all */
-	mtdcr(UIC1CR, 0x00000000);  /* all non-critical */
-	mtdcr(UIC1PR, 0xFFFFC6A5);  /* Adjustment of the polarity */
-	mtdcr(UIC1TR, 0x60000040);  /* per ref-board manual */
-	mtdcr(UIC1VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
-	mtdcr(UIC1SR, 0xffffffff);  /* clear all */
-
-	mtdcr(UIC2SR, 0xffffffff);  /* clear all */
-	mtdcr(UIC2ER, 0x00000000);  /* disable all */
-	mtdcr(UIC2CR, 0x00000000);  /* all non-critical */
-	mtdcr(UIC2PR, 0x27C00000);  /* Adjustment of the polarity */
-	mtdcr(UIC2TR, 0x3C000000);  /* per ref-board manual */
-	mtdcr(UIC2VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
-	mtdcr(UIC2SR, 0xffffffff);  /* clear all */
-
-	/* Trace Pins are disabled. SDR0_PFC0 Register */
-	mtsdr(SDR0_PFC0, 0x0);
-
-	/* select Ethernet pins */
-	mfsdr(SDR0_PFC1, sdr0_pfc1);
-	/* SMII via ZMII */
-	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
-		SDR0_PFC1_SELECT_CONFIG_6;
-	mfsdr(SDR0_PFC2, sdr0_pfc2);
-	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
-		SDR0_PFC2_SELECT_CONFIG_6;
-
-	/* enable SPI (SCP) */
-	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
-
-	mtsdr(SDR0_PFC2, sdr0_pfc2);
-	mtsdr(SDR0_PFC1, sdr0_pfc1);
-
-	mtsdr(SDR0_PFC4, 0x80000000);
-
-	/* PCI arbiter disabled */
-	/* PCI Host Configuration disbaled */
-	mfsdr(SDR0_PCI0, reg);
-	reg = 0;
-	mtsdr(SDR0_PCI0, 0x00000000 | reg);
-
-	gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
-
-#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
-	/* enable the LSB transmitter */
-	gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
-	/* enable the CAN transmitter */
-	gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
-
-	reg = 0; /* reuse as counter */
-	out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
-		in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
-			& ~CONFIG_SYS_DSPIC_TEST_MASK);
-	while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
-		udelay(1000);
-	}
-	if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
-		/* set "boot error" flag */
-		out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
-			in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
-			CONFIG_SYS_DSPIC_TEST_MASK);
-	}
-#endif
-
-	/*
-	 * Reset PHY's:
-	 * The PHY's need a 2nd reset pulse, since the MDIO address is latched
-	 * upon reset, and with the first reset upon powerup, the addresses are
-	 * not latched reliable, since the IRQ line is multiplexed with an
-	 * MDIO address. A 2nd reset at this time will make sure, that the
-	 * correct address is latched.
-	 */
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
-	udelay(1000);
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
-	udelay(1000);
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
-	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
-
-	return 0;
-}
-
-/*
- * Override weak default with board specific version
- */
-phys_addr_t cfi_flash_bank_addr(int bank)
-{
-	return lwmon5_cfi_flash_bank_addr[bank];
-}
-
-/*
- * Override the weak default mapping function with a board specific one
- */
-u32 flash_get_bank_size(int cs, int idx)
-{
-	return flash_info[idx].size;
-}
-
-int board_early_init_r(void)
-{
-	u32 val0, val1;
-
-	/*
-	 * lwmon5 is manufactured in 2 different board versions:
-	 * The lwmon5a board has 64MiB NOR flash instead of the
-	 * 128MiB of the original lwmon5. Unfortunately the CFI driver
-	 * will report 2 banks of 64MiB even for the smaller flash
-	 * chip, since the bank is mirrored. To fix this, we bring
-	 * one bank into CFI query mode and read its response. This
-	 * enables us to detect the real number of flash devices/
-	 * banks which will be used later on by the common CFI driver.
-	 */
-
-	/* Put bank 0 into CFI command mode and read */
-	out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
-	val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
-	val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
-
-	/* Reset flash again out of query mode */
-	out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
-
-	/* When not identical, we have 2 different flash devices/banks */
-	if (val0 != val1)
-		return 0;
-
-	/*
-	 * Now we're sure that we're running on a LWMON5a board with
-	 * only 64MiB NOR flash in one bank:
-	 *
-	 * Set flash base address and bank count for CFI driver probing.
-	 */
-	cfi_flash_num_flash_banks = 1;
-	lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u32 pbcr;
-	int size_val = 0;
-	u32 reg;
-	unsigned long usb2d0cr = 0;
-	unsigned long usb2phy0cr, usb2h0cr = 0;
-	unsigned long sdr0_pfc1, sdr0_srst;
-
-	/*
-	 * FLASH stuff...
-	 */
-
-	/* Re-do sizing to get full correct info */
-
-	/* adjust flash start and offset */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-	gd->bd->bi_flashoffset = 0;
-
-	mfebc(PB0CR, pbcr);
-	size_val = ffs(gd->bd->bi_flashsize) - 21;
-	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
-	mtebc(PB0CR, pbcr);
-
-	/*
-	 * Re-check to get correct base address
-	 */
-	flash_get_size(gd->bd->bi_flashstart, 0);
-
-	/* Monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
-		      &flash_info[cfi_flash_num_flash_banks - 1]);
-
-	/* Env protection ON by default */
-	flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
-		      CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
-		      &flash_info[cfi_flash_num_flash_banks - 1]);
-
-	/*
-	 * USB suff...
-	 */
-
-	/* Reset USB */
-	/* Reset of USB2PHY0 must be active at least 10 us  */
-	mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
-	udelay(2000);
-
-	mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
-	      SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
-	      SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
-	udelay(2000);
-
-	/* Errata CHIP_6 */
-
-	/* 1. Set internal PHY configuration */
-	/* SDR Setting */
-	mfsdr(SDR0_PFC1, sdr0_pfc1);
-	mfsdr(SDR0_USB0, usb2d0cr);
-	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-	mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
-	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
-	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
-	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
-	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
-	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
-	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_DVBUS_PUREN;		/*1*/
-	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
-	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
-	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
-	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
-
-	/*
-	 * An 8-bit/60MHz interface is the only possible alternative
-	 * when connecting the Device to the PHY
-	 */
-	usb2h0cr   = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
-	usb2h0cr   = usb2h0cr |  SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/
-
-	mtsdr(SDR0_PFC1, sdr0_pfc1);
-	mtsdr(SDR0_USB0, usb2d0cr);
-	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-	mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
-	/* 2. De-assert internal PHY reset */
-	mfsdr(SDR0_SRST1, sdr0_srst);
-	sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
-	mtsdr(SDR0_SRST1, sdr0_srst);
-
-	/* 3. Wait for more than 1 ms */
-	udelay(2000);
-
-	/* 4. De-assert USB 2.0 Host main reset */
-	mfsdr(SDR0_SRST0, sdr0_srst);
-	sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
-	mtsdr(SDR0_SRST0, sdr0_srst);
-	udelay(1000);
-
-	/* 5. De-assert reset of OPB2 cores */
-	mfsdr(SDR0_SRST1, sdr0_srst);
-	sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
-	sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
-	sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
-	mtsdr(SDR0_SRST1, sdr0_srst);
-	udelay(1000);
-
-	/* 6. Set EHCI Configure FLAG */
-
-	/* 7. Reassert internal PHY reset: */
-	mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
-	udelay(1000);
-
-	/*
-	 * Clear resets
-	 */
-	mtsdr(SDR0_SRST1, 0x00000000);
-	mtsdr(SDR0_SRST0, 0x00000000);
-
-	printf("USB:   Host(int phy) Device(ext phy)\n");
-
-	/*
-	 * Clear PLB4A0_ACR[WRP]
-	 * This fix will make the MAL burst disabling patch for the Linux
-	 * EMAC driver obsolete.
-	 */
-	reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
-	mtdcr(PLB4A0_ACR, reg);
-
-	/*
-	 * Init matrix keyboard
-	 */
-	misc_init_r_kbd();
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf("Board: %s", __stringify(CONFIG_HOSTNAME));
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return (0);
-}
-
-void hw_watchdog_reset(void)
-{
-	int val;
-#if defined(CONFIG_WD_MAX_RATE)
-	unsigned long long ct = get_ticks();
-
-	/*
-	 * Don't allow watch-dog triggering more frequently than
-	 * the predefined value CONFIG_WD_MAX_RATE [ticks].
-	 */
-	if (ct >= gd->arch.wdt_last) {
-		if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE)
-			return;
-	} else {
-		/* Time base counter had been reset */
-		if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) <
-		    CONFIG_WD_MAX_RATE)
-			return;
-	}
-	gd->arch.wdt_last = get_ticks();
-#endif
-
-	/*
-	 * Toggle watchdog output
-	 */
-	val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
-	gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
-}
-
-int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	if (argc < 2)
-		return cmd_usage(cmdtp);
-
-	if ((strcmp(argv[1], "on") == 0))
-		gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
-	else if ((strcmp(argv[1], "off") == 0))
-		gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
-	else
-		return cmd_usage(cmdtp);
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	eepromwp,	2,	0,	do_eeprom_wp,
-	"eeprom write protect off/on",
-	"<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
-);
-
-#if defined(CONFIG_VIDEO)
-#include <video_fb.h>
-#include <mb862xx.h>
-
-extern GraphicDevice mb862xx;
-
-static const gdc_regs init_regs [] = {
-	{ 0x0100, 0x00000f00 },
-	{ 0x0020, 0x801401df },
-	{ 0x0024, 0x00000000 },
-	{ 0x0028, 0x00000000 },
-	{ 0x002c, 0x00000000 },
-	{ 0x0110, 0x00000000 },
-	{ 0x0114, 0x00000000 },
-	{ 0x0118, 0x01df0280 },
-	{ 0x0004, 0x031f0000 },
-	{ 0x0008, 0x027f027f },
-	{ 0x000c, 0x015f028f },
-	{ 0x0010, 0x020c0000 },
-	{ 0x0014, 0x01df01ea },
-	{ 0x0018, 0x00000000 },
-	{ 0x001c, 0x01e00280 },
-	{ 0x0100, 0x80010f00 },
-	{ 0x0, 0x0 }
-};
-
-const gdc_regs *board_get_regs(void)
-{
-	return init_regs;
-}
-
-/* Returns Lime base address */
-unsigned int board_video_init(void)
-{
-	/*
-	 * Reset Lime controller
-	 */
-	gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
-	udelay(500);
-	gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
-
-	mb862xx.winSizeX = 640;
-	mb862xx.winSizeY = 480;
-	mb862xx.gdfBytesPP = 2;
-	mb862xx.gdfIndex = GDF_15BIT_555RGB;
-
-	return CONFIG_SYS_LIME_BASE_0;
-}
-
-#define DEFAULT_BRIGHTNESS	0x64
-
-static void board_backlight_brightness(int brightness)
-{
-	if (brightness > 0) {
-		/* pwm duty, lamp on */
-		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
-		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
-	} else {
-		/* lamp off */
-		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
-		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
-	}
-}
-
-void board_backlight_switch(int flag)
-{
-	char * param;
-	int rc;
-
-	if (flag) {
-		param = getenv("brightness");
-		rc = param ? simple_strtol(param, NULL, 10) : -1;
-		if (rc < 0)
-			rc = DEFAULT_BRIGHTNESS;
-	} else {
-		rc = 0;
-	}
-	board_backlight_brightness(rc);
-}
-
-#if defined(CONFIG_CONSOLE_EXTRA_INFO)
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str(int line_number, char *info)
-{
-	if (line_number == 1)
-		strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
-	else
-		info [0] = '\0';
-}
-#endif /* CONFIG_CONSOLE_EXTRA_INFO */
-#endif /* CONFIG_VIDEO */
-
-void board_reset(void)
-{
-	gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-/*
- * lwmon5 specific implementation of spl_start_uboot()
- *
- * RETURN
- * 0 if booting into OS is selected (default)
- * 1 if booting into U-Boot is selected
- */
-int spl_start_uboot(void)
-{
-	char s[8];
-
-	env_init();
-	getenv_f("boot_os", s, sizeof(s));
-	if ((s != NULL) && (strcmp(s, "yes") == 0))
-		return 0;
-
-	return 1;
-}
-
-/*
- * This function is called from the SPL U-Boot version for
- * early init stuff, that needs to be done for OS (e.g. Linux)
- * booting. Doing it later in the real U-Boot would not work
- * in case that the SPL U-Boot boots Linux directly.
- */
-void spl_board_init(void)
-{
-	const gdc_regs *regs = board_get_regs();
-
-	/*
-	 * Setup PFC registers, mainly for ethernet support
-	 * later on in Linux
-	 */
-	board_early_init_f();
-
-	/* enable the LSB transmitter */
-	gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
-
-	/*
-	 * Clear resets
-	 */
-	mtsdr(SDR0_SRST1, 0x00000000);
-	mtsdr(SDR0_SRST0, 0x00000000);
-
-	/*
-	 * Reset Lime controller
-	 */
-	gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
-	udelay(500);
-	gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
-
-	out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF);
-	udelay(300);
-	out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR);
-
-	while (regs->index) {
-		out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) +
-			 regs->index, regs->value);
-		regs++;
-	}
-
-	board_backlight_brightness(DEFAULT_BRIGHTNESS);
-}
-#endif
diff --git a/board/liebherr/lwmon5/sdram.c b/board/liebherr/lwmon5/sdram.c
deleted file mode 100644
index bcb3449..0000000
--- a/board/liebherr/lwmon5/sdram.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * (C) Copyright 2006
- * Sylvie Gohl,		    AMCC/IBM, gohl.sylvie@fr.ibm.com
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Thierry Roman,	    AMCC/IBM, thierry_roman@fr.ibm.com
- * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
- * Robert Snyder,	    AMCC/IBM, rob.snyder@fr.ibm.com
- *
- * (C) Copyright 2007-2013
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/* define DEBUG for debugging output (obviously ;-)) */
-#if 0
-#define DEBUG
-#endif
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/cache.h>
-#include <asm/ppc440.h>
-#include <watchdog.h>
-
-/*
- * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
- * region. Right now the cache should still be disabled in U-Boot because of the
- * EMAC driver, that need it's buffer descriptor to be located in non cached
- * memory.
- *
- * If at some time this restriction doesn't apply anymore, just define
- * CONFIG_4xx_DCACHE in the board config file and this code should setup
- * everything correctly.
- */
-#ifdef CONFIG_4xx_DCACHE
-#define MY_TLB_WORD2_I_ENABLE	0			/* enable caching on SDRAM */
-#else
-#define MY_TLB_WORD2_I_ENABLE	TLB_WORD2_I_ENABLE	/* disable caching on SDRAM */
-#endif
-
-/*-----------------------------------------------------------------------------+
- * Prototypes
- *-----------------------------------------------------------------------------*/
-extern int denali_wait_for_dlllock(void);
-extern void denali_core_search_data_eye(void);
-extern void dcbz_area(u32 start_address, u32 num_bytes);
-
-static u32 is_ecc_enabled(void)
-{
-	u32 val;
-
-	mfsdram(DDR0_22, val);
-	val &= DDR0_22_CTRL_RAW_MASK;
-	if (val)
-		return 1;
-	else
-		return 0;
-}
-
-void board_add_ram_info(int use_default)
-{
-	PPC4xx_SYS_INFO board_cfg;
-	u32 val;
-
-	if (is_ecc_enabled())
-		puts(" (ECC");
-	else
-		puts(" (ECC not");
-
-	get_sys_info(&board_cfg);
-	printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000);
-
-	mfsdram(DDR0_03, val);
-	val = DDR0_03_CASLAT_DECODE(val);
-	printf(", CL%d)", val);
-}
-
-#ifdef CONFIG_DDR_ECC
-static void wait_ddr_idle(void)
-{
-	/*
-	 * Controller idle status cannot be determined for Denali
-	 * DDR2 code. Just return here.
-	 */
-}
-
-static void program_ecc(u32 start_address,
-			u32 num_bytes,
-			u32 tlb_word2_i_value)
-{
-	u32 val;
-	u32 current_addr = start_address;
-	u32 size;
-	int bytes_remaining;
-
-	sync();
-	wait_ddr_idle();
-
-	/*
-	 * Because of 440EPx errata CHIP 11, we don't touch the last 256
-	 * bytes of SDRAM.
-	 */
-	bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE;
-
-	/*
-	 * We have to write the ECC bytes by zeroing and flushing in smaller
-	 * steps, since the whole 256MByte takes too long for the external
-	 * watchdog.
-	 */
-	while (bytes_remaining > 0) {
-		size = min((64 << 20), bytes_remaining);
-
-		/* Write zero's to SDRAM */
-		dcbz_area(current_addr, size);
-
-		/* Write modified dcache lines back to memory */
-		clean_dcache_range(current_addr, current_addr + size);
-
-		current_addr += 64 << 20;
-		bytes_remaining -= 64 << 20;
-		WATCHDOG_RESET();
-	}
-
-	sync();
-	wait_ddr_idle();
-
-	/* Clear error status */
-	mfsdram(DDR0_00, val);
-	mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
-
-	/* Set 'int_mask' parameter to functionnal value */
-	mfsdram(DDR0_01, val);
-	mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
-
-	sync();
-	wait_ddr_idle();
-}
-#endif
-
-/*************************************************************************
- *
- * initdram -- 440EPx's DDR controller is a DENALI Core
- *
- ************************************************************************/
-phys_size_t initdram (int board_type)
-{
-	/* CL=4 */
-	mtsdram(DDR0_02, 0x00000000);
-
-	mtsdram(DDR0_00, 0x0000190A);
-	mtsdram(DDR0_01, 0x01000000);
-	mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
-
-	mtsdram(DDR0_04, 0x0B030300);
-	mtsdram(DDR0_05, 0x02020308);
-	mtsdram(DDR0_06, 0x0003C812);
-	mtsdram(DDR0_07, 0x00090100);
-	mtsdram(DDR0_08, 0x03c80001);
-	mtsdram(DDR0_09, 0x00011D5F);
-	mtsdram(DDR0_10, 0x00000100);
-	mtsdram(DDR0_11, 0x000CC800);
-	mtsdram(DDR0_12, 0x00000003);
-	mtsdram(DDR0_14, 0x00000000);
-	mtsdram(DDR0_17, 0x1e000000);
-	mtsdram(DDR0_18, 0x1e1e1e1e);
-	mtsdram(DDR0_19, 0x1e1e1e1e);
-	mtsdram(DDR0_20, 0x0B0B0B0B);
-	mtsdram(DDR0_21, 0x0B0B0B0B);
-#ifdef CONFIG_DDR_ECC
-	mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC       */
-#else
-	mtsdram(DDR0_22, 0x00267F0B);
-#endif
-
-	mtsdram(DDR0_23, 0x01000000);
-	mtsdram(DDR0_24, 0x01010001);
-
-	mtsdram(DDR0_26, 0x2D93028A);
-	mtsdram(DDR0_27, 0x0784682B);
-
-	mtsdram(DDR0_28, 0x00000080);
-	mtsdram(DDR0_31, 0x00000000);
-	mtsdram(DDR0_42, 0x01000008);
-
-	mtsdram(DDR0_43, 0x050A0200);
-	mtsdram(DDR0_44, 0x00000005);
-	mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
-
-	denali_wait_for_dlllock();
-
-#if defined(CONFIG_DDR_DATA_EYE)
-	/* -----------------------------------------------------------+
-	 * Perform data eye search if requested.
-	 * ----------------------------------------------------------*/
-	program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
-		    TLB_WORD2_I_ENABLE);
-	denali_core_search_data_eye();
-	remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
-#endif
-
-	/*
-	 * Program tlb entries for this size (dynamic)
-	 */
-	program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
-		    MY_TLB_WORD2_I_ENABLE);
-
-#if defined(CONFIG_DDR_ECC)
-#if defined(CONFIG_4xx_DCACHE)
-	/*
-	 * If ECC is enabled, initialize the parity bits.
-	 */
-	program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-#else /* CONFIG_4xx_DCACHE */
-	/*
-	 * Setup 2nd TLB with same physical address but different virtual address
-	 * with cache enabled. This is done for fast ECC generation.
-	 */
-	program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-
-	/*
-	 * If ECC is enabled, initialize the parity bits.
-	 */
-	program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
-
-	/*
-	 * Now after initialization (auto-calibration and ECC generation)
-	 * remove the TLB entries with caches enabled and program again with
-	 * desired cache functionality
-	 */
-	remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
-#endif /* CONFIG_4xx_DCACHE */
-#endif /* CONFIG_DDR_ECC */
-
-	/*
-	 * Clear possible errors resulting from data-eye-search.
-	 * If not done, then we could get an interrupt later on when
-	 * exceptions are enabled.
-	 */
-	set_mcsr(get_mcsr());
-
-	return (CONFIG_SYS_MBYTES_SDRAM << 20);
-}
diff --git a/board/liebherr/mccmon6/Kconfig b/board/liebherr/mccmon6/Kconfig
new file mode 100644
index 0000000..4cc7fc2
--- /dev/null
+++ b/board/liebherr/mccmon6/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MCCMON6
+
+config SYS_BOARD
+	default "mccmon6"
+
+config SYS_VENDOR
+	default "liebherr"
+
+config SYS_CONFIG_NAME
+	default "mccmon6"
+
+endif
diff --git a/board/liebherr/mccmon6/MAINTAINERS b/board/liebherr/mccmon6/MAINTAINERS
new file mode 100644
index 0000000..c9c7183
--- /dev/null
+++ b/board/liebherr/mccmon6/MAINTAINERS
@@ -0,0 +1,7 @@
+MCCMON6 BOARD
+M:	Lukasz Majewski <lukma@denx.de>
+S:	Maintained
+F:	board/liebherr/mccmon6/
+F:	include/configs/mccmon6.h
+F:	configs/mccmon6_nor_defconfig
+F:	configs/mccmon6_sd_defconfig
diff --git a/board/liebherr/mccmon6/Makefile b/board/liebherr/mccmon6/Makefile
new file mode 100644
index 0000000..e37baf8
--- /dev/null
+++ b/board/liebherr/mccmon6/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2016-2017
+# Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mccmon6.o spl.o
diff --git a/board/liebherr/mccmon6/mccmon6.c b/board/liebherr/mccmon6/mccmon6.c
new file mode 100644
index 0000000..e265e2a
--- /dev/null
+++ b/board/liebherr/mccmon6/mccmon6.c
@@ -0,0 +1,490 @@
+/*
+ * Copyright (C) 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/io.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <micrel.h>
+#include <phy.h>
+#include <input.h>
+#include <i2c.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define USDHC2_CD_GPIO		IMX_GPIO_NR(1, 4)
+#define ETH_PHY_RESET		IMX_GPIO_NR(1, 27)
+#define ECSPI3_CS0		IMX_GPIO_NR(4, 24)
+#define ECSPI3_FLWP		IMX_GPIO_NR(4, 27)
+#define NOR_WP			IMX_GPIO_NR(1, 1)
+#define DISPLAY_EN		IMX_GPIO_NR(1, 2)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	/* Carrier MicroSD Card Detect */
+	IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
+		   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
+		   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
+		   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	/* KSZ9031 PHY Reset */
+	IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+}
+
+static void setup_iomux_enet(void)
+{
+	SETUP_IOMUX_PADS(enet_pads);
+
+	/* Reset KSZ9031 PHY */
+	gpio_direction_output(ETH_PHY_RESET, 0);
+	mdelay(10);
+	gpio_set_value(ETH_PHY_RESET, 1);
+	udelay(100);
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC3_BASE_ADDR},
+	{USDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		/*
+		 * eMMC don't have card detect pin - since it is soldered to the
+		 * PCB board
+		 */
+		ret = 1;
+		break;
+	}
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+	u32 index = 0;
+
+	/*
+	 * MMC MAP
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    Soldered on board eMMC device
+	 * mmc1                    MicroSD card
+	 */
+	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+		switch (index) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc3_pads);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			usdhc_cfg[0].max_bus_width = 8;
+			break;
+		case 1:
+			SETUP_IOMUX_PADS(usdhc2_pads);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			usdhc_cfg[1].max_bus_width = 4;
+			gpio_direction_input(USDHC2_CD_GPIO);
+			break;
+		default:
+			printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
+			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const eimnor_pads[] = {
+	IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA0__EIM_AD00   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA1__EIM_AD01   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA2__EIM_AD02   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA3__EIM_AD03   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA4__EIM_AD04   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA5__EIM_AD05   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA6__EIM_AD06   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA7__EIM_AD07   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA8__EIM_AD08   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA9__EIM_AD09   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA10__EIM_AD10  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA11__EIM_AD11  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA12__EIM_AD12  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA13__EIM_AD13  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA14__EIM_AD14  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA15__EIM_AD15  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_OE__EIM_OE_B	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_RW__EIM_RW		| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void eimnor_cs_setup(void)
+{
+	struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+
+
+	/* NOR configuration */
+	writel(0x00620181, &weim_regs->cs0gcr1);
+	writel(0x00000001, &weim_regs->cs0gcr2);
+	writel(0x0b020000, &weim_regs->cs0rcr1);
+	writel(0x0000b000, &weim_regs->cs0rcr2);
+	writel(0x0804a240, &weim_regs->cs0wcr1);
+	writel(0x00000000, &weim_regs->cs0wcr2);
+
+	writel(0x00000120, &weim_regs->wcr);
+	writel(0x00000010, &weim_regs->wiar);
+	writel(0x00000000, &weim_regs->ear);
+
+	set_chipselect_size(CS0_128);
+}
+
+static void setup_eimnor(void)
+{
+	SETUP_IOMUX_PADS(eimnor_pads);
+	gpio_direction_output(NOR_WP, 1);
+
+	enable_eim_clk(1);
+	eimnor_cs_setup();
+}
+
+/* mccmon6 board has SPI Flash is connected to SPI3 */
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 2 && cs == 0) ? ECSPI3_CS0 : -1;
+}
+
+static iomux_v3_cfg_t const ecspi3_pads[] = {
+	/* SPI3 */
+	IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+};
+
+void setup_spi(void)
+{
+	SETUP_IOMUX_PADS(ecspi3_pads);
+
+	enable_spi_clk(true, 2);
+
+	/* set cs0 to high */
+	gpio_direction_output(ECSPI3_CS0, 1);
+
+	/* set flwp to high */
+	gpio_direction_output(ECSPI3_FLWP, 1);
+}
+
+struct i2c_pads_info mx6q_i2c1_pad_info = {
+	.scl = {
+		.i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(5, 27)
+	},
+	.sda = {
+		.i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(5, 26)
+	}
+};
+
+struct i2c_pads_info mx6q_i2c2_pad_info = {
+	.scl = {
+		.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+int board_eth_init(bd_t *bis)
+{
+	setup_iomux_enet();
+
+	return cpu_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	gpio_direction_output(DISPLAY_EN, 1);
+
+	setup_eimnor();
+	setup_spi();
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c1_pad_info);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("board_name", "mccmon6");
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: MCCMON6\n");
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/*
+	 * Default setting for GMII Clock Pad Skew Register 0x1EF:
+	 * MMD Address 0x2h, Register 0x8h
+	 *
+	 * GTX_CLK Pad Skew 0xF -> 0.9 nsec skew
+	 * RX_CLK Pad Skew 0xF -> 0.9 nsec skew
+	 *
+	 * Adjustment -> write 0x3FF:
+	 * GTX_CLK Pad Skew 0x1F -> 1.8 nsec skew
+	 * RX_CLK Pad Skew 0x1F -> 1.8 nsec skew
+	 *
+	 */
+	ksz9031_phy_extended_write(phydev, 0x2,
+				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x3FF);
+
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x00FF);
+
+	ksz9031_phy_extended_write(phydev, 0x2,
+				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+				   0x3333);
+
+	ksz9031_phy_extended_write(phydev, 0x2,
+				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+				   0x2052);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+	setup_eimnor();
+
+	gpio_direction_output(DISPLAY_EN, 1);
+}
+#endif /* CONFIG_SPL_BOARD_INIT */
+
+#ifdef CONFIG_SPL_BUILD
+void board_boot_order(u32 *spl_boot_list)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC2:
+	case BOOT_DEVICE_MMC1:
+		spl_boot_list[0] = BOOT_DEVICE_MMC2;
+		spl_boot_list[1] = BOOT_DEVICE_MMC1;
+		break;
+
+	case BOOT_DEVICE_NOR:
+		spl_boot_list[0] = BOOT_DEVICE_NOR;
+		break;
+	}
+}
+#endif /* CONFIG_SPL_BUILD */
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	char s[16];
+	int ret;
+	/*
+	 * We use BOOT_DEVICE_MMC1, but SD card is connected
+	 * to MMC2
+	 *
+	 * Correct "mapping" is delivered in board defined
+	 * board_boot_order() function.
+	 *
+	 * SD card boot is regarded as a "development" one,
+	 * hence we _always_ go through the u-boot.
+	 *
+	 */
+	if (spl_boot_device() == BOOT_DEVICE_MMC1)
+		return 1;
+
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+	env_init();
+	ret = getenv_f("boot_os", s, sizeof(s));
+	if ((ret != -1) && (strcmp(s, "no") == 0))
+		return 1;
+
+	/*
+	 * Check if SWUpdate recovery needs to be started
+	 *
+	 * recovery_status = NULL (not set - ret == -1) -> normal operation
+	 *
+	 * recovery_status = progress or
+	 * recovery_status = failed   or
+	 * recovery_status = <any value> -> start SWUpdate
+	 *
+	 */
+	ret = getenv_f("recovery_status", s, sizeof(s));
+	if (ret != -1)
+		return 1;
+
+	return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
diff --git a/board/liebherr/mccmon6/mon6_imximage_nor.cfg b/board/liebherr/mccmon6/mon6_imximage_nor.cfg
new file mode 100644
index 0000000..35faa11
--- /dev/null
+++ b/board/liebherr/mccmon6/mon6_imximage_nor.cfg
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+IMAGE_VERSION	2
+BOOT_FROM	nor
diff --git a/board/liebherr/mccmon6/mon6_imximage_sd.cfg b/board/liebherr/mccmon6/mon6_imximage_sd.cfg
new file mode 100644
index 0000000..7a3063c
--- /dev/null
+++ b/board/liebherr/mccmon6/mon6_imximage_sd.cfg
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+IMAGE_VERSION	2
+BOOT_FROM	sd
diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c
new file mode 100644
index 0000000..15844ef
--- /dev/null
+++ b/board/liebherr/mccmon6/spl.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (C) 2014 Wandboard
+ * Author: Tungyi Lin <tungyilin1127@gmail.com>
+ *         Richard Hu <hakahu@gmail.com>
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SPL_BUILD)
+#include <asm/arch/mx6-ddr.h>
+/*
+ * Driving strength:
+ *   0x30 == 40 Ohm
+ *   0x28 == 48 Ohm
+ */
+
+#define IMX6DQ_DRIVE_STRENGTH		0x30
+#define IMX6SDL_DRIVE_STRENGTH		0x28
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
+	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
+	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_cas = IMX6SDL_DRIVE_STRENGTH,
+	.dram_ras = IMX6SDL_DRIVE_STRENGTH,
+	.dram_reset = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* H5T04G63AFR-PB */
+static struct mx6_ddr3_cfg h5t04g63afr = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+/* H5TQ2G63DFR-H9 */
+static struct mx6_ddr3_cfg h5tq2g63dfr = {
+	.mem_speed = 1333,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1350,
+	.trcmin = 4950,
+	.trasmin = 3600,
+};
+
+static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x001f001f,
+	.p0_mpwldectrl1 = 0x001f001f,
+	.p1_mpwldectrl0 = 0x001f001f,
+	.p1_mpwldectrl1 = 0x001f001f,
+	.p0_mpdgctrl0 = 0x4301030d,
+	.p0_mpdgctrl1 = 0x03020277,
+	.p1_mpdgctrl0 = 0x4300030a,
+	.p1_mpdgctrl1 = 0x02780248,
+	.p0_mprddlctl = 0x4536393b,
+	.p1_mprddlctl = 0x36353441,
+	.p0_mpwrdlctl = 0x41414743,
+	.p1_mpwrdlctl = 0x462f453f,
+};
+
+/* DDR 64bit 2GB */
+static struct mx6_ddr_sysinfo mem_q = {
+	.dsize		= 2,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x001f001f,
+	.p0_mpwldectrl1 = 0x001f001f,
+	.p1_mpwldectrl0 = 0x001f001f,
+	.p1_mpwldectrl1 = 0x001f001f,
+	.p0_mpdgctrl0 = 0x420e020e,
+	.p0_mpdgctrl1 = 0x02000200,
+	.p1_mpdgctrl0 = 0x42020202,
+	.p1_mpdgctrl1 = 0x01720172,
+	.p0_mprddlctl = 0x494c4f4c,
+	.p1_mprddlctl = 0x4a4c4c49,
+	.p0_mpwrdlctl = 0x3f3f3133,
+	.p1_mpwrdlctl = 0x39373f2e,
+};
+
+static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x0040003c,
+	.p0_mpwldectrl1 = 0x0032003e,
+	.p0_mpdgctrl0 = 0x42350231,
+	.p0_mpdgctrl1 = 0x021a0218,
+	.p0_mprddlctl = 0x4b4b4e49,
+	.p0_mpwrdlctl = 0x3f3f3035,
+};
+
+/* DDR 64bit 1GB */
+static struct mx6_ddr_sysinfo mem_dl = {
+	.dsize		= 2,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+/* DDR 32bit 512MB */
+static struct mx6_ddr_sysinfo mem_s = {
+	.dsize		= 1,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* enable AXI cache for VDOA/VPU/IPU */
+	writel(0xF00000CF, &iomux->gpr[4]);
+	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+	writel(0x007F007F, &iomux->gpr[6]);
+	writel(0x007F007F, &iomux->gpr[7]);
+}
+
+static void spl_dram_init(void)
+{
+	if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
+	} else if (is_cpu_type(MXC_CPU_MX6DL)) {
+		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
+	} else if (is_cpu_type(MXC_CPU_MX6Q)) {
+		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+		mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
+	}
+
+	udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	gpr_init();
+
+	/* iomux */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+#endif
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
index 1f1e5ae..c18a5a3 100644
--- a/board/logicpd/am3517evm/am3517evm.c
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -21,7 +21,7 @@
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/musb.h>
 #include <asm/mach-types.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
@@ -105,7 +105,7 @@ int misc_init_r(void)
 	volatile unsigned int ctr;
 	u32 reset;
 
-#ifdef CONFIG_SYS_I2C_OMAP34XX
+#ifdef CONFIG_SYS_I2C_OMAP24XX
 	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 #endif
 
@@ -152,7 +152,7 @@ void set_muxconf_regs(void)
 	MUX_AM3517EVM();
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/logicpd/imx6/Kconfig b/board/logicpd/imx6/Kconfig
new file mode 100644
index 0000000..f5e2f58
--- /dev/null
+++ b/board/logicpd/imx6/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX6LOGICPD
+
+config SYS_BOARD
+       default "imx6"
+
+config SYS_VENDOR
+       default "logicpd"
+
+config SYS_CONFIG_NAME
+       default "imx6_logic"
+
+endif
diff --git a/board/logicpd/imx6/MAINTAINERS b/board/logicpd/imx6/MAINTAINERS
new file mode 100644
index 0000000..5db7d2c
--- /dev/null
+++ b/board/logicpd/imx6/MAINTAINERS
@@ -0,0 +1,6 @@
+MX6LOGICPD BOARD
+M:     Adam Ford <aford173@gmail.com>
+S:     Maintained
+F:     board/logicpd/imx6/
+F:     include/configs/imx6_logic.h
+F:     configs/imx6q_logic_defconfig
diff --git a/board/logicpd/imx6/Makefile b/board/logicpd/imx6/Makefile
new file mode 100644
index 0000000..337df92
--- /dev/null
+++ b/board/logicpd/imx6/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  := imx6logic.o
+
diff --git a/board/logicpd/imx6/README b/board/logicpd/imx6/README
new file mode 100644
index 0000000..df43b55
--- /dev/null
+++ b/board/logicpd/imx6/README
@@ -0,0 +1,37 @@
+U-Boot for LogicPD i.MX6 Development Kit
+----------------------------------------
+
+This file contains information for the port of U-Boot to the Logic PD Development kit.
+
+Logic PD has an i.MX6 System On Module (SOM) and a correspondong development
+board.  SOM has a built-in microSD socket, DDR and NAND flash.  The development kit has
+an SMSC Ethernet PHY, serial debug port and a variety of peripherals.
+
+On the intial release, the SOM came with either an i.MX6D or i.MX6Q.
+
+For more details about Logic PD i.MX6 Development kit, visit:
+https://www.logicpd.com/
+
+Building U-Boot for Logic PD Development Kit
+--------------------------------------------
+To build U-Boot for the Dual and Quad variants:
+
+ make imx6q_logic_defconfig
+ make u-boot.imx ARCH=arm CROSS_COMPILE=arm-linux-
+
+
+Flashing U-Boot into the SD card
+--------------------------------
+
+See README.imximage for details on booting from SD
+
+Flashing U-Boot into NAND
+-------------------------
+Once in Linux with MTD support for the NAND on /dev/mtd0, program U-Boot with the following:
+with:
+
+  kobs-ng init -v -x u-boot-dtb.imx
+
+Additional Support Documentation can be found at:
+https://support.logicpd.com/
+
diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c
new file mode 100644
index 0000000..0a7d412
--- /dev/null
+++ b/board/logicpd/imx6/imx6logic.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (C) 2017 Logic PD, Inc.
+ *
+ * Author: Adam Ford <aford173@gmail.com>
+ *
+ * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
+ * and updates by Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define NAND_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+	MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart3_pads[] = {
+	MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void fixup_enet_clock(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	struct gpio_desc nint;
+	struct gpio_desc reset;
+	int ret;
+
+	/* Set Ref Clock to 50 MHz */
+	enable_fec_anatop_clock(0, ENET_50MHZ);
+
+	/* Set GPIO_16 as ENET_REF_CLK_OUT */
+	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
+	/* Request GPIO Pins to reset Ethernet with new clock */
+	ret = dm_gpio_lookup_name("GPIO4_7", &nint);
+	if (ret) {
+		printf("Unable to lookup GPIO4_7\n");
+		return;
+	}
+
+	ret = dm_gpio_request(&nint, "eth0_nInt");
+	if (ret) {
+		printf("Unable to request eth0_nInt\n");
+		return;
+	}
+
+	/* Ensure nINT is input or PHY won't startup */
+	dm_gpio_set_dir_flags(&nint, GPIOD_IS_IN);
+
+	ret = dm_gpio_lookup_name("GPIO4_9", &reset);
+	if (ret) {
+		printf("Unable to lookup GPIO4_9\n");
+		return;
+	}
+
+	ret = dm_gpio_request(&reset, "eth0_reset");
+	if (ret) {
+		printf("Unable to request eth0_reset\n");
+		return;
+	}
+
+	/* Reset LAN8710A PHY */
+	dm_gpio_set_dir_flags(&reset, GPIOD_IS_OUT);
+	dm_gpio_set_value(&reset, 0);
+	udelay(150);
+	dm_gpio_set_value(&reset, 1);
+	mdelay(50);
+}
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+}
+
+static iomux_v3_cfg_t const nand_pads[] = {
+	MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_ALE__NAND_ALE  | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_CLE__NAND_CLE  | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_WP_B__NAND_WP_B  | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_RB0__NAND_READY_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D0__NAND_DATA00    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D1__NAND_DATA01    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D2__NAND_DATA02    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D3__NAND_DATA03    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D4__NAND_DATA04    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D5__NAND_DATA05    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D6__NAND_DATA06    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_NANDF_D7__NAND_DATA07    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_SD4_CLK__NAND_WE_B    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX6_PAD_SD4_CMD__NAND_RE_B    | MUX_PAD_CTRL(NAND_PAD_CTRL),
+};
+
+static void setup_nand_pins(void)
+{
+	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_early_init_f(void)
+{
+	fixup_enet_clock();
+	setup_iomux_uart();
+	setup_nand_pins();
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("board_name", "imx6logic");
+
+	if (is_mx6dq()) {
+		setenv("board_rev", "MX6DQ");
+		setenv("fdt_file", "imx6q-logicpd.dtb");
+	}
+
+	return 0;
+}
diff --git a/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg b/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg
new file mode 100644
index 0000000..a757461
--- /dev/null
+++ b/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2017 Logic PD, Inc.
+ * Adam Ford <aford173@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <asm/mach-imx/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION 2
+
+BOOT_OFFSET FLASH_OFFSET_STANDARD
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch-mx6/mx6-ddr.h"
+#include "asm/arch-mx6/iomux.h"
+#include "asm/arch-mx6/crm_regs.h"
+
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
+DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03340338
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0334032C
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4036383C
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x2E384038
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+DATA 4, MX6_MMDC_P0_MDCFG0, 0xB8BE7955
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00BE1023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
+DATA 4, MX6_MMDC_P0_MDCTL, 0x85190000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00888032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0xFFFFF300
+DATA 4, CCM_CCGR5, 0x0F0000F3
+DATA 4, CCM_CCGR6, 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 MX6_IOMUXC_GPR4 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 MX6_IOMUXC_GPR6 0x007F007F
+DATA 4 MX6_IOMUXC_GPR7 0x007F007F
diff --git a/board/logicpd/omap3som/Kconfig b/board/logicpd/omap3som/Kconfig
index 03d272a..68d40dc 100644
--- a/board/logicpd/omap3som/Kconfig
+++ b/board/logicpd/omap3som/Kconfig
@@ -9,4 +9,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "omap3_logic"
 
+source "board/ti/common/Kconfig"
+
 endif
diff --git a/board/logicpd/omap3som/README b/board/logicpd/omap3som/README
new file mode 100644
index 0000000..06b3998
--- /dev/null
+++ b/board/logicpd/omap3som/README
@@ -0,0 +1,19 @@
+Summary
+=======
+
+The source for omap3som encompases the DM3730 SOM-LV and DM3730 Torpedo platforms.
+
+By default, the Torpedo Device Tree is integrated into U-Boot,but the MMC controller, GPIO and I2C controllers are the same, so for the purposes of loading U-Boot, it should be sufficient.  However this will display the Model as "LogicPD Zoom DM3730 Torpedo + Wireless Development Kit" upon boot.
+
+The actual board remains autodetected and the Board will read "DM37xx SOM LV" when used on the DM37 SOM-LV.  The device tree loaded with Linux is also correct.
+
+Integrating the SOM-LV Device Tree into U-Boot
+==============================================
+
+This step is optional, but should you want to change the default to the SOM-LV, locate the configs/omap3_logic_defconfig file and make the following change.
+
+  CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-37xx-devkit"
+
+  make distclean
+  make omap3_logic_defconfig
+
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c
index c2bb730..f8b9f68 100644
--- a/board/logicpd/omap3som/omap3logic.c
+++ b/board/logicpd/omap3som/omap3logic.c
@@ -28,7 +28,7 @@
 #include <asm/mach-types.h>
 #include <linux/mtd/nand.h>
 #include <asm/omap_musb.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 #include <linux/usb/musb.h>
@@ -36,49 +36,51 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define CONTROL_WKUP_CTRL	0x48002a5c
-#define GPIO_IO_PWRDNZ	(1 << 6)
-#define PBIASLITEVMODE1	(1 << 8)
-
-/*
- * two dimensional array of strucures containining board name and Linux
- * machine IDs; row it selected based on CPU column is slected based
- * on hsusb0_data5 pin having a pulldown resistor
- */
-
+/* This is only needed until SPL gets OF support */
+#ifdef CONFIG_SPL_BUILD
 static const struct ns16550_platdata omap3logic_serial = {
 	.base = OMAP34XX_UART1,
 	.reg_shift = 2,
-	.clock = V_NS16550_CLK
+	.clock = V_NS16550_CLK,
+	.fcr = UART_FCR_DEFVAL,
 };
 
 U_BOOT_DEVICE(omap3logic_uart) = {
 	"ns16550_serial",
 	&omap3logic_serial
 };
+#endif
 
+/*
+ * two dimensional array of strucures containining board name and Linux
+ * machine IDs; row it selected based on CPU column is slected based
+ * on hsusb0_data5 pin having a pulldown resistor
+ */
 static struct board_id {
 	char *name;
 	int machine_id;
+	char *fdtfile;
 } boards[2][2] = {
 	{
 		{
 			.name		= "OMAP35xx SOM LV",
 			.machine_id	= MACH_TYPE_OMAP3530_LV_SOM,
+			.fdtfile	= "logicpd-som-lv-35xx-devkit.dtb",
 		},
 		{
 			.name		= "OMAP35xx Torpedo",
 			.machine_id	= MACH_TYPE_OMAP3_TORPEDO,
+			.fdtfile	= "logicpd-torpedo-35xx-devkit.dtb",
 		},
 	},
 	{
 		{
 			.name		= "DM37xx SOM LV",
-			.machine_id	= MACH_TYPE_DM3730_SOM_LV,
+			.fdtfile	= "logicpd-som-lv-37xx-devkit.dtb",
 		},
 		{
 			.name		= "DM37xx Torpedo",
-			.machine_id	= MACH_TYPE_DM3730_TORPEDO,
+			.fdtfile	= "logicpd-torpedo-37xx-devkit.dtb",
 		},
 	},
 };
@@ -165,14 +167,20 @@ int misc_init_r(void)
  */
 int board_init(void)
 {
-	struct board_id *board;
-	unsigned int val;
-
 	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
 
 	/* boot param addr */
 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
 
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	struct board_id *board;
+	unsigned int val;
+
 	/*
 	 * To identify between a SOM LV and Torpedo module,
 	 * a pulldown resistor is on hsusb0_data5 for the SOM LV module.
@@ -207,47 +215,28 @@ int board_init(void)
 		printf("Board: %s\n", board->name);
 
 		/* Set the machine_id passed to Linux */
-		gd->bd->bi_arch_number = board->machine_id;
+		if (board->machine_id)
+			gd->bd->bi_arch_number = board->machine_id;
+
+		/* If the user has not set fdtimage, set the default */
+		if (!getenv("fdtimage"))
+			setenv("fdtimage", board->fdtfile);
 	}
 
 	/* restore hsusb0_data5 pin as hsusb0_data5 */
 	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0));
-
-	return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
-	switch (gd->bd->bi_arch_number) {
-	case MACH_TYPE_DM3730_TORPEDO:
-		setenv("fdtimage", "logicpd-torpedo-37xx-devkit.dtb");
-		break;
-	case MACH_TYPE_DM3730_SOM_LV:
-		setenv("fdtimage", "logicpd-som-lv-37xx-devkit.dtb");
-		break;
-	case MACH_TYPE_OMAP3_TORPEDO:
-		setenv("fdtimage", "logicpd-torpedo-35xx-devkit.dtb");
-		break;
-	case MACH_TYPE_OMAP3530_LV_SOM:
-		setenv("fdtimage", "logicpd-som-lv-35xx-devkit.dtb");
-		break;
-	default:
-		/* unknown machine type */
-		break;
-	}
 	return 0;
 }
 #endif
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
 }
 #endif
 
-#if defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 void board_mmc_power_init(void)
 {
 	twl4030_power_mmc_init(0);
@@ -331,7 +320,7 @@ void set_muxconf_regs(void)
 	MUX_VAL(CP(SDRC_DQS2), (IEN  | PTD | DIS | M0)); /*SDRC_DQS2*/
 	MUX_VAL(CP(SDRC_DQS3), (IEN  | PTD | DIS | M0)); /*SDRC_DQS3*/
 	MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN  | M0)); /*SDRC_CKE0*/
-	MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
+	MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)); /*SDRC_CKE1*/
 
 	MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN  | M0)); /*GPMC_A1*/
 	MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN  | M0)); /*GPMC_A2*/
diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c
index 2821ee2..e91f874 100644
--- a/board/logicpd/zoom1/zoom1.c
+++ b/board/logicpd/zoom1/zoom1.c
@@ -47,7 +47,8 @@ static const u32 gpmc_lab_enet[] = {
 static const struct ns16550_platdata zoom1_serial = {
 	.base = OMAP34XX_UART3,
 	.reg_shift = 2,
-	.clock = V_NS16550_CLK
+	.clock = V_NS16550_CLK,
+	.fcr = UART_FCR_DEFVAL,
 };
 
 U_BOOT_DEVICE(zoom1_uart) = {
@@ -105,7 +106,7 @@ void set_muxconf_regs(void)
 	MUX_ZOOM1_MDK();
 }
 
-#ifdef CONFIG_GENERIC_MMC
+#ifdef CONFIG_MMC
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/micronas/vct/dcgu.c b/board/micronas/vct/dcgu.c
index 20ee3ac..562c827 100644
--- a/board/micronas/vct/dcgu.c
+++ b/board/micronas/vct/dcgu.c
@@ -8,7 +8,7 @@
  */
 
 #include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 
 #include "vct.h"
 
diff --git a/board/micronas/vct/scc.c b/board/micronas/vct/scc.c
index 40f8ecd..0d33cc4 100644
--- a/board/micronas/vct/scc.c
+++ b/board/micronas/vct/scc.c
@@ -7,7 +7,7 @@
  */
 
 #include <common.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 
 #include "vct.h"
 
diff --git a/board/micronas/vct/vct.c b/board/micronas/vct/vct.c
index 0745cee..8bf8d5f 100644
--- a/board/micronas/vct/vct.c
+++ b/board/micronas/vct/vct.c
@@ -28,6 +28,8 @@
 #define BOARD_NAME_ADD	" NOR"
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int board_early_init_f(void)
 {
 	/*
@@ -59,10 +61,12 @@ void _machine_restart(void)
  * SDRAM is already configured by the bootstrap code, only return the
  * auto-detected size here
  */
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
-	return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 			    CONFIG_SYS_MBYTES_SDRAM << 20);
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/mini-box/picosam9g45/picosam9g45.c b/board/mini-box/picosam9g45/picosam9g45.c
index 32ba9c6..09ec247 100644
--- a/board/mini-box/picosam9g45/picosam9g45.c
+++ b/board/mini-box/picosam9g45/picosam9g45.c
@@ -27,6 +27,7 @@
 #include <net.h>
 #endif
 #include <netdev.h>
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -283,7 +284,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
@@ -291,6 +292,8 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 	gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
 							PHYS_SDRAM_2_SIZE);
+
+	return 0;
 }
 
 #ifdef CONFIG_RESET_PHY_R
diff --git a/board/mosaixtech/icon/Kconfig b/board/mosaixtech/icon/Kconfig
deleted file mode 100644
index 3145a06..0000000
--- a/board/mosaixtech/icon/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_ICON
-
-config SYS_BOARD
-	default "icon"
-
-config SYS_VENDOR
-	default "mosaixtech"
-
-config SYS_CONFIG_NAME
-	default "icon"
-
-endif
diff --git a/board/mosaixtech/icon/MAINTAINERS b/board/mosaixtech/icon/MAINTAINERS
deleted file mode 100644
index f3af072..0000000
--- a/board/mosaixtech/icon/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-ICON BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/mosaixtech/icon/
-F:	include/configs/icon.h
-F:	configs/icon_defconfig
diff --git a/board/mosaixtech/icon/Makefile b/board/mosaixtech/icon/Makefile
deleted file mode 100644
index d554a8b..0000000
--- a/board/mosaixtech/icon/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2009-2010
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= icon.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-extra-y	+= init.o
diff --git a/board/mosaixtech/icon/chip_config.c b/board/mosaixtech/icon/chip_config.c
deleted file mode 100644
index 3c5706f..0000000
--- a/board/mosaixtech/icon/chip_config.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2009-2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-struct ppc4xx_config ppc4xx_config_val[] = {
-	{
-		"400-133", "CPU: 400 PLB: 133 OPB:  66 EBC:  66",
-		{ 0x86, 0x78, 0xc2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
-	},
-	{
-		"500-166", "CPU: 500 PLB: 166 OPB:  83 EBC:  83",
-		{ 0x87, 0x78, 0xf2, 0xc6, 0x05, 0xa5, 0x04, 0xe1 }
-	},
-	{
-		"533-133", "CPU: 533 PLB: 133 OPB:  66 EBC:  66",
-		{ 0x87, 0x79, 0x02, 0x52, 0x05, 0xa5, 0x04, 0xe1 }
-	},
-	{
-		"667-133", "CPU: 667 PLB: 133 OPB:  66 EBC:  66",
-		{ 0x87, 0x79, 0x42, 0x56, 0x05, 0xa5, 0x04, 0xe1 }
-	},
-	{
-		"667-166", "CPU: 667 PLB: 166 OPB:  83 EBC:  83",
-		{ 0x87, 0x79, 0x42, 0x06, 0x05, 0xa5, 0x04, 0xe1 }
-	},
-	{
-		"800-160", "CPU: 800 PLB: 160 OPB:  53 EBC:  17",
-		{ 0x86, 0x79, 0x81, 0xa7, 0x07, 0xa5, 0x04, 0xe1 }
-	},
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/mosaixtech/icon/config.mk b/board/mosaixtech/icon/config.mk
deleted file mode 100644
index b689fd0..0000000
--- a/board/mosaixtech/icon/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2009-2010
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/mosaixtech/icon/icon.c b/board/mosaixtech/icon/icon.c
deleted file mode 100644
index e3fb1e6..0000000
--- a/board/mosaixtech/icon/icon.c
+++ /dev/null
@@ -1,372 +0,0 @@
-/*
- * (C) Copyright 2009-2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <i2c.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <netdev.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/4xx_pcie.h>
-#include <asm/errno.h>
-#include <asm/mmu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	unsigned long mfr;
-
-	/*
-	 * Interrupt controller setup for the ICON 440SPe board.
-	 *
-	 *--------------------------------------------------------------------
-	 * IRQ    | Source                            | Pol.  | Sensi.| Crit.
-	 *--------+-----------------------------------+-------+-------+-------
-	 * IRQ 00 | UART0                             | High  | Level | Non
-	 * IRQ 01 | UART1                             | High  | Level | Non
-	 * IRQ 02 | IIC0                              | High  | Level | Non
-	 * IRQ 03 | IIC1                              | High  | Level | Non
-	 * IRQ 04 | PCI0X0 MSG IN                     | High  | Level | Non
-	 * IRQ 05 | PCI0X0 CMD Write                  | High  | Level | Non
-	 * IRQ 06 | PCI0X0 Power Mgt                  | High  | Level | Non
-	 * IRQ 07 | PCI0X0 VPD Access                 | Rising| Edge  | Non
-	 * IRQ 08 | PCI0X0 MSI level 0                | High  | Lvl/ed| Non
-	 * IRQ 09 | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non
-	 * IRQ 10 | UIC2 Non-critical Int.            | NA    | NA    | Non
-	 * IRQ 11 | UIC2 Critical Interrupt           | NA    | NA    | Crit
-	 * IRQ 12 | PCI Express MSI Level 0           | Rising| Edge  | Non
-	 * IRQ 13 | PCI Express MSI Level 1           | Rising| Edge  | Non
-	 * IRQ 14 | PCI Express MSI Level 2           | Rising| Edge  | Non
-	 * IRQ 15 | PCI Express MSI Level 3           | Rising| Edge  | Non
-	 * IRQ 16 | UIC3 Non-critical Int.            | NA    | NA    | Non
-	 * IRQ 17 | UIC3 Critical Interrupt           | NA    | NA    | Crit
-	 * IRQ 18 | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non
-	 * IRQ 19 | DMA Channel 0 FIFO Full           | High  | Level | Non
-	 * IRQ 20 | DMA Channel 0 Stat FIFO           | High  | Level | Non
-	 * IRQ 21 | DMA Channel 1 FIFO Full           | High  | Level | Non
-	 * IRQ 22 | DMA Channel 1 Stat FIFO           | High  | Level | Non
-	 * IRQ 23 | I2O Inbound Doorbell              | High  | Level | Non
-	 * IRQ 24 | Inbound Post List FIFO Not Empt   | High  | Level | Non
-	 * IRQ 25 | I2O Region 0 LL PLB Write         | High  | Level | Non
-	 * IRQ 26 | I2O Region 1 LL PLB Write         | High  | Level | Non
-	 * IRQ 27 | I2O Region 0 HB PLB Write         | High  | Level | Non
-	 * IRQ 28 | I2O Region 1 HB PLB Write         | High  | Level | Non
-	 * IRQ 29 | GPT Down Count Timer              | Rising| Edge  | Non
-	 * IRQ 30 | UIC1 Non-critical Int.            | NA    | NA    | Non
-	 * IRQ 31 | UIC1 Critical Interrupt           | NA    | NA    | Crit.
-	 *--------------------------------------------------------------------
-	 * IRQ 32 | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non
-	 * IRQ 33 | MAL Serr                          | High  | Level | Non
-	 * IRQ 34 | MAL Txde                          | High  | Level | Non
-	 * IRQ 35 | MAL Rxde                          | High  | Level | Non
-	 * IRQ 36 | DMC CE or DMC UE                  | High  | Level | Non
-	 * IRQ 37 | EBC or UART2                      | High  |Lvl Edg| Non
-	 * IRQ 38 | MAL TX EOB                        | High  | Level | Non
-	 * IRQ 39 | MAL RX EOB                        | High  | Level | Non
-	 * IRQ 40 | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non
-	 * IRQ 41 | PCIX0 MSI level 2                 | High  |Lvl Edg| Non
-	 * IRQ 42 | PCIX0 MSI level 3                 | High  |Lvl Edg| Non
-	 * IRQ 43 | L2 Cache                          | Risin | Edge  | Non
-	 * IRQ 44 | GPT Compare Timer 0               | Risin | Edge  | Non
-	 * IRQ 45 | GPT Compare Timer 1               | Risin | Edge  | Non
-	 * IRQ 46 | GPT Compare Timer 2               | Risin | Edge  | Non
-	 * IRQ 47 | GPT Compare Timer 3               | Risin | Edge  | Non
-	 * IRQ 48 | GPT Compare Timer 4               | Risin | Edge  | Non
-	 * IRQ 49 | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non
-	 * IRQ 50 | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non
-	 * IRQ 51 | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non
-	 * IRQ 52 | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non
-	 * IRQ 53 | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non
-	 * IRQ 54 | DMA Error                         | High  | Level | Non
-	 * IRQ 55 | DMA I2O Error                     | High  | Level | Non
-	 * IRQ 56 | Serial ROM                        | High  | Level | Non
-	 * IRQ 57 | PCIX0 Error                       | High  | Edge  | Non
-	 * IRQ 58 | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non
-	 * IRQ 59 | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non
-	 * IRQ 60 | EMAC0 Interrupt                   | High  | Level | Non
-	 * IRQ 61 | EMAC0 Wake-up                     | High  | Level | Non
-	 * IRQ 62 | Reserved                          | High  | Level | Non
-	 * IRQ 63 | XOR                               | High  | Level | Non
-	 *--------------------------------------------------------------------
-	 * IRQ 64 | PE0 AL                            | High  | Level | Non
-	 * IRQ 65 | PE0 VPD Access                    | Risin | Edge  | Non
-	 * IRQ 66 | PE0 Hot Reset Request             | Risin | Edge  | Non
-	 * IRQ 67 | PE0 Hot Reset Request             | Falli | Edge  | Non
-	 * IRQ 68 | PE0 TCR                           | High  | Level | Non
-	 * IRQ 69 | PE0 BusMaster VCO                 | Falli | Edge  | Non
-	 * IRQ 70 | PE0 DCR Error                     | High  | Level | Non
-	 * IRQ 71 | Reserved                          | N/A   | N/A   | Non
-	 * IRQ 72 | PE1 AL                            | High  | Level | Non
-	 * IRQ 73 | PE1 VPD Access                    | Risin | Edge  | Non
-	 * IRQ 74 | PE1 Hot Reset Request             | Risin | Edge  | Non
-	 * IRQ 75 | PE1 Hot Reset Request             | Falli | Edge  | Non
-	 * IRQ 76 | PE1 TCR                           | High  | Level | Non
-	 * IRQ 77 | PE1 BusMaster VCO                 | Falli | Edge  | Non
-	 * IRQ 78 | PE1 DCR Error                     | High  | Level | Non
-	 * IRQ 79 | Reserved                          | N/A   | N/A   | Non
-	 * IRQ 80 | PE2 AL                            | High  | Level | Non
-	 * IRQ 81 | PE2 VPD Access                    | Risin | Edge  | Non
-	 * IRQ 82 | PE2 Hot Reset Request             | Risin | Edge  | Non
-	 * IRQ 83 | PE2 Hot Reset Request             | Falli | Edge  | Non
-	 * IRQ 84 | PE2 TCR                           | High  | Level | Non
-	 * IRQ 85 | PE2 BusMaster VCO                 | Falli | Edge  | Non
-	 * IRQ 86 | PE2 DCR Error                     | High  | Level | Non
-	 * IRQ 87 | Reserved                          | N/A   | N/A   | Non
-	 * IRQ 88 | External IRQ(5)                   | Progr | Progr | Non
-	 * IRQ 89 | External IRQ 4 - Ethernet         | Progr | Progr | Non
-	 * IRQ 90 | External IRQ 3 - PCI-X            | Progr | Progr | Non
-	 * IRQ 91 | External IRQ 2 - PCI-X            | Progr | Progr | Non
-	 * IRQ 92 | External IRQ 1 - PCI-X            | Progr | Progr | Non
-	 * IRQ 93 | External IRQ 0 - PCI-X            | Progr | Progr | Non
-	 * IRQ 94 | Reserved                          | N/A   | N/A   | Non
-	 * IRQ 95 | Reserved                          | N/A   | N/A   | Non
-	 *--------------------------------------------------------------------
-	 * IRQ 96 | PE0 INTA                          | High  | Level | Non
-	 * IRQ 97 | PE0 INTB                          | High  | Level | Non
-	 * IRQ 98 | PE0 INTC                          | High  | Level | Non
-	 * IRQ 99 | PE0 INTD                          | High  | Level | Non
-	 * IRQ 100| PE1 INTA                          | High  | Level | Non
-	 * IRQ 101| PE1 INTB                          | High  | Level | Non
-	 * IRQ 102| PE1 INTC                          | High  | Level | Non
-	 * IRQ 103| PE1 INTD                          | High  | Level | Non
-	 * IRQ 104| PE2 INTA                          | High  | Level | Non
-	 * IRQ 105| PE2 INTB                          | High  | Level | Non
-	 * IRQ 106| PE2 INTC                          | High  | Level | Non
-	 * IRQ 107| PE2 INTD                          | Risin | Edge  | Non
-	 * IRQ 108| PCI Express MSI Level 4           | Risin | Edge  | Non
-	 * IRQ 109| PCI Express MSI Level 5           | Risin | Edge  | Non
-	 * IRQ 110| PCI Express MSI Level 6           | Risin | Edge  | Non
-	 * IRQ 111| PCI Express MSI Level 7           | Risin | Edge  | Non
-	 * IRQ 116| PCI Express MSI Level 12          | Risin | Edge  | Non
-	 * IRQ 112| PCI Express MSI Level 8           | Risin | Edge  | Non
-	 * IRQ 113| PCI Express MSI Level 9           | Risin | Edge  | Non
-	 * IRQ 114| PCI Express MSI Level 10          | Risin | Edge  | Non
-	 * IRQ 115| PCI Express MSI Level 11          | Risin | Edge  | Non
-	 * IRQ 117| PCI Express MSI Level 13          | Risin | Edge  | Non
-	 * IRQ 118| PCI Express MSI Level 14          | Risin | Edge  | Non
-	 * IRQ 119| PCI Express MSI Level 15          | Risin | Edge  | Non
-	 * IRQ 120| PCI Express MSI Level 16          | Risin | Edge  | Non
-	 * IRQ 121| PCI Express MSI Level 17          | Risin | Edge  | Non
-	 * IRQ 122| PCI Express MSI Level 18          | Risin | Edge  | Non
-	 * IRQ 123| PCI Express MSI Level 19          | Risin | Edge  | Non
-	 * IRQ 124| PCI Express MSI Level 20          | Risin | Edge  | Non
-	 * IRQ 125| PCI Express MSI Level 21          | Risin | Edge  | Non
-	 * IRQ 126| PCI Express MSI Level 22          | Risin | Edge  | Non
-	 * IRQ 127| PCI Express MSI Level 23          | Risin | Edge  | Non
-	 */
-
-	/*
-	 * Put UICs in PowerPC 440SPe mode.
-	 * Initialise UIC registers. Clear all interrupts. Disable all
-	 * interrupts. Set critical interrupt values. Set interrupt polarities.
-	 * Set interrupt trigger levels. Make bit 0 High priority. Clear all
-	 * interrupts again.
-	 */
-	mtdcr(UIC3SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr(UIC3ER, 0x00000000);	/* disable all interrupts */
-	mtdcr(UIC3CR, 0x00000000);	/* Set Critical / Non Critical IRQs */
-	mtdcr(UIC3PR, 0xffffffff);	/* Set Interrupt Polarities*/
-	mtdcr(UIC3TR, 0x001fffff);	/* Set Interrupt Trigger Levels */
-	mtdcr(UIC3VR, 0x00000001);	/* Set Vect base=0,INT31 Highest prio */
-	mtdcr(UIC3SR, 0x00000000);	/* clear all  interrupts*/
-	mtdcr(UIC3SR, 0xffffffff);	/* clear all  interrupts*/
-
-	mtdcr(UIC2SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr(UIC2ER, 0x00000000);	/* disable all interrupts*/
-	mtdcr(UIC2CR, 0x00000000);	/* Set Critical / Non Critical IRQs */
-	mtdcr(UIC2PR, 0xebebebff);	/* Set Interrupt Polarities*/
-	mtdcr(UIC2TR, 0x74747400);	/* Set Interrupt Trigger Levels */
-	mtdcr(UIC2VR, 0x00000001);	/* Set Vect base=0,INT31 Highest prio */
-	mtdcr(UIC2SR, 0x00000000);	/* clear all interrupts */
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all interrupts */
-
-	mtdcr(UIC1SR, 0xffffffff);	/* Clear all interrupts*/
-	mtdcr(UIC1ER, 0x00000000);	/* disable all interrupts*/
-	mtdcr(UIC1CR, 0x00000000);	/* Set Critical / Non Critical IRQs */
-	mtdcr(UIC1PR, 0xffffffff);	/* Set Interrupt Polarities */
-	mtdcr(UIC1TR, 0x001f8040);	/* Set Interrupt Trigger Levels*/
-	mtdcr(UIC1VR, 0x00000001);	/* Set Vect base=0,INT31 Highest prio */
-	mtdcr(UIC1SR, 0x00000000);	/* clear all interrupts*/
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all interrupts*/
-
-	mtdcr(UIC0SR, 0xffffffff);	/* Clear all interrupts */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all int. excepted cascade */
-	mtdcr(UIC0CR, 0x00104001);	/* Set Critical / Non Critical IRQs */
-	mtdcr(UIC0PR, 0xffffffff);	/* Set Interrupt Polarities*/
-	mtdcr(UIC0TR, 0x010f0004);	/* Set Interrupt Trigger Levels */
-	mtdcr(UIC0VR, 0x00000001);	/* Set Vect base=0,INT31 Highest prio */
-	mtdcr(UIC0SR, 0x00000000);	/* clear all interrupts*/
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all interrupts*/
-
-	mfsdr(SDR0_MFR, mfr);
-	mfr |= SDR0_MFR_FIXD;		/* Workaround for PCI/DMA */
-	mtsdr(SDR0_MFR, mfr);
-
-	mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
-
-	out_be32((void *)GPIO0_OR, CONFIG_SYS_GPIO_OR);
-	out_be32((void *)GPIO0_ODR, CONFIG_SYS_GPIO_ODR);
-	out_be32((void *)GPIO0_TCR, CONFIG_SYS_GPIO_TCR);
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	/*
-	 * ICON has 64MBytes of NOR FLASH (Spansion 29GL512), but the
-	 * boot EBC mapping only supports a maximum of 16MBytes
-	 * (4.ff00.0000 - 4.ffff.ffff).
-	 * To solve this problem, the FLASH has to get remapped to another
-	 * EBC address which accepts bigger regions:
-	 *
-	 * 0xfc00.0000 -> 4.ec00.0000
-	 */
-
-	/* Remap the NOR FLASH to 0xec00.0000 ... 0xefff.ffff */
-	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
-
-	/* Remove TLB entry of boot EBC mapping */
-	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
-
-	/* Add TLB entry for 0xfc00.0000 -> 0x4.ec00.0000 */
-	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
-		    CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
-
-	/*
-	 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
-	 * 0xfc00.0000 is possible
-	 */
-
-	/*
-	 * Clear potential errors resulting from auto-calibration.
-	 * If not done, then we could get an interrupt later on when
-	 * exceptions are enabled.
-	 */
-	set_mcsr(get_mcsr());
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf("Board: ICON");
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-/*
- * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
- * board specific values.
- *
- * Tested successfully with the following SODIMM:
- * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
- *
- * Tests with Micron MT4HTF6464HZ-667H1 showed problems in "cold" state,
- * directly after power-up. Only after running for more than 10 minutes
- * real stable auto-calibration windows could be found.
- */
-u32 ddr_wrdtr(u32 default_val)
-{
-	return SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV;
-}
-
-u32 ddr_clktr(u32 default_val)
-{
-	return SDRAM_CLKTR_CLKP_180_DEG_ADV;
-}
-
-/*
- * Override the weak default implementation and return the
- * last PCIe slot number (max number - 1).
- */
-int board_pcie_last(void)
-{
-	/* Only 2 PCIe ports used on ICON, so the last one is 1 */
-	return 1;
-}
-
-/*
- * Video
- */
-#ifdef CONFIG_VIDEO_SM501
-#include <sm501.h>
-
-#define DISPLAY_WIDTH   640
-#define DISPLAY_HEIGHT  480
-
-static const SMI_REGS sm502_init_regs[] = {
-	{0x00004, 0x0},
-	{0x00040, 0x00021847},
-	{0x00044, 0x091a0a01}, /* 24 MHz pixclk */
-	{0x00054, 0x0},
-	{0x00048, 0x00021847},
-	{0x0004C, 0x091a0a01},
-	{0x00054, 0x1},
-	{0x80004, 0xc428bb17},
-	{0x8000C, 0x00000000},
-	{0x80010, 0x0a000a00},
-	{0x80014, 0x02800000},
-	{0x80018, 0x01e00000},
-	{0x8001C, 0x00000000},
-	{0x80020, 0x01e00280},
-	{0x80024, 0x02fa027f},
-	{0x80028, 0x004a0280},
-	{0x8002C, 0x020c01df},
-	{0x80030, 0x000201e7},
-	{0x80200, 0x00010000},
-	{0x00008, 0x20000000}, /* gpio29 is pwm0, LED_PWM */
-	{0x0000C, 0x3f000000}, /* gpio56 - gpio61 as flat panel data pins */
-	{0x10020, 0x25725728}, /* 20 kHz pwm0, 50 % duty cycle, disabled */
-	{0x80000, 0x0f010106}, /* vsync & hsync pos, disp on */
-	{0, 0}
-};
-
-/*
- * Return a pointer to the register initialization table.
- */
-const SMI_REGS *board_get_regs(void)
-{
-	return sm502_init_regs;
-}
-
-int board_get_width(void)
-{
-	return DISPLAY_WIDTH;
-}
-
-int board_get_height(void)
-{
-	return DISPLAY_HEIGHT;
-}
-
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str(int line_number, char *info)
-{
-	if (line_number == 1)
-		strcpy(info, " Board: ICON");
-	else
-		info[0] = '\0';
-}
-#endif
-
-#endif /* CONFIG_VIDEO_SM501 */
diff --git a/board/mosaixtech/icon/init.S b/board/mosaixtech/icon/init.S
deleted file mode 100644
index c28a3a3..0000000
--- a/board/mosaixtech/icon/init.S
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * (C) Copyright 2009-2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-
-/*
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- */
-
-	.section .bootpg,"ax"
-
-	.globl tlbtab
-tlbtab:
-	tlbtab_start
-
-	/*
-	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
-	 * use the speed up boot process. It is patched after relocation to
-	 * enable SA_I.
-	 */
-	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
-		 4, AC_RWX | SA_G) /* TLB 0 */
-
-	/*
-	 * TLB entries for SDRAM are not needed on this platform.
-	 * They are dynamically generated in the SPD DDR(2) detection
-	 * routine.
-	 */
-
-	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4,
-		 AC_RWX | SA_I)
-
-	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4,
-		 AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K,
-		 CONFIG_SYS_ACE_BASE_PHYS_L, CONFIG_SYS_ACE_BASE_PHYS_H,
-		 AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD,
-		 AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD,
-		 AC_RW | SA_IG)
-	tlbtab_end
diff --git a/board/motionpro/Kconfig b/board/motionpro/Kconfig
deleted file mode 100644
index f624f6c..0000000
--- a/board/motionpro/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MOTIONPRO
-
-config SYS_BOARD
-	default "motionpro"
-
-config SYS_CONFIG_NAME
-	default "motionpro"
-
-endif
diff --git a/board/motionpro/MAINTAINERS b/board/motionpro/MAINTAINERS
deleted file mode 100644
index 2f8b5cb..0000000
--- a/board/motionpro/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MOTIONPRO BOARD
-#M:	-
-S:	Maintained
-F:	board/motionpro/
-F:	include/configs/motionpro.h
-F:	configs/motionpro_defconfig
diff --git a/board/motionpro/Makefile b/board/motionpro/Makefile
deleted file mode 100644
index 898a384..0000000
--- a/board/motionpro/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= motionpro.o
diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
deleted file mode 100644
index dc237c1..0000000
--- a/board/motionpro/motionpro.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * (C) Copyright 2003-2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * modified for Promess PRO - by Andy Joseph, andy@promessdev.com
- * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com
- * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3
- * Also changed the refresh for 100MHz operation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <miiphy.h>
-#include <libfdt.h>
-
-#if defined(CONFIG_STATUS_LED)
-#include <status_led.h>
-#endif /* CONFIG_STATUS_LED */
-
-/* Kollmorgen DPR initialization data */
-struct init_elem {
-	unsigned long addr;
-	unsigned len;
-	char *data;
-	} init_seq[] = {
-		{0x500003F2, 2, "\x86\x00"},		/* HW parameter */
-		{0x500003F0, 2, "\x00\x00"},
-		{0x500003EC, 4, "\x00\x80\xc1\x52"},	/* Magic word */
-	};
-
-/*
- * Initialize Kollmorgen DPR
- */
-static void kollmorgen_init(void)
-{
-	unsigned i, j;
-	vu_char *p;
-
-	for (i = 0; i < sizeof(init_seq) / sizeof(struct init_elem); ++i) {
-		p = (vu_char *)init_seq[i].addr;
-		for (j = 0; j < init_seq[i].len; ++j)
-			*(p + j) = *(init_seq[i].data + j);
-	}
-
-	printf("DPR:   Kollmorgen DPR initialized\n");
-}
-
-
-/*
- * Early board initalization.
- */
-int board_early_init_r(void)
-{
-	/* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */
-	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25);
-	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16);
-
-	/* Initialize Kollmorgen DPR */
-	kollmorgen_init();
-
-	return 0;
-}
-
-
-/*
- * Additional PHY intialization. After being reset in mpc5xxx_fec_init_phy(),
- * PHY goes into FX mode.  To take it out of the FX mode and switch into
- * desired TX operation, one needs to clear the FX_SEL bit of Mode Control
- * Register.
- */
-void reset_phy(void)
-{
-	unsigned short mode_control;
-
-	miiphy_read("FEC", CONFIG_PHY_ADDR, 0x15, &mode_control);
-	miiphy_write("FEC", CONFIG_PHY_ADDR, 0x15,
-			mode_control & 0xfffe);
-	return;
-}
-
-#ifndef CONFIG_SYS_RAMBOOT
-/*
- * Helper function to initialize SDRAM controller.
- */
-static void sdram_start(int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
-						hi_addr_bit;
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
-						hi_addr_bit;
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
-						hi_addr_bit;
-
-	/* auto refresh, second time */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
-						hi_addr_bit;
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-}
-#endif /* !CONFIG_SYS_RAMBOOT */
-
-
-/*
- * Initalize SDRAM - configure SDRAM controller, detect memory size.
- */
-phys_size_t initdram(int board_type)
-{
-	ulong dramsize = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* According to AN3221 (MPC5200B SDRAM Initialization and
-	 * Configuration), the SDelay register must be written a value of
-	 * 0x00000004 as the first step of the SDRAM contorller configuration.
-	 */
-	*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
-
-	/* configure SDRAM start/end for detection */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
-			__builtin_ffs(dramsize >> 20) - 1;
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 and disable it */
-	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;
-
-#else /* !CONFIG_SYS_RAMBOOT */
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/* return total ram size */
-	return dramsize;
-}
-
-
-int checkboard(void)
-{
-	uchar rev = *(vu_char *)CPLD_REV_REGISTER;
-	printf("Board: Promess Motion-PRO board (CPLD rev. 0x%02x)\n", rev);
-	return 0;
-}
-
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-
-#if defined(CONFIG_STATUS_LED)
-void __led_init(led_id_t regaddr, int state)
-{
-	*((vu_long *) regaddr) |= ENABLE_GPIO_OUT;
-
-	if (state == STATUS_LED_ON)
-		*((vu_long *) regaddr) |= LED_ON;
-	else
-		*((vu_long *) regaddr) &= ~LED_ON;
-}
-
-void __led_set(led_id_t regaddr, int state)
-{
-	if (state == STATUS_LED_ON)
-		*((vu_long *) regaddr) |= LED_ON;
-	else
-		*((vu_long *) regaddr) &= ~LED_ON;
-}
-
-void __led_toggle(led_id_t regaddr)
-{
-	*((vu_long *) regaddr) ^= LED_ON;
-}
-#endif /* CONFIG_STATUS_LED */
diff --git a/board/mpc8308_p1m/mpc8308_p1m.c b/board/mpc8308_p1m/mpc8308_p1m.c
index 688cc12..234a387 100644
--- a/board/mpc8308_p1m/mpc8308_p1m.c
+++ b/board/mpc8308_p1m/mpc8308_p1m.c
@@ -65,7 +65,7 @@ void pci_init_board(void)
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 
 	return 0;
 }
diff --git a/board/mpc8308_p1m/sdram.c b/board/mpc8308_p1m/sdram.c
index da36f63..05c477d 100644
--- a/board/mpc8308_p1m/sdram.c
+++ b/board/mpc8308_p1m/sdram.c
@@ -61,7 +61,7 @@ static long fixed_sdram(void)
 	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;
@@ -72,6 +72,8 @@ phys_size_t initdram(int board_type)
 	/* DDR SDRAM */
 	msize = fixed_sdram();
 
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize;
+
+	return 0;
 }
diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
deleted file mode 100644
index 2262175..0000000
--- a/board/mpl/common/common_util.c
+++ /dev/null
@@ -1,757 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <video_fb.h>
-#include "common_util.h"
-#include <asm/processor.h>
-#include <asm/byteorder.h>
-#include <i2c.h>
-#include <pci.h>
-#include <malloc.h>
-#include <bzlib.h>
-
-#ifdef CONFIG_PIP405
-#include "../pip405/pip405.h"
-#include <asm/4xx_pci.h>
-#endif
-#ifdef CONFIG_MIP405
-#include "../mip405/mip405.h"
-#include <asm/4xx_pci.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_PATI)
-#define FIRM_START 0xFFF00000
-#endif
-
-extern int mem_test(ulong start, ulong ramsize, int quiet);
-
-#define I2C_BACKUP_ADDR 0x7C00		/* 0x200 bytes for backup */
-#define IMAGE_SIZE CONFIG_SYS_MONITOR_LEN	/* ugly, but it works for now */
-
-#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
-/*-----------------------------------------------------------------------
- * On PIP/MIP405 we have 3 (4) possible boot mode
- *
- * - Boot from Flash (Flash CS = CS0, MPS CS = CS1)
- * - Boot from MPS   (Flash CS = CS1, MPS CS = CS0)
- * - Boot from PCI with Flash map (Flash CS = CS0, MPS CS = CS1)
- * - Boot from PCI with MPS map   (Flash CS = CS1, MPS CS = CS0)
- * The flash init is the first board specific routine which is called
- * after code relocation (running from SDRAM)
- * The first thing we do is to map the Flash CS to the Flash area and
- * the MPS CS to the MPS area. Since the flash size is unknown at this
- * point, we use the max flash size and the lowest flash address as base.
- *
- * After flash detection we adjust the size of the CS area accordingly.
- * update_flash_size() will fix in wrong values in the flash_info structure,
- * misc_init_r() will fix the values in the board info structure
- */
-int get_boot_mode(void)
-{
-	unsigned long pbcr;
-	int res = 0;
-	pbcr = mfdcr(CPC0_PSR);
-	if ((pbcr & PSR_ROM_WIDTH_MASK) == 0)
-		/* boot via MPS or MPS mapping */
-		res = BOOT_MPS;
-	if (pbcr & PSR_ROM_LOC)
-		/* boot via PCI.. */
-		res |= BOOT_PCI;
-	 return res;
-}
-
-/* Map the flash high (in boot area)
-   This code can only be executed from SDRAM (after relocation).
-*/
-void setup_cs_reloc(void)
-{
-	int mode;
-	/*
-	 * since we are relocated, we can set-up the CS finaly
-	 * but first of all, switch off PCI mapping (in case it
-	 * was a PCI boot)
-	 */
-	out32r(PMM0MA, 0L);
-	/* get boot mode */
-	mode = get_boot_mode();
-	/*
-	 * we map the flash high in every case
-	 * first find out to which CS the flash is attached to
-	 */
-	if (mode & BOOT_MPS) {
-		/* map flash high on CS1 and MPS on CS0 */
-		mtdcr(EBC0_CFGADDR, PB0AP);
-		mtdcr(EBC0_CFGDATA, MPS_AP);
-		mtdcr(EBC0_CFGADDR, PB0CR);
-		mtdcr(EBC0_CFGDATA, MPS_CR);
-		/*
-		 * we use the default values (max values) for the flash
-		 * because its real size is not yet known
-		 */
-		mtdcr(EBC0_CFGADDR, PB1AP);
-		mtdcr(EBC0_CFGDATA, FLASH_AP);
-		mtdcr(EBC0_CFGADDR, PB1CR);
-		mtdcr(EBC0_CFGDATA, FLASH_CR_B);
-	} else {
-		/* map flash high on CS0 and MPS on CS1 */
-		mtdcr(EBC0_CFGADDR, PB1AP);
-		mtdcr(EBC0_CFGDATA, MPS_AP);
-		mtdcr(EBC0_CFGADDR, PB1CR);
-		mtdcr(EBC0_CFGDATA, MPS_CR);
-		/*
-		 * we use the default values (max values) for the flash
-		 * because its real size is not yet known
-		 */
-		mtdcr(EBC0_CFGADDR, PB0AP);
-		mtdcr(EBC0_CFGDATA, FLASH_AP);
-		mtdcr(EBC0_CFGADDR, PB0CR);
-		mtdcr(EBC0_CFGDATA, FLASH_CR_B);
-	}
-}
-#endif /* #if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) */
-
-#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
-/* adjust flash start and protection info */
-int update_flash_size(int flash_size)
-{
-	int i = 0, mode;
-	flash_info_t *info = &flash_info[0];
-	unsigned long flashcr;
-	unsigned long flash_base = (0 - flash_size) & 0xFFF00000;
-
-	if (flash_size > 128*1024*1024) {
-		printf("\n ### ERROR, wrong flash size: %X, reset board ###\n",
-		       flash_size);
-		hang();
-	}
-
-	if ((flash_size >> 20) != 0)
-		i = __ilog2(flash_size >> 20);
-
-	/* set up flash CS according to the size */
-	mode = get_boot_mode();
-	if (mode & BOOT_MPS) {
-		/* flash is on CS1 */
-		mtdcr(EBC0_CFGADDR, PB1CR);
-		flashcr = mfdcr(EBC0_CFGDATA);
-		/* we map the flash high in every case */
-		flashcr &= 0x0001FFFF; /* mask out address bits */
-		flashcr |= flash_base; /* start addr */
-		flashcr |= (i << 17); /* size addr */
-		mtdcr(EBC0_CFGADDR, PB1CR);
-		mtdcr(EBC0_CFGDATA, flashcr);
-	} else {
-		/* flash is on CS0 */
-		mtdcr(EBC0_CFGADDR, PB0CR);
-		flashcr = mfdcr(EBC0_CFGDATA);
-		/* we map the flash high in every case */
-		flashcr &= 0x0001FFFF; /* mask out address bits */
-		flashcr |= flash_base; /* start addr */
-		flashcr |= (i << 17); /* size addr */
-		mtdcr(EBC0_CFGADDR, PB0CR);
-		mtdcr(EBC0_CFGDATA, flashcr);
-	}
-
-	for (i = 0; i < info->sector_count; i++)
-		/* adjust sector start address */
-		info->start[i] = flash_base +
-				(info->start[i] - CONFIG_SYS_FLASH_BASE);
-
-	/* unprotect all sectors */
-	flash_protect(FLAG_PROTECT_CLEAR,
-		      info->start[0],
-		      0xFFFFFFFF,
-		      info);
-	flash_protect_default();
-	/* protect reset vector too*/
-	flash_protect(FLAG_PROTECT_SET,
-		      info->start[info->sector_count-1],
-		      0xFFFFFFFF,
-		      info);
-
-	return 0;
-}
-#endif
-
-static int
-mpl_prg(uchar *src, ulong size)
-{
-	ulong start;
-	flash_info_t *info = &flash_info[0];
-	int i, rc;
-#if defined(CONFIG_PATI)
-	int start_sect;
-#endif
-#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI)
-	char *copystr = (char *)src;
-	ulong *magic = (ulong *)src;
-#endif
-
-#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI)
-	if (uimage_to_cpu (magic[0]) != IH_MAGIC) {
-		puts("Bad Magic number\n");
-		return -1;
-	}
-	/* some more checks before we delete the Flash... */
-	/* Checking the ISO_STRING prevents to program a
-	 * wrong Firmware Image into the flash.
-	 */
-	i = 4; /* skip Magic number */
-	while (1) {
-		if (strncmp(&copystr[i], "MEV-", 4) == 0)
-			break;
-		if (i++ >= 0x100) {
-			puts("Firmware Image for unknown Target\n");
-			return -1;
-		}
-	}
-	/* we have the ISO STRING, check */
-	if (strncmp(&copystr[i], CONFIG_ISO_STRING, sizeof(CONFIG_ISO_STRING)-1) != 0) {
-		printf("Wrong Firmware Image: %s\n", &copystr[i]);
-		return -1;
-	}
-#if !defined(CONFIG_PATI)
-	start = 0 - size;
-
-	/* unprotect sectors used by u-boot */
-	flash_protect(FLAG_PROTECT_CLEAR,
-		      start,
-		      0xFFFFFFFF,
-		      info);
-
-	/* search start sector */
-	for (i = info->sector_count-1; i > 0; i--)
-		if (start >= info->start[i])
-			break;
-
-	/* now erase flash */
-	printf("Erasing at %lx (sector %d) (start %lx)\n",
-				start,i,info->start[i]);
-	if ((rc = flash_erase (info, i, info->sector_count-1)) != 0) {
-		puts("ERROR ");
-		flash_perror(rc);
-		return (1);
-	}
-
-#else /* #if !defined(CONFIG_PATI */
-	start = FIRM_START;
-	start_sect = -1;
-
-	/* search start sector */
-	for (i = info->sector_count-1; i > 0; i--)
-		if (start >= info->start[i])
-			break;
-
-	start_sect = i;
-
-	for (i = info->sector_count-1; i > 0; i--)
-		if ((start + size) >= info->start[i])
-			break;
-
-	/* unprotect sectors used by u-boot */
-	flash_protect(FLAG_PROTECT_CLEAR,
-		      start,
-		      start + size,
-		      info);
-
-	/* now erase flash */
-	printf ("Erasing at %lx to %lx (sector %d to %d) (%lx to %lx)\n",
-		start, start + size, start_sect, i,
-		info->start[start_sect], info->start[i]);
-	if ((rc = flash_erase (info, start_sect, i)) != 0) {
-		puts ("ERROR ");
-		flash_perror (rc);
-		return (1);
-	}
-#endif /* defined(CONFIG_PATI) */
-
-#elif defined(CONFIG_VCMA9)
-	start = 0;
-
-	/* search end sector */
-	for (i = 0; i < info->sector_count; i++)
-		if (size < info->start[i])
-		    break;
-
-	flash_protect(FLAG_PROTECT_CLEAR,
-		      start,
-		      size,
-		      info);
-
-	/* now erase flash */
-	printf("Erasing at %lx (sector %d) (start %lx)\n",
-				start,0,info->start[0]);
-	if ((rc = flash_erase (info, 0, i)) != 0) {
-		puts("ERROR ");
-		flash_perror(rc);
-		return (1);
-	}
-
-#endif
-	printf("flash erased, programming from 0x%lx 0x%lx Bytes\n",
-		(ulong)src, size);
-	if ((rc = flash_write ((char *)src, start, size)) != 0) {
-		puts("ERROR ");
-		flash_perror(rc);
-		return (1);
-	}
-	puts("OK programming done\n");
-	return 0;
-}
-
-
-static int
-mpl_prg_image(uchar *ld_addr)
-{
-	unsigned long len;
-	uchar *data;
-	image_header_t *hdr = (image_header_t *)ld_addr;
-	int rc;
-
-#if defined(CONFIG_FIT)
-	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
-		puts ("Non legacy image format not supported\n");
-		return -1;
-	}
-#endif
-
-	if (!image_check_magic (hdr)) {
-		puts("Bad Magic Number\n");
-		return 1;
-	}
-	image_print_contents (hdr);
-	if (!image_check_os (hdr, IH_OS_U_BOOT)) {
-		puts("No U-Boot Image\n");
-		return 1;
-	}
-	if (!image_check_type (hdr, IH_TYPE_FIRMWARE)) {
-		puts("No Firmware Image\n");
-		return 1;
-	}
-	if (!image_check_hcrc (hdr)) {
-		puts("Bad Header Checksum\n");
-		return 1;
-	}
-	puts("Verifying Checksum ... ");
-	if (!image_check_dcrc (hdr)) {
-		puts("Bad Data CRC\n");
-		return 1;
-	}
-	puts("OK\n");
-
-	data = (uchar *)image_get_data (hdr);
-	len = image_get_data_size (hdr);
-
-	if (image_get_comp (hdr) != IH_COMP_NONE) {
-		uchar *buf;
-		/* reserve space for uncompressed image */
-		if ((buf = malloc(IMAGE_SIZE)) == NULL) {
-			puts("Insufficient space for decompression\n");
-			return 1;
-		}
-
-		switch (image_get_comp (hdr)) {
-		case IH_COMP_GZIP:
-			puts("Uncompressing (GZIP) ... ");
-			rc = gunzip ((void *)(buf), IMAGE_SIZE, data, &len);
-			if (rc != 0) {
-				puts("GUNZIP ERROR\n");
-				free(buf);
-				return 1;
-			}
-			puts("OK\n");
-			break;
-#ifdef CONFIG_BZIP2
-		case IH_COMP_BZIP2:
-			puts("Uncompressing (BZIP2) ... ");
-			{
-			uint retlen = IMAGE_SIZE;
-			rc = BZ2_bzBuffToBuffDecompress ((char *)(buf), &retlen,
-				(char *)data, len, 0, 0);
-			len = retlen;
-			}
-			if (rc != BZ_OK) {
-				printf ("BUNZIP2 ERROR: %d\n", rc);
-				free(buf);
-				return 1;
-			}
-			puts("OK\n");
-			break;
-#endif
-		default:
-			printf ("Unimplemented compression type %d\n",
-				image_get_comp (hdr));
-			free(buf);
-			return 1;
-		}
-
-		rc = mpl_prg(buf, len);
-		free(buf);
-	} else {
-		rc = mpl_prg(data, len);
-	}
-
-	return(rc);
-}
-
-#if !defined(CONFIG_PATI)
-void get_backup_values(backup_t *buf)
-{
-	i2c_read(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t));
-}
-
-void set_backup_values(int overwrite)
-{
-	backup_t back;
-	int i;
-
-	get_backup_values(&back);
-	if(!overwrite) {
-		if(strncmp(back.signature,"MPL\0",4)==0) {
-			puts("Not possible to write Backup\n");
-			return;
-		}
-	}
-	memcpy(back.signature,"MPL\0",4);
-	i = getenv_f("serial#",back.serial_name,16);
-	if(i < 0) {
-		puts("Not possible to write Backup\n");
-		return;
-	}
-	back.serial_name[16]=0;
-	i = getenv_f("ethaddr",back.eth_addr,20);
-	if(i < 0) {
-		puts("Not possible to write Backup\n");
-		return;
-	}
-	back.eth_addr[20]=0;
-	i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t));
-}
-
-void clear_env_values(void)
-{
-	backup_t back;
-	unsigned char env_crc[4];
-
-	memset(&back,0xff,sizeof(backup_t));
-	memset(env_crc,0x00,4);
-	i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR,I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t));
-	i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR,CONFIG_ENV_OFFSET,2,(void *)env_crc,4);
-}
-
-/*
- * check crc of "older" environment
- */
-int check_env_old_size(ulong oldsize)
-{
-	ulong crc, len, new;
-	unsigned off;
-	uchar buf[64];
-
-	/* read old CRC */
-	eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR,
-		     CONFIG_ENV_OFFSET,
-		     (uchar *)&crc, sizeof(ulong));
-
-	new = 0;
-	len = oldsize;
-	off = sizeof(long);
-	len = oldsize-off;
-	while (len > 0) {
-		int n = (len > sizeof(buf)) ? sizeof(buf) : len;
-
-		eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, buf, n);
-		new = crc32 (new, buf, n);
-		len -= n;
-		off += n;
-	}
-
-	return (crc == new);
-}
-
-static ulong oldsizes[] = {
-	0x200,
-	0x800,
-	0
-};
-
-void copy_old_env(ulong size)
-{
-	uchar name_buf[64];
-	uchar value_buf[0x800];
-	uchar c;
-	ulong len;
-	unsigned off;
-	uchar *name, *value;
-
-	name = &name_buf[0];
-	value = &value_buf[0];
-	len=size;
-	off = sizeof(long);
-	while (len > off) {
-		eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1);
-		if(c != '=') {
-			*name++=c;
-			off++;
-		}
-		else {
-			*name++='\0';
-			off++;
-			do {
-				eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1);
-				*value++=c;
-				off++;
-				if(c == '\0')
-					break;
-			} while(len > off);
-			name = &name_buf[0];
-			value = &value_buf[0];
-			if(strncmp((char *)name,"baudrate",8)!=0) {
-				setenv((char *)name,(char *)value);
-			}
-
-		}
-	}
-}
-
-
-void check_env(void)
-{
-	char *s;
-	int i=0;
-	char buf[32];
-	backup_t back;
-
-	s=getenv("serial#");
-	if(!s) {
-		while(oldsizes[i]) {
-			if(check_env_old_size(oldsizes[i]))
-				break;
-			i++;
-		}
-		if(!oldsizes[i]) {
-			/* no old environment has been found */
-			get_backup_values (&back);
-			if (strncmp (back.signature, "MPL\0", 4) == 0) {
-				sprintf (buf, "%s", back.serial_name);
-				setenv ("serial#", buf);
-				sprintf (buf, "%s", back.eth_addr);
-				setenv ("ethaddr", buf);
-				printf ("INFO:  serial# and ethaddr recovered, use saveenv\n");
-				return;
-			}
-		}
-		else {
-			copy_old_env(oldsizes[i]);
-			puts("INFO:  old environment ajusted, use saveenv\n");
-		}
-	}
-	else {
-		/* check if back up is set */
-		get_backup_values(&back);
-		if(strncmp(back.signature,"MPL\0",4)!=0) {
-			set_backup_values(0);
-		}
-	}
-}
-
-#endif /* #if !defined(CONFIG_PATI) */
-
-int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong ld_addr;
-	int result;
-#if !defined(CONFIG_PATI)
-	ulong size = IMAGE_SIZE;
-	ulong src = MULTI_PURPOSE_SOCKET_ADDR;
-	backup_t back;
-#endif
-
-	if (strcmp(argv[1], "flash") == 0)
-	{
-#if defined(CONFIG_CMD_FDC)
-		if (strcmp(argv[2], "floppy") == 0) {
-			char *local_args[3];
-			extern int do_fdcboot (cmd_tbl_t *, int, int, char *[]);
-			puts("\nupdating bootloader image from floppy\n");
-			local_args[0] = argv[0];
-			if(argc==4) {
-				local_args[1] = argv[3];
-				local_args[2] = NULL;
-				ld_addr=simple_strtoul(argv[3], NULL, 16);
-				result=do_fdcboot(cmdtp, 0, 2, local_args);
-			}
-			else {
-				local_args[1] = NULL;
-				ld_addr=CONFIG_SYS_LOAD_ADDR;
-				result=do_fdcboot(cmdtp, 0, 1, local_args);
-			}
-			result=mpl_prg_image((uchar *)ld_addr);
-			return result;
-		}
-#endif
-		if (strcmp(argv[2], "mem") == 0) {
-			if(argc==4) {
-				ld_addr=simple_strtoul(argv[3], NULL, 16);
-			}
-			else {
-				ld_addr=load_addr;
-			}
-			printf ("\nupdating bootloader image from memory at %lX\n",ld_addr);
-			result=mpl_prg_image((uchar *)ld_addr);
-			return result;
-		}
-#if !defined(CONFIG_PATI)
-		if (strcmp(argv[2], "mps") == 0) {
-			puts("\nupdating bootloader image from MPS\n");
-			result=mpl_prg((uchar *)src,size);
-			return result;
-		}
-#endif /* #if !defined(CONFIG_PATI)	*/
-	}
-#if !defined(CONFIG_PATI)
-	if (strcmp(argv[1], "clearenvvalues") == 0)
-	{
-		if (strcmp(argv[2], "yes") == 0)
-		{
-			clear_env_values();
-			return 0;
-		}
-	}
-	if (strcmp(argv[1], "getback") == 0) {
-		get_backup_values(&back);
-		back.signature[3]=0;
-		back.serial_name[16]=0;
-		back.eth_addr[20]=0;
-		printf("GetBackUp: signature: %s\n",back.signature);
-		printf("           serial#:   %s\n",back.serial_name);
-		printf("           ethaddr:   %s\n",back.eth_addr);
-		return 0;
-	}
-	if (strcmp(argv[1], "setback") == 0) {
-		set_backup_values(1);
-		return 0;
-	}
-#endif
-	return cmd_usage(cmdtp);
-}
-
-
-#if defined(CONFIG_CMD_DOC)
-void doc_init (void)
-{
-  doc_probe(MULTI_PURPOSE_SOCKET_ADDR);
-}
-#endif
-
-
-#ifdef CONFIG_VIDEO
-/******************************************************
- * Routines to display the Board information
- * to the screen (since the VGA will be initialized as last,
- * we must resend the infos)
- */
-
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-extern GraphicDevice ctfb;
-extern int get_boot_mode(void);
-
-void video_get_info_str (int line_number, char *info)
-{
-	/* init video info strings for graphic console */
-	PPC4xx_SYS_INFO sys_info;
-	char rev;
-	int i,boot;
-	unsigned long pvr;
-	char buf[64];
-	char buf1[32], buf2[32], buf3[32], buf4[32];
-	char cpustr[16];
-	char *s, *e, bc;
-	switch (line_number)
-	{
-	case 2:
-		/* CPU and board infos */
-		pvr=get_pvr();
-		get_sys_info (&sys_info);
-		switch (pvr) {
-			case PVR_405GP_RB: rev='B'; break;
-			case PVR_405GP_RC: rev='C'; break;
-			case PVR_405GP_RD: rev='D'; break;
-			case PVR_405GP_RE: rev='E'; break;
-			case PVR_405GPR_RB: rev='B'; break;
-			default:           rev='?'; break;
-		}
-		if(pvr==PVR_405GPR_RB)
-			sprintf(cpustr,"PPC405GPr %c",rev);
-		else
-			sprintf(cpustr,"PPC405GP %c",rev);
-		/* Board info */
-		i=0;
-		s=getenv ("serial#");
-#ifdef CONFIG_PIP405
-		if (!s || strncmp (s, "PIP405", 6)) {
-			strcpy(buf,"### No HW ID - assuming PIP405");
-		}
-#endif
-#ifdef CONFIG_MIP405
-		if (!s || strncmp (s, "MIP405", 6)) {
-			strcpy(buf,"### No HW ID - assuming MIP405");
-		}
-#endif
-		else {
-			for (e = s; *e; ++e) {
-				if (*e == ' ')
-					break;
-			}
-			for (; s < e; ++s) {
-				if (*s == '_') {
-					++s;
-					break;
-				}
-				buf[i++] = *s;
-			}
-			strcpy(&buf[i]," SN ");
-			i+=4;
-			for (; s < e; ++s) {
-				buf[i++] = *s;
-			}
-			buf[i++]=0;
-		}
-		sprintf (info," %s %s %s MHz (%s/%s/%s MHz)",
-			buf, cpustr,
-			strmhz (buf1, gd->cpu_clk),
-			strmhz (buf2, sys_info.freqPLB),
-			strmhz (buf3, sys_info.freqPLB / sys_info.pllOpbDiv),
-			strmhz (buf4, sys_info.freqPLB / sys_info.pllExtBusDiv));
-		return;
-	case 3:
-		/* Memory Info */
-		boot = get_boot_mode();
-		bc = in8 (CONFIG_PORT_ADDR);
-		sprintf(info, " %luMB RAM, %luMB Flash Cfg 0x%02X %s %s",
-			gd->bd->bi_memsize / 0x100000,
-			gd->bd->bi_flashsize / 0x100000,
-			bc,
-			(boot & BOOT_MPS) ? "MPS boot" : "Flash boot",
-			ctfb.modeIdent);
-		return;
-	case 1:
-		strcpy(buf, CONFIG_IDENT_STRING);
-		sprintf (info, " %s", &buf[1]);
-		return;
-    }
-    /* no more info lines */
-    *info = 0;
-    return;
-}
-#endif /* CONFIG_CONSOLE_EXTRA_INFO */
-
-#endif /* CONFIG_VIDEO */
diff --git a/board/mpl/common/common_util.h b/board/mpl/common/common_util.h
deleted file mode 100644
index e81ee35..0000000
--- a/board/mpl/common/common_util.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _COMMON_UTIL_H_
-#define _COMMON_UTIL_H_
-
-typedef struct {
-	char signature[4];
-	char serial_name[17];	/* "MIP405_1000xxxxx" */
-	char eth_addr[21];	/* "00:60:C2:0a:00:00" */
-} backup_t;
-
-extern flash_info_t flash_info[];	/* info for FLASH chips */
-
-void get_backup_values(backup_t *buf);
-
-#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
-#define BOOT_MPS	0x01
-#define BOOT_PCI	0x02
-int get_boot_mode(void);
-void setup_cs_reloc(void);
-#endif
-
-void check_env(void);
-#if defined(CONFIG_CMD_DOC)
-void doc_init (void);
-#endif
-
-#endif /* _COMMON_UTIL_H_ */
diff --git a/board/mpl/common/isa.c b/board/mpl/common/isa.c
deleted file mode 100644
index 54ec66b..0000000
--- a/board/mpl/common/isa.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * TODO: clean-up
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <stdio_dev.h>
-#include "isa.h"
-#include "piix4_pci.h"
-#include "kbd.h"
-#include "video.h"
-
-
-#undef	ISA_DEBUG
-
-#ifdef	ISA_DEBUG
-#define	PRINTF(fmt,args...)	printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-#if defined(CONFIG_PIP405)
-
-extern int drv_isa_kbd_init (void);
-
-/* fdc (logical device 0) */
-const SIO_LOGDEV_TABLE sio_fdc[] = {
-	{0x60, 3},			/* set IO to FDPort (3F0) */
-	{0x61, 0xF0},		/* set IO to FDPort (3F0) */
-	{0x70, 06},			/* set IRQ 6 for FDPort */
-	{0x74, 02},			/* set DMA 2 for FDPort */
-	{0xF0, 0x05},		/* set to PS2 type */
-	{0xF1, 0x00},	  /* default value */
-	{0x30, 1},			/* and activate the device */
-	{0xFF, 0}				/* end of device table */
-};
-/* paralell port (logical device 3) */
-const SIO_LOGDEV_TABLE sio_pport[] = {
-	{0x60, 3},			/* set IO to PPort (378) */
-	{0x61, 0x78},		/* set IO to PPort (378) */
-	{0x70, 07},			/* set IRQ 7 for PPort */
-	{0xF1, 00},			/* set PPort to normal */
-	{0x30, 1},			/* and activate the device */
-	{0xFF, 0}				/* end of device table */
-};
-/* paralell port (logical device 3) Floppy assigned to lpt */
-const SIO_LOGDEV_TABLE sio_pport_fdc[] = {
-	{0x60, 3},			/* set IO to PPort (378) */
-	{0x61, 0x78},		/* set IO to PPort (378) */
-	{0x70, 07},			/* set IRQ 7 for PPort */
-	{0xF1, 02},			/* set PPort to Floppy */
-	{0x30, 1},			/* and activate the device */
-	{0xFF, 0}				/* end of device table */
-};
-/* uart 1 (logical device 4) */
-const SIO_LOGDEV_TABLE sio_com1[] = {
-	{0x60, 3},			/* set IO to COM1 (3F8) */
-	{0x61, 0xF8},		/* set IO to COM1 (3F8) */
-	{0x70, 04},			/* set IRQ 4 for COM1 */
-	{0x30, 1},			/* and activate the device */
-	{0xFF, 0}				/* end of device table */
-};
-/* uart 2 (logical device 5) */
-const SIO_LOGDEV_TABLE sio_com2[] = {
-	{0x60, 2},			/* set IO to COM2 (2F8) */
-	{0x61, 0xF8},		/* set IO to COM2 (2F8) */
-	{0x70, 03},			/* set IRQ 3 for COM2 */
-	{0x30, 1},			/* and activate the device */
-	{0xFF, 0}				/* end of device table */
-};
-
-/* keyboard controller (logical device 7) */
-const SIO_LOGDEV_TABLE sio_keyboard[] = {
-	{0x70, 1},			/* set IRQ 1 for keyboard */
-	{0x72, 12},			/* set IRQ 12 for mouse */
-	{0xF0, 0},			/* disable Port92 (this is a PowerPC!!) */
-	{0x30, 1},			/* and activate the device */
-	{0xFF, 0}				/* end of device table */
-};
-
-
-/*******************************************************************************
-* Config SuperIO FDC37C672
-********************************************************************************/
-unsigned char open_cfg_super_IO(int address)
-{
-	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x55); /* open config */
-	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x20); /* set address to DEV ID */
-	if(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 0x1)==0x40) /* ok Device ID is correct */
-		return true;
-	else
-		return false;
-}
-
-void close_cfg_super_IO(int address)
-{
-	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0xAA); /* close config */
-}
-
-
-unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr)
-{
-	/* assuming config reg is open */
-	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */
-	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */
-	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */
-	return in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1);
-}
-
-void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data)
-{
-	/* assuming config reg is open */
-	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */
-	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */
-	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */
-	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,data); /* writes the data */
-}
-
-void isa_write_table(SIO_LOGDEV_TABLE *ldt,unsigned char ldev)
-{
-	while (ldt->index != 0xFF) {
-		write_cfg_super_IO(SIO_CFG_PORT, ldev, ldt->index, ldt->val);
-		ldt++;
-	} /* endwhile */
-}
-
-void isa_sio_loadtable(void)
-{
-	char *s = getenv("floppy");
-	/* setup Floppy device 0*/
-	isa_write_table((SIO_LOGDEV_TABLE *)&sio_fdc,0);
-	/* setup parallel port device 3 */
-	if(s && !strncmp(s, "lpt", 3)) {
-		printf("SIO:   Floppy assigned to LPT\n");
-		/* floppy is assigned to the LPT */
-		isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport_fdc,3);
-	}
-	else {
-		/*printf("Floppy assigned to internal port\n");*/
-		isa_write_table((SIO_LOGDEV_TABLE *)&sio_pport,3);
-	}
-	/* setup Com1 port device 4 */
-	isa_write_table((SIO_LOGDEV_TABLE *)&sio_com1,4);
-	/* setup Com2 port device 5 */
-	isa_write_table((SIO_LOGDEV_TABLE *)&sio_com2,5);
-	/* setup keyboards device 7 */
-	isa_write_table((SIO_LOGDEV_TABLE *)&sio_keyboard,7);
-}
-
-
-void isa_sio_setup(void)
-{
-	if (open_cfg_super_IO(SIO_CFG_PORT) == true)
-	{
-		isa_sio_loadtable();
-		close_cfg_super_IO(0x3F0);
-	}
-}
-#endif
-
-/******************************************************************************
- * IRQ Controller
- * we use the Vector mode
- */
-
-struct	isa_irq_action {
-	 interrupt_handler_t *handler;
-	 void *arg;
-	 int count;
-};
-
-static struct isa_irq_action isa_irqs[16];
-
-
-/*
- * This contains the irq mask for both 8259A irq controllers,
- */
-static unsigned int cached_irq_mask = 0xfff9;
-
-#define cached_imr1	(unsigned char)cached_irq_mask
-#define cached_imr2	(unsigned char)(cached_irq_mask>>8)
-#define IMR_1		CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_OCW1
-#define IMR_2		CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_OCW1
-#define ICW1_1	CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW1
-#define ICW1_2	CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW1
-#define ICW2_1	CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW2
-#define ICW2_2	CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW2
-#define ICW3_1	ICW2_1
-#define ICW3_2	ICW2_2
-#define ICW4_1	ICW2_1
-#define ICW4_2	ICW2_2
-#define ISR_1		ICW1_1
-#define ISR_2		ICW1_2
-
-
-void disable_8259A_irq(unsigned int irq)
-{
-	unsigned int mask = 1 << irq;
-
-	cached_irq_mask |= mask;
-	if (irq & 8)
-		out8(IMR_2,cached_imr2);
-	else
-		out8(IMR_1,cached_imr1);
-}
-
-void enable_8259A_irq(unsigned int irq)
-{
-	unsigned int mask = ~(1 << irq);
-
-	cached_irq_mask &= mask;
-	if (irq & 8)
-		out8(IMR_2,cached_imr2);
-	else
-		out8(IMR_1,cached_imr1);
-}
-/*
-int i8259A_irq_pending(unsigned int irq)
-{
-	unsigned int mask = 1<<irq;
-	int ret;
-
-	if (irq < 8)
-		ret = inb(0x20) & mask;
-	else
-		ret = inb(0xA0) & (mask >> 8);
-	spin_unlock_irqrestore(&i8259A_lock, flags);
-
-	return ret;
-}
-*/
-
-/*
- * This function assumes to be called rarely. Switching between
- * 8259A registers is slow.
- */
-int i8259A_irq_real(unsigned int irq)
-{
-	int value;
-	int irqmask = 1<<irq;
-
-	if (irq < 8) {
-		out8(ISR_1,0x0B);		/* ISR register */
-		value = in8(ISR_1) & irqmask;
-		out8(ISR_1,0x0A);		/* back to the IRR register */
-		return value;
-	}
-	out8(ISR_2,0x0B);		/* ISR register */
-	value = in8(ISR_2) & (irqmask >> 8);
-	out8(ISR_2,0x0A);		/* back to the IRR register */
-	return value;
-}
-
-/*
- * Careful! The 8259A is a fragile beast, it pretty
- * much _has_ to be done exactly like this (mask it
- * first, _then_ send the EOI, and the order of EOI
- * to the two 8259s is important!
- */
-void mask_and_ack_8259A(unsigned int irq)
-{
-	unsigned int irqmask = 1 << irq;
-	unsigned int temp_irqmask = cached_irq_mask;
-	/*
-	 * Lightweight spurious IRQ detection. We do not want
-	 * to overdo spurious IRQ handling - it's usually a sign
-	 * of hardware problems, so we only do the checks we can
-	 * do without slowing down good hardware unnecesserily.
-	 *
-	 * Note that IRQ7 and IRQ15 (the two spurious IRQs
-	 * usually resulting from the 8259A-1|2 PICs) occur
-	 * even if the IRQ is masked in the 8259A. Thus we
-	 * can check spurious 8259A IRQs without doing the
-	 * quite slow i8259A_irq_real() call for every IRQ.
-	 * This does not cover 100% of spurious interrupts,
-	 * but should be enough to warn the user that there
-	 * is something bad going on ...
-	 */
-	if (temp_irqmask & irqmask)
-		goto spurious_8259A_irq;
-	temp_irqmask |= irqmask;
-
-handle_real_irq:
-	if (irq & 8) {
-		in8(IMR_2);		/* DUMMY - (do we need this?) */
-		out8(IMR_2,(unsigned char)(temp_irqmask>>8));
-		out8(ISR_2,0x60+(irq&7));/* 'Specific EOI' to slave */
-		out8(ISR_1,0x62);	/* 'Specific EOI' to master-IRQ2 */
-		out8(IMR_2,cached_imr2); /* turn it on again */
-	} else {
-		in8(IMR_1);		/* DUMMY - (do we need this?) */
-		out8(IMR_1,(unsigned char)temp_irqmask);
-		out8(ISR_1,0x60+irq);	/* 'Specific EOI' to master */
-		out8(IMR_1,cached_imr1); /* turn it on again */
-	}
-
-	return;
-
-spurious_8259A_irq:
-	/*
-	 * this is the slow path - should happen rarely.
-	 */
-	if (i8259A_irq_real(irq))
-		/*
-		 * oops, the IRQ _is_ in service according to the
-		 * 8259A - not spurious, go handle it.
-		 */
-		goto handle_real_irq;
-
-	{
-		static int spurious_irq_mask;
-		/*
-		 * At this point we can be sure the IRQ is spurious,
-		 * lets ACK and report it. [once per IRQ]
-		 */
-		if (!(spurious_irq_mask & irqmask)) {
-			PRINTF("spurious 8259A interrupt: IRQ%d.\n", irq);
-			spurious_irq_mask |= irqmask;
-		}
-		/* irq_err_count++; */
-		/*
-		 * Theoretically we do not have to handle this IRQ,
-		 * but in Linux this does not cause problems and is
-		 * simpler for us.
-		 */
-		goto handle_real_irq;
-	}
-}
-
-void init_8259A(void)
-{
-	out8(IMR_1,0xff);	/* mask all of 8259A-1 */
-	out8(IMR_2,0xff);	/* mask all of 8259A-2 */
-
-	out8(ICW1_1,0x11);	/* ICW1: select 8259A-1 init */
-	out8(ICW2_1,0x20 + 0);	/* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
-	out8(ICW3_1,0x04);	/* 8259A-1 (the master) has a slave on IR2 */
-	out8(ICW4_1,0x01);	/* master expects normal EOI */
-	out8(ICW1_2,0x11);	/* ICW2: select 8259A-2 init */
-	out8(ICW2_2,0x20 + 8);	/* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
-	out8(ICW3_2,0x02);	/* 8259A-2 is a slave on master's IR2 */
-	out8(ICW4_2,0x01);	/* (slave's support for AEOI in flat mode
-				    is to be investigated) */
-	udelay(10000);		/* wait for 8259A to initialize */
-	out8(IMR_1,cached_imr1);	/* restore master IRQ mask */
-	udelay(10000);		/* wait for 8259A to initialize */
-	out8(IMR_2,cached_imr2);	/* restore slave IRQ mask */
-}
-
-
-#define PCI_INT_ACK_ADDR 0xEED00000
-
-int handle_isa_int(void)
-{
-	unsigned long irqack;
-	unsigned char irq;
-	/* first we acknokledge the int via the PCI bus */
-	irqack=in32(PCI_INT_ACK_ADDR);
-	/* now we get the ISRs */
-	in8(ISR_2);
-	in8(ISR_1);
-	irq=(unsigned char)irqack;
-	irq-=32;
-/*	if((irq==7)&&((isr1&0x80)==0)) {
-		PRINTF("IRQ7 detected but not in ISR\n");
-	}
-	else {
-*/		/* we should handle cascaded interrupts here also */
-	{
-/*		printf("ISA Irq %d\n",irq); */
-		isa_irqs[irq].count++;
-		if(irq!=2) { /* just swallow the cascade irq 2 */
-			if (isa_irqs[irq].handler != NULL)
-				(*isa_irqs[irq].handler)(isa_irqs[irq].arg);      /* call isr */
-			else {
-				PRINTF ("bogus interrupt vector 0x%x\n", irq);
-			}
-		}
-	}
-	/* issue EOI instruction to clear the IRQ */
-	mask_and_ack_8259A(irq);
-	return 0;
-}
-
-
-/******************************************************************
- * Install and free an ISA interrupt handler.
- */
-
-void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
-{
-	if (isa_irqs[vec].handler != NULL) {
-		printf ("ISA Interrupt vector %d: handler 0x%x replacing 0x%x\n",
-			vec, (uint)handler, (uint)isa_irqs[vec].handler);
-	}
-	isa_irqs[vec].handler = handler;
-	isa_irqs[vec].arg     = arg;
-	enable_8259A_irq(vec);
-	PRINTF ("Install ISA IRQ %d ==> %p, @ %p mask=%04x\n", vec, handler, &isa_irqs[vec].handler,cached_irq_mask);
-
-}
-
-void isa_irq_free_handler(int vec)
-{
-	disable_8259A_irq(vec);
-	isa_irqs[vec].handler = NULL;
-	isa_irqs[vec].arg     = NULL;
-	PRINTF ("Free ISA IRQ %d mask=%04x\n", vec, cached_irq_mask);
-
-}
-
-/****************************************************************************/
-void isa_init_irq_contr(void)
-{
-	int i;
-	/* disable all Interrupts */
-	/* first write icws controller 1 */
-	for(i=0;i<16;i++)
-	{
-		isa_irqs[i].handler=NULL;
-		isa_irqs[i].arg=NULL;
-		isa_irqs[i].count=0;
-	}
-	init_8259A();
-	out8(IMR_2,0xFF);
-}
-/*************************************************************************/
-
-void isa_show_irq(void)
-{
-	int vec;
-
-	printf ("\nISA Interrupt-Information:\n");
-	printf ("Nr  Routine   Arg       Count\n");
-
-	for (vec=0; vec<16; vec++) {
-		if (isa_irqs[vec].handler != NULL) {
-			printf ("%02d  %08lx  %08lx  %d\n",
-				vec,
-				(ulong)isa_irqs[vec].handler,
-				(ulong)isa_irqs[vec].arg,
-				isa_irqs[vec].count);
-		}
-	}
-}
-
-int isa_irq_get_count(int vec)
-{
-	return(isa_irqs[vec].count);
-}
-
-/******************************************************************
- * Init the ISA bus and devices.
- */
-
-#if defined(CONFIG_PIP405)
-
-int isa_init(void)
-{
-	isa_sio_setup();
-	isa_init_irq_contr();
-	drv_isa_kbd_init();
-	return 0;
-}
-#endif
diff --git a/board/mpl/common/isa.h b/board/mpl/common/isa.h
deleted file mode 100644
index c706d67..0000000
--- a/board/mpl/common/isa.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ISA_H_
-#define _ISA_H_
-/* Super IO */
-#define SIO_CFG_PORT	0x3F0	/* Config Port Address */
-
-#if defined(CONFIG_PIP405)
-/* table fore SIO initialization */
-typedef struct {
-	const uchar index;
-	const uchar val;
-} SIO_LOGDEV_TABLE;
-
-typedef struct {
-	const uchar ldev;
-	const SIO_LOGDEV_TABLE *ldev_table;
-} SIO_TABLE;
-
-
-unsigned char open_cfg_super_IO(int address);
-unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr);
-void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data);
-void close_cfg_super_IO(int address);
-void isa_sio_setup(void);
-#endif
-
-void isa_irq_install_handler(int vec, interrupt_handler_t *handler, void *arg);
-void isa_irq_free_handler(int vec);
-int handle_isa_int(void);
-void isa_init_irq_contr(void);
-void isa_show_irq(void);
-int isa_irq_get_count(int vec);
-
-
-#endif
diff --git a/board/mpl/common/kbd.c b/board/mpl/common/kbd.c
deleted file mode 100644
index 36b1694..0000000
--- a/board/mpl/common/kbd.c
+++ /dev/null
@@ -1,625 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Source partly derived from:
- * linux/drivers/char/pc_keyb.c
- */
-#include <common.h>
-#include <console.h>
-#include <asm/processor.h>
-#include <stdio_dev.h>
-#include "isa.h"
-#include "kbd.h"
-
-
-unsigned char kbd_read_status(void);
-unsigned char kbd_read_input(void);
-void kbd_send_data(unsigned char data);
-void disable_8259A_irq(unsigned int irq);
-void enable_8259A_irq(unsigned int irq);
-
-/* used only by send_data - set by keyboard_interrupt */
-
-
-#undef KBG_DEBUG
-
-#ifdef KBG_DEBUG
-#define	PRINTF(fmt,args...)	printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-#define KBD_STAT_KOBF		0x01
-#define KBD_STAT_IBF		0x02
-#define KBD_STAT_SYS		0x04
-#define KBD_STAT_CD		0x08
-#define KBD_STAT_LOCK		0x10
-#define KBD_STAT_MOBF		0x20
-#define KBD_STAT_TI_OUT		0x40
-#define KBD_STAT_PARERR		0x80
-
-#define KBD_INIT_TIMEOUT	1000	/* Timeout in ms for initializing the keyboard */
-#define KBC_TIMEOUT		250	/* Timeout in ms for sending to keyboard controller */
-#define KBD_TIMEOUT		2000	/* Timeout in ms for keyboard command acknowledge */
-/*
- *	Keyboard Controller Commands
- */
-
-#define KBD_CCMD_READ_MODE	0x20	/* Read mode bits */
-#define KBD_CCMD_WRITE_MODE	0x60	/* Write mode bits */
-#define KBD_CCMD_GET_VERSION	0xA1	/* Get controller version */
-#define KBD_CCMD_MOUSE_DISABLE	0xA7	/* Disable mouse interface */
-#define KBD_CCMD_MOUSE_ENABLE	0xA8	/* Enable mouse interface */
-#define KBD_CCMD_TEST_MOUSE	0xA9	/* Mouse interface test */
-#define KBD_CCMD_SELF_TEST	0xAA	/* Controller self test */
-#define KBD_CCMD_KBD_TEST	0xAB	/* Keyboard interface test */
-#define KBD_CCMD_KBD_DISABLE	0xAD	/* Keyboard interface disable */
-#define KBD_CCMD_KBD_ENABLE	0xAE	/* Keyboard interface enable */
-#define KBD_CCMD_WRITE_AUX_OBUF	0xD3    /* Write to output buffer as if
-					   initiated by the auxiliary device */
-#define KBD_CCMD_WRITE_MOUSE	0xD4	/* Write the following byte to the mouse */
-
-/*
- *	Keyboard Commands
- */
-
-#define KBD_CMD_SET_LEDS	0xED	/* Set keyboard leds */
-#define KBD_CMD_SET_RATE	0xF3	/* Set typematic rate */
-#define KBD_CMD_ENABLE		0xF4	/* Enable scanning */
-#define KBD_CMD_DISABLE		0xF5	/* Disable scanning */
-#define KBD_CMD_RESET		0xFF	/* Reset */
-
-/*
- *	Keyboard Replies
- */
-
-#define KBD_REPLY_POR		0xAA	/* Power on reset */
-#define KBD_REPLY_ACK		0xFA	/* Command ACK */
-#define KBD_REPLY_RESEND	0xFE	/* Command NACK, send the cmd again */
-
-/*
- *	Status Register Bits
- */
-
-#define KBD_STAT_OBF		0x01	/* Keyboard output buffer full */
-#define KBD_STAT_IBF		0x02	/* Keyboard input buffer full */
-#define KBD_STAT_SELFTEST	0x04	/* Self test successful */
-#define KBD_STAT_CMD		0x08	/* Last write was a command write (0=data) */
-#define KBD_STAT_UNLOCKED	0x10	/* Zero if keyboard locked */
-#define KBD_STAT_MOUSE_OBF	0x20	/* Mouse output buffer full */
-#define KBD_STAT_GTO		0x40	/* General receive/xmit timeout */
-#define KBD_STAT_PERR		0x80	/* Parity error */
-
-#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
-
-/*
- *	Controller Mode Register Bits
- */
-
-#define KBD_MODE_KBD_INT	0x01	/* Keyboard data generate IRQ1 */
-#define KBD_MODE_MOUSE_INT	0x02	/* Mouse data generate IRQ12 */
-#define KBD_MODE_SYS		0x04	/* The system flag (?) */
-#define KBD_MODE_NO_KEYLOCK	0x08	/* The keylock doesn't affect the keyboard if set */
-#define KBD_MODE_DISABLE_KBD	0x10	/* Disable keyboard interface */
-#define KBD_MODE_DISABLE_MOUSE	0x20	/* Disable mouse interface */
-#define KBD_MODE_KCC		0x40	/* Scan code conversion to PC format */
-#define KBD_MODE_RFU		0x80
-
-
-#define KDB_DATA_PORT		0x60
-#define KDB_COMMAND_PORT	0x64
-
-#define	LED_SCR			0x01	/* scroll lock led */
-#define	LED_CAP			0x04	/* caps lock led */
-#define	LED_NUM			0x02	/* num lock led */
-
-#define	KBD_BUFFER_LEN		0x20	/* size of the keyboardbuffer */
-
-
-static volatile char kbd_buffer[KBD_BUFFER_LEN];
-static volatile int in_pointer = 0;
-static volatile int out_pointer = 0;
-
-
-static unsigned char num_lock = 0;
-static unsigned char caps_lock = 0;
-static unsigned char scroll_lock = 0;
-static unsigned char shift = 0;
-static unsigned char ctrl = 0;
-static unsigned char alt = 0;
-static unsigned char e0 = 0;
-static unsigned char leds = 0;
-
-#define DEVNAME "kbd"
-
-/* Simple translation table for the keys */
-
-static unsigned char kbd_plain_xlate[] = {
-	0xff,0x1b, '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '-', '=','\b','\t',	/* 0x00 - 0x0f */
-	 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', 'o', 'p', '[', ']','\r',0xff, 'a', 's',	/* 0x10 - 0x1f */
-	 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';','\'', '`',0xff,'\\', 'z', 'x', 'c', 'v',	/* 0x20 - 0x2f */
-	 'b', 'n', 'm', ',', '.', '/',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff,	/* 0x30 - 0x3f */
-	0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1',	/* 0x40 - 0x4f */
-	 '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,  /* 0x50 - 0x5F */
-	'\r',0xff,0xff
-	};
-
-static unsigned char kbd_shift_xlate[] = {
-	0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t',	/* 0x00 - 0x0f */
-	 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S',	/* 0x10 - 0x1f */
-	 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', '"', '~',0xff, '|', 'Z', 'X', 'C', 'V',	/* 0x20 - 0x2f */
-	 'B', 'N', 'M', '<', '>', '?',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff,	/* 0x30 - 0x3f */
-	0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1',	/* 0x40 - 0x4f */
-	 '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,  /* 0x50 - 0x5F */
-	'\r',0xff,0xff
-	};
-
-static unsigned char kbd_ctrl_xlate[] = {
-	0xff,0x1b, '1',0x00, '3', '4', '5',0x1E, '7', '8', '9', '0',0x1F, '=','\b','\t',	/* 0x00 - 0x0f */
-	0x11,0x17,0x05,0x12,0x14,0x18,0x15,0x09,0x0f,0x10,0x1b,0x1d,'\n',0xff,0x01,0x13,	/* 0x10 - 0x1f */
-	0x04,0x06,0x08,0x09,0x0a,0x0b,0x0c, ';','\'', '~',0x00,0x1c,0x1a,0x18,0x03,0x16,	/* 0x20 - 0x2f */
-	0x02,0x0e,0x0d, '<', '>', '?',0xff,0xff,0xff,0x00,0xff,0xff,0xff,0xff,0xff,0xff,	/* 0x30 - 0x3f */
-	0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1',	/* 0x40 - 0x4f */
-	 '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,  /* 0x50 - 0x5F */
-	'\r',0xff,0xff
-	};
-
-/******************************************************************
- * Init
- ******************************************************************/
-int isa_kbd_init(void)
-{
-	char* result;
-	result=kbd_initialize();
-	if(result==NULL) {
-		PRINTF("AT Keyboard initialized\n");
-		irq_install_handler(25, (interrupt_handler_t *)handle_isa_int, NULL);
-		isa_irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL);
-		return (1);
-	} else {
-		printf("%s\n",result);
-		return (-1);
-	}
-}
-
-#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-extern int overwrite_console (void);
-#else
-int overwrite_console (void)
-{
-	return (0);
-}
-#endif
-
-int drv_isa_kbd_init (void)
-{
-	int error;
-	struct stdio_dev kbddev ;
-	char *stdinname  = getenv ("stdin");
-
-	if(isa_kbd_init()==-1)
-		return -1;
-	memset (&kbddev, 0, sizeof(kbddev));
-	strcpy(kbddev.name, DEVNAME);
-	kbddev.flags =  DEV_FLAGS_INPUT;
-	kbddev.getc = kbd_getc ;
-	kbddev.tstc = kbd_testc ;
-
-	error = stdio_register (&kbddev);
-	if(error==0) {
-		/* check if this is the standard input device */
-		if(strcmp(stdinname,DEVNAME)==0) {
-			/* reassign the console */
-			if(overwrite_console()) {
-				return 1;
-			}
-			error=console_assign(stdin,DEVNAME);
-			if(error==0)
-				return 1;
-			else
-				return error;
-		}
-		return 1;
-	}
-	return error;
-}
-
-/******************************************************************
- * Queue handling
- ******************************************************************/
-/* puts character in the queue and sets up the in and out pointer */
-void kbd_put_queue(char data)
-{
-	if((in_pointer+1)==KBD_BUFFER_LEN) {
-		if(out_pointer==0) {
-			return; /* buffer full */
-		} else{
-			in_pointer=0;
-		}
-	} else {
-		if((in_pointer+1)==out_pointer)
-			return; /* buffer full */
-		in_pointer++;
-	}
-	kbd_buffer[in_pointer]=data;
-	return;
-}
-
-/* test if a character is in the queue */
-int kbd_testc(struct stdio_dev *dev)
-{
-	if(in_pointer==out_pointer)
-		return(0); /* no data */
-	else
-		return(1);
-}
-/* gets the character from the queue */
-int kbd_getc(struct stdio_dev *dev)
-{
-	char c;
-	while(in_pointer==out_pointer);
-	if((out_pointer+1)==KBD_BUFFER_LEN)
-		out_pointer=0;
-	else
-		out_pointer++;
-	c=kbd_buffer[out_pointer];
-	return (int)c;
-
-}
-
-
-/* set LEDs */
-
-void kbd_set_leds(void)
-{
-	if(caps_lock==0)
-		leds&=~LED_CAP; /* switch caps_lock off */
-	else
-		leds|=LED_CAP; /* switch on LED */
-	if(num_lock==0)
-		leds&=~LED_NUM; /* switch LED off */
-	else
-		leds|=LED_NUM;  /* switch on LED */
-	if(scroll_lock==0)
-		leds&=~LED_SCR; /* switch LED off */
-	else
-		leds|=LED_SCR; /* switch on LED */
-	kbd_send_data(KBD_CMD_SET_LEDS);
-	kbd_send_data(leds);
-}
-
-
-void handle_keyboard_event (unsigned char scancode)
-{
-	unsigned char keycode;
-
-	/*  Convert scancode to keycode */
-	PRINTF ("scancode %x\n", scancode);
-	if (scancode == 0xe0) {
-		e0 = 1;		/* special charakters */
-		return;
-	}
-	if (e0 == 1) {
-		e0 = 0;		/* delete flag */
-		if (!(((scancode & 0x7F) == 0x38) ||	/* the right ctrl key */
-		      ((scancode & 0x7F) == 0x1D) ||	/* the right alt key */
-		      ((scancode & 0x7F) == 0x35) ||	/* the right '/' key */
-		      ((scancode & 0x7F) == 0x1C)))
-			/* the right enter key */
-			/* we swallow unknown e0 codes */
-			return;
-	}
-	/* special cntrl keys */
-	switch (scancode) {
-	case 0x2A:
-	case 0x36:		/* shift pressed */
-		shift = 1;
-		return;		/* do nothing else */
-	case 0xAA:
-	case 0xB6:		/* shift released */
-		shift = 0;
-		return;		/* do nothing else */
-	case 0x38:		/* alt pressed */
-		alt = 1;
-		return;		/* do nothing else */
-	case 0xB8:		/* alt released */
-		alt = 0;
-		return;		/* do nothing else */
-	case 0x1d:		/* ctrl pressed */
-		ctrl = 1;
-		return;		/* do nothing else */
-	case 0x9d:		/* ctrl released */
-		ctrl = 0;
-		return;		/* do nothing else */
-	case 0x46:		/* scrollock pressed */
-		scroll_lock = ~scroll_lock;
-		kbd_set_leds ();
-		return;		/* do nothing else */
-	case 0x3A:		/* capslock pressed */
-		caps_lock = ~caps_lock;
-		kbd_set_leds ();
-		return;
-	case 0x45:		/* numlock pressed */
-		num_lock = ~num_lock;
-		kbd_set_leds ();
-		return;
-	case 0xC6:		/* scroll lock released */
-	case 0xC5:		/* num lock released */
-	case 0xBA:		/* caps lock released */
-		return;		/* just swallow */
-	}
-	if ((scancode & 0x80) == 0x80)	/* key released */
-		return;
-	/* now, decide which table we need */
-	if (scancode > (sizeof (kbd_plain_xlate) / sizeof (kbd_plain_xlate[0]))) {	/* scancode not in list */
-		PRINTF ("unkown scancode %X\n", scancode);
-		return;		/* swallow it */
-	}
-	/* setup plain code first */
-	keycode = kbd_plain_xlate[scancode];
-	if (caps_lock == 1) {	/* caps_lock is pressed, overwrite plain code */
-		if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) {	/* scancode not in list */
-			PRINTF ("unkown caps-locked scancode %X\n", scancode);
-			return;	/* swallow it */
-		}
-		keycode = kbd_shift_xlate[scancode];
-		if (keycode < 'A') {	/* we only want the alphas capital */
-			keycode = kbd_plain_xlate[scancode];
-		}
-	}
-	if (shift == 1) {	/* shift overwrites caps_lock */
-		if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) {	/* scancode not in list */
-			PRINTF ("unkown shifted scancode %X\n", scancode);
-			return;	/* swallow it */
-		}
-		keycode = kbd_shift_xlate[scancode];
-	}
-	if (ctrl == 1) {	/* ctrl overwrites caps_lock and shift */
-		if (scancode > (sizeof (kbd_ctrl_xlate) / sizeof (kbd_ctrl_xlate[0]))) {	/* scancode not in list */
-			PRINTF ("unkown ctrl scancode %X\n", scancode);
-			return;	/* swallow it */
-		}
-		keycode = kbd_ctrl_xlate[scancode];
-	}
-	/* check if valid keycode */
-	if (keycode == 0xff) {
-		PRINTF ("unkown scancode %X\n", scancode);
-		return;		/* swallow unknown codes */
-	}
-
-	kbd_put_queue (keycode);
-	PRINTF ("%x\n", keycode);
-}
-
-/*
- * This reads the keyboard status port, and does the
- * appropriate action.
- *
- */
-unsigned char handle_kbd_event(void)
-{
-	unsigned char status = kbd_read_status();
-	unsigned int work = 10000;
-
-	while ((--work > 0) && (status & KBD_STAT_OBF)) {
-		unsigned char scancode;
-
-		scancode = kbd_read_input();
-
-		/* Error bytes must be ignored to make the
-		   Synaptics touchpads compaq use work */
-		/* Ignore error bytes */
-		if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR)))
-		{
-			if (status & KBD_STAT_MOUSE_OBF)
-				; /* not supported: handle_mouse_event(scancode); */
-			else
-				handle_keyboard_event(scancode);
-		}
-		status = kbd_read_status();
-	}
-	if (!work)
-		PRINTF("pc_keyb: controller jammed (0x%02X).\n", status);
-	return status;
-}
-
-
-/******************************************************************************
- * Lowlevel Part of keyboard section
- */
-unsigned char kbd_read_status(void)
-{
-	return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
-}
-
-unsigned char kbd_read_input(void)
-{
-	return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
-}
-
-void kbd_write_command(unsigned char cmd)
-{
-	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
-}
-
-void kbd_write_output(unsigned char data)
-{
-	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
-}
-
-int kbd_read_data(void)
-{
-	int val;
-	unsigned char status;
-
-	val = -1;
-	status = kbd_read_status();
-	if (status & KBD_STAT_OBF) {
-		val = kbd_read_input();
-		if (status & (KBD_STAT_GTO | KBD_STAT_PERR))
-			val = -2;
-	}
-	return val;
-}
-
-int kbd_wait_for_input(void)
-{
-	unsigned long timeout;
-	int val;
-
-	timeout = KBD_TIMEOUT;
-	val=kbd_read_data();
-	while(val < 0)
-	{
-		if(timeout--==0)
-			return -1;
-		udelay(1000);
-		val=kbd_read_data();
-	}
-	return val;
-}
-
-
-int kb_wait(void)
-{
-	unsigned long timeout = KBC_TIMEOUT * 10;
-
-	do {
-		unsigned char status = handle_kbd_event();
-		if (!(status & KBD_STAT_IBF))
-			return 0; /* ok */
-		udelay(1000);
-		timeout--;
-	} while (timeout);
-	return 1;
-}
-
-void kbd_write_command_w(int data)
-{
-	if(kb_wait())
-		PRINTF("timeout in kbd_write_command_w\n");
-	kbd_write_command(data);
-}
-
-void kbd_write_output_w(int data)
-{
-	if(kb_wait())
-		PRINTF("timeout in kbd_write_output_w\n");
-	kbd_write_output(data);
-}
-
-void kbd_send_data(unsigned char data)
-{
-	unsigned char status;
-	disable_8259A_irq(1); /* disable interrupt */
-	kbd_write_output_w(data);
-	status = kbd_wait_for_input();
-	if (status == KBD_REPLY_ACK)
-		enable_8259A_irq(1); /* enable interrupt */
-}
-
-
-char * kbd_initialize(void)
-{
-	int status;
-
-	in_pointer = 0; /* delete in Buffer */
-	out_pointer = 0;
-	/*
-	 * Test the keyboard interface.
-	 * This seems to be the only way to get it going.
-	 * If the test is successful a x55 is placed in the input buffer.
-	 */
-	kbd_write_command_w(KBD_CCMD_SELF_TEST);
-	if (kbd_wait_for_input() != 0x55)
-		return "Kbd:   failed self test";
-	/*
-	 * Perform a keyboard interface test.  This causes the controller
-	 * to test the keyboard clock and data lines.  The results of the
-	 * test are placed in the input buffer.
-	 */
-	kbd_write_command_w(KBD_CCMD_KBD_TEST);
-	if (kbd_wait_for_input() != 0x00)
-		return "Kbd:   interface failed self test";
-	/*
-	 * Enable the keyboard by allowing the keyboard clock to run.
-	 */
-	kbd_write_command_w(KBD_CCMD_KBD_ENABLE);
-	status = kbd_wait_for_input();
-	/*
-	 * Reset keyboard. If the read times out
-	 * then the assumption is that no keyboard is
-	 * plugged into the machine.
-	 * This defaults the keyboard to scan-code set 2.
-	 *
-	 * Set up to try again if the keyboard asks for RESEND.
-	 */
-	do {
-		kbd_write_output_w(KBD_CMD_RESET);
-		status = kbd_wait_for_input();
-		if (status == KBD_REPLY_ACK)
-			break;
-		if (status != KBD_REPLY_RESEND) {
-			PRINTF("status: %X\n",status);
-			return "Kbd:   reset failed, no ACK";
-		}
-	} while (1);
-	if (kbd_wait_for_input() != KBD_REPLY_POR)
-		return "Kbd:   reset failed, no POR";
-
-	/*
-	 * Set keyboard controller mode. During this, the keyboard should be
-	 * in the disabled state.
-	 *
-	 * Set up to try again if the keyboard asks for RESEND.
-	 */
-	do {
-		kbd_write_output_w(KBD_CMD_DISABLE);
-		status = kbd_wait_for_input();
-		if (status == KBD_REPLY_ACK)
-			break;
-		if (status != KBD_REPLY_RESEND)
-			return "Kbd:   disable keyboard: no ACK";
-	} while (1);
-
-	kbd_write_command_w(KBD_CCMD_WRITE_MODE);
-	kbd_write_output_w(KBD_MODE_KBD_INT
-			      | KBD_MODE_SYS
-			      | KBD_MODE_DISABLE_MOUSE
-			      | KBD_MODE_KCC);
-
-	/* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
-	kbd_write_command_w(KBD_CCMD_READ_MODE);
-	if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
-		/*
-		 * If the controller does not support conversion,
-		 * Set the keyboard to scan-code set 1.
-		 */
-		kbd_write_output_w(0xF0);
-		kbd_wait_for_input();
-		kbd_write_output_w(0x01);
-		kbd_wait_for_input();
-	}
-	kbd_write_output_w(KBD_CMD_ENABLE);
-	if (kbd_wait_for_input() != KBD_REPLY_ACK)
-		return "Kbd:   enable keyboard: no ACK";
-
-	/*
-	 * Finally, set the typematic rate to maximum.
-	 */
-	kbd_write_output_w(KBD_CMD_SET_RATE);
-	if (kbd_wait_for_input() != KBD_REPLY_ACK)
-		return "Kbd:   Set rate: no ACK";
-	kbd_write_output_w(0x00);
-	if (kbd_wait_for_input() != KBD_REPLY_ACK)
-		return "Kbd:   Set rate: no ACK";
-	return NULL;
-}
-
-void kbd_interrupt(void)
-{
-	handle_kbd_event();
-}
diff --git a/board/mpl/common/kbd.h b/board/mpl/common/kbd.h
deleted file mode 100644
index b549e20..0000000
--- a/board/mpl/common/kbd.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _KBD_H_
-#define _KBD_H_
-
-struct stdio_dev;
-
-int kbd_testc(struct stdio_dev *sdev);
-int kbd_getc(struct stdio_dev *sdev);
-extern void kbd_interrupt(void);
-extern char *kbd_initialize(void);
-
-unsigned char kbd_is_init(void);
-#define KBD_INTERRUPT 1
-#endif
diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c
deleted file mode 100644
index cd969cb..0000000
--- a/board/mpl/common/pci.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
- */
-/*
- * Adapted for PIP405 03.07.01
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * TODO: Clean-up
- */
-
-#include <common.h>
-#include <pci.h>
-#include "isa.h"
-
-#ifdef CONFIG_405GP
-#ifdef CONFIG_PCI
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#include "piix4_pci.h"
-#include "pci_parts.h"
-
-void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev,
-			   struct pci_config_table *entry)
-{
-	struct pci_pip405_config_entry *table;
-	int i;
-
-	table = (struct pci_pip405_config_entry*) entry->priv[0];
-
-	for (i=0; table[i].width; i++)
-	{
-#ifdef DEBUG
-		printf("Reg 0x%02X Value 0x%08lX Width %02d written\n",
-		       table[i].index, table[i].val, table[i].width);
-#endif
-
-		switch(table[i].width)
-		{
-		case 1: pci_hose_write_config_byte(hose, dev, table[i].index, table[i].val); break;
-		case 2: pci_hose_write_config_word(hose, dev, table[i].index, table[i].val); break;
-		case 4: pci_hose_write_config_dword(hose, dev, table[i].index, table[i].val); break;
-		}
-	}
-}
-
-
-static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
-	unsigned char int_line = 0xff;
-	unsigned char pin;
-	/*
-	 * Write pci interrupt line register
-	 */
-	if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */
-		return;
-	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
-	if ((pin == 0) || (pin > 4))
-	    return;
-
-	int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28;
-	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
-#ifdef DEBUG
-	printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n",
-	       PCI_DEV(dev),dev,int_line,int_line);
-#endif
-}
-
-extern void pci_405gp_init(struct pci_controller *hose);
-
-
-static struct pci_controller hose = {
-  config_table: pci_pip405_config_table,
-  fixup_irq: pci_pip405_fixup_irq,
-};
-
-
-void pci_init_board(void)
-{
-	/*we want the ptrs to RAM not flash (ie don't use init list)*/
-	hose.fixup_irq    = pci_pip405_fixup_irq;
-	hose.config_table = pci_pip405_config_table;
-#ifdef DEBUG
-	printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose);
-#endif
-	pci_405gp_init(&hose);
-}
-
-#endif /* CONFIG_PCI */
-#endif /* CONFIG_405GP */
diff --git a/board/mpl/common/pci_parts.h b/board/mpl/common/pci_parts.h
deleted file mode 100644
index 4193e92..0000000
--- a/board/mpl/common/pci_parts.h
+++ /dev/null
@@ -1,176 +0,0 @@
- /*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _PCI_PARTS_H_
-#define _PCI_PARTS_H_
-
-
-/* Board specific file containing:
- * - PCI Memory Mapping
- * - PCI IO Mapping
- * - PCI Interrupt Mapping
- */
-
-/* PIP405 PCI INT Routing:
- *                      IRQ0  VECTOR
- * PIXX4 IDSEL  = AD16  INTA#  28 (Function 2 USB is INTD# = 31)
- * VGA   IDSEL  = AD17  INTB#  29
- * SCSI  IDSEL  = AD18  INTC#  30
- * PC104 IDSEL0 = AD20  INTA#  28
- * PC104 IDSEL1 = AD21  INTB#  29
- * PC104 IDSEL2 = AD22  INTC#  30
- * PC104 IDSEL3 = AD23  INTD#  31
- *
- * busdevfunc = EXXX XXXX BBBB BBBB DDDD DFFF RRRR RR00
- *              ^         ^         ^     ^   ^
- *             31        23        15    10   7
- * E = Enabled
- * B = Bussnumber
- * D = Devicenumber (Device0 = AD10)
- * F = Functionnumber
- * R = Registernumber
- *
- * Device = (busdevfunc>>11) + 10
- * Vector = devicenumber % 4 + 28
- *
- */
-#define PCI_HIGHEST_ON_BOARD_ID	19
-/*#define PCI_DEV_NUMBER(x)	(((x>>11) & 0x1f) + 10) */
-#define PCI_IRQ_VECTOR(x)	((PCI_DEV(x) + 10) % 4) + 28
-
-
-/* PCI Device List for PIP405 */
-
-/* Mapping:
- * +-------------+------------+------------+--------------------------------+
- * | PCI MemAddr | PCI IOAddr | Local Addr | Device / Function              |
- * +-------------+------------+------------+--------------------------------+
- * |  0x00000000 |            | 0xA0000000 | ISA Memory (hard wired)        |
- * |  0x00FFFFFF |            | 0xA0FFFFFF |                                |
- * +-------------+------------+------------+--------------------------------+
- * |             | 0x00000000 | 0xE8000000 | ISA IO (hard wired)            |
- * |             | 0x0000FFFF | 0xE800FFFF |                                |
- * +-------------+------------+------------+--------------------------------+
- * |  0x80000000 |            | 0x80000000 | VGA Controller Memory          |
- * |  0x80FFFFFF |            | 0x80FFFFFF |                                |
- * +-------------+------------+------------+--------------------------------+
- * |  0x81000000 |            | 0x81000000 | SCSI Controller Memory         |
- * |  0x81FFFFFF |            | 0x81FFFFFF |                                |
- * +-------------+------------+------------+--------------------------------+
- */
-
-struct pci_pip405_config_entry {
-	int		index;	/* address */
-	unsigned long	val;	/* value */
-	int		width;	/* data size */
-};
-
-extern void pci_pip405_write_regs(struct pci_controller *,
-				  pci_dev_t,
-				  struct pci_config_table *);
-
-/* PIIX4 ISA Bridge Function 0 */
-static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
-	{PCI_CFG_PIIX4_SERIRQ,	0xD0,		1}, /* enable Continous SERIRQ Pin */
-	{PCI_CFG_PIIX4_GENCFG,	0x00018041,	4}, /* enable SERIRQs, ISA, PNP, GPI11 */
-	{PCI_CFG_PIIX4_TOM,	0xFE,		1}, /* Top of Memory		*/
-	{PCI_CFG_PIIX4_XBCS,	0x02C4,		2}, /* disable all peri CS	*/
-	{PCI_CFG_PIIX4_RTCCFG,	0x21,		1}, /* enable RTC		*/
-#if defined(CONFIG_PIP405)
-	{PCI_CFG_PIIX4_MBDMA,	0x82,		1}, /* set MBDMA0 to DMA 2	*/
-	{PCI_CFG_PIIX4_MBDMA+1,	0x83,		1}, /* set MBDMA1 to DMA 3	*/
-#endif
-	{PCI_CFG_PIIX4_DLC,	0x0,		1}, /* disable passive release feature */
-	{ }					    /* end of device table	*/
-};
-
-/* PIIX4 IDE Controller Function 1 */
-static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
-	{PCI_CFG_PIIX4_BMIBA,	0x0001000,	4}, /* set BMI to a valid address */
-	{PCI_COMMAND,		0x0001,		2}, /* enable IO access	*/
-#if !defined(CONFIG_MIP405T)
-	{PCI_CFG_PIIX4_IDETIM,	0x80008000,	4}, /* enable Both IDE channels	*/
-#else
-	{PCI_CFG_PIIX4_IDETIM,	0x00008000,	4}, /* enable IDE channel0	*/
-#endif
-	{ }					    /* end of device table	*/
-};
-
-/* PIIX4 USB Controller Function 2 */
-static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = {
-#if !defined(CONFIG_MIP405T)
-	{PCI_INTERRUPT_LINE,	31,		1}, /* Int vector = 31		*/
-	{PCI_BASE_ADDRESS_4,	0x0000E001,	4}, /* Set IO Address to 0xe000 to 0xe01F */
-	{PCI_LATENCY_TIMER,	0x80,		1}, /* Latency Timer 0x80	*/
-	{0xC0,			0x2000,		2}, /* Legacy support		*/
-	{PCI_COMMAND,		0x0005,		2}, /* enable IO access and Master */
-#endif
-	{ }					    /* end of device table	*/
-};
-
-/* PIIX4 Power Management Function 3 */
-static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = {
-	{PCI_CFG_PIIX4_PMBA,	0x00004000,	4}, /* set PMBA to "valid" value */
-	{PCI_CFG_PIIX4_SMBBA,	0x00005000,	4}, /* set SMBBA to "valid" value */
-	{PCI_CFG_PIIX4_PMMISC,	0x01,		1}, /* enable PMBA IO access	*/
-	{PCI_COMMAND,		0x0001,		2}, /* enable IO access	*/
-	{ }					    /* end of device table	*/
-};
-/* PPC405 Dummy only used to prevent autosetup on this host bridge */
-static struct pci_pip405_config_entry ppc405_dummy[] = {
-	{ }					    /* end of device table	*/
-};
-
-void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
-			 struct pci_config_table *entry);
-
-
-static struct pci_config_table pci_pip405_config_table[]={
-	{PCI_VENDOR_ID_IBM,			/* 405 dummy */
-	 PCI_DEVICE_ID_IBM_405GP,
-	 PCI_ANY_ID,
-	 PCI_ANY_ID, PCI_ANY_ID, 0,
-	 pci_pip405_write_regs, {(unsigned long) ppc405_dummy}},
-
-	{PCI_VENDOR_ID_INTEL,			/* PIIX4 ISA Bridge Function 0 */
-	 PCI_DEVICE_ID_INTEL_82371AB_0,
-	 PCI_ANY_ID,
-	 PCI_ANY_ID, PCI_ANY_ID, 0,
-	 pci_pip405_write_regs, {(unsigned long) piix4_isa_bridge_f0}},
-
-	{PCI_VENDOR_ID_INTEL,			/* PIIX4 IDE Controller Function 1 */
-	 PCI_DEVICE_ID_INTEL_82371AB,
-	 PCI_ANY_ID,
-	 PCI_ANY_ID, PCI_ANY_ID, 1,
-	 pci_pip405_write_regs, {(unsigned long) piix4_ide_cntrl_f1}},
-
-	{PCI_VENDOR_ID_INTEL,			/* PIIX4 USB Controller Function 2 */
-	 PCI_DEVICE_ID_INTEL_82371AB_2,
-	 PCI_ANY_ID,
-	 PCI_ANY_ID, PCI_ANY_ID, 2,
-	 pci_pip405_write_regs, {(unsigned long) piix4_usb_cntrl_f2}},
-
-	{PCI_VENDOR_ID_INTEL,			/* PIIX4 USB Controller Function 3 */
-	 PCI_DEVICE_ID_INTEL_82371AB_3,
-	 PCI_ANY_ID,
-	 PCI_ANY_ID, PCI_ANY_ID, 3,
-	 pci_pip405_write_regs, {(unsigned long) piix4_pmm_cntrl_f3}},
-
-	{PCI_ANY_ID,
-	 PCI_ANY_ID,
-	 PCI_CLASS_DISPLAY_VGA,
-	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	 pci_405gp_setup_vga},
-
-	{PCI_ANY_ID,
-	 PCI_ANY_ID,
-	 PCI_CLASS_NOT_DEFINED_VGA,
-	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	 pci_405gp_setup_vga},
-
-	{ }
-};
-#endif /* _PCI_PARTS_H_ */
diff --git a/board/mpl/common/piix4_pci.h b/board/mpl/common/piix4_pci.h
deleted file mode 100644
index c19b64e..0000000
--- a/board/mpl/common/piix4_pci.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-#ifndef _PIIX4_PCI_H
-#define _PIIX4_PCI_H
-
-/***************************************************************************
-* Defines PIIX4 Config Registers
-****************************************************************************/
-
-/* Function 0 ISA Bridge */
-#define	PCI_CFG_PIIX4_IORT		0x4C	/* 8 bit ISA Recovery Timer Reg (default 0x4D) */
-#define	PCI_CFG_PIIX4_XBCS		0x4E	/* 16 bit XBus Chip select reg (default 0x0003) */
-#define	PCI_CFG_PIIX4_PIRQC		0x60  /* PCI IRQ Route Register 4 x 8bit (default )*/
-#define	PCI_CFG_PIIX4_SERIRQ	0x64
-#define	PCI_CFG_PIIX4_TOM			0x69
-#define	PCI_CFG_PIIX4_MSTAT		0x6A
-#define	PCI_CFG_PIIX4_MBDMA		0x76
-#define	PCI_CFG_PIIX4_APICBS	0x80
-#define	PCI_CFG_PIIX4_DLC			0x82
-#define	PCI_CFG_PIIX4_PDMACFG	0x90
-#define	PCI_CFG_PIIX4_DDMABS	0x92
-#define	PCI_CFG_PIIX4_GENCFG	0xB0
-#define	PCI_CFG_PIIX4_RTCCFG	0xCB
-
-/* IO Addresses */
-#define PIIX4_ISA_DMA1_CH0BA	0x00
-#define PIIX4_ISA_DMA1_CH0CA	0x01
-#define PIIX4_ISA_DMA1_CH1BA	0x02
-#define PIIX4_ISA_DMA1_CH1CA	0x03
-#define PIIX4_ISA_DMA1_CH2BA	0x04
-#define PIIX4_ISA_DMA1_CH2CA	0x05
-#define PIIX4_ISA_DMA1_CH3BA	0x06
-#define PIIX4_ISA_DMA1_CH3CA	0x07
-#define PIIX4_ISA_DMA1_CMDST	0x08
-#define PIIX4_ISA_DMA1_REQ		0x09
-#define PIIX4_ISA_DMA1_WSBM		0x0A
-#define PIIX4_ISA_DMA1_CH_MOD	0x0B
-#define PIIX4_ISA_DMA1_CLR_PT	0x0C
-#define PIIX4_ISA_DMA1_M_CLR	0x0D
-#define PIIX4_ISA_DMA1_CLR_M	0x0E
-#define PIIX4_ISA_DMA1_RWAMB	0x0F
-
-#define PIIX4_ISA_DMA2_CH0BA	0xC0
-#define PIIX4_ISA_DMA2_CH0CA	0xC1
-#define PIIX4_ISA_DMA2_CH1BA	0xC2
-#define PIIX4_ISA_DMA2_CH1CA	0xC3
-#define PIIX4_ISA_DMA2_CH2BA	0xC4
-#define PIIX4_ISA_DMA2_CH2CA	0xC5
-#define PIIX4_ISA_DMA2_CH3BA	0xC6
-#define PIIX4_ISA_DMA2_CH3CA	0xC7
-#define PIIX4_ISA_DMA2_CMDST	0xD0
-#define PIIX4_ISA_DMA2_REQ		0xD2
-#define PIIX4_ISA_DMA2_WSBM		0xD4
-#define PIIX4_ISA_DMA2_CH_MOD	0xD6
-#define PIIX4_ISA_DMA2_CLR_PT	0xD8
-#define PIIX4_ISA_DMA2_M_CLR	0xDA
-#define PIIX4_ISA_DMA2_CLR_M	0xDC
-#define PIIX4_ISA_DMA2_RWAMB	0xDE
-
-#define PIIX4_ISA_INT1_ICW1		0x20
-#define PIIX4_ISA_INT1_OCW2		0x20
-#define PIIX4_ISA_INT1_OCW3		0x20
-#define PIIX4_ISA_INT1_ICW2		0x21
-#define PIIX4_ISA_INT1_ICW3		0x21
-#define PIIX4_ISA_INT1_ICW4		0x21
-#define PIIX4_ISA_INT1_OCW1		0x21
-
-#define PIIX4_ISA_INT1_ELCR		0x4D0
-
-#define PIIX4_ISA_INT2_ICW1		0xA0
-#define PIIX4_ISA_INT2_OCW2		0xA0
-#define PIIX4_ISA_INT2_OCW3		0xA0
-#define PIIX4_ISA_INT2_ICW2		0xA1
-#define PIIX4_ISA_INT2_ICW3		0xA1
-#define PIIX4_ISA_INT2_ICW4		0xA1
-#define PIIX4_ISA_INT2_OCW1		0xA1
-#define PIIX4_ISA_INT2_IMR		0xA1 /* read only */
-
-#define PIIX4_ISA_INT2_ELCR		0x4D1
-
-#define PIIX4_ISA_TMR0_CNT_ST	0x40
-#define PIIX4_ISA_TMR1_CNT_ST	0x41
-#define PIIX4_ISA_TMR2_CNT_ST	0x42
-#define PIIX4_ISA_TMR_TCW			0x43
-
-#define PIIX4_ISA_RST_XBUS		0x60
-
-#define PIIX4_ISA_NMI_CNT_ST	0x61
-#define PIIX4_ISA_NMI_ENABLE	0x70
-
-#define PIIX4_ISA_RTC_INDEX		0x70
-#define PIIX4_ISA_RTC_DATA		0x71
-#define PIIX4_ISA_RTCEXT_IND	0x70
-#define PIIX4_ISA_RTCEXT_DATA	0x71
-
-#define PIIX4_ISA_DMA1_CH2LPG	0x81
-#define PIIX4_ISA_DMA1_CH3LPG	0x82
-#define PIIX4_ISA_DMA1_CH1LPG	0x83
-#define PIIX4_ISA_DMA1_CH0LPG	0x87
-#define PIIX4_ISA_DMA2_CH2LPG	0x89
-#define PIIX4_ISA_DMA2_CH3LPG	0x8A
-#define PIIX4_ISA_DMA2_CH1LPG	0x8B
-#define PIIX4_ISA_DMA2_LPGRFR	0x8F
-
-#define PIIX4_ISA_PORT_92			0x92
-
-#define PIIX4_ISA_APM_CONTRL	0xB2
-#define PIIX4_ISA_APM_STATUS	0xB3
-
-#define PIIX4_ISA_COCPU_ERROR	0xF0
-
-/* Function 1 IDE Controller */
-#define	PCI_CFG_PIIX4_BMIBA		0x20
-#define	PCI_CFG_PIIX4_IDETIM	0x40
-#define	PCI_CFG_PIIX4_SIDETIM	0x44
-#define	PCI_CFG_PIIX4_UDMACTL	0x48
-#define	PCI_CFG_PIIX4_UDMATIM 0x4A
-
-/* Function 2 USB Controller */
-#define	PCI_CFG_PIIX4_SBRNUM	0x60
-#define	PCI_CFG_PIIX4_LEGSUP	0xC0
-
-/* Function 3 Power Management */
-#define	PCI_CFG_PIIX4_PMBA		0x40
-#define	PCI_CFG_PIIX4_CNTA		0x44
-#define	PCI_CFG_PIIX4_CNTB		0x48
-#define	PCI_CFG_PIIX4_GPICTL	0x4C
-#define	PCI_CFG_PIIX4_DEVRESD	0x50
-#define	PCI_CFG_PIIX4_DEVACTA	0x54
-#define	PCI_CFG_PIIX4_DEVACTB	0x58
-#define	PCI_CFG_PIIX4_DEVRESA	0x5C
-#define	PCI_CFG_PIIX4_DEVRESB	0x60
-#define	PCI_CFG_PIIX4_DEVRESC	0x64
-#define	PCI_CFG_PIIX4_DEVRESE	0x68
-#define	PCI_CFG_PIIX4_DEVRESF	0x6C
-#define	PCI_CFG_PIIX4_DEVRESG	0x70
-#define	PCI_CFG_PIIX4_DEVRESH	0x74
-#define	PCI_CFG_PIIX4_DEVRESI	0x78
-#define	PCI_CFG_PIIX4_PMMISC	0x80
-#define	PCI_CFG_PIIX4_SMBBA	0x90
-
-
-#endif
diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c
deleted file mode 100644
index 8399407..0000000
--- a/board/mpl/common/usb_uhci.c
+++ /dev/null
@@ -1,1042 +0,0 @@
-/*
- * Part of this code has been derived from linux:
- * Universal Host Controller Interface driver for USB (take II).
- *
- * (c) 1999-2001 Georg Acher, acher@in.tum.de (executive slave) (base guitar)
- *               Deti Fliegl, deti@fliegl.de (executive slave) (lead voice)
- *               Thomas Sailer, sailer@ife.ee.ethz.ch (chief consultant) (cheer leader)
- *               Roman Weissgaerber, weissg@vienna.at (virt root hub) (studio porter)
- * (c) 2000      Yggdrasil Computing, Inc. (port of new PCI interface support
- *               from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
- * (C) 2000      David Brownell, david-b@pacbell.net (usb-ohci.c)
- *
- * HW-initalization based on material of
- *
- * (C) Copyright 1999 Linus Torvalds
- * (C) Copyright 1999 Johannes Erdfelt
- * (C) Copyright 1999 Randy Dunlap
- * (C) Copyright 1999 Gregory P. Smith
- *
- *
- * Adapted for U-Boot:
- * (C) Copyright 2001 Denis Peter, MPL AG Switzerland
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/**********************************************************************
- * How it works:
- * -------------
- * The framelist / Transfer descriptor / Queue Heads are similar like
- * in the linux usb_uhci.c.
- *
- * During initialization, the following skeleton is allocated in init_skel:
- *
- *         framespecific           |           common chain
- *
- * framelist[]
- * [  0 ]-----> TD ---------\
- * [  1 ]-----> TD ----------> TD ------> QH -------> QH -------> QH ---> NULL
- *   ...        TD ---------/
- * [1023]-----> TD --------/
- *
- *              ^^             ^^         ^^          ^^          ^^
- *              7 TDs for      1 TD for   Start of    Start of    End Chain
- *              INT (2-128ms)  1ms-INT    CTRL Chain  BULK Chain
- *
- *
- * Since this is a bootloader, the isochronous transfer descriptor have been removed.
- *
- * Interrupt Transfers.
- * --------------------
- * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
- * will be inserted after the appropriate (depending the interval setting) skeleton TD.
- * If an interrupt has been detected the dev->irqhandler is called. The status and number
- * of transferred bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
- * dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned,
- * the interrupt TD will be reactivated.
- *
- * Control Transfers
- * -----------------
- * Control Transfers are issued by filling the tmp_td with the appropriate data and connect
- * them to the qh_cntrl queue header. Before other control/bulk transfers can be issued,
- * the programm has to wait for completion. This does not allows asynchronous data transfer.
- *
- * Bulk Transfers
- * --------------
- * Bulk Transfers are issued by filling the tmp_td with the appropriate data and connect
- * them to the qh_bulk queue header. Before other control/bulk transfers can be issued,
- * the programm has to wait for completion. This does not allows asynchronous data transfer.
- *
- *
- */
-
-#include <common.h>
-#include <pci.h>
-
-#ifdef CONFIG_USB_UHCI
-
-#include <usb.h>
-#include "usb_uhci.h"
-
-#define USB_MAX_TEMP_TD      128  /* number of temporary TDs for bulk and control transfers */
-#define USB_MAX_TEMP_INT_TD  32   /* number of temporary TDs for Interrupt transfers */
-
-
-#undef USB_UHCI_DEBUG
-
-#ifdef	USB_UHCI_DEBUG
-#define	USB_UHCI_PRINTF(fmt,args...)	printf (fmt ,##args)
-#else
-#define USB_UHCI_PRINTF(fmt,args...)
-#endif
-
-
-static int irqvec = -1;            /* irq vector, if -1 uhci is stopped / reseted */
-unsigned int usb_base_addr;       /* base address */
-
-static uhci_td_t td_int[8];        /* Interrupt Transfer descriptors */
-static uhci_qh_t qh_cntrl;         /* control Queue Head */
-static uhci_qh_t qh_bulk;          /*  bulk Queue Head */
-static uhci_qh_t qh_end;           /* end Queue Head */
-static uhci_td_t td_last;          /* last TD (linked with end chain) */
-
-/* temporary tds */
-static uhci_td_t tmp_td[USB_MAX_TEMP_TD];          /* temporary bulk/control td's  */
-static uhci_td_t tmp_int_td[USB_MAX_TEMP_INT_TD];  /* temporary interrupt td's  */
-
-static unsigned long framelist[1024] __attribute__ ((aligned (0x1000))); /* frame list */
-
-static struct virt_root_hub rh;   /* struct for root hub */
-
-/**********************************************************************
- * some forward decleration
- */
-int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
-						void *buffer, int transfer_len,struct devrequest *setup);
-
-/* fill a td with the approproiate data. Link, status, info and buffer
- * are used by the USB controller itselfes, dev is used to identify the
- * "connected" device
- */
-void usb_fill_td(uhci_td_t* td,unsigned long link,unsigned long status,
-					unsigned long info, unsigned long buffer, unsigned long dev)
-{
-	td->link=swap_32(link);
-	td->status=swap_32(status);
-	td->info=swap_32(info);
-	td->buffer=swap_32(buffer);
-	td->dev_ptr=dev;
-}
-
-/* fill a qh with the approproiate data. Head and element are used by the USB controller
- * itselfes. As soon as a valid dev_ptr is filled, a td chain is connected to the qh.
- * Please note, that after completion of the td chain, the entry element is removed /
- * marked invalid by the USB controller.
- */
-void usb_fill_qh(uhci_qh_t* qh,unsigned long head,unsigned long element)
-{
-	qh->head=swap_32(head);
-	qh->element=swap_32(element);
-	qh->dev_ptr=0L;
-}
-
-/* get the status of a td->status
- */
-unsigned long usb_uhci_td_stat(unsigned long status)
-{
-	unsigned long result=0;
-	result |= (status & TD_CTRL_NAK)      ? USB_ST_NAK_REC : 0;
-	result |= (status & TD_CTRL_STALLED)  ? USB_ST_STALLED : 0;
-	result |= (status & TD_CTRL_DBUFERR)  ? USB_ST_BUF_ERR : 0;
-	result |= (status & TD_CTRL_BABBLE)   ? USB_ST_BABBLE_DET : 0;
-	result |= (status & TD_CTRL_CRCTIMEO) ? USB_ST_CRC_ERR : 0;
-	result |= (status & TD_CTRL_BITSTUFF) ? USB_ST_BIT_ERR : 0;
-	result |= (status & TD_CTRL_ACTIVE)   ? USB_ST_NOT_PROC : 0;
-	return result;
-}
-
-/* get the status and the transferred len of a td chain.
- * called from the completion handler
- */
-int usb_get_td_status(uhci_td_t *td,struct usb_device *dev)
-{
-	unsigned long temp,info;
-	unsigned long stat;
-	uhci_td_t *mytd=td;
-
-	if(dev->devnum==rh.devnum)
-		return 0;
-	dev->act_len=0;
-	stat=0;
-	do {
-		temp=swap_32((unsigned long)mytd->status);
-		stat=usb_uhci_td_stat(temp);
-		info=swap_32((unsigned long)mytd->info);
-		if(((info & 0xff)!= USB_PID_SETUP) &&
-				(((info >> 21) & 0x7ff)!= 0x7ff) &&
-				(temp & 0x7FF)!=0x7ff)
-		{  /* if not setup and not null data pack */
-			dev->act_len+=(temp & 0x7FF) + 1; /* the transferred len is act_len + 1 */
-		}
-		if(stat) {           /* status no ok */
-			dev->status=stat;
-			return -1;
-		}
-		temp=swap_32((unsigned long)mytd->link);
-		mytd=(uhci_td_t *)(temp & 0xfffffff0);
-	}while((temp & 0x1)==0); /* process all TDs */
-	dev->status=stat;
-	return 0; /* Ok */
-}
-
-
-/*-------------------------------------------------------------------
- *                         LOW LEVEL STUFF
- *          assembles QHs und TDs for control, bulk and iso
- *-------------------------------------------------------------------*/
-
-/* Submits a control message. That is a Setup, Data and Status transfer.
- * Routine does not wait for completion.
- */
-int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-										int transfer_len,struct devrequest *setup)
-{
-	unsigned long destination, status;
-	int maxsze = usb_maxpacket(dev, pipe);
-	unsigned long dataptr;
-	int len;
-	int pktsze;
-	int i=0;
-
-	if (!maxsze) {
-		USB_UHCI_PRINTF("uhci_submit_control_urb: pipesize for pipe %lx is zero\n", pipe);
-		return -1;
-	}
-	if(((pipe>>8)&0x7f)==rh.devnum) {
-		/* this is the root hub -> redirect it */
-		return uhci_submit_rh_msg(dev,pipe,buffer,transfer_len,setup);
-	}
-	USB_UHCI_PRINTF("uhci_submit_control start len %x, maxsize %x\n",transfer_len,maxsze);
-	/* The "pipe" thing contains the destination in bits 8--18 */
-	destination = (pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP; /* Setup stage */
-	/* 3 errors */
-	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
-	/* (urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD); */
-	/*  Build the TD for the control request, try forever, 8 bytes of data */
-	usb_fill_td(&tmp_td[i],UHCI_PTR_TERM ,status, destination | (7 << 21),(unsigned long)setup,(unsigned long)dev);
-#if 0
-	{
-		char *sp=(char *)setup;
-		printf("SETUP to pipe %lx: %x %x %x %x %x %x %x %x\n", pipe,
-		    sp[0],sp[1],sp[2],sp[3],sp[4],sp[5],sp[6],sp[7]);
-	}
-#endif
-	dataptr = (unsigned long)buffer;
-	len=transfer_len;
-
-	/* If direction is "send", change the frame from SETUP (0x2D)
-	   to OUT (0xE1). Else change it from SETUP to IN (0x69). */
-	destination = (pipe & PIPE_DEVEP_MASK) | ((pipe & USB_DIR_IN)==0 ? USB_PID_OUT : USB_PID_IN);
-	while (len > 0) {
-		/* data stage */
-		pktsze = len;
-		i++;
-		if (pktsze > maxsze)
-			pktsze = maxsze;
-		destination ^= 1 << TD_TOKEN_TOGGLE;	/* toggle DATA0/1 */
-		usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, destination | ((pktsze - 1) << 21),dataptr,(unsigned long)dev);	/* Status, pktsze bytes of data */
-		tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);
-
-		dataptr += pktsze;
-		len -= pktsze;
-	}
-
-	/*  Build the final TD for control status */
-	/* It's only IN if the pipe is out AND we aren't expecting data */
-
-	destination &= ~UHCI_PID;
-	if (((pipe & USB_DIR_IN)==0) || (transfer_len == 0))
-		destination |= USB_PID_IN;
-	else
-		destination |= USB_PID_OUT;
-	destination |= 1 << TD_TOKEN_TOGGLE;	/* End in Data1 */
-	i++;
-	status &=~TD_CTRL_SPD;
-	/* no limit on errors on final packet , 0 bytes of data */
-	usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status | TD_CTRL_IOC, destination | (UHCI_NULL_DATA_SIZE << 21),0,(unsigned long)dev);
-	tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);	/* queue status td */
-	/*	usb_show_td(i+1);*/
-	USB_UHCI_PRINTF("uhci_submit_control end (%d tmp_tds used)\n",i);
-	/* first mark the control QH element terminated */
-	qh_cntrl.element=0xffffffffL;
-	/* set qh active */
-	qh_cntrl.dev_ptr=(unsigned long)dev;
-	/* fill in tmp_td_chain */
-	qh_cntrl.element=swap_32((unsigned long)&tmp_td[0]);
-	return 0;
-}
-
-/*-------------------------------------------------------------------
- * Prepare TDs for bulk transfers.
- */
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len)
-{
-	unsigned long destination, status,info;
-	unsigned long dataptr;
-	int maxsze = usb_maxpacket(dev, pipe);
-	int len;
-	int i=0;
-
-	if(transfer_len < 0) {
-		printf("Negative transfer length in submit_bulk\n");
-		return -1;
-	}
-	if (!maxsze)
-		return -1;
-	/* The "pipe" thing contains the destination in bits 8--18. */
-	destination = (pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe);
-	/* 3 errors */
-	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | (3 << 27);
-	/*	((urb->transfer_flags & USB_DISABLE_SPD) ? 0 : TD_CTRL_SPD) | (3 << 27); */
-	/* Build the TDs for the bulk request */
-	len = transfer_len;
-	dataptr = (unsigned long)buffer;
-	do {
-		int pktsze = len;
-		if (pktsze > maxsze)
-			pktsze = maxsze;
-		/* pktsze bytes of data  */
-		info = destination | (((pktsze - 1)&UHCI_NULL_DATA_SIZE) << 21) |
-			(usb_gettoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe)) << TD_TOKEN_TOGGLE);
-
-		if((len-pktsze)==0)
-			status |= TD_CTRL_IOC;	/* last one generates INT */
-
-		usb_fill_td(&tmp_td[i],UHCI_PTR_TERM, status, info,dataptr,(unsigned long)dev);	/* Status, pktsze bytes of data */
-		if(i>0)
-			tmp_td[i-1].link=swap_32((unsigned long)&tmp_td[i]);
-		i++;
-		dataptr += pktsze;
-		len -= pktsze;
-		usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe));
-	} while (len > 0);
-	/* first mark the bulk QH element terminated */
-	qh_bulk.element=0xffffffffL;
-	/* set qh active */
-	qh_bulk.dev_ptr=(unsigned long)dev;
-	/* fill in tmp_td_chain */
-	qh_bulk.element=swap_32((unsigned long)&tmp_td[0]);
-	return 0;
-}
-
-
-/* search a free interrupt td
- */
-uhci_td_t *uhci_alloc_int_td(void)
-{
-	int i;
-	for(i=0;i<USB_MAX_TEMP_INT_TD;i++) {
-		if(tmp_int_td[i].dev_ptr==0) /* no device assigned -> free TD */
-			return &tmp_int_td[i];
-	}
-	return NULL;
-}
-
-#if 0
-void uhci_show_temp_int_td(void)
-{
-	int i;
-	for(i=0;i<USB_MAX_TEMP_INT_TD;i++) {
-		if((tmp_int_td[i].dev_ptr&0x01)!=0x1L) /* no device assigned -> free TD */
-			printf("temp_td %d is assigned to dev %lx\n",i,tmp_int_td[i].dev_ptr);
-	}
-	printf("all others temp_tds are free\n");
-}
-#endif
-/*-------------------------------------------------------------------
- * submits USB interrupt (ie. polling ;-)
- */
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len, int interval)
-{
-	int nint, n;
-	unsigned long status, destination;
-	unsigned long info,tmp;
-	uhci_td_t *mytd;
-	if (interval < 0 || interval >= 256)
-		return -1;
-
-	if (interval == 0)
-		nint = 0;
-	else {
-		for (nint = 0, n = 1; nint <= 8; nint++, n += n)	/* round interval down to 2^n */
-		 {
-			if(interval < n) {
-				interval = n / 2;
-				break;
-			}
-		}
-		nint--;
-	}
-
-	USB_UHCI_PRINTF("Rounded interval to %i, chain  %i\n", interval, nint);
-	mytd=uhci_alloc_int_td();
-	if(mytd==NULL) {
-		printf("No free INT TDs found\n");
-		return -1;
-	}
-	status = (pipe & TD_CTRL_LS) | TD_CTRL_ACTIVE | TD_CTRL_IOC | (3 << 27);
-/*		(urb->transfer_flags & USB_DISABLE_SPD ? 0 : TD_CTRL_SPD) | (3 << 27);
-*/
-
-	destination =(pipe & PIPE_DEVEP_MASK) | usb_packetid (pipe) | (((transfer_len - 1) & 0x7ff) << 21);
-
-	info = destination | (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)) << TD_TOKEN_TOGGLE);
-	tmp = swap_32(td_int[nint].link);
-	usb_fill_td(mytd,tmp,status, info,(unsigned long)buffer,(unsigned long)dev);
-	/* Link it */
-	tmp = swap_32((unsigned long)mytd);
-	td_int[nint].link=tmp;
-
-	usb_dotoggle (dev, usb_pipeendpoint (pipe), usb_pipeout (pipe));
-
-	return 0;
-}
-
-/**********************************************************************
- * Low Level functions
- */
-
-
-void reset_hc(void)
-{
-
-	/* Global reset for 100ms */
-	out16r( usb_base_addr + USBPORTSC1,0x0204);
-	out16r( usb_base_addr + USBPORTSC2,0x0204);
-	out16r( usb_base_addr + USBCMD,USBCMD_GRESET | USBCMD_RS);
-	/* Turn off all interrupts */
-	out16r(usb_base_addr + USBINTR,0);
-	mdelay(50);
-	out16r( usb_base_addr + USBCMD,0);
-	mdelay(10);
-}
-
-void start_hc(void)
-{
-	int timeout = 1000;
-
-	while(in16r(usb_base_addr + USBCMD) & USBCMD_HCRESET) {
-		if (!--timeout) {
-			printf("USBCMD_HCRESET timed out!\n");
-			break;
-		}
-	}
-	/* Turn on all interrupts */
-	out16r(usb_base_addr + USBINTR,USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP);
-	/* Start at frame 0 */
-	out16r(usb_base_addr + USBFRNUM,0);
-	/* set Framebuffer base address */
-	out32r(usb_base_addr+USBFLBASEADD,(unsigned long)&framelist);
-	/* Run and mark it configured with a 64-byte max packet */
-	out16r(usb_base_addr + USBCMD,USBCMD_RS | USBCMD_CF | USBCMD_MAXP);
-}
-
-/* Initialize the skeleton
- */
-void usb_init_skel(void)
-{
-	unsigned long temp;
-	int n;
-
-	for(n=0;n<USB_MAX_TEMP_INT_TD;n++)
-		tmp_int_td[n].dev_ptr=0L; /* no devices connected */
-	/* last td */
-	usb_fill_td(&td_last,UHCI_PTR_TERM,TD_CTRL_IOC ,0,0,0L);
-  /* usb_fill_td(&td_last,UHCI_PTR_TERM,0,0,0); */
-	/* End Queue Header */
-	usb_fill_qh(&qh_end,UHCI_PTR_TERM,(unsigned long)&td_last);
-	/* Bulk Queue Header */
-	temp=(unsigned long)&qh_end;
-	usb_fill_qh(&qh_bulk,temp | UHCI_PTR_QH,UHCI_PTR_TERM);
-	/* Control Queue Header */
-	temp=(unsigned long)&qh_bulk;
-	usb_fill_qh(&qh_cntrl, temp | UHCI_PTR_QH,UHCI_PTR_TERM);
-	/* 1ms Interrupt td */
-	temp=(unsigned long)&qh_cntrl;
-	usb_fill_td(&td_int[0],temp | UHCI_PTR_QH,0,0,0,0L);
-	temp=(unsigned long)&td_int[0];
-	for(n=1; n<8; n++)
-		usb_fill_td(&td_int[n],temp,0,0,0,0L);
-	for (n = 0; n < 1024; n++) {
-	/* link all framelist pointers to one of the interrupts */
-		int m, o;
-		if ((n&127)==127)
-			framelist[n]= swap_32((unsigned long)&td_int[0]);
-		else
-			for (o = 1, m = 2; m <= 128; o++, m += m)
-				if ((n & (m - 1)) == ((m - 1) / 2))
-						framelist[n]= swap_32((unsigned long)&td_int[o]);
-	}
-}
-
-/* check the common skeleton for completed transfers, and update the status
- * of the "connected" device. Called from the IRQ routine.
- */
-void usb_check_skel(void)
-{
-	struct usb_device *dev;
-	/* start with the control qh */
-	if(qh_cntrl.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */
-	{
-		dev=(struct usb_device *)qh_cntrl.dev_ptr;
-		usb_get_td_status(&tmp_td[0],dev); /* update status */
-		if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
-			qh_cntrl.dev_ptr=0;
-		}
-	}
-	/* now process the bulk */
-	if(qh_bulk.dev_ptr!=0) /* it's a device assigned check if this caused IRQ */
-	{
-		dev=(struct usb_device *)qh_bulk.dev_ptr;
-		usb_get_td_status(&tmp_td[0],dev); /* update status */
-		if(!(dev->status & USB_ST_NOT_PROC)) { /* is not active anymore, disconnect devices */
-			qh_bulk.dev_ptr=0;
-		}
-	}
-}
-
-/* check the interrupt chain, ubdate the status of the appropriate device,
- * call the appropriate irqhandler and reactivate the TD if the irqhandler
- * returns with 1
- */
-void usb_check_int_chain(void)
-{
-	int i,res;
-	unsigned long link,status;
-	struct usb_device *dev;
-	uhci_td_t *td,*prevtd;
-
-	for(i=0;i<8;i++) {
-		prevtd = &td_int[i]; /* the first previous td is the skeleton td */
-		link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */
-		td=(uhci_td_t *)link; /* assign it */
-		/* all interrupt TDs are finally linked to the td_int[0].
-		 * so we process all until we find the td_int[0].
-		 * if int0 chain points to a QH, we're also done
-	   */
-		while(((i>0) && (link != (unsigned long)&td_int[0])) ||
-					((i==0) && !(swap_32(td->link) &  UHCI_PTR_QH)))
-		{
-			/* check if a device is assigned with this td */
-			status=swap_32(td->status);
-			if((td->dev_ptr!=0L) && !(status & TD_CTRL_ACTIVE)) {
-				/* td is not active and a device is assigned -> call irqhandler */
-				dev=(struct usb_device *)td->dev_ptr;
-				dev->irq_act_len=((status & 0x7FF)==0x7FF) ? 0 : (status & 0x7FF) + 1; /* transferred length */
-				dev->irq_status=usb_uhci_td_stat(status); /* get status */
-				res=dev->irq_handle(dev); /* call irqhandler */
-				if(res==1) {
-					/* reactivate */
-					status|=TD_CTRL_ACTIVE;
-					td->status=swap_32(status);
-					prevtd=td; /* previous td = this td */
-				}
-				else {
-					prevtd->link=td->link; /* link previous td directly to the nex td -> unlinked */
-					/* remove device pointer */
-					td->dev_ptr=0L;
-				}
-			} /* if we call the irq handler */
-			link=swap_32(td->link) & 0xfffffff0; /* next in chain */
-			td=(uhci_td_t *)link; /* assign it */
-		} /* process all td in this int chain */
-	} /* next interrupt chain */
-}
-
-
-/* usb interrupt service routine.
- */
-void handle_usb_interrupt(void)
-{
-	unsigned short status;
-
-	/*
-	 * Read the interrupt status, and write it back to clear the
-	 * interrupt cause
-	 */
-
-	status = in16r(usb_base_addr + USBSTS);
-
-	if (!status)		/* shared interrupt, not mine */
-		return;
-	if (status != 1) {
-		/* remove host controller halted state */
-		if ((status&0x20) && ((in16r(usb_base_addr+USBCMD) && USBCMD_RS)==0)) {
-			out16r(usb_base_addr + USBCMD, USBCMD_RS | in16r(usb_base_addr + USBCMD));
-		}
-	}
-	usb_check_int_chain(); /* call interrupt handlers for int tds */
-	usb_check_skel(); /* call completion handler for common transfer routines */
-	out16r(usb_base_addr+USBSTS,status);
-}
-
-
-/* init uhci
- */
-int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
-{
-	unsigned char temp;
-	int	busdevfunc;
-
-	busdevfunc=pci_find_device(USB_UHCI_VEND_ID,USB_UHCI_DEV_ID,0); /* get PCI Device ID */
-	if(busdevfunc==-1) {
-		printf("Error USB UHCI (%04X,%04X) not found\n",USB_UHCI_VEND_ID,USB_UHCI_DEV_ID);
-		return -1;
-	}
-	pci_read_config_byte(busdevfunc,PCI_INTERRUPT_LINE,&temp);
-	irqvec = temp;
-	irq_free_handler(irqvec);
-	USB_UHCI_PRINTF("Interrupt Line = %d, is %d\n",irqvec);
-	pci_read_config_byte(busdevfunc,PCI_INTERRUPT_PIN,&temp);
-	USB_UHCI_PRINTF("Interrupt Pin = %ld\n",temp);
-	pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr);
-	USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr);
-	usb_base_addr&=0xFFFFFFF0;
-	usb_base_addr+=CONFIG_SYS_ISA_IO_BASE_ADDRESS;
-	rh.devnum = 0;
-	usb_init_skel();
-	reset_hc();
-	start_hc();
-	irq_install_handler(irqvec, (interrupt_handler_t *)handle_usb_interrupt, NULL);
-	return 0;
-}
-
-/* stop uhci
- */
-int usb_lowlevel_stop(int index)
-{
-	if(irqvec==-1)
-		return 1;
-	irq_free_handler(irqvec);
-	reset_hc();
-	irqvec = -1;
-	return 0;
-}
-
-/*******************************************************************************************
- * Virtual Root Hub
- * Since the uhci does not have a real HUB, we simulate one ;-)
- */
-#undef	USB_RH_DEBUG
-
-#ifdef	USB_RH_DEBUG
-#define	USB_RH_PRINTF(fmt,args...)	printf (fmt ,##args)
-static void usb_display_wValue(unsigned short wValue,unsigned short wIndex);
-static void usb_display_Req(unsigned short req);
-#else
-#define USB_RH_PRINTF(fmt,args...)
-static void usb_display_wValue(unsigned short wValue,unsigned short wIndex) {}
-static void usb_display_Req(unsigned short req) {}
-#endif
-
-#define WANT_USB_ROOT_HUB_HUB_DES
-#include <usbroothubdes.h>
-#undef WANT_USB_ROOT_HUB_HUB_DES
-
-/*
- * Root Hub Control Pipe (interrupt Pipes are not supported)
- */
-
-
-int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len,struct devrequest *cmd)
-{
-	void *data = buffer;
-	int leni = transfer_len;
-	int len = 0;
-	int status = 0;
-	int stat = 0;
-	int i;
-
-	unsigned short cstatus;
-
-	unsigned short bmRType_bReq;
-	unsigned short wValue;
-	unsigned short wIndex;
-	unsigned short wLength;
-
-	if (usb_pipeint(pipe)) {
-		printf("Root-Hub submit IRQ: NOT implemented\n");
-#if 0
-		uhci->rh.urb = urb;
-		uhci->rh.send = 1;
-		uhci->rh.interval = urb->interval;
-		rh_init_int_timer (urb);
-#endif
-		return 0;
-	}
-	bmRType_bReq = cmd->requesttype | cmd->request << 8;
-	wValue = swap_16(cmd->value);
-	wIndex = swap_16(cmd->index);
-	wLength = swap_16(cmd->length);
-	usb_display_Req(bmRType_bReq);
-	for (i = 0; i < 8; i++)
-		rh.c_p_r[i] = 0;
-	USB_RH_PRINTF("Root-Hub: adr: %2x cmd(%1x): %02x%02x %04x %04x %04x\n",
-	     dev->devnum, 8, cmd->requesttype,cmd->request, wValue, wIndex, wLength);
-
-	switch (bmRType_bReq) {
-		/* Request Destination:
-		   without flags: Device,
-		   RH_INTERFACE: interface,
-		   RH_ENDPOINT: endpoint,
-		   RH_CLASS means HUB here,
-		   RH_OTHER | RH_CLASS  almost ever means HUB_PORT here
-		 */
-
-	case RH_GET_STATUS:
-		*(unsigned short *) data = swap_16(1);
-		len=2;
-		break;
-	case RH_GET_STATUS | RH_INTERFACE:
-		*(unsigned short *) data = swap_16(0);
-		len=2;
-		break;
-	case RH_GET_STATUS | RH_ENDPOINT:
-		*(unsigned short *) data = swap_16(0);
-		len=2;
-		break;
-	case RH_GET_STATUS | RH_CLASS:
-		*(unsigned long *) data = swap_32(0);
-		len=4;
-		break;	/* hub power ** */
-	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
-
-		status = in16r(usb_base_addr + USBPORTSC1 + 2 * (wIndex - 1));
-		cstatus = ((status & USBPORTSC_CSC) >> (1 - 0)) |
-			((status & USBPORTSC_PEC) >> (3 - 1)) |
-			(rh.c_p_r[wIndex - 1] << (0 + 4));
-		status = (status & USBPORTSC_CCS) |
-			((status & USBPORTSC_PE) >> (2 - 1)) |
-			((status & USBPORTSC_SUSP) >> (12 - 2)) |
-			((status & USBPORTSC_PR) >> (9 - 4)) |
-			(1 << 8) |	/* power on ** */
-			((status & USBPORTSC_LSDA) << (-8 + 9));
-
-		*(unsigned short *) data = swap_16(status);
-		*(unsigned short *) (data + 2) = swap_16(cstatus);
-		len=4;
-		break;
-	case RH_CLEAR_FEATURE | RH_ENDPOINT:
-		switch (wValue) {
-		case (RH_ENDPOINT_STALL):
-			len=0;
-			break;
-		}
-		break;
-
-	case RH_CLEAR_FEATURE | RH_CLASS:
-		switch (wValue) {
-		case (RH_C_HUB_OVER_CURRENT):
-			len=0;	/* hub power over current ** */
-			break;
-		}
-		break;
-
-	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
-		usb_display_wValue(wValue,wIndex);
-		switch (wValue) {
-		case (RH_PORT_ENABLE):
-			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
-			status = (status & 0xfff5) & ~USBPORTSC_PE;
-			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
-			len=0;
-			break;
-		case (RH_PORT_SUSPEND):
-			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
-			status = (status & 0xfff5) & ~USBPORTSC_SUSP;
-			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
-			len=0;
-			break;
-		case (RH_PORT_POWER):
-			len=0;	/* port power ** */
-			break;
-		case (RH_C_PORT_CONNECTION):
-			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
-			status = (status & 0xfff5) | USBPORTSC_CSC;
-			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
-			len=0;
-			break;
-		case (RH_C_PORT_ENABLE):
-			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
-			status = (status & 0xfff5) | USBPORTSC_PEC;
-			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
-			len=0;
-			break;
-		case (RH_C_PORT_SUSPEND):
-/*** WR_RH_PORTSTAT(RH_PS_PSSC); */
-			len=0;
-			break;
-		case (RH_C_PORT_OVER_CURRENT):
-			len=0;
-			break;
-		case (RH_C_PORT_RESET):
-			rh.c_p_r[wIndex - 1] = 0;
-			len=0;
-			break;
-		}
-		break;
-	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
-		usb_display_wValue(wValue,wIndex);
-		switch (wValue) {
-		case (RH_PORT_SUSPEND):
-			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
-			status = (status & 0xfff5) | USBPORTSC_SUSP;
-			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
-			len=0;
-			break;
-		case (RH_PORT_RESET):
-			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
-			status = (status & 0xfff5) | USBPORTSC_PR;
-			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
-			mdelay(10);
-			status = (status & 0xfff5) & ~USBPORTSC_PR;
-			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
-			udelay(10);
-			status = (status & 0xfff5) | USBPORTSC_PE;
-			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
-			mdelay(10);
-			status = (status & 0xfff5) | 0xa;
-			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
-			len=0;
-			break;
-		case (RH_PORT_POWER):
-			len=0;	/* port power ** */
-			break;
-		case (RH_PORT_ENABLE):
-			status = in16r(usb_base_addr+USBPORTSC1+2*(wIndex-1));
-			status = (status & 0xfff5) | USBPORTSC_PE;
-			out16r(usb_base_addr+USBPORTSC1+2*(wIndex-1),status);
-			len=0;
-			break;
-		}
-		break;
-
-	case RH_SET_ADDRESS:
-		rh.devnum = wValue;
-		len=0;
-		break;
-	case RH_GET_DESCRIPTOR:
-		switch ((wValue & 0xff00) >> 8) {
-		case (0x01):	/* device descriptor */
-			i=sizeof(root_hub_config_des);
-			status=i > wLength ? wLength : i;
-			len = leni > status ? status : leni;
-			memcpy (data, root_hub_dev_des, len);
-			break;
-		case (0x02):	/* configuration descriptor */
-			i=sizeof(root_hub_config_des);
-			status=i > wLength ? wLength : i;
-			len = leni > status ? status : leni;
-			memcpy (data, root_hub_config_des, len);
-			break;
-		case (0x03):	/*string descriptors */
-			if(wValue==0x0300) {
-				i=sizeof(root_hub_str_index0);
-				status = i > wLength ? wLength : i;
-				len = leni > status ? status : leni;
-				memcpy (data, root_hub_str_index0, len);
-				break;
-			}
-			if(wValue==0x0301) {
-				i=sizeof(root_hub_str_index1);
-				status = i > wLength ? wLength : i;
-				len = leni > status ? status : leni;
-				memcpy (data, root_hub_str_index1, len);
-				break;
-			}
-			stat = USB_ST_STALLED;
-		}
-		break;
-
-	case RH_GET_DESCRIPTOR | RH_CLASS:
-		root_hub_hub_des[2] = 2;
-		i=sizeof(root_hub_hub_des);
-		status= i > wLength ? wLength : i;
-		len = leni > status ? status : leni;
-		memcpy (data, root_hub_hub_des, len);
-		break;
-	case RH_GET_CONFIGURATION:
-		*(unsigned char *) data = 0x01;
-		len = 1;
-		break;
-	case RH_SET_CONFIGURATION:
-		len=0;
-		break;
-	default:
-		stat = USB_ST_STALLED;
-	}
-	USB_RH_PRINTF("Root-Hub stat %lx port1: %x port2: %x\n\n",stat,
-	     in16r(usb_base_addr + USBPORTSC1), in16r(usb_base_addr + USBPORTSC2));
-	dev->act_len=len;
-	dev->status=stat;
-	return stat;
-
-}
-
-/********************************************************************************
- * Some Debug Routines
- */
-
-#ifdef	USB_RH_DEBUG
-
-static void usb_display_Req(unsigned short req)
-{
-	USB_RH_PRINTF("- Root-Hub Request: ");
-	switch (req) {
-	case RH_GET_STATUS:
-		USB_RH_PRINTF("Get Status ");
-		break;
-	case RH_GET_STATUS | RH_INTERFACE:
-		USB_RH_PRINTF("Get Status Interface ");
-		break;
-	case RH_GET_STATUS | RH_ENDPOINT:
-		USB_RH_PRINTF("Get Status Endpoint ");
-		break;
-	case RH_GET_STATUS | RH_CLASS:
-		USB_RH_PRINTF("Get Status Class");
-		break;	/* hub power ** */
-	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
-		USB_RH_PRINTF("Get Status Class Others");
-		break;
-	case RH_CLEAR_FEATURE | RH_ENDPOINT:
-		USB_RH_PRINTF("Clear Feature Endpoint ");
-		break;
-	case RH_CLEAR_FEATURE | RH_CLASS:
-		USB_RH_PRINTF("Clear Feature Class ");
-		break;
-	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
-		USB_RH_PRINTF("Clear Feature Other Class ");
-		break;
-	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
-		USB_RH_PRINTF("Set Feature Other Class ");
-		break;
-	case RH_SET_ADDRESS:
-		USB_RH_PRINTF("Set Address ");
-		break;
-	case RH_GET_DESCRIPTOR:
-		USB_RH_PRINTF("Get Descriptor ");
-		break;
-	case RH_GET_DESCRIPTOR | RH_CLASS:
-		USB_RH_PRINTF("Get Descriptor Class ");
-		break;
-	case RH_GET_CONFIGURATION:
-		USB_RH_PRINTF("Get Configuration ");
-		break;
-	case RH_SET_CONFIGURATION:
-		USB_RH_PRINTF("Get Configuration ");
-		break;
-	default:
-		USB_RH_PRINTF("****UNKNOWN**** 0x%04X ",req);
-	}
-	USB_RH_PRINTF("\n");
-
-}
-
-static void usb_display_wValue(unsigned short wValue,unsigned short wIndex)
-{
-	switch (wValue) {
-		case (RH_PORT_ENABLE):
-			USB_RH_PRINTF("Root-Hub: Enable Port %d\n",wIndex);
-			break;
-		case (RH_PORT_SUSPEND):
-			USB_RH_PRINTF("Root-Hub: Suspend Port %d\n",wIndex);
-			break;
-		case (RH_PORT_POWER):
-			USB_RH_PRINTF("Root-Hub: Port Power %d\n",wIndex);
-			break;
-		case (RH_C_PORT_CONNECTION):
-			USB_RH_PRINTF("Root-Hub: C Port Connection Port %d\n",wIndex);
-			break;
-		case (RH_C_PORT_ENABLE):
-			USB_RH_PRINTF("Root-Hub: C Port Enable Port %d\n",wIndex);
-			break;
-		case (RH_C_PORT_SUSPEND):
-			USB_RH_PRINTF("Root-Hub: C Port Suspend Port %d\n",wIndex);
-			break;
-		case (RH_C_PORT_OVER_CURRENT):
-			USB_RH_PRINTF("Root-Hub: C Port Over Current Port %d\n",wIndex);
-			break;
-		case (RH_C_PORT_RESET):
-			USB_RH_PRINTF("Root-Hub: C Port reset Port %d\n",wIndex);
-			break;
-		default:
-			USB_RH_PRINTF("Root-Hub: unknown %x %x\n",wValue,wIndex);
-			break;
-	}
-}
-
-#endif
-
-
-#ifdef	USB_UHCI_DEBUG
-
-static int usb_display_td(uhci_td_t *td)
-{
-	unsigned long tmp;
-	int valid;
-
-	printf("TD at %p:\n",td);
-
-	tmp=swap_32(td->link);
-	printf("Link points to 0x%08lX, %s first, %s, %s\n",tmp&0xfffffff0,
-		((tmp & 0x4)==0x4) ? "Depth" : "Breath",
-		((tmp & 0x2)==0x2) ? "QH" : "TD",
-		((tmp & 0x1)==0x1) ? "invalid" : "valid");
-	valid=((tmp & 0x1)==0x0);
-	tmp=swap_32(td->status);
-	printf("     %s %ld Errors %s %s %s \n     %s %s %s %s %s %s\n     Len 0x%lX\n",
-		(((tmp>>29)&0x1)==0x1) ? "SPD Enable" : "SPD Disable",
-		((tmp>>28)&0x3),
-		(((tmp>>26)&0x1)==0x1) ? "Low Speed" : "Full Speed",
-		(((tmp>>25)&0x1)==0x1) ? "ISO " : "",
-		(((tmp>>24)&0x1)==0x1) ? "IOC " : "",
-		(((tmp>>23)&0x1)==0x1) ? "Active " : "Inactive ",
-		(((tmp>>22)&0x1)==0x1) ? "Stalled" : "",
-		(((tmp>>21)&0x1)==0x1) ? "Data Buffer Error" : "",
-		(((tmp>>20)&0x1)==0x1) ? "Babble" : "",
-		(((tmp>>19)&0x1)==0x1) ? "NAK" : "",
-		(((tmp>>18)&0x1)==0x1) ? "Bitstuff Error" : "",
-		(tmp&0x7ff));
-	tmp=swap_32(td->info);
-	printf("     MaxLen 0x%lX\n",((tmp>>21)&0x7FF));
-	printf("     %s Endpoint 0x%lX Dev Addr 0x%lX PID 0x%lX\n",((tmp>>19)&0x1)==0x1 ? "TOGGLE" : "",
-		((tmp>>15)&0xF),((tmp>>8)&0x7F),tmp&0xFF);
-	tmp=swap_32(td->buffer);
-	printf("     Buffer 0x%08lX\n",tmp);
-	printf("     DEV %08lX\n",td->dev_ptr);
-	return valid;
-}
-
-
-void usb_show_td(int max)
-{
-	int i;
-	if(max>0) {
-		for(i=0;i<max;i++) {
-			usb_display_td(&tmp_td[i]);
-		}
-	}
-	else {
-		i=0;
-		do {
-			printf("tmp_td[%d]\n",i);
-		}while(usb_display_td(&tmp_td[i++]));
-	}
-}
-
-
-#endif
-#endif /* CONFIG_USB_UHCI */
-
-/* EOF */
diff --git a/board/mpl/common/usb_uhci.h b/board/mpl/common/usb_uhci.h
deleted file mode 100644
index 582015f..0000000
--- a/board/mpl/common/usb_uhci.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Note: Part of this code has been derived from linux
- */
-#ifndef _USB_UHCI_H_
-#define _USB_UHCI_H_
-
-
-/* Command register */
-#define USBCMD		0
-#define   USBCMD_RS       0x0001	/* Run/Stop */
-#define   USBCMD_HCRESET  0x0002	/* Host reset */
-#define   USBCMD_GRESET   0x0004	/* Global reset */
-#define   USBCMD_EGSM     0x0008	/* Global Suspend Mode */
-#define   USBCMD_FGR      0x0010	/* Force Global Resume */
-#define   USBCMD_SWDBG    0x0020	/* SW Debug mode */
-#define   USBCMD_CF       0x0040	/* Config Flag (sw only) */
-#define   USBCMD_MAXP     0x0080	/* Max Packet (0 = 32, 1 = 64) */
-
-/* Status register */
-#define USBSTS		2
-#define   USBSTS_USBINT   0x0001	/* Interrupt due to IOC */
-#define   USBSTS_ERROR    0x0002	/* Interrupt due to error */
-#define   USBSTS_RD       0x0004	/* Resume Detect */
-#define   USBSTS_HSE      0x0008	/* Host System Error - basically PCI problems */
-#define   USBSTS_HCPE     0x0010	/* Host Controller Process Error - the scripts were buggy */
-#define   USBSTS_HCH      0x0020	/* HC Halted */
-
-/* Interrupt enable register */
-#define USBINTR		4
-#define   USBINTR_TIMEOUT 0x0001	/* Timeout/CRC error enable */
-#define   USBINTR_RESUME  0x0002	/* Resume interrupt enable */
-#define   USBINTR_IOC     0x0004	/* Interrupt On Complete enable */
-#define   USBINTR_SP      0x0008	/* Short packet interrupt enable */
-
-#define USBFRNUM      6
-#define USBFLBASEADD  8
-#define USBSOF        12
-
-/* USB port status and control registers */
-#define USBPORTSC1	16
-#define USBPORTSC2	18
-#define   USBPORTSC_CCS   0x0001	/* Current Connect Status ("device present") */
-#define   USBPORTSC_CSC   0x0002	/* Connect Status Change */
-#define   USBPORTSC_PE    0x0004	/* Port Enable */
-#define   USBPORTSC_PEC   0x0008	/* Port Enable Change */
-#define   USBPORTSC_LS    0x0030	/* Line Status */
-#define   USBPORTSC_RD    0x0040	/* Resume Detect */
-#define   USBPORTSC_LSDA  0x0100	/* Low Speed Device Attached */
-#define   USBPORTSC_PR    0x0200	/* Port Reset */
-#define   USBPORTSC_SUSP  0x1000	/* Suspend */
-
-/* Legacy support register */
-#define USBLEGSUP 0xc0
-#define USBLEGSUP_DEFAULT 0x2000	/* only PIRQ enable set */
-
-#define UHCI_NULL_DATA_SIZE 0x7ff	/* for UHCI controller TD */
-#define UHCI_PID            0xff	/* PID MASK */
-
-#define UHCI_PTR_BITS       0x000F
-#define UHCI_PTR_TERM       0x0001
-#define UHCI_PTR_QH         0x0002
-#define UHCI_PTR_DEPTH      0x0004
-
-/* for TD <status>: */
-#define TD_CTRL_SPD         (1 << 29)	/* Short Packet Detect */
-#define TD_CTRL_C_ERR_MASK  (3 << 27)	/* Error Counter bits */
-#define TD_CTRL_LS          (1 << 26)	/* Low Speed Device */
-#define TD_CTRL_IOS         (1 << 25)	/* Isochronous Select */
-#define TD_CTRL_IOC         (1 << 24)	/* Interrupt on Complete */
-#define TD_CTRL_ACTIVE      (1 << 23)	/* TD Active */
-#define TD_CTRL_STALLED     (1 << 22)	/* TD Stalled */
-#define TD_CTRL_DBUFERR     (1 << 21)	/* Data Buffer Error */
-#define TD_CTRL_BABBLE      (1 << 20)	/* Babble Detected */
-#define TD_CTRL_NAK         (1 << 19)	/* NAK Received */
-#define TD_CTRL_CRCTIMEO    (1 << 18)	/* CRC/Time Out Error */
-#define TD_CTRL_BITSTUFF    (1 << 17)	/* Bit Stuff Error */
-#define TD_CTRL_ACTLEN_MASK 0x7ff	/* actual length, encoded as n - 1 */
-
-#define TD_CTRL_ANY_ERROR	(TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
-				 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
-
-#define TD_TOKEN_TOGGLE		19
-
-/* ------------------------------------------------------------------------------------
-   Virtual Root HUB
-   ------------------------------------------------------------------------------------ */
-/* destination of request */
-#define RH_INTERFACE               0x01
-#define RH_ENDPOINT                0x02
-#define RH_OTHER                   0x03
-
-#define RH_CLASS                   0x20
-#define RH_VENDOR                  0x40
-
-/* Requests: bRequest << 8 | bmRequestType */
-#define RH_GET_STATUS           0x0080
-#define RH_CLEAR_FEATURE        0x0100
-#define RH_SET_FEATURE          0x0300
-#define RH_SET_ADDRESS          0x0500
-#define RH_GET_DESCRIPTOR       0x0680
-#define RH_SET_DESCRIPTOR       0x0700
-#define RH_GET_CONFIGURATION    0x0880
-#define RH_SET_CONFIGURATION    0x0900
-#define RH_GET_STATE            0x0280
-#define RH_GET_INTERFACE        0x0A80
-#define RH_SET_INTERFACE        0x0B00
-#define RH_SYNC_FRAME           0x0C80
-/* Our Vendor Specific Request */
-#define RH_SET_EP               0x2000
-
-/* Hub port features */
-#define RH_PORT_CONNECTION         0x00
-#define RH_PORT_ENABLE             0x01
-#define RH_PORT_SUSPEND            0x02
-#define RH_PORT_OVER_CURRENT       0x03
-#define RH_PORT_RESET              0x04
-#define RH_PORT_POWER              0x08
-#define RH_PORT_LOW_SPEED          0x09
-#define RH_C_PORT_CONNECTION       0x10
-#define RH_C_PORT_ENABLE           0x11
-#define RH_C_PORT_SUSPEND          0x12
-#define RH_C_PORT_OVER_CURRENT     0x13
-#define RH_C_PORT_RESET            0x14
-
-/* Hub features */
-#define RH_C_HUB_LOCAL_POWER       0x00
-#define RH_C_HUB_OVER_CURRENT      0x01
-
-#define RH_DEVICE_REMOTE_WAKEUP    0x00
-#define RH_ENDPOINT_STALL          0x01
-
-/* Our Vendor Specific feature */
-#define RH_REMOVE_EP               0x00
-
-
-#define RH_ACK                     0x01
-#define RH_REQ_ERR                 -1
-#define RH_NACK                    0x00
-
-
-/* Transfer descriptor structure */
-typedef struct {
-	unsigned long link;     /* next td/qh (LE)*/
-	unsigned long status;   /* status of the td */
-	unsigned long info;     /* Max Lenght / Endpoint / device address and PID */
-	unsigned long buffer;   /* pointer to data buffer (LE) */
-	unsigned long dev_ptr;  /* pointer to the assigned device (BE) */
-	unsigned long res[3];   /* reserved (TDs must be 8Byte aligned) */
-} uhci_td_t, *puhci_td_t;
-
-/* Queue Header structure */
-typedef struct {
-	unsigned long head;       /* Next QH (LE)*/
-	unsigned long element;		/* Queue element pointer (LE) */
-	unsigned long res[5];     /* reserved */
-	unsigned long dev_ptr;    /* if 0 no tds have been assigned to this qh */
-} uhci_qh_t, *puhci_qh_t;
-
-struct virt_root_hub {
-	int devnum;		            /* Address of Root Hub endpoint */
-	int numports;             /* number of ports */
-	int c_p_r[8];             /* C_PORT_RESET */
-};
-
-
-#endif /* _USB_UHCI_H_ */
diff --git a/board/mpl/mip405/Kconfig b/board/mpl/mip405/Kconfig
deleted file mode 100644
index 48ba91a..0000000
--- a/board/mpl/mip405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MIP405
-
-config SYS_BOARD
-	default "mip405"
-
-config SYS_VENDOR
-	default "mpl"
-
-config SYS_CONFIG_NAME
-	default "MIP405"
-
-endif
diff --git a/board/mpl/mip405/MAINTAINERS b/board/mpl/mip405/MAINTAINERS
deleted file mode 100644
index b323e5a..0000000
--- a/board/mpl/mip405/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-MIP405 BOARD
-M:	Denis Peter <d.peter@mpl.ch>
-S:	Maintained
-F:	board/mpl/mip405/
-F:	include/configs/MIP405.h
-F:	configs/MIP405_defconfig
-F:	configs/MIP405T_defconfig
diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile
deleted file mode 100644
index 5bcf130..0000000
--- a/board/mpl/mip405/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= mip405.o cmd_mip405.o \
-		../common/pci.o \
-		../common/usb_uhci.o \
-		../common/common_util.o
-obj-y	+= init.o
diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c
deleted file mode 100644
index ca6f0af..0000000
--- a/board/mpl/mip405/cmd_mip405.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * hacked for MIP405
- */
-
-#include <common.h>
-#include <command.h>
-#include "mip405.h"
-#include "../common/common_util.h"
-
-
-extern void print_mip405_info(void);
-extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-
-/* ------------------------------------------------------------------------- */
-
-int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-
-	ulong led_on;
-
-	if (strcmp(argv[1], "info") == 0)
-	{
-		print_mip405_info();
-		return 0;
-	}
-	if (strcmp(argv[1], "led") == 0)
-	{
-		led_on = (ulong)simple_strtoul(argv[2], NULL, 10);
-		user_led0(led_on);
-		return 0;
-	}
-	return (do_mplcommon(cmdtp, flag, argc, argv));
-}
-U_BOOT_CMD(
-	mip405,	8,	1,	do_mip405,
-	"MIP405 specific Cmds",
-	"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
-	"mip405 flash mps - updates U-Boot with image from MPS\n"
-	"mip405 info      - displays board information\n"
-	"mip405 led <on>  - switches LED on (on=1) or off (on=0)"
-);
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S
deleted file mode 100644
index 2ea2e29..0000000
--- a/board/mpl/mip405/init.S
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
- */
-/*-----------------------------------------------------------------------------
- * Function:     ext_bus_cntlr_init
- * Description:  Initializes the External Bus Controller for the external
- *		peripherals. IMPORTANT: For pass1 this code must run from
- *		cache since you can not reliably change a peripheral banks
- *		timing register (pbxap) while running code from that bank.
- *		For ex., since we are running from ROM on bank 0, we can NOT
- *		execute the code that modifies bank 0 timings from ROM, so
- *		we run it from cache.
- *	Bank 0 - Flash or Multi Purpose Socket
- *	Bank 1 - Multi Purpose Socket or Flash (set in C-Code)
- *	Bank 2 - UART 1 (set in C-Code)
- *	Bank 3 - UART 2 (set in C-Code)
- *	Bank 4 - not used
- *	Bank 5 - not used
- *	Bank 6 - not used
- *	Bank 7 - PLD Register
- *-----------------------------------------------------------------------------*/
-
-#include <configs/MIP405.h>
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-#include "mip405.h"
-
-
-  .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
-  mflr   r4                      /* save link register */
-  mfdcr  r3,CPC0_PSR                /* get strapping reg */
-  andi.  r0, r3, PSR_ROM_LOC     /* mask out irrelevant bits */
-  bnelr                          /* jump back if PCI boot */
-
-  bl      ..getAddr
-..getAddr:
-  mflr    r3                      /* get address of ..getAddr */
-  mtlr    r4                      /* restore link register */
-  addi    r4,0,14                 /* set ctr to 14; used to prefetch */
-  mtctr   r4                      /* 14 cache lines to fit this function */
-				   /* in cache (gives us 8x14=112 instrctns) */
-..ebcloop:
-  icbt    r0,r3                   /* prefetch cache line for addr in r3 */
-  addi    r3,r3,32								/* move to next cache line */
-  bdnz    ..ebcloop               /* continue for 14 cache lines */
-
-   /*-------------------------------------------------------------------
-    * Delay to ensure all accesses to ROM are complete before changing
-    * bank 0 timings.
-    *------------------------------------------------------------------- */
-	addis	r3,0,0x0
-  ori     r3,r3,0xA000
-  mtctr   r3
-..spinlp:
-  bdnz    ..spinlp                /* spin loop */
-
-	/*-----------------------------------------------------------------------
-	 * decide boot up mode
-	 *----------------------------------------------------------------------- */
-	addi		r4,0,PB0CR
-	mtdcr		EBC0_CFGADDR,r4
-	mfdcr		r4,EBC0_CFGDATA
-
-	andi.		r0, r4, 0x2000			/* mask out irrelevant bits */
-	beq		0f				/* jump if 8 bit bus width */
-
-	/* setup 16 bit things
-   *-----------------------------------------------------------------------
-   * Memory Bank 0 (16 Bit Flash) initialization
-   *---------------------------------------------------------------------- */
-
-	addi    r4,0,PB1AP
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,(FLASH_AP_B)@h
-	ori     r4,r4,(FLASH_AP_B)@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	addi    r4,0,PB0CR
-	mtdcr   EBC0_CFGADDR,r4
-	/* BS=0x010(4MB),BU=0x3(R/W), */
-	addis   r4,0,(FLASH_CR_B)@h
-	ori     r4,r4,(FLASH_CR_B)@l
-	mtdcr   EBC0_CFGDATA,r4
-	b				1f
-
-0:
-
-	/* 8Bit boot mode: */
-	/*-----------------------------------------------------------------------
-	* Memory Bank 0 Multi Purpose Socket initialization
-	*----------------------------------------------------------------------- */
-	/* 0x7F8FFE80 slowest boot */
-	addi    r4,0,PB1AP
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,(MPS_AP_B)@h
-	ori     r4,r4,(MPS_AP_B)@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	addi    r4,0,PB0CR
-	mtdcr   EBC0_CFGADDR,r4
-	/* BS=0x010(4MB),BU=0x3(R/W), */
-	addis   r4,0,(MPS_CR_B)@h
-	ori     r4,r4,(MPS_CR_B)@l
-
-	mtdcr   EBC0_CFGDATA,r4
-
-
-1:
-  /*-----------------------------------------------------------------------
-   * Memory Bank 2-3-4-5-6 (not used) initialization
-   *-----------------------------------------------------------------------*/
-  addi    r4,0,PB1CR
-  mtdcr   EBC0_CFGADDR,r4
-  addis   r4,0,0x0000
-  ori     r4,r4,0x0000
-  mtdcr   EBC0_CFGDATA,r4
-
-  addi    r4,0,PB2CR
-  mtdcr   EBC0_CFGADDR,r4
-  addis   r4,0,0x0000
-  ori     r4,r4,0x0000
-  mtdcr   EBC0_CFGDATA,r4
-
-  addi    r4,0,PB3CR
-  mtdcr   EBC0_CFGADDR,r4
-  addis   r4,0,0x0000
-  ori     r4,r4,0x0000
-  mtdcr   EBC0_CFGDATA,r4
-
-  addi    r4,0,PB4CR
-  mtdcr   EBC0_CFGADDR,r4
-  addis   r4,0,0x0000
-  ori     r4,r4,0x0000
-  mtdcr   EBC0_CFGDATA,r4
-
-  addi    r4,0,PB5CR
-  mtdcr   EBC0_CFGADDR,r4
-  addis   r4,0,0x0000
-  ori     r4,r4,0x0000
-  mtdcr   EBC0_CFGDATA,r4
-
-  addi    r4,0,PB6CR
-  mtdcr   EBC0_CFGADDR,r4
-  addis   r4,0,0x0000
-  ori     r4,r4,0x0000
-  mtdcr   EBC0_CFGDATA,r4
-
-  addi    r4,0,PB7CR
-  mtdcr   EBC0_CFGADDR,r4
-  addis   r4,0,0x0000
-  ori     r4,r4,0x0000
-  mtdcr   EBC0_CFGDATA,r4
-  nop				/* pass2 DCR errata #8 */
-  blr
-
-#if defined(CONFIG_BOOT_PCI)
-    .section .bootpg,"ax"
-    .globl _start_pci
-/*******************************************
- */
-
-_start_pci:
-  /* first handle errata #68 / PCI_18 */
-  iccci   r0, r0          /* invalidate I-cache */
-  lis     r31, 0
-  mticcr  r31             /* ICCR = 0 (all uncachable) */
-  isync
-
-  mfccr0  r28             /* set CCR0[24] = 1 */
-  ori     r28, r28, 0x0080
-  mtccr0  r28
-
-  /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
-  lis     r28, 0xEF40
-  addi    r28, r28, 0x0004
-  stw     r31, 0x0C(r28)  /* clear PMM0PCIHA */
-  lis     r29, 0xFFF8     /* open 512 kByte */
-  addi    r29, r29, 0x0001/* and enable this region */
-  stwbrx  r29, r0, r28    /* write PMM0MA */
-
-  lis     r28, 0xEEC0     /* address of PCIC0_CFGADDR */
-  addi    r29, r28, 4     /* add 4 to r29 -> PCIC0_CFGDATA */
-
-  lis     r31, 0x8000     /* set en bit bus 0 */
-  ori     r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
-  stwbrx  r31, r0, r28    /* write it */
-
-  lwbrx   r31, r0, r29    /* load XBCS register */
-  oris    r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
-  stwbrx  r31, r0, r29    /* write back XBCS register */
-
-  nop
-  nop
-  b	_start		/* normal start */
-#endif
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
deleted file mode 100644
index 4a0d696..0000000
--- a/board/mpl/mip405/mip405.c
+++ /dev/null
@@ -1,803 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * TODO: clean-up
- */
-
-/*
- * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
- *
- * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
- * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
- * parameters from the datasheet are:
- * Tclk = 7.5ns (CL = 2)
- * Trp = 15ns
- * Trc = 60ns
- * Trcd = 15ns
- * Trfc = 66ns
- *
- * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
- * period is 10ns and the parameters needed for the Timing Register are:
- * CASL = CL = 2 clock cycles
- * PTA = Trp = 15ns / 10ns = 2 clock cycles
- * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
- * LDF = 2 clock cycles (but can be extended to meet board-level timing)
- * RFTA = Trfc = 66ns / 10ns= 7 clock cycles
- * RCD = Trcd = 15ns / 10ns= 2 clock cycles
- *
- * The actual bit settings in the register would be:
- *
- * CASL = 0b01
- * PTA = 0b01
- * CTP = 0b10
- * LDF = 0b01
- * RFTA = 0b011
- * RCD = 0b01
- *
- * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
- * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
- * defined as Trc rather than Trfc.
- * When using DIMM modules, most but not all of the required timing parameters can be read
- * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
- * are not available from the EEPROM
- */
-
-#include <common.h>
-#include "mip405.h"
-#include <asm/processor.h>
-#include <asm/ppc4xx.h>
-#include <asm/ppc4xx-i2c.h>
-#include <miiphy.h>
-#include "../common/common_util.h"
-#include <stdio_dev.h>
-#include <i2c.h>
-#include <rtc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#undef SDRAM_DEBUG
-#define ENABLE_ECC /* for ecc boards */
-
-/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
-#ifndef __ldiv_t_defined
-typedef struct {
-	long int quot;		/* Quotient	*/
-	long int rem;		/* Remainder	*/
-} ldiv_t;
-extern ldiv_t ldiv (long int __numer, long int __denom);
-# define __ldiv_t_defined	1
-#endif
-
-
-#define PLD_PART_REG		PER_PLD_ADDR + 0
-#define PLD_VERS_REG		PER_PLD_ADDR + 1
-#define PLD_BOARD_CFG_REG	PER_PLD_ADDR + 2
-#define PLD_IRQ_REG		PER_PLD_ADDR + 3
-#define PLD_COM_MODE_REG	PER_PLD_ADDR + 4
-#define PLD_EXT_CONF_REG	PER_PLD_ADDR + 5
-
-#define MEGA_BYTE (1024*1024)
-
-typedef struct {
-	unsigned char boardtype; /* Board revision and Population Options */
-	unsigned char cal;		/* cas Latency (will be programmend as cal-1) */
-	unsigned char trp;		/* datain27 in clocks */
-	unsigned char trcd;		/* datain29 in clocks */
-	unsigned char tras;		/* datain30 in clocks */
-	unsigned char tctp;		/* tras - trcd in clocks */
-	unsigned char am;		/* Address Mod (will be programmed as am-1) */
-	unsigned char sz;		/* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
-	unsigned char ecc;		/* if true, ecc is enabled */
-} sdram_t;
-#if defined(CONFIG_MIP405T)
-const sdram_t sdram_table[] = {
-	{ 0x0F,	/* MIP405T Rev A, 64MByte -1 Board */
-		3,	/* Case Latenty = 3 */
-		3,	/* trp 20ns / 7.5 ns datain[27] */
-		3,	/* trcd 20ns /7.5 ns (datain[29]) */
-		6,	/* tras 44ns /7.5 ns  (datain[30]) */
-		4,	/* tcpt 44 - 20ns = 24ns */
-		2,	/* Address Mode = 2 (12x9x4) */
-		3,	/* size value (32MByte) */
-		0},	/* ECC disabled */
-	{ 0xff, /* terminator */
-	  0xff,
-	  0xff,
-	  0xff,
-	  0xff,
-	  0xff,
-	  0xff,
-	  0xff }
-};
-#else
-const sdram_t sdram_table[] = {
-	{ 0x0f,	/* Rev A, 128MByte -1 Board */
-		3,	/* Case Latenty = 3 */
-		3,	/* trp 20ns / 7.5 ns datain[27] */
-		3,	/* trcd 20ns /7.5 ns (datain[29]) */
-		6,	/* tras 44ns /7.5 ns  (datain[30]) */
-		4,	/* tcpt 44 - 20ns = 24ns */
-		3,	/* Address Mode = 3 */
-		5,	/* size value */
-		1},	/* ECC enabled */
-	{ 0x07,	/* Rev A, 64MByte -2 Board */
-		3,	/* Case Latenty = 3 */
-		3,	/* trp 20ns / 7.5 ns datain[27] */
-		3,	/* trcd 20ns /7.5 ns (datain[29]) */
-		6,	/* tras 44ns /7.5 ns  (datain[30]) */
-		4,	/* tcpt 44 - 20ns = 24ns */
-		2,	/* Address Mode = 2 */
-		4,	/* size value */
-		1},	/* ECC enabled */
-	{ 0x03,	/* Rev A, 128MByte -4 Board */
-		3,	/* Case Latenty = 3 */
-		3,	/* trp 20ns / 7.5 ns datain[27] */
-		3,	/* trcd 20ns /7.5 ns (datain[29]) */
-		6,	/* tras 44ns /7.5 ns  (datain[30]) */
-		4,	/* tcpt 44 - 20ns = 24ns */
-		3,	/* Address Mode = 3 */
-		5,	/* size value */
-		1},	/* ECC enabled */
-	{ 0x1f,	/* Rev B, 128MByte -3 Board */
-		3,	/* Case Latenty = 3 */
-		3,	/* trp 20ns / 7.5 ns datain[27] */
-		3,	/* trcd 20ns /7.5 ns (datain[29]) */
-		6,	/* tras 44ns /7.5 ns  (datain[30]) */
-		4,	/* tcpt 44 - 20ns = 24ns */
-		3,	/* Address Mode = 3 */
-		5,	/* size value */
-		1},	/* ECC enabled */
-	{ 0x2f,	/* Rev C, 128MByte -3 Board */
-		3,	/* Case Latenty = 3 */
-		3,	/* trp 20ns / 7.5 ns datain[27] */
-		3,	/* trcd 20ns /7.5 ns (datain[29]) */
-		6,	/* tras 44ns /7.5 ns  (datain[30]) */
-		4,	/* tcpt 44 - 20ns = 24ns */
-		3,	/* Address Mode = 3 */
-		5,	/* size value */
-		1},	/* ECC enabled */
-	{ 0xff, /* terminator */
-	  0xff,
-	  0xff,
-	  0xff,
-	  0xff,
-	  0xff,
-	  0xff,
-	  0xff }
-};
-#endif /*CONFIG_MIP405T */
-void SDRAM_err (const char *s)
-{
-#ifndef SDRAM_DEBUG
-	(void) get_clocks ();
-	gd->baudrate = 9600;
-	serial_init ();
-#endif
-	serial_puts ("\n");
-	serial_puts (s);
-	serial_puts ("\n enable SDRAM_DEBUG for more info\n");
-	for (;;);
-}
-
-
-unsigned char get_board_revcfg (void)
-{
-	out8 (PER_BOARD_ADDR, 0);
-	return (in8 (PER_BOARD_ADDR));
-}
-
-
-#ifdef SDRAM_DEBUG
-
-void write_hex (unsigned char i)
-{
-	char cc;
-
-	cc = i >> 4;
-	cc &= 0xf;
-	if (cc > 9)
-		serial_putc (cc + 55);
-	else
-		serial_putc (cc + 48);
-	cc = i & 0xf;
-	if (cc > 9)
-		serial_putc (cc + 55);
-	else
-		serial_putc (cc + 48);
-}
-
-void write_4hex (unsigned long val)
-{
-	write_hex ((unsigned char) (val >> 24));
-	write_hex ((unsigned char) (val >> 16));
-	write_hex ((unsigned char) (val >> 8));
-	write_hex ((unsigned char) val);
-}
-
-#endif
-
-
-int init_sdram (void)
-{
-	unsigned long	tmp, baseaddr;
-	unsigned short	i;
-	unsigned char	trp_clocks,
-			trcd_clocks,
-			tras_clocks,
-			trc_clocks;
-	unsigned char	cal_val;
-	unsigned char	bc;
-	unsigned long	sdram_tim, sdram_bank;
-
-	/*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/
-	(void) get_clocks ();
-	gd->baudrate = 9600;
-	serial_init ();
-	/* set up the pld */
-	mtdcr (EBC0_CFGADDR, PB7AP);
-	mtdcr (EBC0_CFGDATA, PLD_AP);
-	mtdcr (EBC0_CFGADDR, PB7CR);
-	mtdcr (EBC0_CFGDATA, PLD_CR);
-	/* THIS IS OBSOLETE */
-	/* set up the board rev reg*/
-	mtdcr (EBC0_CFGADDR, PB5AP);
-	mtdcr (EBC0_CFGDATA, BOARD_AP);
-	mtdcr (EBC0_CFGADDR, PB5CR);
-	mtdcr (EBC0_CFGDATA, BOARD_CR);
-#ifdef SDRAM_DEBUG
-	/* get all informations from PLD */
-	serial_puts ("\nPLD Part  0x");
-	bc = in8 (PLD_PART_REG);
-	write_hex (bc);
-	serial_puts ("\nPLD Vers  0x");
-	bc = in8 (PLD_VERS_REG);
-	write_hex (bc);
-	serial_puts ("\nBoard Rev 0x");
-	bc = in8 (PLD_BOARD_CFG_REG);
-	write_hex (bc);
-	serial_puts ("\n");
-#endif
-	/* check board */
-	bc = in8 (PLD_PART_REG);
-#if defined(CONFIG_MIP405T)
-	if((bc & 0x80)==0)
-		SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
-#else
-	if((bc & 0x80)==0x80)
-		SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
-#endif
-	/* set-up the chipselect machine */
-	mtdcr (EBC0_CFGADDR, PB0CR);		/* get cs0 config reg */
-	tmp = mfdcr (EBC0_CFGDATA);
-	if ((tmp & 0x00002000) == 0) {
-		/* MPS Boot, set up the flash */
-		mtdcr (EBC0_CFGADDR, PB1AP);
-		mtdcr (EBC0_CFGDATA, FLASH_AP);
-		mtdcr (EBC0_CFGADDR, PB1CR);
-		mtdcr (EBC0_CFGDATA, FLASH_CR);
-	} else {
-		/* Flash boot, set up the MPS */
-		mtdcr (EBC0_CFGADDR, PB1AP);
-		mtdcr (EBC0_CFGDATA, MPS_AP);
-		mtdcr (EBC0_CFGADDR, PB1CR);
-		mtdcr (EBC0_CFGDATA, MPS_CR);
-	}
-	/* set up UART0 (CS2) and UART1 (CS3) */
-	mtdcr (EBC0_CFGADDR, PB2AP);
-	mtdcr (EBC0_CFGDATA, UART0_AP);
-	mtdcr (EBC0_CFGADDR, PB2CR);
-	mtdcr (EBC0_CFGDATA, UART0_CR);
-	mtdcr (EBC0_CFGADDR, PB3AP);
-	mtdcr (EBC0_CFGDATA, UART1_AP);
-	mtdcr (EBC0_CFGADDR, PB3CR);
-	mtdcr (EBC0_CFGDATA, UART1_CR);
-	bc = in8 (PLD_BOARD_CFG_REG);
-#ifdef SDRAM_DEBUG
-	serial_puts ("\nstart SDRAM Setup\n");
-	serial_puts ("\nBoard Rev: ");
-	write_hex (bc);
-	serial_puts ("\n");
-#endif
-	i = 0;
-	baseaddr = CONFIG_SYS_SDRAM_BASE;
-	while (sdram_table[i].sz != 0xff) {
-		if (sdram_table[i].boardtype == bc)
-			break;
-		i++;
-	}
-	if (sdram_table[i].boardtype != bc)
-		SDRAM_err ("No SDRAM table found for this board!!!\n");
-#ifdef SDRAM_DEBUG
-	serial_puts (" found table ");
-	write_hex (i);
-	serial_puts (" \n");
-#endif
-	/* since the ECC initialisation needs some time,
-	 * we show that we're alive
-	 */
-	if (sdram_table[i].ecc)
-		serial_puts ("\nInitializing SDRAM, Please stand by");
-	cal_val = sdram_table[i].cal - 1;	/* Cas Latency */
-	trp_clocks = sdram_table[i].trp;	/* 20ns / 7.5 ns datain[27] */
-	trcd_clocks = sdram_table[i].trcd;	/* 20ns /7.5 ns (datain[29]) */
-	tras_clocks = sdram_table[i].tras;	/* 44ns /7.5 ns  (datain[30]) */
-	/* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
-	/* trc_clocks is sum of trp_clocks + tras_clocks */
-	trc_clocks = trp_clocks + tras_clocks;
-	/* get SDRAM timing register */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
-	sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
-	/* insert CASL value */
-	sdram_tim |= ((unsigned long) (cal_val)) << 23;
-	/* insert PTA value */
-	sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
-	/* insert CTP value */
-	sdram_tim |=
-			((unsigned long) (trc_clocks - trp_clocks -
-							  trcd_clocks)) << 16;
-	/* insert LDF (always 01) */
-	sdram_tim |= ((unsigned long) 0x01) << 14;
-	/* insert RFTA value */
-	sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
-	/* insert RCD value */
-	sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
-
-	tmp = ((unsigned long) (sdram_table[i].am - 1) << 13);	/* AM = 3 */
-	/* insert SZ value; */
-	tmp |= ((unsigned long) sdram_table[i].sz << 17);
-	/* get SDRAM bank 0 register */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
-	sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
-	sdram_bank |= (baseaddr | tmp | 0x01);
-
-#ifdef SDRAM_DEBUG
-	serial_puts ("sdtr: ");
-	write_4hex (sdram_tim);
-	serial_puts ("\n");
-#endif
-
-	/* write SDRAM timing register */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
-	mtdcr (SDRAM0_CFGDATA, sdram_tim);
-
-#ifdef SDRAM_DEBUG
-	serial_puts ("mb0cf: ");
-	write_4hex (sdram_bank);
-	serial_puts ("\n");
-#endif
-
-	/* write SDRAM bank 0 register */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
-	mtdcr (SDRAM0_CFGDATA, sdram_bank);
-
-	if (get_bus_freq (tmp) > 110000000) {	/* > 110MHz */
-		/* get SDRAM refresh interval register */
-		mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
-		tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
-		tmp |= 0x07F00000;
-	} else {
-		/* get SDRAM refresh interval register */
-		mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
-		tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
-		tmp |= 0x05F00000;
-	}
-	/* write SDRAM refresh interval register */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
-	mtdcr (SDRAM0_CFGDATA, tmp);
-	/* enable ECC if used */
-#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
-	if (sdram_table[i].ecc) {
-		/* disable checking for all banks */
-		unsigned long	*p;
-#ifdef SDRAM_DEBUG
-		serial_puts ("disable ECC.. ");
-#endif
-		mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
-		tmp = mfdcr (SDRAM0_CFGDATA);
-		tmp &= 0xff0fffff;		/* disable all banks */
-		mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
-		/* set up SDRAM Controller with ECC enabled */
-#ifdef SDRAM_DEBUG
-		serial_puts ("setup SDRAM Controller.. ");
-#endif
-		mtdcr (SDRAM0_CFGDATA, tmp);
-		mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
-		tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
-		mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
-		mtdcr (SDRAM0_CFGDATA, tmp);
-		udelay (600);
-#ifdef SDRAM_DEBUG
-		serial_puts ("fill the memory..\n");
-#endif
-		serial_puts (".");
-		/* now, fill all the memory */
-		tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
-		p = (unsigned long) 0;
-		while ((unsigned long) p < tmp) {
-			*p++ = 0L;
-			if (!((unsigned long) p % 0x00800000))	/* every 8MByte */
-				serial_puts (".");
-		}
-		/* enable bank 0 */
-		serial_puts (".");
-#ifdef SDRAM_DEBUG
-		serial_puts ("enable ECC\n");
-#endif
-		udelay (400);
-		mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
-		tmp = mfdcr (SDRAM0_CFGDATA);
-		tmp |= 0x00800000;		/* enable bank 0 */
-		mtdcr (SDRAM0_CFGDATA, tmp);
-		udelay (400);
-	} else
-#endif
-	{
-		/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
-		mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
-		tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000;
-		mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
-		mtdcr (SDRAM0_CFGDATA, tmp);
-		udelay (400);
-	}
-	serial_puts ("\n");
-	return (0);
-}
-
-int board_early_init_f (void)
-{
-	init_sdram ();
-
-   /*-------------------------------------------------------------------------+
-   | Interrupt controller setup for the PIP405 board.
-   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
-   |       IRQ 16    405GP internally generated; active low; level sensitive
-   |       IRQ 17-24 RESERVED
-   |       IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
-   |       IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
-   |       IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
-   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
-   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
-   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
-   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
-   | Note for MIP405 board:
-   |       An interrupt taken for the SouthBridge (IRQ 25) indicates that
-   |       the Interrupt Controller in the South Bridge has caused the
-   |       interrupt. The IC must be read to determine which device
-   |       caused the interrupt.
-   |
-   +-------------------------------------------------------------------------*/
-	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
-	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical (for now) */
-	mtdcr (UIC0PR, 0xFFFFFF80);	/* set int polarities */
-	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
-	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	int mode;
-
-	/*
-	 * since we are relocated, we can finally enable i-cache
-	 * and set up the flash CS correctly
-	 */
-	icache_enable();
-	setup_cs_reloc();
-	/* get and display boot mode */
-	mode = get_boot_mode();
-	if (mode & BOOT_PCI)
-		printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ?
-			"MPS" : "Flash");
-	else
-		printf("%s Boot\n", (mode & BOOT_MPS) ?
-			"MPS" : "Flash");
-
-	return 0;
-}
-
-/*
- * Get some PLD Registers
- */
-
-unsigned short get_pld_parvers (void)
-{
-	unsigned short result;
-	unsigned char rc;
-
-	rc = in8 (PLD_PART_REG);
-	result = (unsigned short) rc << 8;
-	rc = in8 (PLD_VERS_REG);
-	result |= rc;
-	return result;
-}
-
-
-void user_led0 (unsigned char on)
-{
-	if (on)
-		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
-	else
-		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
-}
-
-
-void ide_set_reset (int idereset)
-{
-	/* if reset = 1 IDE reset will be asserted */
-	if (idereset)
-		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
-	else {
-		udelay (10000);
-		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
-	}
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
-{
-#if !defined(CONFIG_MIP405T)
-	unsigned char bc,rc,tmp;
-	int i;
-
-	bc = in8 (PLD_BOARD_CFG_REG);
-	tmp = ~bc;
-	tmp &= 0xf;
-	rc = 0;
-	for (i = 0; i < 4; i++) {
-		rc <<= 1;
-		rc += (tmp & 0x1);
-		tmp >>= 1;
-	}
-	rc++;
-	if((  (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */
-	   || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */
-		&& (rc==0x1))     /* Population Option 1 is a -3 */
-		rc=3;
-	*pcbrev=(bc >> 4) & 0xf;
-	*var=rc;
-#else
-	unsigned char bc;
-	bc = in8 (PLD_BOARD_CFG_REG);
-	*pcbrev=(bc >> 4) & 0xf;
-	*var=16-(bc & 0xf);
-#endif
-}
-
-/*
- * Check Board Identity:
- */
-/* serial String: "MIP405_1000" OR "MIP405T_1000" */
-#if !defined(CONFIG_MIP405T)
-#define BOARD_NAME	"MIP405"
-#else
-#define BOARD_NAME	"MIP405T"
-#endif
-
-int checkboard (void)
-{
-	char s[50];
-	unsigned char bc, var;
-	int i;
-	backup_t *b = (backup_t *) s;
-
-	puts ("Board: ");
-	get_pcbrev_var(&bc,&var);
-	i = getenv_f("serial#", (char *)s, 32);
-	if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) {
-		get_backup_values (b);
-		if (strncmp (b->signature, "MPL\0", 4) != 0) {
-			puts ("### No HW ID - assuming " BOARD_NAME);
-			printf ("-%d Rev %c", var, 'A' + bc);
-		} else {
-			b->serial_name[sizeof(BOARD_NAME)-1] = 0;
-			printf ("%s-%d Rev %c SN: %s", b->serial_name, var,
-					'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]);
-		}
-	} else {
-		s[sizeof(BOARD_NAME)-1] = 0;
-		printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc,
-				&s[sizeof(BOARD_NAME)]);
-	}
-	bc = in8 (PLD_EXT_CONF_REG);
-	printf (" Boot Config: 0x%x\n", bc);
-	return (0);
-}
-
-
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-/*
-  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
-  the necessary info for SDRAM controller configuration
-*/
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-static int test_dram (unsigned long ramsize);
-
-phys_size_t initdram (int board_type)
-{
-
-	unsigned long bank_reg[4], tmp, bank_size;
-	int i;
-	unsigned long TotalSize;
-
-	/* since the DRAM controller is allready set up, calculate the size with the
-	   bank registers    */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
-	bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
-	bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
-	bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
-	bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
-	TotalSize = 0;
-	for (i = 0; i < 4; i++) {
-		if ((bank_reg[i] & 0x1) == 0x1) {
-			tmp = (bank_reg[i] >> 17) & 0x7;
-			bank_size = 4 << tmp;
-			TotalSize += bank_size;
-		}
-	}
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
-	tmp = mfdcr (SDRAM0_CFGDATA);
-
-	if (!tmp)
-		printf ("No ");
-	printf ("ECC ");
-
-	test_dram (TotalSize * MEGA_BYTE);
-	return (TotalSize * MEGA_BYTE);
-}
-
-/* ------------------------------------------------------------------------- */
-
-
-static int test_dram (unsigned long ramsize)
-{
-#ifdef SDRAM_DEBUG
-	mem_test (0L, ramsize, 1);
-#endif
-	/* not yet implemented */
-	return (1);
-}
-
-/* used to check if the time in RTC is valid */
-static unsigned long start;
-static struct rtc_time tm;
-
-int misc_init_r (void)
-{
-	/* adjust flash start and size as well as the offset */
-	gd->bd->bi_flashstart=0-flash_info[0].size;
-	gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
-	gd->bd->bi_flashoffset=0;
-
-	/* check, if RTC is running */
-	rtc_get (&tm);
-	start=get_timer(0);
-	/* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
-	if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
-	       mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
-
-	return (0);
-}
-
-
-void print_mip405_rev (void)
-{
-	unsigned char part, vers, pcbrev, var;
-
-	get_pcbrev_var(&pcbrev,&var);
-	part = in8 (PLD_PART_REG);
-	vers = in8 (PLD_VERS_REG);
-	printf ("Rev:   " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n",
-			var, pcbrev + 'A', part & 0x7F, vers);
-}
-
-
-extern int mk_date (char *, struct rtc_time *);
-
-int last_stage_init (void)
-{
-	unsigned long stop;
-	struct rtc_time newtm;
-	char *s;
-
-	/* write correct LED configuration */
-	if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
-		printf ("Error writing to the PHY\n");
-	}
-	/* since LED/CFG2 is not connected on the -2,
-	 * write to correct capability information */
-	if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
-		printf ("Error writing to the PHY\n");
-	}
-	print_mip405_rev ();
-	stdio_print_current_devices ();
-	check_env ();
-	/* check if RTC time is valid */
-	stop=get_timer(start);
-	while(stop<1200) {   /* we wait 1.2 sec to check if the RTC is running */
-		udelay(1000);
-		stop=get_timer(start);
-	}
-	rtc_get (&newtm);
-	if(tm.tm_sec==newtm.tm_sec) {
-		s=getenv("defaultdate");
-		if(!s)
-			mk_date ("010112001970", &newtm);
-		else
-			if(mk_date (s, &newtm)!=0) {
-				printf("RTC: Bad date format in defaultdate\n");
-				return 0;
-			}
-		rtc_reset ();
-		rtc_set(&newtm);
-	}
-	return 0;
-}
-
-/***************************************************************************
- * some helping routines
- */
-
-int overwrite_console (void)
-{
-	/* return true if console should be overwritten */
-	return ((in8(PLD_EXT_CONF_REG) & 0x1) == 0);
-}
-
-
-/************************************************************************
-* Print MIP405 Info
-************************************************************************/
-void print_mip405_info (void)
-{
-	unsigned char part, vers, cfg, irq_reg, com_mode, ext;
-
-	part = in8 (PLD_PART_REG);
-	vers = in8 (PLD_VERS_REG);
-	cfg = in8 (PLD_BOARD_CFG_REG);
-	irq_reg = in8 (PLD_IRQ_REG);
-	com_mode = in8 (PLD_COM_MODE_REG);
-	ext = in8 (PLD_EXT_CONF_REG);
-
-	printf ("PLD Part %d version %d\n", part & 0x7F, vers);
-	printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
-	printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
-			(cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
-	printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
-	printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
-#if !defined(CONFIG_MIP405T)
-	printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
-			(ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
-			(ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
-			(ext >> 6) & 0x1, (ext >> 7) & 0x1);
-	printf ("SER1 uses handshakes %s\n",
-			(ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
-#else
-	printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
-			(ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
-			(ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
-			(ext >> 6) & 0x1,(ext >> 7) & 0x1);
-#endif
-	printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
-	printf ("IRQs:\n");
-	printf ("  PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
-#if !defined(CONFIG_MIP405T)
-	printf ("  UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
-	printf ("  UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
-#endif
-	printf ("  PIIX SMI:  %s\n", (irq_reg & 0x10) ? "inactive" : "active");
-	printf ("  PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
-	printf ("  PIIX NMI:  %s\n", (irq_reg & 0x4) ? "inactive" : "active");
-}
diff --git a/board/mpl/mip405/mip405.h b/board/mpl/mip405/mip405.h
deleted file mode 100644
index b1f69aa..0000000
--- a/board/mpl/mip405/mip405.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
- /****************************************************************************
- * Global routines used for MIP405
- *****************************************************************************/
-#ifndef __ASSEMBLY__
-/*int switch_cs(unsigned char boot);*/
-
-extern int  mem_test(unsigned long start, unsigned long ramsize,int mode);
-
-void user_led0(unsigned char on);
-
-
-#endif
-/* timings */
-/* PLD (CS7) */
-#define PLD_BME	0	/* Burst disable */
-#define PLD_TWE	5	/* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */
-#define PLD_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define PLD_OEN	1	/* Cycles from CS low to OE low   */
-#define PLD_WBN	1	/* Cycles from CS low to WE low   */
-#define PLD_WBF	1	/* Cycles from WE high to CS high */
-#define PLD_TH	2	/* Number of hold cycles after transfer */
-#define PLD_RE	0	/* Ready disabled */
-#define PLD_SOR	1	/* Sample on Ready disabled */
-#define PLD_BEM	0	/* Byte Write only active on Write cycles */
-#define PLD_PEN	0	/* Parity disable */
-#define PLD_AP	((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
-					(PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define PLD_BS	0	/* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define PLD_BU	3	/* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define PLD_BW	0	/* 16Bit */
-#define PLD_CR	((PER_PLD_ADDR & 0xfff00000) + (PLD_BS << 17) + (PLD_BU << 15) + (PLD_BW << 13))
-
-
-/* timings */
-
-#define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024))
-/* Dummy CS to get the board revision */
-#define BOARD_BME	0	/* Burst disable */
-#define BOARD_TWE	255	/* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
-#define BOARD_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define BOARD_OEN	1	/* Cycles from CS low to OE low   */
-#define BOARD_WBN	1	/* Cycles from CS low to WE low   */
-#define BOARD_WBF	1	/* Cycles from WE high to CS high */
-#define BOARD_TH	2	/* Number of hold cycles after transfer */
-#define BOARD_RE	0	/* Ready disabled */
-#define BOARD_SOR	1	/* Sample on Ready disabled */
-#define BOARD_BEM	0	/* Byte Write only active on Write cycles */
-#define BOARD_PEN	0	/* Parity disable */
-#define BOARD_AP	((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
-					(BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define BOARD_BS	0	/* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define BOARD_BU	3	/* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define BOARD_BW	0	/* 16Bit */
-#define BOARD_CR	((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13))
-
-
-/* UART0 CS2 */
-#define UART0_BME	0	/* Burst disable */
-#define UART0_TWE	7	/* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */
-#define UART0_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define UART0_OEN	1	/* Cycles from CS low to OE low   */
-#define UART0_WBN	1	/* Cycles from CS low to WE low   */
-#define UART0_WBF	1	/* Cycles from WE high to CS high */
-#define UART0_TH	2	/* Number of hold cycles after transfer */
-#define UART0_RE	0	/* Ready disabled */
-#define UART0_SOR	1	/* Sample on Ready disabled */
-#define UART0_BEM	0	/* Byte Write only active on Write cycles */
-#define UART0_PEN	0	/* Parity disable */
-#define UART0_AP	((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
-					(UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define UART0_BS	0	/* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define UART0_BU	3	/* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define UART0_BW	0	/* 8Bit */
-#define UART0_CR	((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
-
-/* UART1 CS3 */
-#define UART1_AP UART0_AP /* same timing as UART0 */
-#define UART1_CR	((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
-
-
-/* Flash CS0 or CS 1 */
-/* 0x7F8FFE80 slowest timing at all... */
-#define FLASH_BME_B	1	/* Burst enable */
-#define FLASH_FWT_B	0x6	/* 6 * 30ns 210ns First Wait Access */
-#define FLASH_BWT_B	0x6	/* 6 * 30ns 210ns Burst Wait Access */
-#define FLASH_BME	0	/* Burst disable */
-#define FLASH_TWE	0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
-#define FLASH_CSN	0	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define FLASH_OEN	1	/* Cycles from CS low to OE low   */
-#define FLASH_WBN	1	/* Cycles from CS low to WE low   */
-#define FLASH_WBF	1	/* Cycles from WE high to CS high */
-#define FLASH_TH	2	/* Number of hold cycles after transfer */
-#define FLASH_RE	0	/* Ready disabled */
-#define FLASH_SOR	1	/* Sample on Ready disabled */
-#define FLASH_BEM	0	/* Byte Write only active on Write cycles */
-#define FLASH_PEN	0	/* Parity disable */
-/* Access Parameter Register for non Boot */
-#define FLASH_AP	((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
-					(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
-/* Access Parameter Register for Boot */
-#define FLASH_AP_B	((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
-					(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define FLASH_BS	FLASH_SIZE_PRELIM	/* 4 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define FLASH_BU	3	/* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define FLASH_BW	1	/* 16Bit */
-/* CR register for Boot */
-#define FLASH_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
-/* CR register for non Boot */
-#define FLASH_CR	((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
-
-/* MPS CS1 or CS0 */
-/* Boot CS: */
-#define MPS_BME_B	1	/* Burst enable */
-#define MPS_FWT_B	0x6/* 6 * 30ns 210ns First Wait Access */
-#define MPS_BWT_B	0x6	/* 6 * 30ns 210ns Burst Wait Access */
-#define MPS_BME		0	/* Burst disable */
-#define MPS_TWE		0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
-#define MPS_CSN		0	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define MPS_OEN		1	/* Cycles from CS low to OE low   */
-#define MPS_WBN		1	/* Cycles from CS low to WE low   */
-#define MPS_WBF		1	/* Cycles from WE high to CS high */
-#define MPS_TH		2	/* Number of hold cycles after transfer */
-#define MPS_RE		0	/* Ready disabled */
-#define MPS_SOR		1	/* Sample on Ready disabled */
-#define MPS_BEM		0	/* Byte Write only active on Write cycles */
-#define MPS_PEN		0	/* Parity disable */
-/* Access Parameter Register for non Boot */
-#define MPS_AP		((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
-					(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
-/* Access Parameter Register for Boot */
-#define MPS_AP_B		((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
-					(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define MPS_BS		2	/* 4 MByte */
-#define MPS_BS_B		FLASH_SIZE_PRELIM	/* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define MPS_BU		3	/* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define MPS_BW		0	/* 8Bit */
-/* CR register for Boot */
-#define MPS_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13))
-/* CR register for non Boot */
-#define MPS_CR		((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
diff --git a/board/mpl/pati/Kconfig b/board/mpl/pati/Kconfig
deleted file mode 100644
index b141da3..0000000
--- a/board/mpl/pati/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_PATI
-
-config SYS_BOARD
-	default "pati"
-
-config SYS_VENDOR
-	default "mpl"
-
-config SYS_CONFIG_NAME
-	default "PATI"
-
-endif
diff --git a/board/mpl/pati/MAINTAINERS b/board/mpl/pati/MAINTAINERS
deleted file mode 100644
index 19ad05d..0000000
--- a/board/mpl/pati/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PATI BOARD
-#M:	-
-S:	Maintained
-F:	board/mpl/pati/
-F:	include/configs/PATI.h
-F:	configs/PATI_defconfig
diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile
deleted file mode 100644
index 9822082..0000000
--- a/board/mpl/pati/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:=  pati.o cmd_pati.o \
-		../common/common_util.o
diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c
deleted file mode 100644
index fcae5e0..0000000
--- a/board/mpl/pati/cmd_pati.c
+++ /dev/null
@@ -1,433 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Adapted for PATI
- */
-
-#include <common.h>
-#include <command.h>
-#define PLX9056_LOC
-#include "plx9056.h"
-#include "pati.h"
-#include "pci_eeprom.h"
-
-extern void show_pld_regs(void);
-extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-extern void user_led0(int led_on);
-extern void user_led1(int led_on);
-
-/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_SYS_PCI_CON_DEVICE)
-extern void pci_con_disc(void);
-extern void pci_con_connect(void);
-#endif
-
-/******************************************************************************
- * Eeprom Support
- ******************************************************************************/
-unsigned long get32(unsigned long addr)
-{
-	unsigned long *p=(unsigned long *)addr;
-	return *p;
-}
-
-void set32(unsigned long addr,unsigned long data)
-{
-	unsigned long *p=(unsigned long *)addr;
-	*p=data;
-}
-
-#define PCICFG_GET_REG(x)	(get32((x) + PCI_CONFIG_BASE))
-#define PCICFG_SET_REG(x,y)	(set32((x) + PCI_CONFIG_BASE,(y)))
-
-
-/******************************************************************************
- * reload_pci_eeprom
- ******************************************************************************/
-
-static void reload_pci_eeprom(void)
-{
-	unsigned long reg;
-	/* Set Bit 29 and clear it again */
-	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
-	udelay(1);
-	/* set it*/
-	reg|=(1<<29);
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
-	/* EECLK @ 33MHz = 125kHz
-	 * -> extra long load = 32 * 16bit = 512Bit @ 125kHz = 4.1msec
-	 * use 20msec
-	 */
-	udelay(20000); /* wait 20ms */
-	reg &= ~(1<<29); /* set it low */
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
-	udelay(1); /* wait some time */
-}
-
-/******************************************************************************
- * clock_pci_eeprom
- ******************************************************************************/
-
-static void clock_pci_eeprom(void)
-{
-	unsigned long reg;
-	/* clock is low, data is valid */
-	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
-	udelay(1);
-	/* set clck high */
-	reg|=(1<<24);
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
-	udelay(1); /* wait some time */
-	reg &= ~(1<<24); /* set clock low */
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
-	udelay(1); /* wait some time */
-}
-
-/******************************************************************************
- * send_pci_eeprom_cmd
- ******************************************************************************/
-static void send_pci_eeprom_cmd(unsigned long cmd, unsigned char len)
-{
-	unsigned long reg;
-	int i;
-	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
-	/* Clear all EEPROM bits */
-	reg &= ~(0xF << 24);
-	/* Toggle EEPROM's Chip select to get it out of Shift Register Mode */
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
-	udelay(1); /* wait some time */
-	/* Enable EEPROM Chip Select */
-	reg |= (1 << 25);
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
-	/* Send EEPROM command - one bit at a time */
-	for (i = (int)(len-1); i >= 0; i--) {
-		/* Check if current bit is 0 or 1 */
-		if (cmd & (1 << i))
-			PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26)));
-		else
-			PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
-		clock_pci_eeprom();
-	}
-}
-
-/******************************************************************************
- * write_pci_eeprom_offs
- ******************************************************************************/
-static void write_pci_eeprom_offs(unsigned short offset, unsigned short value)
-{
-	unsigned long reg;
-	int bitpos, cmdshft, cmdlen, timeout;
-	/* we're using the Eeprom 93CS66 */
-	cmdshft  = 2;
-	cmdlen = EE66_CMD_LEN;
-	/* Send Write_Enable command to EEPROM */
-	send_pci_eeprom_cmd((EE_WREN << cmdshft),cmdlen);
-	/* Send EEPROM Write command and offset to EEPROM */
-	send_pci_eeprom_cmd((EE_WRITE << cmdshft) | (offset / 2),cmdlen);
-	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
-	/* Clear all EEPROM bits */
-	reg &= ~(0xF << 24);
-	/* Make sure EEDO Input is disabled for some PLX chips */
-	reg &= ~(1 << 31);
-	/* Enable EEPROM Chip Select */
-	reg |= (1 << 25);
-	/* Write 16-bit value to EEPROM - one bit at a time */
-	for (bitpos = 15; bitpos >= 0; bitpos--) {
-		/* Get bit value and shift into result */
-		if (value & (1 << bitpos))
-			PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26)));
-		else
-			PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg );
-		clock_pci_eeprom();
-	} /* for */
-	/* Deselect Chip */
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(1 << 25));
-	/* Re-select Chip */
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 25));
-	/* A small delay is needed to let EEPROM complete */
-	timeout = 0;
-	do {
-		udelay(10);
-		reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
-		timeout++;
-	} while (((reg & (1 << 27)) == 0) && timeout < 20000);
-	/* Send Write_Disable command to EEPROM */
-	send_pci_eeprom_cmd((EE_WDS << cmdshft),cmdlen);
-	/* Clear Chip Select and all other EEPROM bits */
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24));
-}
-
-
-/******************************************************************************
- * read_pci_eeprom_offs
- ******************************************************************************/
-static void read_pci_eeprom_offs(unsigned short offset, unsigned short *pvalue)
-{
-	unsigned long reg;
-	int bitpos, cmdshft, cmdlen;
-	/* we're using the Eeprom 93CS66 */
-	cmdshft  = 2;
-	cmdlen = EE66_CMD_LEN;
-	/* Send EEPROM read command and offset to EEPROM */
-	send_pci_eeprom_cmd((EE_READ << cmdshft) | (offset / 2),cmdlen);
-	/* Set EEPROM write output bit */
-	reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
-	/* Set EEDO Input enable */
-	reg |= (1 << 31);
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 26));
-	/* Get 16-bit value from EEPROM - one bit at a time */
-	for (bitpos = 0; bitpos < 16; bitpos++) {
-		clock_pci_eeprom();
-		udelay(10);
-		reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
-		/* Get bit value and shift into result */
-		if (reg & (1 << 27))
-			*pvalue = (unsigned short)((*pvalue << 1) | 1);
-		else
-			*pvalue = (unsigned short)(*pvalue << 1);
-	}
-	/* Clear EEDO Input enable */
-	reg &= ~(1 << 31);
-	/* Clear Chip Select and all other EEPROM bits */
-	PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24));
-}
-
-
-/******************************************************************************
- * EEPROM read/writes
-******************************************************************************/
-
-#undef EEPROM_DBG
-static int pati_pci_eeprom_erase(void)
-{
-	int i;
-	printf("Erasing EEPROM ");
-	for( i=0; i < PATI_EEPROM_LAST_OFFSET; i+=2) {
-		write_pci_eeprom_offs(i,0xffff);
-		if((i%0x10))
-			printf(".");
-	}
-	printf("\nDone\n");
-	return 0;
-}
-
-static int pati_pci_eeprom_prg(void)
-{
-	int i;
-	i=0;
-	printf("Programming EEPROM ");
-	while(pati_eeprom[i].offset<0xffff) {
-		write_pci_eeprom_offs(pati_eeprom[i].offset,pati_eeprom[i].value);
-		#ifdef EEPROM_DBG
-		printf("0x%04X: 0x%04X\n",pati_eeprom[i].offset, pati_eeprom[i].value);
-		#else
-		if((i%0x10))
-			printf(".");
-		#endif
-		i++;
-	}
-	printf("\nDone\n");
-	return 0;
-}
-
-static int pati_pci_eeprom_write(unsigned short offset, unsigned long addr, unsigned short size)
-{
-	int i;
-	unsigned short value;
-	unsigned short *buffer =(unsigned short *)addr;
-	if((offset + size) > PATI_EEPROM_LAST_OFFSET) {
-		size = PATI_EEPROM_LAST_OFFSET - offset;
-	}
-	printf("Write To EEPROM from 0x%lX to 0x%X 0x%X words\n", addr, offset, size/2);
-	for( i = offset; i< (offset + size); i+=2) {
-		value = *buffer++;
-		write_pci_eeprom_offs(i,value);
-		#ifdef EEPROM_DBG
-		printf("0x%04X: 0x%04X\n",i, value);
-		#else
-		if((i%0x10))
-			printf(".");
-		#endif
-	}
-	printf("\nDone\n");
-	return 0;
-}
-
-static int pati_pci_eeprom_read(unsigned short offset, unsigned long addr, unsigned short size)
-{
-	int i;
-	unsigned short value = 0;
-	unsigned short *buffer =(unsigned short *)addr;
-	if((offset + size) > PATI_EEPROM_LAST_OFFSET) {
-		size = PATI_EEPROM_LAST_OFFSET - offset;
-	}
-	printf("Read from EEPROM from 0x%X to 0x%lX 0x%X words\n", offset, addr, size/2);
-	for( i = offset; i< (offset + size); i+=2) {
-		read_pci_eeprom_offs(i,&value);
-		*buffer++=value;
-		#ifdef EEPROM_DBG
-		printf("0x%04X: 0x%04X\n",i, value);
-		#else
-		if((i%0x10))
-			printf(".");
-		#endif
-	}
-	printf("\nDone\n");
-	return 0;
-}
-
-/******************************************************************************
- * PCI Bridge Registers Dump
-*******************************************************************************/
-static void display_pci_regs(void)
-{
-	printf(" PCI9056_SPACE0_RANGE     %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_RANGE));
-	printf(" PCI9056_SPACE0_REMAP     %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_REMAP));
-	printf(" PCI9056_LOCAL_DMA_ARBIT  %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_DMA_ARBIT));
-	printf(" PCI9056_ENDIAN_DESC      %08lX\n",PCICFG_GET_REG(PCI9056_ENDIAN_DESC));
-	printf(" PCI9056_EXP_ROM_RANGE    %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_RANGE));
-	printf(" PCI9056_EXP_ROM_REMAP    %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_REMAP));
-	printf(" PCI9056_SPACE0_ROM_DESC  %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_ROM_DESC));
-	printf(" PCI9056_DM_RANGE         %08lX\n",PCICFG_GET_REG(PCI9056_DM_RANGE));
-	printf(" PCI9056_DM_MEM_BASE      %08lX\n",PCICFG_GET_REG(PCI9056_DM_MEM_BASE));
-	printf(" PCI9056_DM_IO_BASE       %08lX\n",PCICFG_GET_REG(PCI9056_DM_IO_BASE));
-	printf(" PCI9056_DM_PCI_MEM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_MEM_REMAP));
-	printf(" PCI9056_DM_PCI_IO_CONFIG %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_IO_CONFIG));
-	printf(" PCI9056_SPACE1_RANGE     %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_RANGE));
-	printf(" PCI9056_SPACE1_REMAP     %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_REMAP));
-	printf(" PCI9056_SPACE1_DESC      %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_DESC));
-	printf(" PCI9056_DM_DAC           %08lX\n",PCICFG_GET_REG(PCI9056_DM_DAC));
-	printf(" PCI9056_MAILBOX0         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX0));
-	printf(" PCI9056_MAILBOX1         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX1));
-	printf(" PCI9056_MAILBOX2         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX2));
-	printf(" PCI9056_MAILBOX3         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX3));
-	printf(" PCI9056_MAILBOX4         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX4));
-	printf(" PCI9056_MAILBOX5         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX5));
-	printf(" PCI9056_MAILBOX6         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX6));
-	printf(" PCI9056_MAILBOX7         %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX7));
-	printf(" PCI9056_PCI_TO_LOC_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_PCI_TO_LOC_DBELL));
-	printf(" PCI9056_LOC_TO_PCI_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_LOC_TO_PCI_DBELL));
-	printf(" PCI9056_INT_CTRL_STAT    %08lX\n",PCICFG_GET_REG(PCI9056_INT_CTRL_STAT));
-	printf(" PCI9056_EEPROM_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT));
-	printf(" PCI9056_PERM_VENDOR_ID   %08lX\n",PCICFG_GET_REG(PCI9056_PERM_VENDOR_ID));
-	printf(" PCI9056_REVISION_ID      %08lX\n",PCICFG_GET_REG(PCI9056_REVISION_ID));
-	printf(" \n");
-	printf(" PCI9056_VENDOR_ID        %08lX\n",PCICFG_GET_REG(PCI9056_VENDOR_ID));
-	printf(" PCI9056_COMMAND          %08lX\n",PCICFG_GET_REG(PCI9056_COMMAND));
-	printf(" PCI9056_REVISION         %08lX\n",PCICFG_GET_REG(PCI9056_REVISION));
-	printf(" PCI9056_CACHE_SIZE       %08lX\n",PCICFG_GET_REG(PCI9056_CACHE_SIZE));
-	printf(" PCI9056_RTR_BASE         %08lX\n",PCICFG_GET_REG(PCI9056_RTR_BASE));
-	printf(" PCI9056_RTR_IO_BASE      %08lX\n",PCICFG_GET_REG(PCI9056_RTR_IO_BASE));
-	printf(" PCI9056_LOCAL_BASE0      %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE0));
-	printf(" PCI9056_LOCAL_BASE1      %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE1));
-	printf(" PCI9056_UNUSED_BASE1     %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE1));
-	printf(" PCI9056_UNUSED_BASE2     %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE2));
-	printf(" PCI9056_CIS_PTR          %08lX\n",PCICFG_GET_REG(PCI9056_CIS_PTR));
-	printf(" PCI9056_SUB_ID           %08lX\n",PCICFG_GET_REG(PCI9056_SUB_ID));
-	printf(" PCI9056_EXP_ROM_BASE     %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_BASE));
-	printf(" PCI9056_CAP_PTR          %08lX\n",PCICFG_GET_REG(PCI9056_CAP_PTR));
-	printf(" PCI9056_INT_LINE         %08lX\n",PCICFG_GET_REG(PCI9056_INT_LINE));
-	printf(" PCI9056_PM_CAP_ID        %08lX\n",PCICFG_GET_REG(PCI9056_PM_CAP_ID));
-	printf(" PCI9056_PM_CSR           %08lX\n",PCICFG_GET_REG(PCI9056_PM_CSR));
-	printf(" PCI9056_HS_CAP_ID        %08lX\n",PCICFG_GET_REG(PCI9056_HS_CAP_ID));
-	printf(" PCI9056_VPD_CAP_ID       %08lX\n",PCICFG_GET_REG(PCI9056_VPD_CAP_ID));
-	printf(" PCI9056_VPD_DATA         %08lX\n",PCICFG_GET_REG(PCI9056_VPD_DATA));
-}
-
-
-int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	if (strcmp(argv[1], "info") == 0)
-	{
-		show_pld_regs();
-		return 0;
-	}
-	if (strcmp(argv[1], "pci") == 0)
-	{
-		display_pci_regs();
-		return 0;
-	}
-	if (strcmp(argv[1], "led") == 0)
-	{
-		int led_nr,led_on;
-		led_nr = (int)simple_strtoul(argv[2], NULL, 10);
-		led_on = (int)simple_strtoul(argv[3], NULL, 10);
-		if(!led_nr)
-			user_led0(led_on);
-		else
-			user_led1(led_on);
-		return 0;
-	}
-#if defined(CONFIG_SYS_PCI_CON_DEVICE)
-	if (strcmp(argv[1], "con") == 0) {
-		pci_con_connect();
-		return 0;
-	}
-	if (strcmp(argv[1], "disc") == 0) {
-		pci_con_disc();
-		return 0;
-	}
-#endif
-	if (strcmp(argv[1], "eeprom") == 0) {
-		unsigned long addr;
-		int size, offset;
-		offset = 0;
-		size = PATI_EEPROM_LAST_OFFSET;
-		if(argc>2) {
-			if(argc>3) {
-				addr = simple_strtoul(argv[3], NULL, 16);
-				if(argc>4)
-					offset = (int) simple_strtoul(argv[4], NULL, 16);
-				if(argc>5)
-					size = (int) simple_strtoul(argv[5], NULL, 16);
-				if (strcmp(argv[2], "read") == 0) {
-					return (pati_pci_eeprom_read(offset, addr, size));
-				}
-				if (strcmp(argv[2], "write") == 0) {
-					return (pati_pci_eeprom_write(offset, addr, size));
-				}
-			}
-			if (strcmp(argv[2], "prg") == 0) {
-				return (pati_pci_eeprom_prg());
-			}
-			if (strcmp(argv[2], "era") == 0) {
-				return (pati_pci_eeprom_erase());
-			}
-			if (strcmp(argv[2], "reload") == 0) {
-				reload_pci_eeprom();
-				return 0;
-			}
-
-
-		}
-	}
-
-	return (do_mplcommon(cmdtp, flag, argc, argv));
-}
-
-U_BOOT_CMD(
-	pati,	8,	1,	do_pati,
-	"PATI specific Cmds",
-	"info - displays board information\n"
-	"pati pci  - displays PCI registers\n"
-	"pati led <nr> <on> \n"
-	"          - switch LED <nr> <on>\n"
-	"pati flash mem [SrcAddr]\n"
-	"          - updates U-Boot with image in memory\n"
-	"pati eeprom <cmd> - PCI EEPROM sub-system\n"
-	"    read <addr> <offset> <size>\n"
-	"          - read PCI EEPROM to <addr> from <offset> <size> words\n"
-	"    write <addr> <offset> <size>\n"
-	"          - write PCI EEPROM from <addr> to <offset> <size> words\n"
-	"    prg   - programm PCI EEPROM with default values\n"
-	"    era   - erase PCI EEPROM (write all word to 0xffff)\n"
-	"    reload- Reload PCI Bridge with EEPROM Values\n"
-	"    NOTE: <addr> must start on word boundary\n"
-	"          <offset> and <size> must be even byte values"
-);
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c
deleted file mode 100644
index ddc2108..0000000
--- a/board/mpl/pati/pati.c
+++ /dev/null
@@ -1,606 +0,0 @@
-/*
- * (C) Copyright 2003
- * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
- * Atapted for PATI
- * Denis Peter, d.peter@mpl.ch
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/***********************************************************************************
- * Bits for the SDRAM controller
- * -----------------------------
- *
- * CAL:	CAS Latency. If cleared to 0 (default) the SDRAM controller asserts TA# on
- *	the 2nd Clock after ACTIVE command (CAS Latency = 2). If set to 1 the SDRAM
- *	controller asserts TA# on the 3rd Clock after ACTIVE command (CAS Latency = 3).
- * RCD:	RCD ACTIVE to READ or WRITE Delay (Ras to Cas Delay). If cleared 0 (default)
- *	tRCD of the SDRAM must equal or less 25ns. If set to 1 tRCD must be equal or less 50ns.
- * WREC:Write Recovery. If cleared 0 (default) tWR of the SDRAM must equal or less 25ns.
- *	If set to 1 tWR must be equal or less 50ns.
- * RP:	Precharge Command Time. If cleared 0 (default) tRP of the SDRAM must equal or less
- *	25ns. If set to 1 tRP must be equal or less 50ns.
- * RC:	Auto Refresh to Active Time. If cleared 0 (default) tRC of the SDRAM must equal
- *	or less 75ns. If set to 1 tRC must be equal or less 100ns.
- * LMR:	Bit to set the Mode Register of the SDRAM. If set, the next access to the SDRAM
- *	is the Load Mode Register Command.
- * IIP:	Init in progress. Set to 1 for starting the init sequence
- *	(Precharge All). As long this bit is set, the Precharge All is still in progress.
- *	After command has completed, wait at least for 8 refresh (200usec) before proceed.
- **********************************************************************************/
-
-#include <common.h>
-#include <console.h>
-#include <mpc5xx.h>
-#include <stdio_dev.h>
-#include <pci_ids.h>
-#define PLX9056_LOC
-#include "plx9056.h"
-#include "pati.h"
-
-#if defined(__APPLE__)
-/* Leading underscore on symbols */
-#  define SYM_CHAR "_"
-#else /* No leading character on symbols */
-#  define SYM_CHAR
-#endif
-
-#undef SDRAM_DEBUG
-/*
- * Macros to generate global absolutes.
- */
-#define GEN_SYMNAME(str) SYM_CHAR #str
-#define GEN_VALUE(str) #str
-#define GEN_ABS(name, value) \
-		asm (".globl " GEN_SYMNAME(name)); \
-		asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
-
-
-/************************************************************************
- * Early debug routines
- */
-void write_hex (unsigned char i)
-{
-	char cc;
-
-	cc = i >> 4;
-	cc &= 0xf;
-	if (cc > 9)
-		serial_putc (cc + 55);
-	else
-		serial_putc (cc + 48);
-	cc = i & 0xf;
-	if (cc > 9)
-		serial_putc (cc + 55);
-	else
-		serial_putc (cc + 48);
-}
-
-#if defined(SDRAM_DEBUG)
-
-void write_4hex (unsigned long val)
-{
-	write_hex ((unsigned char) (val >> 24));
-	write_hex ((unsigned char) (val >> 16));
-	write_hex ((unsigned char) (val >> 8));
-	write_hex ((unsigned char) val);
-}
-
-#endif
-
-unsigned long in32(unsigned long addr)
-{
-	unsigned long *p=(unsigned long *)addr;
-	return *p;
-}
-
-void out32(unsigned long addr,unsigned long data)
-{
-	unsigned long *p=(unsigned long *)addr;
-	*p=data;
-}
-
-typedef struct {
-	unsigned short boardtype; /* Board revision and Population Options */
-	unsigned char cal;		/* cas Latency  0:CAL=2 1:CAL=3 */
-	unsigned char rcd;		/* ras to cas delay  0:<25ns 1:<50ns*/
-	unsigned char wrec;		/* write recovery 0:<25ns 1:<50ns */
-	unsigned char pr;		/* Precharge Command Time 0:<25ns 1:<50ns */
-	unsigned char rc;		/* Auto Refresh to Active Time 0:<75ns 1:<100ns */
-	unsigned char sz;		/* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
-} sdram_t;
-
-const sdram_t sdram_table[] = {
-	{ 0x0000,	/* PATI Rev A, 16MByte -1 Board */
-		1,	/* Case Latenty = 3 */
-		0,	/* ras to cas delay  0 (20ns) */
-		0,	/* write recovery 0:<25ns 1:<50ns*/
-		0,	/* Precharge Command Time 0 (20ns) */
-		0,	/* Auto Refresh to Active Time 0 (68) */
-		2	/* log binary => Size 2 = 16MByte, 1=8 */
-	},
-	{ 0xffff, /* terminator */
-	  0xff,
-	  0xff,
-	  0xff,
-	  0xff,
-	  0xff,
-	  0xff }
-};
-
-
-extern int mem_test (unsigned long start, unsigned long ramsize, int quiet);
-
-/*
- * Get RAM size.
- */
-phys_size_t initdram(int board_type)
-{
-	unsigned char board_rev;
-	unsigned long reg;
-	unsigned long lmr;
-	int i,timeout;
-
-#if defined(SDRAM_DEBUG)
-	reg=in32(PLD_CONFIG_BASE+PLD_PART_ID);
-	puts("\n\nSYSTEM part 0x"); write_4hex(SYSCNTR_PART(reg));
-	puts(" Vers 0x"); write_4hex(SYSCNTR_ID(reg));
-	puts("\nSDRAM  part  0x"); write_4hex(SDRAM_PART(reg));
-	puts(" Vers 0x"); write_4hex(SDRAM_ID(reg));
-	reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
-	puts("\nBoard rev.   0x"); write_4hex(SYSCNTR_BREV(reg));
-   putc('\n');
-#endif
-	reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
-	board_rev=(unsigned char)(SYSCNTR_BREV(reg));
-	i=0;
-	while(1) {
-		if(sdram_table[i].boardtype==0xffff) {
-			puts("ERROR, found no table for Board 0x");
-			write_hex(board_rev);
-			while(1);
-		}
-		if(sdram_table[i].boardtype==(unsigned char)board_rev)
-			break;
-		i++;
-	}
-	/* Set CAL, RCD, WREQ, PR and RC Bits */
-#if defined(SDRAM_DEBUG)
-	puts("Set CAL, RCD, WREQ, PR and RC Bits\n");
-#endif
-	/* mask bits */
-	reg &= ~(SET_REG_BIT(1,SDRAM_CAL) | SET_REG_BIT(1,SDRAM_RCD) | SET_REG_BIT(1,SDRAM_WREQ) |
-				SET_REG_BIT(1,SDRAM_PR)  |  SET_REG_BIT(1,SDRAM_RC) | SET_REG_BIT(1,SDRAM_LMR)  |
-				SET_REG_BIT(1,SDRAM_IIP) | SET_REG_BIT(1,SDRAM_RES0));
-	/* set bits */
-	reg |= (SET_REG_BIT(sdram_table[i].cal,SDRAM_CAL) |
-			  SET_REG_BIT(sdram_table[i].rcd,SDRAM_RCD) |
-			  SET_REG_BIT(sdram_table[i].wrec,SDRAM_WREQ) |
-			  SET_REG_BIT(sdram_table[i].pr,SDRAM_PR) |
-			  SET_REG_BIT(sdram_table[i].rc,SDRAM_RC));
-
-	out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg);
-	/* step 2 set IIP */
-#if defined(SDRAM_DEBUG)
-	puts("step 2 set IIP\n");
-#endif
-	/* step 2 set IIP */
-	reg |= SET_REG_BIT(1,SDRAM_IIP);
-	timeout=0;
-	while (timeout!=0xffff) {
-		__asm__ volatile("eieio");
-		reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
-		if((reg & SET_REG_BIT(1,SDRAM_IIP))==0)
-			break;
-		timeout++;
-		udelay(1);
-	}
-	/* wait for at least 8 refresh */
-	udelay(1000);
-	/* set LMR */
-	reg |= SET_REG_BIT(1,SDRAM_LMR);
-	out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg);
-	__asm__ volatile("eieio");
-	lmr=0x00000002; /* sequential burst 4 data */
-	if(sdram_table[i].cal==1)
-		lmr|=0x00000030; /* cal = 3 */
-	else
-		lmr|=0000000020; /* cal = 2 */
-	/* rest standard operation programmed write burst length */
-	/* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */
-	lmr<<=2;
-	in32(CONFIG_SYS_SDRAM_BASE + lmr);
-	/* ok, we're done, return SDRAM size */
-	return ((0x400000 << sdram_table[i].sz));		/* log2 value of 4MByte  */
-}
-
-
-void set_flash_vpp(int ext_vpp, int ext_wp, int int_vpp)
-{
-	unsigned long reg;
-	reg=in32(PLD_CONF_REG2+PLD_CONFIG_BASE);
-	reg &= ~(SET_REG_BIT(1,SYSCNTR_CPU_VPP) |
-			   SET_REG_BIT(1,SYSCNTR_FL_VPP) |
-				SET_REG_BIT(1,SYSCNTR_FL_WP));
-
-	reg |= (SET_REG_BIT(int_vpp,SYSCNTR_CPU_VPP) |
-			   SET_REG_BIT(ext_vpp,SYSCNTR_FL_VPP) |
-				SET_REG_BIT(ext_wp,SYSCNTR_FL_WP));
-	out32(PLD_CONF_REG2+PLD_CONFIG_BASE,reg);
-	udelay(100);
-}
-
-
-void show_pld_regs(void)
-{
-	unsigned long reg,reg1;
-	reg=in32(PLD_CONFIG_BASE+PLD_PART_ID);
-	printf("\nSYSTEM part %ld, Vers %ld\n",SYSCNTR_PART(reg),SYSCNTR_ID(reg));
-	printf("SDRAM  part %ld, Vers %ld\n",SDRAM_PART(reg),SDRAM_ID(reg));
-	reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
-	printf("Board rev.  %c\n",(char) (SYSCNTR_BREV(reg)+'A'));
-	printf("Waitstates  %ld\n",GET_SYSCNTR_FLWAIT(reg));
-	printf("SDRAM:      CAL=%ld RCD=%ld WREQ=%ld PR=%ld\n            RC=%ld  LMR=%ld IIP=%ld\n",
-		GET_REG_BIT(reg,SDRAM_CAL),GET_REG_BIT(reg,SDRAM_RCD),
-		GET_REG_BIT(reg,SDRAM_WREQ),GET_REG_BIT(reg,SDRAM_PR),
-		GET_REG_BIT(reg,SDRAM_RC),GET_REG_BIT(reg,SDRAM_LMR),
-		GET_REG_BIT(reg,SDRAM_IIP));
-	reg=in32(PLD_CONFIG_BASE+PLD_CONF_REG1);
-	reg1=in32(PLD_CONFIG_BASE+PLD_CONF_REG2);
-	printf("HW Config:  FLAG=%ld IP=%ld  index=%ld PRPM=%ld\n            ICW=%ld  ISB=%ld BDIS=%ld  PCIM=%ld\n",
-		GET_REG_BIT(reg,SYSCNTR_FLAG),GET_REG_BIT(reg,SYSCNTR_IP),
-		GET_SYSCNTR_BOOTIND(reg),GET_REG_BIT(reg,SYSCNTR_PRM),
-		GET_REG_BIT(reg,SYSCNTR_ICW),GET_SYSCNTR_ISB(reg),
-		GET_REG_BIT(reg1,SYSCNTR_BDIS),GET_REG_BIT(reg1,SYSCNTR_PCIM));
-	printf("Switches:   MUX=%ld PCI_DIS=%ld Boot_EN=%ld  Config=%ld\n",GET_SDRAM_MUX(reg),
-		GET_REG_BIT(reg,SDRAM_PDIS),GET_REG_BIT(reg1,SYSCNTR_BOOTEN),
-		GET_SYSCNTR_CFG(reg1));
-	printf("Misc:       RIP=%ld CPU_VPP=%ld FLSH_VPP=%ld FLSH_WP=%ld\n\n",
-		GET_REG_BIT(reg,SDRAM_RIP),GET_REG_BIT(reg1,SYSCNTR_CPU_VPP),
-		GET_REG_BIT(reg1,SYSCNTR_FL_VPP),GET_REG_BIT(reg1,SYSCNTR_FL_WP));
-}
-
-
-/****************************************************************
- * Setting IOs
- * -----------
- * GPIO6 is User LED1
- * GPIO7 is Interrupt PLX (Output)
- * GPIO5 is User LED0
- * GPIO2 is PLX USERi (Output)
- * GPIO1 is PLX Interrupt (Input)
- ****************************************************************/
- void init_ios(void)
- {
-	volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
-	volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
-	unsigned long reg;
-	reg=sysconf->sc_sgpiocr; /* Data direction register */
-	reg &= ~0x67000000;
-	reg |= 0x27000000; /* set outpupts */
-	sysconf->sc_sgpiocr=reg; /* Data direction register */
-	reg=sysconf->sc_sgpiodt2; /* Data register */
-	/* set output to 0 */
-	reg &= ~0x27000000;
-	/* set IRQ and USERi to 1 */
-	reg |= 0x28000000;
-	sysconf->sc_sgpiodt2=reg; /* Data register */
-}
-
-void user_led0(int led_on)
-{
-	volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
-	volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
-	unsigned long reg;
-	reg=sysconf->sc_sgpiodt2; /* Data register */
-	if(led_on)	/* set output to 1 */
-		reg |= 0x04000000;
-	else
-		reg &= ~0x04000000;
-	sysconf->sc_sgpiodt2=reg; /* Data register */
-}
-
-void user_led1(int led_on)
-{
-	volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
-	volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
-	unsigned long reg;
-	reg=sysconf->sc_sgpiodt2; /* Data register */
-	if(led_on)	/* set output to 1 */
-		reg |= 0x02000000;
-	else
-		reg &= ~0x02000000;
-	sysconf->sc_sgpiodt2=reg; /* Data register */
-}
-
-int board_early_init_f(void)
-{
-	spi_init_f();
-	return 0;
-}
-
-/****************************************************************
- * Last Stage Init
- ****************************************************************/
-int last_stage_init (void)
-{
-	init_ios();
-	return 0;
-}
-
-/****************************************************************
- * Check the board
- ****************************************************************/
-
-#define BOARD_NAME	"PATI"
-
-int checkboard (void)
-{
-	char s[50];
-	ulong reg;
-	char rev;
-	int i;
-
-	puts ("\nBoard: ");
-	reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
-	rev=(char)(SYSCNTR_BREV(reg)+'A');
-	i = getenv_f("serial#", s, 32);
-	if ((i == -1)) {
-		puts ("### No HW ID - assuming " BOARD_NAME);
-		printf(" Rev. %c\n",rev);
-	}
-	else {
-		s[sizeof(BOARD_NAME)-1] = 0;
-		printf ("%s-1 Rev %c SN: %s\n", s,rev,
-				&s[sizeof(BOARD_NAME)]);
-	}
-	set_flash_vpp(1,0,0); /* set Flash VPP */
-	return 0;
-}
-
-
-#ifdef CONFIG_SYS_PCI_CON_DEVICE
-/************************************************************************
- * PCI Communication
- *
- * Alive (Pinging):
- * ----------------
- * PCI Host sends message ALIVE, Local acknowledges with ALIVE
- *
- * PCI_CON console over PCI:
- * -------------------------
- * Local side:
- *     - uses PCI9056_LOC_TO_PCI_DBELL register to signal that
- *       data is avaible (PCIMSG_CONN)
- *     - uses PCI9056_MAILBOX1 to send data
- *     - uses PCI9056_MAILBOX0 to receive data
- * PCI side:
- *     - uses PCI9056_PCI_TO_LOC_DBELL register to signal that
- *       data is avaible (PCIMSG_CONN)
- *     - uses PCI9056_MAILBOX0 to send data
- *     - uses PCI9056_MAILBOX1 to receive data
- *
- * How it works:
- *     Send:
- *     - check if PCICON_TRANSMIT_REG is empty
- *     - write data or'ed with 0x80000000 into the PCICON_TRANSMIT_REG
- *     - write PCIMSG_CONN into the PCICON_DBELL_REG to signal a data
- *       is waiting
- *     Receive:
- *     - get an interrupt via the PCICON_ACK_REG register message
- *       PCIMSG_CONN
- *     - write the data from the PCICON_RECEIVE_REG into the receive
- *       buffer and if the receive buffer is not full, clear the
- *       PCICON_RECEIVE_REG (this allows the counterpart to write more data)
- *     - Clear the interrupt by writing 0xFFFFFFFF to the PCICON_ACK_REG
- *
- *     The PCICON_RECEIVE_REG must be cleared by the routine which reads
- *     the receive buffer if the buffer is not full any more
- *
- */
-
-#undef PCI_CON_DEBUG
-
-#ifdef	PCI_CON_DEBUG
-#define	PCI_CON_PRINTF(fmt,args...)	serial_printf (fmt ,##args)
-#else
-#define PCI_CON_PRINTF(fmt,args...)
-#endif
-
-
-/*********************************************************
- * we work only with a receive buffer on eiter side.
- * Transmit buffer is free, if mailbox is cleared.
- * Transmit character is or'ed with 0x80000000
- * PATI receive register MAILBOX0
- * PATI transmit register MAILBOX1
- *********************************************************/
-#define PCICON_RECEIVE_REG	PCI9056_MAILBOX0
-#define PCICON_TRANSMIT_REG	PCI9056_MAILBOX1
-#define PCICON_DBELL_REG	PCI9056_LOC_TO_PCI_DBELL
-#define PCICON_ACK_REG		PCI9056_PCI_TO_LOC_DBELL
-
-
-#define PCIMSG_ALIVE		0x1
-#define PCIMSG_CONN		0x2
-#define PCIMSG_DISC		0x3
-#define PCIMSG_CON_DATA	0x5
-
-
-#define PCICON_GET_REG(x)	(in32(x + PCI_CONFIG_BASE))
-#define PCICON_SET_REG(x,y)	(out32(x + PCI_CONFIG_BASE,y))
-#define PCICON_TX_FLAG		0x80000000
-
-
-#define REC_BUFFER_SIZE	0x100
-int recbuf[REC_BUFFER_SIZE];
-static int r_ptr = 0;
-int w_ptr;
-struct stdio_dev pci_con_dev;
-int conn=0;
-int buff_full=0;
-
-void pci_con_put_it(const char c)
-{
-	/* Test for completition */
-	unsigned long reg;
-	do {
-		reg=PCICON_GET_REG(PCICON_TRANSMIT_REG);
-	}while(reg);
-	reg=PCICON_TX_FLAG + c;
-	PCICON_SET_REG(PCICON_TRANSMIT_REG,reg);
-	PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA);
-}
-
-void pci_con_putc(struct stdio_dev *dev, const char c)
-{
-	pci_con_put_it(c);
-	if(c == '\n')
-		pci_con_put_it('\r');
-}
-
-
-int pci_con_getc(struct stdio_dev *dev)
-{
-	int res;
-	int diff;
-	while(r_ptr==(volatile int)w_ptr);
-	res=recbuf[r_ptr++];
-	if(r_ptr==REC_BUFFER_SIZE)
-		r_ptr=0;
-	if(w_ptr<r_ptr)
-		diff=r_ptr+REC_BUFFER_SIZE-w_ptr;
-	else
-		diff=r_ptr-w_ptr;
-	if((diff<(REC_BUFFER_SIZE-4)) && buff_full) {
-		/* clear Mail box */
-			buff_full=0;
-			PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
-	}
-	return res;
-}
-
-int pci_con_tstc(struct stdio_dev *dev)
-{
-	if(r_ptr==(volatile int)w_ptr)
-		return 0;
-	return 1;
-}
-
-void pci_con_puts(struct stdio_dev *dev, const char *s)
-{
-	while (*s) {
-		pci_con_putc(*s);
-		++s;
-	}
-}
-
-void pci_con_init (void)
-{
-	w_ptr = 0;
-	r_ptr = 0;
-	PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
-	conn=1;
-}
-
-/*******************************************
- * IRQ routine
- ******************************************/
-int pci_dorbell_irq(void)
-{
-	unsigned long reg,data;
-	int diff;
-	reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT);
-	PCI_CON_PRINTF(" PCI9056_INT_CTRL_STAT = %08lX\n",reg);
-	if(reg & (1<<20) ) {
-		/* read doorbell */
-		reg=PCICON_GET_REG(PCICON_ACK_REG);
-		switch(reg) {
-			case PCIMSG_ALIVE:
-				PCI_CON_PRINTF(" Alive\n");
-				PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_ALIVE);
-				break;
-			case PCIMSG_CONN:
-				PCI_CON_PRINTF(" Conn %d",conn);
-				w_ptr = 0;
-				r_ptr = 0;
-				buff_full=0;
-				PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
-				conn=1;
-				PCI_CON_PRINTF(" ... %d\n",conn);
-				break;
-			case PCIMSG_CON_DATA:
-				data=PCICON_GET_REG(PCICON_RECEIVE_REG);
-				recbuf[w_ptr++]=(int)(data&0xff);
-				PCI_CON_PRINTF(" Data Console %lX, %X %d %d %X\n",data,((int)(data&0xFF)),
-					r_ptr,w_ptr,recbuf[w_ptr-1]);
-				if(w_ptr==REC_BUFFER_SIZE)
-					w_ptr=0;
-				if(w_ptr<r_ptr)
-					diff=r_ptr+REC_BUFFER_SIZE-w_ptr;
-				else
-					diff=r_ptr-w_ptr;
-				if(diff>(REC_BUFFER_SIZE-4))
-					buff_full=1;
-				else
-					/* clear Mail box */
-					PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
-				break;
-			default:
-				serial_printf(" PCI9056_PCI_TO_LOC_DBELL = %08lX\n",reg);
-		}
-		/* clear IRQ */
-		PCICON_SET_REG(PCICON_ACK_REG,~0L);
-	}
-	return 0;
-}
-
-void pci_con_connect(void)
-{
-	unsigned long reg;
-	conn=0;
-	reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT);
-	/* default 0x0f010180 */
-	reg &= 0xff000000;
-	reg |= 0x00030000; /* enable local dorbell */
-	reg |= 0x00000300; /* enable PCI dorbell */
-	PCICON_SET_REG(PCI9056_INT_CTRL_STAT , reg);
-	irq_install_handler (0x2, (interrupt_handler_t *) pci_dorbell_irq,NULL);
-	memset (&pci_con_dev, 0, sizeof (pci_con_dev));
-	strcpy (pci_con_dev.name, "pci_con");
-	pci_con_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
-	pci_con_dev.putc = pci_con_putc;
-	pci_con_dev.puts = pci_con_puts;
-	pci_con_dev.getc = pci_con_getc;
-	pci_con_dev.tstc = pci_con_tstc;
-	stdio_register (&pci_con_dev);
-	printf("PATI ready for PCI connection, type ctrl-c for exit\n");
-	do {
-		udelay(10);
-		if((volatile int)conn)
-			break;
-		if(ctrlc()) {
-			irq_free_handler(0x2);
-			return;
-		}
-	}while(1);
-	console_assign(stdin,"pci_con");
-	console_assign(stderr,"pci_con");
-	console_assign(stdout,"pci_con");
-}
-
-void pci_con_disc(void)
-{
-	console_assign(stdin,"serial");
-	console_assign(stderr,"serial");
-	console_assign(stdout,"serial");
-	PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_DISC);
-	/* reconnection */
-	irq_free_handler(0x02);
-	pci_con_connect();
-}
-#endif /* #ifdef CONFIG_SYS_PCI_CON_DEVICE */
-
-/*
- * Absolute environment address for linker file.
- */
-GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE);
diff --git a/board/mpl/pati/pati.h b/board/mpl/pati/pati.h
deleted file mode 100644
index 2600bba..0000000
--- a/board/mpl/pati/pati.h
+++ /dev/null
@@ -1,424 +0,0 @@
-/*
- * (C) Copyright 2003
- * Denis Peter, d.peter@mpl.ch
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/************************************************************************
- * MACROS and register definitions for PATI Registers
- ************************************************************************/
-#ifndef __PATI_H_
-#define __PATI_H_	1
-
-#define PLD_PART_ID		0x0
-#define PLD_BOARD_TIMING	0x4
-#define PLD_CONF_REG1		0x8
-#define PLD_CONF_REG2		0xC
-#define PLD_CONF_RES		0x10
-
-#define SET_REG_BIT(y,x) (y<<(31-x))
-#define GET_REG_BIT(y,x) ((y>>(31-x)) & 0x1L)
-
-/* SDRAM Controller PLD_PART_ID */
-/* 9  10 11 12 13 14 19 31 */
-#define SDRAM_PART3	9
-#define SDRAM_PART2	10
-#define SDRAM_PART1	11
-#define SDRAM_PART0	12
-#define SDRAM_ID3	13
-#define SDRAM_ID2	14
-#define SDRAM_ID1	19
-#define SDRAM_ID0	31
-
-#define SDRAM_PART(x)	(	\
-	(GET_REG_BIT(x,SDRAM_PART3)<<3) |\
-	(GET_REG_BIT(x,SDRAM_PART2)<<2) |\
-	(GET_REG_BIT(x,SDRAM_PART1)<<1) |\
-	(GET_REG_BIT(x,SDRAM_PART0)))
-
-#define SDRAM_ID(x)	(	\
-	(GET_REG_BIT(x,SDRAM_ID3)<<3) |\
-	(GET_REG_BIT(x,SDRAM_ID2)<<2) |\
-	(GET_REG_BIT(x,SDRAM_ID1)<<1) |\
-	(GET_REG_BIT(x,SDRAM_ID0)))
-
-/* System Controller */
-/* 0  1 3 4 5 16 20 28 29 30 */
-#define SYSCNTR_PART4	0
-#define SYSCNTR_PART3	1
-#define SYSCNTR_PART2	3
-#define SYSCNTR_PART1	4
-#define SYSCNTR_PART0	5
-#define SYSCNTR_ID4	16
-#define SYSCNTR_ID3	20
-#define SYSCNTR_ID2	28
-#define SYSCNTR_ID1	29
-#define SYSCNTR_ID0	30
-
-#define SYSCNTR_PART(x)	(	\
-	(GET_REG_BIT(x,SYSCNTR_PART4)<<4) |\
-	(GET_REG_BIT(x,SYSCNTR_PART3)<<3) |\
-	(GET_REG_BIT(x,SYSCNTR_PART2)<<2) |\
-	(GET_REG_BIT(x,SYSCNTR_PART1)<<1) |\
-	(GET_REG_BIT(x,SYSCNTR_PART0)))
-
-#define SYSCNTR_ID(x)	(	\
-	(GET_REG_BIT(x,SYSCNTR_ID4)<<4) |\
-	(GET_REG_BIT(x,SYSCNTR_ID3)<<3) |\
-	(GET_REG_BIT(x,SYSCNTR_ID2)<<2) |\
-	(GET_REG_BIT(x,SYSCNTR_ID1)<<1) |\
-	(GET_REG_BIT(x,SYSCNTR_ID0)))
-
-/* SDRAM Controller PLD_BOARD_TIMING */
-/* 9  10 11 12 13 14 19 31 */
-#define SDRAM_CAL	9
-#define SDRAM_RCD	10
-#define SDRAM_WREQ	11
-#define SDRAM_PR	12
-#define SDRAM_RC	13
-#define SDRAM_LMR	14
-#define SDRAM_IIP	19
-#define SDRAM_RES0	31
-/* System Controller */
-/* 0  1 3 4 5 16 20 28 29 30 */
-#define SYSCNTR_BREV0	0
-#define SYSCNTR_BREV1	1
-#define SYSCNTR_BREV2	3
-#define SYSCNTR_BREV3	4
-#define SYSCNTR_RES0	5
-#define SYSCNTR_RES1	16
-#define SYSCNTR_RES2	20
-#define SYSCNTR_FLWAIT2	28
-#define SYSCNTR_FLWAIT1	29
-#define SYSCNTR_FLWAIT0	30
-
-#define SYSCNTR_BREV(x)	(	\
-	(GET_REG_BIT(x,SYSCNTR_BREV3)<<3) |\
-	(GET_REG_BIT(x,SYSCNTR_BREV2)<<2) |\
-	(GET_REG_BIT(x,SYSCNTR_BREV1)<<1) |\
-	(GET_REG_BIT(x,SYSCNTR_BREV0)))
-
-#define GET_SYSCNTR_FLWAIT(x)	(	\
-	(GET_REG_BIT(x,SYSCNTR_FLWAIT2)<<2) |\
-	(GET_REG_BIT(x,SYSCNTR_FLWAIT1)<<1) |\
-	(GET_REG_BIT(x,SYSCNTR_FLWAIT0)))
-
-#define SET_SYSCNTR_FLWAIT(x)	(	\
-	(SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_FLWAIT2)) |\
-	(SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_FLWAIT1)) |\
-	(SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_FLWAIT0)))
-
-/* SDRAM Controller REG 2*/
-/* 9  10 11 12 13 14 19 31 */
-#define SDRAM_MUX0	9
-#define SDRAM_MUX1	10
-#define SDRAM_PDIS	11
-#define SDRAM_RES1	12
-#define SDRAM_RES2	13
-#define SDRAM_RES3	14
-#define SDRAM_RES4	19
-#define SDRAM_RIP	31
-
-#define GET_SDRAM_MUX(x)	(	\
-	(GET_REG_BIT(x,SDRAM_MUX1)<<1)| \
-	(GET_REG_BIT(x,SDRAM_MUX0)))
-
-
-/* System Controller */
-/* 0  1 3 4 5 16 20 28 29 30 */
-#define SYSCNTR_FLAG	0
-#define SYSCNTR_IP	1
-#define SYSCNTR_BIND2	3
-#define SYSCNTR_BIND1	4
-#define SYSCNTR_BIND0	5
-#define SYSCNTR_PRM	16
-#define SYSCNTR_ICW	20
-#define SYSCNTR_ISB2	28
-#define SYSCNTR_ISB1	29
-#define SYSCNTR_ISB0	30
-
-#define GET_SYSCNTR_BOOTIND(x)	(	\
-	(GET_REG_BIT(x,SYSCNTR_BIND2)<<2) |\
-	(GET_REG_BIT(x,SYSCNTR_BIND1)<<1) |\
-	(GET_REG_BIT(x,SYSCNTR_BIND0)))
-
-#define SET_SYSCNTR_BOOTIND(x)	(	\
-	(SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_BIND2)) |\
-	(SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_BIND1))| \
-	(SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_BIND0)))
-
-#define GET_SYSCNTR_ISB(x)	(	\
-	(GET_REG_BIT(x,SYSCNTR_ISB2)<<2)| \
-	(GET_REG_BIT(x,SYSCNTR_ISB1)<<1)| \
-	(GET_REG_BIT(x,SYSCNTR_ISB0)))
-
-#define SET_SYSCNTR_ISB(x)	(	\
-	(SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_ISB2))| \
-	(SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_ISB))| \
-	(SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_ISB0)))
-
-/* SDRAM Controller REG 3*/
-/* 9  10 11 12 13 14 19 31 */
-#define SDRAM_RES5	9
-#define SDRAM_CFG1	10
-#define SDRAM_CFG2	11
-#define SDRAM_CFG3	12
-#define SDRAM_RES6	13
-#define SDRAM_CFG5	14
-#define SDRAM_CFG6	19
-#define SDRAM_RES7	31
-
-#define GET_SDRAM_CFG(x)	(	\
-	(GET_REG_BIT(x,SDRAM_CFG6)<<4) |\
-	(GET_REG_BIT(x,SDRAM_CFG5)<<3) |\
-	(GET_REG_BIT(x,SDRAM_CFG3)<<2) |\
-	(GET_REG_BIT(x,SDRAM_CFG2)<<1) |\
-	(GET_REG_BIT(x,SDRAM_CFG1)))
-
-/* System Controller */
-/* 0  1 3 4 5 16 20 28 29 30 */
-#define SYSCNTR_BDIS	0
-#define SYSCNTR_PCIM	1
-#define SYSCNTR_CFG0	3
-#define SYSCNTR_CFG1	4
-#define SYSCNTR_CFG2	5
-#define SYSCNTR_CFG3	16
-#define SYSCNTR_BOOTEN	20
-#define SYSCNTR_CPU_VPP	28
-#define SYSCNTR_FL_VPP	29
-#define SYSCNTR_FL_WP	30
-
-#define GET_SYSCNTR_CFG(x)	(	\
-	(GET_REG_BIT(x,SYSCNTR_CFG3)<<3)| \
-	(GET_REG_BIT(x,SYSCNTR_CFG2)<<2)| \
-	(GET_REG_BIT(x,SYSCNTR_CFG1)<<1)| \
-	(GET_REG_BIT(x,SYSCNTR_CFG0)))
-
-
-/***************************************************************
- * MISC Defines
- ***************************************************************/
-
-#define PCI_VENDOR_ID_MPL	0x18E6
-#define PCI_DEVICE_ID_PATI	0x00DA
-
-#if defined(CONFIG_MIP405)
-#define PATI_FIRMWARE_START_OFFSET	0x00300000
-#define PATI_ISO_STRING  "MEV-10084-001"
-#endif
-
-#define PATI_ENDIAN_MODE	0x3E
-
-/*******************************************
- * PATI Mapping:
- * -------------
- * PCI Map:
- * -------
- * All addreses are mapped into the memory area
- * (IO Area on some areas may also be possible)
- * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
- * - pci_space0_addr:  configurable
- * - pci_space1_addr	  configurable
- *
- * Local Map:
- * ----------
- * Local addresses (Remap)
- * - SDRAM      0x06000000 Size 16MByte mask 0xff000000
- * - EPLD CFG   0x07000000 Size 512Bytes
- * - FLASH      0x03000000 Size up to 8MByte
- * - CPU        0x01000000 Size 4MByte (only accessable if special configured)
- *
- * Implemention:
- * -------------
- * To prevent using large resources reservation on the host following
- * PCI mapping is choosed:
- * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
- * - pci_space0_addr:  configured to the EPLD Config Area size 256Bytes
- * - pci_space1_addr:  configured to the SDRAM Area size 1MBytes, this
- *                     space is used to switch between SDRAM, Flash and CPU
- *
- */
-
-/* Attribute definitions */
-#define PATI_BUS_SIZE_8		0
-#define PATI_BUS_SIZE_16	1
-#define PATI_BUS_SIZE_32	3
-
-#define PATI_SPACE0_MASK	(0xFEFFFE00)  /* Mask Attributes */
-#define PATI_SPACE1_MASK	(0x00000000)  /* Mask Attributes */
-
-#define PATI_EXTRA_LONG_EEPROM	1
-
-#define SPACE0_TA_ENABLE (1<<6)
-#define SPACE1_TA_ENABLE (1<<6)
-
-/* Config Area */
-#define PATI_LOC_CFG_ADDR		0x07000000		/* Local Address */
-#define PATI_LOC_CFG_MASK		0xFFFFFF00		/* 256 Bytes */
-/* Attributes */
-#define PATI_LOC_CFG_BUS_SIZE		PATI_BUS_SIZE_32	/* 32 Bit */
-#define PATI_LOC_CFG_BURST		0			/* No Burst */
-#define PATI_LOC_CFG_NO_PREFETCH	1			/* No Prefetch */
-#define PATI_LOC_CFG_TA_ENABLE		1			/* Enable TA */
-
-#define PATI_LOC_CFG_SPACE0_ATTR  ( \
-		PATI_LOC_CFG_BUS_SIZE | \
-		(PATI_LOC_CFG_TA_ENABLE << 6) | \
-		(PATI_LOC_CFG_NO_PREFETCH << 8) | \
-		(PATI_LOC_CFG_BURST << 24) | \
-		(PATI_EXTRA_LONG_EEPROM << 25))
-
-/* should never be used */
-#define PATI_LOC_CFG_SPACE1_ATTR  ( \
-		PATI_LOC_CFG_BUS_SIZE | \
-		(PATI_LOC_CFG_TA_ENABLE << 6) | \
-		(PATI_LOC_CFG_NO_PREFETCH << 9) | \
-		(PATI_LOC_CFG_BURST << 8))
-
-
-/* SDRAM Area */
-#define PATI_LOC_SDRAM_ADDR		0x06000000		/* Local Address */
-#define PATI_LOC_SDRAM_MASK		0xFFF00000		/* 1MByte */
-/* Attributes */
-#define PATI_LOC_SDRAM_BUS_SIZE		PATI_BUS_SIZE_32	/* 32 Bit */
-#define PATI_LOC_SDRAM_BURST		0			/* No Burst */
-#define PATI_LOC_SDRAM_NO_PREFETCH	0			/* Prefetch */
-#define PATI_LOC_SDRAM_TA_ENABLE	1			/* Enable TA */
-
-/* should never be used */
-#define PATI_LOC_SDRAM_SPACE0_ATTR  ( \
-		PATI_LOC_SDRAM_BUS_SIZE | \
-		(PATI_LOC_SDRAM_TA_ENABLE << 6) | \
-		(PATI_LOC_SDRAM_NO_PREFETCH << 8) | \
-		(PATI_LOC_SDRAM_BURST << 24) | \
-		(PATI_EXTRA_LONG_EEPROM << 25))
-
-#define PATI_LOC_SDRAM_SPACE1_ATTR  ( \
-		PATI_LOC_SDRAM_BUS_SIZE | \
-		(PATI_LOC_SDRAM_TA_ENABLE << 6) | \
-		(PATI_LOC_SDRAM_NO_PREFETCH << 9) | \
-		(PATI_LOC_SDRAM_BURST << 8))
-
-
-/* Flash Area */
-#define PATI_LOC_FLASH_ADDR		0x03000000		/* Local Address */
-#define PATI_LOC_FLASH_MASK		0xFFF00000		/* 1MByte */
-/* Attributes */
-#define PATI_LOC_FLASH_BUS_SIZE		PATI_BUS_SIZE_16	/* 16 Bit */
-#define PATI_LOC_FLASH_BURST		0			/* No Burst */
-#define PATI_LOC_FLASH_NO_PREFETCH	1			/* No Prefetch */
-#define PATI_LOC_FLASH_TA_ENABLE	1			/* Enable TA */
-
-/* should never be used */
-#define PATI_LOC_FLASH_SPACE0_ATTR  ( \
-		PATI_LOC_FLASH_BUS_SIZE | \
-		(PATI_LOC_FLASH_TA_ENABLE << 6) | \
-		(PATI_LOC_FLASH_NO_PREFETCH << 8) | \
-		(PATI_LOC_FLASH_BURST << 24) | \
-		(PATI_EXTRA_LONG_EEPROM << 25))
-
-#define PATI_LOC_FLASH_SPACE1_ATTR  ( \
-		PATI_LOC_FLASH_BUS_SIZE | \
-		(PATI_LOC_FLASH_TA_ENABLE << 6) | \
-		(PATI_LOC_FLASH_NO_PREFETCH << 9) | \
-		(PATI_LOC_FLASH_BURST << 8))
-
-
-/* CPU Area */
-#define PATI_LOC_CPU_ADDR		0x01000000		/* Local Address */
-#define PATI_LOC_CPU_MASK		0xFFF00000		/* 1Mbyte */
-/* Attributes */
-#define PATI_LOC_CPU_BUS_SIZE		PATI_BUS_SIZE_32	/* 32 Bit */
-#define PATI_LOC_CPU_BURST		0			/* No Burst */
-#define PATI_LOC_CPU_NO_PREFETCH	1			/* No Prefetch */
-#define PATI_LOC_CPU_TA_ENABLE		1			/* Enable TA */
-
-/* should never be used */
-#define PATI_LOC_CPU_SPACE0_ATTR  ( \
-		PATI_LOC_CPU_BUS_SIZE | \
-		(PATI_LOC_CPU_TA_ENABLE << 6) | \
-		(PATI_LOC_CPU_NO_PREFETCH << 8) | \
-		(PATI_LOC_CPU_BURST << 24) | \
-		(PATI_EXTRA_CPU_EEPROM << 25))
-
-#define PATI_LOC_CPU_SPACE1_ATTR  ( \
-		PATI_LOC_CPU_BUS_SIZE | \
-		(PATI_LOC_CPU_TA_ENABLE << 6) | \
-		(PATI_LOC_CPU_NO_PREFETCH << 9) | \
-		(PATI_LOC_CPU_BURST << 8))
-
-/***************************************************
- * Hardware Config word definition
- ***************************************************/
-#define BOOT_EXT_FLASH		0x00000000
-#define BOOT_INT_FLASH		0x00000004
-#define BOOT_FROM_PCI		0x00000006
-#define BOOT_FROM_SDRAM		0x00000005
-
-#define ENABLE_INT_ARB		0x00000008
-
-#define INITIAL_IRQ_PREF	0x00000010
-
-#define INITIAL_MEM_0M		0x00000000
-#define INITIAL_MEM_4M		0x00000080
-#define INITIAL_MEM_8M		0x00000040
-#define INITIAL_MEM_12M		0x000000C0
-#define INITIAL_MEM_16M		0x00000020
-#define INITIAL_MEM_20M		0x000000A0
-#define INITIAL_MEM_24M		0x00000060
-#define INITIAL_MEM_28M		0x000000E0
-/* CONF */
-#define INTERNAL_HWCONF		0x00000100
-/* PRPM */
-#define LOCAL_CPU_SLAVE		0x00000200
-/* BDIS */
-#define DISABLE_MEM_CNTR	0x00000400
-/* PCIM */
-#define PCI_MASTER_ONLY		0x00000800
-
-
-#define PATI_HW_START		((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF))
-#define PATI_HW_PCI_ONLY	((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
-#define PATI_HW_CPU_ACC		((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
-#define PATI_HW_CPU_SLAVE	((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE))
-
-/***************************************************
- * Direct Master Config
- ***************************************************/
-#define PATI_DMASTER_PCI_ADDR		0x01000000
-#define PATI_BUS_MASTER 1
-
-
-#define PATI_DMASTER_MASK		0xFFF00000  /* 1MByte */
-#define PATI_DMASTER_ADDR		0x01000000  /* Local Address */
-
-#define PATI_DMASTER_MEMORY_EN		0x00000001 /* 0x00000001 */
-#define PATI_DMASTER_READ_AHEAD		0x00000004 /* 0x00000004 */
-#define PATI_DMASTER_READ_NOT_AHEAD	0x00000000 /* 0x00000004 */
-#define PATI_DMASTER_PRE_SIZE_CNTRL_0	0x00000000
-#define PATI_DMASTER_PRE_SIZE_CNTRL_4	0x00000008
-#define PATI_DMASTER_PRE_SIZE_CNTRL_8	0x00001000
-#define PATI_DMASTER_PRE_SIZE_CNTRL_16	0x00001008
-#define PATI_DMASTER_REL_PCI		0x00000000
-#define PATI_DMASTER_NOT_REL_PCI	0x00000010
-#define PATI_DMASTER_WR_INVAL		0x00000200
-#define PATI_DMASTER_NOT_WR_INVAL	0x00000000
-#define PATI_DMASTER_PRE_LIMIT		0x00000800
-#define PATI_DMASTER_PRE_CONT		0x00000000
-#define PATI_DMASTER_DELAY_WR_0		0x00000000
-#define PATI_DMASTER_DELAY_WR_4		0x00004000
-#define PATI_DMASTER_DELAY_WR_8		0x00008000
-#define PATI_DMASTER_DELAY_WR_16	0x0000C000
-
-#define PATI_DMASTER_PCI_ADDR_MASK	0xFFFF0000
-
-#define PATI_DMASTER_ATTR	\
-	PATI_DMASTER_MEMORY_EN | \
-	PATI_DMASTER_READ_AHEAD | \
-	PATI_DMASTER_PRE_SIZE_CNTRL_4 | \
-	PATI_DMASTER_REL_PCI | \
-	PATI_DMASTER_NOT_WR_INVAL | \
-	PATI_DMASTER_PRE_LIMIT | \
-	PATI_DMASTER_DELAY_WR_0
-
-
-#endif /* #ifndef __PATI_H_ */
diff --git a/board/mpl/pati/pci_eeprom.h b/board/mpl/pati/pci_eeprom.h
deleted file mode 100644
index 459c143..0000000
--- a/board/mpl/pati/pci_eeprom.h
+++ /dev/null
@@ -1,90 +0,0 @@
-#ifndef __PCI_EEPROM_H_
-#define __PCI_EEPROM_H_	1
-
-#include "pati.h"
-/******************************************************************************
- * Eeprom Support
- ******************************************************************************/
-/**********************************************
-*               Definitions
-**********************************************/
-#define EE46_CMD_LEN    9       /* Bits in instructions */
-#define EE56_CMD_LEN    11      /* Bits in instructions */
-#define EE66_CMD_LEN    11      /* Bits in instructions */
-#define EE_READ         0x0180  /* 01 1000 0000 read instruction */
-#define EE_WRITE        0x0140  /* 01 0100 0000 write instruction */
-#define EE_WREN         0x0130  /* 01 0011 0000 write enable instruction */
-#define EE_WRALL        0x0110  /* 01 0001 0000 write all registers */
-#define EE_PRREAD       0x0180  /* 01 1000 0000 read address stored in Protect Register */
-#define EE_PRWRITE      0x0140  /* 01 0100 0000 write the address into PR */
-#define EE_WDS          0x0100  /* 01 0000 0000 write disable instruction */
-#define EE_PREN         0x0130  /* 01 0011 0000 protect enable instruction */
-#define EE_PRCLEAR      0x01FF  /* 01 1111 1111 clear protect register instr */
-#define EE_PRDS         0x0100  /* 01 0000 0000 ONE TIME ONLY, permenant */
-
-/***************************************************
- * EEPROM
- ***************************************************/
-#define LOW_WORD(x)	(((x) & 0xFFFF))
-#define HIGH_WORD(x)	(((x) >> 16) & 0xFFFF)
-
-typedef struct pci_eeprom_t {
-	unsigned short offset;
-	unsigned short value;
-} pci_eeprom;
-
-static pci_eeprom pati_eeprom[] = {
-	{ 0x00,PCI_DEVICE_ID_PATI },	/* PCI Device ID PCIIDR[31:16] */
-	{ 0x02,PCI_VENDOR_ID_MPL },	/* PCI Vendor ID PCIIDR[15:0] */
-	{ 0x04,PCI_CLASS_PROCESSOR_POWERPC },	/* PCI Class Code PCICCR[23:8] */
-	{ 0x06,0x00BA },	/* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */
-	{ 0x08,0x0007 },	/* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */
-	{ 0x0A,0x0100 },	/* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */
-	{ 0x0C,0x0000 },	/* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */
-	{ 0x0E,0x0000 },	/* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */
-	{ 0x10,0x0000 },	/* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */
-	{ 0x12,0x0000 },	/* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */
-	{ 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) },	/* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */
-	{ 0x16,LOW_WORD(PATI_LOC_CFG_MASK) },	/* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */
-	{ 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) },	/* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */
-	{ 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 },	/* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */
-	{ 0x1C,0x0000 },	/* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */
-	{ 0x1E,0x0000 },	/* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */
-	{ 0x20,0x0030 },	/* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */
-	{ 0x22,0x0510 },	/* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */
-	{ 0x24,0x0000 },	/* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */
-	{ 0x26,0x0000 },	/* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1]  */
-	{ 0x28,0x0000 },	/* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */
-	{ 0x2A,0x0000 },	/* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */
-	{ 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) },	/* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */
-	{ 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) },	/* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */
-	{ 0x30,HIGH_WORD(PATI_DMASTER_MASK) },	/* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */
-	{ 0x32,LOW_WORD(PATI_DMASTER_MASK) },	/* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */
-	{ 0x34,HIGH_WORD(PATI_DMASTER_ADDR) },	/* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */
-	{ 0x36,LOW_WORD(PATI_DMASTER_ADDR) },	/* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */
-	{ 0x38,0x0000 },	/* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */
-	{ 0x3A,0x0000 },	/* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */
-	{ 0x3C,0x0000 },	/* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */
-	{ 0x3E,0x0000 },	/* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */
-	{ 0x40,0x0000 },	/* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/
-	{ 0x42,0x0000 },	/* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */
-	{ 0x44,0x0000 },	/* PCI Subsystem ID PCISID[15:0] */
-	{ 0x46,0x0000 },	/* PCI Subsystem Vendor ID PCISVID[15:0] */
-	{ 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) },	/* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */
-	{ 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) },	/* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */
-	{ 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) },	/* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */
-	{ 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 },	/* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */
-	{ 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) },	/* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */
-	{ 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) },	/* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */
-	{ 0x54,0x0000 },	/* Hot Swap Control/Status (Reserved) Reserved */
-	{ 0x56,0x0000 },	/* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */
-	{ 0x58,0x0000 },	/* Reserved Reserved */
-	{ 0x5A,0x0000 },	/* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */
-	{ 0x5C,0x0000 },	/* Power Management Capabilities PMC[15:9, 2:0] */
-	{ 0x5E,0x0000 },	/* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/
-	{ 0x60,0x0000 },	/* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */
-	{ 0x62,0x0000 },	/* Power Management Control/Status PMCSR[14:8] */
-	{ 0xFFFF,0xFFFF}	/* terminaror */
-};
-#define PATI_EEPROM_LAST_OFFSET	0x64
-#endif /* #ifndef __PCI_EEPROM_H_ */
diff --git a/board/mpl/pati/plx9056.h b/board/mpl/pati/plx9056.h
deleted file mode 100644
index 754e720..0000000
--- a/board/mpl/pati/plx9056.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * (C) Copyright 2003
- * Denis Peter, d.peter@mpl.ch
- * SPDX-License-Identifier:	GPL-2.0+
- */
-/* PLX9096 register definitions
-*/
-#ifndef __PLX9056_H_
-#define __PLX9056_H_	1
-
-#include <pci.h>
-
-#ifdef PLX9056_LOC
-#define LOCAL_OFFSET					0x080
-/* PCI Config regs */
-#else
-#define LOCAL_OFFSET					0x000
-#endif
-
-#define PCI9056_VENDOR_ID            PCI_VENDOR_ID
-/*#define PCI9656_DEVICE_ID            PCI_DEVICE_ID */
-#define PCI9056_COMMAND              PCI_COMMAND
-/*#define PCI9656_STATUS               PCI_STATUS */
-#define PCI9056_REVISION             PCI_REVISION_ID
-
-#define PCI9056_CACHE_SIZE           PCI_CACHE_LINE_SIZE
-#define PCI9056_RTR_BASE             PCI_BASE_ADDRESS_0
-#define PCI9056_RTR_IO_BASE          PCI_BASE_ADDRESS_1
-#define PCI9056_LOCAL_BASE0          PCI_BASE_ADDRESS_2
-#define PCI9056_LOCAL_BASE1          PCI_BASE_ADDRESS_3
-#define PCI9056_UNUSED_BASE1         PCI_BASE_ADDRESS_4
-#define PCI9056_UNUSED_BASE2         PCI_BASE_ADDRESS_5
-#define PCI9056_CIS_PTR              PCI_CARDBUS_CIS
-#define PCI9056_SUB_ID               PCI_SUBSYSTEM_VENDOR_ID
-#define PCI9056_EXP_ROM_BASE         PCI_ROM_ADDRESS
-#define PCI9056_CAP_PTR              PCI_CAPABILITY_LIST
-#define PCI9056_INT_LINE             PCI_INTERRUPT_LINE
-
-#if defined(PLX9056_LOC)
-    #define PCI9056_PM_CAP_ID            0x180
-    #define PCI9056_PM_CSR               0x184
-    #define PCI9056_HS_CAP_ID            0x188
-    #define PCI9056_VPD_CAP_ID           0x18C
-    #define PCI9056_VPD_DATA             0x190
-#endif
-
-
-#define PCI_DEVICE_ID_PLX9056		0x9056
-
-/* Local Configuration Registers Accessible via the PCI Base address + Variable */
-#define PCI9056_SPACE0_RANGE         (0x000 + LOCAL_OFFSET)
-#define PCI9056_SPACE0_REMAP         (0x004 + LOCAL_OFFSET)
-#define PCI9056_LOCAL_DMA_ARBIT      (0x008 + LOCAL_OFFSET)
-#define PCI9056_ENDIAN_DESC          (0x00c + LOCAL_OFFSET)
-#define PCI9056_EXP_ROM_RANGE        (0x010 + LOCAL_OFFSET)
-#define PCI9056_EXP_ROM_REMAP        (0x014 + LOCAL_OFFSET)
-#define PCI9056_SPACE0_ROM_DESC      (0x018 + LOCAL_OFFSET)
-#define PCI9056_DM_RANGE             (0x01c + LOCAL_OFFSET)
-#define PCI9056_DM_MEM_BASE          (0x020 + LOCAL_OFFSET)
-#define PCI9056_DM_IO_BASE           (0x024 + LOCAL_OFFSET)
-#define PCI9056_DM_PCI_MEM_REMAP     (0x028 + LOCAL_OFFSET)
-#define PCI9056_DM_PCI_IO_CONFIG     (0x02c + LOCAL_OFFSET)
-#define PCI9056_SPACE1_RANGE         (0x0f0 + LOCAL_OFFSET)
-#define PCI9056_SPACE1_REMAP         (0x0f4 + LOCAL_OFFSET)
-#define PCI9056_SPACE1_DESC          (0x0f8 + LOCAL_OFFSET)
-#define PCI9056_DM_DAC               (0x0fc + LOCAL_OFFSET)
-
-#ifdef PLX9056_LOC
-#define PCI9056_ARBITER_CTRL         0x1A0
-#define PCI9056_ABORT_ADDRESS        0x1A4
-#endif
-
-/* Runtime registers  PCI Address + LOCAL_OFFSET */
-#ifdef PLX9056_LOC
-#define PCI9056_MAILBOX0				0x0C0
-#define PCI9056_MAILBOX1				0x0C4
-#else
-#define PCI9056_MAILBOX0				0x078
-#define PCI9056_MAILBOX1				0x07c
-#endif
-
-#define PCI9056_MAILBOX2				(0x048 + LOCAL_OFFSET)
-#define PCI9056_MAILBOX3				(0x04c + LOCAL_OFFSET)
-#define PCI9056_MAILBOX4				(0x050 + LOCAL_OFFSET)
-#define PCI9056_MAILBOX5				(0x054 + LOCAL_OFFSET)
-#define PCI9056_MAILBOX6				(0x058 + LOCAL_OFFSET)
-#define PCI9056_MAILBOX7				(0x05c + LOCAL_OFFSET)
-#define PCI9056_PCI_TO_LOC_DBELL		(0x060 + LOCAL_OFFSET)
-#define PCI9056_LOC_TO_PCI_DBELL		(0x064 + LOCAL_OFFSET)
-#define PCI9056_INT_CTRL_STAT			(0x068 + LOCAL_OFFSET)
-#define PCI9056_EEPROM_CTRL_STAT		(0x06c + LOCAL_OFFSET)
-#define PCI9056_PERM_VENDOR_ID		(0x070 + LOCAL_OFFSET)
-#define PCI9056_REVISION_ID			(0x074 + LOCAL_OFFSET)
-
-#endif /* #ifndef __PLX9056_H_ */
diff --git a/board/mpl/pip405/Kconfig b/board/mpl/pip405/Kconfig
deleted file mode 100644
index f485367..0000000
--- a/board/mpl/pip405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_PIP405
-
-config SYS_BOARD
-	default "pip405"
-
-config SYS_VENDOR
-	default "mpl"
-
-config SYS_CONFIG_NAME
-	default "PIP405"
-
-endif
diff --git a/board/mpl/pip405/MAINTAINERS b/board/mpl/pip405/MAINTAINERS
deleted file mode 100644
index 9b3b974..0000000
--- a/board/mpl/pip405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PIP405 BOARD
-M:	Denis Peter <d.peter@mpl.ch>
-S:	Maintained
-F:	board/mpl/pip405/
-F:	include/configs/PIP405.h
-F:	configs/PIP405_defconfig
diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile
deleted file mode 100644
index 0a3d059..0000000
--- a/board/mpl/pip405/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= pip405.o cmd_pip405.o \
-		../common/pci.o \
-		../common/isa.o \
-		../common/kbd.o \
-		../common/usb_uhci.o \
-		../common/common_util.o
-obj-y	+= init.o
diff --git a/board/mpl/pip405/README b/board/mpl/pip405/README
deleted file mode 100644
index f039817..0000000
--- a/board/mpl/pip405/README
+++ /dev/null
@@ -1,371 +0,0 @@
-U-Boot Changes due to PIP405 Port:
-===================================
-
-Changed files:
-==============
-- MAKEALL			added PIP405
-- makefile			added PIP405
-- common/Makefile		added Floppy disk and SCSI support
-- common/board.c		added PIP405, SCSI support, get_PCI_freq()
-- common/bootm.c		added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
-- common/cmd_i2c.c		added "defined(CONFIG_PIP405)"
-- common/cmd_ide.c		changed div. functions to work with block device
-				description
-				added ATAPI support
-- common/command.c		added SCSI and Floppy support
-- common/console.c		replaced // with /* comments
-				added console settings from environment
-- common/devices.c		added ISA keyboard init
-- common/main.c			corrected the read of bootdelay
-- arch/powerpc/cpu/ppc4xx/405gp_pci.c	excluded file from PIP405
-- arch/powerpc/cpu/ppc4xx/i2c.c		added 16bit read write I2C support
-				added page write
-- arch/powerpc/cpu/ppc4xx/speed.c		added get_PCI_freq
-- arch/powerpc/cpu/ppc4xx/start.S		added CONFIG_IDENT_STRING
-- disk/Makefile			added part_iso for CD support
-- disk/part.c			changed to work with block device description
-				added ISO CD support
-				added dev_print (was ide_print in cmd_ide.c)
-- disk/part_dos.c		changed to work with block device description
-- disk/part_mac.c		changed to work with block device description
-- include/ata.h			added ATAPI commands
-- include/cmd_bsp.h		added PIP405 commands definitions
-- include/cmd_condefs.h		added Floppy and SCSI support
-- include/cmd_disk.h		changed to work with block device description
-- include/config_LANTEC.h	excluded CONFIG_CMD_FDC and CONFIG_SCSI
-- include/config_hymod.h	excluded CONFIG_CMD_FDC and CONFIG_SCSI
-- include/flash.h		added INTEL_ID_28F320C3T  0x88C488C4
-- include/i2c.h			added "defined(CONFIG_PIP405)"
-- include/image.h		added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
-- include/u-boot.h		moved partitions functions definitions to part.h
-				added "defined(CONFIG_PIP405)"
-				added get_PCI_freq() definition
-- rtc/Makefile			added MC146818 RTC support
-- tools/mkimage.c		added IH_OS_U_BOOT, IH_TYPE_FIRMWARE
-
-Added files:
-============
-- board/pip405			directory for PIP405
-- board/pip405/cmd_pip405.c	board specific commands
-- board/pip405/config.mk	config make
-- board/pip405/flash.c		flash support
-- board/pip405/init.s		start-up
-- board/pip405/kbd.c		keyboard support
-- board/pip405/kbd.h		keyboard support
-- board/pip405/Makefile		Makefile
-- board/pip405/pci_piix4.h	southbridge definitions
-- board/pip405/pci_pip405.c	PCI support for PIP405
-- board/pip405/pci_pip405.h	PCI support for PIP405
-- board/pip405/pip405.c		PIP405 board init
-- board/pip405/pip405.h		PIP405 board init
-- board/pip405/pip405_isa.c	ISA support
-- board/pip405/pip405_isa.h	ISA support
-- board/pip405/u-boot.lds	Linker description
-- board/pip405/u-boot.lds.debugLinker description debug
-- board/pip405/sym53c8xx.c	SYM53C810A support
-- board/pip405/sym53c8xx_defs.h SYM53C810A definitions
-- board/pip405/vga_table.h	definitions of tables for VGA
-- board/pip405/video.c		CT69000 support
-- board/pip405/video.h		CT69000 support
-- common/cmd_fdc.c		Floppy disk support
-- common/cmd_scsi.c		SCSI support
-- disk/part_iso.c		ISO CD ROM support
-- disk/part_iso.h		ISO CD ROM support
-- include/cmd_fdc.h		command forFloppy disk support
-- include/cmd_scsi.h		command for SCSI support
-- include/part.h		partitions functions definitions
-				(was part of u-boot.h)
-- include/scsi.h		SCSI support
-- rtc/mc146818.c		MC146818 RTC support
-
-
-New Config Switches:
-====================
-For detailed description, refer to the corresponding paragraph in the
-section "Changes".
-
-New Commands:
--------------
-CONFIG_SCSI	SCSI Support
-CONFIG_CMF_FDC	Floppy disk support
-
-IDE additions:
---------------
-CONFIG_IDE_RESET_ROUTINE	defines that instead of a reset Pin,
-				the routine ide_set_reset(int idereset) is used.
-ATAPI support (experimental)
-----------------------------
-CONFIG_ATAPI	enables ATAPI Support
-
-SCSI support (experimental) only SYM53C8xx supported
-----------------------------------------------------
-CONFIG_SCSI_SYM53C8XX		type of SCSI controller
-CONFIG_SYS_SCSI_MAX_LUN	8	number of supported LUNs
-CONFIG_SYS_SCSI_MAX_SCSI_ID	7	maximum SCSI ID (0..6)
-CONFIG_SYS_SCSI_MAX_DEVICE	CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN
-				maximum of Target devices (multiple LUN support
-				for boot)
-
-ISO (CD-Boot) partition support (Experimental)
-----------------------------------------------
-CONFIG_ISO_PARTITION		CD-boot support
-
-RTC
-----
-CONFIG_RTC_MC146818		MC146818 RTC support
-
-Video:
-------
-CONFIG_VIDEO_CT69000		Enable Chips & Technologies 69000 Video chip
-				CONFIG_VIDEO must be defined also
-
-External peripheral base address:
----------------------------------
-CONFIG_SYS_ISA_IO_BASE_ADDRESS		address of all ISA-bus related parts
-				_must_ be defined for ISA-bus parts
-
-Identify:
----------
-CONFIG_IDENT_STRING		added to the U_BOOT_VERSION String
-
-Environment / Console:
-----------------------
-
-CONFIG_SYS_CONSOLE_IS_IN_ENV		if defined, stdin, stdout and stderr used from
-				the values stored in the evironment.
-
-CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE	if defined, console_overwrite() decides if the
-				values stored in the environment or the standard
-				serial in/out put should be assigned to the console.
-
-CONFIG_SYS_CONSOLE_ENV_OVERWRITE	if defined, the start-up console switching
-				are stored in the environment.
-
-PIP405 specific:
-----------------
-CONFIG_PORT_ADDR		address used to read boot configuration
-MULTI_PURPOSE_SOCKET_ADDR	address of the multi purpose socked
-SDRAM_EEPROM_WRITE_ADDRESS	addresses of the serial presence detect
-SDRAM_EEPROM_READ_ADDRESS	EEPROM on the SDRAM module.
-
-
-Changes:
-========
-
-Added Devices:
-==============
-
-Floppy support:
----------------
-Support of a standard floppy disk controller at address CONFIG_SYS_ISA_IO_BASE_ADDRESS
-+ 0x3F0. Enabled with define CONFIG_CMD_FDC. Reads a unformated floppy disk
-with a image header (see: mkimage). No interrupts and no DMA are used for this.
-Added files:
-- common/cmd_fdc.c
-- include/cmd_fdc.h
-
-SCSI support:
--------------
-Support for Symbios SYM53C810A chip. Implemented as follows:
-- without disconnect
-- only asynchrounous
-- multiple LUN support (caution, needs a lot of RAM. define CONFIG_SYS_SCSI_MAX_LUN 1 to
-  save RAM)
-- multiple SCSI ID support
-- no write support
-- analyses the MAC, DOS and ISO pratition similar to the IDE support
-- allows booting from SCSI devices similar to the IDE support.
-The device numbers are not assigned like they are within the IDE support. The first
-device found will get the number 0, the next 1 etc. If all SCSI IDs (0..6) and all
-LUNs (8) are enabled, 56 boot devices are possible. This uses a lot of RAM since the
-device descriptors are not yet dynamically allocated. 56 boot devices are overkill
-anyway. Please refer to the section "Todo" chapter "block device support enhancement".
-The SYM53C810A uses 1 Interrupt and must be able of mastering the PCI bus.
-Added files:
-- common/cmd_scsi.c
-- common/board.c
-- include/cmd_scsi.h
-- include/scsi.h
-- board/pip405/sym53c8xx.c
-- board/pip405/sym53c8xx_defs.h
-
-ATAPI support (IDE changes):
-----------------------------
-Added ATAPI support (with CONFIG_ATAPI) in the file cmd_ide.c.
-To support a hardreset, when the IDE reset pin is not connected to the
-CONFIG_SYS_PC_IDE_RESET pin, the switch CONFIG_IDE_RESET_ROUTINE has been added. When
-this switch is enabled the routine void ide_set_reset(int idereset) must be
-within the board specific files.
-Only read from ATAPI devices are supported.
-Found out that the function trim_trail cuts off the last character if the whole
-string is filled. Added function cpy_ident instead, which trims also leading
-spaces and copies the string in the buffer.
-Changed files:
-- common/cmd_ide.c
-- include/ata.h
-
-ISO partition support:
-----------------------
-Added CD boot support for El-Torito bootable ISO CDs. The bootfile image must contain
-the U-Boot image header. Since CDs do not have "partitions", the boot partition is 0.
-The bootcatalog feature has not been tested so far. CD Boot is supported for ATAPI
-("diskboot") and SCSI ("scsiboot") devices.
-Added files:
-- disk/iso_part.c
-- disk/iso_part.h
-
-Block device changes:
----------------------
-To allow the use of dos_part.c, mac_part.c and iso_part.c, the parameter
-blk_desc will be used when accessing the functions in these files. The block
-device descriptor (blk_desc) contains a pointer to the read routine of the
-device, which will be used to read blocks from the device.
-Renamed function ide_print to dev_print and moved it to the file disk/part.c to use
-it for IDE ATAPI and SCSI devices.
-Please refer to the section "Todo" chapter "block device support enhancement".
-Added files:
-- include/part.h
-changed files:
-- disk/dos_part.c
-- disk/dos_part.h
-- disk/mac_part.c
-- disk/mac_part.h
-- disk/part.c
-- common/cmd_ide.c
-- include/u-boot.h
-
-
-MC146818 RTC support:
----------------------
-Added support for MC146818 RTC with defining CONFIG_RTC_MC146818. The ISA bus IO
-base address must be defined with CONFIG_SYS_ISA_IO_BASE_ADDRESS.
-Added files:
-- rtc/mc146818.c
-
-Standard ISA bus Keyboard support:
-----------------------------------
-Added support for the standard PC kyeboard controller. For the PIP405 the superIO
-controller must be set up previously. The keyboard uses the standard ISA IRQ, so
-the ISA PIC must also be set up.
-Added files:
-- board/pip405/kbd.c
-- board/pip405/kbd.h
-- board/pip405/pip405_isa.c
-- board/pip405/pip405_isa.h
-
-Chips and Technologie 69000 VGA controller support:
----------------------------------------------------
-Added support for the CT69000 VGA controller.
-Added files:
-- board/pip405/video.c
-- board/pip405/video.h
-- board/pip405/vga_table.h
-
-
-Changed Items:
-==============
-
-Identify:
----------
-Added the config variable CONFIG_IDENT_STRING which will be added to the
-"U_BOOT_VERSION __TIME__ DATE___ " String, to allows to identify intermidiate
-and custom versions.
-Changed files:
-- arch/powerpc/cpu/ppc4xx/start.s
-
-Firmware Image:
----------------
-Added IH_OS_U_BOOT and IH_TYPE_FIRMWARE to the image definitions to allows the
-U-Boot update with prior CRC check.
-Changed files:
-- include/image.h
-- tools/mkimage.c
-- common/cmd_bootm.c
-
-Correct PCI Frequency for PPC405:
----------------------------------
-Added function (in arch/powerpc/cpu/ppc4xx/speed.c) to get the PCI frequency for PPC405 CPU.
-The PCI Frequency will now be set correct in the board description in common/board.c.
-(was set to the busfreq before).
-Changed files:
-- arch/powerpc/cpu/ppc4xx/speed.c
-- common/board.c
-
-I2C Stuff:
-----------
-Added defined(CONFIG_PIP405) at several points in common/cmd_i2c.c.
-Added 16bit read/write support for I2C (PPC405), and page write to
-I2C EEPROM if defined CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE.
-Changed files:
-- arch/powerpc/cpu/ppc4xx/i2c.c
-- common/cmd_i2c.c
-
-Environment / Console:
-----------------------
-Although in README.console described, the U-Boot has not assinged the values
-found in the environment to the console. Corrected this behavior, but only if
-CONFIG_SYS_CONSOLE_IS_IN_ENV is defined.
-If CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is defined, console_overwrite() decides if the
-values stored in the environment or the standard serial in/output should be
-assigned to the console. This is useful if the environment values are not correct.
-If CONFIG_SYS_CONSOLE_ENV_OVERWRITE is defined the devices assigned to the console at
-start-up time will be written to the environment. This means that if the
-environment values are overwritten by the overwrite_console() routine, they will be
-stored in the environment.
-Changed files:
-- common/console.c
-
-Correct bootdelay intepretation:
---------------------------------
-Changed bootdelay read from the environment from simple_strtoul (unsigned) to
-simple_strtol (signed), to be able to get a bootdelay of -1.
-Changed files:
-- common/main.c
-
-Todo:
-=====
-
-Block device support enhancement:
----------------------------------
-Consider to unify the block device handling. Instead of using diskboot for IDE,
-scsiboot for SCSI and fdcboot for floppy disks, it would make sense to use only
-one command ("devboot" ???) with a parameter of the desired device ("hda1", "sda1",
-"fd0" ???) to boot from. The other ide commands can be handled in the same way
-("dev hda read.." instead of "ide read.." or "dev sda read.." instead of
-"scsi read..."). Todo this, a common way of assign a block device to its name
-(first found ide device = hda, second found hdb etc., or hda is device 0 on bus 0,
-hdb is device 1 on bus 0 etc.) as well as the names (hdx for ide, sdx for scsi, fx for
-floppy ???) must be defined.
-Maybe there are better ideas to do this.
-
-Console assingment:
--------------------
-Consider to initialize and assign the console stdin, stdout and stderr as soon as
-possible to see the boot messages also on an other console than serial.
-
-
-Todo for PIP405:
-================
-
-LCD support for VGA:
---------------------
-Add LCD support for the CT69000
-
-Default environment:
---------------------
-Consider to write a default environment to the OTP part of the EEPROM and use it
-if the normal environment is not valid. Useful for serial# and ethaddr values.
-
-Watchdog:
----------
-Implement Watchdog.
-
-Files clean-up:
----------------
-Following files needs to be cleaned up:
-- cmd_pip405.c
-- flash.c
-- pci_pip405.c
-- pip405.c
-- pip405_isa.c
-Consider to split up the files in their functions.
diff --git a/board/mpl/pip405/cmd_pip405.c b/board/mpl/pip405/cmd_pip405.c
deleted file mode 100644
index 43b182e..0000000
--- a/board/mpl/pip405/cmd_pip405.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * hacked for PIP405
- */
-
-#include <common.h>
-#include <command.h>
-#include "pip405.h"
-#include "../common/common_util.h"
-
-
-extern void print_pip405_info(void);
-extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
-
-/* ------------------------------------------------------------------------- */
-
-int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-
-	ulong led_on,led_nr;
-
-	if (strcmp(argv[1], "info") == 0)
-	{
-		print_pip405_info();
-		return 0;
-	}
-	if (strcmp(argv[1], "led") == 0)
-	{
-		led_nr = (ulong)simple_strtoul(argv[2], NULL, 10);
-		led_on = (ulong)simple_strtoul(argv[3], NULL, 10);
-		if(!led_nr)
-			user_led0(led_on);
-		else
-			user_led1(led_on);
-		return 0;
-	}
-
-	return (do_mplcommon(cmdtp, flag, argc, argv));
-}
-U_BOOT_CMD(
-	pip405,	6,	1,	do_pip405,
-	"PIP405 specific Cmds",
-	"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
-	"pip405 flash floppy [SrcAddr] - updates U-Boot with image from floppy\n"
-	"pip405 flash mps - updates U-Boot with image from MPS"
-);
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S
deleted file mode 100644
index 292393e..0000000
--- a/board/mpl/pip405/init.S
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
- */
-/*-----------------------------------------------------------------------------
- * Function:     ext_bus_cntlr_init
- * Description:  Initializes the External Bus Controller for the external
- *		peripherals. IMPORTANT: For pass1 this code must run from
- *		cache since you can not reliably change a peripheral banks
- *		timing register (pbxap) while running code from that bank.
- *		For ex., since we are running from ROM on bank 0, we can NOT
- *		execute the code that modifies bank 0 timings from ROM, so
- *		we run it from cache.
- *	Bank 0 - Flash or Multi Purpose Socket
- *	Bank 1 - Multi Purpose Socket or Flash
- *	Bank 2 - not used
- *	Bank 3 - not used
- *	Bank 4 - not used
- *	Bank 5 - not used
- *	Bank 6 - used to switch on the 12V for the Multipurpose socket
- *	Bank 7 - Config Register
- *-----------------------------------------------------------------------------*/
-
-#include <configs/PIP405.h>
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-#include <asm/ppc4xx.h>
-#include "pip405.h"
-
-  .globl ext_bus_cntlr_init
- ext_bus_cntlr_init:
-  mflr   r4                      /* save link register */
-  mfdcr  r3,CPC0_PSR                /* get strapping reg */
-  andi.  r0, r3, PSR_ROM_LOC     /* mask out irrelevant bits */
-  bnelr                          /* jump back if PCI boot */
-
-  bl      ..getAddr
-..getAddr:
-  mflr    r3                      /* get address of ..getAddr */
-  mtlr    r4                      /* restore link register */
-  addi    r4,0,14                 /* set ctr to 14; used to prefetch */
-  mtctr   r4                      /* 14 cache lines to fit this function */
-				   /* in cache (gives us 8x14=112 instrctns) */
-..ebcloop:
-  icbt    r0,r3                   /* prefetch cache line for addr in r3 */
-  addi    r3,r3,32								/* move to next cache line */
-  bdnz    ..ebcloop               /* continue for 14 cache lines */
-
-   /*-------------------------------------------------------------------
-    * Delay to ensure all accesses to ROM are complete before changing
-    * bank 0 timings.
-    *------------------------------------------------------------------- */
-	addis	r3,0,0x0
-  ori     r3,r3,0xA000
-  mtctr   r3
-..spinlp:
-  bdnz    ..spinlp                /* spin loop */
-
-	/*-----------------------------------------------------------------------
-	 * decide boot up mode
-	 *----------------------------------------------------------------------- */
-	addi		r4,0,PB0CR
-	mtdcr		EBC0_CFGADDR,r4
-	mfdcr		r4,EBC0_CFGDATA
-
-	andi.		r0, r4, 0x2000			/* mask out irrelevant bits */
-	beq		0f				/* jump if 8 bit bus width */
-
-	/* setup 16 bit things
-   *-----------------------------------------------------------------------
-   * Memory Bank 0 (16 Bit Flash) initialization
-   *---------------------------------------------------------------------- */
-
-	addi    r4,0,PB1AP
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,(FLASH_AP_B)@h
-	ori     r4,r4,(FLASH_AP_B)@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	addi    r4,0,PB0CR
-	mtdcr   EBC0_CFGADDR,r4
-	/* BS=0x010(4MB),BU=0x3(R/W), */
-	addis   r4,0,(FLASH_CR_B)@h
-	ori     r4,r4,(FLASH_CR_B)@l
-	mtdcr   EBC0_CFGDATA,r4
-	b				1f
-
-0:
-	/* 8Bit boot mode: */
-	/*-----------------------------------------------------------------------
-	* Memory Bank 0 Multi Purpose Socket initialization
-	*----------------------------------------------------------------------- */
-	/* 0x7F8FFE80 slowest boot */
-	addi    r4,0,PB1AP
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,(MPS_AP_B)@h
-	ori     r4,r4,(MPS_AP_B)@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	addi    r4,0,PB0CR
-	mtdcr   EBC0_CFGADDR,r4
-	/* BS=0x010(4MB),BU=0x3(R/W), */
-	addis   r4,0,(MPS_CR_B)@h
-	ori     r4,r4,(MPS_CR_B)@l
-	mtdcr   EBC0_CFGDATA,r4
-
-
-1:
-  /*-----------------------------------------------------------------------
-   * Memory Bank 2-3-4-5-6 (not used) initialization
-   *-----------------------------------------------------------------------*/
-  addi    r4,0,PB1CR
-  mtdcr   EBC0_CFGADDR,r4
-  addis   r4,0,0x0000
-  ori     r4,r4,0x0000
-  mtdcr   EBC0_CFGDATA,r4
-
-  addi    r4,0,PB2CR
-  mtdcr   EBC0_CFGADDR,r4
-  addis   r4,0,0x0000
-  ori     r4,r4,0x0000
-  mtdcr   EBC0_CFGDATA,r4
-
-  addi    r4,0,PB3CR
-  mtdcr   EBC0_CFGADDR,r4
-  addis   r4,0,0x0000
-  ori     r4,r4,0x0000
-  mtdcr   EBC0_CFGDATA,r4
-
-  addi    r4,0,PB4CR
-  mtdcr   EBC0_CFGADDR,r4
-  addis   r4,0,0x0000
-  ori     r4,r4,0x0000
-  mtdcr   EBC0_CFGDATA,r4
-
-  addi    r4,0,PB5CR
-  mtdcr   EBC0_CFGADDR,r4
-  addis   r4,0,0x0000
-  ori     r4,r4,0x0000
-  mtdcr   EBC0_CFGDATA,r4
-
-  addi    r4,0,PB6CR
-  mtdcr   EBC0_CFGADDR,r4
-  addis   r4,0,0x0000
-  ori     r4,r4,0x0000
-  mtdcr   EBC0_CFGDATA,r4
-
-  addi    r4,0,PB7CR
-  mtdcr   EBC0_CFGADDR,r4
-  addis   r4,0,0x0000
-  ori     r4,r4,0x0000
-  mtdcr   EBC0_CFGDATA,r4
-  nop				/* pass2 DCR errata #8 */
-  blr
-
-#if defined(CONFIG_BOOT_PCI)
-    .section .bootpg,"ax"
-    .globl _start_pci
-/*******************************************
- */
-
-_start_pci:
-  /* first handle errata #68 / PCI_18 */
-  iccci   r0, r0          /* invalidate I-cache */
-  lis     r31, 0
-  mticcr  r31             /* ICCR = 0 (all uncachable) */
-  isync
-
-  mfccr0  r28             /* set CCR0[24] = 1 */
-  ori     r28, r28, 0x0080
-  mtccr0  r28
-
-  /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
-  lis     r28, 0xEF40
-  addi    r28, r28, 0x0004
-  stw     r31, 0x0C(r28)  /* clear PMM0PCIHA */
-  lis     r29, 0xFFF8     /* open 512 kByte */
-  addi    r29, r29, 0x0001/* and enable this region */
-  stwbrx  r29, r0, r28    /* write PMM0MA */
-
-  lis     r28, 0xEEC0     /* address of PCIC0_CFGADDR */
-  addi    r29, r28, 4     /* add 4 to r29 -> PCIC0_CFGDATA */
-
-  lis     r31, 0x8000     /* set en bit bus 0 */
-  ori     r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
-  stwbrx  r31, r0, r28    /* write it */
-
-  lwbrx   r31, r0, r29    /* load XBCS register */
-  oris    r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
-  stwbrx  r31, r0, r29    /* write back XBCS register */
-
-  nop
-  nop
-  b	_start		/* normal start */
-#endif
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
deleted file mode 100644
index 1bd2fbf..0000000
--- a/board/mpl/pip405/pip405.c
+++ /dev/null
@@ -1,956 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * TODO: clean-up
- */
-
-#include <common.h>
-#include "pip405.h"
-#include <asm/processor.h>
-#include <i2c.h>
-#include <stdio_dev.h>
-#include "../common/isa.h"
-#include "../common/common_util.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#undef SDRAM_DEBUG
-
-/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
-#ifndef __ldiv_t_defined
-typedef struct {
-	long int quot;		/* Quotient */
-	long int rem;		/* Remainder    */
-} ldiv_t;
-extern ldiv_t ldiv (long int __numer, long int __denom);
-
-# define __ldiv_t_defined	1
-#endif
-
-
-typedef enum {
-	SDRAM_NO_ERR,
-	SDRAM_SPD_COMM_ERR,
-	SDRAM_SPD_CHKSUM_ERR,
-	SDRAM_UNSUPPORTED_ERR,
-	SDRAM_UNKNOWN_ERR
-} SDRAM_ERR;
-
-typedef struct {
-	const unsigned char mode;
-	const unsigned char row;
-	const unsigned char col;
-	const unsigned char bank;
-} SDRAM_SETUP;
-
-static const SDRAM_SETUP sdram_setup_table[] = {
-	{1, 11, 9, 2},
-	{1, 11, 10, 2},
-	{2, 12, 9, 4},
-	{2, 12, 10, 4},
-	{3, 13, 9, 4},
-	{3, 13, 10, 4},
-	{3, 13, 11, 4},
-	{4, 12, 8, 2},
-	{4, 12, 8, 4},
-	{5, 11, 8, 2},
-	{5, 11, 8, 4},
-	{6, 13, 8, 2},
-	{6, 13, 8, 4},
-	{7, 13, 9, 2},
-	{7, 13, 10, 2},
-	{0, 0, 0, 0}
-};
-
-static const unsigned char cal_indextable[] = {
-	9, 23, 25
-};
-
-
-/*
- * translate ns.ns/10 coding of SPD timing values
- * into 10 ps unit values
- */
-
-unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version)
-{
-	unsigned short ns, ns10;
-
-	/* isolate upper nibble */
-	ns = (spd_byte >> 4) & 0x0F;
-	/* isolate lower nibble */
-	ns10 = (spd_byte & 0x0F);
-
-	return (ns * 100 + ns10 * 10);
-}
-
-/*
- * translate ns.ns/4 coding of SPD timing values
- * into 10 ps unit values
- */
-
-unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version)
-{
-	unsigned short ns, ns4;
-
-	/* isolate upper 6 bits */
-	ns = (spd_byte >> 2) & 0x3F;
-	/* isloate lower 2 bits */
-	ns4 = (spd_byte & 0x03);
-
-	return (ns * 100 + ns4 * 25);
-}
-
-/*
- * translate ns coding of SPD timing values
- * into 10 ps unit values
- */
-
-unsigned short NSto10PS (unsigned char spd_byte)
-{
-	return (spd_byte * 100);
-}
-
-void SDRAM_err (const char *s)
-{
-#ifndef SDRAM_DEBUG
-	(void) get_clocks ();
-	gd->baudrate = 9600;
-	serial_init ();
-#endif
-	serial_puts ("\n");
-	serial_puts (s);
-	serial_puts ("\n enable SDRAM_DEBUG for more info\n");
-	for (;;);
-}
-
-
-#ifdef SDRAM_DEBUG
-
-void write_hex (unsigned char i)
-{
-	char cc;
-
-	cc = i >> 4;
-	cc &= 0xf;
-	if (cc > 9)
-		serial_putc (cc + 55);
-	else
-		serial_putc (cc + 48);
-	cc = i & 0xf;
-	if (cc > 9)
-		serial_putc (cc + 55);
-	else
-		serial_putc (cc + 48);
-}
-
-void write_4hex (unsigned long val)
-{
-	write_hex ((unsigned char) (val >> 24));
-	write_hex ((unsigned char) (val >> 16));
-	write_hex ((unsigned char) (val >> 8));
-	write_hex ((unsigned char) val);
-}
-
-#endif
-
-int board_early_init_f (void)
-{
-	unsigned char datain[128];
-	unsigned long sdram_size = 0;
-	SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
-	unsigned long memclk;
-	unsigned long tmemclk = 0;
-	unsigned long tmp, bank, baseaddr, bank_size;
-	unsigned short i;
-	unsigned char rows, cols, banks, sdram_banks, density;
-	unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks,
-		trc_clocks;
-	unsigned char cal_index, cal_val, spd_version, spd_chksum;
-	unsigned char buf[8];
-#ifdef SDRAM_DEBUG
-	unsigned char tctp_clocks;
-#endif
-
-	/* set up the config port */
-	mtdcr (EBC0_CFGADDR, PB7AP);
-	mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP);
-	mtdcr (EBC0_CFGADDR, PB7CR);
-	mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR);
-
-	memclk = get_bus_freq (tmemclk);
-	tmemclk = 1000000000 / (memclk / 100);	/* in 10 ps units */
-
-#ifdef SDRAM_DEBUG
-	(void) get_clocks ();
-	gd->baudrate = 9600;
-	serial_init ();
-	serial_puts ("\nstart SDRAM Setup\n");
-#endif
-
-	/* Read Serial Presence Detect Information */
-	i2c_set_bus_num(0);
-	for (i = 0; i < 128; i++)
-		datain[i] = 127;
-	i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128);
-#ifdef SDRAM_DEBUG
-	serial_puts ("\ni2c_read returns ");
-	write_hex (i);
-	serial_puts ("\n");
-#endif
-
-#ifdef SDRAM_DEBUG
-	for (i = 0; i < 128; i++) {
-		write_hex (datain[i]);
-		serial_puts (" ");
-		if (((i + 1) % 16) == 0)
-			serial_puts ("\n");
-	}
-	serial_puts ("\n");
-#endif
-	spd_chksum = 0;
-	for (i = 0; i < 63; i++) {
-		spd_chksum += datain[i];
-	}							/* endfor */
-	if (datain[63] != spd_chksum) {
-#ifdef SDRAM_DEBUG
-		serial_puts ("SPD chksum: 0x");
-		write_hex (datain[63]);
-		serial_puts (" != calc. chksum: 0x");
-		write_hex (spd_chksum);
-		serial_puts ("\n");
-#endif
-		SDRAM_err ("SPD checksum Error");
-	}
-	/* SPD seems to be ok, use it */
-
-	/* get SPD version */
-	spd_version = datain[62];
-
-	/* do some sanity checks on the kind of RAM */
-	if ((datain[0] < 0x80) ||	/* less than 128 valid bytes in SPD */
-		(datain[2] != 0x04) ||	/* if not SDRAM */
-		(!((datain[6] == 0x40) || (datain[6] == 0x48))) ||	/* or not (64 Bit or 72 Bit)  */
-		(datain[7] != 0x00) || (datain[8] != 0x01) ||	/* or not LVTTL signal levels */
-		(datain[126] == 0x66))	/* or a 66MHz modules */
-		SDRAM_err ("unsupported SDRAM");
-#ifdef SDRAM_DEBUG
-	serial_puts ("SDRAM sanity ok\n");
-#endif
-
-	/* get number of rows/cols/banks out of byte 3+4+5 */
-	rows = datain[3];
-	cols = datain[4];
-	banks = datain[5];
-
-	/* get number of SDRAM banks out of byte 17 and
-	   supported CAS latencies out of byte 18 */
-	sdram_banks = datain[17];
-	supported_cal = datain[18] & ~0x81;
-
-	while (t->mode != 0) {
-		if ((t->row == rows) && (t->col == cols)
-			&& (t->bank == sdram_banks))
-			break;
-		t++;
-	}							/* endwhile */
-
-#ifdef SDRAM_DEBUG
-	serial_puts ("rows: ");
-	write_hex (rows);
-	serial_puts (" cols: ");
-	write_hex (cols);
-	serial_puts (" banks: ");
-	write_hex (banks);
-	serial_puts (" mode: ");
-	write_hex (t->mode);
-	serial_puts ("\n");
-#endif
-	if (t->mode == 0)
-		SDRAM_err ("unsupported SDRAM");
-	/* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */
-#ifdef SDRAM_DEBUG
-	serial_puts ("tRP: ");
-	write_hex (datain[27]);
-	serial_puts ("\ntRCD: ");
-	write_hex (datain[29]);
-	serial_puts ("\ntRAS: ");
-	write_hex (datain[30]);
-	serial_puts ("\n");
-#endif
-
-	trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk;
-	trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk;
-	tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk;
-	density = datain[31];
-
-	/* trc_clocks is sum of trp_clocks + tras_clocks */
-	trc_clocks = trp_clocks + tras_clocks;
-
-#ifdef SDRAM_DEBUG
-	/* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
-	tctp_clocks =
-			((NSto10PS (datain[30]) - NSto10PS (datain[29])) +
-			 (tmemclk - 1)) / tmemclk;
-
-	serial_puts ("c_RP: ");
-	write_hex (trp_clocks);
-	serial_puts ("\nc_RCD: ");
-	write_hex (trcd_clocks);
-	serial_puts ("\nc_RAS: ");
-	write_hex (tras_clocks);
-	serial_puts ("\nc_RC: (RP+RAS): ");
-	write_hex (trc_clocks);
-	serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
-	write_hex (tctp_clocks);
-	serial_puts ("\nt_CTP: RAS - RCD: ");
-	write_hex ((unsigned
-				char) ((NSto10PS (datain[30]) -
-						NSto10PS (datain[29])) >> 8));
-	write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29])));
-	serial_puts ("\ntmemclk: ");
-	write_hex ((unsigned char) (tmemclk >> 8));
-	write_hex ((unsigned char) (tmemclk));
-	serial_puts ("\n");
-#endif
-
-
-	cal_val = 255;
-	for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) {
-		/* is this CAS latency supported ? */
-		if ((supported_cal >> i) & 0x01) {
-			buf[0] = datain[cal_indextable[cal_index]];
-			if (cal_index < 2) {
-				if (NS10to10PS (buf[0], spd_version) <= tmemclk)
-					cal_val = i;
-			} else {
-				/* SPD bytes 25+26 have another format */
-				if (NS4to10PS (buf[0], spd_version) <= tmemclk)
-					cal_val = i;
-			}	/* endif */
-			cal_index++;
-		}	/* endif */
-	}	/* endfor */
-#ifdef SDRAM_DEBUG
-	serial_puts ("CAL: ");
-	write_hex (cal_val + 1);
-	serial_puts ("\n");
-#endif
-
-	if (cal_val == 255)
-		SDRAM_err ("unsupported SDRAM");
-
-	/* get SDRAM timing register */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
-	tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
-	/* insert CASL value */
-/*  tmp |= ((unsigned long)cal_val) << 23; */
-	tmp |= ((unsigned long) cal_val) << 23;
-	/* insert PTA value */
-	tmp |= ((unsigned long) (trp_clocks - 1)) << 18;
-	/* insert CTP value */
-/*  tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */
-	tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16;
-	/* insert LDF (always 01) */
-	tmp |= ((unsigned long) 0x01) << 14;
-	/* insert RFTA value */
-	tmp |= ((unsigned long) (trc_clocks - 4)) << 2;
-	/* insert RCD value */
-	tmp |= ((unsigned long) (trcd_clocks - 1)) << 0;
-
-#ifdef SDRAM_DEBUG
-	serial_puts ("sdtr: ");
-	write_4hex (tmp);
-	serial_puts ("\n");
-#endif
-
-	/* write SDRAM timing register */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
-	mtdcr (SDRAM0_CFGDATA, tmp);
-	baseaddr = CONFIG_SYS_SDRAM_BASE;
-	bank_size = (((unsigned long) density) << 22) / 2;
-	/* insert AM value */
-	tmp = ((unsigned long) t->mode - 1) << 13;
-	/* insert SZ value; */
-	switch (bank_size) {
-	case 0x00400000:
-		tmp |= ((unsigned long) 0x00) << 17;
-		break;
-	case 0x00800000:
-		tmp |= ((unsigned long) 0x01) << 17;
-		break;
-	case 0x01000000:
-		tmp |= ((unsigned long) 0x02) << 17;
-		break;
-	case 0x02000000:
-		tmp |= ((unsigned long) 0x03) << 17;
-		break;
-	case 0x04000000:
-		tmp |= ((unsigned long) 0x04) << 17;
-		break;
-	case 0x08000000:
-		tmp |= ((unsigned long) 0x05) << 17;
-		break;
-	case 0x10000000:
-		tmp |= ((unsigned long) 0x06) << 17;
-		break;
-	default:
-		SDRAM_err ("unsupported SDRAM");
-	}	/* endswitch */
-	/* get SDRAM bank 0 register */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
-	bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
-	bank |= (baseaddr | tmp | 0x01);
-#ifdef SDRAM_DEBUG
-	serial_puts ("bank0: baseaddr: ");
-	write_4hex (baseaddr);
-	serial_puts (" banksize: ");
-	write_4hex (bank_size);
-	serial_puts (" mb0cf: ");
-	write_4hex (bank);
-	serial_puts ("\n");
-#endif
-	baseaddr += bank_size;
-	sdram_size += bank_size;
-
-	/* write SDRAM bank 0 register */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
-	mtdcr (SDRAM0_CFGDATA, bank);
-
-	/* get SDRAM bank 1 register */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
-	bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
-	sdram_size = 0;
-
-#ifdef SDRAM_DEBUG
-	serial_puts ("bank1: baseaddr: ");
-	write_4hex (baseaddr);
-	serial_puts (" banksize: ");
-	write_4hex (bank_size);
-#endif
-	if (banks == 2) {
-		bank |= (baseaddr | tmp | 0x01);
-		baseaddr += bank_size;
-		sdram_size += bank_size;
-	}	/* endif */
-#ifdef SDRAM_DEBUG
-	serial_puts (" mb1cf: ");
-	write_4hex (bank);
-	serial_puts ("\n");
-#endif
-	/* write SDRAM bank 1 register */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
-	mtdcr (SDRAM0_CFGDATA, bank);
-
-	/* get SDRAM bank 2 register */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
-	bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
-
-	bank |= (baseaddr | tmp | 0x01);
-
-#ifdef SDRAM_DEBUG
-	serial_puts ("bank2: baseaddr: ");
-	write_4hex (baseaddr);
-	serial_puts (" banksize: ");
-	write_4hex (bank_size);
-	serial_puts (" mb2cf: ");
-	write_4hex (bank);
-	serial_puts ("\n");
-#endif
-
-	baseaddr += bank_size;
-	sdram_size += bank_size;
-
-	/* write SDRAM bank 2 register */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
-	mtdcr (SDRAM0_CFGDATA, bank);
-
-	/* get SDRAM bank 3 register */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
-	bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
-
-#ifdef SDRAM_DEBUG
-	serial_puts ("bank3: baseaddr: ");
-	write_4hex (baseaddr);
-	serial_puts (" banksize: ");
-	write_4hex (bank_size);
-#endif
-
-	if (banks == 2) {
-		bank |= (baseaddr | tmp | 0x01);
-		baseaddr += bank_size;
-		sdram_size += bank_size;
-	}
-	/* endif */
-#ifdef SDRAM_DEBUG
-	serial_puts (" mb3cf: ");
-	write_4hex (bank);
-	serial_puts ("\n");
-#endif
-
-	/* write SDRAM bank 3 register */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
-	mtdcr (SDRAM0_CFGDATA, bank);
-
-
-	/* get SDRAM refresh interval register */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
-	tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
-
-	if (tmemclk < NSto10PS (16))
-		tmp |= 0x05F00000;
-	else
-		tmp |= 0x03F80000;
-
-	/* write SDRAM refresh interval register */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
-	mtdcr (SDRAM0_CFGDATA, tmp);
-
-	/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
-	tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000;
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
-	mtdcr (SDRAM0_CFGDATA, tmp);
-
-
-   /*-------------------------------------------------------------------------+
-   | Interrupt controller setup for the PIP405 board.
-   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
-   |       IRQ 16    405GP internally generated; active low; level sensitive
-   |       IRQ 17-24 RESERVED
-   |       IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive
-   |       IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
-   |       IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
-   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
-   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
-   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
-   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
-   | Note for PIP405 board:
-   |       An interrupt taken for the SouthBridge (IRQ 25) indicates that
-   |       the Interrupt Controller in the South Bridge has caused the
-   |       interrupt. The IC must be read to determine which device
-   |       caused the interrupt.
-   |
-   +-------------------------------------------------------------------------*/
-	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
-	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical (for now) */
-	mtdcr (UIC0PR, 0xFFFFFF80);	/* set int polarities */
-	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
-	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	int mode;
-
-	/*
-	 * since we are relocated, we can finally enable i-cache
-	 * and set up the flash CS correctly
-	 */
-	icache_enable();
-	setup_cs_reloc();
-	/* get and display boot mode */
-	mode = get_boot_mode();
-	if (mode & BOOT_PCI)
-		printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ?
-			"MPS" : "Flash");
-	else
-		printf("%s Boot\n", (mode & BOOT_MPS) ?
-			"MPS" : "Flash");
-
-	return 0;
-}
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
-	char s[50];
-	unsigned char bc;
-	int i;
-	backup_t *b = (backup_t *) s;
-
-	puts ("Board: ");
-
-	i = getenv_f("serial#", (char *)s, 32);
-	if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) {
-		get_backup_values (b);
-		if (strncmp (b->signature, "MPL\0", 4) != 0) {
-			puts ("### No HW ID - assuming PIP405");
-		} else {
-			b->serial_name[6] = 0;
-			printf ("%s SN: %s", b->serial_name,
-				&b->serial_name[7]);
-		}
-	} else {
-		s[6] = 0;
-		printf ("%s SN: %s", s, &s[7]);
-	}
-	bc = in8 (CONFIG_PORT_ADDR);
-	printf (" Boot Config: 0x%x\n", bc);
-	return (0);
-}
-
-
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-/*
-  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
-  the necessary info for SDRAM controller configuration
-*/
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-static int test_dram (unsigned long ramsize);
-
-phys_size_t initdram (int board_type)
-{
-	unsigned long bank_reg[4], tmp, bank_size;
-	int i, ds;
-	unsigned long TotalSize;
-
-	ds = 0;
-	/* since the DRAM controller is allready set up,
-	 * calculate the size with the bank registers
-	 */
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
-	bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
-	bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
-	bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
-	bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
-	TotalSize = 0;
-	for (i = 0; i < 4; i++) {
-		if ((bank_reg[i] & 0x1) == 0x1) {
-			tmp = (bank_reg[i] >> 17) & 0x7;
-			bank_size = 4 << tmp;
-			TotalSize += bank_size;
-		} else
-			ds = 1;
-	}
-	if (ds == 1)
-		printf ("single-sided DIMM ");
-	else
-		printf ("double-sided DIMM ");
-	test_dram (TotalSize * 1024 * 1024);
-	/* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */
-	(void) get_clocks();
-	if (gd->cpu_clk > 220000000)
-		TotalSize /= 2;
-	return (TotalSize * 1024 * 1024);
-}
-
-/* ------------------------------------------------------------------------- */
-
-
-static int test_dram (unsigned long ramsize)
-{
-	/* not yet implemented */
-	return (1);
-}
-
-int misc_init_r (void)
-{
-	/* adjust flash start and size as well as the offset */
-	gd->bd->bi_flashstart=0-flash_info[0].size;
-	gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
-	gd->bd->bi_flashoffset=0;
-
-	/* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
-	if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
-	       mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
-
-	return (0);
-}
-
-/***************************************************************************
- * some helping routines
- */
-
-int overwrite_console (void)
-{
-	/* return true if console should be overwritten */
-	return in8(CONFIG_PORT_ADDR) & 0x1;
-}
-
-
-extern int isa_init (void);
-
-
-void print_pip405_rev (void)
-{
-	unsigned char part, vers, cfg;
-
-	part = in8 (PLD_PART_REG);
-	vers = in8 (PLD_VERS_REG);
-	cfg = in8 (PLD_BOARD_CFG_REG);
-	printf ("Rev:   PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
-			16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf,
-			vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf);
-}
-
-extern void check_env(void);
-
-
-int last_stage_init (void)
-{
-	print_pip405_rev ();
-	isa_init ();
-	stdio_print_current_devices ();
-	check_env();
-	return 0;
-}
-
-/************************************************************************
-* Print PIP405 Info
-************************************************************************/
-void print_pip405_info (void)
-{
-	unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr,
-			compwr, nicvga, scsirst;
-
-	part = in8 (PLD_PART_REG);
-	vers = in8 (PLD_VERS_REG);
-	cfg = in8 (PLD_BOARD_CFG_REG);
-	ledu = in8 (PLD_LED_USER_REG);
-	sysman = in8 (PLD_SYS_MAN_REG);
-	flashcom = in8 (PLD_FLASH_COM_REG);
-	can = in8 (PLD_CAN_REG);
-	serpwr = in8 (PLD_SER_PWR_REG);
-	compwr = in8 (PLD_COM_PWR_REG);
-	nicvga = in8 (PLD_NIC_VGA_REG);
-	scsirst = in8 (PLD_SCSI_RST_REG);
-	printf ("PLD Part %d version %d\n",
-		part & 0xf, vers & 0xf);
-	printf ("PLD Part %d version %d\n",
-		(part >> 4) & 0xf, (vers >> 4) & 0xf);
-	printf ("Board Revision %c\n", (cfg & 0xf) + 'A');
-	printf ("Population Options %d %d %d %d\n",
-		(cfg >> 4) & 0x1, (cfg >> 5) & 0x1,
-		(cfg >> 6) & 0x1, (cfg >> 7) & 0x1);
-	printf ("User LED0 %s User LED1 %s\n",
-		((ledu & 0x1) == 0x1) ? "on" : "off",
-		((ledu & 0x2) == 0x2) ? "on" : "off");
-	printf ("Additionally Options %d %d\n",
-		(ledu >> 2) & 0x1, (ledu >> 3) & 0x1);
-	printf ("User Config Switch %d %d %d %d\n",
-		(ledu >> 4) & 0x1, (ledu >> 5) & 0x1,
-		(ledu >> 6) & 0x1, (ledu >> 7) & 0x1);
-	switch (sysman & 0x3) {
-	case 0:
-		printf ("PCI Clocks are running\n");
-		break;
-	case 1:
-		printf ("PCI Clocks are stopped in POS State\n");
-		break;
-	case 2:
-		printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
-		break;
-	case 3:
-		printf ("PCI Clocks are stopped\n");
-		break;
-	}
-	switch ((sysman >> 2) & 0x3) {
-	case 0:
-		printf ("Main Clocks are running\n");
-		break;
-	case 1:
-		printf ("Main Clocks are stopped in POS State\n");
-		break;
-	case 2:
-	case 3:
-		printf ("PCI Clocks are stopped\n");
-		break;
-	}
-	printf ("INIT asserts %sINT2# (SMI)\n",
-			((sysman & 0x10) == 0x10) ? "" : "not ");
-	printf ("INIT asserts %sINT1# (NMI)\n",
-			((sysman & 0x20) == 0x20) ? "" : "not ");
-	printf ("INIT occurred %d\n", (sysman >> 6) & 0x1);
-	printf ("SER1 is routed to %s\n",
-			((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
-	printf ("COM2 is routed to %s\n",
-			((flashcom & 0x2) == 0x2) ? "RS485" : "RS232");
-	printf ("RS485 is configured as %s duplex\n",
-			((flashcom & 0x4) == 0x4) ? "full" : "half");
-	printf ("RS485 is connected to %s\n",
-			((flashcom & 0x8) == 0x8) ? "COM1" : "COM2");
-	printf ("SER1 uses handshakes %s\n",
-			((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
-	printf ("Bootflash is %swriteprotected\n",
-			((flashcom & 0x20) == 0x20) ? "not " : "");
-	printf ("Bootflash VPP is %s\n",
-			((flashcom & 0x40) == 0x40) ? "on" : "off");
-	printf ("Bootsector is %swriteprotected\n",
-			((flashcom & 0x80) == 0x80) ? "not " : "");
-	switch ((can) & 0x3) {
-	case 0:
-		printf ("CAN Controller is on address 0x1000..0x10FF\n");
-		break;
-	case 1:
-		printf ("CAN Controller is on address 0x8000..0x80FF\n");
-		break;
-	case 2:
-		printf ("CAN Controller is on address 0xE000..0xE0FF\n");
-		break;
-	case 3:
-		printf ("CAN Controller is disabled\n");
-		break;
-	}
-	switch ((can >> 2) & 0x3) {
-	case 0:
-		printf ("CAN Controller Reset is ISA Reset\n");
-		break;
-	case 1:
-		printf ("CAN Controller Reset is ISA Reset and POS State\n");
-		break;
-	case 2:
-	case 3:
-		printf ("CAN Controller is in reset\n");
-		break;
-	}
-	if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13))
-		printf ("CAN Interrupt is disabled\n");
-	else
-		printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf);
-	switch (serpwr & 0x3) {
-	case 0:
-		printf ("SER0 Drivers are enabled\n");
-		break;
-	case 1:
-		printf ("SER0 Drivers are disabled in the POS state\n");
-		break;
-	case 2:
-	case 3:
-		printf ("SER0 Drivers are disabled\n");
-		break;
-	}
-	switch ((serpwr >> 2) & 0x3) {
-	case 0:
-		printf ("SER1 Drivers are enabled\n");
-		break;
-	case 1:
-		printf ("SER1 Drivers are disabled in the POS state\n");
-		break;
-	case 2:
-	case 3:
-		printf ("SER1 Drivers are disabled\n");
-		break;
-	}
-	switch (compwr & 0x3) {
-	case 0:
-		printf ("COM1 Drivers are enabled\n");
-		break;
-	case 1:
-		printf ("COM1 Drivers are disabled in the POS state\n");
-		break;
-	case 2:
-	case 3:
-		printf ("COM1 Drivers are disabled\n");
-		break;
-	}
-	switch ((compwr >> 2) & 0x3) {
-	case 0:
-		printf ("COM2 Drivers are enabled\n");
-		break;
-	case 1:
-		printf ("COM2 Drivers are disabled in the POS state\n");
-		break;
-	case 2:
-	case 3:
-		printf ("COM2 Drivers are disabled\n");
-		break;
-	}
-	switch ((nicvga) & 0x3) {
-	case 0:
-		printf ("PHY is running\n");
-		break;
-	case 1:
-		printf ("PHY is in Power save mode in POS state\n");
-		break;
-	case 2:
-	case 3:
-		printf ("PHY is in Power save mode\n");
-		break;
-	}
-	switch ((nicvga >> 2) & 0x3) {
-	case 0:
-		printf ("VGA is running\n");
-		break;
-	case 1:
-		printf ("VGA is in Power save mode in POS state\n");
-		break;
-	case 2:
-	case 3:
-		printf ("VGA is in Power save mode\n");
-		break;
-	}
-	printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not ");
-	printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not ");
-	printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1,
-			(nicvga >> 7) & 0x1);
-	switch ((scsirst) & 0x3) {
-	case 0:
-		printf ("SCSI Controller is running\n");
-		break;
-	case 1:
-		printf ("SCSI Controller is in Power save mode in POS state\n");
-		break;
-	case 2:
-	case 3:
-		printf ("SCSI Controller is in Power save mode\n");
-		break;
-	}
-	printf ("SCSI termination is %s\n",
-			((scsirst & 0x4) == 0x4) ? "disabled" : "enabled");
-	printf ("SCSI Controller is %sreseted\n",
-			((scsirst & 0x10) == 0x10) ? "" : "not ");
-	printf ("IDE disks are %sreseted\n",
-			((scsirst & 0x20) == 0x20) ? "" : "not ");
-	printf ("ISA Bus is %sreseted\n",
-			((scsirst & 0x40) == 0x40) ? "" : "not ");
-	printf ("Super IO is %sreseted\n",
-			((scsirst & 0x80) == 0x80) ? "" : "not ");
-}
-
-void user_led0 (unsigned char on)
-{
-	if (on == true)
-		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1));
-	else
-		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe));
-}
-
-void user_led1 (unsigned char on)
-{
-	if (on == true)
-		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2));
-	else
-		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd));
-}
-
-void ide_set_reset (int idereset)
-{
-	/* if reset = 1 IDE reset will be asserted */
-	unsigned char resreg;
-
-	resreg = in8 (PLD_SCSI_RST_REG);
-	if (idereset == 1)
-		resreg |= 0x20;
-	else {
-		udelay(10000);
-		resreg &= 0xdf;
-	}
-	out8 (PLD_SCSI_RST_REG, resreg);
-}
diff --git a/board/mpl/pip405/pip405.h b/board/mpl/pip405/pip405.h
deleted file mode 100644
index 1f07d79..0000000
--- a/board/mpl/pip405/pip405.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * (C) Copyright 2001
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
- /****************************************************************************
- * Global routines used for PIP405
- *****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-extern int  mem_test(unsigned long start, unsigned long ramsize,int mode);
-
-void print_pip405_info(void);
-
-void user_led0(unsigned char on);
-void user_led1(unsigned char on);
-
-
-#define PLD_BASE_ADDRESS		CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x800
-#define PLD_PART_REG			PLD_BASE_ADDRESS + 0
-#define PLD_VERS_REG			PLD_BASE_ADDRESS + 1
-#define PLD_BOARD_CFG_REG		PLD_BASE_ADDRESS + 2
-#define PLD_LED_USER_REG		PLD_BASE_ADDRESS + 3
-#define PLD_SYS_MAN_REG			PLD_BASE_ADDRESS + 4
-#define PLD_FLASH_COM_REG		PLD_BASE_ADDRESS + 5
-#define PLD_CAN_REG			PLD_BASE_ADDRESS + 6
-#define PLD_SER_PWR_REG			PLD_BASE_ADDRESS + 7
-#define PLD_COM_PWR_REG			PLD_BASE_ADDRESS + 8
-#define PLD_NIC_VGA_REG			PLD_BASE_ADDRESS + 9
-#define PLD_SCSI_RST_REG		PLD_BASE_ADDRESS + 0xA
-
-#define PIIX4_VENDOR_ID			0x8086
-#define PIIX4_IDE_DEV_ID		0x7111
-
-#endif
-
-/* timings */
-
-/* CS Config register (CS7) */
-#define CONFIG_PORT_BME	0	/* Burst disable */
-#define CONFIG_PORT_TWE	255	/* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
-#define CONFIG_PORT_CSN	1	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define CONFIG_PORT_OEN	1	/* Cycles from CS low to OE low   */
-#define CONFIG_PORT_WBN	1	/* Cycles from CS low to WE low   */
-#define CONFIG_PORT_WBF	1	/* Cycles from WE high to CS high */
-#define CONFIG_PORT_TH	2	/* Number of hold cycles after transfer */
-#define CONFIG_PORT_RE	0	/* Ready disabled */
-#define CONFIG_PORT_SOR	1	/* Sample on Ready disabled */
-#define CONFIG_PORT_BEM	0	/* Byte Write only active on Write cycles */
-#define CONFIG_PORT_PEN	0	/* Parity disable */
-#define CONFIG_PORT_AP	((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \
-				(CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define CONFIG_PORT_BS	0	/* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define CONFIG_PORT_BU	3	/* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define CONFIG_PORT_BW	0	/* 16Bit */
-#define CONFIG_PORT_CR	((CONFIG_PORT_ADDR & 0xfff00000) + (CONFIG_PORT_BS << 17) + (CONFIG_PORT_BU << 15) + (CONFIG_PORT_BW << 13))
-
-/* Flash CS0 or CS 1 */
-/* 0x7F8FFE80 slowest timing at all... */
-#define FLASH_BME_B	1	/* Burst enable */
-#define FLASH_FWT_B	0x6	/* 6 * 30ns 210ns First Wait Access */
-#define FLASH_BWT_B	0x6	/* 6 * 30ns 210ns Burst Wait Access */
-#define FLASH_BME	0	/* Burst disable */
-#define FLASH_TWE	0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
-#define FLASH_CSN	0	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define FLASH_OEN	1	/* Cycles from CS low to OE low   */
-#define FLASH_WBN	1	/* Cycles from CS low to WE low   */
-#define FLASH_WBF	1	/* Cycles from WE high to CS high */
-#define FLASH_TH	2	/* Number of hold cycles after transfer */
-#define FLASH_RE	0	/* Ready disabled */
-#define FLASH_SOR	1	/* Sample on Ready disabled */
-#define FLASH_BEM	0	/* Byte Write only active on Write cycles */
-#define FLASH_PEN	0	/* Parity disable */
-/* Access Parameter Register for non Boot */
-#define FLASH_AP	((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
-				(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
-/* Access Parameter Register for Boot */
-#define FLASH_AP_B	((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
-				(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define FLASH_BS	FLASH_SIZE_PRELIM	/* 4 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define FLASH_BU	3	/* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define FLASH_BW	1	/* 16Bit */
-/* CR register for Boot */
-#define FLASH_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
-/* CR register for non Boot */
-#define FLASH_CR	((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
-
-/* MPS CS1 or CS0 */
-/* Boot CS: */
-#define MPS_BME_B	1	/* Burst enable */
-#define MPS_FWT_B	0x6/* 6 * 30ns 210ns First Wait Access */
-#define MPS_BWT_B	0x6	/* 6 * 30ns 210ns Burst Wait Access */
-#define MPS_BME		0	/* Burst disable */
-#define MPS_TWE		0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
-#define MPS_CSN		0	/* Chipselect is driven inactive for 1 Cycle BTW transfers */
-#define MPS_OEN		1	/* Cycles from CS low to OE low   */
-#define MPS_WBN		1	/* Cycles from CS low to WE low   */
-#define MPS_WBF		1	/* Cycles from WE high to CS high */
-#define MPS_TH		2	/* Number of hold cycles after transfer */
-#define MPS_RE		0	/* Ready disabled */
-#define MPS_SOR		1	/* Sample on Ready disabled */
-#define MPS_BEM		0	/* Byte Write only active on Write cycles */
-#define MPS_PEN		0	/* Parity disable */
-/* Access Parameter Register for non Boot */
-#define MPS_AP		((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
-				(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
-/* Access Parameter Register for Boot */
-#define MPS_AP_B	((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
-				(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
-
-/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
-#define MPS_BS		2	/* 4 MByte */
-#define MPS_BS_B		FLASH_SIZE_PRELIM	/* 1 MByte */
-/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
-#define MPS_BU		3	/* R/W */
-/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
-#define MPS_BW		0	/* 8Bit */
-/* CR register for Boot */
-#define MPS_CR_B	((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
-/* CR register for non Boot */
-#define MPS_CR		((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug
deleted file mode 100644
index 890f592..0000000
--- a/board/mpl/pip405/u-boot.lds.debug
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    mpc8xx/start.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib/vsprintf.o	(.text)
-    lib/crc32.o		(.text)
-    arch/powerpc/lib/extable.o	(.text)
-
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/mpl/vcma9/Kconfig b/board/mpl/vcma9/Kconfig
deleted file mode 100644
index a156452..0000000
--- a/board/mpl/vcma9/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_VCMA9
-
-config SYS_BOARD
-	default "vcma9"
-
-config SYS_VENDOR
-	default "mpl"
-
-config SYS_SOC
-	default "s3c24x0"
-
-config SYS_CONFIG_NAME
-	default "VCMA9"
-
-endif
diff --git a/board/mpl/vcma9/MAINTAINERS b/board/mpl/vcma9/MAINTAINERS
deleted file mode 100644
index 3817436..0000000
--- a/board/mpl/vcma9/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-VCMA9 BOARD
-M:	David Müller <d.mueller@elsoft.ch>
-S:	Maintained
-F:	board/mpl/vcma9/
-F:	include/configs/VCMA9.h
-F:	configs/VCMA9_defconfig
diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile
deleted file mode 100644
index 175a19f..0000000
--- a/board/mpl/vcma9/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= ../common/common_util.o
-obj-y	+= vcma9.o cmd_vcma9.o
-
-obj-y	+= lowlevel_init.o
diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c
deleted file mode 100644
index c2d62e4..0000000
--- a/board/mpl/vcma9/cmd_vcma9.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * (C) Copyright 2002
- * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
- *
- * adapted for VCMA9
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <net.h>
-#include "vcma9.h"
-#include "../common/common_util.h"
-
-#if defined(CONFIG_CS8900)
-#include <../drivers/net/cs8900.h>
-
-static uchar cs8900_chksum(ushort data)
-{
-	return((data >> 8) & 0x00FF) + (data & 0x00FF);
-}
-
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	struct eth_device *dev;
-	char cs8900_name[10];
-	if (strcmp(argv[1], "info") == 0)
-	{
-		vcma9_print_info();
-		return 0;
-	}
-#if defined(CONFIG_CS8900)
-	if (strcmp(argv[1], "cs8900") == 0) {
-		sprintf(cs8900_name, "%s-0", CS8900_DRIVERNAME);
-		dev = eth_get_dev_by_name(cs8900_name);
-		if (!dev) {
-			printf("Couldn't find CS8900 driver");
-			return 0;
-		}
-		if (strcmp(argv[2], "read") == 0) {
-			uchar addr; ushort data;
-
-			addr = simple_strtoul(argv[3], NULL, 16);
-			cs8900_e2prom_read(dev, addr, &data);
-			printf("0x%2.2X: 0x%4.4X\n", addr, data);
-		} else if (strcmp(argv[2], "write") == 0) {
-			uchar addr; ushort data;
-
-			addr = simple_strtoul(argv[3], NULL, 16);
-			data = simple_strtoul(argv[4], NULL, 16);
-			cs8900_e2prom_write(dev, addr, data);
-		} else if (strcmp(argv[2], "setaddr") == 0) {
-			uchar addr, i, csum; ushort data;
-			uchar ethaddr[6];
-
-			/* check for valid ethaddr */
-			if (eth_getenv_enetaddr("ethaddr", ethaddr)) {
-				addr = 1;
-				data = 0x2158;
-				cs8900_e2prom_write(dev, addr, data);
-				csum = cs8900_chksum(data);
-				addr++;
-				for (i = 0; i < 6; i+=2) {
-					data = ethaddr[i+1] << 8 |
-					       ethaddr[i];
-					cs8900_e2prom_write(dev, addr, data);
-					csum += cs8900_chksum(data);
-					addr++;
-				}
-				/* calculate header link byte */
-				data = 0xA100 | (addr * 2);
-				cs8900_e2prom_write(dev, 0, data);
-				csum += cs8900_chksum(data);
-				/* write checksum word */
-				cs8900_e2prom_write(dev, addr, (0 - csum) << 8);
-			} else {
-				puts("\nplease defined 'ethaddr'\n");
-			}
-		} else if (strcmp(argv[2], "dump") == 0) {
-			uchar addr = 0, endaddr, csum; ushort data;
-
-			puts("Dump of CS8900 config device: ");
-			cs8900_e2prom_read(dev, addr, &data);
-			if ((data & 0xE000) == 0xA000) {
-				endaddr = (data & 0x00FF) / 2;
-				csum = cs8900_chksum(data);
-				for (addr = 1; addr <= endaddr; addr++) {
-					cs8900_e2prom_read(dev, addr, &data);
-					printf("\n0x%2.2X: 0x%4.4X", addr, data);
-					csum += cs8900_chksum(data);
-				}
-				printf("\nChecksum: %s", (csum == 0) ? "ok" : "wrong");
-			} else {
-				puts("no valid config found");
-			}
-			puts("\n");
-		}
-
-		return 0;
-	}
-#endif
-
-	return (do_mplcommon(cmdtp, flag, argc, argv));
-}
-
-U_BOOT_CMD(
-	vcma9, 6, 1, do_vcma9,
-	"VCMA9 specific commands",
-	"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
-	"vcma9 info                - displays board information"
-);
diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S
deleted file mode 100644
index c0d6cc8..0000000
--- a/board/mpl/vcma9/lowlevel_init.S
+++ /dev/null
@@ -1,500 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for MPL VCMA9 by
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- * (C) Copyright 2002, 2003, 2004, 2005
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-#include <config.h>
-
-/* register definitions */
-
-#define PLD_BASE	0x28000000
-#define MISC_REG	0x103
-#define SDRAM_REG	0x106
-#define BWSCON		0x48000000
-#define CLKBASE		0x4C000000
-#define LOCKTIME	0x0
-#define MPLLCON		0x4
-#define UPLLCON		0x8
-#define GPIOBASE	0x56000000
-#define GSTATUS1	0xB0
-#define FASTCPU		0x02
-
-/* some parameters for the board */
-/* BWSCON */
-#define DW8			(0x0)
-#define DW16			(0x1)
-#define DW32			(0x2)
-#define WAIT			(0x1<<2)
-#define UBLB			(0x1<<3)
-
-/* BANKSIZE */
-#define BURST_EN		(0x1<<7)
-
-/* BANK0CON 200 */
-#define B0_Tacs_200		0x0	/*  0clk  (or 0x1 1clk) */
-#define B0_Tcos_200		0x1	/*  1clk  (or 0x2 2clk) */
-#define B0_Tacc_200		0x5	/*  8clk  (or 0x6 10clk) */
-#define B0_Tcoh_200		0x0	/*  0clk */
-#define B0_Tcah_200		0x3	/*  4clk  (or0x01 1clk) */
-#define B0_Tacp_200		0x0     /* page mode is not used */
-#define B0_PMC_200		0x0	/* page mode disabled */
-
-/* BANK0CON 250 */
-#define B0_Tacs_250		0x0	/*  0clk  (or 0x1 1clk) */
-#define B0_Tcos_250		0x1	/*  1clk  (or 0x2 2clk) */
-#define B0_Tacc_250		0x5	/*  8clk  (or 0x7 14clk) */
-#define B0_Tcoh_250		0x0	/*  0clk */
-#define B0_Tcah_250		0x3	/*  4clk  (or 0x1 1clk) */
-#define B0_Tacp_250		0x0     /* page mode is not used */
-#define B0_PMC_250		0x0	/* page mode disabled */
-
-/* BANK0CON 266 */
-#define B0_Tacs_266		0x0	/*  0clk  (or 0x1 1clk) */
-#define B0_Tcos_266		0x1	/*  1clk  (or 0x2 2clk) */
-#define B0_Tacc_266		0x6	/*  10clk (or 0x7 14clk) */
-#define B0_Tcoh_266		0x0	/*  0clk */
-#define B0_Tcah_266		0x3	/*  4clk  (or 0x1 1clk) */
-#define B0_Tacp_266		0x0     /* page mode is not used */
-#define B0_PMC_266		0x0	/* page mode disabled */
-
-/* BANK1CON 200 */
-#define B1_Tacs_200		0x0	/*  0clk  (or 0x1 1clk) */
-#define B1_Tcos_200		0x1	/*  1clk  (or 0x2 2clk) */
-#define B1_Tacc_200		0x5	/*  8clk  (or 0x6 10clk) */
-#define B1_Tcoh_200		0x0	/*  0clk */
-#define B1_Tcah_200		0x3	/*  4clk  (or 0x1 1clk) */
-#define B1_Tacp_200		0x0     /* page mode is not used */
-#define B1_PMC_200		0x0	/* page mode disabled */
-
-/* BANK1CON 250 */
-#define B1_Tacs_250		0x0	/*  0clk  (or 0x1 1clk) */
-#define B1_Tcos_250		0x1	/*  1clk  (or 0x2 2clk) */
-#define B1_Tacc_250		0x5	/*  8clk  (or 0x7 14clk) */
-#define B1_Tcoh_250		0x0	/*  0clk */
-#define B1_Tcah_250		0x3	/*  4clk  (or 0x1 1clk) */
-#define B1_Tacp_250		0x0     /* page mode is not used */
-#define B1_PMC_250		0x0	/* page mode disabled */
-
-/* BANK1CON 266 */
-#define B1_Tacs_266		0x0	/*  0clk  (or 0x1 1clk) */
-#define B1_Tcos_266		0x1	/*  1clk  (or 0x2 2clk) */
-#define B1_Tacc_266		0x6	/*  10clk (or 0x7 14clk) */
-#define B1_Tcoh_266		0x0	/*  0clk */
-#define B1_Tcah_266		0x3	/*  4clk  (or 0x1 1clk) */
-#define B1_Tacp_266		0x0     /* page mode is not used */
-#define B1_PMC_266		0x0	/* page mode disabled */
-
-/* BANK2CON 200 + 250 + 266 */
-#define B2_Tacs			0x3	/*  4clk */
-#define B2_Tcos			0x3	/*  4clk */
-#define B2_Tacc			0x7     /* 14clk */
-#define B2_Tcoh			0x3	/*  4clk */
-#define B2_Tcah			0x3	/*  4clk */
-#define B2_Tacp			0x0	/* page mode is not used */
-#define B2_PMC			0x0     /* page mode disabled */
-
-/* BANK3CON 200 + 250 + 266 */
-#define B3_Tacs			0x3	/*  4clk */
-#define B3_Tcos			0x3	/*  4clk */
-#define B3_Tacc			0x7     /* 14clk */
-#define B3_Tcoh			0x3	/*  4clk */
-#define B3_Tcah			0x3	/*  4clk */
-#define B3_Tacp			0x0	/* page mode is not used */
-#define B3_PMC			0x0     /* page mode disabled */
-
-/* BANK4CON 200 */
-#define B4_Tacs_200		0x1	/*  1clk */
-#define B4_Tcos_200		0x3	/*  4clk */
-#define B4_Tacc_200		0x7	/* 14clk */
-#define B4_Tcoh_200		0x3	/*  4clk */
-#define B4_Tcah_200		0x2	/*  2clk */
-#define B4_Tacp_200		0x0     /* page mode is not used */
-#define B4_PMC_200		0x0	/* page mode disabled */
-
-/* BANK4CON 250 */
-#define B4_Tacs_250		0x1	/*  1clk */
-#define B4_Tcos_250		0x3	/*  4clk */
-#define B4_Tacc_250		0x7	/* 14clk */
-#define B4_Tcoh_250		0x3	/*  4clk */
-#define B4_Tcah_250		0x2	/*  2clk */
-#define B4_Tacp_250		0x0     /* page mode is not used */
-#define B4_PMC_250		0x0	/* page mode disabled */
-
-/* BANK4CON 266 */
-#define B4_Tacs_266		0x1	/*  1clk */
-#define B4_Tcos_266		0x3	/*  4clk */
-#define B4_Tacc_266		0x7	/* 14clk */
-#define B4_Tcoh_266		0x3	/*  4clk */
-#define B4_Tcah_266		0x2	/*  2clk */
-#define B4_Tacp_266		0x0     /* page mode is not used */
-#define B4_PMC_266		0x0	/* page mode disabled */
-
-/* BANK5CON 200 */
-#define B5_Tacs_200		0x0	/*  0clk */
-#define B5_Tcos_200		0x3	/*  4clk */
-#define B5_Tacc_200		0x4	/*  6clk */
-#define B5_Tcoh_200		0x3	/*  4clk */
-#define B5_Tcah_200		0x1	/*  1clk */
-#define B5_Tacp_200		0x0     /* page mode is not used */
-#define B5_PMC_200		0x0	/* page mode disabled */
-
-/* BANK5CON 250 */
-#define B5_Tacs_250		0x0	/*  0clk */
-#define B5_Tcos_250		0x3	/*  4clk */
-#define B5_Tacc_250		0x5	/*  8clk */
-#define B5_Tcoh_250		0x3	/*  4clk */
-#define B5_Tcah_250		0x1	/*  1clk */
-#define B5_Tacp_250		0x0     /* page mode is not used */
-#define B5_PMC_250		0x0	/* page mode disabled */
-
-/* BANK5CON 266 */
-#define B5_Tacs_266		0x0	/*  0clk */
-#define B5_Tcos_266		0x3	/*  4clk */
-#define B5_Tacc_266		0x5	/*  8clk */
-#define B5_Tcoh_266		0x3	/*  4clk */
-#define B5_Tcah_266		0x1	/*  1clk */
-#define B5_Tacp_266		0x0     /* page mode is not used */
-#define B5_PMC_266		0x0	/* page mode disabled */
-
-#define B6_MT			0x3	/* SDRAM */
-#define B6_Trcd_200		0x0	/* 2clk */
-#define B6_Trcd_250		0x1	/* 3clk */
-#define B6_Trcd_266		0x1	/* 3clk */
-#define B6_SCAN			0x2	/* 10bit */
-
-#define B7_MT			0x3	/* SDRAM */
-#define B7_Trcd_200		0x0	/* 2clk */
-#define B7_Trcd_250		0x1	/* 3clk */
-#define B7_Trcd_266		0x1	/* 3clk */
-#define B7_SCAN			0x2	/* 10bit */
-
-/* REFRESH parameter */
-#define REFEN			0x1	/* Refresh enable */
-#define TREFMD			0x0	/* CBR(CAS before RAS)/Auto refresh */
-#define Trp_200			0x0	/* 2clk */
-#define Trp_250			0x1	/* 3clk */
-#define Trp_266			0x1	/* 3clk */
-#define Tsrc_200		0x1	/* 5clk */
-#define Tsrc_250		0x2	/* 6clk */
-#define Tsrc_266		0x3	/* 7clk */
-
-/* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */
-#define REFCNT_200		489
-/* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */
-#define REFCNT_250		99
-/* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */
-#define REFCNT_266		0
-/**************************************/
-
-.globl lowlevel_init
-lowlevel_init:
-	/* use r0 to relocate DATA read/write to flash rather than memory ! */
-	ldr	r0, =CONFIG_SYS_TEXT_BASE
-	ldr	r13, =BWSCON
-
-	/* enable minimal access to PLD */
-	ldr	r1, [r13]			/* load default BWSCON */
-	orr	r1, r1, #(DW8 + UBLB) << 20	/* set necessary CS attrs */
-	str	r1, [r13]			/* set BWSCON */
-	ldr	r1, =0x7FF0			/* select slowest timing */
-	str	r1, [r13, #0x18]		/* set BANKCON5 */
-
-	ldr	r1, =PLD_BASE
-	ldr	r2, =SETUPDATA
-	ldrb	r1, [r1, #MISC_REG]
-	sub	r2, r2, r0
-	tst	r1, #FASTCPU			/* FASTCPU available ? */
-	addeq	r2, r2, #SETUPENTRY_SIZE
-
-	/* memory control configuration */
-	/* r2 = pointer into timing table */
-	/* r13 = pointer to MEM controller regs (starting with BWSCON) */
-	add     r3, r2, #CSDATA_OFFSET
-	add     r4, r3, #CSDATAENTRY_SIZE
-0:
-	ldr     r1, [r3], #4
-	str     r1, [r13], #4
-	cmp     r3, r4
-	bne     0b
-
-	/* PLD access is now possible */
-	/* r3 = SDRAMDATA */
-	/* r13 = pointer to MEM controller regs */
-	ldr	r1, =PLD_BASE
-	mov	r4, #SDRAMENTRY_SIZE
-	ldrb	r1, [r1, #SDRAM_REG]
-	/* calculate start and end point */
-	mla	r3, r4, r1, r3
-	add     r4, r3, r4
-0:
-	ldr     r1, [r3], #4
-	str     r1, [r13], #4
-	cmp     r3, r4
-	bne     0b
-
-	/* setup MPLL registers */
-	ldr	r1, =CLKBASE
-	ldr	r4, =0xFFFFFF
-	add	r3, r2, #4		/* r3 points to PLL values */
-	str	r4, [r1, #LOCKTIME]
-	ldmia	r3, {r4,r5}
-	str	r5, [r1, #UPLLCON]	/* writing PLL register */
-					/* !! order seems to be important !! */
-	/* a little delay */
-	ldr	r3, =0x4000
-0:
-	subs	r3, r3, #1
-	bne	0b
-
-	str	r4, [r1, #MPLLCON]	/* writing PLL register */
-					/* !! order seems to be important !! */
-	/* a little delay */
-	ldr	r3, =0x4000
-0:
-	subs	r3, r3, #1
-	bne	0b
-
-	/* everything is fine now */
-	mov	pc, lr
-
-	.ltorg
-/* the literal pools origin */
-
-#define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \
-	((bws1) << 4) + \
-	((bws2) << 8) + \
-	((bws3) << 12) + \
-	((bws4) << 16) + \
-	((bws5) << 20) + \
-	((bws6) << 24) + \
-	((bws7) << 28)
-
-#define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \
-	((tacs) << 13) + \
-	((tcos) << 11) + \
-	((tacc) << 8) + \
-	((tcoh) << 6) + \
-	((tcah) << 4) + \
-	((tacp) << 2) + \
-	(pmc)
-
-#define MK_BANKCON_SDRAM(trcd, scan) \
-	((0x03) << 15) + \
-	((trcd) << 2) + \
-	(scan)
-
-#define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \
-	((enable) << 23) + \
-	((trefmd) << 22) + \
-	((trp) << 20) + \
-	((tsrc) << 18) + \
-	(cnt)
-
-SETUPDATA:
-	.word 0x32410002
-	/* PLL values (MDIV, PDIV, SDIV) for 250 MHz */
-	.word (0x75 << 12) + (0x01 << 4) + (0x01 << 0)
-	/* PLL values for USB clock */
-	.word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
-
-	/* timing for 250 MHz*/
-0:
-	.equiv CSDATA_OFFSET, (. - SETUPDATA)
-	.word MK_BWSCON(DW16, \
-			DW32, \
-			DW32, \
-			DW16 + WAIT + UBLB, \
-			DW8 + UBLB, \
-			DW32, \
-			DW32)
-
-	.word MK_BANKCON(B0_Tacs_250, \
-			 B0_Tcos_250, \
-			 B0_Tacc_250, \
-			 B0_Tcoh_250, \
-			 B0_Tcah_250, \
-			 B0_Tacp_250, \
-			 B0_PMC_250)
-
-	.word MK_BANKCON(B1_Tacs_250, \
-			 B1_Tcos_250, \
-			 B1_Tacc_250, \
-			 B1_Tcoh_250, \
-			 B1_Tcah_250, \
-			 B1_Tacp_250, \
-			 B1_PMC_250)
-
-	.word MK_BANKCON(B2_Tacs, \
-			 B2_Tcos, \
-			 B2_Tacc, \
-			 B2_Tcoh, \
-			 B2_Tcah, \
-			 B2_Tacp, \
-			 B2_PMC)
-
-	.word MK_BANKCON(B3_Tacs, \
-			 B3_Tcos, \
-			 B3_Tacc, \
-			 B3_Tcoh, \
-			 B3_Tcah, \
-			 B3_Tacp, \
-			 B3_PMC)
-
-	.word MK_BANKCON(B4_Tacs_250, \
-			 B4_Tcos_250, \
-			 B4_Tacc_250, \
-			 B4_Tcoh_250, \
-			 B4_Tcah_250, \
-			 B4_Tacp_250, \
-			 B4_PMC_250)
-
-	.word MK_BANKCON(B5_Tacs_250, \
-			 B5_Tcos_250, \
-			 B5_Tacc_250, \
-			 B5_Tcoh_250, \
-			 B5_Tcah_250, \
-			 B5_Tacp_250, \
-			 B5_PMC_250)
-
-	.equiv CSDATAENTRY_SIZE, (. - 0b)
-	/* 4Mx8x4 */
-0:
-	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
-	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
-	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
-	.word 0x32 + BURST_EN
-	.word 0x30
-	.word 0x30
-	.equiv SDRAMENTRY_SIZE, (. - 0b)
-
-	/* 8Mx8x4 */
-	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
-	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
-	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
-	.word 0x32 + BURST_EN
-	.word 0x30
-	.word 0x30
-
-	/* 2Mx8x4 */
-	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
-	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
-	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
-	.word 0x32 + BURST_EN
-	.word 0x30
-	.word 0x30
-
-	/* 4Mx8x2 */
-	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
-	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
-	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
-	.word 0x32 + BURST_EN
-	.word 0x30
-	.word 0x30
-
-	.equiv SETUPENTRY_SIZE, (. - SETUPDATA)
-
-	.word 0x32410000
-	/* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */
-	.word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0)
-	/* PLL values for USB clock */
-	.word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
-
-	/* timing for 200 MHz and default*/
-	.word MK_BWSCON(DW16, \
-			DW32, \
-			DW32, \
-			DW16 + WAIT + UBLB, \
-			DW8 + UBLB, \
-			DW32, \
-			DW32)
-
-	.word MK_BANKCON(B0_Tacs_200, \
-			 B0_Tcos_200, \
-			 B0_Tacc_200, \
-			 B0_Tcoh_200, \
-			 B0_Tcah_200, \
-			 B0_Tacp_200, \
-			 B0_PMC_200)
-
-	.word MK_BANKCON(B1_Tacs_200, \
-			 B1_Tcos_200, \
-			 B1_Tacc_200, \
-			 B1_Tcoh_200, \
-			 B1_Tcah_200, \
-			 B1_Tacp_200, \
-			 B1_PMC_200)
-
-	.word MK_BANKCON(B2_Tacs, \
-			 B2_Tcos, \
-			 B2_Tacc, \
-			 B2_Tcoh, \
-			 B2_Tcah, \
-			 B2_Tacp, \
-			 B2_PMC)
-
-	.word MK_BANKCON(B3_Tacs, \
-			 B3_Tcos, \
-			 B3_Tacc, \
-			 B3_Tcoh, \
-			 B3_Tcah, \
-			 B3_Tacp, \
-			 B3_PMC)
-
-	.word MK_BANKCON(B4_Tacs_200, \
-			 B4_Tcos_200, \
-			 B4_Tacc_200, \
-			 B4_Tcoh_200, \
-			 B4_Tcah_200, \
-			 B4_Tacp_200, \
-			 B4_PMC_200)
-
-	.word MK_BANKCON(B5_Tacs_200, \
-			 B5_Tcos_200, \
-			 B5_Tacc_200, \
-			 B5_Tcoh_200, \
-			 B5_Tcah_200, \
-			 B5_Tacp_200, \
-			 B5_PMC_200)
-
-	/* 4Mx8x4 */
-	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
-	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
-	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
-	.word 0x32 + BURST_EN
-	.word 0x30
-	.word 0x30
-
-	/* 8Mx8x4 */
-	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
-	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
-	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
-	.word 0x32 + BURST_EN
-	.word 0x30
-	.word 0x30
-
-	/* 2Mx8x4 */
-	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
-	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
-	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
-	.word 0x32 + BURST_EN
-	.word 0x30
-	.word 0x30
-
-	/* 4Mx8x2 */
-	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
-	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
-	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
-	.word 0x32 + BURST_EN
-	.word 0x30
-	.word 0x30
-
-	.equiv SETUPDATA_SIZE, (. - SETUPDATA)
diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c
deleted file mode 100644
index 43a3d47..0000000
--- a/board/mpl/vcma9/vcma9.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002, 2010
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <i2c.h>
-#include <asm/io.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-#include "vcma9.h"
-#include "../common/common_util.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_early_init_f(void)
-{
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	/* set up the I/O ports */
-	writel(0x007FFFFF, &gpio->gpacon);
-	writel(0x002AAAAA, &gpio->gpbcon);
-	writel(0x000002BF, &gpio->gpbup);
-	writel(0xAAAAAAAA, &gpio->gpccon);
-	writel(0x0000FFFF, &gpio->gpcup);
-	writel(0xAAAAAAAA, &gpio->gpdcon);
-	writel(0x0000FFFF, &gpio->gpdup);
-	writel(0xAAAAAAAA, &gpio->gpecon);
-	writel(0x000037F7, &gpio->gpeup);
-	writel(0x00000000, &gpio->gpfcon);
-	writel(0x00000000, &gpio->gpfup);
-	writel(0xFFEAFF5A, &gpio->gpgcon);
-	writel(0x0000F0DC, &gpio->gpgup);
-	writel(0x0028AAAA, &gpio->gphcon);
-	writel(0x00000656, &gpio->gphup);
-
-	/* setup correct IRQ modes for NIC (rising edge mode) */
-	writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8),  &gpio->extint2);
-
-	/* select USB port 2 to be host or device (setup as host for now) */
-	writel(readl(&gpio->misccr) | 0x08, &gpio->misccr);
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x30000100;
-
-	icache_enable();
-	dcache_enable();
-
-	return 0;
-}
-
-/*
- * Get some Board/PLD Info
- */
-
-static u8 get_pld_reg(enum vcma9_pld_regs reg)
-{
-	return readb(VCMA9_PLD_BASE + reg);
-}
-
-static u8 get_pld_version(void)
-{
-	return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F;
-}
-
-static u8 get_pld_revision(void)
-{
-	return get_pld_reg(VCMA9_PLD_ID) & 0x0F;
-}
-
-static uchar get_board_pcb(void)
-{
-	return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A';
-}
-
-static u8 get_nr_chips(void)
-{
-	switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) {
-		case 0: return 4;
-		case 1: return 1;
-		case 2: return 2;
-		default: return 0;
-	}
-}
-
-static ulong get_chip_size(void)
-{
-	switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) {
-		case 0: return 16 * (1024*1024);
-		case 1: return 32 * (1024*1024);
-		case 2: return  8 * (1024*1024);
-		case 3: return  8 * (1024*1024);
-		default: return 0;
-	}
-}
-
-static const char *get_chip_geom(void)
-{
-	switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) {
-		case 0: return "4Mx8x4";
-		case 1: return "8Mx8x4";
-		case 2: return "2Mx8x4";
-		case 3: return "4Mx8x2";
-		default: return "unknown";
-	}
-}
-
-static void vcma9_show_info(char *board_name, char *serial)
-{
-	printf("Board: %s SN: %s  PCB Rev: %c PLD(%d,%d)\n",
-		board_name, serial,
-		get_board_pcb(), get_pld_version(), get_pld_revision());
-	printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom());
-}
-
-int dram_init(void)
-{
-	/* dram_init must store complete ramsize in gd->ram_size */
-	gd->ram_size = get_chip_size() * get_nr_chips();
-	return 0;
-}
-
-/*
- * Check Board Identity:
- */
-
-int checkboard(void)
-{
-	char s[50];
-	int i;
-	backup_t *b = (backup_t *) s;
-
-	i = getenv_f("serial#", s, 32);
-	if ((i < 0) || strncmp (s, "VCMA9", 5)) {
-		get_backup_values (b);
-		if (strncmp (b->signature, "MPL\0", 4) != 0) {
-			puts ("### No HW ID - assuming VCMA9");
-		} else {
-			b->serial_name[5] = 0;
-			vcma9_show_info(b->serial_name, &b->serial_name[6]);
-		}
-	} else {
-		s[5] = 0;
-		vcma9_show_info(s, &s[6]);
-	}
-
-	return 0;
-}
-
-int board_late_init(void)
-{
-	/*
-	 * check if environment is healthy, otherwise restore values
-	 * from shadow copy
-	 */
-	check_env();
-	return 0;
-}
-
-void vcma9_print_info(void)
-{
-	char *s = getenv("serial#");
-
-	if (!s) {
-		puts ("### No HW ID - assuming VCMA9");
-	} else {
-		s[5] = 0;
-		vcma9_show_info(s, &s[6]);
-	}
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_CS8900
-	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
-#endif
-	return rc;
-}
-#endif
-
-/*
- * Hardcoded flash setup:
- * Flash 0 is a non-CFI AMD AM29F400BB flash.
- */
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
-	info->portwidth = FLASH_CFI_16BIT;
-	info->chipwidth = FLASH_CFI_BY16;
-	info->interface = FLASH_CFI_X16;
-	return 1;
-}
diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h
deleted file mode 100644
index c585c8e..0000000
--- a/board/mpl/vcma9/vcma9.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2002, 2003
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
- /****************************************************************************
- * Global routines used for VCMA9
- *****************************************************************************/
-
-#include <asm/arch/s3c24x0_cpu.h>
-
-extern void vcma9_print_info(void);
-extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag,
-			int argc, char *const argv[]);
-
-/* VCMA9 PLD registers */
-enum vcma9_pld_regs {
-	VCMA9_PLD_ID,
-	VCMA9_PLD_NIC,
-	VCMA9_PLD_CAN,
-	VCMA9_PLD_MISC,
-	VCMA9_PLD_GPCD,
-	VCMA9_PLD_BOARD,
-	VCMA9_PLD_SDRAM
-};
-
-#define VCMA9_PLD_BASE	(0x2C000100)
diff --git a/board/mpr2/Makefile b/board/mpr2/Makefile
index b6cdeb4..0cb1dd6 100644
--- a/board/mpr2/Makefile
+++ b/board/mpr2/Makefile
@@ -16,4 +16,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y	:= mpr2.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/mpr2/mpr2.c b/board/mpr2/mpr2.c
index 7449e03..3788a39 100644
--- a/board/mpr2/mpr2.c
+++ b/board/mpr2/mpr2.c
@@ -11,8 +11,6 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 int checkboard(void)
 {
 	puts("BOARD: MPR2\n");
@@ -138,11 +136,3 @@ int board_init(void)
 
 	return 0;
 }
-
-int dram_init(void)
-{
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("SDRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-	return 0;
-}
diff --git a/board/mqmaker/miqi_rk3288/Kconfig b/board/mqmaker/miqi_rk3288/Kconfig
new file mode 100644
index 0000000..232a112
--- /dev/null
+++ b/board/mqmaker/miqi_rk3288/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_MIQI_RK3288
+
+config SYS_BOARD
+	default "miqi_rk3288"
+
+config SYS_VENDOR
+	default "mqmaker"
+
+config SYS_CONFIG_NAME
+	default "miqi_rk3288"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/mqmaker/miqi_rk3288/MAINTAINERS b/board/mqmaker/miqi_rk3288/MAINTAINERS
new file mode 100644
index 0000000..053a5e6
--- /dev/null
+++ b/board/mqmaker/miqi_rk3288/MAINTAINERS
@@ -0,0 +1,6 @@
+MIQI
+M:	Jernej Skrabec <jernej.skrabec@siol.net>
+S:	Maintained
+F:	board/mqmaker/miqi_rk3288
+F:	include/configs/miqi_rk3288.h
+F:	configs/miqi-rk3288_defconfig
diff --git a/board/mqmaker/miqi_rk3288/Makefile b/board/mqmaker/miqi_rk3288/Makefile
new file mode 100644
index 0000000..ec95aff
--- /dev/null
+++ b/board/mqmaker/miqi_rk3288/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= miqi-rk3288.o
diff --git a/board/mqmaker/miqi_rk3288/miqi-rk3288.c b/board/mqmaker/miqi_rk3288/miqi-rk3288.c
new file mode 100644
index 0000000..a82f0ae
--- /dev/null
+++ b/board/mqmaker/miqi_rk3288/miqi-rk3288.c
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	/* eMMC prior to sdcard. */
+	spl_boot_list[0] = BOOT_DEVICE_MMC2;
+	spl_boot_list[1] = BOOT_DEVICE_MMC1;
+}
diff --git a/board/ms7720se/Makefile b/board/ms7720se/Makefile
index 1819c4c..66c25fa 100644
--- a/board/ms7720se/Makefile
+++ b/board/ms7720se/Makefile
@@ -13,4 +13,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y	:= ms7720se.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/ms7720se/ms7720se.c b/board/ms7720se/ms7720se.c
index 534a422..48edcc6 100644
--- a/board/ms7720se/ms7720se.c
+++ b/board/ms7720se/ms7720se.c
@@ -17,8 +17,6 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #define LED_BASE	0xB0800000
 
 int checkboard(void)
@@ -32,14 +30,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-	return 0;
-}
-
 void led_set_state(unsigned short value)
 {
 	outw(value & 0xFF, LED_BASE);
diff --git a/board/ms7722se/Makefile b/board/ms7722se/Makefile
index 9f7af78..808d459 100644
--- a/board/ms7722se/Makefile
+++ b/board/ms7722se/Makefile
@@ -10,4 +10,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y	:= ms7722se.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/ms7722se/ms7722se.c b/board/ms7722se/ms7722se.c
index ee1e99c..869b415 100644
--- a/board/ms7722se/ms7722se.c
+++ b/board/ms7722se/ms7722se.c
@@ -15,8 +15,6 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #define LED_BASE	0xB0800000
 
 int checkboard(void)
@@ -33,14 +31,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-	return 0;
-}
-
 void led_set_state(unsigned short value)
 {
 	writew(value & 0xFF, LED_BASE);
diff --git a/board/ms7750se/Makefile b/board/ms7750se/Makefile
index a8e3ca0..a010e32 100644
--- a/board/ms7750se/Makefile
+++ b/board/ms7750se/Makefile
@@ -6,4 +6,4 @@
 #
 
 obj-y	:= ms7750se.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/ms7750se/ms7750se.c b/board/ms7750se/ms7750se.c
index a7f9346..d252faa 100644
--- a/board/ms7750se/ms7750se.c
+++ b/board/ms7750se/ms7750se.c
@@ -8,8 +8,6 @@
 #include <common.h>
 #include <asm/processor.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 int checkboard(void)
 {
 	puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n");
@@ -21,14 +19,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init (void)
-{
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-	return 0;
-}
-
 int board_late_init(void)
 {
 	return 0;
diff --git a/board/munices/Kconfig b/board/munices/Kconfig
deleted file mode 100644
index 019aaae..0000000
--- a/board/munices/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_MUNICES
-
-config SYS_BOARD
-	default "munices"
-
-config SYS_CONFIG_NAME
-	default "munices"
-
-endif
diff --git a/board/munices/MAINTAINERS b/board/munices/MAINTAINERS
deleted file mode 100644
index 50d3e7e..0000000
--- a/board/munices/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MUNICES BOARD
-#M:	-
-S:	Maintained
-F:	board/munices/
-F:	include/configs/munices.h
-F:	configs/munices_defconfig
diff --git a/board/munices/Makefile b/board/munices/Makefile
deleted file mode 100644
index d16e2a1..0000000
--- a/board/munices/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= munices.o
diff --git a/board/munices/mt48lc16m16a2-75.h b/board/munices/mt48lc16m16a2-75.h
deleted file mode 100644
index 0133eaa..0000000
--- a/board/munices/mt48lc16m16a2-75.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	0		/* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/munices/munices.c b/board/munices/munices.c
deleted file mode 100644
index 8f292ea..0000000
--- a/board/munices/munices.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * (C) Copyright 2007
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-
-#include "mt48lc16m16a2-75.h"
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-#endif
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *            is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR && SDRAM_TAPDELAY
-	/* set tap delay */
-	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
-	sdram_start(1);
-	test2 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
-	if (dramsize2 >= 0x13) {
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	} else {
-		dramsize2 = 0;
-	}
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	return dramsize + dramsize2;
-}
-
-int checkboard (void)
-{
-	puts ("Board: MUNICes\n");
-	return 0;
-}
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/netgear/cg3100d/Kconfig b/board/netgear/cg3100d/Kconfig
new file mode 100644
index 0000000..632c22d
--- /dev/null
+++ b/board/netgear/cg3100d/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_NETGEAR_CG3100D
+
+config SYS_BOARD
+	default "cg3100d"
+
+config SYS_VENDOR
+	default "netgear"
+
+config SYS_CONFIG_NAME
+	default "netgear_cg3100d"
+
+endif
diff --git a/board/netgear/cg3100d/MAINTAINERS b/board/netgear/cg3100d/MAINTAINERS
new file mode 100644
index 0000000..f1dcb1f
--- /dev/null
+++ b/board/netgear/cg3100d/MAINTAINERS
@@ -0,0 +1,6 @@
+NETGEAR CG3100D BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/netgear/cg3100d/
+F:	include/configs/netgear_cg3100d.h
+F:	configs/netgear_cg3100d_ram_defconfig
diff --git a/board/netgear/cg3100d/Makefile b/board/netgear/cg3100d/Makefile
new file mode 100644
index 0000000..b82e59e
--- /dev/null
+++ b/board/netgear/cg3100d/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += cg3100d.o
diff --git a/board/netgear/cg3100d/cg3100d.c b/board/netgear/cg3100d/cg3100d.c
new file mode 100644
index 0000000..d181ca6
--- /dev/null
+++ b/board/netgear/cg3100d/cg3100d.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c
index f04f843..2ad9962 100644
--- a/board/nvidia/cardhu/cardhu.c
+++ b/board/nvidia/cardhu/cardhu.c
@@ -33,7 +33,7 @@ void pinmux_init(void)
 	pinmux_config_drvgrp_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl));
 }
 
-#if defined(CONFIG_TEGRA_MMC)
+#if defined(CONFIG_MMC_SDHCI_TEGRA)
 /*
  * Do I2C/PMU writes to bring up SD card bus power
  *
diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c
index e4c4bfb..cb9282e 100644
--- a/board/nvidia/dalmore/dalmore.c
+++ b/board/nvidia/dalmore/dalmore.c
@@ -34,7 +34,7 @@ void pinmux_init(void)
 		ARRAY_SIZE(dalmore_padctrl));
 }
 
-#if defined(CONFIG_TEGRA_MMC)
+#if defined(CONFIG_MMC_SDHCI_TEGRA)
 /*
  * Do I2C/PMU writes to bring up SD card bus power
  *
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
index c892a25..2945785 100644
--- a/board/nvidia/harmony/harmony.c
+++ b/board/nvidia/harmony/harmony.c
@@ -14,7 +14,7 @@
 #include <asm/arch/tegra.h>
 #include <asm/gpio.h>
 
-#ifdef CONFIG_TEGRA_MMC
+#ifdef CONFIG_MMC_SDHCI_TEGRA
 /*
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c
index a66b710..bd08a2e 100644
--- a/board/nvidia/jetson-tk1/jetson-tk1.c
+++ b/board/nvidia/jetson-tk1/jetson-tk1.c
@@ -6,7 +6,9 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <power/as3722.h>
+#include <power/pmic.h>
 
 #include <asm/arch/gpio.h>
 #include <asm/arch/pinmux.h>
@@ -37,27 +39,45 @@ void pinmux_init(void)
 }
 
 #ifdef CONFIG_PCI_TEGRA
-int tegra_pcie_board_init(void)
+/* TODO: Convert to driver model */
+static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
 {
-	struct udevice *pmic;
 	int err;
 
-	err = as3722_init(&pmic);
+	if (sd > 6)
+		return -EINVAL;
+
+	err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
 	if (err) {
-		error("failed to initialize AS3722 PMIC: %d\n", err);
+		error("failed to update SD control register: %d", err);
 		return err;
 	}
 
-	err = as3722_sd_enable(pmic, 4);
-	if (err < 0) {
-		error("failed to enable SD4: %d\n", err);
-		return err;
+	return 0;
+}
+
+int tegra_pcie_board_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = uclass_get_device_by_driver(UCLASS_PMIC,
+					  DM_GET_DRIVER(pmic_as3722), &dev);
+	if (ret) {
+		debug("%s: Failed to find PMIC\n", __func__);
+		return ret;
 	}
 
-	err = as3722_sd_set_voltage(pmic, 4, 0x24);
-	if (err < 0) {
-		error("failed to set SD4 voltage: %d\n", err);
-		return err;
+	ret = as3722_sd_enable(dev, 4);
+	if (ret < 0) {
+		error("failed to enable SD4: %d\n", ret);
+		return ret;
+	}
+
+	ret = as3722_sd_set_voltage(dev, 4, 0x24);
+	if (ret < 0) {
+		error("failed to set SD4 voltage: %d\n", ret);
+		return ret;
 	}
 
 	return 0;
diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c
index 8f68ae9..54acf54 100644
--- a/board/nvidia/nyan-big/nyan-big.c
+++ b/board/nvidia/nyan-big/nyan-big.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
@@ -46,20 +47,23 @@ int tegra_board_id(void)
 
 int tegra_lcd_pmic_init(int board_id)
 {
-	struct udevice *pmic;
+	struct udevice *dev;
 	int ret;
 
-	ret = as3722_get(&pmic);
-	if (ret)
-		return -ENOENT;
+	ret = uclass_get_device_by_driver(UCLASS_PMIC,
+					  DM_GET_DRIVER(pmic_as3722), &dev);
+	if (ret) {
+		debug("%s: Failed to find PMIC\n", __func__);
+		return ret;
+	}
 
 	if (board_id == 0)
-		as3722_write(pmic, 0x00, 0x3c);
+		pmic_reg_write(dev, 0x00, 0x3c);
 	else
-		as3722_write(pmic, 0x00, 0x50);
-	as3722_write(pmic, 0x12, 0x10);
-	as3722_write(pmic, 0x0c, 0x07);
-	as3722_write(pmic, 0x20, 0x10);
+		pmic_reg_write(dev, 0x00, 0x50);
+	pmic_reg_write(dev, 0x12, 0x10);
+	pmic_reg_write(dev, 0x0c, 0x07);
+	pmic_reg_write(dev, 0x20, 0x10);
 
 	return 0;
 }
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index fc9c1c9..0d5eec9 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -7,6 +7,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/mach-types.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch/clock.h>
@@ -25,7 +26,7 @@ void gpio_early_init_uart(void)
 }
 #endif
 
-#ifdef CONFIG_TEGRA_MMC
+#ifdef CONFIG_MMC_SDHCI_TEGRA
 /*
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
@@ -44,6 +45,12 @@ void pin_mux_mmc(void)
 
 void pin_mux_usb(void)
 {
-	/* For USB's GPIO PD0. For now, since we have no pinmux in fdt */
+	/* For USB0's GPIO PD0. For now, since we have no pinmux in fdt */
 	pinmux_tristate_disable(PMUX_PINGRP_SLXK);
+	/* For USB1's ULPI signals */
+	funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
+	pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+	pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
+	/* USB1 PHY reset GPIO */
+	pinmux_tristate_disable(PMUX_PINGRP_UAC);
 }
diff --git a/board/nvidia/whistler/Kconfig b/board/nvidia/whistler/Kconfig
deleted file mode 100644
index 5febc07..0000000
--- a/board/nvidia/whistler/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_WHISTLER
-
-config SYS_BOARD
-	default "whistler"
-
-config SYS_VENDOR
-	default "nvidia"
-
-config SYS_CONFIG_NAME
-	default "whistler"
-
-endif
diff --git a/board/nvidia/whistler/MAINTAINERS b/board/nvidia/whistler/MAINTAINERS
deleted file mode 100644
index 66e2c8d..0000000
--- a/board/nvidia/whistler/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-WHISTLER BOARD
-M:	Tom Warren <twarren@nvidia.com>
-M:	Stephen Warren <swarren@nvidia.com>
-S:	Maintained
-F:	board/nvidia/whistler/
-F:	include/configs/whistler.h
-F:	configs/whistler_defconfig
diff --git a/board/nvidia/whistler/Makefile b/board/nvidia/whistler/Makefile
deleted file mode 100644
index b54c5fd..0000000
--- a/board/nvidia/whistler/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-#  (C) Copyright 2010-2012
-#  NVIDIA Corporation <www.nvidia.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= whistler.o
diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c
deleted file mode 100644
index 3476f11..0000000
--- a/board/nvidia/whistler/whistler.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *  (C) Copyright 2010-2012
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/io.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/pinmux.h>
-#include <asm/gpio.h>
-#include <i2c.h>
-
-#ifdef CONFIG_TEGRA_MMC
-/*
- * Routine: pin_mux_mmc
- * Description: setup the pin muxes/tristate values for the SDMMC(s)
- */
-void pin_mux_mmc(void)
-{
-	struct udevice *dev;
-	uchar val;
-	int ret;
-
-	/* Turn on MAX8907B LDO12 to 2.8V for J40 power */
-	ret = i2c_get_chip_for_busnum(0, 0x3c, 1, &dev);
-	if (ret) {
-		printf("%s: Cannot find MAX8907B I2C chip\n", __func__);
-		return;
-	}
-	val = 0x29;
-	ret = dm_i2c_write(dev, 0x46, &val, 1);
-	if (ret)
-		printf("i2c_write 0 0x3c 0x46 failed: %d\n", ret);
-	val = 0x00;
-	ret = dm_i2c_write(dev, 0x45, &val, 1);
-	if (ret)
-		printf("i2c_write 0 0x3c 0x45 failed: %d\n", ret);
-	val = 0x1f;
-	ret = dm_i2c_write(dev, 0x44, &val, 1);
-	if (ret)
-		printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret);
-
-	funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT);
-	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT);
-}
-#endif
-
-/* this is a weak define that we are overriding */
-void pin_mux_usb(void)
-{
-	struct udevice *dev;
-	uchar val;
-	int ret;
-
-	/*
-	 * This is a hack. This should be represented in DT using the
-	 * vbus-gpio property. However, U-Boot's DT support doesn't
-	 * support any GPIO controller other than the Tegra's yet.
-	 */
-
-	/* Turn on TAC6416's GPIO 0+1 for USB1/3's VBUS */
-	ret = i2c_get_chip_for_busnum(0, 0x20, 1, &dev);
-	if (ret) {
-		printf("%s: Cannot find TAC6416 I2C chip\n", __func__);
-		return;
-	}
-	val = 0x03;
-	ret = dm_i2c_write(dev, 2, &val, 1);
-	if (ret)
-		printf("i2c_write 0 0x20 2 failed: %d\n", ret);
-	val = 0xfc;
-	ret = dm_i2c_write(dev, 6, &val, 1);
-	if (ret)
-		printf("i2c_write 0 0x20 6 failed: %d\n", ret);
-}
diff --git a/board/olimex/mx23_olinuxino/mx23_olinuxino.c b/board/olimex/mx23_olinuxino/mx23_olinuxino.c
index 65cbbf1..f05fd0a 100644
--- a/board/olimex/mx23_olinuxino/mx23_olinuxino.c
+++ b/board/olimex/mx23_olinuxino/mx23_olinuxino.c
@@ -13,7 +13,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
-#ifdef CONFIG_STATUS_LED
+#ifdef CONFIG_LED_STATUS
 #include <status_led.h>
 #endif
 
@@ -72,8 +72,8 @@ int board_init(void)
 	/* Adress of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
-#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
-	status_led_set(STATUS_LED_BOOT, STATUS_LED_STATE);
+#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
+	status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_STATE);
 #endif
 
 	return 0;
diff --git a/board/omicron/calimain/MAINTAINERS b/board/omicron/calimain/MAINTAINERS
index f6e37a2..ad788a6 100644
--- a/board/omicron/calimain/MAINTAINERS
+++ b/board/omicron/calimain/MAINTAINERS
@@ -1,6 +1,6 @@
 CALIMAIN BOARD
-M:	Manfred Rudigier <manfred.rudigier@omicron.at>
-M:	Christian Riesch <christian.riesch@omicron.at>
+M:	Manfred Rudigier <manfred.rudigier@omicronenergy.com>
+M:	Christoph Rüdisser <christoph.ruedisser@omicronenergy.com>
 S:	Maintained
 F:	board/omicron/calimain/
 F:	include/configs/calimain.h
diff --git a/board/omicron/calimain/calimain.c b/board/omicron/calimain/calimain.c
index 32f2b20..80a142e 100644
--- a/board/omicron/calimain/calimain.c
+++ b/board/omicron/calimain/calimain.c
@@ -100,9 +100,7 @@ int board_init(void)
 {
 	int val;
 
-#ifndef CONFIG_USE_IRQ
 	irq_init();
-#endif
 
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
diff --git a/board/openrisc/openrisc-generic/Kconfig b/board/openrisc/openrisc-generic/Kconfig
deleted file mode 100644
index cd2a94f..0000000
--- a/board/openrisc/openrisc-generic/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OPENRISC_GENERIC
-
-config SYS_BOARD
-	default "openrisc-generic"
-
-config SYS_VENDOR
-	default "openrisc"
-
-config SYS_CONFIG_NAME
-	default "openrisc-generic"
-
-endif
diff --git a/board/openrisc/openrisc-generic/MAINTAINERS b/board/openrisc/openrisc-generic/MAINTAINERS
deleted file mode 100644
index c8dbc74..0000000
--- a/board/openrisc/openrisc-generic/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-OPENRISC-GENERIC BOARD
-M:	Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
-S:	Maintained
-F:	board/openrisc/openrisc-generic/
-F:	include/configs/openrisc-generic.h
-F:	configs/openrisc-generic_defconfig
diff --git a/board/openrisc/openrisc-generic/Makefile b/board/openrisc/openrisc-generic/Makefile
deleted file mode 100644
index 342bc80..0000000
--- a/board/openrisc/openrisc-generic/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= openrisc-generic.o
diff --git a/board/openrisc/openrisc-generic/config.mk b/board/openrisc/openrisc-generic/config.mk
deleted file mode 100644
index dd6595f..0000000
--- a/board/openrisc/openrisc-generic/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2011, Julius Baxter <julius@opencores.org>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mhard-mul -mhard-div
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
diff --git a/board/openrisc/openrisc-generic/openrisc-generic.c b/board/openrisc/openrisc-generic/openrisc-generic.c
deleted file mode 100644
index 4f82600..0000000
--- a/board/openrisc/openrisc-generic/openrisc-generic.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Based on nios2-generic.c:
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-int board_early_init_f(void)
-{
-	return 0;
-}
-
-int checkboard(void)
-{
-	printf("BOARD: %s\n", CONFIG_BOARD_NAME);
-	return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
-	return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-
-#ifdef CONFIG_ETHOC
-	rc += ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/board/openrisc/openrisc-generic/or1ksim.cfg b/board/openrisc/openrisc-generic/or1ksim.cfg
deleted file mode 100644
index 2bd8642..0000000
--- a/board/openrisc/openrisc-generic/or1ksim.cfg
+++ /dev/null
@@ -1,871 +0,0 @@
-/* sim.cfg -- Simulator configuration script file
-   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
-
-This file is part of OpenRISC 1000 Architectural Simulator.
-It contains the default configuration and help about configuring
-the simulator.
-
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-/* INTRODUCTION
-
-   The ork1sim has various parameters, that are set in configuration files
-   like this one. The user can switch between configurations at startup by
-   specifying the required configuration file with the -f <filename.cfg> option.
-   If no configuration file is specified or1ksim searches for the default
-   configuration file sim.cfg. First it searches for './sim.cfg'. If this
-   file is not found, it searches for '~/or1k/sim.cfg'. If this file is
-   not found too, it reverts to the built-in default configuration.
-
-   NOTE: Users should not rely on the built-in configuration, since the
-	 default configuration may differ between version.
-	 Rather create a configuration file that sets all critical values.
-
-   This file may contain (standard C) comments only - no // support.
-
-   Configure files may be be included, using:
-   include "file_name_to_include"
-
-   Like normal configuration files, the included file is divided into
-   sections. Each section is described in detail also.
-
-   Some section have subsections. One example of such a subsection is:
-
-   device <index>
-     instance specific parameters...
-   enddevice
-
-   which creates a device instance.
-*/
-
-
-/* MEMORY SECTION
-
-   This section specifies how the memory is generated and the blocks
-   it consists of.
-
-   type = random/unknown/pattern
-      Specifies the initial memory values.
-      'random' generates random memory using seed 'random_seed'.
-      'pattern' fills memory with 'pattern'.
-      'unknown' does not specify how memory should be generated,
-      leaving the memory in a undefined state. This is the fastest
-      option.
-
-   random_seed = <value>
-      random seed for randomizer, used if type = 'random'.
-
-   pattern = <value>
-      pattern to fill memory, used if type = 'pattern'.
-
-   nmemories = <value>
-      number of memory instances connected
-
-   baseaddr = <hex_value>
-      memory start address
-
-   size = <hex_value>
-      memory size
-
-   name = "<string>"
-      memory block name
-
-   ce = <value>
-      chip enable index of the memory instance
-
-   mc = <value>
-      memory controller this memory is connected to
-
-   delayr = <value>
-      cycles, required for read access, -1 if instance does not support reading
-
-   delayw = <value>
-      cycles, required for write access, -1 if instance does not support writing
-
-   log = "<filename>"
-      filename, where to log memory accesses to, no log, if log command is not specified
-*/
-
-
-section memory
-  pattern = 0x00
-  type = unknown /* Fastest */
-
-  name = "FLASH"
-  ce = 0
-  mc = 0
-  baseaddr = 0xf0000000
-  size = 0x01000000
-  delayr =  1
-  delayw = -1
-end
-
-section memory
-  pattern = 0x00
-  type = unknown /* Fastest */
-
-  name = "RAM"
-  ce = 1
-  mc = 0
-  baseaddr = 0x00000000
-  size = 0x02000000
-  delayr = 1
-  delayw = 1
-end
-
-section memory
-  pattern = 0x00
-  type = unknown /* Fastest */
-
-  name = "SRAM"
-  mc = 0
-  ce = 2
-  baseaddr = 0xa4000000
-  size = 0x00100000
-  delayr = 1
-  delayw = 2
-end
-
-
-/* IMMU SECTION
-
-    This section configures the Instruction Memory Manangement Unit
-
-    enabled = 0/1
-       '0': disabled
-       '1': enabled
-       (NOTE: UPR bit is set)
-
-    nsets = <value>
-       number of ITLB sets; must be power of two
-
-    nways = <value>
-       number of ITLB ways
-
-    pagesize = <value>
-       instruction page size; must be power of two
-
-    entrysize = <value>
-       instruction entry size in bytes
-
-    ustates = <value>
-       number of ITLB usage states (2, 3, 4 etc., max is 4)
-
-    hitdelay = <value>
-       number of cycles immu hit costs
-
-    missdelay = <value>
-       number of cycles immu miss costs
-*/
-
-section immu
-  enabled = 1
-  nsets = 64
-  nways = 1
-  pagesize = 8192
-  hitdelay = 0
-  missdelay = 0
-end
-
-
-/* DMMU SECTION
-
-    This section configures the Data Memory Manangement Unit
-
-    enabled = 0/1
-       '0': disabled
-       '1': enabled
-       (NOTE: UPR bit is set)
-
-    nsets = <value>
-       number of DTLB sets; must be power of two
-
-    nways = <value>
-       number of DTLB ways
-
-    pagesize = <value>
-       data page size; must be power of two
-
-    entrysize = <value>
-       data entry size in bytes
-
-    ustates = <value>
-       number of DTLB usage states (2, 3, 4 etc., max is 4)
-
-    hitdelay = <value>
-       number of cycles dmmu hit costs
-
-    missdelay = <value>
-       number of cycles dmmu miss costs
-*/
-
-section dmmu
-  enabled = 1
-  nsets = 64
-  nways = 1
-  pagesize = 8192
-  hitdelay = 0
-  missdelay = 0
-end
-
-
-/* IC SECTION
-
-   This section configures the Instruction Cache
-
-   enabled = 0/1
-       '0': disabled
-       '1': enabled
-      (NOTE: UPR bit is set)
-
-   nsets = <value>
-      number of IC sets; must be power of two
-
-   nways = <value>
-      number of IC ways
-
-   blocksize = <value>
-      IC block size in bytes; must be power of two
-
-   ustates = <value>
-      number of IC usage states (2, 3, 4 etc., max is 4)
-
-   hitdelay = <value>
-      number of cycles ic hit costs
-
-    missdelay = <value>
-      number of cycles ic miss costs
-*/
-
-section ic
-  enabled = 1
-  nsets = 512
-  nways = 1
-  blocksize = 16
-  hitdelay = 1
-  missdelay = 1
-end
-
-
-/* DC SECTION
-
-   This section configures the Data Cache
-
-   enabled = 0/1
-       '0': disabled
-       '1': enabled
-      (NOTE: UPR bit is set)
-
-   nsets = <value>
-      number of DC sets; must be power of two
-
-   nways = <value>
-      number of DC ways
-
-   blocksize = <value>
-      DC block size in bytes; must be power of two
-
-   ustates = <value>
-      number of DC usage states (2, 3, 4 etc., max is 4)
-
-   load_hitdelay = <value>
-      number of cycles dc load hit costs
-
-   load_missdelay = <value>
-      number of cycles dc load miss costs
-
-   store_hitdelay = <value>
-      number of cycles dc load hit costs
-
-   store_missdelay = <value>
-      number of cycles dc load miss costs
-*/
-
-section dc
-  enabled = 1
-  nsets = 512
-  nways = 1
-  blocksize = 16
-  load_hitdelay = 1
-  load_missdelay = 1
-  store_hitdelay = 1
-  store_missdelay = 1
-end
-
-
-/* SIM SECTION
-
-  This section specifies how or1ksim should behave.
-
-  verbose = 0/1
-       '0': don't print extra messages
-       '1': print extra messages
-
-  debug = 0-9
-      0  : no debug messages
-      1-9: debug message level.
-	   higher numbers produce more messages
-
-  profile = 0/1
-      '0': don't generate profiling file 'sim.profile'
-      '1': don't generate profiling file 'sim.profile'
-
-  prof_fn = "<filename>"
-      optional filename for the profiling file.
-      valid only if 'profile' is set
-
-  mprofile = 0/1
-      '0': don't generate memory profiling file 'sim.mprofile'
-      '1': generate memory profiling file 'sim.mprofile'
-
-  mprof_fn = "<filename>"
-      optional filename for the memory profiling file.
-      valid only if 'mprofile' is set
-
-  history = 0/1
-      '0': don't track execution flow
-      '1': track execution flow
-      Execution flow can be tracked for the simulator's
-      'hist' command. Useful for back-trace debugging.
-
-  iprompt = 0/1
-     '0': start in <not interactive prompt> (so what do we start in ???)
-     '1': start in interactive prompt.
-
-  exe_log = 0/1
-      '0': don't generate execution log.
-      '1': generate execution log.
-
-  exe_log = default/hardware/simple/software
-      type of execution log, default is used when not specified
-
-  exe_log_start = <value>
-      index of first instruction to start logging, default = 0
-
-  exe_log_end = <value>
-      index of last instruction to end logging; not limited, if omitted
-
-  exe_log_marker = <value>
-      <value> specifies number of instructions before horizontal marker is
-      printed; if zero, markers are disabled (default)
-
-  exe_log_fn = "<filename>"
-      filename for the exection log file.
-      valid only if 'exe_log' is set
-
-  clkcycle = <value>[ps|ns|us|ms]
-      specifies time measurement for one cycle
-*/
-
-section sim
-  verbose = 1
-  debug = 0
-  profile = 0
-  history = 0
-
-  clkcycle = 10ns
-end
-
-
-/* SECTION VAPI
-
-    This section configures the Verification API, used for Advanced
-    Core Verification.
-
-    enabled = 0/1
-	'0': disbable VAPI server
-	'1': enable/start VAPI server
-
-    server_port = <value>
-	TCP/IP port to start VAPI server on
-
-    log_enabled = 0/1
-       '0': disable VAPI requests logging
-       '1': enable VAPI requests logging
-
-    hide_device_id = 0/1
-       '0': don't log device id (for compatability with old version)
-       '1': log device id
-
-
-    vapi_fn = <filename>
-       filename for the log file.
-       valid only if log_enabled is set
-*/
-
-section VAPI
-  enabled = 0
-  server_port = 9998
-  log_enabled = 0
-  vapi_log_fn = "vapi.log"
-end
-
-
-/* CPU SECTION
-
-   This section specifies various CPU parameters.
-
-   ver = <value>
-   rev = <value>
-      specifies version and revision of the CPU used
-
-   upr = <value>
-      changes the upr register
-
-   sr = <value>
-      sets the initial Supervision Register value
-      supervisor mode (SM) and fixed one (FO) set = 0x8001
-      exception prefix high (EPH, vectors@0xf0000000) = 0x4000
-      together, (SM | FO | EPH) = 0xc001
-   superscalar = 0/1
-      '0': CPU is scalar
-      '1': CPU is superscalar
-      (modify cpu/or32/execute.c to tune superscalar model)
-
-   hazards = 0/1
-      '0': don't track data hazards in superscalar CPU
-      '1': track data hazards in superscalar CPU
-      If tracked, data hazards can be displayed using the
-      simulator's 'r' command.
-
-   dependstats = 0/1
-      '0': don't calculate inter-instruction dependencies.
-      '1': calculate inter-instruction dependencies.
-      If calculated, inter-instruction dependencies can be
-      displayed using the simulator's 'stat' command.
-
-   sbuf_len = <value>
-      length of store buffer (<= 256), 0 = disabled
-*/
-
-section cpu
-  ver = 0x12
-  cfg = 0x00
-  rev = 0x01
-  sr =  0x8001 /*SPR_SR_FO  | SPR_SR_SM | SPR_SR_EPH */
-  /* upr = */
-  superscalar = 0
-  hazards = 0
-  dependstats = 0
-  sbuf_len = 0
-end
-
-
-/* PM SECTION
-
-   This section specifies Power Management parameters
-
-   enabled = 0/1
-      '0': disable power management
-      '1': enable power management
-*/
-
-section pm
-  enabled = 0
-end
-
-
-/* BPB SECTION
-
-   This section specifies how branch prediction should behave.
-
-   enabled = 0/1
-     '0': disable branch prediction
-     '1': enable branch prediction
-
-   btic = 0/1
-     '0': disable branch target instruction cache model
-     '1': enable branch target instruction cache model
-
-   sbp_bf_fwd = 0/1
-     Static branch prediction for 'l.bf'
-     '0': don't use forward prediction
-     '1': use forward prediction
-
-   sbp_bnf_fwd = 0/1
-     Static branch prediction for 'l.bnf'
-     '0': don't use forward prediction
-     '1': use forward prediction
-
-   hitdelay = <value>
-       number of cycles bpb hit costs
-
-   missdelay = <value>
-       number of cycles bpb miss costs
-*/
-
-section bpb
-  enabled = 0
-  btic = 0
-  sbp_bf_fwd = 0
-  sbp_bnf_fwd = 0
-  hitdelay = 0
-  missdelay = 0
-end
-
-
-/* DEBUG SECTION
-
-   This sections specifies how the debug unit should behave.
-
-   enabled = 0/1
-      '0': disable debug unit
-      '1': enable debug unit
-
-   gdb_enabled = 0/1
-      '0': don't start gdb server
-      '1': start gdb server at port 'server_port'
-
-   server_port = <value>
-      TCP/IP port to start gdb server on
-      valid only if gdb_enabled is set
-
-   vapi_id = <hex_value>
-      Used to create "fake" vapi log file containing the JTAG proxy messages.
-*/
-section debug
-  enabled = 0
-/*  gdb_enabled = 0 */
-/*  server_port = 9999*/
-  rsp_enabled = 1
-  rsp_port = 50001
-end
-
-
-/* MC SECTION
-
-   This section configures the memory controller
-
-   enabled = 0/1
-     '0': disable memory controller
-     '1': enable memory controller
-
-   baseaddr = <hex_value>
-      address of first MC register
-
-   POC = <hex_value>
-      Power On Configuration register
-
-   index = <value>
-      Index of this memory controller amongst all the memory controllers
-*/
-
-section mc
-  enabled = 0
-  baseaddr = 0x93000000
-  POC = 0x00000008                 /* Power on configuration register */
-  index = 0
-end
-
-
-/* UART SECTION
-
-   This section configures the UARTs
-
-     enabled = <0|1>
-	Enable/disable the peripheral.  By default if it is enabled.
-
-     baseaddr = <hex_value>
-	address of first UART register for this device
-
-
-     channel = <channeltype>:<args>
-
-	The channel parameter indicates the source of received UART characters
-	and the sink for transmitted UART characters.
-
-	The <channeltype> can be either "file", "xterm", "tcp", "fd", or "tty"
-	(without quotes).
-
-	  A) To send/receive characters from a pair of files, use a file
-	     channel:
-
-	       channel=file:<rxfile>,<txfile>
-
-	  B) To create an interactive terminal window, use an xterm channel:
-
-	       channel=xterm:[<xterm_arg>]*
-
-	  C) To create a bidirectional tcp socket which one could, for example,
-	     access via telnet, use a tcp channel:
-
-	       channel=tcp:<port number>
-
-	  D) To cause the UART to read/write from existing numeric file
-	     descriptors, use an fd channel:
-
-	       channel=fd:<rx file descriptor num>,<tx file descriptor num>
-
-	  E) To connect the UART to a physical serial port, create a tty
-	     channel:
-
-	       channel=tty:device=/dev/ttyS0,baud=9600
-
-     irq = <value>
-	irq number for this device
-
-     16550 = 0/1
-	'0': this device is a UART16450
-	'1': this device is a UART16550
-
-     jitter = <value>
-	in msecs... time to block, -1 to disable it
-
-     vapi_id = <hex_value>
-	VAPI id of this instance
-*/
-
-section uart
-  enabled = 1
-  baseaddr = 0x90000000
-  irq = 2
-  /* channel = "file:uart0.rx,uart0.tx" */
-  /* channel = "tcp:10084" */
-  channel = "xterm:"
-  jitter = -1                     /* async behaviour */
-  16550 = 1
-end
-
-
-/* DMA SECTION
-
-   This section configures the DMAs
-
-     enabled = <0|1>
-	Enable/disable the peripheral.  By default if it is enabled.
-
-     baseaddr = <hex_value>
-	address of first DMA register for this device
-
-     irq = <value>
-	irq number for this device
-
-     vapi_id = <hex_value>
-	VAPI id of this instance
-*/
-
-section dma
-  enabled = 1
-  baseaddr = 0x9a000000
-  irq = 11
-end
-
-
-/* ETHERNET SECTION
-
-   This section configures the ETHERNETs
-
-     enabled = <0|1>
-	Enable/disable the peripheral.  By default if it is enabled.
-
-     baseaddr = <hex_value>
-	address of first ethernet register for this device
-
-     dma = <value>
-	which controller is this ethernet "connected" to
-
-     irq = <value>
-	ethernet mac IRQ level
-
-     rtx_type = <value>
-	use 0 - file interface, 1 - socket interface
-
-     rx_channel = <value>
-	DMA channel used for RX
-
-     tx_channel = <value>
-	DMA channel used for TX
-
-     rxfile = "<filename>"
-	filename, where to read data from
-
-     txfile = "<filename>"
-	filename, where to write data to
-
-     sockif = "<ifacename>"
-	interface name of ethernet socket
-
-     vapi_id = <hex_value>
-	VAPI id of this instance
-*/
-
-section ethernet
-  enabled = 1
-  baseaddr = 0x92000000
-  /* dma = 0 */
-  irq = 4
-  rtx_type = "tap"
-  tap_dev = "tap0"
-  /* tx_channel = 0 */
-  /* rx_channel = 1 */
-  rxfile = "eth0.rx"
-  txfile = "eth0.tx"
-  sockif = "eth0"
-end
-
-
-/* GPIO SECTION
-
-   This section configures the GPIOs
-
-     enabled = <0|1>
-	Enable/disable the peripheral.  By default if it is enabled.
-
-     baseaddr = <hex_value>
-	address of first GPIO register for this device
-
-     irq = <value>
-	irq number for this device
-
-     base_vapi_id = <hex_value>
-	first VAPI id of this instance
-	GPIO uses 8 consecutive VAPI IDs
-*/
-
-section gpio
-  enabled = 0
-  baseaddr = 0x91000000
-  irq = 3
-  base_vapi_id = 0x0200
-end
-
-/* VGA SECTION
-
-    This section configures the VGA/LCD controller
-
-      enabled = <0|1>
-	Enable/disable the peripheral.  By default if it is enabled.
-
-      baseaddr = <hex_value>
-	address of first VGA register
-
-      irq = <value>
-	irq number for this device
-
-      refresh_rate = <value>
-	number of cycles between screen dumps
-
-      filename = "<filename>"
-	template name for generated names (e.g. "primary" produces "primary0023.bmp")
-*/
-
-section vga
-  enabled = 0
-  baseaddr = 0x97100000
-  irq = 8
-  refresh_rate = 100000
-  filename = "primary"
-end
-
-
-/* TICK TIMER SECTION
-
-    This section configures tick timer
-
-    enabled = 0/1
-      whether tick timer is enabled
-*/
-
-section pic
-  enabled = 1
-  edge_trigger = 1
-end
-
-/* FB SECTION
-
-    This section configures the frame buffer
-
-    enabled = <0|1>
-      Enable/disable the peripheral.  By default if it is enabled.
-
-    baseaddr = <hex_value>
-      base address of frame buffer
-
-    paladdr = <hex_value>
-      base address of first palette entry
-
-    refresh_rate = <value>
-      number of cycles between screen dumps
-
-    filename = "<filename>"
-      template name for generated names (e.g. "primary" produces "primary0023.bmp")
-*/
-
-section fb
-  enabled = 0
-  baseaddr = 0x97000000
-  refresh_rate = 1000000
-  filename = "primary"
-end
-
-
-/* KBD SECTION
-
-    This section configures the PS/2 compatible keyboard
-
-    baseaddr = <hex_value>
-      base address of the keyboard device
-
-    rxfile = "<filename>"
-      filename, where to read data from
-*/
-
-section kbd
-  enabled = 0
-  irq = 5
-  baseaddr = 0x94000000
-  rxfile = "kbd.rx"
-end
-
-
-/* ATA SECTION
-
-    This section configures the ATA/ATAPI host controller
-
-      baseaddr = <hex_value>
-	address of first ATA register
-
-      enabled = <0|1>
-	Enable/disable the peripheral.  By default if it is enabled.
-
-      irq = <value>
-	irq number for this device
-
-      debug = <value>
-	debug level for ata models.
-	0: no debug messages
-	1: verbose messages
-	3: normal messages (more messages than verbose)
-	5: debug messages (normal debug messages)
-	7: flow control messages (debug statemachine flows)
-	9: low priority message (display everything the code does)
-
-      dev_type0/1 = <value>
-	ata device 0 type
-	0: NO_CONNeCT: none (not connected)
-	1: FILE      : simulated harddisk
-	2: LOCAL     : local system harddisk
-
-      dev_file0/1 = "<filename>"
-	filename for simulated ATA device
-	valid only if dev_type0 == 1
-
-      dev_size0/1 = <value>
-	size of simulated hard-disk (in MBytes)
-	valid only if dev_type0 == 1
-
-      dev_packet0/1 = <value>
-	0: simulated ATA device does NOT implement PACKET command feature set
-	1: simulated ATA device does implement PACKET command feature set
-
-   FIXME: irq number
-*/
-
-section ata
-  enabled = 0
-  baseaddr = 0x9e000000
-  irq = 15
-
-end
diff --git a/board/overo/common.c b/board/overo/common.c
index f6f6792..5656e2d 100644
--- a/board/overo/common.c
+++ b/board/overo/common.c
@@ -18,6 +18,7 @@
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/overo/overo.c b/board/overo/overo.c
index 40f13e5..adf33cf 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -27,7 +27,7 @@
 #include <asm/mach-types.h>
 #include "overo.h"
 
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
 #include <usb.h>
 #include <asm/ehci-omap.h>
 #endif
@@ -70,7 +70,8 @@ static struct {
 static const struct ns16550_platdata overo_serial = {
 	.base = OMAP34XX_UART3,
 	.reg_shift = 2,
-	.clock = V_NS16550_CLK
+	.clock = V_NS16550_CLK,
+	.fcr = UART_FCR_DEFVAL,
 };
 
 U_BOOT_DEVICE(overo_uart) = {
@@ -378,21 +379,21 @@ int board_eth_init(bd_t *bis)
 }
 #endif
 
-#if defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
 }
 #endif
 
-#if defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 void board_mmc_power_init(void)
 {
 	twl4030_power_mmc_init(0);
 }
 #endif
 
-#if defined(CONFIG_USB_EHCI)
+#if defined(CONFIG_USB_EHCI_HCD)
 static struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
 	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
@@ -419,4 +420,4 @@ int ehci_hcd_stop(void)
 	return omap_ehci_hcd_stop();
 }
 
-#endif /* CONFIG_USB_EHCI */
+#endif /* CONFIG_USB_EHCI_HCD */
diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c
index b371a40..3502bbf 100644
--- a/board/pandora/pandora.c
+++ b/board/pandora/pandora.c
@@ -121,7 +121,7 @@ void set_muxconf_regs(void)
 	}
 }
 
-#ifdef CONFIG_GENERIC_MMC
+#ifdef CONFIG_MMC
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c
index eb92914..1c0540a 100644
--- a/board/pb1x00/pb1x00.c
+++ b/board/pb1x00/pb1x00.c
@@ -11,11 +11,15 @@
 #include <asm/mipsregs.h>
 #include <asm/io.h>
 
-phys_size_t initdram(int board_type)
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
 {
 	/* Sdram is setup by assembler code */
 	/* If memory could be changed, we should return the true value here */
-	return 64*1024*1024;
+	gd->ram_size = 64 * 1024 * 1024;
+
+	return 0;
 }
 
 #define BCSR_PCMCIA_PC0DRVEN		0x0010
diff --git a/board/pdm360ng/Kconfig b/board/pdm360ng/Kconfig
deleted file mode 100644
index 33173a0..0000000
--- a/board/pdm360ng/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PDM360NG
-
-config SYS_BOARD
-	default "pdm360ng"
-
-config SYS_CONFIG_NAME
-	default "pdm360ng"
-
-endif
diff --git a/board/pdm360ng/MAINTAINERS b/board/pdm360ng/MAINTAINERS
deleted file mode 100644
index 5c99f59..0000000
--- a/board/pdm360ng/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PDM360NG BOARD
-M:	Michael Weiss <michael.weiss@ifm.com>
-S:	Maintained
-F:	board/pdm360ng/
-F:	include/configs/pdm360ng.h
-F:	configs/pdm360ng_defconfig
diff --git a/board/pdm360ng/Makefile b/board/pdm360ng/Makefile
deleted file mode 100644
index 99201a4..0000000
--- a/board/pdm360ng/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= pdm360ng.o
diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c
deleted file mode 100644
index d91d427..0000000
--- a/board/pdm360ng/pdm360ng.c
+++ /dev/null
@@ -1,609 +0,0 @@
-/*
- * (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de>
- *
- * (C) Copyright 2009-2010
- * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mpc512x.h>
-#include <fdt_support.h>
-#include <flash.h>
-#ifdef CONFIG_MISC_INIT_R
-#include <i2c.h>
-#endif
-#include <serial.h>
-#include <jffs2/load_kernel.h>
-#include <mtd_node.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[];
-ulong flash_get_size (phys_addr_t base, int banknum);
-
-sdram_conf_t mddrc_config[] = {
-	{
-		(512 << 20),	/* 512 MB RAM configuration */
-		{
-			CONFIG_SYS_MDDRC_SYS_CFG,
-			CONFIG_SYS_MDDRC_TIME_CFG0,
-			CONFIG_SYS_MDDRC_TIME_CFG1,
-			CONFIG_SYS_MDDRC_TIME_CFG2
-		}
-	},
-	{
-		(128 << 20),	/* 128 MB RAM configuration */
-		{
-			CONFIG_SYS_MDDRC_SYS_CFG_ALT1,
-			CONFIG_SYS_MDDRC_TIME_CFG0_ALT1,
-			CONFIG_SYS_MDDRC_TIME_CFG1_ALT1,
-			CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
-		}
-	},
-};
-
-phys_size_t initdram (int board_type)
-{
-	int i;
-	u32 msize = 0;
-	u32 pdm360ng_init_seq[] = {
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_MICRON_INIT_DEV_OP,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_EM2,
-		CONFIG_SYS_DDRCMD_NOP,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_EM2,
-		CONFIG_SYS_DDRCMD_EM3,
-		CONFIG_SYS_DDRCMD_EN_DLL,
-		CONFIG_SYS_DDRCMD_RES_DLL,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_DDRCMD_RFSH,
-		CONFIG_SYS_MICRON_INIT_DEV_OP,
-		CONFIG_SYS_DDRCMD_OCD_DEFAULT,
-		CONFIG_SYS_DDRCMD_OCD_EXIT,
-		CONFIG_SYS_DDRCMD_PCHG_ALL,
-		CONFIG_SYS_DDRCMD_NOP
-	};
-
-	for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) {
-		msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq,
-				    ARRAY_SIZE(pdm360ng_init_seq));
-		if (msize == mddrc_config[i].size)
-			break;
-	}
-
-	return msize;
-}
-
-static int set_lcd_brightness(char *);
-
-int misc_init_r(void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	/*
-	 * Re-configure flash setup using auto-detected info
-	 */
-	if (flash_info[1].size > 0) {
-		out_be32(&im->sysconf.lpcs1aw,
-			CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
-			CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
-				  flash_info[1].size));
-		sync_law(&im->sysconf.lpcs1aw);
-		/*
-		 * Re-check to get correct base address
-		 */
-		flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
-	} else {
-		/* Disable Bank 1 */
-		out_be32(&im->sysconf.lpcs1aw, 0x01000100);
-		sync_law(&im->sysconf.lpcs1aw);
-	}
-
-	out_be32(&im->sysconf.lpcs0aw,
-		CSAW_START(gd->bd->bi_flashstart) |
-		CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
-	sync_law(&im->sysconf.lpcs0aw);
-
-	/*
-	 * Re-check to get correct base address
-	 */
-	flash_get_size (gd->bd->bi_flashstart, 0);
-
-	/*
-	 * Re-do flash protection upon new addresses
-	 */
-	flash_protect (FLAG_PROTECT_CLEAR,
-		       gd->bd->bi_flashstart, 0xffffffff,
-		       &flash_info[0]);
-
-	/* Monitor protection ON by default */
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_MONITOR_BASE,
-		       CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
-		       &flash_info[0]);
-
-	/* Environment protection ON by default */
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV_ADDR,
-		       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-		       &flash_info[0]);
-
-#ifdef CONFIG_ENV_ADDR_REDUND
-	/* Redundant environment protection ON by default */
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV_ADDR_REDUND,
-		       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-		       &flash_info[0]);
-#endif
-
-#ifdef CONFIG_FSL_DIU_FB
-	set_lcd_brightness(0);
-	/* Switch LCD-Backlight and LVDS-Interface on */
-	setbits_be32(&im->gpio.gpdir, 0x01040000);
-	clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
-#endif
-
-#if defined(CONFIG_HARD_I2C)
-	if (!getenv("ethaddr")) {
-		uchar buf[6];
-		uchar ifm_oui[3] = { 0, 2, 1, };
-		int ret;
-
-		/* I2C-0 for on-board eeprom */
-		i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM);
-
-		/* Read ethaddr from EEPROM */
-		ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR,
-			       CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6);
-		if (ret != 0) {
-			printf("Error: Unable to read MAC from I2C"
-				" EEPROM at address %02X:%02X\n",
-				CONFIG_SYS_I2C_EEPROM_ADDR,
-				CONFIG_SYS_I2C_EEPROM_MAC_OFFSET);
-			return 1;
-		}
-
-		/* Owned by IFM ? */
-		if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) {
-			printf("Illegal MAC address in EEPROM: %pM\n", buf);
-			return 1;
-		}
-
-		eth_setenv_enetaddr("ethaddr", buf);
-	}
-#endif /* defined(CONFIG_HARD_I2C) */
-
-	return 0;
-}
-
-static  iopin_t ioregs_init[] = {
-	/* FUNC1=LPC_CS4 */
-	{
-		offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
-		IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=GPIO10 */
-	{
-		offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC1=CAN3_TX */
-	{
-		offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO14 */
-	{
-		offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */
-	/* DIU_LD22-DIU_LD23 */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */
-	/* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */
-	/* VIU_DATA0-VIU_DATA2 */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC2=FEC_TXD_0 */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */
-	/* VIU_DATA3, VIU_DATA4 */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */
-	/* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */
-	/* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */
-	/* DIU_LD00-DIU_LD21 */
-	{
-		offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
-	},
-	/* FUNC2=DIU_CLK Sets Next 3 to DIU pads */
-	/* DIU_CLK, DIU_VSYNC, DIU_HSYNC */
-	{
-		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC2=CAN3_RX */
-	{
-		offsetof(struct ioctrl512x, io_control_irq1), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* Sets lowest slew on 2 CAN_TX Pins*/
-	{
-		offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */
-	/* CAN4_TX, CAN4_RX */
-	{
-		offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
-	/* GPIO8, GPIO9 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */
-	/* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */
-	/* FEC_RXD_3, FEC_RXD_2 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=GPIO17 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
-	/* GPIO2, GPIO20, GPIO21 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC2=VIU_PIX_CLK */
-	{
-		offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=GPIO24 Sets Next 2 to GPIO pads */
-	/* GPIO24, GPIO25 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC1=NFC_CE2 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
-		IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */
-	/* VIU_DATA5-VIU_DATA9 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */
-	/* LPC_TSIZ1-LPC_TSIZ2 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=LPC_TS */
-	{
-		offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC3=GPIO16 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO18 Sets Next 3 to GPIO pads */
-	/* GPIO18-GPIO19, GPT7/GPIO7 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO0/GPT0 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC3=GPIO11 Sets Next 4 to GPIO pads */
-	/* GPIO11, GPIO2, GPIO12, GPIO13 */
-	{
-		offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0,
-		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
-	},
-	/* FUNC2=DIU_DE */
-	{
-		offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	}
-};
-
-int checkboard (void)
-{
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-
-	puts("Board: PDM360NG\n");
-
-	/* initialize function mux & slew rate IO inter alia on IO Pins  */
-
-	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
-
-	/* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */
-	setbits_be32(&im->io_ctrl.io_control_gp,
-		     (1 << 0) |   /* GP_MUX7->GPIO7 */
-		     (1 << 5));	  /* GP_MUX2->GPIO2 */
-
-	/* configure GPIO24 (VIU_CE), output/high */
-	setbits_be32(&im->gpio.gpdir, 0x80);
-	setbits_be32(&im->gpio.gpdat, 0x80);
-
-	return 0;
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
-struct node_info nodes[] = {
-	{ "fsl,mpc5121-nfc",	MTD_DEV_TYPE_NAND, },
-	{ "cfi-flash",		MTD_DEV_TYPE_NOR,  },
-};
-#endif
-
-#if defined(CONFIG_VIDEO)
-/*
- * EDID block has been generated using Phoenix EDID Designer 1.3.
- * This tool creates a text file containing:
- *
- * EDID BYTES:
- * 0x   00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
- *     ------------------------------------------------
- * 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00
- * 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25
- * 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
- * 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80
- * 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F
- * 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50
- * 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF
- * 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4
- *
- * Then this data has been manually converted to the char
- * array below.
- */
-static unsigned char edid_buf[128] = {
-	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
-	0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00,
-	0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78,
-	0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25,
-	0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01,
-	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C,
-	0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80,
-	0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18,
-	0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F,
-	0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20,
-	0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50,
-	0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A,
-	0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF,
-	0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
-	0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4,
-};
-#endif
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	u32 val[8];
-	int rc, i = 0;
-
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
-	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
-#endif
-#if defined(CONFIG_VIDEO)
-	fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf);
-#endif
-
-	/* Fixup NOR FLASH mapping */
-	val[i++] = 0;				/* chip select number */
-	val[i++] = 0;				/* always 0 */
-	val[i++] = gd->bd->bi_flashstart;
-	val[i++] = gd->bd->bi_flashsize;
-
-	/* Fixup MRAM mapping */
-	val[i++] = 2;				/* chip select number */
-	val[i++] = 0;				/* always 0 */
-	val[i++] = CONFIG_SYS_MRAM_BASE;
-	val[i++] = CONFIG_SYS_MRAM_SIZE;
-
-	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
-				  val, i * sizeof(u32), 1);
-	if (rc)
-		printf("Unable to update localbus ranges, err=%s\n",
-		       fdt_strerror(rc));
-
-	/* Fixup reg property in NOR Flash node */
-	i = 0;
-	val[i++] = 0;			/* always 0 */
-	val[i++] = 0;			/* start at offset 0 */
-	val[i++] = flash_info[0].size;	/* size of Bank 0 */
-
-	/* Second Bank available? */
-	if (flash_info[1].size > 0) {
-		val[i++] = 0;			/* always 0 */
-		val[i++] = flash_info[0].size;	/* offset of Bank 1 */
-		val[i++] = flash_info[1].size;	/* size of Bank 1 */
-	}
-
-	rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg",
-				  val, i * sizeof(u32), 1);
-	if (rc)
-		printf("Unable to update flash reg property, err=%s\n",
-		       fdt_strerror(rc));
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-/*
- * If argument is NULL, set the LCD brightness to the
- * value from "brightness" environment variable. Set
- * the LCD brightness to the value specified by the
- * argument otherwise. Default brightness is zero.
- */
-#define MAX_BRIGHTNESS	99
-static int set_lcd_brightness(char *brightness)
-{
-	struct stdio_dev *cop_port;
-	char *env;
-	char cmd_buf[20];
-	int val = 0;
-	int cs = 0;
-	int len, i;
-
-	if (brightness) {
-		val = simple_strtol(brightness, NULL, 10);
-	} else {
-		env = getenv("brightness");
-		if (env)
-			val = simple_strtol(env, NULL, 10);
-	}
-
-	if (val < 0)
-		val = 0;
-
-	if (val > MAX_BRIGHTNESS)
-		val = MAX_BRIGHTNESS;
-
-	sprintf(cmd_buf, "$SB;%04d;", val);
-
-	len = strlen(cmd_buf);
-	for (i = 1; i <= len; i++)
-		cs += cmd_buf[i];
-
-	cs = (~cs + 1) & 0xff;
-	sprintf(cmd_buf + len, "%02X\n", cs);
-
-	/* IO Coprocessor communication */
-	cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
-	if (!cop_port) {
-		printf("Error: Can't open IO Coprocessor port.\n");
-		return -1;
-	}
-
-	debug("%s: cmd: %s", __func__, cmd_buf);
-	write_port(cop_port, cmd_buf);
-	/*
-	 * Wait for transmission and maybe response data
-	 * before closing the port.
-	 */
-	udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
-	memset(cmd_buf, 0, sizeof(cmd_buf));
-	len = read_port(cop_port, cmd_buf, sizeof(cmd_buf));
-	if (len)
-		printf("Error: %s\n", cmd_buf);
-
-	close_port(4);
-
-	return 0;
-}
-
-static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
-			      int argc, char * const argv[])
-{
-	if (argc < 2)
-		return cmd_usage(cmdtp);
-
-	return set_lcd_brightness(argv[1]);
-}
-
-U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness,
-	"set LCD brightness",
-	"<brightness> - set LCD backlight level to <brightness>.\n"
-);
diff --git a/board/phytec/pcm030/Kconfig b/board/phytec/pcm030/Kconfig
deleted file mode 100644
index 3a3eab8..0000000
--- a/board/phytec/pcm030/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_PCM030
-
-config SYS_BOARD
-	default "pcm030"
-
-config SYS_VENDOR
-	default "phytec"
-
-config SYS_CONFIG_NAME
-	default "pcm030"
-
-endif
diff --git a/board/phytec/pcm030/MAINTAINERS b/board/phytec/pcm030/MAINTAINERS
deleted file mode 100644
index 4e2ab0d..0000000
--- a/board/phytec/pcm030/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-PCM030 BOARD
-M:	Jon Smirl <jonsmirl@gmail.com>
-S:	Maintained
-F:	board/phytec/pcm030/
-F:	include/configs/pcm030.h
-F:	configs/pcm030_defconfig
-F:	configs/pcm030_LOWBOOT_defconfig
diff --git a/board/phytec/pcm030/Makefile b/board/phytec/pcm030/Makefile
deleted file mode 100644
index 2bb49dc..0000000
--- a/board/phytec/pcm030/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= pcm030.o
diff --git a/board/phytec/pcm030/README b/board/phytec/pcm030/README
deleted file mode 100644
index 05faab6..0000000
--- a/board/phytec/pcm030/README
+++ /dev/null
@@ -1,42 +0,0 @@
-To build RAMBOOT, replace this section the main Makefile
-
-pcm030_config \
-pcm030_RAMBOOT_config \
-pcm030_LOWBOOT_config:	unconfig
-	@ >include/config.h
-	@[ -z "$(findstring LOWBOOT_,$@)" ] || \
-		{ echo "CONFIG_SYS_TEXT_BASE = 0xFF000000"	>board/phytec/pcm030/config.tmp ; \
-		  echo "... with LOWBOOT configuration" ; \
-		}
-	@[ -z "$(findstring RAMBOOT_,$@)" ] || \
-	       { echo "CONFIG_SYS_TEXT_BASE = 0x00100000" >board/phycore_mpc5200b_tiny/\
-			config.tmp ; \
-		 echo "... with RAMBOOT configuration" ; \
-		 echo "... remember to make sure that MBAR is already \
-				switched to 0xF0000000 !!!" ; \
-	       }
-	@$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec
-	@ echo "remember to set pcm030_REV to 0 for rev 1245.0 rev or to 1 for rev 1245.1"
-
-Alternative SDRAM settings:
-
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x715f0f00
-#define SDRAM_CONFIG1	0x73722930
-#define SDRAM_CONFIG2	0x47770000
-
-/* Settings for XLB = 99 MHz */
-#define SDRAM_MODE	0x008D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x714b0f00
-#define SDRAM_CONFIG1	0x63611730
-#define SDRAM_CONFIG2	0x47670000
-
-The board ships default with the environment in EEPROM
-Moving the environment to flash can be more reliable
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0xfe0000)
-#define CONFIG_ENV_SIZE		0x20000
-#define CONFIG_ENV_SECT_SIZE	0x20000
diff --git a/board/phytec/pcm030/mt46v32m16-75.h b/board/phytec/pcm030/mt46v32m16-75.h
deleted file mode 100644
index 47fc7c0..0000000
--- a/board/phytec/pcm030/mt46v32m16-75.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * Eric Schumann, Phytec Messtechnik
- * adapted for mt46v32m16-75 DDR-RAM
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	1		/* is DDR */
-
-/* Settings for XLB = 132 MHz */
-
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x71500F00
-#define SDRAM_CONFIG1	0x73711930
-#define SDRAM_CONFIG2	0x47770000
-
-#define SDRAM_TAPDELAY	0x10000000 /* reserved Bit in MPC5200 B3-Step */
diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c
deleted file mode 100644
index 8a9de0d..0000000
--- a/board/phytec/pcm030/pcm030.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2006
- * Eric Schumann, Phytec Messtechnik GmbH
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/io.h>
-
-#include "mt46v32m16-75.h"
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start(int hi_addr)
-{
-	volatile struct mpc5xxx_cdm *cdm =
-		(struct mpc5xxx_cdm *)MPC5XXX_CDM;
-	volatile struct mpc5xxx_sdram *sdram =
-		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
-
-	/* precharge all banks */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
-
-#ifdef SDRAM_DDR
-	/* set mode register: extended mode */
-	out_be32 (&sdram->mode, (SDRAM_EMODE));
-
-	/* set mode register: reset DLL */
-	out_be32 (&sdram->mode,
-		(SDRAM_MODE | 0x04000000));
-#endif
-
-	/* precharge all banks */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
-
-	/* auto refresh */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
-
-	/* set mode register */
-	out_be32 (&sdram->mode, (SDRAM_MODE));
-
-	/* normal operation */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | hi_addr_bit));
-
-	/* set CDM clock enable register, set MPC5200B SDRAM bus */
-	/* to reduced driver strength */
-	out_be32 (&cdm->clock_enable, (0x00CFFFFF));
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make
- *	real use of CONFIG_SYS_SDRAM_BASE. The code does not
- *	work if CONFIG_SYS_SDRAM_BASE
- *	is something else than 0x00000000.
- */
-
-phys_size_t initdram(int board_type)
-{
-	volatile struct mpc5xxx_mmap_ctl *mm =
-		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
-	volatile struct mpc5xxx_cdm *cdm =
-		(struct mpc5xxx_cdm *)MPC5XXX_CDM;
-	volatile struct mpc5xxx_sdram *sdram =
-		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-							 /* 256MB at 0x0 */
-	out_be32 (&mm->sdram0, 0x0000001b);
-							 /* disabled */
-	out_be32 (&mm->sdram1, 0x10000000);
-
-	/* setup config registers */
-	out_be32 (&sdram->config1, SDRAM_CONFIG1);
-	out_be32 (&sdram->config2, SDRAM_CONFIG2);
-
-#if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY)
-	/* set tap delay */
-	out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else
-		dramsize = test2;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32 (&mm->sdram0,
-			(0x13 + __builtin_ffs(dramsize >> 20) - 1));
-	} else {
-							/* disabled */
-		out_be32 (&mm->sdram0, 0);
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32(&mm->sdram0) & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = in_be32(&mm->sdram1) & 0xFF;
-	if (dramsize2 >= 0x13)
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	else
-		dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	return dramsize + dramsize2;
-}
-
-int checkboard(void)
-{
-	puts("Board: phyCORE-MPC5200B-tiny\n");
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-#define GPIO_PSC2_4	0x02000000UL
-
-void init_ide_reset(void)
-{
-	volatile struct mpc5xxx_wu_gpio *wu_gpio =
-		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-	debug("init_ide_reset\n");
-
-	/* Configure PSC2_4 as GPIO output for ATA reset */
-	setbits_be32(&wu_gpio->enable, GPIO_PSC2_4);
-	setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4);
-	/* Deassert reset */
-	setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
-}
-
-void ide_set_reset(int idereset)
-{
-	volatile struct mpc5xxx_wu_gpio *wu_gpio =
-		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-	debug("ide_reset(%d)\n", idereset);
-
-	if (idereset) {
-		clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
-		/* Make a delay. MPC5200 spec says 25 usec min */
-		udelay(500000);
-	} else
-		setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
-}
-#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig
index d67a69a..4fde21c 100644
--- a/board/phytec/pcm052/Kconfig
+++ b/board/phytec/pcm052/Kconfig
@@ -6,10 +6,28 @@ config SYS_BOARD
 config SYS_VENDOR
 	default "phytec"
 
-config SYS_SOC
-	default "vf610"
-
 config SYS_CONFIG_NAME
 	default "pcm052"
 
+config PCM052_DDR_SIZE
+	int
+	default 256
+
+endif
+
+if TARGET_BK4R1
+
+config SYS_BOARD
+	default "pcm052"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_CONFIG_NAME
+	default "bk4r1"
+
+config PCM052_DDR_SIZE
+	int
+	default 512
+
 endif
diff --git a/board/phytec/pcm052/imximage.cfg b/board/phytec/pcm052/imximage.cfg
index f5a9747..2a302d7 100644
--- a/board/phytec/pcm052/imximage.cfg
+++ b/board/phytec/pcm052/imximage.cfg
@@ -3,12 +3,12 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
  */
-#include <asm/imx-common/imximage.cfg>
+#include <asm/mach-imx/imximage.cfg>
 
 /* image version */
 IMAGE_VERSION	2
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c
index e4f61e1..54a4e4f 100644
--- a/board/phytec/pcm052/pcm052.c
+++ b/board/phytec/pcm052/pcm052.c
@@ -152,57 +152,6 @@ static struct ddrmc_phy_setting pcm052_phy_settings[] = {
 
 int dram_init(void)
 {
-	static const struct ddr3_jedec_timings pcm052_ddr_timings = {
-		.tinit             = 5,
-		.trst_pwron        = 80000,
-		.cke_inactive      = 200000,
-		.wrlat             = 5,
-		.caslat_lin        = 12,
-		.trc               = 6,
-		.trrd              = 4,
-		.tccd              = 4,
-		.tbst_int_interval = 4,
-		.tfaw              = 18,
-		.trp               = 6,
-		.twtr              = 4,
-		.tras_min          = 15,
-		.tmrd              = 4,
-		.trtp              = 4,
-		.tras_max          = 14040,
-		.tmod              = 12,
-		.tckesr            = 4,
-		.tcke              = 3,
-		.trcd_int          = 6,
-		.tras_lockout      = 1,
-		.tdal              = 10,
-		.bstlen            = 3,
-		.tdll              = 512,
-		.trp_ab            = 6,
-		.tref              = 1542,
-		.trfc              = 64,
-		.tref_int          = 5,
-		.tpdex             = 3,
-		.txpdll            = 10,
-		.txsnr             = 68,
-		.txsr              = 506,
-		.cksrx             = 5,
-		.cksre             = 5,
-		.freq_chg_en       = 1,
-		.zqcl              = 256,
-		.zqinit            = 512,
-		.zqcs              = 64,
-		.ref_per_zq        = 64,
-		.zqcs_rotate       = 1,
-		.aprebit           = 10,
-		.cmd_age_cnt       = 255,
-		.age_cnt           = 255,
-		.q_fullness        = 0,
-		.odt_rd_mapcs0     = 1,
-		.odt_wr_mapcs0     = 1,
-		.wlmrd             = 40,
-		.wldqsen           = 25,
-	};
-
 	static const iomux_v3_cfg_t pcm052_pads[] = {
 		PCM052_VF610_PAD_DDR_A15__DDR_A_15,
 		PCM052_VF610_PAD_DDR_A14__DDR_A_14,
@@ -256,10 +205,126 @@ int dram_init(void)
 		PCM052_VF610_PAD_DDR_RESETB,
 	};
 
+#if defined(CONFIG_TARGET_PCM052)
+
+	static const struct ddr3_jedec_timings pcm052_ddr_timings = {
+		.tinit             = 5,
+		.trst_pwron        = 80000,
+		.cke_inactive      = 200000,
+		.wrlat             = 5,
+		.caslat_lin        = 12,
+		.trc               = 6,
+		.trrd              = 4,
+		.tccd              = 4,
+		.tbst_int_interval = 4,
+		.tfaw              = 18,
+		.trp               = 6,
+		.twtr              = 4,
+		.tras_min          = 15,
+		.tmrd              = 4,
+		.trtp              = 4,
+		.tras_max          = 14040,
+		.tmod              = 12,
+		.tckesr            = 4,
+		.tcke              = 3,
+		.trcd_int          = 6,
+		.tras_lockout      = 1,
+		.tdal              = 10,
+		.bstlen            = 3,
+		.tdll              = 512,
+		.trp_ab            = 6,
+		.tref              = 1542,
+		.trfc              = 64,
+		.tref_int          = 5,
+		.tpdex             = 3,
+		.txpdll            = 10,
+		.txsnr             = 68,
+		.txsr              = 506,
+		.cksrx             = 5,
+		.cksre             = 5,
+		.freq_chg_en       = 1,
+		.zqcl              = 256,
+		.zqinit            = 512,
+		.zqcs              = 64,
+		.ref_per_zq        = 64,
+		.zqcs_rotate       = 1,
+		.aprebit           = 10,
+		.cmd_age_cnt       = 255,
+		.age_cnt           = 255,
+		.q_fullness        = 0,
+		.odt_rd_mapcs0     = 1,
+		.odt_wr_mapcs0     = 1,
+		.wlmrd             = 40,
+		.wldqsen           = 25,
+	};
+
+    const int row_diff = 2;
+
+#elif defined(CONFIG_TARGET_BK4R1)
+
+	static const struct ddr3_jedec_timings pcm052_ddr_timings = {
+		.tinit             = 5,
+		.trst_pwron        = 80000,
+		.cke_inactive      = 200000,
+		.wrlat             = 5,
+		.caslat_lin        = 12,
+		.trc               = 6,
+		.trrd              = 4,
+		.tccd              = 4,
+		.tbst_int_interval = 0,
+		.tfaw              = 16,
+		.trp               = 6,
+		.twtr              = 4,
+		.tras_min          = 15,
+		.tmrd              = 4,
+		.trtp              = 4,
+		.tras_max          = 28080,
+		.tmod              = 12,
+		.tckesr            = 4,
+		.tcke              = 3,
+		.trcd_int          = 6,
+		.tras_lockout      = 1,
+		.tdal              = 12,
+		.bstlen            = 3,
+		.tdll              = 512,
+		.trp_ab            = 6,
+		.tref              = 3120,
+		.trfc              = 104,
+		.tref_int          = 0,
+		.tpdex             = 3,
+		.txpdll            = 10,
+		.txsnr             = 108,
+		.txsr              = 512,
+		.cksrx             = 5,
+		.cksre             = 5,
+		.freq_chg_en       = 1,
+		.zqcl              = 256,
+		.zqinit            = 512,
+		.zqcs              = 64,
+		.ref_per_zq        = 64,
+		.zqcs_rotate       = 1,
+		.aprebit           = 10,
+		.cmd_age_cnt       = 255,
+		.age_cnt           = 255,
+		.q_fullness        = 0,
+		.odt_rd_mapcs0     = 1,
+		.odt_wr_mapcs0     = 1,
+		.wlmrd             = 40,
+		.wldqsen           = 25,
+	};
+
+    const int row_diff = 1;
+
+#else /* Unknown PCM052 variant */
+
+#error DDR characteristics undefined for this target. Please define them.
+
+#endif
+
 	imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads));
 
 	ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
-			     pcm052_phy_settings, 1, 2);
+			     pcm052_phy_settings, 1, row_diff);
 
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 
@@ -513,3 +578,41 @@ int checkboard(void)
 
 	return 0;
 }
+
+static int do_m4go(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	ulong addr;
+
+	/* Consume 'm4go' */
+	argc--; argv++;
+
+	/*
+	 * Parse provided address - default to load_addr in case not provided.
+	 */
+
+	if (argc)
+		addr = simple_strtoul(argv[0], NULL, 16);
+	else
+		addr = load_addr;
+
+	/*
+	 * Write boot address in PERSISTENT_ENTRY1[31:0] aka SRC_GPR2[31:0]
+	 */
+	writel(addr + 0x401, 0x4006E028);
+
+	/*
+	 * Start secondary processor by enabling its clock
+	 */
+	writel(0x15a5a, 0x4006B08C);
+
+	return 1;
+}
+
+U_BOOT_CMD(
+	m4go, 2 /* one arg max */, 1 /* repeatable */, do_m4go,
+	"start the secondary Cortex-M4 from scatter file image",
+	"[<addr>]\n"
+	"    - start secondary Cortex-M4 core using a scatter file image\n"
+	"The argument needs to be a scatter file\n"
+);
diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c
index 4e2122f..4257fbc 100644
--- a/board/phytec/pcm058/pcm058.c
+++ b/board/phytec/pcm058/pcm058.c
@@ -18,11 +18,11 @@
 #include <asm/arch/mx6-ddr.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/spi.h>
-#include <asm/errno.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
 #include <mmc.h>
 #include <i2c.h>
@@ -108,6 +108,7 @@ static iomux_v3_cfg_t const ecspi1_pads[] = {
 	MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
+#ifdef CONFIG_CMD_NAND
 /* NAND */
 static iomux_v3_cfg_t const nfc_pads[] = {
 	MX6_PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NAND_PAD_CTRL),
@@ -130,11 +131,7 @@ static iomux_v3_cfg_t const nfc_pads[] = {
 	MX6_PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NAND_PAD_CTRL),
 	MX6_PAD_SD4_DAT0__NAND_DQS	| MUX_PAD_CTRL(NAND_PAD_CTRL),
 };
-
-
-/* GPIOS */
-static iomux_v3_cfg_t const gpios_pads[] = {
-};
+#endif
 
 static struct i2c_pads_info i2c_pad_info2 = {
 	.scl = {
@@ -167,7 +164,7 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
 	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
-#ifndef CONFIG_CMD_NAND
+#if !defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
 static iomux_v3_cfg_t const usdhc4_pads[] = {
 	MX6_PAD_SD4_CLK__SD4_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_CMD__SD4_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
diff --git a/board/phytec/phycore_rk3288/Kconfig b/board/phytec/phycore_rk3288/Kconfig
new file mode 100644
index 0000000..57cd8e2
--- /dev/null
+++ b/board/phytec/phycore_rk3288/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PHYCORE_RK3288
+
+config SYS_BOARD
+	default "phycore_rk3288"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_CONFIG_NAME
+	default "phycore_rk3288"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/phytec/phycore_rk3288/MAINTAINERS b/board/phytec/phycore_rk3288/MAINTAINERS
new file mode 100644
index 0000000..9c0de3c
--- /dev/null
+++ b/board/phytec/phycore_rk3288/MAINTAINERS
@@ -0,0 +1,6 @@
+phyCORE-RK3288
+M:	Wadim Egorov <w.egorov@phytec.de>
+S:	Maintained
+F:	board/phytec/phycore_rk3288
+F:	include/configs/phycore_rk3288.h
+F:	configs/phycore-rk3288_defconfig
diff --git a/board/phytec/phycore_rk3288/Makefile b/board/phytec/phycore_rk3288/Makefile
new file mode 100644
index 0000000..f379fbe
--- /dev/null
+++ b/board/phytec/phycore_rk3288/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2017 PHYTEC Messtechnik GmbH
+# Author: Wadim Egorov <w.egorov@phytec.de>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += phycore-rk3288.o
diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c
new file mode 100644
index 0000000..20696f6
--- /dev/null
+++ b/board/phytec/phycore_rk3288/phycore-rk3288.c
@@ -0,0 +1,8 @@
+/*
+ * Copyright (C) 2017 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
diff --git a/board/pr1/Kconfig b/board/pr1/Kconfig
deleted file mode 100644
index fb04648..0000000
--- a/board/pr1/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_PR1
-
-config SYS_BOARD
-	default "pr1"
-
-config SYS_CONFIG_NAME
-	default "pr1"
-
-endif
diff --git a/board/pr1/MAINTAINERS b/board/pr1/MAINTAINERS
deleted file mode 100644
index 23fdbc7..0000000
--- a/board/pr1/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PR1 BOARD
-M:	Dimitar Penev <dpn@switchfin.org>
-S:	Maintained
-F:	board/pr1/
-F:	include/configs/pr1.h
-F:	configs/pr1_defconfig
diff --git a/board/pr1/Makefile b/board/pr1/Makefile
deleted file mode 100644
index 8caa360..0000000
--- a/board/pr1/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) Switchfin Org. <dpn@switchfin.org>
-#
-# Copyright (c) 2005-2007 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= pr1.o
diff --git a/board/pr1/pr1.c b/board/pr1/pr1.c
deleted file mode 100644
index 3fffabd..0000000
--- a/board/pr1/pr1.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) Switchfin Org. <dpn@switchfin.org>
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <net.h>
-#include <netdev.h>
-
-int checkboard(void)
-{
-	printf("Board: Switchvoice PR1 Appliance\n");
-	printf("       Support: http://www.switchvoice.com/\n");
-	return 0;
-}
-
-#ifdef CONFIG_BFIN_MAC
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
diff --git a/board/qca/ap121/ap121.c b/board/qca/ap121/ap121.c
index e245faa..ac9be35 100644
--- a/board/qca/ap121/ap121.c
+++ b/board/qca/ap121/ap121.c
@@ -43,9 +43,6 @@ void board_debug_uart_init(void)
 
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
 	ddr_init();
 	ath79_eth_reset();
 	return 0;
diff --git a/board/qca/ap143/ap143.c b/board/qca/ap143/ap143.c
index e921ea5..19b55ac 100644
--- a/board/qca/ap143/ap143.c
+++ b/board/qca/ap143/ap143.c
@@ -59,9 +59,6 @@ void board_debug_uart_init(void)
 
 int board_early_init_f(void)
 {
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
-#endif
 	ddr_init();
 	ath79_eth_reset();
 	return 0;
diff --git a/board/qemu-mips/qemu-mips.c b/board/qemu-mips/qemu-mips.c
index 563044e..583acc2 100644
--- a/board/qemu-mips/qemu-mips.c
+++ b/board/qemu-mips/qemu-mips.c
@@ -11,11 +11,15 @@
 #include <asm/io.h>
 #include <netdev.h>
 
-phys_size_t initdram(int board_type)
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
 {
 	/* Sdram is setup by assembler code */
 	/* If memory could be changed, we should return the true value here */
-	return MEM_SIZE*1024*1024;
+	gd->ram_size = MEM_SIZE * 1024 * 1024;
+
+	return 0;
 }
 
 int checkboard(void)
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c
index 1fa5664..37d0b85 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -19,10 +19,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
 }
 
 
@@ -44,14 +46,15 @@ int board_prepare_usb(enum usb_init_type type)
 
 	/* Try to request gpios needed to start usb host on dragonboard */
 	if (!dm_gpio_is_valid(&hub_reset)) {
-		node = fdt_subnode_offset(gd->fdt_blob, pmic_gpio->of_offset,
+		node = fdt_subnode_offset(gd->fdt_blob,
+					  dev_of_offset(pmic_gpio),
 					  "usb_hub_reset_pm");
 		if (node < 0) {
 			printf("Failed to find usb_hub_reset_pm dt node.\n");
 			return node;
 		}
-		ret = gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 0,
-						 &hub_reset, 0);
+		ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
+						 "gpios", 0, &hub_reset, 0);
 		if (ret < 0) {
 			printf("Failed to request usb_hub_reset_pm gpio.\n");
 			return ret;
@@ -59,14 +62,15 @@ int board_prepare_usb(enum usb_init_type type)
 	}
 
 	if (!dm_gpio_is_valid(&usb_sel)) {
-		node = fdt_subnode_offset(gd->fdt_blob, pmic_gpio->of_offset,
+		node = fdt_subnode_offset(gd->fdt_blob,
+					  dev_of_offset(pmic_gpio),
 					  "usb_sw_sel_pm");
 		if (node < 0) {
 			printf("Failed to find usb_sw_sel_pm dt node.\n");
 			return 0;
 		}
-		ret = gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 0,
-						 &usb_sel, 0);
+		ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
+						 "gpios", 0, &usb_sel, 0);
 		if (ret < 0) {
 			printf("Failed to request usb_sw_sel_pm gpio.\n");
 			return ret;
@@ -110,14 +114,15 @@ int misc_init_r(void)
 		return 0;
 	}
 
-	node = fdt_subnode_offset(gd->fdt_blob, pon->of_offset, "key_vol_down");
+	node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
+				  "key_vol_down");
 	if (node < 0) {
 		printf("Failed to find key_vol_down node. Check device tree\n");
 		return 0;
 	}
 
-	if (gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 0, &resin,
-				       0)) {
+	if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
+				       &resin, 0)) {
 		printf("Failed to request key_vol_down button.\n");
 		return 0;
 	}
diff --git a/board/qualcomm/dragonboard410c/u-boot.lds b/board/qualcomm/dragonboard410c/u-boot.lds
index 6e1c5a8..62ac4d7 100644
--- a/board/qualcomm/dragonboard410c/u-boot.lds
+++ b/board/qualcomm/dragonboard410c/u-boot.lds
@@ -43,6 +43,22 @@ SECTIONS
 
 	. = ALIGN(8);
 
+	.efi_runtime : {
+                __efi_runtime_start = .;
+		*(efi_runtime_text)
+		*(efi_runtime_data)
+                __efi_runtime_stop = .;
+	}
+
+	.efi_runtime_rel : {
+                __efi_runtime_rel_start = .;
+		*(.relaefi_runtime_text)
+		*(.relaefi_runtime_data)
+                __efi_runtime_rel_stop = .;
+	}
+
+	. = ALIGN(8);
+
 	.image_copy_end :
 	{
 		*(.__image_copy_end)
diff --git a/board/quipos/cairo/cairo.c b/board/quipos/cairo/cairo.c
index 77e4482..6cf5409 100644
--- a/board/quipos/cairo/cairo.c
+++ b/board/quipos/cairo/cairo.c
@@ -26,18 +26,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
- * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
- */
-u8 omap3_evm_need_extvbus(void)
-{
-	u8 retval = 0;
-
-	/* TODO: verify if cairo handheld platform needs extvbus programming */
-
-	return retval;
-}
-
-/*
  * Routine: board_init
  * Description: Early hardware init.
  */
@@ -45,7 +33,7 @@ int board_init(void)
 {
 	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
 	/* board id for Linux */
-	gd->bd->bi_arch_number = MACH_TYPE_OMAP3_CAIRO;
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
 	/* boot param addr */
 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
 	return 0;
@@ -62,7 +50,7 @@ void set_muxconf_regs(void)
 	MUX_CAIRO();
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
@@ -93,7 +81,8 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
 static const struct ns16550_platdata cairo_serial = {
 	.base = OMAP34XX_UART2,
 	.reg_shift = 2,
-	.clock = V_NS16550_CLK
+	.clock = V_NS16550_CLK,
+	.fcr = UART_FCR_DEFVAL,
 };
 
 U_BOOT_DEVICE(cairo_uart) = {
diff --git a/board/radxa/rock/Kconfig b/board/radxa/rock/Kconfig
new file mode 100644
index 0000000..855b9b6
--- /dev/null
+++ b/board/radxa/rock/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ROCK
+
+config SYS_BOARD
+	default "rock"
+
+config SYS_VENDOR
+	default "radxa"
+
+config SYS_CONFIG_NAME
+	default "rock"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/radxa/rock/MAINTAINERS b/board/radxa/rock/MAINTAINERS
new file mode 100644
index 0000000..c5f59c0
--- /dev/null
+++ b/board/radxa/rock/MAINTAINERS
@@ -0,0 +1,6 @@
+RADXA_ROCK
+M:	Heiko Stuebner <heiko@sntech.de>
+S:	Maintained
+F:	board/radxa/rock
+F:	include/configs/rock.h
+F:	configs/rock_defconfig
diff --git a/board/radxa/rock/Makefile b/board/radxa/rock/Makefile
new file mode 100644
index 0000000..fe94b60
--- /dev/null
+++ b/board/radxa/rock/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Heiko Stuebner
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= rock.o
diff --git a/board/google/chromebook_jerry/jerry.c b/board/radxa/rock/rock.c
index 5119e95..5119e95 100644
--- a/board/google/chromebook_jerry/jerry.c
+++ b/board/radxa/rock/rock.c
diff --git a/board/raspberrypi/rpi/MAINTAINERS b/board/raspberrypi/rpi/MAINTAINERS
index 98c3758..a7eb365 100644
--- a/board/raspberrypi/rpi/MAINTAINERS
+++ b/board/raspberrypi/rpi/MAINTAINERS
@@ -1,6 +1,6 @@
 RPI BOARD
-M:	Stephen Warren <swarren@wwwdotorg.org>
-S:	Maintained
+#M:	Stephen Warren <swarren@wwwdotorg.org>
+S:	Orphaned (Since 2017-07)
 F:	board/raspberrypi/rpi/
 F:	include/configs/rpi.h
 F:	configs/rpi_*defconfig
diff --git a/board/raspberrypi/rpi/Makefile b/board/raspberrypi/rpi/Makefile
index 4ce2c98..dcb25ac 100644
--- a/board/raspberrypi/rpi/Makefile
+++ b/board/raspberrypi/rpi/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	:= rpi.o
+obj-y	+= lowlevel_init.o
diff --git a/board/raspberrypi/rpi/lowlevel_init.S b/board/raspberrypi/rpi/lowlevel_init.S
new file mode 100644
index 0000000..cdbd8e1
--- /dev/null
+++ b/board/raspberrypi/rpi/lowlevel_init.S
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2016
+ * Cédric Schieli <cschieli@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+.align 8
+.global fw_dtb_pointer
+fw_dtb_pointer:
+#ifdef CONFIG_ARM64
+	.dword 0x0
+#else
+	.word 0x0
+#endif
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ * Description: save ATAG/FDT address provided by the firmware at boot time
+ */
+
+.global save_boot_params
+save_boot_params:
+
+	/* The firmware provided ATAG/FDT address can be found in r2/x0 */
+#ifdef CONFIG_ARM64
+	adr	x8, fw_dtb_pointer
+	str	x0, [x8]
+#else
+	str	r2, fw_dtb_pointer
+#endif
+
+	/* Returns */
+	b	save_boot_params_ret
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 6245b36..d3c6ba5 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -8,6 +8,7 @@
 #include <inttypes.h>
 #include <config.h>
 #include <dm.h>
+#include <efi_loader.h>
 #include <fdt_support.h>
 #include <fdt_simplefb.h>
 #include <lcd.h>
@@ -15,53 +16,21 @@
 #include <mmc.h>
 #include <asm/gpio.h>
 #include <asm/arch/mbox.h>
+#include <asm/arch/msg.h>
 #include <asm/arch/sdhci.h>
 #include <asm/global_data.h>
-#include <dm/platform_data/serial_pl01x.h>
 #include <dm/platform_data/serial_bcm283x_mu.h>
 #ifdef CONFIG_ARM64
 #include <asm/armv8/mmu.h>
 #endif
+#include <watchdog.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct bcm2835_gpio_platdata gpio_platdata = {
-	.base = BCM2835_GPIO_BASE,
-};
-
-U_BOOT_DEVICE(bcm2835_gpios) = {
-	.name = "gpio_bcm2835",
-	.platdata = &gpio_platdata,
-};
-
-#ifdef CONFIG_PL01X_SERIAL
-static const struct pl01x_serial_platdata serial_platdata = {
-#ifndef CONFIG_BCM2835
-	.base = 0x3f201000,
-#else
-	.base = 0x20201000,
-#endif
-	.type = TYPE_PL011,
-	.skip_init = true,
-};
-
-U_BOOT_DEVICE(bcm2835_serials) = {
-	.name = "serial_pl01x",
-	.platdata = &serial_platdata,
-};
-#else
-static struct bcm283x_mu_serial_platdata serial_platdata = {
-	.base = 0x3f215040,
-	.clock = 250000000,
-	.skip_init = true,
-};
-
-U_BOOT_DEVICE(bcm2837_serials) = {
-	.name = "serial_bcm283x_mu",
-	.platdata = &serial_platdata,
-};
-#endif
+/* From lowlevel_init.S */
+extern unsigned long fw_dtb_pointer;
 
+/* TODO(sjg@chromium.org): Move these to the msg.c file */
 struct msg_get_arm_mem {
 	struct bcm2835_mbox_hdr hdr;
 	struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
@@ -86,18 +55,18 @@ struct msg_get_mac_address {
 	u32 end_tag;
 };
 
-struct msg_set_power_state {
-	struct bcm2835_mbox_hdr hdr;
-	struct bcm2835_mbox_tag_set_power_state set_power_state;
-	u32 end_tag;
-};
-
 struct msg_get_clock_rate {
 	struct bcm2835_mbox_hdr hdr;
 	struct bcm2835_mbox_tag_get_clock_rate get_clock_rate;
 	u32 end_tag;
 };
 
+#ifdef CONFIG_ARM64
+#define DTB_DIR "broadcom/"
+#else
+#define DTB_DIR ""
+#endif
+
 /*
  * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/
  * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=32733
@@ -116,24 +85,24 @@ struct rpi_model {
 
 static const struct rpi_model rpi_model_unknown = {
 	"Unknown model",
-	"bcm283x-rpi-other.dtb",
+	DTB_DIR "bcm283x-rpi-other.dtb",
 	false,
 };
 
 static const struct rpi_model rpi_models_new_scheme[] = {
 	[0x4] = {
 		"2 Model B",
-		"bcm2836-rpi-2-b.dtb",
+		DTB_DIR "bcm2836-rpi-2-b.dtb",
 		true,
 	},
 	[0x8] = {
 		"3 Model B",
-		"bcm2837-rpi-3-b.dtb",
+		DTB_DIR "bcm2837-rpi-3-b.dtb",
 		true,
 	},
 	[0x9] = {
 		"Zero",
-		"bcm2835-rpi-zero.dtb",
+		DTB_DIR "bcm2835-rpi-zero.dtb",
 		false,
 	},
 };
@@ -141,87 +110,87 @@ static const struct rpi_model rpi_models_new_scheme[] = {
 static const struct rpi_model rpi_models_old_scheme[] = {
 	[0x2] = {
 		"Model B",
-		"bcm2835-rpi-b.dtb",
+		DTB_DIR "bcm2835-rpi-b.dtb",
 		true,
 	},
 	[0x3] = {
 		"Model B",
-		"bcm2835-rpi-b.dtb",
+		DTB_DIR "bcm2835-rpi-b.dtb",
 		true,
 	},
 	[0x4] = {
 		"Model B rev2",
-		"bcm2835-rpi-b-rev2.dtb",
+		DTB_DIR "bcm2835-rpi-b-rev2.dtb",
 		true,
 	},
 	[0x5] = {
 		"Model B rev2",
-		"bcm2835-rpi-b-rev2.dtb",
+		DTB_DIR "bcm2835-rpi-b-rev2.dtb",
 		true,
 	},
 	[0x6] = {
 		"Model B rev2",
-		"bcm2835-rpi-b-rev2.dtb",
+		DTB_DIR "bcm2835-rpi-b-rev2.dtb",
 		true,
 	},
 	[0x7] = {
 		"Model A",
-		"bcm2835-rpi-a.dtb",
+		DTB_DIR "bcm2835-rpi-a.dtb",
 		false,
 	},
 	[0x8] = {
 		"Model A",
-		"bcm2835-rpi-a.dtb",
+		DTB_DIR "bcm2835-rpi-a.dtb",
 		false,
 	},
 	[0x9] = {
 		"Model A",
-		"bcm2835-rpi-a.dtb",
+		DTB_DIR "bcm2835-rpi-a.dtb",
 		false,
 	},
 	[0xd] = {
 		"Model B rev2",
-		"bcm2835-rpi-b-rev2.dtb",
+		DTB_DIR "bcm2835-rpi-b-rev2.dtb",
 		true,
 	},
 	[0xe] = {
 		"Model B rev2",
-		"bcm2835-rpi-b-rev2.dtb",
+		DTB_DIR "bcm2835-rpi-b-rev2.dtb",
 		true,
 	},
 	[0xf] = {
 		"Model B rev2",
-		"bcm2835-rpi-b-rev2.dtb",
+		DTB_DIR "bcm2835-rpi-b-rev2.dtb",
 		true,
 	},
 	[0x10] = {
 		"Model B+",
-		"bcm2835-rpi-b-plus.dtb",
+		DTB_DIR "bcm2835-rpi-b-plus.dtb",
 		true,
 	},
 	[0x11] = {
 		"Compute Module",
-		"bcm2835-rpi-cm.dtb",
+		DTB_DIR "bcm2835-rpi-cm.dtb",
 		false,
 	},
 	[0x12] = {
 		"Model A+",
-		"bcm2835-rpi-a-plus.dtb",
+		DTB_DIR "bcm2835-rpi-a-plus.dtb",
 		false,
 	},
 	[0x13] = {
 		"Model B+",
-		"bcm2835-rpi-b-plus.dtb",
+		DTB_DIR "bcm2835-rpi-b-plus.dtb",
 		true,
 	},
 	[0x14] = {
 		"Compute Module",
-		"bcm2835-rpi-cm.dtb",
+		DTB_DIR "bcm2835-rpi-cm.dtb",
 		false,
 	},
 	[0x15] = {
 		"Model A+",
-		"bcm2835-rpi-a-plus.dtb",
+		DTB_DIR "bcm2835-rpi-a-plus.dtb",
 		false,
 	},
 };
@@ -285,6 +254,31 @@ static void set_fdtfile(void)
 	setenv("fdtfile", fdtfile);
 }
 
+/*
+ * If the firmware provided a valid FDT at boot time, let's expose it in
+ * ${fdt_addr} so it may be passed unmodified to the kernel.
+ */
+static void set_fdt_addr(void)
+{
+	if (getenv("fdt_addr"))
+		return;
+
+	if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC)
+		return;
+
+	setenv_hex("fdt_addr", fw_dtb_pointer);
+}
+
+/*
+ * Prevent relocation from stomping on a firmware provided FDT blob.
+ */
+unsigned long board_get_usable_ram_top(unsigned long total_size)
+{
+	if ((gd->ram_top - fw_dtb_pointer) > SZ_64M)
+		return gd->ram_top;
+	return fw_dtb_pointer & ~0xffff;
+}
+
 static void set_usbethaddr(void)
 {
 	ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1);
@@ -356,6 +350,7 @@ static void set_serial_number(void)
 
 int misc_init_r(void)
 {
+	set_fdt_addr();
 	set_fdtfile();
 	set_usbethaddr();
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
@@ -366,30 +361,6 @@ int misc_init_r(void)
 	return 0;
 }
 
-static int power_on_module(u32 module)
-{
-	ALLOC_CACHE_ALIGN_BUFFER(struct msg_set_power_state, msg_pwr, 1);
-	int ret;
-
-	BCM2835_MBOX_INIT_HDR(msg_pwr);
-	BCM2835_MBOX_INIT_TAG(&msg_pwr->set_power_state,
-			      SET_POWER_STATE);
-	msg_pwr->set_power_state.body.req.device_id = module;
-	msg_pwr->set_power_state.body.req.state =
-		BCM2835_MBOX_SET_POWER_STATE_REQ_ON |
-		BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT;
-
-	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN,
-				     &msg_pwr->hdr);
-	if (ret) {
-		printf("bcm2835: Could not set module %u power state\n",
-		       module);
-		return -1;
-	}
-
-	return 0;
-}
-
 static void get_board_rev(void)
 {
 	ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_board_rev, msg, 1);
@@ -443,15 +414,6 @@ static void get_board_rev(void)
 	printf("RPI %s (0x%x)\n", model->name, revision);
 }
 
-int board_init(void)
-{
-	get_board_rev();
-
-	gd->bd->bi_boot_params = 0x100;
-
-	return power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
-}
-
 #ifndef CONFIG_PL01X_SERIAL
 static bool rpi_is_serial_active(void)
 {
@@ -471,38 +433,51 @@ static bool rpi_is_serial_active(void)
 
 	return true;
 }
-#endif
 
-int board_early_init_f(void)
+/* Disable mini-UART I/O if it's not pinmuxed to our pins.
+ * The firmware only enables it if explicitly done in config.txt: enable_uart=1
+ */
+static void rpi_disable_inactive_uart(void)
 {
-#ifndef CONFIG_PL01X_SERIAL
-	/* Disable mini-UART I/O if it's not pinmuxed to our pins */
-	if (!rpi_is_serial_active())
-		serial_platdata.disabled = true;
-#endif
+	struct udevice *dev;
+	struct bcm283x_mu_serial_platdata *plat;
 
-	return 0;
+	if (uclass_get_device_by_driver(UCLASS_SERIAL,
+					DM_GET_DRIVER(serial_bcm283x_mu),
+					&dev) || !dev)
+		return;
+
+	if (!rpi_is_serial_active()) {
+		plat = dev_get_platdata(dev);
+		plat->disabled = true;
+	}
 }
+#endif
 
-int board_mmc_init(bd_t *bis)
+int board_init(void)
 {
-	ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1);
-	int ret;
+#ifdef CONFIG_HW_WATCHDOG
+	hw_watchdog_init();
+#endif
+#ifndef CONFIG_PL01X_SERIAL
+	rpi_disable_inactive_uart();
+#endif
 
-	power_on_module(BCM2835_MBOX_POWER_DEVID_SDHCI);
+	get_board_rev();
 
-	BCM2835_MBOX_INIT_HDR(msg_clk);
-	BCM2835_MBOX_INIT_TAG(&msg_clk->get_clock_rate, GET_CLOCK_RATE);
-	msg_clk->get_clock_rate.body.req.clock_id = BCM2835_MBOX_CLOCK_ID_EMMC;
+	gd->bd->bi_boot_params = 0x100;
 
-	ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_clk->hdr);
-	if (ret) {
-		printf("bcm2835: Could not query eMMC clock rate\n");
-		return -1;
-	}
+	return bcm2835_power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
+}
 
-	return bcm2835_sdhci_init(BCM2835_SDHCI_BASE,
-				  msg_clk->get_clock_rate.body.resp.rate_hz);
+/*
+ * If the firmware passed a device tree use it for U-Boot.
+ */
+void *board_fdt_blob_setup(void)
+{
+	if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC)
+		return NULL;
+	return (void *)fw_dtb_pointer;
 }
 
 int ft_board_setup(void *blob, bd_t *bd)
@@ -514,5 +489,10 @@ int ft_board_setup(void *blob, bd_t *bd)
 	 */
 	lcd_dt_simplefb_add_node(blob);
 
+#ifdef CONFIG_EFI_LOADER
+	/* Reserve the spin table */
+	efi_add_memory_map(0, 1, EFI_RESERVED_MEMORY_TYPE, 0);
+#endif
+
 	return 0;
 }
diff --git a/board/renesas/MigoR/Makefile b/board/renesas/MigoR/Makefile
index b4691a1..0686f97 100644
--- a/board/renesas/MigoR/Makefile
+++ b/board/renesas/MigoR/Makefile
@@ -10,4 +10,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y	:= migo_r.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/renesas/MigoR/migo_r.c b/board/renesas/MigoR/migo_r.c
index fa2bf78..6409a73 100644
--- a/board/renesas/MigoR/migo_r.c
+++ b/board/renesas/MigoR/migo_r.c
@@ -15,8 +15,6 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 int checkboard(void)
 {
 	puts("BOARD: Renesas MigoR\n");
@@ -28,14 +26,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init (void)
-{
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-	return 0;
-}
-
 void led_set_state (unsigned short value)
 {
 }
diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
index a1a26a6..b35b6a3 100644
--- a/board/renesas/alt/alt.c
+++ b/board/renesas/alt/alt.c
@@ -13,7 +13,7 @@
 #include <asm/processor.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/arch/rmobile.h>
diff --git a/board/renesas/ap325rxa/Makefile b/board/renesas/ap325rxa/Makefile
index ff72de9..18e1ed5 100644
--- a/board/renesas/ap325rxa/Makefile
+++ b/board/renesas/ap325rxa/Makefile
@@ -9,4 +9,4 @@
 #
 
 obj-y	:= ap325rxa.o cpld-ap325rxa.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/renesas/ap325rxa/ap325rxa.c b/board/renesas/ap325rxa/ap325rxa.c
index 518ad7b..218d479 100644
--- a/board/renesas/ap325rxa/ap325rxa.c
+++ b/board/renesas/ap325rxa/ap325rxa.c
@@ -10,8 +10,6 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 /* PRI control register */
 #define PRPRICR5	0xFF800048 /* LMB */
 #define PRPRICR5_D	0x2a
@@ -130,14 +128,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-	return 0;
-}
-
 void led_set_state(unsigned short value)
 {
 }
diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c
index b2e2e3b..5156eaf 100644
--- a/board/renesas/blanche/blanche.c
+++ b/board/renesas/blanche/blanche.c
@@ -15,7 +15,7 @@
 #include <asm/processor.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/arch/rmobile.h>
@@ -136,7 +136,7 @@ void s_init(void)
 	/* SCIF Init */
 	pin_init();
 
-#if !defined(CONFIG_SYS_NO_FLASH)
+#if defined(CONFIG_MTD_NOR_FLASH)
 	struct rcar_lbsc *lbsc = (struct rcar_lbsc *)LBSC_BASE;
 	struct rcar_dbsc3 *dbsc3_0 = (struct rcar_dbsc3 *)DBSC3_0_BASE;
 
@@ -300,7 +300,7 @@ void s_init(void)
 
 	/* This locks the access to the PHY unit registers */
 	writel(0x00000000, &dbsc3_0->dbpdlck);
-#endif /* CONFIG_SYS_NO_FLASH */
+#endif /* CONFIG_MTD_NOR_FLASH */
 
 }
 
@@ -368,21 +368,21 @@ int board_init(void)
 	gpio_request(GPIO_FN_A17, NULL);
 	gpio_request(GPIO_FN_A18, NULL);
 	gpio_request(GPIO_FN_A19, NULL);
-#if defined(CONFIG_SYS_NO_FLASH)
+#if !defined(CONFIG_MTD_NOR_FLASH)
 	gpio_request(GPIO_FN_MOSI_IO0, NULL);
 	gpio_request(GPIO_FN_MISO_IO1, NULL);
 	gpio_request(GPIO_FN_IO2, NULL);
 	gpio_request(GPIO_FN_IO3, NULL);
 	gpio_request(GPIO_FN_SPCLK, NULL);
 	gpio_request(GPIO_FN_SSL, NULL);
-#else	/* CONFIG_SYS_NO_FLASH */
+#else	/* CONFIG_MTD_NOR_FLASH */
 	gpio_request(GPIO_FN_A20, NULL);
 	gpio_request(GPIO_FN_A21, NULL);
 	gpio_request(GPIO_FN_A22, NULL);
 	gpio_request(GPIO_FN_A23, NULL);
 	gpio_request(GPIO_FN_A24, NULL);
 	gpio_request(GPIO_FN_A25, NULL);
-#endif	/* CONFIG_SYS_NO_FLASH */
+#endif	/* CONFIG_MTD_NOR_FLASH */
 
 	gpio_request(GPIO_FN_CS1_A26, NULL);
 	gpio_request(GPIO_FN_EX_CS0, NULL);
diff --git a/board/renesas/ecovec/Makefile b/board/renesas/ecovec/Makefile
index 943fa47..2e6fb50 100644
--- a/board/renesas/ecovec/Makefile
+++ b/board/renesas/ecovec/Makefile
@@ -5,4 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y := ecovec.o
-obj-y += lowlevel_init.o
+extra-y += lowlevel_init.o
diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c
index d862d99..28b557a 100644
--- a/board/renesas/ecovec/ecovec.c
+++ b/board/renesas/ecovec/ecovec.c
@@ -22,16 +22,6 @@ int checkboard(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-	return 0;
-}
-
 static void debug_led(u8 led)
 {
 	/* PDGR[0-4] is debug LED */
diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c
index 3a8bf86..359f95e 100644
--- a/board/renesas/gose/gose.c
+++ b/board/renesas/gose/gose.c
@@ -13,7 +13,7 @@
 #include <asm/processor.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/arch/rmobile.h>
diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
index b741e2e..dd62145 100644
--- a/board/renesas/koelsch/koelsch.c
+++ b/board/renesas/koelsch/koelsch.c
@@ -14,7 +14,7 @@
 #include <asm/processor.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/arch/rmobile.h>
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index 6fed2f9..2ada816 100644
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c
@@ -16,7 +16,7 @@
 #include <asm/processor.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/arch/rmobile.h>
diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c
index f6467ee..926a657 100644
--- a/board/renesas/porter/porter.c
+++ b/board/renesas/porter/porter.c
@@ -14,7 +14,7 @@
 #include <asm/processor.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/arch/rmobile.h>
diff --git a/board/renesas/r0p7734/Makefile b/board/renesas/r0p7734/Makefile
index 1f24d92..bfe52d6 100644
--- a/board/renesas/r0p7734/Makefile
+++ b/board/renesas/r0p7734/Makefile
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y	:= r0p7734.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/renesas/r0p7734/r0p7734.c b/board/renesas/r0p7734/r0p7734.c
index 2e31ba6..d0b4537 100644
--- a/board/renesas/r0p7734/r0p7734.c
+++ b/board/renesas/r0p7734/r0p7734.c
@@ -11,8 +11,6 @@
 #include <netdev.h>
 #include <i2c.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #define MODEMR			(0xFFCC0020)
 #define MODEMR_MASK		(0x6)
 #define MODEMR_533MHZ	(0x2)
@@ -46,26 +44,7 @@ int board_init(void)
 
 int board_late_init(void)
 {
-	u8 mac[6];
-
-	/* Read Mac Address and set*/
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-	i2c_set_bus_num(CONFIG_SYS_I2C_MODULE);
-
-	/* Read MAC address */
-	i2c_read(0x50, 0x10, 0, mac, 6);
-
-	if (is_valid_ethaddr(mac))
-		eth_setenv_enetaddr("ethaddr", mac);
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+	printf("Cannot get MAC address from I2C\n");
 
 	return 0;
 }
diff --git a/board/renesas/r2dplus/Makefile b/board/renesas/r2dplus/Makefile
index acffb6d..4021ab6 100644
--- a/board/renesas/r2dplus/Makefile
+++ b/board/renesas/r2dplus/Makefile
@@ -6,4 +6,4 @@
 #
 
 obj-y	:= r2dplus.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/renesas/r2dplus/r2dplus.c b/board/renesas/r2dplus/r2dplus.c
index 249c35f..d6fb4da 100644
--- a/board/renesas/r2dplus/r2dplus.c
+++ b/board/renesas/r2dplus/r2dplus.c
@@ -12,8 +12,6 @@
 #include <asm/io.h>
 #include <asm/pci.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 int checkboard(void)
 {
 	puts("BOARD: Renesas Solutions R2D Plus\n");
@@ -25,14 +23,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-	return 0;
-}
-
 int board_late_init(void)
 {
 	return 0;
diff --git a/board/renesas/r7780mp/Makefile b/board/renesas/r7780mp/Makefile
index 8dab435..66813a3 100644
--- a/board/renesas/r7780mp/Makefile
+++ b/board/renesas/r7780mp/Makefile
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y	:= r7780mp.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/renesas/r7780mp/r7780mp.c b/board/renesas/r7780mp/r7780mp.c
index 783352d..de259f5 100644
--- a/board/renesas/r7780mp/r7780mp.c
+++ b/board/renesas/r7780mp/r7780mp.c
@@ -13,8 +13,6 @@
 #include <netdev.h>
 #include "r7780mp.h"
 
-DECLARE_GLOBAL_DATA_PTR;
-
 int checkboard(void)
 {
 #if defined(CONFIG_R7780MP)
@@ -33,14 +31,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-	return 0;
-}
-
 void led_set_state(unsigned short value)
 {
 
diff --git a/board/renesas/rsk7203/Makefile b/board/renesas/rsk7203/Makefile
index 16acfaf..08139a2 100644
--- a/board/renesas/rsk7203/Makefile
+++ b/board/renesas/rsk7203/Makefile
@@ -7,4 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y	:= rsk7203.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/renesas/rsk7203/rsk7203.c b/board/renesas/rsk7203/rsk7203.c
index 8800371..72c562d 100644
--- a/board/renesas/rsk7203/rsk7203.c
+++ b/board/renesas/rsk7203/rsk7203.c
@@ -13,8 +13,6 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 int checkboard(void)
 {
 	puts("BOARD: Renesas Technology RSK7203\n");
@@ -26,14 +24,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-	return 0;
-}
-
 void led_set_state(unsigned short value)
 {
 }
diff --git a/board/renesas/rsk7264/Makefile b/board/renesas/rsk7264/Makefile
index 7ada697..2a845a0 100644
--- a/board/renesas/rsk7264/Makefile
+++ b/board/renesas/rsk7264/Makefile
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y	:= rsk7264.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/renesas/rsk7264/rsk7264.c b/board/renesas/rsk7264/rsk7264.c
index d938b3a..4ebb27b 100644
--- a/board/renesas/rsk7264/rsk7264.c
+++ b/board/renesas/rsk7264/rsk7264.c
@@ -14,8 +14,6 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 int checkboard(void)
 {
 	puts("BOARD: Renesas Technology RSK7264\n");
@@ -27,14 +25,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-	return 0;
-}
-
 void led_set_state(unsigned short value)
 {
 }
diff --git a/board/renesas/rsk7269/Makefile b/board/renesas/rsk7269/Makefile
index 0f053d8..86b2263 100644
--- a/board/renesas/rsk7269/Makefile
+++ b/board/renesas/rsk7269/Makefile
@@ -5,4 +5,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y	:= rsk7269.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/renesas/rsk7269/rsk7269.c b/board/renesas/rsk7269/rsk7269.c
index ae32b6a..0066f9f 100644
--- a/board/renesas/rsk7269/rsk7269.c
+++ b/board/renesas/rsk7269/rsk7269.c
@@ -15,8 +15,6 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 int checkboard(void)
 {
 	puts("BOARD: Renesas RSK7269\n");
@@ -28,14 +26,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-	return 0;
-}
-
 void led_set_state(unsigned short value)
 {
 }
diff --git a/board/renesas/salvator-x/MAINTAINERS b/board/renesas/salvator-x/MAINTAINERS
index abd05c8..f7b98fb 100644
--- a/board/renesas/salvator-x/MAINTAINERS
+++ b/board/renesas/salvator-x/MAINTAINERS
@@ -3,4 +3,5 @@ M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 S:	Maintained
 F:	board/renesas/salvator-x/
 F:	include/configs/salvator-x.h
-F:	configs/salvator-x_defconfig
+F:	configs/r8a7795_salvator-x_defconfig
+F:	configs/r8a7796_salvator-x_defconfig
diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index 47242c6..6270de4 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -1,8 +1,8 @@
 /*
  * board/renesas/salvator-x/salvator-x.c
- *     This file is Salvator-X board support.
+ *     This file is Salvator-X/Salvator-XS board support.
  *
- * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015-2017 Renesas Electronics Corporation
  * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  *
  * SPDX-License-Identifier: GPL-2.0+
@@ -16,12 +16,13 @@
 #include <asm/processor.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/rmobile.h>
 #include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
 #include <i2c.h>
 #include <mmc.h>
 
@@ -44,10 +45,21 @@ void s_init(void)
 	writel(0xFFFFFFFF, CPGWPR);
 }
 
-#define GSX_MSTP112	(1 << 12)	/* 3DG */
-#define TMU0_MSTP125	(1 << 25)	/* secure */
-#define TMU1_MSTP124	(1 << 24)	/* non-secure */
-#define SCIF2_MSTP310	(1 << 10)	/* SCIF2 */
+#define GSX_MSTP112		BIT(12)	/* 3DG */
+#define TMU0_MSTP125		BIT(25)	/* secure */
+#define TMU1_MSTP124		BIT(24)	/* non-secure */
+#define SCIF2_MSTP310		BIT(10)	/* SCIF2 */
+#define ETHERAVB_MSTP812	BIT(12)
+#define DVFS_MSTP926		BIT(26)
+#define SD0_MSTP314		BIT(14)
+#define SD1_MSTP313		BIT(13)
+#define SD2_MSTP312		BIT(12)	/* either MMC0 */
+#define SD3_MSTP311		BIT(11)	/* either MMC1 */
+
+#define SD0CKCR			0xE6150074
+#define SD1CKCR			0xE6150078
+#define SD2CKCR			0xE6150268
+#define SD3CKCR			0xE615026C
 
 int board_early_init_f(void)
 {
@@ -55,7 +67,22 @@ int board_early_init_f(void)
 	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
 	/* SCIF2 */
 	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
+	/* EHTERAVB */
+	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
+	/* eMMC */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
+	/* SDHI0, 3 */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);
+
+	writel(0, SD0CKCR);
+	writel(0, SD1CKCR);
+	writel(0, SD2CKCR);
+	writel(0, SD3CKCR);
 
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+	/* DVFS for reset */
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+#endif
 	return 0;
 }
 
@@ -65,29 +92,203 @@ int board_early_init_f(void)
 /* -/W 32 Power resume control register 2 (3DG) */
 #define	SYSC_PWRONCR2	0xE618010C
 
-DECLARE_GLOBAL_DATA_PTR;
 int board_init(void)
 {
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
 
 	/* Init PFC controller */
+#if defined(CONFIG_R8A7795)
 	r8a7795_pinmux_init();
+#elif defined(CONFIG_R8A7796)
+	r8a7796_pinmux_init();
+#endif
 
+#if defined(CONFIG_R8A7795)
 	/* GSX: force power and clock supply */
 	writel(0x0000001F, SYSC_PWRONCR2);
 	while (readl(SYSC_PWRSR2) != 0x000003E0)
 		mdelay(20);
 
 	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
+#endif
+
+	/* USB1 pull-up */
+	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
+
+#ifdef CONFIG_RAVB
+	/* EtherAVB Enable */
+	/* GPSR2 */
+	gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
+	gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
+	gpio_request(GPIO_GFN_AVB_LINK, NULL);
+	gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
+	gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
+	gpio_request(GPIO_GFN_AVB_MDC, NULL);
+
+	/* IPSR0 */
+	gpio_request(GPIO_IFN_AVB_MDC, NULL);
+	gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
+	gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
+	gpio_request(GPIO_IFN_AVB_LINK, NULL);
+	gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
+	gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
+	/* IPSR1 */
+	gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
+	/* IPSR2 */
+	gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
+	/* IPSR3 */
+	gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);
+
+#if defined(CONFIG_R8A7795)
+	/* USB2_OVC */
+	gpio_request(GPIO_GP_6_15, NULL);
+	gpio_direction_input(GPIO_GP_6_15);
+
+	/* USB2_PWEN */
+	gpio_request(GPIO_GP_6_14, NULL);
+	gpio_direction_output(GPIO_GP_6_14, 1);
+	gpio_set_value(GPIO_GP_6_14, 1);
+#endif
+	/* AVB_PHY_RST */
+	gpio_request(GPIO_GP_2_10, NULL);
+	gpio_direction_output(GPIO_GP_2_10, 0);
+	mdelay(20);
+	gpio_set_value(GPIO_GP_2_10, 1);
+	udelay(1);
+#endif
 
 	return 0;
 }
 
+static struct eth_pdata salvator_x_ravb_platdata = {
+	.iobase		= 0xE6800000,
+	.phy_interface	= 0,
+	.max_speed	= 1000,
+};
+
+U_BOOT_DEVICE(salvator_x_ravb) = {
+	.name		= "ravb",
+	.platdata	= &salvator_x_ravb_platdata,
+};
+
+#ifdef CONFIG_SH_SDHI
+int board_mmc_init(bd_t *bis)
+{
+	int ret = -ENODEV;
+
+	/* SDHI0 */
+	gpio_request(GPIO_GFN_SD0_DAT0, NULL);
+	gpio_request(GPIO_GFN_SD0_DAT1, NULL);
+	gpio_request(GPIO_GFN_SD0_DAT2, NULL);
+	gpio_request(GPIO_GFN_SD0_DAT3, NULL);
+	gpio_request(GPIO_GFN_SD0_CLK, NULL);
+	gpio_request(GPIO_GFN_SD0_CMD, NULL);
+	gpio_request(GPIO_GFN_SD0_CD, NULL);
+	gpio_request(GPIO_GFN_SD0_WP, NULL);
+
+	gpio_request(GPIO_GP_5_2, NULL);
+	gpio_request(GPIO_GP_5_1, NULL);
+	gpio_direction_output(GPIO_GP_5_2, 1);	/* power on */
+	gpio_direction_output(GPIO_GP_5_1, 1);	/* 1: 3.3V, 0: 1.8V */
+
+	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
+			   SH_SDHI_QUIRK_64BIT_BUF);
+	if (ret)
+		return ret;
+
+	/* SDHI1/SDHI2 eMMC */
+	gpio_request(GPIO_GFN_SD1_DAT0, NULL);
+	gpio_request(GPIO_GFN_SD1_DAT1, NULL);
+	gpio_request(GPIO_GFN_SD1_DAT2, NULL);
+	gpio_request(GPIO_GFN_SD1_DAT3, NULL);
+	gpio_request(GPIO_GFN_SD2_DAT0, NULL);
+	gpio_request(GPIO_GFN_SD2_DAT1, NULL);
+	gpio_request(GPIO_GFN_SD2_DAT2, NULL);
+	gpio_request(GPIO_GFN_SD2_DAT3, NULL);
+	gpio_request(GPIO_GFN_SD2_CLK, NULL);
+#if defined(CONFIG_R8A7795)
+	gpio_request(GPIO_GFN_SD2_CMD, NULL);
+#elif defined(CONFIG_R8A7796)
+	gpio_request(GPIO_FN_SD2_CMD, NULL);
+#else
+#error Only R8A7795 and R87796 is supported
+#endif
+	gpio_request(GPIO_GP_5_3, NULL);
+	gpio_request(GPIO_GP_5_9, NULL);
+	gpio_direction_output(GPIO_GP_5_3, 0);	/* 1: 3.3V, 0: 1.8V */
+	gpio_direction_output(GPIO_GP_5_9, 0);	/* 1: 3.3V, 0: 1.8V */
+
+	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1,
+			   SH_SDHI_QUIRK_64BIT_BUF);
+	if (ret)
+		return ret;
+
+#if defined(CONFIG_R8A7795)
+	/* SDHI3 */
+	gpio_request(GPIO_GFN_SD3_DAT0, NULL);	/* GP_4_9 */
+	gpio_request(GPIO_GFN_SD3_DAT1, NULL);	/* GP_4_10 */
+	gpio_request(GPIO_GFN_SD3_DAT2, NULL);	/* GP_4_11 */
+	gpio_request(GPIO_GFN_SD3_DAT3, NULL);	/* GP_4_12 */
+	gpio_request(GPIO_GFN_SD3_CLK, NULL);	/* GP_4_7 */
+	gpio_request(GPIO_GFN_SD3_CMD, NULL);	/* GP_4_8 */
+#elif defined(CONFIG_R8A7796)
+	gpio_request(GPIO_FN_SD3_DAT0, NULL);	/* GP_4_9 */
+	gpio_request(GPIO_FN_SD3_DAT1, NULL);	/* GP_4_10 */
+	gpio_request(GPIO_FN_SD3_DAT2, NULL);	/* GP_4_11 */
+	gpio_request(GPIO_FN_SD3_DAT3, NULL);	/* GP_4_12 */
+	gpio_request(GPIO_FN_SD3_CLK, NULL);	/* GP_4_7 */
+	gpio_request(GPIO_FN_SD3_CMD, NULL);	/* GP_4_8 */
+#else
+#error Only R8A7795 and R87796 is supported
+#endif
+	/* IPSR10 */
+	gpio_request(GPIO_FN_SD3_CD, NULL);
+	gpio_request(GPIO_FN_SD3_WP, NULL);
+
+	gpio_request(GPIO_GP_3_15, NULL);
+	gpio_request(GPIO_GP_3_14, NULL);
+	gpio_direction_output(GPIO_GP_3_15, 1);	/* power on */
+	gpio_direction_output(GPIO_GP_3_14, 1);	/* 1: 3.3V, 0: 1.8V */
+
+	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI3_BASE, 2,
+			   SH_SDHI_QUIRK_64BIT_BUF);
+	return ret;
+}
+#endif
+
 int dram_init(void)
 {
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+	gd->ram_size += PHYS_SDRAM_2_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+	gd->ram_size += PHYS_SDRAM_3_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 4)
+	gd->ram_size += PHYS_SDRAM_4_SIZE;
+#endif
+
+	return 0;
+}
 
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 4)
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+#endif
 	return 0;
 }
 
@@ -103,15 +304,19 @@ const struct rmobile_sysinfo sysinfo = {
 
 void reset_cpu(ulong addr)
 {
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+	i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
+#else
 	/* only CA57 ? */
 	writel(RST_CODE, RST_CA57RESCNT);
+#endif
 }
 
 static const struct sh_serial_platdata serial_platdata = {
 	.base = SCIF2_BASE,
 	.type = PORT_SCIF,
-	.clk = 14745600,		/* 0xE10000 */
-	.clk_mode = EXT_CLK,
+	.clk = CONFIG_SH_SCIF_CLK_FREQ,
+	.clk_mode = INT_CLK,
 };
 
 U_BOOT_DEVICE(salvator_x_scif2) = {
diff --git a/board/renesas/sh7752evb/Makefile b/board/renesas/sh7752evb/Makefile
index 856af81..fb6eeec 100644
--- a/board/renesas/sh7752evb/Makefile
+++ b/board/renesas/sh7752evb/Makefile
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y	:= sh7752evb.o spi-boot.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c
index 3aad532..525d979 100644
--- a/board/renesas/sh7752evb/sh7752evb.c
+++ b/board/renesas/sh7752evb/sh7752evb.c
@@ -159,17 +159,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-
-	return 0;
-}
-
 int board_mmc_init(bd_t *bis)
 {
 	struct gpio_regs *gpio = GPIO_BASE;
diff --git a/board/renesas/sh7752evb/u-boot.lds b/board/renesas/sh7752evb/u-boot.lds
deleted file mode 100644
index 6cd4056..0000000
--- a/board/renesas/sh7752evb/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2012
- * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
-	/*
-	 * entry and reloct_dst will be provided via ldflags
-	 */
-	. = .;
-
-	PROVIDE (_ftext = .);
-	PROVIDE (_fcode = .);
-	PROVIDE (_start = .);
-
-	.text :
-	{
-		KEEP(arch/sh/cpu/sh4/start.o		(.text))
-		*(.spiboot1.text)
-		*(.spiboot2.text)
-		. = ALIGN(8192);
-		common/env_embedded.o	(.ppcenv)
-		. = ALIGN(8192);
-		common/env_embedded.o	(.ppcenvr)
-		. = ALIGN(8192);
-		*(.text)
-		. = ALIGN(4);
-	} =0xFF
-	PROVIDE (_ecode = .);
-	.rodata :
-	{
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-		. = ALIGN(4);
-	}
-	PROVIDE (_etext = .);
-
-
-	PROVIDE (_fdata = .);
-	.data :
-	{
-		*(.data)
-		. = ALIGN(4);
-	}
-	PROVIDE (_edata = .);
-
-	PROVIDE (_fgot = .);
-	.got :
-	{
-		*(.got)
-		. = ALIGN(4);
-	}
-	PROVIDE (_egot = .);
-
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	PROVIDE (__init_end = .);
-	PROVIDE (reloc_dst_end = .);
-	/* _reloc_dst_end = .; */
-
-	PROVIDE (bss_start = .);
-	PROVIDE (__bss_start = .);
-	.bss (NOLOAD) :
-	{
-		*(.bss)
-		. = ALIGN(4);
-	}
-	PROVIDE (bss_end = .);
-
-	PROVIDE (__bss_end = .);
-}
diff --git a/board/renesas/sh7753evb/Makefile b/board/renesas/sh7753evb/Makefile
index f7c8e94..4293142 100644
--- a/board/renesas/sh7753evb/Makefile
+++ b/board/renesas/sh7753evb/Makefile
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y	:= sh7753evb.o spi-boot.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/renesas/sh7753evb/sh7753evb.c b/board/renesas/sh7753evb/sh7753evb.c
index 52a1906..3d1eeda 100644
--- a/board/renesas/sh7753evb/sh7753evb.c
+++ b/board/renesas/sh7753evb/sh7753evb.c
@@ -175,17 +175,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-
-	return 0;
-}
-
 int board_mmc_init(bd_t *bis)
 {
 	struct gpio_regs *gpio = GPIO_BASE;
diff --git a/board/renesas/sh7753evb/u-boot.lds b/board/renesas/sh7753evb/u-boot.lds
deleted file mode 100644
index 6cd4056..0000000
--- a/board/renesas/sh7753evb/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2012
- * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
-	/*
-	 * entry and reloct_dst will be provided via ldflags
-	 */
-	. = .;
-
-	PROVIDE (_ftext = .);
-	PROVIDE (_fcode = .);
-	PROVIDE (_start = .);
-
-	.text :
-	{
-		KEEP(arch/sh/cpu/sh4/start.o		(.text))
-		*(.spiboot1.text)
-		*(.spiboot2.text)
-		. = ALIGN(8192);
-		common/env_embedded.o	(.ppcenv)
-		. = ALIGN(8192);
-		common/env_embedded.o	(.ppcenvr)
-		. = ALIGN(8192);
-		*(.text)
-		. = ALIGN(4);
-	} =0xFF
-	PROVIDE (_ecode = .);
-	.rodata :
-	{
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-		. = ALIGN(4);
-	}
-	PROVIDE (_etext = .);
-
-
-	PROVIDE (_fdata = .);
-	.data :
-	{
-		*(.data)
-		. = ALIGN(4);
-	}
-	PROVIDE (_edata = .);
-
-	PROVIDE (_fgot = .);
-	.got :
-	{
-		*(.got)
-		. = ALIGN(4);
-	}
-	PROVIDE (_egot = .);
-
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	PROVIDE (__init_end = .);
-	PROVIDE (reloc_dst_end = .);
-	/* _reloc_dst_end = .; */
-
-	PROVIDE (bss_start = .);
-	PROVIDE (__bss_start = .);
-	.bss (NOLOAD) :
-	{
-		*(.bss)
-		. = ALIGN(4);
-	}
-	PROVIDE (bss_end = .);
-
-	PROVIDE (__bss_end = .);
-}
diff --git a/board/renesas/sh7757lcr/Makefile b/board/renesas/sh7757lcr/Makefile
index 1fa3992..f1ce0f6 100644
--- a/board/renesas/sh7757lcr/Makefile
+++ b/board/renesas/sh7757lcr/Makefile
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y	:= sh7757lcr.o spi-boot.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/renesas/sh7757lcr/sh7757lcr.c b/board/renesas/sh7757lcr/sh7757lcr.c
index ddcf275..0a04a9d 100644
--- a/board/renesas/sh7757lcr/sh7757lcr.c
+++ b/board/renesas/sh7757lcr/sh7757lcr.c
@@ -224,31 +224,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-	printf("    Physical address\n");
-	printf("    0x%08x - 0x%08x : Accessible Space as ECC Area\n",
-		SH7757LCR_SDRAM_PHYS_TOP,
-		SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE - 1);
-	printf("    0x%08x - 0x%08x : No Access Area\n",
-		SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE,
-		SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE * 2 - 1);
-	printf("    0x%08x - 0x%08x : Non-ECC Area for DVC/AVC\n",
-		SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2,
-		SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2 +
-			SH7757LCR_SDRAM_DVC_SIZE - 1);
-	printf("    0x%08x - 0x%08x : Non-ECC Area for G200eR2\n",
-		SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET,
-		SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET + 0x00ffffff);
-
-	return 0;
-}
-
 int board_mmc_init(bd_t *bis)
 {
 	return mmcif_mmc_init();
diff --git a/board/renesas/sh7757lcr/u-boot.lds b/board/renesas/sh7757lcr/u-boot.lds
deleted file mode 100644
index d701367..0000000
--- a/board/renesas/sh7757lcr/u-boot.lds
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright (C) 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * Copyright (C) 2011
- * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
-OUTPUT_ARCH(sh)
-ENTRY(_start)
-
-SECTIONS
-{
-	/*
-	 * entry and reloct_dst will be provided via ldflags
-	 */
-	. = .;
-
-	PROVIDE (_ftext = .);
-	PROVIDE (_fcode = .);
-	PROVIDE (_start = .);
-
-	.text :
-	{
-		KEEP(arch/sh/cpu/sh4/start.o		(.text))
-		*(.spiboot1.text)
-		*(.spiboot2.text)
-		. = ALIGN(8192);
-		common/env_embedded.o	(.ppcenv)
-		. = ALIGN(8192);
-		common/env_embedded.o	(.ppcenvr)
-		. = ALIGN(8192);
-		*(.text)
-		. = ALIGN(4);
-	} =0xFF
-	PROVIDE (_ecode = .);
-	.rodata :
-	{
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-		. = ALIGN(4);
-	}
-	PROVIDE (_etext = .);
-
-
-	PROVIDE (_fdata = .);
-	.data :
-	{
-		*(.data)
-		. = ALIGN(4);
-	}
-	PROVIDE (_edata = .);
-
-	PROVIDE (_fgot = .);
-	.got :
-	{
-		*(.got)
-		. = ALIGN(4);
-	}
-	PROVIDE (_egot = .);
-
-
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	PROVIDE (__init_end = .);
-	PROVIDE (reloc_dst_end = .);
-	/* _reloc_dst_end = .; */
-
-	PROVIDE (bss_start = .);
-	PROVIDE (__bss_start = .);
-	.bss (NOLOAD) :
-	{
-		*(.bss)
-		. = ALIGN(4);
-	}
-	PROVIDE (bss_end = .);
-
-	PROVIDE (__bss_end = .);
-}
diff --git a/board/renesas/sh7763rdp/Makefile b/board/renesas/sh7763rdp/Makefile
index cbf38bb..13f7ae9 100644
--- a/board/renesas/sh7763rdp/Makefile
+++ b/board/renesas/sh7763rdp/Makefile
@@ -9,4 +9,4 @@
 #
 
 obj-y	:= sh7763rdp.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/renesas/sh7763rdp/sh7763rdp.c b/board/renesas/sh7763rdp/sh7763rdp.c
index 9658a5e..d83e2f8 100644
--- a/board/renesas/sh7763rdp/sh7763rdp.c
+++ b/board/renesas/sh7763rdp/sh7763rdp.c
@@ -12,8 +12,6 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #define CPU_CMDREG	0xB1000006
 #define PDCR        0xffef0006
 #define PECR        0xffef0008
@@ -51,14 +49,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-	return 0;
-}
-
 void led_set_state(unsigned short value)
 {
 }
diff --git a/board/renesas/sh7785lcr/Makefile b/board/renesas/sh7785lcr/Makefile
index e8cfb05..1bf5d53 100644
--- a/board/renesas/sh7785lcr/Makefile
+++ b/board/renesas/sh7785lcr/Makefile
@@ -4,4 +4,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y	:= sh7785lcr.o selfcheck.o rtl8169_mac.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/renesas/sh7785lcr/sh7785lcr.c b/board/renesas/sh7785lcr/sh7785lcr.c
index 622e602..a1a0301 100644
--- a/board/renesas/sh7785lcr/sh7785lcr.c
+++ b/board/renesas/sh7785lcr/sh7785lcr.c
@@ -10,8 +10,6 @@
 #include <asm/pci.h>
 #include <netdev.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 int checkboard(void)
 {
 	puts("BOARD: Renesas Technology Corp. R0P7785LC0011RL\n");
@@ -23,14 +21,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-	return 0;
-}
-
 static struct pci_controller hose;
 void pci_init_board(void)
 {
diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c
index 4ec3f92..e13a38f 100644
--- a/board/renesas/silk/silk.c
+++ b/board/renesas/silk/silk.c
@@ -14,7 +14,7 @@
 #include <asm/processor.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/arch/rmobile.h>
diff --git a/board/renesas/stout/stout.c b/board/renesas/stout/stout.c
index 672a730..fe8dd3d 100644
--- a/board/renesas/stout/stout.c
+++ b/board/renesas/stout/stout.c
@@ -17,7 +17,7 @@
 #include <asm/processor.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/arch/rmobile.h>
diff --git a/board/renesas/ulcb/Kconfig b/board/renesas/ulcb/Kconfig
new file mode 100644
index 0000000..1e9a10d
--- /dev/null
+++ b/board/renesas/ulcb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_ULCB
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "ulcb"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "ulcb"
+
+endif
diff --git a/board/renesas/ulcb/MAINTAINERS b/board/renesas/ulcb/MAINTAINERS
new file mode 100644
index 0000000..e7cdc52
--- /dev/null
+++ b/board/renesas/ulcb/MAINTAINERS
@@ -0,0 +1,7 @@
+ULCB BOARD
+M:	Marek Vasut <marek.vasut+renesas@gmail.com>
+S:	Maintained
+F:	board/renesas/ulcb/
+F:	include/configs/ulcb.h
+F:	configs/r8a7795_ulcb_defconfig
+F:	configs/r8a7796_ulcb_defconfig
diff --git a/board/renesas/ulcb/Makefile b/board/renesas/ulcb/Makefile
new file mode 100644
index 0000000..6fe0b48
--- /dev/null
+++ b/board/renesas/ulcb/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/ulcb/Makefile
+#
+# Copyright (C) 2017 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y	:= ulcb.o cpld.o ../rcar-common/common.o
diff --git a/board/renesas/ulcb/cpld.c b/board/renesas/ulcb/cpld.c
new file mode 100644
index 0000000..f9384b0
--- /dev/null
+++ b/board/renesas/ulcb/cpld.c
@@ -0,0 +1,167 @@
+/*
+ * ULCB board CPLD access support
+ *
+ * Copyright (C) 2017 Renesas Electronics Corporation
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#define SCLK			GPIO_GP_6_8
+#define SSTBZ			GPIO_GP_2_3
+#define MOSI			GPIO_GP_6_7
+#define MISO			GPIO_GP_6_10
+
+#define CPLD_ADDR_MODE		0x00 /* RW */
+#define CPLD_ADDR_MUX		0x02 /* RW */
+#define CPLD_ADDR_DIPSW6	0x08 /* R */
+#define CPLD_ADDR_RESET		0x80 /* RW */
+#define CPLD_ADDR_VERSION	0xFF /* R */
+
+static int cpld_initialized;
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	/* Always valid */
+	return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	/* Always active */
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	/* Always active */
+}
+
+void ulcb_softspi_sda(int set)
+{
+	gpio_set_value(MOSI, set);
+}
+
+void ulcb_softspi_scl(int set)
+{
+	gpio_set_value(SCLK, set);
+}
+
+unsigned char ulcb_softspi_read(void)
+{
+	return !!gpio_get_value(MISO);
+}
+
+static void cpld_rw(u8 write)
+{
+	gpio_set_value(MOSI, write);
+	gpio_set_value(SSTBZ, 0);
+	gpio_set_value(SCLK, 1);
+	gpio_set_value(SCLK, 0);
+	gpio_set_value(SSTBZ, 1);
+}
+
+static u32 cpld_read(u8 addr)
+{
+	u32 data = 0;
+
+	spi_xfer(NULL, 8, &addr, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+
+	cpld_rw(0);
+
+	spi_xfer(NULL, 32, NULL, &data, SPI_XFER_BEGIN | SPI_XFER_END);
+
+	return swab32(data);
+}
+
+static void cpld_write(u8 addr, u32 data)
+{
+	data = swab32(data);
+
+	spi_xfer(NULL, 32, &data, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+
+	spi_xfer(NULL, 8, NULL, &addr, SPI_XFER_BEGIN | SPI_XFER_END);
+
+	cpld_rw(1);
+}
+
+static void cpld_init(void)
+{
+	if (cpld_initialized)
+		return;
+
+	/* PULL-UP on MISO line */
+	setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4);
+
+	gpio_request(SCLK, NULL);
+	gpio_request(SSTBZ, NULL);
+	gpio_request(MOSI, NULL);
+	gpio_request(MISO, NULL);
+
+	gpio_direction_output(SCLK, 0);
+	gpio_direction_output(SSTBZ, 1);
+	gpio_direction_output(MOSI, 0);
+	gpio_direction_input(MISO);
+
+	/* Dummy read */
+	cpld_read(CPLD_ADDR_VERSION);
+
+	cpld_initialized = 1;
+}
+
+static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 addr, val;
+
+	cpld_init();
+
+	if (argc == 2 && strcmp(argv[1], "info") == 0) {
+		printf("CPLD version:\t\t\t0x%08x\n",
+		       cpld_read(CPLD_ADDR_VERSION));
+		printf("H3 Mode setting (MD0..28):\t0x%08x\n",
+		       cpld_read(CPLD_ADDR_MODE));
+		printf("Multiplexer settings:\t\t0x%08x\n",
+		       cpld_read(CPLD_ADDR_MUX));
+		printf("DIPSW (SW6):\t\t\t0x%08x\n",
+		       cpld_read(CPLD_ADDR_DIPSW6));
+		return 0;
+	}
+
+	if (argc < 3)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[2], NULL, 16);
+	if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE ||
+	      addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_DIPSW6 ||
+	      addr == CPLD_ADDR_RESET)) {
+		printf("Invalid CPLD register address\n");
+		return CMD_RET_USAGE;
+	}
+
+	if (argc == 3 && strcmp(argv[1], "read") == 0) {
+		printf("0x%x\n", cpld_read(addr));
+	} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
+		val = simple_strtoul(argv[3], NULL, 16);
+		cpld_write(addr, val);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	cpld, 4, 1, do_cpld,
+	"CPLD access",
+	"info\n"
+	"cpld read addr\n"
+	"cpld write addr val\n"
+);
+
+void reset_cpu(ulong addr)
+{
+	cpld_init();
+	cpld_write(CPLD_ADDR_RESET, 1);
+}
diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
new file mode 100644
index 0000000..4005ec8
--- /dev/null
+++ b/board/renesas/ulcb/ulcb.c
@@ -0,0 +1,257 @@
+/*
+ * board/renesas/ulcb/ulcb.c
+ *     This file is ULCB board support.
+ *
+ * Copyright (C) 2017 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CPGWPCR	0xE6150904
+#define CPGWPR  0xE615090C
+
+#define CLK2MHZ(clk)	(clk / 1000 / 1000)
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	writel(0xA5A50000, CPGWPCR);
+	writel(0xFFFFFFFF, CPGWPR);
+}
+
+#define GSX_MSTP112		BIT(12)	/* 3DG */
+#define TMU0_MSTP125		BIT(25)	/* secure */
+#define TMU1_MSTP124		BIT(24)	/* non-secure */
+#define SCIF2_MSTP310		BIT(10)	/* SCIF2 */
+#define ETHERAVB_MSTP812	BIT(12)
+#define DVFS_MSTP926		BIT(26)
+#define SD0_MSTP314		BIT(14)
+#define SD1_MSTP313		BIT(13)
+#define SD2_MSTP312		BIT(12)	/* either MMC0 */
+
+#define SD0CKCR			0xE6150074
+#define SD1CKCR			0xE6150078
+#define SD2CKCR			0xE6150268
+#define SD3CKCR			0xE615026C
+
+int board_early_init_f(void)
+{
+	/* TMU0,1 */		/* which use ? */
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
+	/* SCIF2 */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
+	/* EHTERAVB */
+	mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812);
+	/* eMMC */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
+	/* SDHI0 */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);
+
+	writel(0, SD0CKCR);
+	writel(0, SD1CKCR);
+	writel(0, SD2CKCR);
+	writel(0, SD3CKCR);
+
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+	/* DVFS for reset */
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+#endif
+	return 0;
+}
+
+/* SYSC */
+/* R/- 32 Power status register 2(3DG) */
+#define	SYSC_PWRSR2	0xE6180100
+/* -/W 32 Power resume control register 2 (3DG) */
+#define	SYSC_PWRONCR2	0xE618010C
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+	/* Init PFC controller */
+#if defined(CONFIG_R8A7795)
+	r8a7795_pinmux_init();
+#elif defined(CONFIG_R8A7796)
+	r8a7796_pinmux_init();
+#endif
+
+	/* USB1 pull-up */
+	setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
+
+#ifdef CONFIG_RAVB
+	/* EtherAVB Enable */
+	/* GPSR2 */
+	gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL);
+	gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL);
+	gpio_request(GPIO_GFN_AVB_LINK, NULL);
+	gpio_request(GPIO_GFN_AVB_PHY_INT, NULL);
+	gpio_request(GPIO_GFN_AVB_MAGIC, NULL);
+	gpio_request(GPIO_GFN_AVB_MDC, NULL);
+
+	/* IPSR0 */
+	gpio_request(GPIO_IFN_AVB_MDC, NULL);
+	gpio_request(GPIO_IFN_AVB_MAGIC, NULL);
+	gpio_request(GPIO_IFN_AVB_PHY_INT, NULL);
+	gpio_request(GPIO_IFN_AVB_LINK, NULL);
+	gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL);
+	gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL);
+	/* IPSR1 */
+	gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL);
+	/* IPSR2 */
+	gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL);
+	/* IPSR3 */
+	gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL);
+
+	/* AVB_PHY_RST */
+	gpio_request(GPIO_GP_2_10, NULL);
+	gpio_direction_output(GPIO_GP_2_10, 0);
+	mdelay(20);
+	gpio_set_value(GPIO_GP_2_10, 1);
+	udelay(1);
+#endif
+
+	return 0;
+}
+
+static struct eth_pdata salvator_x_ravb_platdata = {
+	.iobase		= 0xE6800000,
+	.phy_interface	= 0,
+	.max_speed	= 1000,
+};
+
+U_BOOT_DEVICE(salvator_x_ravb) = {
+	.name		= "ravb",
+	.platdata	= &salvator_x_ravb_platdata,
+};
+
+#ifdef CONFIG_SH_SDHI
+int board_mmc_init(bd_t *bis)
+{
+	int ret = -ENODEV;
+
+	/* SDHI0 */
+	gpio_request(GPIO_GFN_SD0_DAT0, NULL);
+	gpio_request(GPIO_GFN_SD0_DAT1, NULL);
+	gpio_request(GPIO_GFN_SD0_DAT2, NULL);
+	gpio_request(GPIO_GFN_SD0_DAT3, NULL);
+	gpio_request(GPIO_GFN_SD0_CLK, NULL);
+	gpio_request(GPIO_GFN_SD0_CMD, NULL);
+	gpio_request(GPIO_GFN_SD0_CD, NULL);
+	gpio_request(GPIO_GFN_SD0_WP, NULL);
+
+	gpio_request(GPIO_GP_5_2, NULL);
+	gpio_request(GPIO_GP_5_1, NULL);
+	gpio_direction_output(GPIO_GP_5_2, 1);	/* power on */
+	gpio_direction_output(GPIO_GP_5_1, 1);	/* 1: 3.3V, 0: 1.8V */
+
+	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
+			   SH_SDHI_QUIRK_64BIT_BUF);
+	if (ret)
+		return ret;
+
+	/* SDHI1/SDHI2 eMMC */
+	gpio_request(GPIO_GFN_SD1_DAT0, NULL);
+	gpio_request(GPIO_GFN_SD1_DAT1, NULL);
+	gpio_request(GPIO_GFN_SD1_DAT2, NULL);
+	gpio_request(GPIO_GFN_SD1_DAT3, NULL);
+	gpio_request(GPIO_GFN_SD2_DAT0, NULL);
+	gpio_request(GPIO_GFN_SD2_DAT1, NULL);
+	gpio_request(GPIO_GFN_SD2_DAT2, NULL);
+	gpio_request(GPIO_GFN_SD2_DAT3, NULL);
+	gpio_request(GPIO_GFN_SD2_CLK, NULL);
+#if defined(CONFIG_R8A7795)
+	gpio_request(GPIO_GFN_SD2_CMD, NULL);
+#elif defined(CONFIG_R8A7796)
+	gpio_request(GPIO_FN_SD2_CMD, NULL);
+#else
+#error Only R8A7795 and R87796 is supported
+#endif
+	gpio_request(GPIO_GP_5_3, NULL);
+	gpio_request(GPIO_GP_5_9, NULL);
+	gpio_direction_output(GPIO_GP_5_3, 0);	/* 1: 3.3V, 0: 1.8V */
+	gpio_direction_output(GPIO_GP_5_9, 0);	/* 1: 3.3V, 0: 1.8V */
+
+	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1,
+			   SH_SDHI_QUIRK_64BIT_BUF);
+
+	return ret;
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+	gd->ram_size += PHYS_SDRAM_2_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+	gd->ram_size += PHYS_SDRAM_3_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 4)
+	gd->ram_size += PHYS_SDRAM_4_SIZE;
+#endif
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 4)
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+#endif
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RCAR_BOARD_STRING
+};
+
+static const struct sh_serial_platdata serial_platdata = {
+	.base = SCIF2_BASE,
+	.type = PORT_SCIF,
+	.clk = CONFIG_SH_SCIF_CLK_FREQ,
+	.clk_mode = INT_CLK,
+};
+
+U_BOOT_DEVICE(salvator_x_scif2) = {
+	.name = "serial_sh",
+	.platdata = &serial_platdata,
+};
diff --git a/board/rockchip/evb_px5/Kconfig b/board/rockchip/evb_px5/Kconfig
new file mode 100644
index 0000000..9a04ee7
--- /dev/null
+++ b/board/rockchip/evb_px5/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_PX5
+
+config SYS_BOARD
+	default "evb_px5"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_px5"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/rockchip/evb_px5/MAINTAINERS b/board/rockchip/evb_px5/MAINTAINERS
new file mode 100644
index 0000000..5d09fbf
--- /dev/null
+++ b/board/rockchip/evb_px5/MAINTAINERS
@@ -0,0 +1,6 @@
+PX5 EVB
+M:	Andy Yan <andy.yan@rock-chips.com>
+S:	Maintained
+F:	board/rockchip/evb_px5
+F:	include/configs/evb_px5.h
+F:	configs/evb-px5_defconfig
diff --git a/board/rockchip/evb_px5/Makefile b/board/rockchip/evb_px5/Makefile
new file mode 100644
index 0000000..f5aa5a9
--- /dev/null
+++ b/board/rockchip/evb_px5/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2017 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= evb-px5.o
diff --git a/board/rockchip/evb_px5/README b/board/rockchip/evb_px5/README
new file mode 100644
index 0000000..de980f2
--- /dev/null
+++ b/board/rockchip/evb_px5/README
@@ -0,0 +1 @@
+see board/rockchip/sheep_rk3368/README
diff --git a/board/rockchip/evb_px5/evb-px5.c b/board/rockchip/evb_px5/evb-px5.c
new file mode 100644
index 0000000..6dca1fc
--- /dev/null
+++ b/board/rockchip/evb_px5/evb-px5.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2017 Andy Yan
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <fdtdec.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3368.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mach_cpu_init(void)
+{
+	struct rk3368_pmu_grf *pmugrf;
+	int node;
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rk3368-pmugrf");
+	pmugrf = (struct rk3368_pmu_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
+
+	rk_clrsetreg(&pmugrf->gpio0d_iomux,
+		     GPIO0D0_MASK | GPIO0D1_MASK |
+		     GPIO0D2_MASK | GPIO0D3_MASK,
+		     GPIO0D0_GPIO << GPIO0D0_SHIFT |
+		     GPIO0D1_GPIO << GPIO0D1_SHIFT |
+		     GPIO0D2_UART4_SOUT << GPIO0D2_SHIFT |
+		     GPIO0D3_UART4_SIN << GPIO0D3_SHIFT);
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
diff --git a/board/rockchip/evb_rk3036/evb_rk3036.c b/board/rockchip/evb_rk3036/evb_rk3036.c
index e5582b4..288370a 100644
--- a/board/rockchip/evb_rk3036/evb_rk3036.c
+++ b/board/rockchip/evb_rk3036/evb_rk3036.c
@@ -27,69 +27,3 @@ void get_ddr_config(struct rk3036_ddr_config *config)
 	/* 16bit bw */
 	config->bw = 1;
 }
-
-int board_init(void)
-{
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = sdram_size();
-
-	return 0;
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3036_otg_data = {
-	.rx_fifo_sz	= 512,
-	.np_tx_fifo_sz	= 16,
-	.tx_fifo_sz	= 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	int node;
-	const char *mode;
-	bool matched = false;
-	const void *blob = gd->fdt_blob;
-
-	/* find the usb_otg node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3288-usb");
-
-	while (node > 0) {
-		mode = fdt_getprop(blob, node, "dr_mode", NULL);
-		if (mode && strcmp(mode, "otg") == 0) {
-			matched = true;
-			break;
-		}
-
-		node = fdt_node_offset_by_compatible(blob, node,
-					"rockchip,rk3288-usb");
-	}
-	if (!matched) {
-		debug("Not found usb_otg device\n");
-		return -ENODEV;
-	}
-	rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-	return dwc2_udc_probe(&rk3036_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	return 0;
-}
-#endif
diff --git a/board/rockchip/evb_rk3229/Kconfig b/board/rockchip/evb_rk3229/Kconfig
new file mode 100644
index 0000000..361dcb1
--- /dev/null
+++ b/board/rockchip/evb_rk3229/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3229
+
+config SYS_BOARD
+	default "evb_rk3229"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_rk3229"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/rockchip/evb_rk3229/MAINTAINERS b/board/rockchip/evb_rk3229/MAINTAINERS
new file mode 100644
index 0000000..dfa1090
--- /dev/null
+++ b/board/rockchip/evb_rk3229/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3229
+M:      Kever Yang <kever.yang@rock-chips.com>
+S:      Maintained
+F:      board/rockchip/evb_rk3229
+F:      include/configs/evb_rk3229.h
+F:      configs/evb-rk3229_defconfig
diff --git a/board/rockchip/evb_rk3229/Makefile b/board/rockchip/evb_rk3229/Makefile
new file mode 100644
index 0000000..65dcd8b
--- /dev/null
+++ b/board/rockchip/evb_rk3229/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Google, Inc
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evb_rk3229.o
diff --git a/board/rockchip/evb_rk3229/evb_rk3229.c b/board/rockchip/evb_rk3229/evb_rk3229.c
new file mode 100644
index 0000000..a9a3a40
--- /dev/null
+++ b/board/rockchip/evb_rk3229/evb_rk3229.c
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/rockchip/evb_rk3328/Kconfig b/board/rockchip/evb_rk3328/Kconfig
new file mode 100644
index 0000000..ef446b4
--- /dev/null
+++ b/board/rockchip/evb_rk3328/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3328
+
+config SYS_BOARD
+	default "evb_rk3328"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_rk3328"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS
new file mode 100644
index 0000000..2ee6e46
--- /dev/null
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3328
+M:      Kever Yang <kever.yang@rock-chips.com>
+S:      Maintained
+F:      board/rockchip/evb_rk3328
+F:      include/configs/evb_rk3328.h
+F:      configs/evb-rk3328_defconfig
diff --git a/board/rockchip/evb_rk3328/Makefile b/board/rockchip/evb_rk3328/Makefile
new file mode 100644
index 0000000..81c5de8
--- /dev/null
+++ b/board/rockchip/evb_rk3328/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evb-rk3328.o
diff --git a/board/rockchip/evb_rk3328/README b/board/rockchip/evb_rk3328/README
new file mode 100644
index 0000000..6cbb66a
--- /dev/null
+++ b/board/rockchip/evb_rk3328/README
@@ -0,0 +1,70 @@
+Introduction
+============
+
+RK3328 key features we might use in U-Boot:
+* CPU: ARMv8 64bit quad-core Cortex-A53
+* IRAM: 36KB
+* DRAM: 4GB-16MB dual-channel
+* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50
+* SD/MMC: support SD 3.0, MMC 4.51
+* USB: USB2.0 EHCI host port *2
+* Display: RGB/HDMI/DP/MIPI/EDP
+
+evb key features:
+* regulator: pwm regulator for CPU B/L
+* PMIC: rk808
+* debug console: UART2
+
+In order to support Arm Trust Firmware(ATF), we need to use the
+miniloader from rockchip which:
+* do DRAM init
+* load and verify ATF image
+* load and verify U-Boot image
+
+Here is the step-by-step to boot to U-Boot on rk3328.
+
+Get the Source and prebuild binary
+==================================
+
+  > mkdir ~/evb_rk3328
+  > cd ~/evb_rk3328
+  > git clone https://github.com/ARM-software/arm-trusted-firmware.git
+  > git clone https://github.com/rockchip-linux/rkbin
+  > git clone https://github.com/rockchip-linux/rkflashtool
+
+Compile ATF
+===============
+
+  > cd arm-trusted-firmware
+  > make realclean
+  > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3328 bl31
+
+Compile U-Boot
+==================
+
+  > cd ../u-boot
+  > make CROSS_COMPILE=aarch64-linux-gnu- evb-rk3328_defconfig all
+
+Compile rkflashtool
+=======================
+
+  > cd ../rkflashtool
+  > make
+
+Package image for miniloader
+================================
+  > cd ..
+  > cp arm-trusted-firmware/build/rk3328/release/bl31.bin rkbin/rk33
+  > ./rkbin/tools/trust_merger rkbin/tools/RK3328TRUST.ini
+  > ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img
+  > mkdir image
+  > mv trust.img ./image/
+  > mv uboot.img ./image/rk3328evb-uboot.bin
+
+Flash image
+===============
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+
+  > ./rkflashtool/rkflashloader rk3328evb
+
+You should be able to get U-Boot log message in console/UART2 now.
diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c
new file mode 100644
index 0000000..99a73da
--- /dev/null
+++ b/board/rockchip/evb_rk3328/evb-rk3328.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <dwc3-uboot.h>
+#include <power/regulator.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	int ret;
+
+	ret = regulators_enable_boot_on(false);
+	if (ret)
+		debug("%s: Cannot enable boot on regulator\n", __func__);
+
+	return ret;
+}
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data rk3328_otg_data = {
+	.rx_fifo_sz	= 512,
+	.np_tx_fifo_sz	= 16,
+	.tx_fifo_sz	= 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int node;
+	const char *mode;
+	bool matched = false;
+	const void *blob = gd->fdt_blob;
+
+	/* find the usb_otg node */
+	node = fdt_node_offset_by_compatible(blob, -1,
+					"rockchip,rk3328-usb");
+
+	while (node > 0) {
+		mode = fdt_getprop(blob, node, "dr_mode", NULL);
+		if (mode && strcmp(mode, "otg") == 0) {
+			matched = true;
+			break;
+		}
+
+		node = fdt_node_offset_by_compatible(blob, node,
+					"rockchip,rk3328-usb");
+	}
+	if (!matched) {
+		debug("Not found usb_otg device\n");
+		return -ENODEV;
+	}
+
+	rk3328_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+	return dwc2_udc_probe(&rk3328_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	return 0;
+}
+#endif
diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c
index cb2d97d..d50c59d 100644
--- a/board/rockchip/evb_rk3399/evb-rk3399.c
+++ b/board/rockchip/evb_rk3399/evb-rk3399.c
@@ -4,24 +4,66 @@
  * SPDX-License-Identifier:     GPL-2.0+
  */
 #include <common.h>
-#include <asm/armv8/mmu.h>
+#include <dm.h>
+#include <ram.h>
+#include <dm/pinctrl.h>
+#include <dm/uclass-internal.h>
+#include <asm/arch/periph.h>
+#include <power/regulator.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
-	return 0;
-}
+	struct udevice *pinctrl, *regulator;
+	int ret;
 
-int dram_init(void)
-{
-	gd->ram_size = 0x80000000;
-	return 0;
-}
+	/*
+	 * The PWM do not have decicated interrupt number in dts and can
+	 * not get periph_id by pinctrl framework, so let's init them here.
+	 * The PWM2 and PWM3 are for pwm regulater.
+	 */
+	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+	if (ret) {
+		debug("%s: Cannot find pinctrl device\n", __func__);
+		goto out;
+	}
 
-void dram_init_banksize(void)
-{
-	/* Reserve 0x200000 for ATF bl31 */
-	gd->bd->bi_dram[0].start = 0x200000;
-	gd->bd->bi_dram[0].size = 0x80000000;
+	/* Enable pwm0 for panel backlight */
+	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM0);
+	if (ret) {
+		debug("%s PWM0 pinctrl init fail! (ret=%d)\n", __func__, ret);
+		goto out;
+	}
+
+	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2);
+	if (ret) {
+		debug("%s PWM2 pinctrl init fail!\n", __func__);
+		goto out;
+	}
+
+	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM3);
+	if (ret) {
+		debug("%s PWM3 pinctrl init fail!\n", __func__);
+		goto out;
+	}
+
+	ret = regulators_enable_boot_on(false);
+	if (ret)
+		debug("%s: Cannot enable boot on regulator\n", __func__);
+
+	ret = regulator_get_by_platname("vcc5v0_host", &regulator);
+	if (ret) {
+		debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
+		goto out;
+	}
+
+	ret = regulator_set_enable(regulator, true);
+	if (ret) {
+		debug("%s vcc5v0-host-en set fail!\n", __func__);
+		goto out;
+	}
+
+out:
+	return 0;
 }
diff --git a/board/rockchip/evb_rv1108/Kconfig b/board/rockchip/evb_rv1108/Kconfig
new file mode 100644
index 0000000..4a76e0b
--- /dev/null
+++ b/board/rockchip/evb_rv1108/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RV1108
+
+config SYS_BOARD
+	default "evb_rv1108"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "evb_rv1108"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/rockchip/evb_rv1108/MAINTAINERS b/board/rockchip/evb_rv1108/MAINTAINERS
new file mode 100644
index 0000000..94def32
--- /dev/null
+++ b/board/rockchip/evb_rv1108/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RV1108
+M:      Andy Yan <andy.yan@rock-chips.com>
+S:      Maintained
+F:      board/rockchip/evb_rv1108
+F:      include/configs/evb_rv1108.h
+F:      configs/evb-rv1108_defconfig
diff --git a/board/rockchip/evb_rv1108/Makefile b/board/rockchip/evb_rv1108/Makefile
new file mode 100644
index 0000000..dd99054
--- /dev/null
+++ b/board/rockchip/evb_rv1108/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evb_rv1108.o
diff --git a/board/rockchip/evb_rv1108/README b/board/rockchip/evb_rv1108/README
new file mode 100644
index 0000000..5889596
--- /dev/null
+++ b/board/rockchip/evb_rv1108/README
@@ -0,0 +1,47 @@
+Here is the step-by-step to boot U-Boot on rv1108 evb.
+
+Get ddr init binary
+==============================================================================
+  > git clone  https://github.com/rockchip-linux/rkbin.git
+  > dd if=./rkbin/rv1x/rv1108ddr.bin of=ddr.bin bs=4 skip=1
+
+Compile  U-Boot
+===========================
+  > make CROSS_COMPILE=arm-linux-gnueabi- evb-rv1108_defconfig  all
+  > ./tools/mkimage  -n rv1108 -T rksd -d ddr.bin spl.bin
+  > cat spl.bin u-boot.bin > u-boot.img
+
+Flash the image by rkdeveloptool
+================================
+rkdeveloptool can get from https://github.com/rockchip-linux/rkdeveloptool.git
+
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+  > rkdeveloptool db ./rkbin/rv1x/RV1108_usb_boot.bin
+  > rkdeveloptool wl 0x40 u-boot.img
+  > rkdeveloptool RD
+
+You should be able to get U-Boot log message from boot console:
+
+DDR Version V1.02 20170220
+In
+400MHz
+DDR3
+Bus Width=16 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=512MB
+mach:2
+OUT
+
+
+U-Boot 2017.05-00693-g3a5b171 (Jun 01 2017 - 17:37:53 +0800)
+
+Model: Rockchip RV1108 Evaluation board
+DRAM:  128 MiB
+APLL: 600000000 DPLL:792000000 GPLL:384000000
+MMC:
+Using default environment
+
+In:    serial@10210000
+Out:   serial@10210000
+Err:   serial@10210000
+Net:   No ethernet found.
+Hit any key to stop autoboot:  0
+=>
diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c
new file mode 100644
index 0000000..fe37eac
--- /dev/null
+++ b/board/rockchip/evb_rv1108/evb_rv1108.c
@@ -0,0 +1,52 @@
+/*
+ * (C)Copyright 2016 Rockchip Electronics Co., Ltd
+ * Authors: Andy Yan <andy.yan@rock-chips.com>
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <fdtdec.h>
+#include <asm/arch/grf_rv1108.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mach_cpu_init(void)
+{
+	int node;
+	struct rv1108_grf *grf;
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rv1108-grf");
+	grf = (struct rv1108_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
+
+	/*evb board use UART2 m0 for debug*/
+	rk_clrsetreg(&grf->gpio2d_iomux,
+		     GPIO2D2_MASK | GPIO2D1_MASK,
+		     GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
+		     GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
+	rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK);
+
+	return 0;
+}
+
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = 0x8000000;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = 0x60000000;
+	gd->bd->bi_dram[0].size = 0x8000000;
+
+	return 0;
+}
diff --git a/board/rockchip/kylin_rk3036/kylin_rk3036.c b/board/rockchip/kylin_rk3036/kylin_rk3036.c
index 5ade695..7e2edf4 100644
--- a/board/rockchip/kylin_rk3036/kylin_rk3036.c
+++ b/board/rockchip/kylin_rk3036/kylin_rk3036.c
@@ -8,14 +8,11 @@
 #include <dm.h>
 #include <asm/io.h>
 #include <asm/arch/uart.h>
-#include <asm/arch-rockchip/grf_rk3036.h>
 #include <asm/arch/sdram_rk3036.h>
 #include <asm/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define GRF_BASE	0x20008000
-
 void get_ddr_config(struct rk3036_ddr_config *config)
 {
 	/* K4B4G1646Q config */
@@ -43,85 +40,12 @@ int fastboot_key_pressed(void)
 
 #define ROCKCHIP_BOOT_MODE_FASTBOOT	0x5242C309
 
-int board_late_init(void)
+int rk_board_late_init(void)
 {
-	struct rk3036_grf * const grf = (void *)GRF_BASE;
-	int boot_mode = readl(&grf->os_reg[4]);
-
-	/* Clear boot mode */
-	writel(0, &grf->os_reg[4]);
-
-	if (boot_mode == ROCKCHIP_BOOT_MODE_FASTBOOT ||
-	    fastboot_key_pressed()) {
+	if (fastboot_key_pressed()) {
 		printf("enter fastboot!\n");
 		setenv("preboot", "setenv preboot; fastboot usb0");
 	}
 
 	return 0;
 }
-
-int board_init(void)
-{
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = sdram_size();
-
-	return 0;
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3036_otg_data = {
-	.rx_fifo_sz	= 512,
-	.np_tx_fifo_sz	= 16,
-	.tx_fifo_sz	= 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	int node;
-	const char *mode;
-	bool matched = false;
-	const void *blob = gd->fdt_blob;
-
-	/* find the usb_otg node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3288-usb");
-
-	while (node > 0) {
-		mode = fdt_getprop(blob, node, "dr_mode", NULL);
-		if (mode && strcmp(mode, "otg") == 0) {
-			matched = true;
-			break;
-		}
-
-		node = fdt_node_offset_by_compatible(blob, node,
-					"rockchip,rk3288-usb");
-	}
-	if (!matched) {
-		debug("Not found usb_otg device\n");
-		return -ENODEV;
-	}
-	rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-	return dwc2_udc_probe(&rk3036_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	return 0;
-}
-#endif
diff --git a/board/rockchip/miniarm_rk3288/Kconfig b/board/rockchip/miniarm_rk3288/Kconfig
deleted file mode 100644
index 529c09f..0000000
--- a/board/rockchip/miniarm_rk3288/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_MINIARM_RK3288
-
-config SYS_BOARD
-	default "miniarm_rk3288"
-
-config SYS_VENDOR
-	default "rockchip"
-
-config SYS_CONFIG_NAME
-	default "miniarm_rk3288"
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-
-endif
diff --git a/board/rockchip/miniarm_rk3288/MAINTAINERS b/board/rockchip/miniarm_rk3288/MAINTAINERS
deleted file mode 100644
index 7537b8f..0000000
--- a/board/rockchip/miniarm_rk3288/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MINIARM-RK3288
-M:	Lin Huang <hl@rock-chips.com>
-S:	Maintained
-F:	board/rockchip/miniarm_rk3288
-F:	include/configs/miniarm_rk3288.h
-F:	configs/miniarm-rk3288_defconfig
diff --git a/board/rockchip/miniarm_rk3288/Makefile b/board/rockchip/miniarm_rk3288/Makefile
deleted file mode 100644
index 9419b91..0000000
--- a/board/rockchip/miniarm_rk3288/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2016 Rockchip Electronics Co., Ltd
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y	+= miniarm-rk3288.o
diff --git a/board/rockchip/miniarm_rk3288/miniarm-rk3288.c b/board/rockchip/miniarm_rk3288/miniarm-rk3288.c
deleted file mode 100644
index aad74ef..0000000
--- a/board/rockchip/miniarm_rk3288/miniarm-rk3288.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-
-void board_boot_order(u32 *spl_boot_list)
-{
-	/* eMMC prior to sdcard */
-	spl_boot_list[0] = BOOT_DEVICE_MMC2;
-	spl_boot_list[1] = BOOT_DEVICE_MMC1;
-}
diff --git a/board/rockchip/sheep_rk3368/Kconfig b/board/rockchip/sheep_rk3368/Kconfig
new file mode 100644
index 0000000..d39b5e8
--- /dev/null
+++ b/board/rockchip/sheep_rk3368/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SHEEP
+
+config SYS_BOARD
+	default "sheep_rk3368"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "sheep_rk3368"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/rockchip/sheep_rk3368/MAINTAINERS b/board/rockchip/sheep_rk3368/MAINTAINERS
new file mode 100644
index 0000000..cd5de99
--- /dev/null
+++ b/board/rockchip/sheep_rk3368/MAINTAINERS
@@ -0,0 +1,6 @@
+RK3368 Sheep Board
+M:	Andy Yan <andy.yan@rock-chips.com>
+S:	Maintained
+F:	board/rockchip/sheep_rk3368
+F:	include/configs/sheep_rk3368.h
+F:	configs/sheep-rk3368_defconfig
diff --git a/board/rockchip/sheep_rk3368/Makefile b/board/rockchip/sheep_rk3368/Makefile
new file mode 100644
index 0000000..a38b9ce
--- /dev/null
+++ b/board/rockchip/sheep_rk3368/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2017 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= sheep_rk3368.o
diff --git a/board/rockchip/sheep_rk3368/README b/board/rockchip/sheep_rk3368/README
new file mode 100644
index 0000000..2d078cb
--- /dev/null
+++ b/board/rockchip/sheep_rk3368/README
@@ -0,0 +1,44 @@
+Here is the step-by-step to boot to U-Boot on rk3368.
+
+Get miniloader and trust.img form rockchip vendor u-boot source code
+==============================================================================
+  > git clone  https://github.com/rockchip-linux/u-boot.git rockchip-uboot
+  > cd rockchip-uboot
+  > make rk3368_defconfig /*chose px5_defconfig if you run a px5 platform here*/
+  > ./mkv8.sh
+
+Compile the upstream U-Boot
+===========================
+  > cd u-boot
+  > make CROSS_COMPILE=aarch64-linux-gnu- sheep-rk3368_defconfig  all
+
+Package u-boot for miniloader
+================================
+  > ../rockchip-uboot/tools/loaderimage --pack --uboot u-boot.bin u-boot.img
+
+Flash the image by rkdeveloptool
+================================
+rkdeveloptool can get from https://github.com/rockchip-linux/rkdeveloptool.git
+
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+  > rkdeveloptool db ./rockchip-uboot/rk3368_loader_v2.00.256.bin
+  > rkdeveloptool wl 0x6000 ./rockchip-uboot/trust.img
+  > rkdeveloptool wl 0x4000 ./u-boot/u-boot.img
+  > rkdeveloptool RD
+
+You should be able to get U-Boot log message from boot console:
+
+U-Boot 2017.05-rc3-01094-g9ddd1e8-dirty (May 15 2017 - 15:57:23 +0800)
+
+Model: Rockchip sheep board
+DRAM:  2 GiB
+MMC:   dwmmc@ff0f0000: 0
+Using default environment
+
+In:    serial@ff690000
+Out:   serial@ff690000
+Err:   serial@ff690000
+Net:   Net Initialization Skipped
+No ethernet found.
+Hit any key to stop autoboot:  0
+=>
diff --git a/board/rockchip/sheep_rk3368/sheep_rk3368.c b/board/rockchip/sheep_rk3368/sheep_rk3368.c
new file mode 100644
index 0000000..17adb02
--- /dev/null
+++ b/board/rockchip/sheep_rk3368/sheep_rk3368.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2017 Andy Yan
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3368.h>
+#include <syscon.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mach_cpu_init(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
diff --git a/board/rockchip/tinker_rk3288/Kconfig b/board/rockchip/tinker_rk3288/Kconfig
new file mode 100644
index 0000000..bca6c37
--- /dev/null
+++ b/board/rockchip/tinker_rk3288/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TINKER_RK3288
+
+config SYS_BOARD
+	default "tinker_rk3288"
+
+config SYS_VENDOR
+	default "rockchip"
+
+config SYS_CONFIG_NAME
+	default "tinker_rk3288"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/rockchip/tinker_rk3288/MAINTAINERS b/board/rockchip/tinker_rk3288/MAINTAINERS
new file mode 100644
index 0000000..cddceaf
--- /dev/null
+++ b/board/rockchip/tinker_rk3288/MAINTAINERS
@@ -0,0 +1,6 @@
+TINKER-RK3288
+M:	Lin Huang <hl@rock-chips.com>
+S:	Maintained
+F:	board/rockchip/tinker_rk3288
+F:	include/configs/tinker_rk3288.h
+F:	configs/tinker-rk3288_defconfig
diff --git a/board/rockchip/tinker_rk3288/Makefile b/board/rockchip/tinker_rk3288/Makefile
new file mode 100644
index 0000000..432367f
--- /dev/null
+++ b/board/rockchip/tinker_rk3288/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= tinker-rk3288.o
diff --git a/board/rockchip/tinker_rk3288/tinker-rk3288.c b/board/rockchip/tinker_rk3288/tinker-rk3288.c
new file mode 100644
index 0000000..c2872e7
--- /dev/null
+++ b/board/rockchip/tinker_rk3288/tinker-rk3288.c
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c_eeprom.h>
+#include <netdev.h>
+
+static int get_ethaddr_from_eeprom(u8 *addr)
+{
+	int ret;
+	struct udevice *dev;
+
+	ret = uclass_first_device_err(UCLASS_I2C_EEPROM, &dev);
+	if (ret)
+		return ret;
+
+	return i2c_eeprom_read(dev, 0, addr, 6);
+}
+
+int rk_board_late_init(void)
+{
+	u8 ethaddr[6];
+
+	if (get_ethaddr_from_eeprom(ethaddr))
+		return 0;
+
+	if (is_valid_ethaddr(ethaddr))
+		eth_setenv_enetaddr("ethaddr", ethaddr);
+
+	return 0;
+}
diff --git a/board/ronetix/pm9261/Makefile b/board/ronetix/pm9261/Makefile
index 3860283..90835d3 100644
--- a/board/ronetix/pm9261/Makefile
+++ b/board/ronetix/pm9261/Makefile
@@ -11,5 +11,5 @@
 #
 
 obj-y += pm9261.o
-obj-y += led.o
+obj-$(CONFIG_RED_LED) += led.o
 obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index e2cb94e..f338ff8 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -21,11 +21,11 @@
 
 #include <lcd.h>
 #include <atmel_lcdc.h>
-#include <dataflash.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
 #include <net.h>
 #endif
 #include <netdev.h>
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -177,7 +177,7 @@ extern flash_info_t flash_info[];
 
 void lcd_show_board_info(void)
 {
-	ulong dram_size, nand_size, flash_size, dataflash_size;
+	ulong dram_size, nand_size, flash_size;
 	int i;
 	char temp[32];
 
@@ -194,23 +194,17 @@ void lcd_show_board_info(void)
 
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i]->size;
+		nand_size += get_nand_dev_by_index(i)->size;
 
 	flash_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
 		flash_size += flash_info[i].size;
 
-	dataflash_size = 0;
-	for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
-		dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
-				dataflash_info[i].Device.pages_size;
-
 	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
 			"%ld MB DataFlash\n",
 		dram_size >> 20,
 		nand_size >> 20,
-		flash_size >> 20,
-		dataflash_size >> 20);
+		flash_size >> 20);
 }
 #endif /* CONFIG_LCD_INFO */
 
@@ -218,11 +212,6 @@ void lcd_show_board_info(void)
 
 int board_early_init_f(void)
 {
-	at91_periph_clk_enable(ATMEL_ID_PIOA);
-	at91_periph_clk_enable(ATMEL_ID_PIOC);
-
-	at91_seriald_hw_init();
-
 	return 0;
 }
 
@@ -237,9 +226,6 @@ int board_init(void)
 #ifdef CONFIG_CMD_NAND
 	pm9261_nand_hw_init();
 #endif
-#ifdef CONFIG_HAS_DATAFLASH
-	at91_spi0_hw_init(1 << 0);
-#endif
 #ifdef CONFIG_DRIVER_DM9000
 	pm9261_dm9000_hw_init();
 #endif
@@ -264,10 +250,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_RESET_PHY_R
diff --git a/board/ronetix/pm9263/Makefile b/board/ronetix/pm9263/Makefile
index 43ea599..53e621d 100644
--- a/board/ronetix/pm9263/Makefile
+++ b/board/ronetix/pm9263/Makefile
@@ -11,5 +11,5 @@
 #
 
 obj-y += pm9263.o
-obj-y += led.o
+obj-$(CONFIG_AT91_LED) += led.o
 obj-$(CONFIG_HAS_DATAFLASH) += partition.o
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index e9f9b67..8d20084 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -20,11 +20,11 @@
 #include <asm/arch/gpio.h>
 #include <lcd.h>
 #include <atmel_lcdc.h>
-#include <dataflash.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
 #include <net.h>
 #endif
 #include <netdev.h>
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -276,7 +276,7 @@ extern flash_info_t flash_info[];
 
 void lcd_show_board_info(void)
 {
-	ulong dram_size, nand_size, flash_size, dataflash_size;
+	ulong dram_size, nand_size, flash_size;
 	int i;
 	char temp[32];
 
@@ -293,23 +293,17 @@ void lcd_show_board_info(void)
 
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i]->size;
+		nand_size += get_nand_dev_by_index(i)->size;
 
 	flash_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
 		flash_size += flash_info[i].size;
 
-	dataflash_size = 0;
-	for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
-		dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
-				dataflash_info[i].Device.pages_size;
-
 	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
-			"4 MB PSRAM, %ld MB DataFlash\n",
+			"4 MB PSRAM\n",
 		dram_size >> 20,
 		nand_size >> 20,
-		flash_size >> 20,
-		dataflash_size >> 20);
+		flash_size >> 20);
 }
 #endif /* CONFIG_LCD_INFO */
 
@@ -317,12 +311,6 @@ void lcd_show_board_info(void)
 
 int board_early_init_f(void)
 {
-	at91_periph_clk_enable(ATMEL_ID_PIOA);
-	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
-
-	at91_seriald_hw_init();
-
 	return 0;
 }
 
@@ -337,9 +325,6 @@ int board_init(void)
 #ifdef CONFIG_CMD_NAND
 	pm9263_nand_hw_init();
 #endif
-#ifdef CONFIG_HAS_DATAFLASH
-	at91_spi0_hw_init(1 << 0);
-#endif
 #ifdef CONFIG_MACB
 	pm9263_macb_hw_init();
 #endif
@@ -360,10 +345,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_RESET_PHY_R
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
index c2707e0..e2620e3 100644
--- a/board/ronetix/pm9g45/pm9g45.c
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -25,6 +25,7 @@
 #include <net.h>
 #endif
 #include <netdev.h>
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -144,10 +145,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_RESET_PHY_R
diff --git a/board/sagem/f@st1704/Kconfig b/board/sagem/f@st1704/Kconfig
new file mode 100644
index 0000000..4566fcc
--- /dev/null
+++ b/board/sagem/f@st1704/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_SAGEM_FAST1704
+
+config SYS_BOARD
+	default "f@st1704"
+
+config SYS_VENDOR
+	default "sagem"
+
+config SYS_CONFIG_NAME
+	default "sagem_f@st1704"
+
+endif
diff --git a/board/sagem/f@st1704/MAINTAINERS b/board/sagem/f@st1704/MAINTAINERS
new file mode 100644
index 0000000..72e1c5c
--- /dev/null
+++ b/board/sagem/f@st1704/MAINTAINERS
@@ -0,0 +1,6 @@
+SAGEM F@ST1704 BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/sagem/f@st1704/
+F:	include/configs/sagem_f@st1704.h
+F:	configs/sagem_f@st1704_ram_defconfig
diff --git a/board/sagem/f@st1704/Makefile b/board/sagem/f@st1704/Makefile
new file mode 100644
index 0000000..a5f97f8
--- /dev/null
+++ b/board/sagem/f@st1704/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += f@st1704.o
diff --git a/board/sagem/f@st1704/f@st1704.c b/board/sagem/f@st1704/f@st1704.c
new file mode 100644
index 0000000..d181ca6
--- /dev/null
+++ b/board/sagem/f@st1704/f@st1704.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c
index 881d080..49ed324 100644
--- a/board/samsung/arndale/arndale.c
+++ b/board/samsung/arndale/arndale.c
@@ -55,7 +55,7 @@ int power_init_board(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	int i;
 	u32 addr, size;
@@ -67,9 +67,11 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[i].start = addr;
 		gd->bd->bi_dram[i].size = size;
 	}
+
+	return 0;
 }
 
-#ifdef CONFIG_GENERIC_MMC
+#ifdef CONFIG_MMC
 int board_mmc_init(bd_t *bis)
 {
 	int ret;
diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile
index ef1a8f3..fa85f7d 100644
--- a/board/samsung/common/Makefile
+++ b/board/samsung/common/Makefile
@@ -5,7 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
 obj-$(CONFIG_USB_GADGET_DOWNLOAD) += gadget.o
 obj-$(CONFIG_MISC_COMMON) += misc.o
 
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 0eb066c..88299f1 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -108,7 +108,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	unsigned int i;
 	unsigned long addr, size;
@@ -120,6 +120,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[i].start = addr;
 		gd->bd->bi_dram[i].size = size;
 	}
+
+	return 0;
 }
 
 static int board_uart_init(void)
@@ -248,10 +250,10 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
-#ifdef CONFIG_GENERIC_MMC
+#ifdef CONFIG_MMC
 static int init_mmc(void)
 {
-#ifdef CONFIG_SDHCI
+#ifdef CONFIG_MMC_SDHCI
 	return exynos_mmc_init(gd->fdt_blob);
 #else
 	return 0;
@@ -260,7 +262,7 @@ static int init_mmc(void)
 
 static int init_dwmmc(void)
 {
-#ifdef CONFIG_DWMMC
+#ifdef CONFIG_MMC_DW
 	return exynos_dwmmc_init(gd->fdt_blob);
 #else
 	return 0;
@@ -349,8 +351,8 @@ void reset_misc(void)
 	if (node < 0)
 		return;
 
-	gpio_request_by_name_nodev(gd->fdt_blob, node, "reset-gpio", 0, &gpio,
-				   GPIOD_IS_OUT);
+	gpio_request_by_name_nodev(offset_to_ofnode(node), "reset-gpio", 0,
+				   &gpio, GPIOD_IS_OUT);
 
 	if (dm_gpio_is_valid(&gpio)) {
 		/*
diff --git a/board/samsung/common/exynos-uboot-spl.lds b/board/samsung/common/exynos-uboot-spl.lds
index 4a933c8..8c49779 100644
--- a/board/samsung/common/exynos-uboot-spl.lds
+++ b/board/samsung/common/exynos-uboot-spl.lds
@@ -38,8 +38,7 @@ SECTIONS
 	} >.sram
 	. = ALIGN(4);
 
-	/* Align .machine_param on 256 byte boundary for easier searching */
-	.machine_param ALIGN(0x100) : { *(.machine_param) } >.sram
+	.machine_param : { *(.machine_param) } >.sram
 	. = ALIGN(4);
 
 	__image_copy_end = .;
diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c
index 2e3b16d..44f412d 100644
--- a/board/samsung/common/exynos5-dt.c
+++ b/board/samsung/common/exynos5-dt.c
@@ -45,7 +45,7 @@ static void board_enable_audio_codec(void)
 	if (node <= 0)
 		return;
 
-	ret = gpio_request_by_name_nodev(gd->fdt_blob, node,
+	ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
 					 "codec-enable-gpio", 0, &en_gpio,
 					 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 	if (ret == -FDT_ERR_NOTFOUND)
@@ -123,13 +123,7 @@ int exynos_power_init(void)
 	if (ret)
 		return ret;
 
-	/*
-	 * This would normally be 1.3V, but since we are running slowly 1.1V
-	 * is enough. For spring it helps reduce CPU temperature and avoid
-	 * hangs with the case open. 1.1V is minimum voltage borderline for
-	 * chained bootloaders.
-	 */
-	ret = exynos_set_regulator("vdd_arm", 1100000);
+	ret = exynos_set_regulator("vdd_arm", 1300000);
 	if (ret)
 		return ret;
 	ret = exynos_set_regulator("vdd_int", 1012500);
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index 77d0a4e..b18eed2 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -18,6 +18,19 @@
 #include <asm/gpio.h>
 #include <linux/input.h>
 #include <dm.h>
+/*
+ * Use #ifdef to work around conflicting headers while we wait for this to be
+ * converted to driver model.
+ */
+#ifdef CONFIG_DM_PMIC_MAX77686
+#include <power/max77686_pmic.h>
+#endif
+#ifdef CONFIG_DM_PMIC_MAX8998
+#include <power/max8998_pmic.h>
+#endif
+#ifdef CONFIG_PMIC_MAX8997
+#include <power/max8997_pmic.h>
+#endif
 #include <power/pmic.h>
 #include <mmc.h>
 
@@ -101,6 +114,7 @@ void set_board_info(void)
 #ifdef CONFIG_LCD_MENU
 static int power_key_pressed(u32 reg)
 {
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
 	struct pmic *pmic;
 	u32 status;
 	u32 mask;
@@ -123,6 +137,9 @@ static int power_key_pressed(u32 reg)
 		return 0;
 
 	return !!(status & mask);
+#else
+	return 0;
+#endif
 }
 
 static int key_pressed(int key)
@@ -204,7 +221,7 @@ mode_cmd[BOOT_MODE_EXIT + 1] = {
 
 static void display_board_info(void)
 {
-#ifdef CONFIG_GENERIC_MMC
+#ifdef CONFIG_MMC
 	struct mmc *mmc = find_mmc_device(0);
 #endif
 	vidinfo_t *vid = &panel_info;
@@ -222,7 +239,7 @@ static void display_board_info(void)
 	lcd_printf("\tDRAM banks: %u\n", CONFIG_NR_DRAM_BANKS);
 	lcd_printf("\tDRAM size: %u MB\n", gd->ram_size / SZ_1M);
 
-#ifdef CONFIG_GENERIC_MMC
+#ifdef CONFIG_MMC
 	if (mmc) {
 		if (!mmc->capacity)
 			mmc_init(mmc);
diff --git a/board/samsung/common/multi_i2c.c b/board/samsung/common/multi_i2c.c
deleted file mode 100644
index 71c32c0..0000000
--- a/board/samsung/common/multi_i2c.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- *  Copyright (C) 2012 Samsung Electronics
- *  Lukasz Majewski <l.majewski@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-
-#ifndef CONFIG_SOFT_I2C_I2C10_SCL
-#define CONFIG_SOFT_I2C_I2C10_SCL 0
-#endif
-
-#ifndef CONFIG_SOFT_I2C_I2C10_SDA
-#define CONFIG_SOFT_I2C_I2C10_SDA 0
-#endif
-
-/* Handle multiple I2C buses instances */
-int get_multi_scl_pin(void)
-{
-	unsigned int bus = i2c_get_bus_num();
-
-	switch (bus) {
-	case I2C_0:
-		return CONFIG_SOFT_I2C_I2C5_SCL;
-	case I2C_1:
-		return CONFIG_SOFT_I2C_I2C9_SCL;
-	case I2C_2:
-		return CONFIG_SOFT_I2C_I2C10_SCL;
-	default:
-		printf("I2C_%d not supported!\n", bus);
-	};
-
-	return 0;
-}
-
-int get_multi_sda_pin(void)
-{
-	unsigned int bus = i2c_get_bus_num();
-
-	switch (bus) {
-	case I2C_0:
-		return CONFIG_SOFT_I2C_I2C5_SDA;
-	case I2C_1:
-		return CONFIG_SOFT_I2C_I2C9_SDA;
-	case I2C_2:
-		return CONFIG_SOFT_I2C_I2C10_SDA;
-	default:
-		printf("I2C_%d not supported!\n", bus);
-	};
-
-	return 0;
-}
-
-int multi_i2c_init(void)
-{
-	return 0;
-}
diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c
index 1600568..d0247ac 100644
--- a/board/samsung/goni/goni.c
+++ b/board/samsung/goni/goni.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <asm/gpio.h>
 #include <asm/arch/mmc.h>
+#include <dm.h>
 #include <power/pmic.h>
 #include <usb/dwc2_udc.h>
 #include <asm/arch/cpu.h>
@@ -16,6 +17,7 @@
 #include <samsung/misc.h>
 #include <usb.h>
 #include <usb_mass_storage.h>
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -43,21 +45,6 @@ void i2c_init_board(void)
 }
 #endif
 
-int power_init_board(void)
-{
-	int ret;
-
-	/*
-	 * For PMIC the I2C bus is named as I2C5, but it is connected
-	 * to logical I2C adapter 0
-	 */
-	ret = pmic_init(I2C_0);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
 int dram_init(void)
 {
 	gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE +
@@ -66,7 +53,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
@@ -74,6 +61,8 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
 	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_DISPLAY_BOARDINFO
@@ -84,7 +73,7 @@ int checkboard(void)
 }
 #endif
 
-#ifdef CONFIG_GENERIC_MMC
+#ifdef CONFIG_MMC
 int board_mmc_init(bd_t *bis)
 {
 	int i, ret, ret_sd = 0;
@@ -148,38 +137,50 @@ int board_mmc_init(bd_t *bis)
 #ifdef CONFIG_USB_GADGET
 static int s5pc1xx_phy_control(int on)
 {
-	int ret;
+	struct udevice *dev;
 	static int status;
-	struct pmic *p = pmic_get("MAX8998_PMIC");
-	if (!p)
-		return -ENODEV;
+	int reg, ret;
 
-	if (pmic_probe(p))
-		return -1;
+	ret = pmic_get("max8998-pmic", &dev);
+	if (ret)
+		return ret;
 
 	if (on && !status) {
-		ret = pmic_set_output(p, MAX8998_REG_ONOFF1,
-				      MAX8998_LDO3, LDO_ON);
-		ret = pmic_set_output(p, MAX8998_REG_ONOFF2,
-				      MAX8998_LDO8, LDO_ON);
+		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
+		reg |= MAX8998_LDO3;
+		ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
+		if (ret) {
+			puts("MAX8998 LDO setting error!\n");
+			return -EINVAL;
+		}
+
+		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
+		reg |= MAX8998_LDO8;
+		ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
 		if (ret) {
 			puts("MAX8998 LDO setting error!\n");
-			return -1;
+			return -EINVAL;
 		}
 		status = 1;
 	} else if (!on && status) {
-		ret = pmic_set_output(p, MAX8998_REG_ONOFF1,
-				      MAX8998_LDO3, LDO_OFF);
-		ret = pmic_set_output(p, MAX8998_REG_ONOFF2,
-				      MAX8998_LDO8, LDO_OFF);
+		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
+		reg &= ~MAX8998_LDO3;
+		ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
 		if (ret) {
 			puts("MAX8998 LDO setting error!\n");
-			return -1;
+			return -EINVAL;
+		}
+
+		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
+		reg &= ~MAX8998_LDO8;
+		ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
+		if (ret) {
+			puts("MAX8998 LDO setting error!\n");
+			return -EINVAL;
 		}
 		status = 0;
 	}
 	udelay(10000);
-
 	return 0;
 }
 
diff --git a/board/samsung/odroid/MAINTAINERS b/board/samsung/odroid/MAINTAINERS
index 2131d36..3f2cf14 100644
--- a/board/samsung/odroid/MAINTAINERS
+++ b/board/samsung/odroid/MAINTAINERS
@@ -1,5 +1,5 @@
 ODROID BOARD
-M:	Przemyslaw Marczak <p.marczak@samsung.com>
+M:	Jaehoon Chung <jh80.chung@samsung.com>
 S:	Maintained
 F:	board/samsung/odroid/
 F:	include/configs/odroid.h
diff --git a/board/samsung/smdk2410/Kconfig b/board/samsung/smdk2410/Kconfig
deleted file mode 100644
index e987b64..0000000
--- a/board/samsung/smdk2410/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_SMDK2410
-
-config SYS_BOARD
-	default "smdk2410"
-
-config SYS_VENDOR
-	default "samsung"
-
-config SYS_SOC
-	default "s3c24x0"
-
-config SYS_CONFIG_NAME
-	default "smdk2410"
-
-endif
diff --git a/board/samsung/smdk2410/MAINTAINERS b/board/samsung/smdk2410/MAINTAINERS
deleted file mode 100644
index 12a25e8..0000000
--- a/board/samsung/smdk2410/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SMDK2410 BOARD
-M:	David Müller <d.mueller@elsoft.ch>
-S:	Maintained
-F:	board/samsung/smdk2410/
-F:	include/configs/smdk2410.h
-F:	configs/smdk2410_defconfig
diff --git a/board/samsung/smdk2410/Makefile b/board/samsung/smdk2410/Makefile
deleted file mode 100644
index 1939a21..0000000
--- a/board/samsung/smdk2410/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= smdk2410.o
-obj-y	+= lowlevel_init.o
diff --git a/board/samsung/smdk2410/lowlevel_init.S b/board/samsung/smdk2410/lowlevel_init.S
deleted file mode 100644
index c3f4187..0000000
--- a/board/samsung/smdk2410/lowlevel_init.S
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the Samsung SMDK2410 by
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-
-#include <config.h>
-
-/* some parameters for the board */
-
-/*
- *
- * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
- *
- * Copyright (C) 2002 Samsung Electronics SW.LEE  <hitchcar@sec.samsung.com>
- *
- */
-
-#define BWSCON	0x48000000
-
-/* BWSCON */
-#define DW8			(0x0)
-#define DW16			(0x1)
-#define DW32			(0x2)
-#define WAIT			(0x1<<2)
-#define UBLB			(0x1<<3)
-
-#define B1_BWSCON		(DW32)
-#define B2_BWSCON		(DW16)
-#define B3_BWSCON		(DW16 + WAIT + UBLB)
-#define B4_BWSCON		(DW16)
-#define B5_BWSCON		(DW16)
-#define B6_BWSCON		(DW32)
-#define B7_BWSCON		(DW32)
-
-/* BANK0CON */
-#define B0_Tacs			0x0	/*  0clk */
-#define B0_Tcos			0x0	/*  0clk */
-#define B0_Tacc			0x7	/* 14clk */
-#define B0_Tcoh			0x0	/*  0clk */
-#define B0_Tah			0x0	/*  0clk */
-#define B0_Tacp			0x0
-#define B0_PMC			0x0	/* normal */
-
-/* BANK1CON */
-#define B1_Tacs			0x0	/*  0clk */
-#define B1_Tcos			0x0	/*  0clk */
-#define B1_Tacc			0x7	/* 14clk */
-#define B1_Tcoh			0x0	/*  0clk */
-#define B1_Tah			0x0	/*  0clk */
-#define B1_Tacp			0x0
-#define B1_PMC			0x0
-
-#define B2_Tacs			0x0
-#define B2_Tcos			0x0
-#define B2_Tacc			0x7
-#define B2_Tcoh			0x0
-#define B2_Tah			0x0
-#define B2_Tacp			0x0
-#define B2_PMC			0x0
-
-#define B3_Tacs			0x0	/*  0clk */
-#define B3_Tcos			0x3	/*  4clk */
-#define B3_Tacc			0x7	/* 14clk */
-#define B3_Tcoh			0x1	/*  1clk */
-#define B3_Tah			0x0	/*  0clk */
-#define B3_Tacp			0x3     /*  6clk */
-#define B3_PMC			0x0	/* normal */
-
-#define B4_Tacs			0x0	/*  0clk */
-#define B4_Tcos			0x0	/*  0clk */
-#define B4_Tacc			0x7	/* 14clk */
-#define B4_Tcoh			0x0	/*  0clk */
-#define B4_Tah			0x0	/*  0clk */
-#define B4_Tacp			0x0
-#define B4_PMC			0x0	/* normal */
-
-#define B5_Tacs			0x0	/*  0clk */
-#define B5_Tcos			0x0	/*  0clk */
-#define B5_Tacc			0x7	/* 14clk */
-#define B5_Tcoh			0x0	/*  0clk */
-#define B5_Tah			0x0	/*  0clk */
-#define B5_Tacp			0x0
-#define B5_PMC			0x0	/* normal */
-
-#define B6_MT			0x3	/* SDRAM */
-#define B6_Trcd			0x1
-#define B6_SCAN			0x1	/* 9bit */
-
-#define B7_MT			0x3	/* SDRAM */
-#define B7_Trcd			0x1	/* 3clk */
-#define B7_SCAN			0x1	/* 9bit */
-
-/* REFRESH parameter */
-#define REFEN			0x1	/* Refresh enable */
-#define TREFMD			0x0	/* CBR(CAS before RAS)/Auto refresh */
-#define Trp			0x0	/* 2clk */
-#define Trc			0x3	/* 7clk */
-#define Tchr			0x2	/* 3clk */
-#define REFCNT			1113	/* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
-/**************************************/
-
-.globl lowlevel_init
-lowlevel_init:
-	/* memory control configuration */
-	/* make r0 relative the current location so that it */
-	/* reads SMRDATA out of FLASH rather than memory ! */
-	ldr     r0, =SMRDATA
-	ldr	r1, =CONFIG_SYS_TEXT_BASE
-	sub	r0, r0, r1
-	ldr	r1, =BWSCON	/* Bus Width Status Controller */
-	add     r2, r0, #13*4
-0:
-	ldr     r3, [r0], #4
-	str     r3, [r1], #4
-	cmp     r2, r0
-	bne     0b
-
-	/* everything is fine now */
-	mov	pc, lr
-
-	.ltorg
-/* the literal pools origin */
-
-SMRDATA:
-    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
-    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
-    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
-    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
-    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
-    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
-    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
-    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
-    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
-    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
-    .word 0x32
-    .word 0x30
-    .word 0x30
diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c
deleted file mode 100644
index 6e678c7..0000000
--- a/board/samsung/smdk2410/smdk2410.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002, 2010
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define FCLK_SPEED 1
-
-#if (FCLK_SPEED == 0)		/* Fout = 203MHz, Fin = 12MHz for Audio */
-#define M_MDIV	0xC3
-#define M_PDIV	0x4
-#define M_SDIV	0x1
-#elif (FCLK_SPEED == 1)		/* Fout = 202.8MHz */
-#define M_MDIV	0xA1
-#define M_PDIV	0x3
-#define M_SDIV	0x1
-#endif
-
-#define USB_CLOCK 1
-
-#if (USB_CLOCK == 0)
-#define U_M_MDIV	0xA1
-#define U_M_PDIV	0x3
-#define U_M_SDIV	0x1
-#elif (USB_CLOCK == 1)
-#define U_M_MDIV	0x48
-#define U_M_PDIV	0x3
-#define U_M_SDIV	0x2
-#endif
-
-static inline void pll_delay(unsigned long loops)
-{
-	__asm__ volatile ("1:\n"
-	  "subs %0, %1, #1\n"
-	  "bne 1b" : "=r" (loops) : "0" (loops));
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_early_init_f(void)
-{
-	struct s3c24x0_clock_power * const clk_power =
-					s3c24x0_get_base_clock_power();
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	/* to reduce PLL lock time, adjust the LOCKTIME register */
-	writel(0xFFFFFF, &clk_power->locktime);
-
-	/* configure MPLL */
-	writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,
-	       &clk_power->mpllcon);
-
-	/* some delay between MPLL and UPLL */
-	pll_delay(4000);
-
-	/* configure UPLL */
-	writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
-	       &clk_power->upllcon);
-
-	/* some delay between MPLL and UPLL */
-	pll_delay(8000);
-
-	/* set up the I/O ports */
-	writel(0x007FFFFF, &gpio->gpacon);
-	writel(0x00044555, &gpio->gpbcon);
-	writel(0x000007FF, &gpio->gpbup);
-	writel(0xAAAAAAAA, &gpio->gpccon);
-	writel(0x0000FFFF, &gpio->gpcup);
-	writel(0xAAAAAAAA, &gpio->gpdcon);
-	writel(0x0000FFFF, &gpio->gpdup);
-	writel(0xAAAAAAAA, &gpio->gpecon);
-	writel(0x0000FFFF, &gpio->gpeup);
-	writel(0x000055AA, &gpio->gpfcon);
-	writel(0x000000FF, &gpio->gpfup);
-	writel(0xFF95FFBA, &gpio->gpgcon);
-	writel(0x0000FFFF, &gpio->gpgup);
-	writel(0x002AFAAA, &gpio->gphcon);
-	writel(0x000007FF, &gpio->gphup);
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* arch number of SMDK2410-Board */
-	gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x30000100;
-
-	icache_enable();
-	dcache_enable();
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	/* dram_init must store complete ramsize in gd->ram_size */
-	gd->ram_size = PHYS_SDRAM_1_SIZE;
-	return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_CS8900
-	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
-#endif
-	return rc;
-}
-#endif
-
-/*
- * Hardcoded flash setup:
- * Flash 0 is a non-CFI AMD AM29LV800BB flash.
- */
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
-	info->portwidth = FLASH_CFI_16BIT;
-	info->chipwidth = FLASH_CFI_BY16;
-	info->interface = FLASH_CFI_X16;
-	return 1;
-}
diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS
index 0361657..590a114 100644
--- a/board/samsung/smdk5420/MAINTAINERS
+++ b/board/samsung/smdk5420/MAINTAINERS
@@ -10,7 +10,7 @@ F:	include/configs/peach-pi.h
 F:	configs/peach-pi_defconfig
 
 ODROID-XU3 BOARD
-M:	Przemyslaw Marczak <p.marczak@samsung.com>
+M:	Jaehoon Chung <jh80.chung@samsung.com>
 S:	Maintained
 F:	board/samsung/smdk5420/
 F:	include/configs/odroid_xu3.h
diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c
index 66b6a98..5d23844 100644
--- a/board/samsung/smdkc100/smdkc100.c
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -11,6 +11,7 @@
 #include <asm/io.h>
 #include <asm/arch/sromc.h>
 #include <netdev.h>
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -51,10 +52,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_DISPLAY_BOARDINFO
diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c
index fc0e8d2..027755d 100644
--- a/board/samsung/smdkv310/smdkv310.c
+++ b/board/samsung/smdkv310/smdkv310.c
@@ -52,7 +52,7 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
@@ -66,6 +66,8 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
 	gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
 							PHYS_SDRAM_4_SIZE);
+
+	return 0;
 }
 
 int board_eth_init(bd_t *bis)
@@ -85,7 +87,7 @@ int checkboard(void)
 }
 #endif
 
-#ifdef CONFIG_GENERIC_MMC
+#ifdef CONFIG_MMC
 int board_mmc_init(bd_t *bis)
 {
 	int i, err;
diff --git a/board/samsung/trats/MAINTAINERS b/board/samsung/trats/MAINTAINERS
index 1b219b4..060bcdb 100644
--- a/board/samsung/trats/MAINTAINERS
+++ b/board/samsung/trats/MAINTAINERS
@@ -1,5 +1,5 @@
 TRATS BOARD
-M:	Lukasz Majewski <l.majewski@samsung.com>
+M:	Jaehoon Chung <jh80.chung@samsung.com>
 S:	Maintained
 F:	board/samsung/trats/
 F:	include/configs/trats.h
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 66a54d4..00059a1 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -23,6 +23,7 @@
 #include <power/max8997_muic.h>
 #include <power/battery.h>
 #include <power/max17042_fg.h>
+#include <power/pmic.h>
 #include <libtizen.h>
 #include <usb.h>
 #include <usb_mass_storage.h>
@@ -51,24 +52,7 @@ int exynos_init(void)
 	return 0;
 }
 
-void i2c_init_board(void)
-{
-	int err;
-
-	/* I2C_5 -> PMIC */
-	err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
-	if (err) {
-		debug("I2C%d not configured\n", (I2C_5));
-		return;
-	}
-
-	/* I2C_8 -> FG */
-	gpio_request(EXYNOS4_GPIO_Y40, "i2c_clk");
-	gpio_request(EXYNOS4_GPIO_Y41, "i2c_data");
-	gpio_direction_output(EXYNOS4_GPIO_Y40, 1);
-	gpio_direction_output(EXYNOS4_GPIO_Y41, 1);
-}
-
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
 static void trats_low_power_mode(void)
 {
 	struct exynos4_clock *clk =
@@ -126,158 +110,11 @@ static void trats_low_power_mode(void)
 	writel(0x0, &clk->gate_ip_image);	/* IMAGE */
 	writel(0x0, &clk->gate_ip_gps);	/* GPS */
 }
-
-static int pmic_init_max8997(void)
-{
-	struct pmic *p = pmic_get("MAX8997_PMIC");
-	int i = 0, ret = 0;
-	u32 val;
-
-	if (pmic_probe(p))
-		return -1;
-
-	/* BUCK1 VARM: 1.2V */
-	val = (1200000 - 650000) / 25000;
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
-	val = ENBUCK | ACTIVE_DISCHARGE;		/* DVS OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
-
-	/* BUCK2 VINT: 1.1V */
-	val = (1100000 - 650000) / 25000;
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
-	val = ENBUCK | ACTIVE_DISCHARGE;		/* DVS OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
-
-
-	/* BUCK3 G3D: 1.1V - OFF */
-	ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
-	val &= ~ENBUCK;
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
-
-	val = (1100000 - 750000) / 50000;
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
-
-	/* BUCK4 CAMISP: 1.2V - OFF */
-	ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
-	val &= ~ENBUCK;
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
-
-	val = (1200000 - 650000) / 25000;
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
-
-	/* BUCK5 VMEM: 1.2V */
-	val = (1200000 - 650000) / 25000;
-	for (i = 0; i < 8; i++)
-		ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
-
-	val = ENBUCK | ACTIVE_DISCHARGE;		/* DVS OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
-
-	/* BUCK6 CAM AF: 2.8V */
-	/* No Voltage Setting Register */
-	/* GNSLCT 3.0X */
-	val = GNSLCT;
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
-
-	/* BUCK7 VCC_SUB: 2.0V */
-	val = (2000000 - 750000) / 50000;
-	ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
-
-	/* LDO1 VADC: 3.3V */
-	val = max8997_reg_ldo(3300000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
-
-	/* LDO1 Disable active discharging */
-	ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
-	val &= ~LDO_ADE;
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
-
-	/* LDO2 VALIVE: 1.1V */
-	val = max8997_reg_ldo(1100000) | EN_LDO;
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
-
-	/* LDO3 VUSB/MIPI: 1.1V */
-	val = max8997_reg_ldo(1100000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
-
-	/* LDO4 VMIPI: 1.8V */
-	val = max8997_reg_ldo(1800000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
-
-	/* LDO5 VHSIC: 1.2V */
-	val = max8997_reg_ldo(1200000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
-
-	/* LDO6 VCC_1.8V_PDA: 1.8V */
-	val = max8997_reg_ldo(1800000) | EN_LDO;
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
-
-	/* LDO7 CAM_ISP: 1.8V */
-	val = max8997_reg_ldo(1800000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
-
-	/* LDO8 VDAC/VUSB: 3.3V */
-	val = max8997_reg_ldo(3300000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
-
-	/* LDO9 VCC_2.8V_PDA: 2.8V */
-	val = max8997_reg_ldo(2800000) | EN_LDO;
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
-
-	/* LDO10 VPLL: 1.1V */
-	val = max8997_reg_ldo(1100000) | EN_LDO;
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
-
-	/* LDO11 TOUCH: 2.8V */
-	val = max8997_reg_ldo(2800000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
-
-	/* LDO12 VTCAM: 1.8V */
-	val = max8997_reg_ldo(1800000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
-
-	/* LDO13 VCC_3.0_LCD: 3.0V */
-	val = max8997_reg_ldo(3000000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
-
-	/* LDO14 MOTOR: 3.0V */
-	val = max8997_reg_ldo(3000000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
-
-	/* LDO15 LED_A: 2.8V */
-	val = max8997_reg_ldo(2800000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
-
-	/* LDO16 CAM_SENSOR: 1.8V */
-	val = max8997_reg_ldo(1800000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
-
-	/* LDO17 VTF: 2.8V */
-	val = max8997_reg_ldo(2800000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
-
-	/* LDO18 TOUCH_LED 3.3V */
-	val = max8997_reg_ldo(3300000) | DIS_LDO;	/* OFF */
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
-
-	/* LDO21 VDDQ: 1.2V */
-	val = max8997_reg_ldo(1200000) | EN_LDO;
-	ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
-
-	/* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
-	val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
-		ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
-	ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
-
-	if (ret) {
-		puts("MAX8997 PMIC setting error!\n");
-		return -1;
-	}
-	return 0;
-}
+#endif
 
 int exynos_power_init(void)
 {
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
 	int chrg, ret;
 	struct power_battery *pb;
 	struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
@@ -289,9 +126,7 @@ int exynos_power_init(void)
 	 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
 	 * to logical I2C adapter 1
 	 */
-	ret = pmic_init(I2C_5);
-	ret |= pmic_init_max8997();
-	ret |= power_fg_init(I2C_9);
+	ret = power_fg_init(I2C_9);
 	ret |= power_muic_init(I2C_5);
 	ret |= power_bat_init(0);
 	if (ret)
@@ -341,6 +176,7 @@ int exynos_power_init(void)
 
 	if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
 		puts("CHARGE Battery !\n");
+#endif
 
 	return 0;
 }
@@ -384,36 +220,58 @@ static void check_hw_revision(void)
 #ifdef CONFIG_USB_GADGET
 static int s5pc210_phy_control(int on)
 {
-	int ret = 0;
-	u32 val = 0;
-	struct pmic *p = pmic_get("MAX8997_PMIC");
-	if (!p)
-		return -ENODEV;
+	struct udevice *dev;
+	int reg, ret;
 
-	if (pmic_probe(p))
-		return -1;
+	ret = pmic_get("max8997-pmic", &dev);
+	if (ret)
+		return ret;
 
 	if (on) {
-		ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
-				      ENSAFEOUT1, LDO_ON);
-		ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
-		ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
-
-		ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
-		ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
+		reg = pmic_reg_read(dev, MAX8997_REG_SAFEOUTCTRL);
+		reg |= ENSAFEOUT1;
+		ret = pmic_reg_write(dev, MAX8997_REG_SAFEOUTCTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
+		reg = pmic_reg_read(dev, MAX8997_REG_LDO3CTRL);
+		reg |= EN_LDO;
+		ret = pmic_reg_write(dev, MAX8997_REG_LDO3CTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
+		reg = pmic_reg_read(dev, MAX8997_REG_LDO8CTRL);
+		reg |= EN_LDO;
+		ret = pmic_reg_write(dev, MAX8997_REG_LDO8CTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
 	} else {
-		ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
-		ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
-
-		ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
-		ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
-		ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
-				      ENSAFEOUT1, LDO_OFF);
-	}
+		reg = pmic_reg_read(dev, MAX8997_REG_LDO8CTRL);
+		reg &= DIS_LDO;
+		ret = pmic_reg_write(dev, MAX8997_REG_LDO8CTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
+		reg = pmic_reg_read(dev, MAX8997_REG_LDO3CTRL);
+		reg &= DIS_LDO;
+		ret = pmic_reg_write(dev, MAX8997_REG_LDO3CTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
+		reg = pmic_reg_read(dev, MAX8997_REG_SAFEOUTCTRL);
+		reg &= ~ENSAFEOUT1;
+		ret = pmic_reg_write(dev, MAX8997_REG_SAFEOUTCTRL, reg);
+		if (ret) {
+			puts("MAX8997 setting error!\n");
+			return ret;
+		}
 
-	if (ret) {
-		puts("MAX8997 LDO setting error!\n");
-		return -1;
 	}
 
 	return 0;
@@ -435,11 +293,16 @@ int board_usb_init(int index, enum usb_init_type init)
 
 int g_dnl_board_usb_cable_connected(void)
 {
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
 	struct pmic *muic = pmic_get("MAX8997_MUIC");
 	if (!muic)
 		return 0;
 
 	return !!muic->chrg->chrg_type(muic);
+#else
+	return false;
+#endif
+
 }
 #endif
 
@@ -552,6 +415,7 @@ void exynos_reset_lcd(void)
 
 int lcd_power(void)
 {
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
 	int ret = 0;
 	struct pmic *p = pmic_get("MAX8997_PMIC");
 	if (!p)
@@ -569,12 +433,13 @@ int lcd_power(void)
 		puts("MAX8997 LDO setting error!\n");
 		return -1;
 	}
-
+#endif
 	return 0;
 }
 
 int mipi_power(void)
 {
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
 	int ret = 0;
 	struct pmic *p = pmic_get("MAX8997_PMIC");
 	if (!p)
@@ -592,7 +457,7 @@ int mipi_power(void)
 		puts("MAX8997 LDO setting error!\n");
 		return -1;
 	}
-
+#endif
 	return 0;
 }
 
diff --git a/board/samsung/trats2/MAINTAINERS b/board/samsung/trats2/MAINTAINERS
index 7018300..ba17b4e 100644
--- a/board/samsung/trats2/MAINTAINERS
+++ b/board/samsung/trats2/MAINTAINERS
@@ -1,5 +1,5 @@
 TRATS2 BOARD
-M:	Lukasz Majewski <l.majewski@samsung.com>
+M:	Jaehoon Chung <jh80.chung@samsung.com>
 S:	Maintained
 F:	board/samsung/trats2/
 F:	include/configs/trats2.h
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index 7b28ae8..f9acbd3 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -100,50 +100,6 @@ static void board_external_gpio_init(void)
 	gpio_set_pull(EXYNOS4X12_GPIO_X37, S5P_GPIO_PULL_NONE);	/* HDMI_HPD */
 }
 
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
-static void board_init_i2c(void)
-{
-	int err;
-
-	/* I2C_7 */
-	err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
-	if (err) {
-		debug("I2C%d not configured\n", (I2C_7));
-		return;
-	}
-
-	/* I2C_8 */
-	gpio_request(EXYNOS4X12_GPIO_F14, "i2c8_clk");
-	gpio_request(EXYNOS4X12_GPIO_F15, "i2c8_data");
-	gpio_direction_output(EXYNOS4X12_GPIO_F14, 1);
-	gpio_direction_output(EXYNOS4X12_GPIO_F15, 1);
-
-	/* I2C_9 */
-	gpio_request(EXYNOS4X12_GPIO_M21, "i2c9_clk");
-	gpio_request(EXYNOS4X12_GPIO_M20, "i2c9_data");
-	gpio_direction_output(EXYNOS4X12_GPIO_M21, 1);
-	gpio_direction_output(EXYNOS4X12_GPIO_M20, 1);
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_SOFT
-int get_soft_i2c_scl_pin(void)
-{
-	if (I2C_ADAP_HWNR)
-		return EXYNOS4X12_GPIO_M21; /* I2C9 */
-	else
-		return EXYNOS4X12_GPIO_F14; /* I2C8 */
-}
-
-int get_soft_i2c_sda_pin(void)
-{
-	if (I2C_ADAP_HWNR)
-		return EXYNOS4X12_GPIO_M20; /* I2C9 */
-	else
-		return EXYNOS4X12_GPIO_F15; /* I2C8 */
-}
-#endif
-
 int exynos_early_init_f(void)
 {
 	board_external_gpio_init();
@@ -151,8 +107,6 @@ int exynos_early_init_f(void)
 	return 0;
 }
 
-static int pmic_init_max77686(void);
-
 int exynos_init(void)
 {
 	struct exynos4_power *pwr =
@@ -176,15 +130,11 @@ int exynos_init(void)
 
 int exynos_power_init(void)
 {
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
 	int chrg;
 	struct power_battery *pb;
 	struct pmic *p_chrg, *p_muic, *p_fg, *p_bat;
 
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
-	board_init_i2c();
-#endif
-	pmic_init(I2C_7);		/* I2C adapter 7 - bus name s3c24x0_7 */
-	pmic_init_max77686();
 	pmic_init_max77693(I2C_10);	/* I2C adapter 10 - bus name soft1 */
 	power_muic_init(I2C_10);	/* I2C adapter 10 - bus name soft1 */
 	power_fg_init(I2C_9);		/* I2C adapter 9 - bus name soft0 */
@@ -236,13 +186,14 @@ int exynos_power_init(void)
 
 	if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
 		puts("CHARGE Battery !\n");
-
+#endif
 	return 0;
 }
 
 #ifdef CONFIG_USB_GADGET
 static int s5pc210_phy_control(int on)
 {
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
 	int ret = 0;
 	unsigned int val;
 	struct pmic *p, *p_pmic, *p_muic;
@@ -299,7 +250,7 @@ static int s5pc210_phy_control(int on)
 
 	if (ret)
 		return -1;
-
+#endif
 	return 0;
 }
 
@@ -319,66 +270,17 @@ int board_usb_init(int index, enum usb_init_type init)
 
 int g_dnl_board_usb_cable_connected(void)
 {
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
 	struct pmic *muic = pmic_get("MAX77693_MUIC");
 	if (!muic)
 		return 0;
 
 	return !!muic->chrg->chrg_type(muic);
-}
+#else
+	return false;
 #endif
-
-static int pmic_init_max77686(void)
-{
-	struct pmic *p = pmic_get("MAX77686_PMIC");
-
-	if (pmic_probe(p))
-		return -1;
-
-	/* BUCK/LDO Output Voltage */
-	max77686_set_ldo_voltage(p, 21, 2800000);	/* LDO21 VTF_2.8V */
-	max77686_set_ldo_voltage(p, 23, 3300000);	/* LDO23 TSP_AVDD_3.3V*/
-	max77686_set_ldo_voltage(p, 24, 1800000);	/* LDO24 TSP_VDD_1.8V */
-
-	/* BUCK/LDO Output Mode */
-	max77686_set_buck_mode(p, 1, OPMODE_STANDBY);	/* BUCK1 VMIF_1.1V_AP */
-	max77686_set_buck_mode(p, 2, OPMODE_ON);	/* BUCK2 VARM_1.0V_AP */
-	max77686_set_buck_mode(p, 3, OPMODE_ON);	/* BUCK3 VINT_1.0V_AP */
-	max77686_set_buck_mode(p, 4, OPMODE_ON);	/* BUCK4 VG3D_1.0V_AP */
-	max77686_set_buck_mode(p, 5, OPMODE_ON);	/* BUCK5 VMEM_1.2V_AP */
-	max77686_set_buck_mode(p, 6, OPMODE_ON);	/* BUCK6 VCC_SUB_1.35V*/
-	max77686_set_buck_mode(p, 7, OPMODE_ON);	/* BUCK7 VCC_SUB_2.0V */
-	max77686_set_buck_mode(p, 8, OPMODE_OFF);	/* VMEM_VDDF_2.85V */
-	max77686_set_buck_mode(p, 9, OPMODE_OFF);	/* CAM_ISP_CORE_1.2V*/
-
-	max77686_set_ldo_mode(p, 1, OPMODE_LPM);	/* LDO1 VALIVE_1.0V_AP*/
-	max77686_set_ldo_mode(p, 2, OPMODE_STANDBY);	/* LDO2 VM1M2_1.2V_AP */
-	max77686_set_ldo_mode(p, 3, OPMODE_LPM);	/* LDO3 VCC_1.8V_AP */
-	max77686_set_ldo_mode(p, 4, OPMODE_LPM);	/* LDO4 VCC_2.8V_AP */
-	max77686_set_ldo_mode(p, 5, OPMODE_OFF);	/* LDO5_VCC_1.8V_IO */
-	max77686_set_ldo_mode(p, 6, OPMODE_STANDBY);	/* LDO6 VMPLL_1.0V_AP */
-	max77686_set_ldo_mode(p, 7, OPMODE_STANDBY);	/* LDO7 VPLL_1.0V_AP */
-	max77686_set_ldo_mode(p, 8, OPMODE_LPM);	/* LDO8 VMIPI_1.0V_AP */
-	max77686_set_ldo_mode(p, 9, OPMODE_OFF);	/* CAM_ISP_MIPI_1.2*/
-	max77686_set_ldo_mode(p, 10, OPMODE_LPM);	/* LDO10 VMIPI_1.8V_AP*/
-	max77686_set_ldo_mode(p, 11, OPMODE_STANDBY);	/* LDO11 VABB1_1.8V_AP*/
-	max77686_set_ldo_mode(p, 12, OPMODE_LPM);	/* LDO12 VUOTG_3.0V_AP*/
-	max77686_set_ldo_mode(p, 13, OPMODE_OFF);	/* LDO13 VC2C_1.8V_AP */
-	max77686_set_ldo_mode(p, 14, OPMODE_STANDBY);	/* VABB02_1.8V_AP */
-	max77686_set_ldo_mode(p, 15, OPMODE_STANDBY);	/* LDO15 VHSIC_1.0V_AP*/
-	max77686_set_ldo_mode(p, 16, OPMODE_STANDBY);	/* LDO16 VHSIC_1.8V_AP*/
-	max77686_set_ldo_mode(p, 17, OPMODE_OFF);	/* CAM_SENSOR_CORE_1.2*/
-	max77686_set_ldo_mode(p, 18, OPMODE_OFF);	/* CAM_ISP_SEN_IO_1.8V*/
-	max77686_set_ldo_mode(p, 19, OPMODE_OFF);	/* LDO19 VT_CAM_1.8V */
-	max77686_set_ldo_mode(p, 20, OPMODE_ON);	/* LDO20 VDDQ_PRE_1.8V*/
-	max77686_set_ldo_mode(p, 21, OPMODE_OFF);	/* LDO21 VTF_2.8V */
-	max77686_set_ldo_mode(p, 22, OPMODE_OFF);	/* LDO22 VMEM_VDD_2.8V*/
-	max77686_set_ldo_mode(p, 23, OPMODE_OFF);	/* LDO23 TSP_AVDD_3.3V*/
-	max77686_set_ldo_mode(p, 24, OPMODE_OFF);	/* LDO24 TSP_VDD_1.8V */
-	max77686_set_ldo_mode(p, 25, OPMODE_OFF);	/* LDO25 VCC_3.3V_LCD */
-	max77686_set_ldo_mode(p, 26, OPMODE_OFF);	/*LDO26 VCC_3.0V_MOTOR*/
-
-	return 0;
 }
+#endif
 
 /*
  * LCD
@@ -387,18 +289,21 @@ static int pmic_init_max77686(void)
 #ifdef CONFIG_LCD
 int mipi_power(void)
 {
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
 	struct pmic *p = pmic_get("MAX77686_PMIC");
 
 	/* LDO8 VMIPI_1.0V_AP */
 	max77686_set_ldo_mode(p, 8, OPMODE_ON);
 	/* LDO10 VMIPI_1.8V_AP */
 	max77686_set_ldo_mode(p, 10, OPMODE_ON);
+#endif
 
 	return 0;
 }
 
 void exynos_lcd_power_on(void)
 {
+#ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */
 	struct pmic *p = pmic_get("MAX77686_PMIC");
 
 	/* LCD_2.2V_EN: GPC0[1] */
@@ -410,6 +315,7 @@ void exynos_lcd_power_on(void)
 	pmic_probe(p);
 	max77686_set_ldo_voltage(p, 25, 3100000);
 	max77686_set_ldo_mode(p, 25, OPMODE_LPM);
+#endif
 }
 
 void exynos_reset_lcd(void)
diff --git a/board/samsung/universal_c210/MAINTAINERS b/board/samsung/universal_c210/MAINTAINERS
index 6760678..00d6110 100644
--- a/board/samsung/universal_c210/MAINTAINERS
+++ b/board/samsung/universal_c210/MAINTAINERS
@@ -1,5 +1,5 @@
 UNIVERSAL_C210 BOARD
-M:	Przemyslaw Marczak <p.marczak@samsung.com>
+M:	Jaehoon Chung <jh80.chung@samsung.com>
 S:	Maintained
 F:	board/samsung/universal_c210/
 F:	include/configs/s5pc210_universal.h
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
index 81e35b6..cc6eaf7 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -23,38 +23,26 @@
 #include <libtizen.h>
 #include <samsung/misc.h>
 #include <usb_mass_storage.h>
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 unsigned int board_rev;
+static int init_pmic_lcd(void);
 
 u32 get_board_rev(void)
 {
 	return board_rev;
 }
 
-static int get_hwrev(void)
+int exynos_power_init(void)
 {
-	return board_rev & 0xFF;
+	return init_pmic_lcd();
 }
 
-static void init_pmic_lcd(void);
-
-int exynos_power_init(void)
+static int get_hwrev(void)
 {
-	int ret;
-
-	/*
-	 * For PMIC the I2C bus is named as I2C5, but it is connected
-	 * to logical I2C adapter 0
-	 */
-	ret = pmic_init(I2C_0);
-	if (ret)
-		return ret;
-
-	init_pmic_lcd();
-
-	return 0;
+	return board_rev & 0xFF;
 }
 
 static unsigned short get_adc_value(int channel)
@@ -84,19 +72,29 @@ static unsigned short get_adc_value(int channel)
 
 static int adc_power_control(int on)
 {
+	struct udevice *dev;
 	int ret;
-	struct pmic *p = pmic_get("MAX8998_PMIC");
-	if (!p)
-		return -ENODEV;
+	u8 reg;
 
-	if (pmic_probe(p))
-		return -1;
+	ret = pmic_get("max8998-pmic", &dev);
+	if (ret) {
+		puts("Failed to get MAX8998!\n");
+		return ret;
+	}
 
-	ret = pmic_set_output(p,
-			      MAX8998_REG_ONOFF1,
-			      MAX8998_LDO4, !!on);
+	reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
+	if (on)
+		reg |= MAX8998_LDO4;
+	else
+		reg &= ~MAX8998_LDO4;
 
-	return ret;
+	ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
+	if (ret) {
+		puts("MAX8998 LDO setting error\n");
+		return -EINVAL;
+	}
+
+	return 0;
 }
 
 static unsigned int get_hw_revision(void)
@@ -144,36 +142,48 @@ static void check_hw_revision(void)
 #ifdef CONFIG_USB_GADGET
 static int s5pc210_phy_control(int on)
 {
-	int ret = 0;
-	struct pmic *p = pmic_get("MAX8998_PMIC");
-	if (!p)
-		return -ENODEV;
+	struct udevice *dev;
+	int ret;
+	u8 reg;
 
-	if (pmic_probe(p))
-		return -1;
+	ret = pmic_get("max8998-pmic", &dev);
+	if (ret) {
+		puts("Failed to get MAX8998!\n");
+		return ret;
+	}
 
 	if (on) {
-		ret |= pmic_set_output(p,
-				       MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
-				       MAX8998_SAFEOUT1, LDO_ON);
-		ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
-				      MAX8998_LDO3, LDO_ON);
-		ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
-				      MAX8998_LDO8, LDO_ON);
+		reg = pmic_reg_read(dev, MAX8998_REG_BUCK_ACTIVE_DISCHARGE3);
+		reg |= MAX8998_SAFEOUT1;
+		ret |= pmic_reg_write(dev,
+			MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, reg);
+
+		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
+		reg |= MAX8998_LDO3;
+		ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
+
+		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
+		reg |= MAX8998_LDO8;
+		ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
 
 	} else {
-		ret |= pmic_set_output(p, MAX8998_REG_ONOFF2,
-				      MAX8998_LDO8, LDO_OFF);
-		ret |= pmic_set_output(p, MAX8998_REG_ONOFF1,
-				      MAX8998_LDO3, LDO_OFF);
-		ret |= pmic_set_output(p,
-				       MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
-				       MAX8998_SAFEOUT1, LDO_OFF);
+		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
+		reg &= ~MAX8998_LDO8;
+		ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
+
+		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
+		reg &= ~MAX8998_LDO3;
+		ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
+
+		reg = pmic_reg_read(dev, MAX8998_REG_BUCK_ACTIVE_DISCHARGE3);
+		reg &= ~MAX8998_SAFEOUT1;
+		ret |= pmic_reg_write(dev,
+			MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, reg);
 	}
 
 	if (ret) {
 		puts("MAX8998 LDO setting error!\n");
-		return -1;
+		return -EINVAL;
 	}
 
 	return 0;
@@ -201,26 +211,25 @@ int exynos_early_init_f(void)
 	return 0;
 }
 
-static void init_pmic_lcd(void)
+static int init_pmic_lcd(void)
 {
+	struct udevice *dev;
 	unsigned char val;
 	int ret = 0;
 
-	struct pmic *p = pmic_get("MAX8998_PMIC");
-
-	if (!p)
-		return;
-
-	if (pmic_probe(p))
-		return;
+	ret = pmic_get("max8998-pmic", &dev);
+	if (ret) {
+		puts("Failed to get MAX8998 for init_pmic_lcd()!\n");
+		return ret;
+	}
 
 	/* LDO7 1.8V */
 	val = 0x02; /* (1800 - 1600) / 100; */
-	ret |= pmic_reg_write(p,  MAX8998_REG_LDO7, val);
+	ret |= pmic_reg_write(dev,  MAX8998_REG_LDO7, val);
 
 	/* LDO17 3.0V */
 	val = 0xe; /* (3000 - 1600) / 100; */
-	ret |= pmic_reg_write(p,  MAX8998_REG_LDO17, val);
+	ret |= pmic_reg_write(dev,  MAX8998_REG_LDO17, val);
 
 	/* Disable unneeded regulators */
 	/*
@@ -229,24 +238,28 @@ static void init_pmic_lcd(void)
 	 * LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON
 	 */
 	val = 0xB9;
-	ret |= pmic_reg_write(p,  MAX8998_REG_ONOFF1, val);
+	ret |= pmic_reg_write(dev,  MAX8998_REG_ONOFF1, val);
 
 	/* ONOFF2
 	 * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON,
 	 * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF
 	 */
 	val = 0x50;
-	ret |= pmic_reg_write(p,  MAX8998_REG_ONOFF2, val);
+	ret |= pmic_reg_write(dev,  MAX8998_REG_ONOFF2, val);
 
 	/* ONOFF3
 	 * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF
 	 * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF
 	 */
 	val = 0x00;
-	ret |= pmic_reg_write(p,  MAX8998_REG_ONOFF3, val);
+	ret |= pmic_reg_write(dev,  MAX8998_REG_ONOFF3, val);
 
-	if (ret)
+	if (ret) {
 		puts("LCD pmic initialisation error!\n");
+		return -EINVAL;
+	}
+
+	return 0;
 }
 
 void exynos_cfg_lcd_gpio(void)
@@ -304,16 +317,31 @@ void exynos_reset_lcd(void)
 
 void exynos_lcd_power_on(void)
 {
-	struct pmic *p = pmic_get("MAX8998_PMIC");
+	struct udevice *dev;
+	int ret;
+	u8 reg;
 
-	if (!p)
+	ret = pmic_get("max8998-pmic", &dev);
+	if (ret) {
+		puts("Failed to get MAX8998!\n");
 		return;
+	}
 
-	if (pmic_probe(p))
+	reg = pmic_reg_read(dev, MAX8998_REG_ONOFF3);
+	reg |= MAX8998_LDO17;
+	ret = pmic_reg_write(dev, MAX8998_REG_ONOFF3, reg);
+	if (ret) {
+		puts("MAX8998 LDO setting error\n");
 		return;
+	}
 
-	pmic_set_output(p, MAX8998_REG_ONOFF3, MAX8998_LDO17, LDO_ON);
-	pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON);
+	reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
+	reg |= MAX8998_LDO7;
+	ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
+	if (ret) {
+		puts("MAX8998 LDO setting error\n");
+		return;
+	}
 }
 
 void exynos_cfg_ldo(void)
@@ -328,8 +356,6 @@ void exynos_enable_ldo(unsigned int onoff)
 
 int exynos_init(void)
 {
-	char buf[16];
-
 	gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
 
 	switch (get_hwrev()) {
@@ -354,13 +380,6 @@ int exynos_init(void)
 		break;
 	}
 
-	/* Request soft I2C gpios */
-	strcpy(buf, "soft_i2c_scl");
-	gpio_request(CONFIG_SOFT_I2C_GPIO_SCL, buf);
-
-	strcpy(buf, "soft_i2c_sda");
-	gpio_request(CONFIG_SOFT_I2C_GPIO_SDA, buf);
-
 	check_hw_revision();
 	printf("HW Revision:\t0x%x\n", board_rev);
 
diff --git a/board/samtec/vining_2000/Kconfig b/board/samtec/vining_2000/Kconfig
new file mode 100644
index 0000000..3447c27
--- /dev/null
+++ b/board/samtec/vining_2000/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SAMTEC_VINING_2000
+
+config SYS_BOARD
+	default "vining_2000"
+
+config SYS_VENDOR
+	default "samtec"
+
+config SYS_CONFIG_NAME
+	default "vining_2000"
+
+endif
diff --git a/board/samtec/vining_2000/MAINTAINERS b/board/samtec/vining_2000/MAINTAINERS
new file mode 100644
index 0000000..027e527
--- /dev/null
+++ b/board/samtec/vining_2000/MAINTAINERS
@@ -0,0 +1,6 @@
+VINING_2000 BOARD
+M:	Ingo Schroeck <open-source@samtec.de>
+S:	Maintained
+F:	board/samtec/vining_2000/
+F:	include/configs/vining_2000.h
+F:	configs/vining_2000_defconfig
diff --git a/board/samtec/vining_2000/Makefile b/board/samtec/vining_2000/Makefile
new file mode 100644
index 0000000..1b32f66
--- /dev/null
+++ b/board/samtec/vining_2000/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 samtec automotive software & electronics gmbh
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := vining_2000.o
diff --git a/board/samtec/vining_2000/imximage.cfg b/board/samtec/vining_2000/imximage.cfg
new file mode 100644
index 0000000..4133dda
--- /dev/null
+++ b/board/samtec/vining_2000/imximage.cfg
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2016 samtec automotive software & electronics gmbh
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* IOMUX - DDR IO Type */
+DATA 4 0x020e0618 0x000c0000
+DATA 4 0x020e05fc 0x00000000
+
+/* Clock */
+DATA 4 0x020e032c 0x00000030
+
+/* Address */
+DATA 4 0x020e0300 0x00000028
+DATA 4 0x020e02fc 0x00000028
+DATA 4 0x020e05f4 0x00000028
+
+/* Control */
+DATA 4 0x020e0340 0x00000028
+
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000028
+DATA 4 0x020e0314 0x00000028
+DATA 4 0x020e0614 0x00000028
+
+/* Data Strobe */
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00000028
+DATA 4 0x020e0334 0x00000028
+DATA 4 0x020e0338 0x00000028
+DATA 4 0x020e033c 0x00000028
+
+/* Data */
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000028
+DATA 4 0x020e0610 0x00000028
+DATA 4 0x020e061c 0x00000028
+DATA 4 0x020e0620 0x00000028
+DATA 4 0x020e02ec 0x00000028
+DATA 4 0x020e02f0 0x00000028
+DATA 4 0x020e02f4 0x00000028
+DATA 4 0x020e02f8 0x00000028
+
+/* Calibrations - ZQ */
+DATA 4 0x021b0800 0xa1390003
+
+/* Write leveling */
+DATA 4 0x021b080c 0x00290025
+DATA 4 0x021b0810 0x00210022
+
+/* DQS Read Gate */
+DATA 4 0x021b083c 0x4142013a
+DATA 4 0x021b0840 0x012e0123
+
+/* Read/Write Delay */
+DATA 4 0x021b0848 0x43474949
+DATA 4 0x021b0850 0x38383c38
+
+/* Read data bit delay */
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+/* Complete calibration by forced measurement */
+DATA 4 0x021b08b8 0x00000800
+
+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333040
+DATA 4 0x021b000c 0x676b52f2
+DATA 4 0x021b0010 0x926e8b63
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00011740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006b1023
+DATA 4 0x021b0040 0x0000005f
+DATA 4 0x021b0000 0x84190000
+
+/* Initialize MT41K256M16HA-125 - MR2 */
+DATA 4 0x021b001c 0x02008032
+/* MR3 */
+DATA 4 0x021b001c 0x00008033
+/* MR1 */
+DATA 4 0x021b001c 0x00048031
+/* MR0 */
+DATA 4 0x021b001c 0x15108030
+/* DDR device ZQ calibration */
+DATA 4 0x021b001c 0x04008040
+
+/* Final DDR setup, before operation start */
+DATA 4 0x021b0020 0x00007800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b001c 0x00000000
diff --git a/board/samtec/vining_2000/vining_2000.c b/board/samtec/vining_2000/vining_2000.c
new file mode 100644
index 0000000..5c8b436
--- /dev/null
+++ b/board/samtec/vining_2000/vining_2000.c
@@ -0,0 +1,517 @@
+/*
+ * Copyright (C) 2016 samtec automotive software & electronics gmbh
+ *
+ * Author: Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/io.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include <pwm.h>
+#include <wait_bit.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |	\
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+	PAD_CTL_SRE_FAST)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE |	\
+	PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm |		\
+	PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL  PAD_CTL_DSE_34ohm
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE |			\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH |		\
+	PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |	\
+	PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm)
+
+#define USDHC_CLK_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
+
+#define USDHC_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |	\
+	PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm |	\
+	PAD_CTL_SRE_FAST)
+
+#define GPIO_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |	\
+	PAD_CTL_PKE)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
+	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_LCD1_VSYNC__GPIO3_IO_28 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
+	MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |
+		MUX_MODE_SION,
+	/* LAN8720 PHY Reset */
+	MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pwm_led_pads[] = {
+	MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
+	MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
+	MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#define PHY_RESET IMX_GPIO_NR(5, 9)
+
+int board_eth_init(bd_t *bis)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+	unsigned char eth1addr[6];
+
+	/* just to get secound mac address */
+	imx_get_mac_from_fuse(1, eth1addr);
+	if (!getenv("eth1addr") && is_valid_ethaddr(eth1addr))
+		eth_setenv_enetaddr("eth1addr", eth1addr);
+
+	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+
+	/*
+	 * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
+	 * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
+	 * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
+	 */
+	clrsetbits_le32(&iomuxc_regs->gpr[1],
+			IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
+			IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
+			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
+			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
+	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+	if (ret)
+		goto eth_fail;
+
+	/* reset phy */
+	gpio_direction_output(PHY_RESET, 0);
+	mdelay(16);
+	gpio_set_value(PHY_RESET, 1);
+	mdelay(1);
+
+	ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
+					IMX_FEC_BASE);
+	if (ret)
+		goto eth_fail;
+
+	return ret;
+
+eth_fail:
+	printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
+	gpio_set_value(PHY_RESET, 0);
+	return ret;
+}
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
+		.gp = IMX_GPIO_NR(1, 0),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
+		.gp = IMX_GPIO_NR(1, 1),
+	},
+};
+
+static struct pmic *pfuze_init(unsigned char i2cbus)
+{
+	struct pmic *p;
+	int ret;
+	u32 reg;
+
+	ret = power_pfuze100_init(i2cbus);
+	if (ret)
+		return NULL;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return NULL;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+	/* Set SW1AB stanby volage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~SW1x_STBY_MASK;
+	reg |= SW1x_0_975V;
+	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
+	reg &= ~SW1xCONF_DVSSPEED_MASK;
+	reg |= SW1xCONF_DVSSPEED_4US;
+	pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
+
+	/* Set SW1C standby voltage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~SW1x_STBY_MASK;
+	reg |= SW1x_0_975V;
+	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+	reg &= ~SW1xCONF_DVSSPEED_MASK;
+	reg |= SW1xCONF_DVSSPEED_4US;
+	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+	return p;
+}
+
+static int pfuze_mode_init(struct pmic *p, u32 mode)
+{
+	unsigned char offset, i, switch_num;
+	u32 id;
+	int ret;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &id);
+	id = id & 0xf;
+
+	if (id == 0) {
+		switch_num = 6;
+		offset = PFUZE100_SW1CMODE;
+	} else if (id == 1) {
+		switch_num = 4;
+		offset = PFUZE100_SW2MODE;
+	} else {
+		printf("Not supported, id=%d\n", id);
+		return -EINVAL;
+	}
+
+	ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
+	if (ret < 0) {
+		printf("Set SW1AB mode error!\n");
+		return ret;
+	}
+
+	for (i = 0; i < switch_num - 1; i++) {
+		ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
+		if (ret < 0) {
+			printf("Set switch 0x%x mode error!\n",
+			       offset + i * SWITCH_SIZE);
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+
+	p = pfuze_init(I2C_PMIC);
+	if (!p)
+		return -ENODEV;
+
+	ret = pfuze_mode_init(p, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+	/* OGT1 */
+	MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* OTG2 */
+	MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_iomux_usb(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+					 ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+	if (port == 1)
+		return USB_INIT_HOST;
+	else
+		return usb_phy_mode(port);
+}
+#endif
+
+#ifdef CONFIG_PWM_IMX
+static int set_pwm_leds(void)
+{
+	int ret;
+
+	imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
+					 ARRAY_SIZE(pwm_led_pads));
+	/* enable backlight PWM 2, green LED */
+	ret = pwm_init(1, 0, 0);
+	if (ret)
+		goto error;
+	/* duty cycle 200ns, period: 8000ns */
+	ret = pwm_config(1, 200, 8000);
+	if (ret)
+		goto error;
+	ret = pwm_enable(1);
+	if (ret)
+		goto error;
+
+	/* enable backlight PWM 1, blue LED */
+	ret = pwm_init(0, 0, 0);
+	if (ret)
+		goto error;
+	/* duty cycle 200ns, period: 8000ns */
+	ret = pwm_config(0, 200, 8000);
+	if (ret)
+		goto error;
+	ret = pwm_enable(0);
+	if (ret)
+		goto error;
+
+	/* enable backlight PWM 6, red LED */
+	ret = pwm_init(5, 0, 0);
+	if (ret)
+		goto error;
+	/* duty cycle 200ns, period: 8000ns */
+	ret = pwm_config(5, 200, 8000);
+	if (ret)
+		goto error;
+	ret = pwm_enable(5);
+
+error:
+	return ret;
+}
+#else
+static int set_pwm_leds(void)
+{
+	return 0;
+}
+#endif
+
+#define ADCx_HC0        0x00
+#define ADCx_HS         0x08
+#define ADCx_HS_C0      BIT(0)
+#define ADCx_R0         0x0c
+#define ADCx_CFG        0x14
+#define ADCx_CFG_SWMODE 0x308
+#define ADCx_GC         0x18
+#define ADCx_GC_CAL     BIT(7)
+
+static int read_adc(u32 *val)
+{
+	int ret;
+	void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
+
+	/* use software mode */
+	writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
+
+	/* start auto calibration */
+	setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
+	ret = wait_for_bit("ADC", b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
+	if (ret)
+		goto adc_exit;
+
+	/* start conversion */
+	writel(0, b + ADCx_HC0);
+
+	/* wait for conversion */
+	ret = wait_for_bit("ADC", b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
+	if (ret)
+		goto adc_exit;
+
+	/* read result */
+	*val = readl(b + ADCx_R0);
+
+adc_exit:
+	if (ret)
+		printf("ADC failure (ret=%i)\n", ret);
+	unmap_physmem(b, MAP_NOCACHE);
+	return ret;
+}
+
+#define VAL_UPPER	2498
+#define VAL_LOWER	1550
+
+static int set_pin_state(void)
+{
+	u32 val;
+	int ret;
+
+	ret = read_adc(&val);
+	if (ret)
+		return ret;
+
+	if (val >= VAL_UPPER)
+		setenv("pin_state", "connected");
+	else if (val < VAL_UPPER && val > VAL_LOWER)
+		setenv("pin_state", "open");
+	else
+		setenv("pin_state", "button");
+
+	return ret;
+}
+
+int board_late_init(void)
+{
+	int ret;
+
+	ret = set_pwm_leds();
+	if (ret)
+		return ret;
+
+	ret = set_pin_state();
+
+	return ret;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	setup_iomux_usb();
+
+	return 0;
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC4_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(3, 28)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+	if (cfg->esdhc_base == USDHC4_BASE_ADDR)
+		return 1;
+	if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+		return !gpio_get_value(USDHC2_CD_GPIO);
+
+	return -EINVAL;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC4
+	 * mmc1                    USDHC2
+	 */
+	imx_iomux_v3_setup_multiple_pads(
+		usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+	imx_iomux_v3_setup_multiple_pads(
+		usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+	gpio_direction_input(USDHC2_CD_GPIO);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+	if (ret) {
+		printf("Warning: failed to initialize USDHC4\n");
+		return ret;
+	}
+
+	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+	if (ret) {
+		printf("Warning: failed to initialize USDHC2\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C_MXC
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: VIN|ING 2000\n");
+
+	return 0;
+}
diff --git a/board/samtec/vining_fpga/qts/sdram_config.h b/board/samtec/vining_fpga/qts/sdram_config.h
index 74cb405..372e8bc 100644
--- a/board/samtec/vining_fpga/qts/sdram_config.h
+++ b/board/samtec/vining_fpga/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			6
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		200
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x0
diff --git a/board/samtec/vining_fpga/socfpga.c b/board/samtec/vining_fpga/socfpga.c
index f3a92b5..f888ecb 100644
--- a/board/samtec/vining_fpga/socfpga.c
+++ b/board/samtec/vining_fpga/socfpga.c
@@ -21,8 +21,8 @@ int board_late_init(void)
 	const unsigned int usb_nrst_gpio = 35;
 	int ret;
 
-	status_led_set(1, STATUS_LED_ON);
-	status_led_set(2, STATUS_LED_ON);
+	status_led_set(1, CONFIG_LED_STATUS_ON);
+	status_led_set(2, CONFIG_LED_STATUS_ON);
 
 	/* Address of boot parameters for ATAG (if ATAG is used) */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
diff --git a/board/sandbox/MAINTAINERS b/board/sandbox/MAINTAINERS
index 4dcbf4b..6d0790c 100644
--- a/board/sandbox/MAINTAINERS
+++ b/board/sandbox/MAINTAINERS
@@ -18,3 +18,10 @@ S:	Maintained
 F:	board/sandbox/
 F:	include/configs/sandbox_spl.h
 F:	configs/sandbox_spl_defconfig
+
+SANDBOX FLAT TREE BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/sandbox/
+F:	include/configs/sandbox.h
+F:	configs/sandbox_flattree_defconfig
diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox
index ed820d3..9dc2eb0 100644
--- a/board/sandbox/README.sandbox
+++ b/board/sandbox/README.sandbox
@@ -320,6 +320,25 @@ CONFIG_SPI_IDLE_VAL
 	The idle value on the SPI bus
 
 
+Block Device Emulation
+----------------------
+
+U-Boot can use raw disk images for block device emulation. To e.g. list
+the contents of the root directory on the second partion of the image
+"disk.raw", you can use the following commands:
+
+=>host bind 0 ./disk.raw
+=>ls host 0:2
+
+A disk image can be created using the following commands:
+
+$> truncate -s 1200M ./disk.raw
+$> echo -e "label: gpt\n,64M,U\n,,L" | /usr/sbin/sgdisk  ./disk.raw
+$> lodev=`sudo losetup -P -f --show ./disk.raw`
+$> sudo mkfs.vfat -n EFI -v ${lodev}p1
+$> sudo mkfs.ext4 -L ROOT -v ${lodev}p2
+
+
 Writing Sandbox Drivers
 -----------------------
 
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 72786d2..a3395ed 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -19,6 +19,8 @@
 #include <libfdt.h>
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int fixed_sdram(void);
 void sdram_init(void);
 
@@ -35,7 +37,7 @@ int board_early_init_f (void)
 
 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;
@@ -61,8 +63,10 @@ phys_size_t initdram (int board_type)
 	 */
 	ddr_enable_ecc(msize * 1024 * 1024);
 #endif
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return (msize * 1024 * 1024);
+	/* set total bus SDRAM size(bytes)  -- DDR */
+	gd->ram_size = msize * 1024 * 1024;
+
+	return 0;
 }
 
 #if !defined(CONFIG_SPD_EEPROM)
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 6bdf1a2..08ced10 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -23,6 +23,8 @@
 #include <libfdt.h>
 #include <fdt_support.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 long int fixed_sdram (void);
 
 int board_early_init_f (void)
@@ -37,7 +39,7 @@ int checkboard (void)
 	return 0;
 }
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	long dram_size = 0;
 
@@ -48,7 +50,9 @@ phys_size_t initdram (int board_type)
 #endif
 
 	debug ("    DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
 #if defined(CONFIG_SYS_DRAM_TEST)
diff --git a/board/scalys/common/Kconfig b/board/scalys/common/Kconfig
new file mode 100644
index 0000000..51cdc24
--- /dev/null
+++ b/board/scalys/common/Kconfig
@@ -0,0 +1,81 @@
+if TARGET_SIMC_TXXXX || TARGET_QT1040_1GB
+
+config SYS_VENDOR
+	default "scalys"
+	
+config RAMBOOT_PBL
+	bool
+	default y
+
+config SPL_FSL_PBL
+	bool
+	default y
+
+config NOR_FLASH
+	bool
+	prompt "Support NOR flash"
+	default y
+
+config NAND_FLASH
+	bool
+	prompt "Support NAND flash"
+	default y
+	
+config SPI_FLASH
+	bool
+	prompt "Support SPI flash"
+	default y
+	
+config SDHC_FLASH
+	bool
+	prompt "Support SDHC flash"
+	default y
+
+choice
+	prompt "SYSCLK frequency"
+	default SYS_CLK_FREQ_100
+
+config SYS_CLK_FREQ_66
+	bool
+	prompt "66.6 MHz"
+	
+config SYS_CLK_FREQ_100
+	bool
+	prompt "100 MHz"
+
+endchoice
+
+choice
+	prompt "Bootsource"
+	default NAND_FLASH_BOOT
+	
+config NAND_FLASH_BOOT
+	bool
+	depends on NAND_FLASH
+	prompt "NAND boot"
+	help
+	Select NAND Flash as the bootsource
+	
+config NOR_FLASH_BOOT
+	bool
+	depends on NOR_FLASH
+	prompt "NOR boot"
+	help
+	Select NOR Flash as the bootsource
+
+config SPI_FLASH_BOOT
+	bool
+	depends on SPI_FLASH
+	prompt "SPI boot"
+	help
+	Select SPI Flash as the bootsource
+	
+config SDHC_FLASH_BOOT
+	bool
+	depends on SDHC_FLASH
+	prompt "SDHC boot"
+	help
+	Select SDHC Flash as the bootsource
+endchoice
+
+endif
diff --git a/board/scalys/common/board_configuration_data.c b/board/scalys/common/board_configuration_data.c
index b6374da..fcb4e92 100644
--- a/board/scalys/common/board_configuration_data.c
+++ b/board/scalys/common/board_configuration_data.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -11,7 +11,7 @@
 #include <fdt_support.h>
 
 #include <i2c.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
 #include <malloc.h>
 
 #include "board_configuration_data.h"
@@ -49,7 +49,7 @@ int add_mac_addressess_to_env(const void* blob)
 			
 		memcpy(mac_address, value, 6);
 		
-		//ret = fdtdec_get_byte_array( blob, prop_offset, propname, mac_address, 6 );
+		/* ret = fdtdec_get_byte_array( blob, prop_offset, propname, mac_address, 6 ); */
 		
 		if (count) {
 			snprintf(eth_string, sizeof(eth_string), "eth%iaddr", count);
@@ -93,17 +93,17 @@ const void* get_boardinfo_eeprom(void)
 	/* Read the last 4 bytes to determine the lenght of the DTB data */
 	ret = i2c_read(BCD_I2C_ADDRESS, (BCD_EEPROM_SIZE-4), 2, (uint8_t*) &bcd_data_lenght, 4 );
 	if (ret != 0) {
-		debug("Error reading bcd length\n");
+		printf("Error reading bcd length\n");
 		errno = -ENODEV;
 		goto err_no_free;
 	}
 	
 	/* Convert lenght from big endianess to architecture endianess */
 	bcd_data_lenght = ntohl(bcd_data_lenght);
-	debug("bcd_data_lenght = %i\n", bcd_data_lenght );	
+	printf("bcd_data_lenght = %i\n", bcd_data_lenght );	
 	
 	if (bcd_data_lenght > BCD_EEPROM_SIZE ) {
-		debug("%02x %02x %02x %02x\n", 
+		printf("BCD data length error %02x %02x %02x %02x\n", 
 		      ( (uint8_t*) &bcd_data_lenght)[0],
 		      ( (uint8_t*) &bcd_data_lenght)[1],
 		      ( (uint8_t*) &bcd_data_lenght)[2],
@@ -115,17 +115,17 @@ const void* get_boardinfo_eeprom(void)
 	/* Allocate, and verify memory for the BCD data */
 	bcd_data = (uint8_t*) malloc(bcd_data_lenght);
 	if (bcd_data == NULL) {
-		debug("Error locating memory for BCD data\n");
+		printf("Error locating memory for BCD data\n");
 		goto err_no_free;
 	}
-	debug("Allocated memory for BCD data\n");
+	printf("Allocated memory for BCD data\n");
 	
 	/* Read the DTB BCD data to memory */
 	ret = i2c_read(BCD_I2C_ADDRESS, (BCD_EEPROM_SIZE-bcd_data_lenght), 2, (uint8_t*) bcd_data, bcd_data_lenght );
-	debug("Read data from I2C bus\n");
+	printf("Read data from I2C bus\n");
 
 	if (ret != 0) {
-		debug("Error reading complete BCD data from EEPROM\n");
+		printf("Error reading complete BCD data from EEPROM\n");
 		errno = -ENOMEM;
 		goto err_free;
 	}
@@ -141,7 +141,7 @@ const void* get_boardinfo_eeprom(void)
 	received_crc = ntohl(received_crc);
 	
    	if (calculated_crc !=  received_crc) {
-		debug("Checksum error. expected %08x, got %08x\n",
+		printf("Checksum error. expected %08x, got %08x\n",
 			calculated_crc, received_crc);
 		errno = -EBADMSG;
 		goto err_free;
@@ -389,4 +389,4 @@ U_BOOT_CMD(
 	"Show the Board Configuration Data (stored in eeprom)",
 	""
 );
-#endif
\ No newline at end of file
+#endif
diff --git a/board/scalys/simc-t10xx/Kconfig b/board/scalys/simc-t10xx/Kconfig
index 2b18913..a82d91d 100644
--- a/board/scalys/simc-t10xx/Kconfig
+++ b/board/scalys/simc-t10xx/Kconfig
@@ -1,72 +1,23 @@
-if TARGET_SIMC_T10XX
+if ((TARGET_SIMC_TXXXX && !ARCH_T2081) || TARGET_QT1040_1GB) 
 
 config SYS_BOARD
 	string
 	default "simc-t10xx"
+	
+endif
 
-config SYS_VENDOR
-	string
-	default "scalys"
+if TARGET_SIMC_TXXXX && !ARCH_T2081
 
 config SYS_CONFIG_NAME
 	string
 	default "simc-t10xx"
-	
-config RAMBOOT_PBL
-	bool
-	default y
-
-config SPL_FSL_PBL
-	bool
-	default y
 
-choice
-	prompt "Bootsource"
-	default NAND
-config NAND
-	bool
-	prompt "NAND boot"
-	help
-	Select NAND as the bootsource
-
-endchoice
-
-choice
-	prompt "SYSCLK frequency"
-	default SYS_CLK_FREQ_100
-
-config SYS_CLK_FREQ_66
-	bool
-	prompt "66.6 MHz"
-	
-config SYS_CLK_FREQ_100
-	bool
-	prompt "100 MHz"
-
-endchoice
-
-choice
-	prompt "CPU type"
-	default PPC_T1040
-	help
-	Select the exact type of CPU which is used on the version of the simc-t10xx module
-	
-config PPC_T1020
-	bool
-	prompt "T1020"
-	
-config PPC_T1022
-	bool
-	prompt "T1022"
+endif
 
-config PPC_T1040
-	bool
-	prompt "T1040"
+if TARGET_QT1040_1GB
 
-config PPC_T1042
-	bool
-	prompt "T1042"
-	
-endchoice
+config SYS_CONFIG_NAME
+	string
+	default "QT1040-1GB"
 
 endif
diff --git a/board/scalys/simc-t10xx/Makefile b/board/scalys/simc-t10xx/Makefile
index 83ac551..59f29ec 100644
--- a/board/scalys/simc-t10xx/Makefile
+++ b/board/scalys/simc-t10xx/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2016 Scalys B.V.
+# Copyright 2017 Scalys B.V.
 # opensource@scalys.com
 # 
 # SPDX-License-Identifier:	GPL-2.0+
@@ -13,7 +13,11 @@ obj-y	+= simc-t10xx.o
 obj-y	+= eth.o
 obj-$(CONFIG_PCI)	+= pci.o
 endif
+ifdef CONFIG_TARGET_QT1040_1GB
+obj-y	+= ddr_QT1040-1GB.o
+else
 obj-y	+= ddr.o
+endif
 obj-y	+= law.o
 obj-y	+= tlb.o
-obj-y	+= dragonfruit.o
\ No newline at end of file
+obj-y	+= dragonfruit.o
diff --git a/board/scalys/simc-t10xx/ddr.c b/board/scalys/simc-t10xx/ddr.c
index f6d04ac..7fed0d2 100644
--- a/board/scalys/simc-t10xx/ddr.c
+++ b/board/scalys/simc-t10xx/ddr.c
@@ -1,24 +1,19 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
-#include <asm/mmu.h>
-//#include <asm/gpio.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-#include <common.h>
 #include <i2c.h>
 #include <hwconfig.h>
 #include <asm/mmu.h>
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
-//#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /* MT41K512M8RH-125 */
 dimm_params_t ddr_raw_timing = {
@@ -45,7 +40,7 @@ dimm_params_t ddr_raw_timing = {
 	.tfaw_ps = 30000,
 	.twr_ps = 15000,
 	.trfc_ps = 260000,
-	.trrd_ps = 6000,
+	.trrd_ps = 5000, //1Kb page size!
 	.twtr_ps = 7500,
 	.trtp_ps = 7500,
 	.refresh_rate_ps = 70200000,
@@ -90,6 +85,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 
 	/* Clock is launched 1/2 applied cycle after address/command */
 	popts->clk_adjust = 8; 
+	
+	/* Optimized cpo */
+	popts->cpo_sample = 0x46;
 }
 
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
@@ -108,7 +106,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 	return 0;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -142,5 +140,7 @@ phys_size_t initdram(int board_type)
 	dram_size =  fsl_ddr_sdram_size();
 #endif
 	
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/scalys/simc-t10xx/ddr_QT1040-1GB.c b/board/scalys/simc-t10xx/ddr_QT1040-1GB.c
new file mode 100644
index 0000000..e4fdcf6
--- /dev/null
+++ b/board/scalys/simc-t10xx/ddr_QT1040-1GB.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+ 
+DECLARE_GLOBAL_DATA_PTR;
+ 
+/* Values for QT1040 */ 
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 1073741824u,
+	.capacity = 1073741824u,
+	.device_width = 16,
+	.primary_sdram_width = 64,
+	.ec_sdram_width = 8,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 14,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 2,
+	.burst_lengths_bitmask = 0x0c,
+	.tckmin_x_ps = 1250,
+	.caslat_x = (0x7fe << 4),
+	.taa_ps = 13750,
+	.twr_ps = 15000,
+	.trcd_ps = 13750,
+	.trrd_ps = 7500,
+	.trp_ps = 13750,
+	.tras_ps = 37500,
+	.trc_ps = 50600,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
+	.refresh_rate_ps = 3900000,
+	.tfaw_ps = 50000,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	int i;
+	
+	if (ctrl_num != 0) {
+		printf("Only 1 memory controller supported, but %i requested\n",
+		       ctrl_num);
+		return; 
+	}
+	
+	if (pdimm == NULL ) {
+		printf("Error, no valid dimm pararmeter supplied\n");
+		return;
+	}
+
+	if (!pdimm->n_ranks) {
+		printf("No ranks in dimm parameters. Configuration error?\n");
+		return;
+	}
+	
+	/* DDR speed is fixed in the RCW */
+
+	/* set odt_rd_cfg and odt_wr_cfg. */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		popts->cs_local_opts[i].odt_wr_cfg = 4;
+	}
+	
+	popts->half_strength_driver_enable = 0; /* */
+
+	popts->wrlvl_en = 1;
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+	popts->wrlvl_start  = 5;
+	popts->wrlvl_ctl_2 = 0x05050506;
+	popts->wrlvl_ctl_3 = 0x06060605; /* 1333MT/s */
+	
+ 	popts->ddr_cdr1 = 0x800c0000;
+ 	popts->ddr_cdr2 = 0x00000001;
+	
+	/*
+	 * rtt and rtt_wr override
+	 */
+	popts->rtt_override = 0; /* */
+	
+	/* Enable ZQ calibration */
+	popts->zq_en = 1; /* */
+
+	/* Clock is launched 1/2 applied cycle after address/command */
+	popts->clk_adjust = 4; 
+	
+	/* Optimized cpo */
+	popts->cpo_sample = 0x33;
+}
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+			    unsigned int controller_number,
+			    unsigned int dimm_number)
+{
+	const char dimm_model[] = "Soldered-down discrete DDR3";
+	
+	if (((controller_number == 0) && (dimm_number == 0)) ||
+		((controller_number == 1) && (dimm_number == 0))) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+	
+	return 0;
+}
+
+int test123(void){
+	{
+		volatile int waitforme = 0;
+		
+		while (waitforme) {
+			asm volatile ("nop");
+		}
+	}
+	return 0;
+}
+
+
+int dram_init(void)
+{
+	phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+	uint32_t regval;
+	
+	/* Remove reset of DDR using GPIO pin. We do this manually since
+	 * we have not yet access to the DM gpio at this time */
+	/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */
+	
+#define CONFIG_SYS_MPC85XX_GPIO2_ADDR	(CONFIG_SYS_IMMR + 0x131000)
+#define DDR_RST_N			(12)
+/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */
+/* #define DDR_RST_N     MPC85XX_GPIO_NR(2, 12) */
+
+	/* Set output */
+	regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8);
+	regval |= (0x80000000 >> 12);
+	out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8, regval);
+	
+	/* Set direction to acivate gpio pin */
+	regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR);
+	regval |= (0x80000000 >> 12);
+	out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR, regval);
+	
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+#else
+	/* DDR has been initialised by SPL loader */
+	dram_size =  fsl_ddr_sdram_size();
+#endif
+	
+	test123();
+	
+	gd->ram_size = dram_size;
+	
+	return 0;
+}
+
diff --git a/board/scalys/simc-t10xx/dragonfruit.c b/board/scalys/simc-t10xx/dragonfruit.c
index 0ae849c..12accc0 100644
--- a/board/scalys/simc-t10xx/dragonfruit.c
+++ b/board/scalys/simc-t10xx/dragonfruit.c
@@ -1,53 +1,67 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+
 #include <common.h>
 #include <asm-generic/gpio.h>
-
 #include "dragonfruit.h"
 
-
 /*
  * SERDER MUX Configuration pins:
  * IFC_A25 : GPIO2_25 : SERDES_CLK_ MUX_SER0_1_SEL
  * IFC_A26 : GPIO2_26 : SERDES_CLK_ MUX_SER2_3_SEL
  * IFC_A27 : GPIO2_27 : SERDES_CLK_ MUX_SER5_6_SEL
- * 
+ */
+#define MUX_SER0_1_SEL MPC85XX_GPIO_NR(2, 25)
+#define MUX_SER2_3_SEL MPC85XX_GPIO_NR(2, 26)
+#define MUX_SER5_6_SEL MPC85XX_GPIO_NR(2, 27)
+#define SERDES_CLK_OE  MPC85XX_GPIO_NR(2, 29)
+
+/* 
  * MUX_SER0_1_SEL
  * 	0: SERDES A => Slot1, lane 0
  *	   SERDES B => Slot1, lane 1
  *	1: SERDES A => CS4315 retimer => SFP+ 0
  * 	   SERDES B => CS4315 retimer => SFP+ 1
-  * 
+ */
+#define SER_0_1_SLOT1	0
+#define SER_0_1_SFP01	1
+
+/* 
  * MUX_SER2_3_SEL
  * 	0: SERDES C => Slot1, lane 2
  * 	   SERDES D => Slot1, lane 3
  * 	1: SERDES C => QSFP+ 2
  * 	   SERDES D => QSFP+ 3
- * 
+ */
+#define SER_2_3_SLOT1	0
+#define SER_2_3_SFP23	2
+
+/* 
  * SERDES E => Slot 4, lane 0 
- *
- * MUX_SER5_6_SEL
+ */
+
+/* MUX_SER5_6_SEL
  *	0: SERDES F => SLOT4, lane 1
  *	   SERDES G => SLOT4, lane 2
  * 	1: SERDES F => SLOT2
  *	   SERDES G => SLOT3
- * 
- * SERDES H => Slot 4, lane 3
  */
+#define SER_5_6_SLOT4	0
+#define SER_5_6_SLOT23	4
 
-#define MUX_SER0_1_SEL MPC85XX_GPIO_NR(2, 25)
-#define MUX_SER2_3_SEL MPC85XX_GPIO_NR(2, 26)
-#define MUX_SER5_6_SEL MPC85XX_GPIO_NR(2, 27)
-#define SERDES_CLK_OE  MPC85XX_GPIO_NR(2, 29)
+/* 
+ * SERDES H => Slot 4, lane 3
+ */
 
 int scalys_carrier_setup_muxing(int serdes_config)
 {
 	int ret = 0;
+	int mux_config = 0;
 
 	ret = gpio_request(MUX_SER0_1_SEL, "mux_ser0_1_sel");
 	if (ret != 0) {
@@ -56,34 +70,121 @@ int scalys_carrier_setup_muxing(int serdes_config)
 	gpio_request(MUX_SER2_3_SEL, "mux_ser2_3_sel");
 	gpio_request(MUX_SER5_6_SEL, "mux_ser5_6_sel");
 	gpio_request(SERDES_CLK_OE, "serdes_clk_oe");
-
+	
+	
+	/* 
+	 * SERDES options for each target as supported by the dragonfruit 
+	 * carrier board. Refer to the QorIQ reference manual for the SERDES options table 
+	 * and all relevant information.
+	 * 
+	 * Note: The SERDES lanes A&B, C&D, and F&G can only be switched 
+	 * as pairs using the multiplexers. Which means some SERDES options are only partly usable.
+	 * 
+	 * Note/TODO: SERDES PLL2 must be powered down using SRDS_PLL_PD_S1 when
+	 * SRDS_PRTCL_S1 is any of the following values: 0x00, 0x40, 0x60, 0x67, 
+	 * 0x85, 0x87, 0x8D, 0x45.
+	 * 
+	 */
 	switch(serdes_config){
-	case 0x06:
-		/* A-D: PCIe1 (5/2.5G); E: PCIe2 (5/2.5G);
-		 * F: PCIe3 (5/2.5G); G: PCIe4 (5/2.5); H: SATA.1 (3/1.5G) */
-		gpio_direction_output(MUX_SER0_1_SEL, 0);
-		gpio_direction_output(MUX_SER2_3_SEL, 0);
-		gpio_direction_output(MUX_SER5_6_SEL, 1);
-
+#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1020)
+/* With Ethernet Switch (T1040/T1020 only) */
+	//case 0x69:
+	//case 0x67: /* See note 2 */
+	case 0x60: /* See note 2 */
+		mux_config = SER_5_6_SLOT4 | SER_2_3_SFP23 | SER_0_1_SFP01;
+		break;
+	//case 0x8D: /* See note 2 */
+	//case 0x8E:
+	//case 0x66:
+	case 0x89:
+		/* A: unused; B: sg.s3; C: sg.s1; D: sg.s2;
+		 * E: PCIe2 (5/2.5G); F: PCIe3 (5/2.5G); G: unused; H: SATA1(3/1.5G) */
+		mux_config = SER_5_6_SLOT23 | SER_2_3_SFP23 | SER_0_1_SFP01;
 		break;
 	case 0x81:
+		/* A: Unused; B: sg.m3/sg.s3; C: sg.m1/sg.s1; D: sg.m2/sg.s2;
+		 * E: PCIe2 (5/2.5G); F: unused; G: unused; H: SATA1(3/1.5G) */
+	//case 0x88: /* Option has been verified to work, but is not officially supported */
+		/* A: Unused; B: sg.m3; C: sg.m1; D: sg.m2;
+		 * E: PCIe2 (5/2.5G); F: unused; G: SATA.2(3/1.5G); H: SATA1(3/1.5G) */
+		mux_config = SER_5_6_SLOT4 | SER_2_3_SFP23 | SER_0_1_SFP01;
+		break;
+#elif defined(CONFIG_PPC_T1042) || defined(CONFIG_PPC_T1022)
 	case 0x86:
+		/* A: Unused; B: sg.m3; C: sg.m1; D: sg.m2;
+		 * E: PCIe2 (5/2.5G); F: PCIe3 (5/2.5G); G: PCIe4 (5/2.5G); H: SATA1(3/1.5G) */
+		mux_config = SER_5_6_SLOT23 | SER_2_3_SFP23 | SER_0_1_SFP01;
+		break;
+	case 0x81:
+		/* A: Unused; B: sg.m3/sg.s3; C: sg.m1/sg.s1; D: sg.m2/sg.s2;
+		 * E: PCIe2 (5/2.5G); F: unused; G: unused; H: SATA1(3/1.5G) */
 	case 0x88:
-	case 0x89:
-		/* A: PCIe1 (5/2.5G); B: sg.m3; C: sg.m1; D: sg.m2;
-		 * E: PCIe2 (5/2.5G); F:PCIe3 (5/2.5G); G: SATA2(3/1.5G);
-		 * H: SATA1(3/1.5G) */
+		/* A: Unused; B: sg.m3; C: sg.m1; D: sg.m2;
+		 * E: PCIe2 (5/2.5G); F: unused; G: SATA.2(3/1.5G); H: SATA1(3/1.5G) */
+		mux_config = SER_5_6_SLOT4 | SER_2_3_SFP23 | SER_0_1_SFP01;
+		break;
+	case 0x06:
+		/* A-D: PCIe1 (5/2.5G); 
+		 * E: PCIe2 (5/2.5G); F: PCIe3 (5/2.5G); G: PCIe4 (5/2.5G); H: SATA.1 (3/1.5G) */
+		mux_config = SER_5_6_SLOT23 | SER_2_3_SLOT1 | SER_0_1_SLOT1;
+		break;
+	//case 0x08:
+	//case 0x87: /* See note 2 */
+	//case 0xA7:
+	//case 0xAA:
+	//case 0xA2:
+	//case 0x45:
+	//case 0x40: /* See note 2 */
+	//case 0x8E:
+	//case 0x85: /* See note 2 */
+	//case 0xA5:
+	//case 0x00: /* See note 2 */
+#else
+#error "Invalid or unspecified target cpu for dragonfruit carrier board!"
+#endif
+	default:
+		printf("Unsupported SERDES configuration (%02x) detected for dragonfruit carrier board (Warning: Using default multiplexer settings)!\n", serdes_config);
+	}
+	
+	printf("-----------------------------------------------------\n");
+	printf("Serdes lane configuration:\n");
+	if ((mux_config & 1) != 0) {
 		gpio_direction_output(MUX_SER0_1_SEL, 1);
+		printf("A: SFP slot 0 (T2081 only)\n");
+		printf("B: SFP slot 1 (T2081 only)\n");
+	} else {
+		gpio_direction_output(MUX_SER0_1_SEL, 0);
+		printf("A: PCIe slot 1 on lane 0\n");
+		printf("B: PCIe slot 1 on lane 1\n");
+	}
+	
+	if ((mux_config & 2) != 0) {
 		gpio_direction_output(MUX_SER2_3_SEL, 1);
+		printf("C: SFP slot 2\n");
+		printf("D: SFP slot 3\n");
+	} else {
+		gpio_direction_output(MUX_SER2_3_SEL, 0);
+		printf("C: PCIe slot 1 on lane 2\n");
+		printf("D: PCIe slot 1 on lane 3\n");
+	}
+	
+	printf("E: PCIe slot 4 on lane 0\n");
+	
+	if ((mux_config & 4) != 0) {
 		gpio_direction_output(MUX_SER5_6_SEL, 1);
-
-		break;
-	default:
-		printf("Unsupported SERDES configuration (%02x)\n", serdes_config);
+		printf("F: PCIe slot 2 on lane 0\n");
+		printf("G: PCIe slot 3 on lane 0\n");
+	} else {
+		gpio_direction_output(MUX_SER5_6_SEL, 0);
+		printf("F: PCIe slot 4 on lane 1\n");
+		printf("G: PCIe slot 4 on lane 2\n");
 	}
+	
+	printf("H: PCIe slot 4 on lane 3\n");
+	printf("-----------------------------------------------------\n");
 
 	/* Enable serdes clock */
 	gpio_direction_output(SERDES_CLK_OE, 1);
-
+	
 	return ret;
-}
\ No newline at end of file
+}
diff --git a/board/scalys/simc-t10xx/dragonfruit.h b/board/scalys/simc-t10xx/dragonfruit.h
index 900b2e4..12928b4 100644
--- a/board/scalys/simc-t10xx/dragonfruit.h
+++ b/board/scalys/simc-t10xx/dragonfruit.h
@@ -1,6 +1,14 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
 #ifndef _DRAGON_FRUIT_H
 #define _DRAGON_FRUIT_H
 
 int scalys_carrier_setup_muxing(int serdes_config);
 
-#endif /* _DRAGON_FRUIT_H */
\ No newline at end of file
+#endif /* _DRAGON_FRUIT_H */
diff --git a/board/scalys/simc-t10xx/eth.c b/board/scalys/simc-t10xx/eth.c
index 2f5c401..2b548f1 100644
--- a/board/scalys/simc-t10xx/eth.c
+++ b/board/scalys/simc-t10xx/eth.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -7,17 +7,6 @@
 
 #include <common.h>
 #include <netdev.h>
-#include <asm/immap_85xx.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <i2c.h>
-
-
-
-
-#include <common.h>
-#include <netdev.h>
 #include <asm/fsl_serdes.h>
 #include <asm/immap_85xx.h>
 #include <fm_eth.h>
@@ -25,11 +14,7 @@
 #include <malloc.h>
 #include <fsl_dtsec.h>
 #include <vsc9953.h>
-
-//#include "../common/fman.h"
-//#include "../common/qixis.h"
-
-
+#include <i2c.h>
 
 
 #include "../../freescale/common/fman.h"
@@ -53,16 +38,24 @@ int board_eth_init(bd_t *bis)
 	int phy_addr = 0;
 	
 #ifdef CONFIG_VSC9953
-	int lane;
-	phy_interface_t phy_int;
-	struct mii_dev *bus;
+	/*phy_interface_t phy_int;*/
+	/*struct mii_dev *bus;*/
 	struct ccsr_scfg *scfg;
 #endif
 	
 	uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
 	uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
+	uint32_t *gpio4_gpdir = (uint32_t *) 0xffe133000;
+	uint32_t *gpio4_gpdat = (uint32_t *) 0xffe133008;
 	uint32_t regval;
 	
+	/* Try to read a byte from te carrier eeprom te determine if were on the correct carrier */
+	ret = i2c_read(0x54, 0, 2, &i2c_data, 1 );
+	if (ret != 0) {
+		printf("No dragonfruit carrier detected\n");
+		return 0;
+	}
+	
 	printf("Initializing Fman\n");
 
 	memac_mdio_info.regs =
@@ -72,11 +65,24 @@ int board_eth_init(bd_t *bis)
 	/* Register the real 1G MDIO bus */
 	fm_memac_mdio_init(bis, &memac_mdio_info);
 
-	/* Remove reset from Ethernet PHY's 
-	 * IFC_PERR_B : GPIO2_15 : eth1_reset
-	 * IFC_CS_N2  : GPIO2_11 : eth2_reset */
-//	gpio_set_value(2, 0);
-
+   /* Marvell 88E1111 Setup
+	* 
+	* Remove reset from Ethernet PHY's 
+	* 
+	* Carrier board v1.x:
+	* IFC_PERR_B : GPIO2_15 : eth1_reset
+	* IFC_CS_N2  : GPIO2_11 : eth2_reset 
+	*
+	* Carrier board v2.x:
+	* IFC_PERR_B : GPIO2_15 : eth1_reset
+	* IFC_CS_N2  : GPIO4_09 : eth2_reset
+	* 
+	* Note: make sure gpio pins are configured as gpio in RCW! 
+	*/
+
+#if 0 
+	/* TODO: use EEPROM data to chose carrier board version */
+	/* Carrier board v1.x */
 	/* Clear outputs to activate reset */
 	regval = in_be32(gpio2_gpdat);
 	regval &= ~((0x80000000 >> 11 ) | (0x80000000 >> 15));
@@ -94,11 +100,44 @@ int board_eth_init(bd_t *bis)
 	regval = in_be32(gpio2_gpdat);
 	regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15));
 	out_be32(gpio2_gpdat, regval);
-
+#else
+	/* Carrier board v2.x */
+	/* Clear outputs to activate reset */
+	regval = in_be32(gpio2_gpdat);
+	regval &= ~(0x80000000 >> 15);
+	out_be32(gpio2_gpdat, regval);
+	regval = in_be32(gpio4_gpdat);
+	regval &= ~(0x80000000 >> 9);
+	out_be32(gpio4_gpdat, regval);
+	
+	/* Set outputs to output mode */
+	regval = in_be32(gpio2_gpdir);
+	regval |= (0x80000000 >> 15);
+	out_be32(gpio2_gpdir, regval);
+	regval = in_be32(gpio4_gpdir);
+	regval |= (0x80000000 >> 9);
+	out_be32(gpio4_gpdir, regval);
+	
+	/* Wait for 10 ms to to meet reset timing */
+	mdelay(10);
+	
+	/* Set outputs to de-activate reset */
+	regval = in_be32(gpio2_gpdat);
+	regval |= (0x80000000 >> 15);
+	out_be32(gpio2_gpdat, regval);
+	regval = in_be32(gpio4_gpdat);
+	regval |= (0x80000000 >> 9);
+	out_be32(gpio4_gpdat, regval);
+#endif
+	
+	/* Write 0x4111 to reg 0x18 on both PHYs to change LEDs usage */
+	miiphy_write("FSL_MDIO0",0,0x18,0x4111);
+	miiphy_write("FSL_MDIO0",1,0x18,0x4111);
 
 	/* Remove SFP TX_disable */
 	i2c_set_bus_num(0);
-	i2c_data = 0x3b;
+	ret = i2c_read(0x22, 0x0E, 1, &i2c_data, 1);
+	i2c_data &= ~0x04;
 	ret = i2c_write(0x22, 0x0E, 1, &i2c_data, 1);
 
 	mdelay(100);
@@ -163,9 +202,9 @@ int board_eth_init(bd_t *bis)
 	
 #ifdef CONFIG_VSC9953
 	for (i = 0; i < VSC9953_MAX_PORTS; i++) {
-		int lane = -1;
-		int phy_addr = 0;
-		int phy_int = PHY_INTERFACE_MODE_NONE;
+		/*int lane = -1;*/
+		/*int phy_addr = 0;*/
+		/*int phy_int = PHY_INTERFACE_MODE_NONE;*/
 		switch (i) {
 		case 0:
 		case 1:
@@ -193,7 +232,7 @@ int board_eth_init(bd_t *bis)
 			vsc9953_port_enable(i);
 			break;
 		}
-		bus = lane;
+		/*bus = lane;*/
 
 	}
 #endif
diff --git a/board/scalys/simc-t10xx/law.c b/board/scalys/simc-t10xx/law.c
index c3b5e85..df823d1 100644
--- a/board/scalys/simc-t10xx/law.c
+++ b/board/scalys/simc-t10xx/law.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  * 
  * Copyright 2013 Freescale Semiconductor, Inc.
@@ -29,4 +29,4 @@ struct law_entry law_table[] = {
 #endif
 };
 
-int num_law_entries = ARRAY_SIZE(law_table);
\ No newline at end of file
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/scalys/simc-t10xx/pci.c b/board/scalys/simc-t10xx/pci.c
index ab9edbb..9a02f90 100644
--- a/board/scalys/simc-t10xx/pci.c
+++ b/board/scalys/simc-t10xx/pci.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  * 
  * Copyright 2013 Freescale Semiconductor, Inc.
@@ -22,11 +22,16 @@ void pci_init_board(void)
 	uint32_t *gpio1_gpdat = (uint32_t *) 0xffe130008;
 	uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
 	uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
-	uint32_t regval;
-
-	debug("%s\n", __FUNCTION__);
+	uint32_t regval;	
+	
+	/*debug("%s\n", __FUNCTION__);*/
 	
-	//TODO, when present pins are available on the board, use them to enable only active slots
+	/*TODO, when present pins are available on the board, use them to enable only active slots*/
+	
+#if 0
+	/* Dragonfruit Carrier board 1.x */
+
+
 	/* 
 	 * IRQ[0-3] : PCIe present detect signals
 	 * IRQ[0] : SLOT1_PRSNT2_N : XXX
@@ -51,7 +56,47 @@ void pci_init_board(void)
 	regval |= ( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) );
 	out_be32(gpio1_gpdir, regval);
 	
+#else
+	/* Dragonfruit Carrier board 2.x */
+	/* 
+	 * PCIe present detect signals:
+	 * IRQ[3] : GPIO1_23 : SLOT1_PRSNT2_N
+	 * IRQ[4] : GPIO1_24 : SLOT2_PRSNT2_N
+	 * IRQ[5] : GPIO1_25 : SLOT3_PRSNT2_N
+	 * IRQ[10] : GPIO1_30 : SLOT4_PRSNT2_N
+	 * 
+	 * Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7 
+	 * IFC_CS_N7 : GPIO1_IO12 : PCIe SLOT4_REFCLK_OE_N (used for all 4 slots)
+	 * IFC_PAR1 : GPIO2_14 : PEX_REFCLK_SEL
+	 */
+	
+	/* Set output to 0 to enable reference clocks */
+	regval = in_be32(gpio1_gpdat);
+	regval &= ~( 0x80000000 >> 12 );
+	out_be32(gpio1_gpdat, regval);
 	
+	/* Set Enable outputs */
+	regval = in_be32(gpio1_gpdir);
+	regval |= ( 0x80000000 >> 12 );
+	out_be32(gpio1_gpdir, regval);
+	
+	/* Set PEX_REFCLK_SEL to 0 to select CLK0  */
+
+	/* Set IFC_PAR1 to output mode */
+	regval = in_be32(gpio2_gpdir);
+	regval |= ( 0x80000000 >> 14 );
+	out_be32(gpio2_gpdir, regval);
+
+	/* Set output to 0 to select clock source 0 */
+	regval = in_be32(gpio2_gpdat);
+	regval &= ~( 0x80000000 >> 14 );
+	out_be32(gpio2_gpdat, regval);
+
+#endif
+	
+	/*
+	 * IFC_PAR0 : GPIO2_13 : PEX_PERST_N
+	 */
 
 	/* Remove reset from PCIe devices */
 
diff --git a/board/scalys/simc-t10xx/qt1040-1gb_nand_rcw.cfg b/board/scalys/simc-t10xx/qt1040-1gb_nand_rcw.cfg
new file mode 100644
index 0000000..87ec66f
--- /dev/null
+++ b/board/scalys/simc-t10xx/qt1040-1gb_nand_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+
+0a0a000c 0c000000 00000000 00000000 
+81000002 40000002 e8105000 21000000 
+00000000 cafebabe 00000000 00030ffc 
+00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/qt1040-1gb_nor_rcw.cfg b/board/scalys/simc-t10xx/qt1040-1gb_nor_rcw.cfg
new file mode 100644
index 0000000..9fd7e93
--- /dev/null
+++ b/board/scalys/simc-t10xx/qt1040-1gb_nor_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+0a0a000c 0c000000 00000000 00000000 
+81000002 40000002 e8023000 21000000 
+00000000 cafebabe 00000000 00030ffc 
+00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/qt1040-1gb_sdhc_rcw.cfg b/board/scalys/simc-t10xx/qt1040-1gb_sdhc_rcw.cfg
new file mode 100644
index 0000000..43b7304
--- /dev/null
+++ b/board/scalys/simc-t10xx/qt1040-1gb_sdhc_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+0a0a000c 0c000000 00000000 00000000
+81000002 40000002 68105000 21000000
+00000000 cafebabe 00000000 00030ffc
+00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/qt1040-1gb_spi_rcw.cfg b/board/scalys/simc-t10xx/qt1040-1gb_spi_rcw.cfg
new file mode 100644
index 0000000..6cede86
--- /dev/null
+++ b/board/scalys/simc-t10xx/qt1040-1gb_spi_rcw.cfg
@@ -0,0 +1,9 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+0a0a000c 0c000000 00000000 00000000 
+81000002 40000002 58105000 21000000 
+00000000 cafebabe 00000000 00030ffc 
+00000314 00005005 00000000 00000000
+
+#58505000 / 58105000
diff --git a/board/scalys/simc-t10xx/simc-t1022_rcw.cfg b/board/scalys/simc-t10xx/simc-t1022_rcw.cfg
deleted file mode 100644
index 1ddbe0c..0000000
--- a/board/scalys/simc-t10xx/simc-t1022_rcw.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-#PBL preamble and RCW header
-AA55AA55 010E0100
-#
-#120C0015 15000000 00000000 00000000
-#06000000 00C00002 E8104000 21000000
-#00000000 CAFEBABE 00000000 00030ffc
-#00000314 0014500C 00000000 00000000
-#
-#120C0015 15000000 00000000 00000000
-#06000000 00000002 E8105000 21000000
-#00000000 CAFEBABE 00000000 00230FFC
-#00000714 0014500C 00000000 00000000
-
-120C0015 15000000 00000000 00000000
-86000000 00000002 E8104000 21000000
-00000000 CAFEBABE 00000000 00030FFC
-00000314 0014500C 00000000 00000000
diff --git a/board/scalys/simc-t10xx/simc-t1040_nand_secure_rcw.cfg b/board/scalys/simc-t10xx/simc-t1040_nand_secure_rcw.cfg
deleted file mode 100644
index 6a69289..0000000
--- a/board/scalys/simc-t10xx/simc-t1040_nand_secure_rcw.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#PBL preamble and RCW header
-AA55AA55 010E0100
-#
-0A0C000C 0C000000 00000000 00000000
-# HOLDOFF         E8705000
-# core 0 enabled  E8305000
-# PBL disabled    F8505000
-# PBL enabled     E8705000
-
-#Holdoff enabled, PBL enabled No secure boot E8505000
-#Holdoff enabled, PBL enabled with secure boot E8705000
-81000002 00400002 E8305000 21000000
-00000000 CAFEBABE 00000000 00030FFC
-00000314 0014500C 00000000 00000000
\ No newline at end of file
diff --git a/board/scalys/simc-t10xx/simc-t1040_rcw.cfg b/board/scalys/simc-t10xx/simc-t1040_rcw.cfg
deleted file mode 100644
index 323ea71..0000000
--- a/board/scalys/simc-t10xx/simc-t1040_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-AA55AA55 010E0100
-#
-0A0C000C 0C000000 00000000 00000000
-81000002 00400002 E8105000 21000000
-00000000 CAFEBABE 00000000 00030FFC
-00000314 0014500C 00000000 00000000
diff --git a/board/scalys/simc-t10xx/simc-t10x0_nand_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_nand_rcw.cfg
new file mode 100644
index 0000000..ccb3509
--- /dev/null
+++ b/board/scalys/simc-t10xx/simc-t10x0_nand_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+
+0c0c000c 0c000000 00000000 00000000 
+81000002 40000002 e8105000 21000000 
+00000000 cafebabe 00000000 00030ffc 
+00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/simc-t10x0_nand_secure_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_nand_secure_rcw.cfg
new file mode 100644
index 0000000..6f0ec4d
--- /dev/null
+++ b/board/scalys/simc-t10xx/simc-t10x0_nand_secure_rcw.cfg
@@ -0,0 +1,14 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+0c0C000C 0C000000 00000000 00000000
+# HOLDOFF         E8705000
+# core 0 enabled  E8305000
+# PBL disabled    F8505000
+# PBL enabled     E8705000
+
+#Holdoff enabled, PBL enabled No secure boot E8505000
+#Holdoff enabled, PBL enabled with secure boot E8705000
+81000002 40000002 e8305000 21000000 
+00000000 cafebabe 00000000 00030ffc 
+00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/simc-t10x0_nor_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_nor_rcw.cfg
new file mode 100644
index 0000000..a63c1f2
--- /dev/null
+++ b/board/scalys/simc-t10xx/simc-t10x0_nor_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+0c0c000c 0c000000 00000000 00000000 
+81000002 40000002 e8023000 21000000 
+00000000 cafebabe 00000000 00030ffc 
+00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/simc-t10x0_sdhc_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_sdhc_rcw.cfg
new file mode 100644
index 0000000..61236ed
--- /dev/null
+++ b/board/scalys/simc-t10xx/simc-t10x0_sdhc_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+0c0c000c 0c000000 00000000 00000000
+81000002 40000002 68105000 21000000
+00000000 cafebabe 00000000 00030ffc
+00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/simc-t10x0_spi_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_spi_rcw.cfg
new file mode 100644
index 0000000..dba4882
--- /dev/null
+++ b/board/scalys/simc-t10xx/simc-t10x0_spi_rcw.cfg
@@ -0,0 +1,9 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+0c0c000c 0c000000 00000000 00000000 
+81000002 40000002 58105000 21000000 
+00000000 cafebabe 00000000 00030ffc 
+00000314 00005005 00000000 00000000
+
+#58505000 / 58105000
diff --git a/board/scalys/simc-t10xx/simc-t10xx.c b/board/scalys/simc-t10xx/simc-t10xx.c
index 46c5677..2f9b8d3 100644
--- a/board/scalys/simc-t10xx/simc-t10xx.c
+++ b/board/scalys/simc-t10xx/simc-t10xx.c
@@ -1,10 +1,11 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+
 #include <common.h>
 #include <command.h>
 #include <netdev.h>
@@ -31,7 +32,11 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int checkboard(void)
 {
+#ifdef CONFIG_TARGET_QT1040_1GB
+	printf("Board: QT1040-1GB\n" );
+#else
 	printf("Board: simc-t10xx\n" );
+#endif
 	return 0;
 }
 
@@ -110,8 +115,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_liodn(blob);
 
 #ifdef CONFIG_HAS_FSL_DR_USB
-	debug( "fdt_fixup_dr_usb\n" );
-	fdt_fixup_dr_usb(blob, bd);
+	debug( "fsl_fdt_fixup_dr_usb\n" );
+	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
@@ -141,3 +146,8 @@ void board_detail(void)
 	do_bcdinfo();
 }
 #endif
+
+void board_reset(void)
+{
+	printf("U-boot reset command not implemented.\n");
+}
diff --git a/board/scalys/simc-t10xx/simc-t10xx_nand_pbi.cfg b/board/scalys/simc-t10xx/simc-t10xx_nand_pbi.cfg
new file mode 100644
index 0000000..ad31c5b
--- /dev/null
+++ b/board/scalys/simc-t10xx/simc-t10xx_nand_pbi.cfg
@@ -0,0 +1,43 @@
+#PBI commands
+#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
+09250100 00000400
+09250108 00002000
+#Software Workaround for errata A-008007 to reset PVR register
+09000010 0000000b
+09000014 c0000000
+09000018 81d00017
+89020400 a1000000
+091380c0 000f0000
+89020400 00000000
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1 (LAW 13)
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure IFC controller
+# (IFC_CSPR1)
+09124010 ff8000c3
+#  IFC_CSOR_NAND
+09124130 85084101
+#  IFC_FTIM0_CS0_NAND to IFC_FTIM0_CS0_NAND 
+091241c0 181c080c
+091241c4 3850141a
+091241c8 03008028
+091241cc 28000000
+# Set IFC_CCR clkdiv to 2 (=/3) to get: 
+# (platform clock/2/3=83.3MHz)
+0912444c 02008000
+#Flush PBL data (Wait 0xFFFFF cycles )
+091380c0 000fffff
\ No newline at end of file
diff --git a/board/scalys/simc-t10xx/simc-t10xx_nor_pbi.cfg b/board/scalys/simc-t10xx/simc-t10xx_nor_pbi.cfg
new file mode 100644
index 0000000..1e7a20e
--- /dev/null
+++ b/board/scalys/simc-t10xx/simc-t10xx_nor_pbi.cfg
@@ -0,0 +1,44 @@
+#PBI commands
+#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
+09250100 00000400
+09250108 00002000
+#Software Workaround for errata A-008007 to reset PVR register
+09000010 0000000b
+09000014 c0000000
+09000018 81d00017
+89020400 a1000000
+091380c0 000f0000
+89020400 00000000
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1 (LAW 13)
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+
+#Configure IFC controller
+# (IFC_CSPR1)
+#09124010 ff8000c3
+#  IFC_CSOR_NAND
+#09124130 0108a100
+#  IFC_FTIM0_CS0_NAND to IFC_FTIM0_CS0_NAND 
+#091241c0 181c080c
+#091241c4 3850141a
+#091241c8 03008028
+#091241cc 28000000
+
+# Set IFC_CCR clkdiv to 6 (IFC clock to platform clock/6=83.3MHz)
+0912444c 05008000
+#Flush PBL data (Wait 0xFFFFF cycles )
+091380c0 000fffff
\ No newline at end of file
diff --git a/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg b/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg
deleted file mode 100644
index c5fd95d..0000000
--- a/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg
+++ /dev/null
@@ -1,42 +0,0 @@
-#PBI commands
-#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
-09250100 00000400
-09250108 00002000
-#Software Workaround for errata A-008007 to reset PVR register
-09000010 0000000b
-09000014 c0000000
-09000018 81d00017
-89020400 a1000000
-091380c0 000f0000
-89020400 00000000
-#Initialize CPC1
-09010000 00200400
-09138000 00000000
-091380c0 00000100
-#Configure CPC1 as 256KB SRAM
-09010100 00000000
-09010104 fffc0007
-09010f00 08000000
-09010000 80000000
-#Configure LAW for CPC1 (LAW 13)
-09000cd0 00000000
-09000cd4 fffc0000
-09000cd8 81000011
-#Configure alternate space
-09000010 00000000
-09000014 ff000000
-09000018 81000000
-#Configure IFC controller
-# (IFC_CSPR1)
-09124010 ff8000c3
-#  IFC_CSOR_NAND
-09124130 0108a100
-#  IFC_FTIM0_CS0_NAND to IFC_FTIM0_CS0_NAND 
-091241c0 181c080c
-091241c4 3850141a
-091241c8 03008028
-091241cc 28000000
-# Set IFC_CCR clkdiv to 6 (IFC clock to platform clock/6=83.3MHz)
-0912444c 05008000
-#Flush PBL data (Wait 0xFFFFF cycles )
-091380c0 000fffff
\ No newline at end of file
diff --git a/board/scalys/simc-t10xx/simc-t10xx_sdhc_pbi.cfg b/board/scalys/simc-t10xx/simc-t10xx_sdhc_pbi.cfg
new file mode 100644
index 0000000..51945b4
--- /dev/null
+++ b/board/scalys/simc-t10xx/simc-t10xx_sdhc_pbi.cfg
@@ -0,0 +1,36 @@
+#PBI commands
+#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
+09250100 00000400
+09250108 00002000
+#Software Workaround for errata A-008007 to reset PVR register
+09000010 0000000b
+09000014 c0000000
+09000018 81d00017
+89020400 a1000000
+091380c0 000f0000
+89020400 00000000
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 081e000d
+09010000 80000000
+#Configure LAW for CPC1
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+091380c0 000FFFFF
diff --git a/board/scalys/simc-t10xx/simc-t10xx_spi_pbi.cfg b/board/scalys/simc-t10xx/simc-t10xx_spi_pbi.cfg
new file mode 100644
index 0000000..51945b4
--- /dev/null
+++ b/board/scalys/simc-t10xx/simc-t10xx_spi_pbi.cfg
@@ -0,0 +1,36 @@
+#PBI commands
+#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
+09250100 00000400
+09250108 00002000
+#Software Workaround for errata A-008007 to reset PVR register
+09000010 0000000b
+09000014 c0000000
+09000018 81d00017
+89020400 a1000000
+091380c0 000f0000
+89020400 00000000
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 081e000d
+09010000 80000000
+#Configure LAW for CPC1
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+091380c0 000FFFFF
diff --git a/board/scalys/simc-t10xx/spl.c b/board/scalys/simc-t10xx/spl.c
index 3675169..cfb6e04 100644
--- a/board/scalys/simc-t10xx/spl.c
+++ b/board/scalys/simc-t10xx/spl.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  * 
  * Copyright 2013 Freescale Semiconductor, Inc.
@@ -10,10 +10,11 @@
 #include <common.h>
 #include <malloc.h>
 #include <ns16550.h>
+#include <console.h>
 #include <nand.h>
-#include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
+#include <i2c.h>
 #include <spi_flash.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -61,9 +62,40 @@ void board_init_f(ulong bootflag)
 	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
 }
 
+void setup_ifc_nand(enum ifc_chip_sel cs)
+{
+	set_ifc_cspr_ext(cs, CONFIG_SYS_NAND_CSPR_EXT);
+	set_ifc_csor	(cs, CONFIG_SYS_NAND_CSOR);
+	set_ifc_amask	(cs, CONFIG_SYS_NAND_AMASK);
+	set_ifc_cspr	(cs, CONFIG_SYS_NAND_CSPR);
+	set_ifc_ftim	(cs, IFC_FTIM0, CONFIG_SYS_NAND_FTIM0);
+	set_ifc_ftim	(cs, IFC_FTIM1, CONFIG_SYS_NAND_FTIM1);
+	set_ifc_ftim	(cs, IFC_FTIM2, CONFIG_SYS_NAND_FTIM2);
+	set_ifc_ftim	(cs, IFC_FTIM3, CONFIG_SYS_NAND_FTIM3);
+	set_ifc_csor_ext(cs, 0);
+
+}
+
+void setup_ifc_nor(enum ifc_chip_sel cs)
+{
+	set_ifc_cspr_ext(cs, CONFIG_SYS_NOR_CSPR_EXT);
+	set_ifc_csor	(cs, CONFIG_SYS_NOR_CSOR);
+	set_ifc_amask	(cs, CONFIG_SYS_NOR_AMASK);
+	set_ifc_cspr	(cs, CONFIG_SYS_NOR_CSPR);
+	set_ifc_ftim	(cs, IFC_FTIM0, CONFIG_SYS_NOR_FTIM0);
+	set_ifc_ftim	(cs, IFC_FTIM1, CONFIG_SYS_NOR_FTIM1);
+	set_ifc_ftim	(cs, IFC_FTIM2, CONFIG_SYS_NOR_FTIM2);
+	set_ifc_ftim	(cs, IFC_FTIM3, CONFIG_SYS_NOR_FTIM3);
+	set_ifc_csor_ext(cs, 0);
+}
+
 void board_init_r(gd_t *gd, ulong dest_addr)
 {
 	bd_t *bd;
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	uint32_t boot_source;
+	
+	__attribute__((noreturn)) void (*boot)(void) = hang;
 
 	bd = (bd_t *)(gd + sizeof(gd_t));
 	memset(bd, 0, sizeof(bd_t));
@@ -71,11 +103,80 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
 	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
-	probecpu();
+	arch_cpu_init();
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
 
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+
+	dram_init();
+
+	/* Get the boot source from the Power On Status Register (set by QSC) */
+	boot_source = (in_be32(&gur->porsr1) >> 23);
+
+	switch (boot_source) {
+	case 0x23:
+		/* NOR boot */
+		setup_ifc_nor(IFC_CS0);
+		setup_ifc_nand(IFC_CS1);
+
+		memcpy((void*)CONFIG_SYS_NAND_U_BOOT_DST, (void*) CONFIG_SYS_FLASH_BASE + CONFIG_SPL_PAD_TO, CONFIG_SYS_NAND_U_BOOT_SIZE);
+
+		flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+		boot = (void*) CONFIG_SYS_NAND_U_BOOT_START;
+		break;
+
+	case 0x45:
+#if 0
+		/*SPI nor flash */
+		setup_ifc_nand(IFC_CS0);
+		setup_ifc_nor(IFC_CS1);
+		//fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, (uchar *)CONFIG_ENV_ADDR);
+		{
+			struct spi_flash *flash;
+
+			flash = spi_flash_probe(0, 0,
+				CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
+			if (flash == NULL) {
+				puts("\nspi_flash_probe failed");
+				hang();
+			}
+
+			spi_flash_read(flash, CONFIG_SPL_PAD_TO, CONFIG_SYS_NAND_U_BOOT_SIZE, (void*) CONFIG_SYS_NAND_U_BOOT_DST);
+		}
+#endif
+		printf("TODO, load u-boot from SPI....\n");
+		hang();
+		break;
+	case 0x40:
+		/* SD/MMC (eSDHC) boot */
+#if defined(CONFIG_SPL_MMC_BOOT) || defined(CONFIG_SDHC_FLASH_BOOT)
+		setup_ifc_nand(IFC_CS0);
+		setup_ifc_nor(IFC_CS1);
+		
+		mmc_initialize(bd);
+		mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)CONFIG_ENV_ADDR);
+		boot = mmc_boot;
+#endif
+		break;
+	case 0x105:
+		/* NAND boot */
+		setup_ifc_nand(IFC_CS0);
+		setup_ifc_nor(IFC_CS1);
+
+		nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+		    (uchar *)CONFIG_ENV_ADDR);
+		boot = nand_boot;
+		break;
+	default:
+		printf("Unknown boot source (%3x\n", boot_source);
+	break;
+	}
+	boot();
+#if 0
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_initialize(bd);
 #endif
@@ -85,6 +186,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 			    (uchar *)CONFIG_ENV_ADDR);
 #endif
+
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 			   (uchar *)CONFIG_ENV_ADDR);
@@ -109,4 +211,5 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 #elif defined(CONFIG_SPL_NAND_BOOT)
 	nand_boot();
 #endif
+#endif
 }
diff --git a/board/scalys/simc-t10xx/tlb.c b/board/scalys/simc-t10xx/tlb.c
index fa2dccb..e6edf51 100644
--- a/board/scalys/simc-t10xx/tlb.c
+++ b/board/scalys/simc-t10xx/tlb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  * 
  * Copyright 2013 Freescale Semiconductor, Inc.
@@ -40,14 +40,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_256K, 1),
-
 #elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot
 	 * the physical address of the SRAM is at 0xbffc0000,
 	 * and virtual address is 0xfffc0000
 	 */
-
 	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR,
 		      CONFIG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -66,8 +64,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	/* *I*G* - Flash, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_64M, 1),
 
 #ifndef CONFIG_SPL_BUILD
 #ifdef CONFIG_PCI
@@ -116,21 +114,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_64K, 1),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE
-	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 11, BOOKE_PAGESZ_256K, 1),
-#endif
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 12, BOOKE_PAGESZ_1G, 1),
+#if defined(CONFIG_SYS_SDRAM_SIZE)
+#if (CONFIG_SYS_SDRAM_SIZE >= 2048)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 13, BOOKE_PAGESZ_1G, 1)
 #endif
+#endif
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/scalys/simc-t2081/Kconfig b/board/scalys/simc-t2081/Kconfig
new file mode 100644
index 0000000..323ae5b
--- /dev/null
+++ b/board/scalys/simc-t2081/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_SIMC_TXXXX && ARCH_T2081
+
+config SYS_BOARD
+	default "simc-t2081"
+
+config SYS_CONFIG_NAME
+	default "simc-t2081"	
+	
+endif
diff --git a/board/scalys/simc-t2081/Makefile b/board/scalys/simc-t2081/Makefile
new file mode 100644
index 0000000..730b5ad
--- /dev/null
+++ b/board/scalys/simc-t2081/Makefile
@@ -0,0 +1,19 @@
+# Copyright 2016 Scalys B.V.
+# opensource@scalys.com
+# 
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+UBOOTINCLUDE += -I$(srctree)/board/$(VENDOR)/common/
+
+ifdef CONFIG_SPL_BUILD
+obj-y	+= spl.o
+else
+obj-y	+= simc-t2081.o
+obj-y	+= eth.o
+obj-$(CONFIG_PCI)	+= pci.o
+endif
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
+obj-y	+= dragonfruit.o
diff --git a/board/scalys/simc-t2081/ddr.c b/board/scalys/simc-t2081/ddr.c
new file mode 100644
index 0000000..3d8821c
--- /dev/null
+++ b/board/scalys/simc-t2081/ddr.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* MT41K512M8RH-125 */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 2,
+	.rank_density = 0x100000000ULL,
+	.capacity = 0x200000000ULL,
+	.primary_sdram_width = 64,
+	.ec_sdram_width = 8,
+	.registered_dimm = 0,
+	.mirrored_dimm = 1,
+	.n_row_addr = 16,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = EDC_ECC,
+	.burst_lengths_bitmask = 0x0c,
+	.tckmin_x_ps = 1250,
+	.tckmax_ps = 1499,
+	.caslat_x = (1 << 11),
+	.taa_ps = 13750,
+	.trcd_ps = 13750,
+	.trp_ps = 13750,
+	.tras_ps = 35000,
+	.trc_ps = 48750,
+	.tfaw_ps = 30000,
+	.twr_ps = 15000,
+	.trfc_ps = 260000,
+	.trrd_ps = 5000, //1Kb page size!
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
+	.refresh_rate_ps = 70200000,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	int i;
+	
+	if (ctrl_num != 0) {
+		printf("Only 1 memory controller supported, but %i requested\n",
+		       ctrl_num);
+		return; 
+	}
+	
+	if (pdimm == NULL ) {
+		printf("Error, no valid dimm pararmeter supplied\n");
+		return;
+	}
+
+	if (!pdimm->n_ranks) {
+		printf("No ranks in dimm parameters. Configuration error?\n");
+		return;
+	}
+
+	/* set odt_rd_cfg and odt_wr_cfg. */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		popts->cs_local_opts[i].odt_wr_cfg = 4;
+	}
+
+	popts->wrlvl_en = 1;
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 13;
+	popts->wrlvl_start  = 7; /* 7/8 clock delay */
+	popts->wrlvl_ctl_2 = 0x06070809;
+	popts->wrlvl_ctl_3 = 0x0d0f0a09;
+
+	popts->ddr_cdr1 = 0x800c0000;
+	popts->ddr_cdr2 = 0x00000001;
+
+	/* Clock is launched 1/2 applied cycle after address/command */
+	popts->clk_adjust = 8; 
+	
+	/* cpo optimization */
+	popts->cpo_sample = 0x46;
+}
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+			    unsigned int controller_number,
+			    unsigned int dimm_number)
+{
+	const char dimm_model[] = "Soldered-down discrete DDR3";
+
+	if (((controller_number == 0) && (dimm_number == 0)) ||
+		((controller_number == 1) && (dimm_number == 0))) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+	
+	return 0;
+}
+
+int dram_init(void)
+{
+	phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+	uint32_t regval;
+
+	/* Remove reset of DDR using GPIO pin. We do this manually since
+	 * we have not yet access to the DM gpio at this time */
+	/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */
+	
+#define CONFIG_SYS_MPC85XX_GPIO2_ADDR	(CONFIG_SYS_IMMR + 0x131000)
+#define DDR_RST_N			(12)
+/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */
+/* #define DDR_RST_N     MPC85XX_GPIO_NR(2, 12) */
+
+	/* Set output */
+	regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8);
+	regval |= (0x80000000 >> 12);
+	out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8, regval);
+	
+	/* Set direction to acivate gpio pin */
+	regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR);
+	regval |= (0x80000000 >> 12);
+	out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR, regval);
+    
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+#else
+	/* DDR has been initialised by SPL loader */
+	dram_size =  fsl_ddr_sdram_size();
+#endif
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
diff --git a/board/scalys/simc-t2081/dragonfruit.c b/board/scalys/simc-t2081/dragonfruit.c
new file mode 100644
index 0000000..e3f1641
--- /dev/null
+++ b/board/scalys/simc-t2081/dragonfruit.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm-generic/gpio.h>
+#include "dragonfruit.h"
+
+/*
+ * SERDER MUX Configuration pins:
+ * IFC_A25 : GPIO2_25 : SERDES_CLK_ MUX_SER0_1_SEL
+ * IFC_A26 : GPIO2_26 : SERDES_CLK_ MUX_SER2_3_SEL
+ * IFC_A27 : GPIO2_27 : SERDES_CLK_ MUX_SER5_6_SEL
+ */
+#define MUX_SER0_1_SEL MPC85XX_GPIO_NR(2, 25)
+#define MUX_SER2_3_SEL MPC85XX_GPIO_NR(2, 26)
+#define MUX_SER5_6_SEL MPC85XX_GPIO_NR(2, 27)
+#define SERDES_CLK_OE  MPC85XX_GPIO_NR(2, 29)
+
+/* 
+ * MUX_SER0_1_SEL
+ * 	0: SERDES A => Slot1, lane 0
+ *	   SERDES B => Slot1, lane 1
+ *	1: SERDES A => CS4315 retimer => SFP+ 0
+ * 	   SERDES B => CS4315 retimer => SFP+ 1
+ */
+#define SER_0_1_SLOT1	0
+#define SER_0_1_SFP01	1
+
+/* 
+ * MUX_SER2_3_SEL
+ * 	0: SERDES C => Slot1, lane 2
+ * 	   SERDES D => Slot1, lane 3
+ * 	1: SERDES C => QSFP+ 2
+ * 	   SERDES D => QSFP+ 3
+ */
+#define SER_2_3_SLOT1	0
+#define SER_2_3_SFP23	2
+
+/* 
+ * SERDES E => Slot 4, lane 0 
+ */
+
+/* MUX_SER5_6_SEL
+ *	0: SERDES F => SLOT4, lane 1
+ *	   SERDES G => SLOT4, lane 2
+ * 	1: SERDES F => SLOT2
+ *	   SERDES G => SLOT3
+ */
+#define SER_5_6_SLOT4	0
+#define SER_5_6_SLOT23	4
+
+/* 
+ * SERDES H => Slot 4, lane 3
+ */
+
+int scalys_carrier_setup_muxing(int serdes_config)
+{
+	int ret = 0;
+	int mux_config = 0;
+	
+		
+	mdelay(100);
+
+	ret += gpio_request(MUX_SER0_1_SEL, "mux_ser0_1_sel");
+	ret += gpio_request(MUX_SER2_3_SEL, "mux_ser2_3_sel");
+	ret += gpio_request(MUX_SER5_6_SEL, "mux_ser5_6_sel");
+	ret += gpio_request(SERDES_CLK_OE, "serdes_clk_oe");
+	if (ret != 0) {
+		printf("gpio request failed(%i)\n", ret);
+	}
+	
+	
+	/* 
+	 * SERDES options for each target as supported by the dragonfruit 
+	 * carrier board. Refer to the QorIQ reference manual for the SERDES options table 
+	 * and all relevant information.
+	 * 
+	 * Note: The SERDES lanes A&B, C&D, and F&G can only be switched 
+	 * as pairs using the multiplexers. Which means some SERDES options are only partly usable.
+	 * 
+	 * 
+	 * T2081 has 8 SERDES lanes at up to 10GHz (ie. SERDES 2 configurations are DNC)
+	 * 
+	 */
+	switch(serdes_config){
+#if defined(CONFIG_PPC_T2081)
+		/* TODO: test all major cases */
+	case 0x6E:
+	case 0xC8:
+	case 0xD6:
+	case 0x6C:
+		mux_config = SER_5_6_SLOT4 | SER_2_3_SFP23 | SER_0_1_SFP01;
+		break;
+	case 0xAA: /* Note 2 */
+		mux_config = SER_5_6_SLOT4 | SER_2_3_SLOT1 | SER_0_1_SLOT1;
+		break;
+	case 0xBC: /* Note 2 */
+		mux_config = SER_5_6_SLOT4 | SER_2_3_SFP23 | SER_0_1_SLOT1;
+		break;
+	case 0xCA:
+	case 0xF2: /* Note 2 */
+	case 0xF8:
+	case 0xFA:
+	case 0x70:
+		mux_config = SER_5_6_SLOT23 | SER_2_3_SFP23 | SER_0_1_SFP01;
+		break;
+	case 0xDE: /* Note 2 */
+	case 0xE0: /* Note 2 */
+		mux_config = SER_5_6_SLOT23 | SER_2_3_SLOT1 | SER_0_1_SLOT1;
+		break;
+#else
+#error "Invalid or unspecified target cpu for dragonfruit carrier board!"
+#endif
+	default:
+		printf("Unsupported SERDES configuration (%02x) detected for dragonfruit carrier board (Warning: Using default multiplexer settings)!\n", serdes_config);
+	}
+	
+	printf("-----------------------------------------------------\n");
+	printf("Serdes lane configuration:\n");
+	if ((mux_config & 1) != 0) {
+		gpio_direction_output(MUX_SER0_1_SEL, 1);
+		printf("A: SFP slot 0 (T2081 only)\n");
+		printf("B: SFP slot 1 (T2081 only)\n");
+	} else {
+		gpio_direction_output(MUX_SER0_1_SEL, 0);
+		printf("A: PCIe slot 1 on lane 0\n");
+		printf("B: PCIe slot 1 on lane 1\n");
+	}
+	
+	if ((mux_config & 2) != 0) {
+		gpio_direction_output(MUX_SER2_3_SEL, 1);
+		printf("C: SFP slot 2\n");
+		printf("D: SFP slot 3\n");
+	} else {
+		gpio_direction_output(MUX_SER2_3_SEL, 0);
+		printf("C: PCIe slot 1 on lane 2\n");
+		printf("D: PCIe slot 1 on lane 3\n");
+	}
+	
+	printf("E: PCIe slot 4 on lane 0\n");
+	
+	if ((mux_config & 4) != 0) {
+		gpio_direction_output(MUX_SER5_6_SEL, 1);
+		printf("F: PCIe slot 2 on lane 0\n");
+		printf("G: PCIe slot 3 on lane 0\n");
+	} else {
+		gpio_direction_output(MUX_SER5_6_SEL, 0);
+		printf("F: PCIe slot 4 on lane 1\n");
+		printf("G: PCIe slot 4 on lane 2\n");
+	}
+	
+	printf("H: PCIe slot 4 on lane 3\n");
+	printf("-----------------------------------------------------\n");
+
+	/* Enable serdes clock */
+	gpio_direction_output(SERDES_CLK_OE, 1);
+	
+	mdelay(100);
+	
+	return ret;
+}
diff --git a/board/scalys/simc-t2081/dragonfruit.h b/board/scalys/simc-t2081/dragonfruit.h
new file mode 100644
index 0000000..554b2bf
--- /dev/null
+++ b/board/scalys/simc-t2081/dragonfruit.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DRAGON_FRUIT_H
+#define _DRAGON_FRUIT_H
+
+int scalys_carrier_setup_muxing(int serdes_config);
+
+#endif /* _DRAGON_FRUIT_H */
diff --git a/board/scalys/simc-t2081/eth.c b/board/scalys/simc-t2081/eth.c
new file mode 100644
index 0000000..82703d4
--- /dev/null
+++ b/board/scalys/simc-t2081/eth.c
@@ -0,0 +1,281 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <asm/immap_85xx.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fsl_dtsec.h>
+#include <vsc9953.h>
+#include <i2c.h>
+#include <phy.h>
+#include <cortina.h>
+
+#include "../../freescale/common/fman.h"
+
+#define VILLA_EEPROM_LOADER_STATUS 0xc01
+
+uint8_t sfp_phy_config[][2] = {
+	{ 0x1b, 0x90 },
+	{ 0x1b, 0x84 },
+	{ 0x09, 0x0F },
+	{ 0x09, 0x00 },
+	{ 0x00, 0x81 },
+	{ 0x00, 0x40 },
+};
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	struct memac_mdio_info dtsec_mdio_info;
+	struct memac_mdio_info tgec_mdio_info;
+	/*struct phy_driver *cortina_10G_phy;*/
+	unsigned int i;
+	uint8_t i2c_data;
+	int ret;
+	int phy_addr = 0;
+	
+	/*uint32_t *gpio1_gpdir = (uint32_t *) 0xffe130000;
+	uint32_t *gpio1_gpdat = (uint32_t *) 0xffe130008;*/
+	uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
+	uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
+	uint32_t *gpio4_gpdir = (uint32_t *) 0xffe133000;
+	uint32_t *gpio4_gpdat = (uint32_t *) 0xffe133008;
+	uint32_t regval;
+	
+	/* Try to read a byte from the carrier eeprom the determine if were on the correct carrier */
+	ret = i2c_read(0x54, 0, 2, &i2c_data, 1 );
+	if (ret != 0) {
+		printf("No dragonfruit carrier detected\n");
+		return 0;
+	}
+	
+	printf("Initializing Fman\n");
+
+	dtsec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the real 1G MDIO bus */
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+	
+	tgec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the 10G MDIO bus */
+	fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+   /* Marvell 88E1111 Setup
+	* 
+	* Remove reset from Ethernet PHY's 
+	* 
+	* Carrier board v1.x:
+	* IFC_PERR_B : GPIO2_15 : eth1_reset_n
+	* IFC_CS_N2  : GPIO2_11 : eth2_reset_n
+	*
+	* Carrier board v2.x:
+	* IFC_PERR_B : GPIO2_15 : eth1_reset_n
+	* N_DMA2_DDONE0_B : GPIO4_09 : eth2_reset_n
+	* 
+	* Note: make sure gpio pins are configured as gpio in RCW! 
+	*/
+
+#if 0 
+
+#define ETH1_RESET_N (0x80000000 >> 15)
+#define ETH2_RESET_N (0x80000000 >> 11)
+	/* TODO: use EEPROM data to chose carrier board version */
+	/* Carrier board v1.x */
+	/* Clear outputs to activate reset */
+	regval = in_be32(gpio2_gpdat);
+	regval &= ~(ETH1_RESET_N | ETH2_RESET_N);
+	out_be32(gpio2_gpdat, regval);
+	
+	/* Set outputs to output mode */
+	regval = in_be32(gpio2_gpdir);
+	regval |= (ETH1_RESET_N | ETH2_RESET_N);
+	out_be32(gpio2_gpdir, regval);
+	
+	/* Wait for 10 ms to to meet reset timing */
+	mdelay(10);
+	
+	/* Set outputs to de-activate reset */
+	regval = in_be32(gpio2_gpdat);
+	regval |= (ETH1_RESET_N | ETH2_RESET_N);
+	out_be32(gpio2_gpdat, regval);
+#else
+
+#define ETH1_RESET_N (0x80000000 >> 15)
+#define ETH2_RESET_N (0x80000000 >> 9)
+	/* Carrier board v2.x */
+	/* Clear outputs to activate reset */
+	regval = in_be32(gpio2_gpdat);
+	regval &= ~(ETH1_RESET_N);
+	out_be32(gpio2_gpdat, regval);
+	regval = in_be32(gpio4_gpdat);
+	regval &= ~(ETH2_RESET_N);
+	out_be32(gpio4_gpdat, regval);
+	
+	/* Set outputs to output mode */
+	regval = in_be32(gpio2_gpdir);
+	regval |= (ETH1_RESET_N);
+	out_be32(gpio2_gpdir, regval);
+	regval = in_be32(gpio4_gpdir);
+	regval |= (ETH2_RESET_N);
+	out_be32(gpio4_gpdir, regval);
+	
+	/* Wait for 10 ms to to meet reset timing */
+	mdelay(10);
+	
+	/* Set outputs to de-activate reset */
+	regval = in_be32(gpio2_gpdat);
+	regval |= (ETH1_RESET_N);
+	out_be32(gpio2_gpdat, regval);
+	regval = in_be32(gpio4_gpdat);
+	regval |= (ETH2_RESET_N);
+	out_be32(gpio4_gpdat, regval);
+#endif
+	
+	/* Write 0x4111 to reg 0x18 on both PHYs to change LEDs usage */
+	miiphy_write("FSL_MDIO0",0,0x18,0x4111);
+	miiphy_write("FSL_MDIO0",1,0x18,0x4111);
+
+	/* Remove SFP TX_disable */
+	i2c_set_bus_num(0);
+	ret = i2c_read(0x22, 0x0E, 1, &i2c_data, 1);
+	i2c_data &= ~0x04;
+	ret = i2c_write(0x22, 0x0E, 1, &i2c_data, 1);
+
+	mdelay(100);
+	
+	i2c_set_bus_num(3);
+	
+	for (phy_addr=0; phy_addr<4; phy_addr++) {
+		i2c_data = (1 << phy_addr);
+		ret = i2c_write(0x70, 0, 1, &i2c_data, 1);
+		if (ret) {
+			printf("Error Setting SFP i2c MUX\n");
+			break;
+		}
+		
+		for ( i = 0; i < 6; i++) {
+			ret = i2c_write(0x56, sfp_phy_config[i][0], 1, &(sfp_phy_config[i][1]), 1);
+			if (ret) {
+				printf("Error sfp phy(%i:%i):%02x to address %02x\n", phy_addr, i, sfp_phy_config[i][1],sfp_phy_config[i][0]);
+				break;
+			}
+		}
+	}
+	
+	/* Two external pin interfaces
+	 * MAC3|MAC4|MAC10 EC1|EC2 RGMII interface
+	 */
+	
+	/*
+	 * Program on board RGMII, SGMII PHY addresses.
+	 */
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		int idx = i - FM1_DTSEC1;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_RGMII:
+			if (FM1_DTSEC3 == i)
+				phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
+			if (FM1_DTSEC4 == i)
+				phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
+			/*if (FM1_DTSEC10 == i)
+				phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;*/
+			fm_info_set_phy_address(i, phy_addr);
+			break;
+/*		case PHY_INTERFACE_MODE_QSGMII:
+			fm_info_set_phy_address(i, i+2); 
+			break;*/
+		case PHY_INTERFACE_MODE_NONE:
+			fm_info_set_phy_address(i, 0);
+			break;
+		case PHY_INTERFACE_MODE_SGMII:
+			printf("TODO, add phy interface to SGMII\n");
+			fm_info_set_phy_address(i, PHY_INTERFACE_MODE_NONE);
+			break;
+		default:
+			printf("Fman1: DTSEC%u set to unknown interface %i\n",
+			       idx + 1, fm_info_get_enet_if(i));
+			//fm_info_set_phy_address(i, 0);
+			break;
+		}
+		fm_info_set_mdio(i, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+	}
+	
+	/* 10G XFI interface initialization (TODO)*/
+#if 0
+	/* Reset phy */
+	/* N_DMA2_DDONE0_B : GPIO1_09 : EDC_RST_N */
+#define EDC_RST_N (0x80000000 >> 9)
+	/* Clear outputs to activate reset */
+	regval = in_be32(gpio1_gpdat);
+	regval &= ~(EDC_RST_N);
+	out_be32(gpio1_gpdat, regval);
+	
+	/* Set outputs to output mode */
+	regval = in_be32(gpio1_gpdir);
+	regval |= (EDC_RST_N);
+	out_be32(gpio1_gpdir, regval);
+	
+	/* Wait for 10 ms to to meet reset timing */
+	mdelay(10);
+	
+	/* Set outputs to de-activate reset */
+	regval = in_be32(gpio1_gpdat);
+	regval |= (EDC_RST_N);
+	out_be32(gpio1_gpdat, regval);
+	
+	/* Wait 10ms to let phy set the load_failed bit */
+	mdelay(10);
+	
+	/* get cs4315 phy */
+	cortina_10G_phy = phy_find_by_mask(tgec_mdio_info, 0xfffffff0, PHY_INTERFACE_MODE_XGMII);
+	
+	/* Check load_failed == 1 (else skip initialization) */
+	mii_data = miiphy_read("FM_TGEC_MDIO",0,VILLA_EEPROM_LOADER_STATUS);
+	
+	if ((mii_data & 0x02) != 0) {
+		/* TODO: upload microcode */
+		cortina_10G_phy->config();
+	}
+	
+	/* TODO: insert additional configuration */
+	
+	/* Start phy */
+	cortina_10G_phy->startup();
+#endif
+	
+	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_XGMII:
+			fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
+			fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
+			break;
+		case PHY_INTERFACE_MODE_NONE:
+			fm_info_set_phy_address(i, 0);
+		default:
+			break;
+		}
+		fm_info_set_mdio(i, miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
+	}
+	
+	cpu_eth_init(bis);
+#endif
+	return pci_eth_init(bis);
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	return;
+}
diff --git a/board/scalys/simc-t2081/law.c b/board/scalys/simc-t2081/law.c
new file mode 100644
index 0000000..ec8ed07
--- /dev/null
+++ b/board/scalys/simc-t2081/law.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ * 
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+/*#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif*/
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	/* Limit DCSR to 32M to access NPC Trace Buffer */
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
+
diff --git a/board/scalys/simc-t2081/pci.c b/board/scalys/simc-t2081/pci.c
new file mode 100644
index 0000000..f3473f8
--- /dev/null
+++ b/board/scalys/simc-t2081/pci.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ * 
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+#include <asm-generic/gpio.h>
+#include "dragonfruit.h"
+
+#define SLOT1_REFCLK_OE_N MPC85XX_GPIO_NR(1, 9)
+#define SLOT2_REFCLK_OE_N MPC85XX_GPIO_NR(1, 10)
+#define SLOT3_REFCLK_OE_N MPC85XX_GPIO_NR(1, 11)
+#define SLOT4_REFCLK_OE_N MPC85XX_GPIO_NR(1, 12)
+	
+#define SLOT1_PRSNT2_N MPC85XX_GPIO_NR(1, 23)
+#define SLOT2_PRSNT2_N MPC85XX_GPIO_NR(1, 24)
+#define SLOT3_PRSNT2_N MPC85XX_GPIO_NR(1, 25)
+#define SLOT4_PRSNT2_N MPC85XX_GPIO_NR(1, 30)
+	
+#define PEX_REFCLK_SEL MPC85XX_GPIO_NR(2, 14)
+#define PEX_PERST_N MPC85XX_GPIO_NR(2, 13)
+
+
+void pci_init_board(void)
+{
+	int ret = 0;
+	int serdes_config;
+	ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	
+	/* SERDES configuration is determined boot time through the RCW config.
+	 * It is located in the fourth RCW word (bit 128-135 of the RCW). */
+	serdes_config = ( in_be32(&gur->rcwsr[4]) >> 24);
+	scalys_carrier_setup_muxing(serdes_config);
+	
+	ret += gpio_request(SLOT4_REFCLK_OE_N, "c19");
+	ret += gpio_request(PEX_REFCLK_SEL, "c14");
+	ret += gpio_request(PEX_PERST_N, "c15");
+	if (ret != 0)
+		printf("A gpio request failed(%i)\n", ret);
+	
+#if 0
+	/* Dragonfruit Carrier board 1.x */
+
+	/* 
+	 * IRQ[0-3] : PCIe present detect signals
+	 * IRQ[3] : GPIO1_23 : SLOT1_PRSNT2_N
+	 * IRQ[4] : GPIO1_24 : SLOT2_PRSNT2_N
+	 * IRQ[5] : GPIO1_25 : SLOT3_PRSNT2_N
+	 * IRQ[10] : GPIO1_30 : SLOT4_PRSNT2_N
+	 * 
+	 * Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7 
+	 * IFC_CS_N4 : GPIO1_IO09 : PCIe SLOT1_REFCLK_OE_N
+	 * IFC_CS_N5 : GPIO1_IO10 : PCIe SLOT2_REFCLK_OE_N
+	 * IFC_CS_N6 : GPIO1_IO11 : PCIe SLOT3_REFCLK_OE_N
+	 * IFC_CS_N7 : GPIO1_IO12 : PCIe SLOT4_REFCLK_OE_N
+	 */
+	
+	/* Set output to 0 to enable reference clocks */
+	regval = in_be32(gpio1_gpdat);
+	regval &= ~( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) );
+	out_be32(gpio1_gpdat, regval);
+	
+	/* Set Enable outputs*/
+	regval = in_be32(gpio1_gpdir);
+	regval |= ( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) );
+	out_be32(gpio1_gpdir, regval);
+	
+#else
+	/* Dragonfruit Carrier board 2.x */
+	/* 
+	 * PCIe present detect signals:
+	 * IRQ[3] : GPIO1_23 : SLOT1_PRSNT2_N
+	 * IRQ[4] : GPIO1_24 : SLOT2_PRSNT2_N
+	 * IRQ[5] : GPIO1_25 : SLOT3_PRSNT2_N
+	 * IRQ[10] : GPIO1_30 : SLOT4_PRSNT2_N
+	 * 
+	 * Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7 
+	 * IFC_CS_N7 : GPIO1_IO12 : PCIe SLOT4_REFCLK_OE_N (used for all 4 slots)
+	 * IFC_PAR1 : GPIO2_14 : PEX_REFCLK_SEL
+	 */
+	
+	/* Set output to 0 to enable reference clocks */
+	gpio_direction_output(SLOT4_REFCLK_OE_N, 0);
+	
+	/* Set PEX_REFCLK_SEL to 0 to select CLK0  */
+	gpio_direction_output(PEX_REFCLK_SEL, 0);
+#endif 
+	
+	/*
+	 * IFC_PAR0 : GPIO2_13 : PEX_PERST_N
+	 */
+
+	/* Remove reset from PCIe devices */
+	gpio_direction_output(PEX_PERST_N, 1);
+
+	/* Wait for 100 ms to allow the PCIe device to become ready */
+	mdelay(100);
+	
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/board/scalys/simc-t2081/simc-t2081.c b/board/scalys/simc-t2081/simc-t2081.c
new file mode 100644
index 0000000..0569d88
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <asm/fsl_pci.h>
+#include <fm_eth.h>
+#include <asm/processor.h>
+#include <asm/gpio.h>
+#include <fsl_esdhc.h>
+#include <dm.h>
+#include <board_configuration_data.h>
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: simc-t2081\n" );
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	const void* bcd_dtc_blob;
+	int ret;
+	
+	debug("t2081: misc_init_r\n");
+	/*
+	 * Initialize and set the LED's on the module to indicate u-boot is alive
+	 * IFC_A30 : led green : GPIO2_30
+	 * IFC_A31 : led red   : GPIO2_31
+	 */
+	#define MODULE_LED_RED      MPC85XX_GPIO_NR(2, 31)
+	#define MODULE_LED_GREEN    MPC85XX_GPIO_NR(2, 30)
+	gpio_request(MODULE_LED_RED, "module_led_red");
+	gpio_request(MODULE_LED_GREEN, "module_led_green");
+
+	gpio_direction_output(MODULE_LED_RED, 0);
+	gpio_direction_output(MODULE_LED_GREEN, 1);
+	
+	bcd_dtc_blob = get_boardinfo_eeprom();
+	if (bcd_dtc_blob != NULL) {
+		/* Board Configuration Data is intact, ready for parsing */
+		ret = add_mac_addressess_to_env(bcd_dtc_blob);
+		if (ret != 0) {
+			printf("Error adding BCD data to environement\n");
+		}
+	}
+
+	return 0;
+}
+
+/* Platform data for the GPIOs */
+static const struct mpc85xx_gpio_plat gpio_platdata[] = {
+	{ .addr = 0x130000, .ngpios = 32 },
+	{ .addr = 0x131000, .ngpios = 32 },
+	{ .addr = 0x132000, .ngpios = 32 },
+	{ .addr = 0x133000, .ngpios = 32,},
+};
+
+U_BOOT_DEVICES(mpc85xx_gpios) = {
+	{ "gpio_mpc85xx", &gpio_platdata[0] },
+	{ "gpio_mpc85xx", &gpio_platdata[1] },
+	{ "gpio_mpc85xx", &gpio_platdata[2] },
+	{ "gpio_mpc85xx", &gpio_platdata[3] },
+};
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	debug( "t2081: ft_board_setup\n" );
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	debug( "fdt_fixup_memory\n" );
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+    
+#ifdef CONFIG_PCI
+	debug( "pci_of_setup\n" );
+	FT_FSL_PCI_SETUP;
+#endif
+	debug( "fdt_fixup_liodn\n" );
+	fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+	debug( "fsl_fdt_fixup_dr_usb\n" );
+	fsl_fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	debug( "fdt_fixup_fman_ethernet\n" );
+	fdt_fixup_fman_ethernet(blob);
+#endif
+
+    return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	struct fsl_esdhc_cfg *cfg;
+
+	cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
+	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+	cfg->sdhc_clk = gd->arch.sdhc_clk;
+	cfg->max_bus_width = 4;
+	return fsl_esdhc_initialize(bis, cfg);
+
+	return 0;
+}
+
+#if 0
+void board_detail(void) 
+{
+	do_bcdinfo();
+}
+#endif
diff --git a/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg b/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg
new file mode 100644
index 0000000..9b0a4d6
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg
@@ -0,0 +1,46 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fffc0009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1 (LAW 13)
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure IFC controller
+# (IFC_CSPR1)
+09124010 ff8000c3
+#  IFC_CSOR_NAND
+09124130 85084101
+#  IFC_FTIM0_CS0_NAND to IFC_FTIM0_CS0_NAND 
+091241c0 181c080c
+091241c4 3850141a
+091241c8 03008028
+091241cc 28000000
+# Set IFC_CCR clkdiv to 2 (=/3) to get: 
+# (platform clock/2/3
+0912444c 02008000
+#Write clk_out reg (platform clock/2)
+#090E1A00 0001D800
+#Flush PBL data (Wait 0xFFFFF cycles )
+091380c0 000fffff
diff --git a/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg b/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
new file mode 100644
index 0000000..249bea9
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
@@ -0,0 +1,29 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+## SYS_CLK: 100MHz PLAT:600MHz Core:1800MHz FMAN:700MHz (1800MHz speedgrade)
+## DDR:1600MT/s
+0c06000e 12000000 00000000 40000000
+6c000002 40004000 e8105000 41000000
+00000000 cafebabe 00000000 00030ffc
+00000314 80000009 00000000 00000004
+
+## SYS_CLK: 100MHz PLAT:600MHz Core:1500MHz FMAN: 700MHz (1533MHz speedgrade)
+## DDR:1600MT/s
+# 0c06000e 0f000000 00000000 40000000
+# bc000002 40004000 e8105000 41000000
+# 00000000 cafebabe 00000000 00030ffc
+# 00000314 80000009 00000000 00000004
+
+
+### lowest valid clock & pll settings
+# 0806000a 0a000000 00000000 20000000
+# bc000002 40004000 e8105000 61000000
+# 00000000 cafebabe 00000000 00030ffc
+# 00000314 80000009 00000000 00000004
+
+## PCI SATA + Virtualization demo 
+# 0c06000e 12000000 00000000 40000000
+# aa000002 00404000 e8105000 41000000
+# 00000000 cafebabe 00000000 00030ffc
+# 00000314 80000009 00000000 00000004
diff --git a/board/scalys/simc-t2081/simc-t2081_nor_pbi.cfg b/board/scalys/simc-t2081/simc-t2081_nor_pbi.cfg
new file mode 100644
index 0000000..fd38b58
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_nor_pbi.cfg
@@ -0,0 +1,31 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fffc0009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1 (LAW 13)
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data (Wait 0xFFFFF cycles )
+091380c0 000fffff
diff --git a/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg b/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg
new file mode 100644
index 0000000..08c3b2a
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg
@@ -0,0 +1,9 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+## SYS_CLK: 100MHz PLAT:600MHz Core:1800MHz FMAN:700MHz (Max speedgrade)
+## DDR:1600MT/s SERDES:0x6c 
+0c06000e 12000000 00000000 40000000
+6c000002 40004000 e8023000 41000000
+00000000 cafebabe 00000000 00030ffc
+00000314 80000009 00000000 00000004
diff --git a/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg b/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg
new file mode 100644
index 0000000..849721a
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg
@@ -0,0 +1,33 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fffc0009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1 (LAW 13)
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Write clk_out reg (platform clock/2)
+#090E1A00 0000EC00
+#Flush PBL data (Wait 0xFFFFF cycles )
+091380c0 000fffff
diff --git a/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg b/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg
new file mode 100644
index 0000000..e7c9aad
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg
@@ -0,0 +1,11 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+## SYS_CLK: 100MHz PLAT:600MHz Core:1800MHz FMAN:700MHz (Max speedgrade)
+## DDR:1600MT/s SERDES:0x6c  
+0c06000e 12000000 00000000 40000000
+6c000002 40004000 68105000 41000000
+00000000 cafebabe 00000000 00030ffc
+00000314 80000009 00000000 00000004
+
+
diff --git a/board/scalys/simc-t2081/spl.c b/board/scalys/simc-t2081/spl.c
new file mode 100644
index 0000000..d36e9f4
--- /dev/null
+++ b/board/scalys/simc-t2081/spl.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ * 
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <console.h>
+#include <nand.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	return CONFIG_DDR_CLK_FREQ;
+}
+
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK	0xFF800000
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, sys_clk, uart_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+	/* Update GD pointer */
+	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+	/* compiler optimization barrier needed for GCC >= 3.4 */
+	__asm__ __volatile__("" : : : "memory");
+
+	console_init_f();
+
+	/* initialize selected port with appropriate baud rate */
+	sys_clk = get_board_sys_clk();
+	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+	uart_clk = sys_clk * plat_ratio / 2;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     uart_clk / 16 / CONFIG_BAUDRATE);
+
+	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void setup_ifc_nand(enum ifc_chip_sel cs)
+{
+	set_ifc_cspr_ext(cs, CONFIG_SYS_NAND_CSPR_EXT);
+	set_ifc_csor	(cs, CONFIG_SYS_NAND_CSOR);
+	set_ifc_amask	(cs, CONFIG_SYS_NAND_AMASK);
+	set_ifc_cspr	(cs, CONFIG_SYS_NAND_CSPR);
+	set_ifc_ftim	(cs, IFC_FTIM0, CONFIG_SYS_NAND_FTIM0);
+	set_ifc_ftim	(cs, IFC_FTIM1, CONFIG_SYS_NAND_FTIM1);
+	set_ifc_ftim	(cs, IFC_FTIM2, CONFIG_SYS_NAND_FTIM2);
+	set_ifc_ftim	(cs, IFC_FTIM3, CONFIG_SYS_NAND_FTIM3);
+	set_ifc_csor_ext(cs, 0);
+
+}
+
+void setup_ifc_nor(enum ifc_chip_sel cs)
+{
+	set_ifc_cspr_ext(cs, CONFIG_SYS_NOR_CSPR_EXT);
+	set_ifc_csor	(cs, CONFIG_SYS_NOR_CSOR);
+	set_ifc_amask	(cs, CONFIG_SYS_NOR_AMASK);
+	set_ifc_cspr	(cs, CONFIG_SYS_NOR_CSPR);
+	set_ifc_ftim	(cs, IFC_FTIM0, CONFIG_SYS_NOR_FTIM0);
+	set_ifc_ftim	(cs, IFC_FTIM1, CONFIG_SYS_NOR_FTIM1);
+	set_ifc_ftim	(cs, IFC_FTIM2, CONFIG_SYS_NOR_FTIM2);
+	set_ifc_ftim	(cs, IFC_FTIM3, CONFIG_SYS_NOR_FTIM3);
+	set_ifc_csor_ext(cs, 0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	bd_t *bd;
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	uint32_t boot_source;
+	
+	__attribute__((noreturn)) void (*boot)(void) = hang;
+
+	bd = (bd_t *)(gd + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+	arch_cpu_init();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+
+	gd->ram_size = dram_init();
+
+	/* Get the boot source from the Power On Status Register (set by QSC) */
+	boot_source = (in_be32(&gur->porsr1) >> 23);
+
+	switch (boot_source) {
+	case 0x23:
+		/* NOR boot */
+		setup_ifc_nor(IFC_CS0);
+		setup_ifc_nand(IFC_CS1);
+
+		memcpy((void*)CONFIG_SYS_NAND_U_BOOT_DST, (void*) CONFIG_SYS_FLASH_BASE + CONFIG_SPL_PAD_TO, CONFIG_SYS_NAND_U_BOOT_SIZE);
+
+		flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+		boot = (void*) CONFIG_SYS_NAND_U_BOOT_START;
+		break;
+
+	case 0x45:
+#if 0
+		/*SPI nor flash */
+		setup_ifc_nand(IFC_CS0);
+		setup_ifc_nor(IFC_CS1);
+		//fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, (uchar *)CONFIG_ENV_ADDR);
+		{
+			struct spi_flash *flash;
+
+			flash = spi_flash_probe(0, 0,
+				CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
+			if (flash == NULL) {
+				puts("\nspi_flash_probe failed");
+				hang();
+			}
+
+			spi_flash_read(flash, CONFIG_SPL_PAD_TO, CONFIG_SYS_NAND_U_BOOT_SIZE, (void*) CONFIG_SYS_NAND_U_BOOT_DST);
+		}
+#endif
+		printf("TODO, load u-boot from SPI....\n");
+		hang();
+		break;
+	case 0x40:
+		/* SD/MMC (eSDHC) boot */
+#if defined(CONFIG_SPL_MMC_BOOT) || defined(CONFIG_SDHC_FLASH_BOOT)
+		setup_ifc_nand(IFC_CS0);
+		setup_ifc_nor(IFC_CS1);
+		
+		mmc_initialize(bd);
+		mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)CONFIG_ENV_ADDR);
+		boot = mmc_boot;
+#endif
+		break;
+	case 0x105:
+		/* NAND boot */
+		setup_ifc_nand(IFC_CS0);
+		setup_ifc_nor(IFC_CS1);
+
+		nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+		    (uchar *)CONFIG_ENV_ADDR);
+		boot = nand_boot;
+		break;
+	default:
+		printf("Unknown boot source (%3x\n", boot_source);
+	break;
+	}
+	boot();
+}
diff --git a/board/scalys/simc-t2081/tlb.c b/board/scalys/simc-t2081/tlb.c
new file mode 100644
index 0000000..b16b682
--- /dev/null
+++ b/board/scalys/simc-t2081/tlb.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ * 
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
+	!defined(CONFIG_SECURE_BOOT)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 512K SRAM, the address of the
+	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 512K SRAM, in case of Secure Boot
+	 * the physical address of the SRAM is at 0xbffc0000,
+	 * and virtual address is 0xfffc0000
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR,
+		      CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_512K, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_64M, 1),
+
+#ifndef CONFIG_SPL_BUILD
+	/* *I*G* - PCIe 1, 0x80000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_512M, 1),
+
+	/* *I*G* - PCIe 2, 0xa0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCIe 3, 0xb0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+			  
+	/* *I*G* - PCIe 4, 0xc0000000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_256K, 1),
+
+
+	/* Bman/Qman
+	 */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 9, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 11, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+			  
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 17, BOOKE_PAGESZ_1G, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 18, BOOKE_PAGESZ_1G, 1)
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/seco/common/mx6.c b/board/seco/common/mx6.c
index 2f14f59..ad4bb5b 100644
--- a/board/seco/common/mx6.c
+++ b/board/seco/common/mx6.c
@@ -12,10 +12,10 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
@@ -27,7 +27,7 @@
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <micrel.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
 #include <i2c.h>
 
 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
diff --git a/board/seco/mx6quq7/mx6quq7.c b/board/seco/mx6quq7/mx6quq7.c
index 08566fc..be8fef4 100644
--- a/board/seco/mx6quq7/mx6quq7.c
+++ b/board/seco/mx6quq7/mx6quq7.c
@@ -12,10 +12,10 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
 #include <malloc.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
@@ -28,7 +28,7 @@
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <micrel.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
 #include <i2c.h>
 
 #include "../common/mx6.h"
diff --git a/board/sfr/nb4_ser/Kconfig b/board/sfr/nb4_ser/Kconfig
new file mode 100644
index 0000000..78aefb5
--- /dev/null
+++ b/board/sfr/nb4_ser/Kconfig
@@ -0,0 +1,12 @@
+if BOARD_SFR_NB4_SER
+
+config SYS_BOARD
+	default "nb4_ser"
+
+config SYS_VENDOR
+	default "sfr"
+
+config SYS_CONFIG_NAME
+	default "sfr_nb4_ser"
+
+endif
diff --git a/board/sfr/nb4_ser/MAINTAINERS b/board/sfr/nb4_ser/MAINTAINERS
new file mode 100644
index 0000000..bf80267
--- /dev/null
+++ b/board/sfr/nb4_ser/MAINTAINERS
@@ -0,0 +1,6 @@
+SFR NEUFBOX 4 SERCOMM BOARD
+M:	Álvaro Fernández Rojas <noltari@gmail.com>
+S:	Maintained
+F:	board/sfr/nb4_ser/
+F:	include/configs/sfr_nb4_ser.h
+F:	configs/sfr_nb4-ser_ram_defconfig
diff --git a/board/sfr/nb4_ser/Makefile b/board/sfr/nb4_ser/Makefile
new file mode 100644
index 0000000..f3b1404
--- /dev/null
+++ b/board/sfr/nb4_ser/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += nb4-ser.o
diff --git a/board/sfr/nb4_ser/nb4-ser.c b/board/sfr/nb4_ser/nb4-ser.c
new file mode 100644
index 0000000..d181ca6
--- /dev/null
+++ b/board/sfr/nb4_ser/nb4-ser.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
diff --git a/board/shmin/Makefile b/board/shmin/Makefile
index daf36de..d169661 100644
--- a/board/shmin/Makefile
+++ b/board/shmin/Makefile
@@ -7,4 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 
 obj-y	:= shmin.o
-obj-y	+= lowlevel_init.o
+extra-y	+= lowlevel_init.o
diff --git a/board/shmin/shmin.c b/board/shmin/shmin.c
index 74d1e39..42bd126 100644
--- a/board/shmin/shmin.c
+++ b/board/shmin/shmin.c
@@ -33,16 +33,6 @@ int board_init(void)
 	return 0;
 }
 
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
-	return 0;
-}
-
 int board_eth_init(bd_t *bis)
 {
 	return ne2k_register();
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index 9cafcea..b967227 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -28,6 +28,7 @@
 #include <miiphy.h>
 #include <cpsw.h>
 #include <watchdog.h>
+#include <asm/mach-types.h>
 #include "../common/factoryset.h"
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c
index 78a7946..c6ba673 100644
--- a/board/siemens/smartweb/smartweb.c
+++ b/board/siemens/smartweb/smartweb.c
@@ -34,6 +34,7 @@
 #ifndef CONFIG_DM_ETH
 # include <netdev.h>
 #endif
+#include <g_dnl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -257,11 +258,8 @@ void mem_init(void)
 }
 #endif
 
-static struct atmel_serial_platdata at91sam9260_serial_plat = {
-	.base_addr = ATMEL_BASE_DBGU,
-};
-
-U_BOOT_DEVICE(at91sam9260_serial) = {
-	.name	= "serial_atmel",
-	.platdata = &at91sam9260_serial_plat,
-};
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+	g_dnl_set_serialnumber("1");
+	return 0;
+}
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
index 8da24be..4aa8d64 100644
--- a/board/siemens/taurus/taurus.c
+++ b/board/siemens/taurus/taurus.c
@@ -448,12 +448,3 @@ U_BOOT_CMD(
 );
 #endif
 #endif
-
-static struct atmel_serial_platdata at91sam9260_serial_plat = {
-	.base_addr = ATMEL_BASE_DBGU,
-};
-
-U_BOOT_DEVICE(at91sam9260_serial) = {
-	.name   = "serial_atmel",
-	.platdata = &at91sam9260_serial_plat,
-};
diff --git a/board/socrates/nand.c b/board/socrates/nand.c
index a67d812..c7483fe 100644
--- a/board/socrates/nand.c
+++ b/board/socrates/nand.c
@@ -9,7 +9,7 @@
 
 #if defined(CONFIG_SYS_NAND_BASE)
 #include <nand.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/io.h>
 
 static int state;
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 8b34a80..fb691c2 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -378,7 +378,7 @@ static void board_backlight_brightness(int br)
 
 		/* LEDs on */
 		reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
-		if (!(reg & BACKLIGHT_ENABLE));
+		if (!(reg & BACKLIGHT_ENABLE))
 			out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c),
 				 reg | BACKLIGHT_ENABLE);
 	} else {
diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
index 2773f59..8906636 100644
--- a/board/solidrun/clearfog/clearfog.c
+++ b/board/solidrun/clearfog/clearfog.c
@@ -83,7 +83,8 @@ static struct hws_topology_map board_topology_map = {
 	    MEM_4G,			/* mem_size */
 	    DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_l cas_wl */
-	    HWS_TEMP_LOW} },		/* temperature */
+	    HWS_TEMP_LOW,		/* temperature */
+	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per Interface*/
 	BUS_MASK_32BIT			/* Busses mask */
 };
@@ -131,8 +132,12 @@ int board_init(void)
 	/* Toggle GPIO41 to reset onboard switch and phy */
 	clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
 	clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
+	/* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
+	clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
+	clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
 	mdelay(1);
 	setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
+	setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
 	mdelay(10);
 
 	/* Init I2C IO expanders */
diff --git a/board/solidrun/clearfog/kwbimage.cfg b/board/solidrun/clearfog/kwbimage.cfg
index c650c2c..f41d25a 100644
--- a/board/solidrun/clearfog/kwbimage.cfg
+++ b/board/solidrun/clearfog/kwbimage.cfg
@@ -2,7 +2,7 @@
 # Copyright (C) 2015 Stefan Roese <sr@denx.de>
 #
 
-# Armada XP uses version 1 image format
+# Armada 38x use version 1 image format
 VERSION		1
 
 # Boot Media configurations
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 3a1ce24..1ccdfa8 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -19,10 +19,11 @@
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/mxc_hdmi.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <malloc.h>
@@ -314,6 +315,10 @@ int board_early_init_f(void)
 	ret = setup_display();
 #endif
 
+#ifdef CONFIG_CMD_SATA
+	setup_sata();
+#endif
+
 #ifdef CONFIG_USB_EHCI_MX6
 	setup_usb();
 #endif
diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c
index bc92cd6..d6a84db 100644
--- a/board/spear/common/spr_misc.c
+++ b/board/spear/common/spr_misc.c
@@ -33,10 +33,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
 }
 
 int board_early_init_f()
diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c
index 396b5bd..8f8132a 100644
--- a/board/spear/spear300/spear300.c
+++ b/board/spear/spear300/spear300.c
@@ -11,6 +11,7 @@
 #include <nand.h>
 #include <asm/io.h>
 #include <linux/mtd/fsmc_nand.h>
+#include <asm/mach-types.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c
index 6f39ef1..d07dda3 100644
--- a/board/spear/spear310/spear310.c
+++ b/board/spear/spear310/spear310.c
@@ -12,6 +12,7 @@
 #include <nand.h>
 #include <asm/io.h>
 #include <linux/mtd/fsmc_nand.h>
+#include <asm/mach-types.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c
index 52196af..66073f3 100644
--- a/board/spear/spear320/spear320.c
+++ b/board/spear/spear320/spear320.c
@@ -12,6 +12,7 @@
 #include <nand.h>
 #include <asm/io.h>
 #include <linux/mtd/fsmc_nand.h>
+#include <asm/mach-types.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c
index 858a9ca..2a54b8b 100644
--- a/board/spear/spear600/spear600.c
+++ b/board/spear/spear600/spear600.c
@@ -11,6 +11,7 @@
 #include <nand.h>
 #include <asm/io.h>
 #include <linux/mtd/fsmc_nand.h>
+#include <asm/mach-types.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c
index f8e9fdd..2c34ea1 100644
--- a/board/spear/x600/x600.c
+++ b/board/spear/x600/x600.c
@@ -14,6 +14,7 @@
 #include <phy.h>
 #include <rtc.h>
 #include <asm/io.h>
+#include <asm/mach-types.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
diff --git a/board/sr1500/qts/sdram_config.h b/board/sr1500/qts/sdram_config.h
index edbaf89..83b8a35 100644
--- a/board/sr1500/qts/sdram_config.h
+++ b/board/sr1500/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			5
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x330
diff --git a/board/st/stih410-b2260/Kconfig b/board/st/stih410-b2260/Kconfig
new file mode 100644
index 0000000..590add0
--- /dev/null
+++ b/board/st/stih410-b2260/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_STIH410_B2260
+
+config SYS_BOARD
+	string
+	default "stih410-b2260"
+
+config SYS_VENDOR
+	string
+	default "st"
+
+config SYS_SOC
+	string
+	default "stih410"
+
+config SYS_CONFIG_NAME
+	string
+	default "stih410-b2260"
+
+endif
diff --git a/board/st/stih410-b2260/MAINTAINERS b/board/st/stih410-b2260/MAINTAINERS
new file mode 100644
index 0000000..4f557ac
--- /dev/null
+++ b/board/st/stih410-b2260/MAINTAINERS
@@ -0,0 +1,7 @@
+STIH410-B2260 BOARD
+M:	Patrice Chotard <patrice.chotard@st.com>
+S:	Maintained
+F:	board/st/stih410-b2260/
+F:	include/configs/stih410-b2260.h
+F:	configs/stih410-b2260_defconfig
+F:	arch/arm/dts/stih*
diff --git a/board/st/stih410-b2260/Makefile b/board/st/stih410-b2260/Makefile
new file mode 100644
index 0000000..68a7903
--- /dev/null
+++ b/board/st/stih410-b2260/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2017
+# Patrice Chotard, <patrice.chotard@st.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	= board.o
diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c
new file mode 100644
index 0000000..92b0695
--- /dev/null
+++ b/board/st/stih410-b2260/board.c
@@ -0,0 +1,38 @@
+/*
+ * Board init file for STiH410-B2260
+ *
+ * (C) Copyright 2017 Patrice Chotard <patrice.chotard@st.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
+
+int board_init(void)
+{
+	return 0;
+}
diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c
index d16d73f..8c8abf6 100644
--- a/board/st/stm32f429-discovery/stm32f429-discovery.c
+++ b/board/st/stm32f429-discovery/stm32f429-discovery.c
@@ -12,12 +12,12 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <asm/io.h>
 #include <asm/armv7m.h>
 #include <asm/arch/stm32.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/fmc.h>
-#include <dm/platdata.h>
 #include <dm/platform_data/serial_stm32.h>
 #include <asm/arch/stm32_periph.h>
 #include <asm/arch/stm32_defs.h>
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 404fdfa..f31768e 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -6,302 +6,162 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
 #include <asm/io.h>
 #include <asm/armv7m.h>
 #include <asm/arch/stm32.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/rcc.h>
-#include <asm/arch/fmc.h>
-#include <dm/platdata.h>
-#include <dm/platform_data/serial_stm32x7.h>
 #include <asm/arch/stm32_periph.h>
 #include <asm/arch/stm32_defs.h>
+#include <asm/arch/syscfg.h>
+#include <asm/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-const struct stm32_gpio_ctl gpio_ctl_gpout = {
-	.mode = STM32_GPIO_MODE_OUT,
-	.otype = STM32_GPIO_OTYPE_PP,
-	.speed = STM32_GPIO_SPEED_50M,
-	.pupd = STM32_GPIO_PUPD_NO,
-	.af = STM32_GPIO_AF0
-};
-
-const struct stm32_gpio_ctl gpio_ctl_usart = {
-	.mode = STM32_GPIO_MODE_AF,
-	.otype = STM32_GPIO_OTYPE_PP,
-	.speed = STM32_GPIO_SPEED_50M,
-	.pupd = STM32_GPIO_PUPD_UP,
-	.af = STM32_GPIO_AF7
-};
-
-const struct stm32_gpio_ctl gpio_ctl_fmc = {
-	.mode = STM32_GPIO_MODE_AF,
-	.otype = STM32_GPIO_OTYPE_PP,
-	.speed = STM32_GPIO_SPEED_100M,
-	.pupd = STM32_GPIO_PUPD_NO,
-	.af = STM32_GPIO_AF12
-};
-
-static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = {
-	/* Chip is LQFP144, see DM00077036.pdf for details */
-	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_10},	/* 79, FMC_D15 */
-	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_9},	/* 78, FMC_D14 */
-	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_8},	/* 77, FMC_D13 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_15},	/* 68, FMC_D12 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_14},	/* 67, FMC_D11 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_13},	/* 66, FMC_D10 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_12},	/* 65, FMC_D9 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_11},	/* 64, FMC_D8 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_10},	/* 63, FMC_D7 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_9},	/* 60, FMC_D6 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_8},	/* 59, FMC_D5 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_7},	/* 58, FMC_D4 */
-	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_1},	/* 115, FMC_D3 */
-	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_0},	/* 114, FMC_D2 */
-	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_15},	/* 86, FMC_D1 */
-	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_14},	/* 85, FMC_D0 */
-
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_1},	/* 142, FMC_NBL1 */
-	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_0},	/* 141, FMC_NBL0 */
-
-	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_5},	/* 90, FMC_A15, BA1 */
-	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_4},	/* 89, FMC_A14, BA0 */
-
-	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_1},	/* 57, FMC_A11 */
-	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_0},	/* 56, FMC_A10 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_15},	/* 55, FMC_A9 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_14},	/* 54, FMC_A8 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_13},	/* 53, FMC_A7 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_12},	/* 50, FMC_A6 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_5},	/* 15, FMC_A5 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_4},	/* 14, FMC_A4 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_3},	/* 13, FMC_A3 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_2},	/* 12, FMC_A2 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_1},	/* 11, FMC_A1 */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_0},	/* 10, FMC_A0 */
-
-	{STM32_GPIO_PORT_H, STM32_GPIO_PIN_3},	/* 136, SDRAM_NE */
-	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_11},	/* 49, SDRAM_NRAS */
-	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_15},	/* 132, SDRAM_NCAS */
-	{STM32_GPIO_PORT_H, STM32_GPIO_PIN_5},	/* 26, SDRAM_NWE */
-	{STM32_GPIO_PORT_C, STM32_GPIO_PIN_3},	/* 135, SDRAM_CKE */
-
-	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_8},	/* 93, SDRAM_CLK */
-};
-
-static int fmc_setup_gpio(void)
+int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size)
 {
-	int rv = 0;
-	int i;
+	int mr_node;
 
-	clock_setup(GPIO_B_CLOCK_CFG);
-	clock_setup(GPIO_C_CLOCK_CFG);
-	clock_setup(GPIO_D_CLOCK_CFG);
-	clock_setup(GPIO_E_CLOCK_CFG);
-	clock_setup(GPIO_F_CLOCK_CFG);
-	clock_setup(GPIO_G_CLOCK_CFG);
-	clock_setup(GPIO_H_CLOCK_CFG);
-
-	for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
-		rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
-				&gpio_ctl_fmc);
-		if (rv)
-			goto out;
-	}
+	mr_node = fdt_path_offset(gd->fdt_blob, "/memory");
+	if (mr_node < 0)
+		return mr_node;
+	*mr_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, mr_node,
+						      "reg", 0, mr_size, false);
+	debug("mr_base = %lx, mr_size= %lx\n", *mr_base, *mr_size);
 
-out:
-	return rv;
-}
-
-/*
- * STM32 RCC FMC specific definitions
- */
-#define RCC_ENR_FMC	(1 << 0)	/* FMC module clock  */
-
-static inline u32 _ns2clk(u32 ns, u32 freq)
-{
-	u32 tmp = freq/1000000;
-	return (tmp * ns) / 1000;
+	return 0;
 }
-
-#define NS2CLK(ns) (_ns2clk(ns, freq))
-
-/*
- * Following are timings for IS42S16400J, from corresponding datasheet
- */
-#define SDRAM_CAS	3	/* 3 cycles */
-#define SDRAM_NB	1	/* Number of banks */
-#define SDRAM_MWID	1	/* 16 bit memory */
-
-#define SDRAM_NR	0x1	/* 12-bit row */
-#define SDRAM_NC	0x0	/* 8-bit col */
-#define SDRAM_RBURST	0x1	/* Single read requests always as bursts */
-#define SDRAM_RPIPE	0x0	/* No HCLK clock cycle delay */
-
-#define SDRAM_TRRD	NS2CLK(12)
-#define SDRAM_TRCD	NS2CLK(18)
-#define SDRAM_TRP	NS2CLK(18)
-#define SDRAM_TRAS	NS2CLK(42)
-#define SDRAM_TRC	NS2CLK(60)
-#define SDRAM_TRFC	NS2CLK(60)
-#define SDRAM_TCDL	(1 - 1)
-#define SDRAM_TRDL	NS2CLK(12)
-#define SDRAM_TBDL	(1 - 1)
-#define SDRAM_TREF	(NS2CLK(64000000 / 8192) - 20)
-#define SDRAM_TCCD	(1 - 1)
-
-#define SDRAM_TXSR	SDRAM_TRFC	/* Row cycle time after precharge */
-#define SDRAM_TMRD	1		/* Page 10, Mode Register Set */
-
-
-/* Last data in to row precharge, need also comply ineq on page 1648 */
-#define SDRAM_TWR	max(\
-	(int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
-	(int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\
-)
-
-
-#define SDRAM_MODE_BL_SHIFT	0
-#define SDRAM_MODE_CAS_SHIFT	4
-#define SDRAM_MODE_BL		0
-#define SDRAM_MODE_CAS		SDRAM_CAS
-
 int dram_init(void)
 {
-	u32 freq;
 	int rv;
+	fdt_addr_t mr_base, mr_size;
 
-	rv = fmc_setup_gpio();
+#ifndef CONFIG_SUPPORT_SPL
+	struct udevice *dev;
+	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (rv) {
+		debug("DRAM init failed: %d\n", rv);
+		return rv;
+	}
+
+#endif
+	rv = get_memory_base_size(&mr_base, &mr_size);
 	if (rv)
 		return rv;
+	gd->ram_size = mr_size;
+	gd->ram_top = mr_base;
 
-	setbits_le32(RCC_BASE + RCC_AHB3ENR, RCC_ENR_FMC);
+	return rv;
+}
 
+int dram_init_banksize(void)
+{
+	fdt_addr_t mr_base, mr_size;
+	get_memory_base_size(&mr_base, &mr_size);
 	/*
-	 * Get frequency for NS2CLK calculation.
+	 * Fill in global info with description of SRAM configuration
 	 */
-	freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
-
-	writel(
-		CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
-		| SDRAM_CAS << FMC_SDCR_CAS_SHIFT
-		| SDRAM_NB << FMC_SDCR_NB_SHIFT
-		| SDRAM_MWID << FMC_SDCR_MWID_SHIFT
-		| SDRAM_NR << FMC_SDCR_NR_SHIFT
-		| SDRAM_NC << FMC_SDCR_NC_SHIFT
-		| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
-		| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
-		&STM32_SDRAM_FMC->sdcr1);
-
-	writel(
-		SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
-		| SDRAM_TRP << FMC_SDTR_TRP_SHIFT
-		| SDRAM_TWR << FMC_SDTR_TWR_SHIFT
-		| SDRAM_TRC << FMC_SDTR_TRC_SHIFT
-		| SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
-		| SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
-		| SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
-		&STM32_SDRAM_FMC->sdtr1);
-
-	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
-	       &STM32_SDRAM_FMC->sdcmr);
-
-	udelay(200);	/* 200 us delay, page 10, "Power-Up" */
-	FMC_BUSY_WAIT();
+	gd->bd->bi_dram[0].start = mr_base;
+	gd->bd->bi_dram[0].size  = mr_size;
 
-	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
-	       &STM32_SDRAM_FMC->sdcmr);
-
-	udelay(100);
-	FMC_BUSY_WAIT();
-
-	writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
-		| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
-
-	udelay(100);
-	FMC_BUSY_WAIT();
-
-	writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
-		| SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
-		<< FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
-		&STM32_SDRAM_FMC->sdcmr);
-
-	udelay(100);
-
-	FMC_BUSY_WAIT();
-
-	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
-	       &STM32_SDRAM_FMC->sdcmr);
-
-	FMC_BUSY_WAIT();
+	return 0;
+}
 
-	/* Refresh timer */
-	writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
+#ifdef CONFIG_ETH_DESIGNWARE
+static int stmmac_setup(void)
+{
+	clock_setup(SYSCFG_CLOCK_CFG);
+	/* Set >RMII mode */
+	STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
+	clock_setup(STMMAC_CLOCK_CFG);
 
-	/*
-	 * Fill in global info with description of SRAM configuration
-	 */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
-	gd->bd->bi_dram[0].size  = CONFIG_SYS_RAM_SIZE;
+	return 0;
+}
 
-	gd->ram_size = CONFIG_SYS_RAM_SIZE;
+int board_early_init_f(void)
+{
+	stmmac_setup();
 
-	return rv;
+	return 0;
 }
+#endif
 
-static const struct stm32_gpio_dsc usart_gpio[] = {
-	{STM32_GPIO_PORT_A, STM32_GPIO_PIN_9},	/* TX */
-	{STM32_GPIO_PORT_B, STM32_GPIO_PIN_7},	/* RX */
-};
-
-int uart_setup_gpio(void)
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
 {
-	int i;
-	int rv = 0;
-
-	clock_setup(GPIO_A_CLOCK_CFG);
-	clock_setup(GPIO_B_CLOCK_CFG);
-	for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
-		rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
-		if (rv)
-			goto out;
-	}
+	debug("SPL: booting kernel\n");
+	/* break into full u-boot on 'c' */
+	return serial_tstc() && serial_getc() == 'c';
+}
+#endif
 
-out:
+int spl_dram_init(void)
+{
+	struct udevice *dev;
+	int rv;
+	rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (rv)
+		debug("DRAM init failed: %d\n", rv);
 	return rv;
 }
+void spl_board_init(void)
+{
+	spl_dram_init();
+	preloader_console_init();
+	arch_cpu_init(); /* to configure mpu for sdram rw permissions */
+}
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_XIP;
+}
 
-static const struct stm32x7_serial_platdata serial_platdata = {
-	.base = (struct stm32_usart *)USART1_BASE,
-	.clock = CONFIG_SYS_CLK_FREQ,
-};
-
-U_BOOT_DEVICE(stm32x7_serials) = {
-	.name = "serial_stm32x7",
-	.platdata = &serial_platdata,
-};
-
+#endif
 u32 get_board_rev(void)
 {
 	return 0;
 }
 
-int board_early_init_f(void)
+int board_late_init(void)
 {
-	int res;
+	struct gpio_desc gpio = {};
+	int node;
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,led1");
+	if (node < 0)
+		return -1;
+
+	gpio_request_by_name_nodev(offset_to_ofnode(node), "led-gpio", 0, &gpio,
+				   GPIOD_IS_OUT);
+
+	if (dm_gpio_is_valid(&gpio)) {
+		dm_gpio_set_value(&gpio, 0);
+		mdelay(10);
+		dm_gpio_set_value(&gpio, 1);
+	}
+
+	/* read button 1*/
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,button1");
+	if (node < 0)
+		return -1;
 
-	res = uart_setup_gpio();
-	clock_setup(USART1_CLOCK_CFG);
-	if (res)
-		return res;
+	gpio_request_by_name_nodev(offset_to_ofnode(node), "button-gpio", 0,
+				   &gpio, GPIOD_IS_IN);
+
+	if (dm_gpio_is_valid(&gpio)) {
+		if (dm_gpio_get_value(&gpio))
+			puts("usr button is at HIGH LEVEL\n");
+		else
+			puts("usr button is at LOW LEVEL\n");
+	}
 
 	return 0;
 }
 
 int board_init(void)
 {
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
+	gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
 	return 0;
 }
diff --git a/board/st/stv0991/stv0991.c b/board/st/stv0991/stv0991.c
index add1ce1..85ac66e 100644
--- a/board/st/stv0991/stv0991.c
+++ b/board/st/stv0991/stv0991.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <miiphy.h>
 #include <asm/arch/stv0991_periph.h>
 #include <asm/arch/stv0991_defs.h>
@@ -13,7 +14,6 @@
 #include <asm/arch/gpio.h>
 #include <netdev.h>
 #include <asm/io.h>
-#include <dm/platdata.h>
 #include <dm/platform_data/serial_pl01x.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -93,10 +93,12 @@ int dram_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
 }
 
 #ifdef CONFIG_CMD_NET
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
deleted file mode 100644
index 68443c9..0000000
--- a/board/sunxi/Kconfig
+++ /dev/null
@@ -1,639 +0,0 @@
-if ARCH_SUNXI
-
-# Note only one of these may be selected at a time! But hidden choices are
-# not supported by Kconfig
-config SUNXI_GEN_SUN4I
-	bool
-	---help---
-	Select this for sunxi SoCs which have resets and clocks set up
-	as the original A10 (mach-sun4i).
-
-config SUNXI_GEN_SUN6I
-	bool
-	---help---
-	Select this for sunxi SoCs which have sun6i like periphery, like
-	separate ahb reset control registers, custom pmic bus, new style
-	watchdog, etc.
-
-
-choice
-	prompt "Sunxi SoC Variant"
-	optional
-
-config MACH_SUN4I
-	bool "sun4i (Allwinner A10)"
-	select CPU_V7
-	select SUNXI_GEN_SUN4I
-	select SUPPORT_SPL
-
-config MACH_SUN5I
-	bool "sun5i (Allwinner A13)"
-	select CPU_V7
-	select SUNXI_GEN_SUN4I
-	select SUPPORT_SPL
-
-config MACH_SUN6I
-	bool "sun6i (Allwinner A31)"
-	select CPU_V7
-	select CPU_V7_HAS_NONSEC
-	select CPU_V7_HAS_VIRT
-	select ARCH_SUPPORT_PSCI
-	select SUNXI_GEN_SUN6I
-	select SUPPORT_SPL
-	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
-
-config MACH_SUN7I
-	bool "sun7i (Allwinner A20)"
-	select CPU_V7
-	select CPU_V7_HAS_NONSEC
-	select CPU_V7_HAS_VIRT
-	select ARCH_SUPPORT_PSCI
-	select SUNXI_GEN_SUN4I
-	select SUPPORT_SPL
-	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
-
-config MACH_SUN8I_A23
-	bool "sun8i (Allwinner A23)"
-	select CPU_V7
-	select CPU_V7_HAS_NONSEC
-	select CPU_V7_HAS_VIRT
-	select ARCH_SUPPORT_PSCI
-	select SUNXI_GEN_SUN6I
-	select SUPPORT_SPL
-	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
-
-config MACH_SUN8I_A33
-	bool "sun8i (Allwinner A33)"
-	select CPU_V7
-	select CPU_V7_HAS_NONSEC
-	select CPU_V7_HAS_VIRT
-	select ARCH_SUPPORT_PSCI
-	select SUNXI_GEN_SUN6I
-	select SUPPORT_SPL
-	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
-
-config MACH_SUN8I_A83T
-	bool "sun8i (Allwinner A83T)"
-	select CPU_V7
-	select SUNXI_GEN_SUN6I
-	select SUPPORT_SPL
-
-config MACH_SUN8I_H3
-	bool "sun8i (Allwinner H3)"
-	select CPU_V7
-	select CPU_V7_HAS_NONSEC
-	select CPU_V7_HAS_VIRT
-	select ARCH_SUPPORT_PSCI
-	select SUNXI_GEN_SUN6I
-	select SUPPORT_SPL
-	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
-
-config MACH_SUN9I
-	bool "sun9i (Allwinner A80)"
-	select CPU_V7
-	select SUNXI_GEN_SUN6I
-
-config MACH_SUN50I
-	bool "sun50i (Allwinner A64)"
-	select ARM64
-	select SUNXI_GEN_SUN6I
-
-endchoice
-
-# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
-config MACH_SUN8I
-	bool
-	default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
-
-config DRAM_TYPE
-	int "sunxi dram type"
-	depends on MACH_SUN8I_A83T
-	default 3
-	---help---
-	Set the dram type, 3: DDR3, 7: LPDDR3
-
-config DRAM_CLK
-	int "sunxi dram clock speed"
-	default 312 if MACH_SUN6I || MACH_SUN8I
-	default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
-	---help---
-	Set the dram clock speed, valid range 240 - 480, must be a multiple
-	of 24.
-
-if MACH_SUN5I || MACH_SUN7I
-config DRAM_MBUS_CLK
-	int "sunxi mbus clock speed"
-	default 300
-	---help---
-	Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
-
-endif
-
-config DRAM_ZQ
-	int "sunxi dram zq value"
-	default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
-	default 127 if MACH_SUN7I
-	---help---
-	Set the dram zq value.
-
-config DRAM_ODT_EN
-	bool "sunxi dram odt enable"
-	default n if !MACH_SUN8I_A23
-	default y if MACH_SUN8I_A23
-	---help---
-	Select this to enable dram odt (on die termination).
-
-if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
-config DRAM_EMR1
-	int "sunxi dram emr1 value"
-	default 0 if MACH_SUN4I
-	default 4 if MACH_SUN5I || MACH_SUN7I
-	---help---
-	Set the dram controller emr1 value.
-
-config DRAM_TPR3
-	hex "sunxi dram tpr3 value"
-	default 0
-	---help---
-	Set the dram controller tpr3 parameter. This parameter configures
-	the delay on the command lane and also phase shifts, which are
-	applied for sampling incoming read data. The default value 0
-	means that no phase/delay adjustments are necessary. Properly
-	configuring this parameter increases reliability at high DRAM
-	clock speeds.
-
-config DRAM_DQS_GATING_DELAY
-	hex "sunxi dram dqs_gating_delay value"
-	default 0
-	---help---
-	Set the dram controller dqs_gating_delay parmeter. Each byte
-	encodes the DQS gating delay for each byte lane. The delay
-	granularity is 1/4 cycle. For example, the value 0x05060606
-	means that the delay is 5 quarter-cycles for one lane (1.25
-	cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
-	The default value 0 means autodetection. The results of hardware
-	autodetection are not very reliable and depend on the chip
-	temperature (sometimes producing different results on cold start
-	and warm reboot). But the accuracy of hardware autodetection
-	is usually good enough, unless running at really high DRAM
-	clocks speeds (up to 600MHz). If unsure, keep as 0.
-
-choice
-	prompt "sunxi dram timings"
-	default DRAM_TIMINGS_VENDOR_MAGIC
-	---help---
-	Select the timings of the DDR3 chips.
-
-config DRAM_TIMINGS_VENDOR_MAGIC
-	bool "Magic vendor timings from Android"
-	---help---
-	The same DRAM timings as in the Allwinner boot0 bootloader.
-
-config DRAM_TIMINGS_DDR3_1066F_1333H
-	bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
-	---help---
-	Use the timings of the standard JEDEC DDR3-1066F speed bin for
-	DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
-	for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
-	used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
-	or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
-	that down binning to DDR3-1066F is supported (because DDR3-1066F
-	uses a bit faster timings than DDR3-1333H).
-
-config DRAM_TIMINGS_DDR3_800E_1066G_1333J
-	bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
-	---help---
-	Use the timings of the slowest possible JEDEC speed bin for the
-	selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
-	DDR3-800E, DDR3-1066G or DDR3-1333J.
-
-endchoice
-
-endif
-
-if MACH_SUN8I_A23
-config DRAM_ODT_CORRECTION
-	int "sunxi dram odt correction value"
-	default 0
-	---help---
-	Set the dram odt correction value (range -255 - 255). In allwinner
-	fex files, this option is found in bits 8-15 of the u32 odt_en variable
-	in the [dram] section. When bit 31 of the odt_en variable is set
-	then the correction is negative. Usually the value for this is 0.
-endif
-
-config SYS_CLK_FREQ
-	default 816000000 if MACH_SUN50I
-	default 912000000 if MACH_SUN7I
-	default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
-
-config SYS_CONFIG_NAME
-	default "sun4i" if MACH_SUN4I
-	default "sun5i" if MACH_SUN5I
-	default "sun6i" if MACH_SUN6I
-	default "sun7i" if MACH_SUN7I
-	default "sun8i" if MACH_SUN8I
-	default "sun9i" if MACH_SUN9I
-	default "sun50i" if MACH_SUN50I
-
-config SYS_BOARD
-	default "sunxi"
-
-config SYS_SOC
-	default "sunxi"
-
-config UART0_PORT_F
-	bool "UART0 on MicroSD breakout board"
-	default n
-	---help---
-	Repurpose the SD card slot for getting access to the UART0 serial
-	console. Primarily useful only for low level u-boot debugging on
-	tablets, where normal UART0 is difficult to access and requires
-	device disassembly and/or soldering. As the SD card can't be used
-	at the same time, the system can be only booted in the FEL mode.
-	Only enable this if you really know what you are doing.
-
-config OLD_SUNXI_KERNEL_COMPAT
-	bool "Enable workarounds for booting old kernels"
-	default n
-	---help---
-	Set this to enable various workarounds for old kernels, this results in
-	sub-optimal settings for newer kernels, only enable if needed.
-
-config MMC
-	depends on !UART0_PORT_F
-	default y if ARCH_SUNXI
-
-config MMC0_CD_PIN
-	string "Card detect pin for mmc0"
-	default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
-	default ""
-	---help---
-	Set the card detect pin for mmc0, leave empty to not use cd. This
-	takes a string in the format understood by sunxi_name_to_gpio, e.g.
-	PH1 for pin 1 of port H.
-
-config MMC1_CD_PIN
-	string "Card detect pin for mmc1"
-	default ""
-	---help---
-	See MMC0_CD_PIN help text.
-
-config MMC2_CD_PIN
-	string "Card detect pin for mmc2"
-	default ""
-	---help---
-	See MMC0_CD_PIN help text.
-
-config MMC3_CD_PIN
-	string "Card detect pin for mmc3"
-	default ""
-	---help---
-	See MMC0_CD_PIN help text.
-
-config MMC1_PINS
-	string "Pins for mmc1"
-	default ""
-	---help---
-	Set the pins used for mmc1, when applicable. This takes a string in the
-	format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
-
-config MMC2_PINS
-	string "Pins for mmc2"
-	default ""
-	---help---
-	See MMC1_PINS help text.
-
-config MMC3_PINS
-	string "Pins for mmc3"
-	default ""
-	---help---
-	See MMC1_PINS help text.
-
-config MMC_SUNXI_SLOT_EXTRA
-	int "mmc extra slot number"
-	default -1
-	---help---
-	sunxi builds always enable mmc0, some boards also have a second sdcard
-	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
-	support for this.
-
-config INITIAL_USB_SCAN_DELAY
-	int "delay initial usb scan by x ms to allow builtin devices to init"
-	default 0
-	---help---
-	Some boards have on board usb devices which need longer than the
-	USB spec's 1 second to connect from board powerup. Set this config
-	option to a non 0 value to add an extra delay before the first usb
-	bus scan.
-
-config USB0_VBUS_PIN
-	string "Vbus enable pin for usb0 (otg)"
-	default ""
-	---help---
-	Set the Vbus enable pin for usb0 (otg). This takes a string in the
-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config USB0_VBUS_DET
-	string "Vbus detect pin for usb0 (otg)"
-	default ""
-	---help---
-	Set the Vbus detect pin for usb0 (otg). This takes a string in the
-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config USB0_ID_DET
-	string "ID detect pin for usb0 (otg)"
-	default ""
-	---help---
-	Set the ID detect pin for usb0 (otg). This takes a string in the
-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config USB1_VBUS_PIN
-	string "Vbus enable pin for usb1 (ehci0)"
-	default "PH6" if MACH_SUN4I || MACH_SUN7I
-	default "PH27" if MACH_SUN6I
-	---help---
-	Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
-	a string in the format understood by sunxi_name_to_gpio, e.g.
-	PH1 for pin 1 of port H.
-
-config USB2_VBUS_PIN
-	string "Vbus enable pin for usb2 (ehci1)"
-	default "PH3" if MACH_SUN4I || MACH_SUN7I
-	default "PH24" if MACH_SUN6I
-	---help---
-	See USB1_VBUS_PIN help text.
-
-config USB3_VBUS_PIN
-	string "Vbus enable pin for usb3 (ehci2)"
-	default ""
-	---help---
-	See USB1_VBUS_PIN help text.
-
-config I2C0_ENABLE
-	bool "Enable I2C/TWI controller 0"
-	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
-	default n if MACH_SUN6I || MACH_SUN8I
-	select CMD_I2C
-	---help---
-	This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
-	its clock and setting up the bus. This is especially useful on devices
-	with slaves connected to the bus or with pins exposed through e.g. an
-	expansion port/header.
-
-config I2C1_ENABLE
-	bool "Enable I2C/TWI controller 1"
-	default n
-	select CMD_I2C
-	---help---
-	See I2C0_ENABLE help text.
-
-config I2C2_ENABLE
-	bool "Enable I2C/TWI controller 2"
-	default n
-	select CMD_I2C
-	---help---
-	See I2C0_ENABLE help text.
-
-if MACH_SUN6I || MACH_SUN7I
-config I2C3_ENABLE
-	bool "Enable I2C/TWI controller 3"
-	default n
-	select CMD_I2C
-	---help---
-	See I2C0_ENABLE help text.
-endif
-
-if SUNXI_GEN_SUN6I
-config R_I2C_ENABLE
-	bool "Enable the PRCM I2C/TWI controller"
-	# This is used for the pmic on H3
-	default y if SY8106A_POWER
-	select CMD_I2C
-	---help---
-	Set this to y to enable the I2C controller which is part of the PRCM.
-endif
-
-if MACH_SUN7I
-config I2C4_ENABLE
-	bool "Enable I2C/TWI controller 4"
-	default n
-	select CMD_I2C
-	---help---
-	See I2C0_ENABLE help text.
-endif
-
-config AXP_GPIO
-	bool "Enable support for gpio-s on axp PMICs"
-	default n
-	---help---
-	Say Y here to enable support for the gpio pins of the axp PMIC ICs.
-
-config VIDEO
-	bool "Enable graphical uboot console on HDMI, LCD or VGA"
-	depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
-	default y
-	---help---
-	Say Y here to add support for using a cfb console on the HDMI, LCD
-	or VGA output found on most sunxi devices. See doc/README.video for
-	info on how to select the video output and mode.
-
-config VIDEO_HDMI
-	bool "HDMI output support"
-	depends on VIDEO && !MACH_SUN8I
-	default y
-	---help---
-	Say Y here to add support for outputting video over HDMI.
-
-config VIDEO_VGA
-	bool "VGA output support"
-	depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
-	default n
-	---help---
-	Say Y here to add support for outputting video over VGA.
-
-config VIDEO_VGA_VIA_LCD
-	bool "VGA via LCD controller support"
-	depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
-	default n
-	---help---
-	Say Y here to add support for external DACs connected to the parallel
-	LCD interface driving a VGA connector, such as found on the
-	Olimex A13 boards.
-
-config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
-	bool "Force sync active high for VGA via LCD controller support"
-	depends on VIDEO_VGA_VIA_LCD
-	default n
-	---help---
-	Say Y here if you've a board which uses opendrain drivers for the vga
-	hsync and vsync signals. Opendrain drivers cannot generate steep enough
-	positive edges for a stable video output, so on boards with opendrain
-	drivers the sync signals must always be active high.
-
-config VIDEO_VGA_EXTERNAL_DAC_EN
-	string "LCD panel power enable pin"
-	depends on VIDEO_VGA_VIA_LCD
-	default ""
-	---help---
-	Set the enable pin for the external VGA DAC. This takes a string in the
-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config VIDEO_COMPOSITE
-	bool "Composite video output support"
-	depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
-	default n
-	---help---
-	Say Y here to add support for outputting composite video.
-
-config VIDEO_LCD_MODE
-	string "LCD panel timing details"
-	depends on VIDEO
-	default ""
-	---help---
-	LCD panel timing details string, leave empty if there is no LCD panel.
-	This is in drivers/video/videomodes.c: video_get_params() format, e.g.
-	x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
-	Also see: http://linux-sunxi.org/LCD
-
-config VIDEO_LCD_DCLK_PHASE
-	int "LCD panel display clock phase"
-	depends on VIDEO
-	default 1
-	---help---
-	Select LCD panel display clock phase shift, range 0-3.
-
-config VIDEO_LCD_POWER
-	string "LCD panel power enable pin"
-	depends on VIDEO
-	default ""
-	---help---
-	Set the power enable pin for the LCD panel. This takes a string in the
-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config VIDEO_LCD_RESET
-	string "LCD panel reset pin"
-	depends on VIDEO
-	default ""
-	---help---
-	Set the reset pin for the LCD panel. This takes a string in the format
-	understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config VIDEO_LCD_BL_EN
-	string "LCD panel backlight enable pin"
-	depends on VIDEO
-	default ""
-	---help---
-	Set the backlight enable pin for the LCD panel. This takes a string in the
-	the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
-	port H.
-
-config VIDEO_LCD_BL_PWM
-	string "LCD panel backlight pwm pin"
-	depends on VIDEO
-	default ""
-	---help---
-	Set the backlight pwm pin for the LCD panel. This takes a string in the
-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config VIDEO_LCD_BL_PWM_ACTIVE_LOW
-	bool "LCD panel backlight pwm is inverted"
-	depends on VIDEO
-	default y
-	---help---
-	Set this if the backlight pwm output is active low.
-
-config VIDEO_LCD_PANEL_I2C
-	bool "LCD panel needs to be configured via i2c"
-	depends on VIDEO
-	default n
-	select CMD_I2C
-	---help---
-	Say y here if the LCD panel needs to be configured via i2c. This
-	will add a bitbang i2c controller using gpios to talk to the LCD.
-
-config VIDEO_LCD_PANEL_I2C_SDA
-	string "LCD panel i2c interface SDA pin"
-	depends on VIDEO_LCD_PANEL_I2C
-	default "PG12"
-	---help---
-	Set the SDA pin for the LCD i2c interface. This takes a string in the
-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config VIDEO_LCD_PANEL_I2C_SCL
-	string "LCD panel i2c interface SCL pin"
-	depends on VIDEO_LCD_PANEL_I2C
-	default "PG10"
-	---help---
-	Set the SCL pin for the LCD i2c interface. This takes a string in the
-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-
-# Note only one of these may be selected at a time! But hidden choices are
-# not supported by Kconfig
-config VIDEO_LCD_IF_PARALLEL
-	bool
-
-config VIDEO_LCD_IF_LVDS
-	bool
-
-
-choice
-	prompt "LCD panel support"
-	depends on VIDEO
-	---help---
-	Select which type of LCD panel to support.
-
-config VIDEO_LCD_PANEL_PARALLEL
-	bool "Generic parallel interface LCD panel"
-	select VIDEO_LCD_IF_PARALLEL
-
-config VIDEO_LCD_PANEL_LVDS
-	bool "Generic lvds interface LCD panel"
-	select VIDEO_LCD_IF_LVDS
-
-config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
-	bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
-	select VIDEO_LCD_SSD2828
-	select VIDEO_LCD_IF_PARALLEL
-	---help---
-	7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
-
-config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
-	bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
-	select VIDEO_LCD_ANX9804
-	select VIDEO_LCD_IF_PARALLEL
-	select VIDEO_LCD_PANEL_I2C
-	---help---
-	Select this for eDP LCD panels with 4 lanes running at 1.62G,
-	connected via an ANX9804 bridge chip.
-
-config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
-	bool "Hitachi tx18d42vm LCD panel"
-	select VIDEO_LCD_HITACHI_TX18D42VM
-	select VIDEO_LCD_IF_LVDS
-	---help---
-	7.85" 1024x768 Hitachi tx18d42vm LCD panel support
-
-config VIDEO_LCD_TL059WV5C0
-	bool "tl059wv5c0 LCD panel"
-	select VIDEO_LCD_PANEL_I2C
-	select VIDEO_LCD_IF_PARALLEL
-	---help---
-	6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
-	Aigo M60/M608/M606 tablets.
-
-endchoice
-
-
-config GMAC_TX_DELAY
-	int "GMAC Transmit Clock Delay Chain"
-	default 0
-	---help---
-	Set the GMAC Transmit Clock Delay Chain value.
-
-config SPL_STACK_R_ADDR
-	default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
-	default 0x2fe00000 if MACH_SUN9I
-
-endif
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 6f13cf6..e9f3e35 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -72,7 +72,6 @@ F:	configs/q8_a33_tablet_1024x600_defconfig
 F:	include/configs/sun9i.h
 F:	configs/Merrii_A80_Optimus_defconfig
 F:	include/configs/sun50i.h
-F:	configs/pine64_plus_defconfig
 
 A20-OLIMEX-SOM-EVB BOARD
 M:	Marcus Cooper <codekipper@gmail.com>
@@ -94,6 +93,11 @@ M:	Stefan Mavrodiev <stefan.mavrodiev@gmail.com>
 S:	Maintained
 F:	configs/A33-OLinuXino_defconfig
 
+A80 OPTIMUS BOARD
+M:	Chen-Yu Tsai <wens@csie.org>
+S:	Maintained
+F:	configs/Merrii_A80_Optimus_defconfig
+
 AINOL AW1 BOARD
 M:	Paul Kocialkowski <contact@paulk.fr>
 S:	Maintained
@@ -104,6 +108,17 @@ M:	Paul Kocialkowski <contact@paulk.fr>
 S:	Maintained
 F:	configs/Ampe_A76_defconfig
 
+BANANAPI M2 ULTRA BOARD
+M:	Chen-Yu Tsai <wens@csie.org>
+S:	Maintained
+F:	configs/Bananapi_M2_Ultra_defconfig
+F:	arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
+
+BANANAPI M64
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/bananapi_m64_defconfig
+
 COLOMBUS BOARD
 M:	Maxime Ripard <maxime.ripard@free-electrons.com>
 S:	Maintained
@@ -117,6 +132,11 @@ F:	include/configs/sun7i.h
 F:	configs/Cubieboard2_defconfig
 F:	configs/Cubietruck_defconfig
 
+CUBIEBOARD4 BOARD
+M:	Chen-Yu Tsai <wens@csie.org>
+S:	Maintained
+F:	configs/Cubieboard4_defconfig
+
 CUBIETRUCK-PLUS BOARD
 M:	Chen-Yu Tsai <wens@csie.org>
 S:	Maintained
@@ -172,6 +192,11 @@ M:	Jelle de Jong <jelledejong@powercraft.nl>
 S:	Maintained
 F:	configs/Lamobo_R1_defconfig
 
+LICHEEPI-ZERO BOARD
+M:	Icenowy Zheng <icenowy@aosc.xyz>
+S:	Maintained
+F:	configs/LicheePi_Zero_defconfig
+
 LINKSPRITE-PCDUINO BOARD
 M:	Zoltan Herpai <wigyori@uid0.hu>
 S:	Maintained
@@ -217,6 +242,66 @@ M:	Siarhei Siamashka <siarhei.siamashka@gmail.com>
 S:	Maintained
 F:	configs/MSI_Primo81_defconfig
 
+NANOPI-M1 BOARD
+M:	Mylène Josserand <mylene.josserand@free-electrons.com>
+S:	Maintained
+F:	configs/nanopi_m1_defconfig
+
+NANOPI-M1 PLUS BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/nanopi_m1_plus_defconfig
+
+NANOPI-NEO BOARD
+M:	Jelle van der Waa <jelle@vdwaa.nl>
+S:	Maintained
+F:	configs/nanopi_neo_defconfig
+
+NANOPI-NEO2 BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/nanopi_neo2_defconfig
+
+NANOPI-NEO-AIR BOARD
+M:	Jelle van der Waa <jelle@vdwaa.nl>
+S:	Maintained
+F:	configs/nanopi_neo_air_defconfig
+
+NINTENDO NES CLASSIC EDITION BOARD
+M:	FUKAUMI Naoki <naobsd@gmail.com>
+S:	Maintained
+F:	configs/Nintendo_NES_Classic_Edition_defconfig
+
+ORANGEPI WIN/WIN PLUS BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/orangepi_win_defconfig
+
+ORANGEPI ZERO BOARD
+M:	Icenowy Zheng <icenowy@aosc.xyz>
+S:	Maintained
+F:	configs/orangepi_zero_defconfig
+
+ORANGEPI ZERO PLUS 2 BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/orangepi_zero_plus2_defconfig
+
+ORANGEPI PC 2 BOARD
+M:	Andre Przywara <andre.przywara@arm.com>
+S:	Maintained
+F:	configs/orangepi_pc2_defconfig
+
+ORANGEPI PRIME BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	configs/orangepi_prime_defconfig
+
+PINE64 BOARDS
+M:	Andre Przywara <andre.przywara@arm.com>
+S:	Maintained
+F:	configs/pine64_plus_defconfig
+
 R16 EVB PARROT BOARD
 M:	Quentin Schulz <quentin.schulz@free-electrons.com>
 S:	Maintained
@@ -234,11 +319,27 @@ S:	Maintained
 F:	configs/Sinlinx_SinA33_defconfig
 W:	http://linux-sunxi.org/Sinlinx_SinA33
 
+SINOVOIP BPI M2 PLUS H3 BOARD
+M:	Icenowy Zheng <icenowy@aosc.io>
+S:	Maintained
+F:	configs/Sinovoip_BPI_M2_Plus_defconfig
+
 SINOVOIP BPI M3 A83T BOARD
 M:	VishnuPatekar <vishnupatekar0510@gmail.com>
 S:	Maintained
 F:	configs/Sinovoip_BPI_M3_defconfig
 
+SOPINE BOARD
+M:	Icenowy Zheng <icenowy@aosc.io>
+S:	Maintained
+F:	configs/sopine_baseboard_defconfig
+
+SUNCHIP CX-A99 BOARD
+M:	Rask Ingemann Lambertsen <rask@formelder.dk>
+S:	Maintained
+F:	configs/Sunchip_CX-A99_defconfig
+W:	https://linux-sunxi.org/Sunchip_CX-A99
+
 WEXLER-TAB7200 BOARD
 M:	Aleksei Mamlin <mamlinav@gmail.com>
 S:	Maintained
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index 43766e0..f4411f0 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -10,7 +10,9 @@
 #
 obj-y	+= board.o
 obj-$(CONFIG_SUNXI_GMAC)	+= gmac.o
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_SUNXI_AHCI)	+= ahci.o
+endif
 obj-$(CONFIG_MACH_SUN4I)	+= dram_sun4i_auto.o
 obj-$(CONFIG_MACH_SUN5I)	+= dram_sun5i_auto.o
 obj-$(CONFIG_MACH_SUN7I)	+= dram_sun5i_auto.o
diff --git a/board/sunxi/README.nand b/board/sunxi/README.nand
new file mode 100644
index 0000000..a5d4ff0
--- /dev/null
+++ b/board/sunxi/README.nand
@@ -0,0 +1,54 @@
+Allwinner NAND flashing
+=======================
+
+A lot of Allwinner devices, especially the older ones (pre-H3 era),
+comes with a NAND. NANDs storages are a pretty weak choice when it
+comes to the reliability, and it comes with a number of flaws like
+read and write disturbs, data retention issues, bloks becoming
+unusable, etc.
+
+In order to mitigate that, various strategies have been found to be
+able to recover from those issues like ECC, hardware randomization,
+and of course, redundancy for the critical parts.
+
+This is obviously something that we will take into account when
+creating our images. However, the BROM will use a quite weird pattern
+when accessing the NAND, and will access only at most 4kB per page,
+which means that we also have to split that binary accross several
+pages.
+
+In order to accomodate that, we create a tool that will generate an
+SPL image that is ready to be programmed directly embedding the ECCs,
+randomized, and with the necessary bits needed to reduce the number of
+bitflips. The U-Boot build system, when configured for the NAND will
+also generate the image sunxi-spl-with-ecc.bin that will have been
+generated by that tool.
+
+In order to flash your U-Boot image onto a board, assuming that the
+board is in FEL mode, you'll need the sunxi-tools that you can find at
+this repository: https://github.com/linux-sunxi/sunxi-tools
+
+Then, you'll need to first load an SPL to initialise the RAM:
+sunxi-fel spl spl/sunxi-spl.bin
+
+Load the binaries we'll flash into RAM:
+sunxi-fel write 0x4a000000 u-boot-dtb.bin
+sunxi-fel write 0x43000000 spl/sunxi-spl-with-ecc.bin
+
+And execute U-Boot
+sunxi-fel exe 0x4a000000
+
+On your board, you'll now have all the needed binaries into RAM, so
+you only need to erase the NAND...
+
+nand erase.chip
+
+Then write the SPL and its backup:
+
+nand write.raw.noverify 0x43000000 0 40
+nand write.raw.noverify 0x43000000 0x400000 40
+
+And finally write the U-Boot binary:
+nand write 0x4a000000 0x800000 0xc0000
+
+You can now reboot and enjoy your NAND.
\ No newline at end of file
diff --git a/board/sunxi/README.pine64 b/board/sunxi/README.pine64
deleted file mode 100644
index 5553415..0000000
--- a/board/sunxi/README.pine64
+++ /dev/null
@@ -1,98 +0,0 @@
-Pine64 board README
-====================
-
-The Pine64(+) is a single board computer equipped with an AArch64 capable ARMv8
-compliant Allwinner A64 SoC.
-This chip has ARM Cortex A-53 cores and thus can run both in AArch32
-(compatible to 32-bit ARMv7) and AArch64 modes. Upon reset the SoC starts
-in AArch32 mode and executes 32-bit code from the Boot ROM (BROM).
-This has some implications on U-Boot.
-
-Quick start
-============
-- Get hold of a boot0.img file (see below for more details).
-- Get the boot0img tool source from the tools directory in [1] and compile
-  that on your host.
-- Build U-Boot:
-$ export CROSS_COMPILE=aarch64-linux-gnu-
-$ make pine64_plus_defconfig
-$ make
-- You also need a compiled ARM Trusted Firmware (ATF) binary. Checkout the
-  "allwinner" branch from the github repository [2] and build it:
-$ export CROSS_COMPILE=aarch64-linux-gnu-
-$ make PLAT=sun50iw1p1 DEBUG=1 bl31
-  The resulting binary is build/sun50iw1p1/debug/bl31.bin.
-
-Now put an empty (or disposable) micro SD card in your card reader and learn
-its device file name, replacing /dev/sd<x> below with the result (that could
-be /dev/mmcblk<x> as well):
-
-$ ./boot0img --device /dev/sd<x> -e -u u-boot.bin -B boot0.img \
-	-d trampoline64:0x44000 -s bl31.bin -a 0x44008 -p 100
-(either copying the respective files to the working directory or specifying
-the paths directly)
-
-This will create a new partition table (with a 100 MB FAT boot partition),
-copies boot0.img, ATF and U-Boot to the proper locations on the SD card and
-will fill in the magic Allwinner header to be recognized by boot0.
-Prefix the above call with "sudo" if you don't have write access to the
-uSD card. You can also use "-o output.img" instead of "--device /dev/sd<x>"
-to create an image file and "dd" that to the uSD card.
-Omitting the "-p" option will skip the partition table.
-
-Now put this uSD card in the board and power it on. You should be greeted by
-the U-Boot prompt.
-
-
-Main U-Boot
-============
-The main U-Boot proper is a real 64-bit ARMv8 port and runs entirely in the
-64-bit AArch64 mode. It can load any AArch64 code, EFI applications or arm64
-Linux kernel images (often named "Image") using the booti command.
-Launching 32-bit code and kernels is technically possible, though not without
-drawbacks (or hacks to avoid them) and currently not implemented.
-
-SPL support
-============
-The main task of the SPL support is to bring up the DRAM controller and make
-DRAM actually accessible. At the moment there is no documentation or source
-code available which would do this.
-There are currently two ways to overcome this situation: using a tainted 32-bit
-SPL (involving some hacks and resulting in a non-redistributable binary, thus
-not described here) or using the Allwinner boot0 blob.
-
-boot0 method
--------------
-boot0 is Allwiner's secondary program loader and it can be used as some kind
-of SPL replacement to get U-Boot up and running.
-The binary is a 32 KByte blob and contained on every Pine64 image distributed
-so far. It can be easily extracted from a micro SD card or an image file:
-# dd if=/dev/sd<x> of=boot0.bin bs=8k skip=1 count=4
-where /dev/sd<x> is the device name of the uSD card or the name of the image
-file. Apparently Allwinner allows re-distribution of this proprietary code
-as-is.
-For the time being this boot0 blob is the only redistributable way of making
-U-Boot work on the Pine64. Beside loading the various parts of the (original)
-firmware it also switches the core into AArch64 mode.
-The original boot0 code looks for U-Boot at a certain place on an uSD card
-(at 19096 KB), also it expects a header with magic bytes and a checksum.
-There is a tool called boot0img[1] which takes a boot0.bin image and a compiled
-U-Boot binary (plus other binaries) and will populate that header accordingly.
-To make space for the magic header, the pine64_plus_defconfig will make sure
-there is sufficient space at the beginning of the U-Boot binary.
-boot0img will also take care of putting the different binaries at the right
-places on the uSD card and works around unused, but mandatory parts by using
-trampoline code. See the output of "boot0img -h" for more information.
-boot0img can also patch boot0 to avoid loading U-Boot from 19MB, instead
-fetching it from just behind the boot0 binary (-B option).
-
-FEL boot
-=========
-FEL is the name of the Allwinner defined USB boot protocol built-in the
-mask ROM of most Allwinner SoCs. It allows to bootstrap a board solely
-by using the USB-OTG interface and a host port on another computer.
-Since FEL boot does not work with boot0, it requires the libdram hack, which
-is not described here.
-
-[1] https://github.com/apritzel/pine64/
-[2] https://github.com/apritzel/arm-trusted-firmware.git
diff --git a/board/sunxi/README.sunxi64 b/board/sunxi/README.sunxi64
new file mode 100644
index 0000000..c492f74
--- /dev/null
+++ b/board/sunxi/README.sunxi64
@@ -0,0 +1,165 @@
+Allwinner 64-bit boards README
+==============================
+
+Newer Allwinner SoCs feature ARMv8 cores (ARM Cortex-A53) with support for
+both the 64-bit AArch64 mode and the ARMv7 compatible 32-bit AArch32 mode.
+Examples are the Allwinner A64 (used for instance on the Pine64 board) or
+the Allwinner H5 SoC (as used on the OrangePi PC 2).
+These SoCs are wired to start in AArch32 mode on reset and execute 32-bit
+code from the Boot ROM (BROM). As this has some implications on U-Boot, this
+file describes how to make full use of the 64-bit capabilities.
+
+Quick Start / Overview
+======================
+- Build the ARM Trusted Firmware binary (see "ARM Trusted Firmware (ATF)" below)
+- Build U-Boot (see "SPL/U-Boot" below)
+- Transfer to an uSD card (see "microSD card" below)
+- Boot and enjoy!
+
+Building the firmware
+=====================
+
+The Allwinner A64/H5 firmware consists of three parts: U-Boot's SPL, an
+ARM Trusted Firmware (ATF) build and the U-Boot proper.
+The SPL will load both ATF and U-Boot proper along with the right device
+tree blob (.dtb) and will pass execution to ATF (in EL3), which in turn will
+drop into the U-Boot proper (in EL2).
+As the ATF binary will become part of the U-Boot image file, you will need
+to build it first.
+
+ ARM Trusted Firmware (ATF)
+----------------------------
+Checkout the "allwinner" branch from the github repository [1] and build it:
+$ export CROSS_COMPILE=aarch64-linux-gnu-
+$ make PLAT=sun50iw1p1 DEBUG=1 bl31
+The resulting binary is build/sun50iw1p1/debug/bl31.bin. Either put the
+location of this file into the BL31 environment variable or copy this to
+the root of your U-Boot build directory (or create a symbolic link).
+$ export BL31=/src/arm-trusted-firmware/build/sun50iw1p1/debug/bl31.bin
+  (adjust the actual path accordingly)
+
+ SPL/U-Boot
+------------
+Both U-Boot proper and the SPL are using the 64-bit mode. As the boot ROM
+enters the SPL still in AArch32 secure SVC mode, there is some shim code to
+enter AArch64 very early. The rest of the SPL runs in AArch64 EL3.
+U-Boot proper runs in EL2 and can load any AArch64 code (using the "go"
+command), EFI applications (with "bootefi") or arm64 Linux kernel images
+(often named "Image"), using the "booti" command.
+
+$ make clean
+$ export CROSS_COMPILE=aarch64-linux-gnu-
+$ make pine64_plus_defconfig
+$ make
+
+This will build the SPL in spl/sunxi-spl.bin and a FIT image called u-boot.itb,
+which contains the rest of the firmware.
+
+
+Boot process
+============
+The on-die BROM code will try several methods to load and execute the firmware.
+On a typical board like the Pine64 this will result in the following boot order:
+
+1) Reading 32KB from sector 16 (@8K) of the microSD card to SRAM A1. If the
+BROM finds the magic "eGON" header in the first bytes, it will execute that
+code. If not (no SD card at all or invalid magic), it will:
+2) Try to read 32KB from sector 16 (@8K) of memory connected to the MMC2
+controller, typically an on-board eMMC chip. If there is no eMMC or it does
+not contain a valid boot header, it will:
+3) Initialize the SPI0 controller and try to access a NOR flash connected to
+it (using the CS0 pin). If a flash chip is found, the BROM will load the
+first 32KB (from offset 0) into SRAM A1. Now it checks for the magic eGON
+header and checksum and will execute the code upon finding it. If not, it will:
+4) Initialize the USB OTG controller and will wait for a host to connect to
+it, speaking the Allwinner proprietary (but deciphered) "FEL" USB protocol.
+
+
+To boot the Pine64 board, you can use U-Boot and any of the described methods.
+
+FEL boot (USB OTG)
+------------------
+FEL is the name of the Allwinner defined USB boot protocol built in the
+mask ROM of most Allwinner SoCs. It allows to bootstrap a board solely
+by using the USB-OTG interface and a host port on another computer.
+As the FEL mode is controlled by the boot ROM, it expects to be running in
+AArch32. For now the AArch64 SPL cannot properly return into FEL mode, so the
+feature is disabled in the configuration at the moment.
+
+microSD card
+------------
+Transfer the SPL and the U-Boot FIT image directly to an uSD card:
+# dd if=spl/sunxi-spl.bin of=/dev/sdx bs=8k seek=1
+# dd if=u-boot.itb of=/dev/sdx bs=8k seek=5
+# sync
+(replace /dev/sdx with you SD card device file name, which could be
+/dev/mmcblk[x] as well).
+
+Alternatively you can concatenate the SPL and the U-Boot FIT image into a
+single file and transfer that instead:
+$ cat spl/sunxi-spl.bin u-boot.itb > u-boot-sunxi-with-spl.bin
+# dd if=u-boot-sunxi-with-spl.bin of=/dev/sdx bs=8k seek=1
+
+You can partition the microSD card, but leave the first MB unallocated (most
+partitioning tools will do this anyway).
+
+NOR flash
+---------
+Some boards (like the SoPine, Pinebook or the OrangePi PC2) come with a
+soldered SPI NOR flash chip. On other boards like the Pine64 such a chip
+can be connected to the SPI0/CS0 pins on the PI-2 headers.
+Create the SPL and FIT image like described above for the SD card.
+Now connect either an "A to A" USB cable to the upper USB port on the Pine64
+or get an adaptor and use a regular A-microB cable connected to it. Other
+boards often have a proper micro-B USB socket connected to the USB OTB port.
+Remove a microSD card from the slot and power on the board.
+On your host computer download and build the sunxi-tools package[2], then
+use "sunxi-fel" to access the board:
+$ ./sunxi-fel ver -v -p
+This should give you an output starting with: AWUSBFEX soc=00001689(A64) ...
+Now use the sunxi-fel tool to write to the NOR flash:
+$ ./sunxi-fel spiflash-write 0 spl/sunxi-spl.bin
+$ ./sunxi-fel spiflash-write 32768 u-boot.itb
+Now boot the board without an SD card inserted and you should see the
+U-Boot prompt on the serial console.
+
+(Legacy) boot0 method
+---------------------
+boot0 is Allwiner's secondary program loader and it can be used as some kind
+of SPL replacement to get U-Boot up and running from an microSD card.
+For some time using boot0 was the only option to get the Pine64 booted.
+With working DRAM init code in U-Boot's SPL this is no longer necessary,
+but this method is described here for the sake of completeness.
+Please note that this method works only with the boot0 files shipped with
+A64 based boards, the H5 uses an incompatible layout which is not supported
+by this method.
+
+The boot0 binary is a 32 KByte blob and contained in the official Pine64 images
+distributed by Pine64 or Allwinner. It can be easily extracted from a micro
+SD card or an image file:
+# dd if=/dev/sd<x> of=boot0.bin bs=8k skip=1 count=4
+where /dev/sd<x> is the device name of the uSD card or the name of the image
+file. Apparently Allwinner allows re-distribution of this proprietary code
+"as-is".
+This boot0 blob takes care of DRAM initialisation and loads the remaining
+firmware parts, then switches the core into AArch64 mode.
+The original boot0 code looks for U-Boot at a certain place on an uSD card
+(at 19096 KB), also it expects a header with magic bytes and a checksum.
+There is a tool called boot0img[3] which takes a boot0.bin image and a compiled
+U-Boot binary (plus other binaries) and will populate that header accordingly.
+To make space for the magic header, the pine64_plus_defconfig will make sure
+there is sufficient space at the beginning of the U-Boot binary.
+boot0img will also take care of putting the different binaries at the right
+places on the uSD card and works around unused, but mandatory parts by using
+trampoline code. See the output of "boot0img -h" for more information.
+boot0img can also patch boot0 to avoid loading U-Boot from 19MB, instead
+fetching it from just behind the boot0 binary (-B option).
+$ ./boot0img -o firmware.img -B boot0.img -u u-boot-dtb.bin -e -s bl31.bin \
+-a 0x44008 -d trampoline64:0x44000
+Then write this image to a microSD card, replacing /dev/sdx with the right
+device file (see above):
+$ dd if=firmware.img of=/dev/sdx bs=8k seek=1
+
+[1] https://github.com/apritzel/arm-trusted-firmware.git
+[2] git://github.com/linux-sunxi/sunxi-tools.git
+[3] https://github.com/apritzel/pine64/
diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c
index 522e54a..a79b80c 100644
--- a/board/sunxi/ahci.c
+++ b/board/sunxi/ahci.c
@@ -1,5 +1,6 @@
 #include <common.h>
 #include <ahci.h>
+#include <dm.h>
 #include <scsi.h>
 #include <errno.h>
 #include <asm/io.h>
@@ -13,9 +14,8 @@
 /* This magic PHY initialisation was taken from the Allwinner releases
  * and Linux driver, but is completely undocumented.
  */
-static int sunxi_ahci_phy_init(u32 base)
+static int sunxi_ahci_phy_init(u8 *reg_base)
 {
-	u8 *reg_base = (u8 *)base;
 	u32 reg_val;
 	int timeout;
 
@@ -70,10 +70,65 @@ static int sunxi_ahci_phy_init(u32 base)
 	return 0;
 }
 
+#ifndef CONFIG_DM_SCSI
 void scsi_init(void)
 {
-	if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0)
+	if (sunxi_ahci_phy_init((u8 *)SUNXI_SATA_BASE) < 0)
 		return;
 
 	ahci_init((void __iomem *)SUNXI_SATA_BASE);
 }
+#else
+static int sunxi_sata_probe(struct udevice *dev)
+{
+	ulong base;
+	u8 *reg;
+	int ret;
+
+	base = dev_read_addr(dev);
+	if (base == FDT_ADDR_T_NONE) {
+		debug("%s: Failed to find address (err=%d\n)", __func__, ret);
+		return -EINVAL;
+	}
+	reg = (u8 *)base;
+	ret = sunxi_ahci_phy_init(reg);
+	if (ret) {
+		debug("%s: Failed to init phy (err=%d\n)", __func__, ret);
+		return ret;
+	}
+	ret = ahci_probe_scsi(dev, base);
+	if (ret) {
+		debug("%s: Failed to probe (err=%d\n)", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int sunxi_sata_bind(struct udevice *dev)
+{
+	struct udevice *scsi_dev;
+	int ret;
+
+	ret = ahci_bind_scsi(dev, &scsi_dev);
+	if (ret) {
+		debug("%s: Failed to bind (err=%d\n)", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id sunxi_ahci_ids[] = {
+	{ .compatible = "allwinner,sun4i-a10-ahci" },
+	{ }
+};
+
+U_BOOT_DRIVER(ahci_sunxi_drv) = {
+	.name		= "ahci_sunxi",
+	.id		= UCLASS_AHCI,
+	.of_match	= sunxi_ahci_ids,
+	.bind		= sunxi_sata_bind,
+	.probe		= sunxi_sata_probe,
+};
+#endif
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 6281c9d..800f412 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -33,6 +33,7 @@
 #include <nand.h>
 #include <net.h>
 #include <sy8106a.h>
+#include <asm/setup.h>
 
 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
@@ -77,10 +78,104 @@ static int soft_i2c_board_init(void) { return 0; }
 
 DECLARE_GLOBAL_DATA_PTR;
 
+void i2c_init_board(void)
+{
+#ifdef CONFIG_I2C0_ENABLE
+#if defined(CONFIG_MACH_SUN4I) || \
+    defined(CONFIG_MACH_SUN5I) || \
+    defined(CONFIG_MACH_SUN7I) || \
+    defined(CONFIG_MACH_SUN8I_R40)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
+	clock_twi_onoff(0, 1);
+#elif defined(CONFIG_MACH_SUN6I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
+	clock_twi_onoff(0, 1);
+#elif defined(CONFIG_MACH_SUN8I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
+	clock_twi_onoff(0, 1);
+#endif
+#endif
+
+#ifdef CONFIG_I2C1_ENABLE
+#if defined(CONFIG_MACH_SUN4I) || \
+    defined(CONFIG_MACH_SUN7I) || \
+    defined(CONFIG_MACH_SUN8I_R40)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
+	clock_twi_onoff(1, 1);
+#elif defined(CONFIG_MACH_SUN5I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
+	clock_twi_onoff(1, 1);
+#elif defined(CONFIG_MACH_SUN6I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
+	clock_twi_onoff(1, 1);
+#elif defined(CONFIG_MACH_SUN8I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
+	clock_twi_onoff(1, 1);
+#endif
+#endif
+
+#ifdef CONFIG_I2C2_ENABLE
+#if defined(CONFIG_MACH_SUN4I) || \
+    defined(CONFIG_MACH_SUN7I) || \
+    defined(CONFIG_MACH_SUN8I_R40)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
+	clock_twi_onoff(2, 1);
+#elif defined(CONFIG_MACH_SUN5I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
+	clock_twi_onoff(2, 1);
+#elif defined(CONFIG_MACH_SUN6I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
+	clock_twi_onoff(2, 1);
+#elif defined(CONFIG_MACH_SUN8I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
+	sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
+	clock_twi_onoff(2, 1);
+#endif
+#endif
+
+#ifdef CONFIG_I2C3_ENABLE
+#if defined(CONFIG_MACH_SUN6I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
+	clock_twi_onoff(3, 1);
+#elif defined(CONFIG_MACH_SUN7I) || \
+      defined(CONFIG_MACH_SUN8I_R40)
+	sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
+	sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
+	clock_twi_onoff(3, 1);
+#endif
+#endif
+
+#ifdef CONFIG_I2C4_ENABLE
+#if defined(CONFIG_MACH_SUN7I) || \
+    defined(CONFIG_MACH_SUN8I_R40)
+	sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
+	sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
+	clock_twi_onoff(4, 1);
+#endif
+#endif
+
+#ifdef CONFIG_R_I2C_ENABLE
+	clock_twi_onoff(5, 1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
+#endif
+}
+
 /* add board specific code here */
 int board_init(void)
 {
-	__maybe_unused int id_pfr1, ret;
+	__maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
 
 	gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
 
@@ -100,14 +195,14 @@ int board_init(void)
 		 * we avoid the risk of writing to it.
 		 */
 		asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
-		if (freq != CONFIG_TIMER_CLK_FREQ) {
+		if (freq != COUNTER_FREQUENCY) {
 			debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
-			      freq, CONFIG_TIMER_CLK_FREQ);
+			      freq, COUNTER_FREQUENCY);
 #ifdef CONFIG_NON_SECURE
 			printf("arch timer frequency is wrong, but cannot adjust it\n");
 #else
 			asm volatile("mcr p15, 0, %0, c14, c0, 0"
-				     : : "r"(CONFIG_TIMER_CLK_FREQ));
+				     : : "r"(COUNTER_FREQUENCY));
 #endif
 		}
 	}
@@ -118,12 +213,22 @@ int board_init(void)
 		return ret;
 
 #ifdef CONFIG_SATAPWR
-	gpio_request(CONFIG_SATAPWR, "satapwr");
-	gpio_direction_output(CONFIG_SATAPWR, 1);
+	satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
+	gpio_request(satapwr_pin, "satapwr");
+	gpio_direction_output(satapwr_pin, 1);
 #endif
 #ifdef CONFIG_MACPWR
-	gpio_request(CONFIG_MACPWR, "macpwr");
-	gpio_direction_output(CONFIG_MACPWR, 1);
+	macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
+	gpio_request(macpwr_pin, "macpwr");
+	gpio_direction_output(macpwr_pin, 1);
+#endif
+
+#ifdef CONFIG_DM_I2C
+	/*
+	 * Temporary workaround for enabling I2C clocks until proper sunxi DM
+	 * clk, reset and pinctrl drivers land.
+	 */
+	i2c_init_board();
 #endif
 
 	/* Uses dm gpio code so do this here and not in i2c_init_board() */
@@ -180,7 +285,7 @@ void board_nand_init(void)
 }
 #endif
 
-#ifdef CONFIG_GENERIC_MMC
+#ifdef CONFIG_MMC
 static void mmc_pinmux_setup(int sdc)
 {
 	unsigned int pin;
@@ -199,7 +304,8 @@ static void mmc_pinmux_setup(int sdc)
 	case 1:
 		pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
 
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
+    defined(CONFIG_MACH_SUN8I_R40)
 		if (pins == SUNXI_GPIO_H) {
 			/* SDC1: PH22-PH-27 */
 			for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
@@ -294,6 +400,17 @@ static void mmc_pinmux_setup(int sdc)
 			sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
 		}
+#elif defined(CONFIG_MACH_SUN8I_R40)
+		/* SDC2: PC6-PC15, PC24 */
+		for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
+			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(pin, 2);
+		}
+
+		sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
+		sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+		sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
 		/* SDC2: PC5-PC6, PC8-PC16 */
 		for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
@@ -307,13 +424,21 @@ static void mmc_pinmux_setup(int sdc)
 			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
 			sunxi_gpio_set_drv(pin, 2);
 		}
+#elif defined(CONFIG_MACH_SUN9I)
+		/* SDC2: PC6-PC16 */
+		for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
+			sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+			sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+			sunxi_gpio_set_drv(pin, 2);
+		}
 #endif
 		break;
 
 	case 3:
 		pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
 
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
+    defined(CONFIG_MACH_SUN8I_R40)
 		/* SDC3: PI4-PI9 */
 		for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
 			sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
@@ -384,96 +509,10 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-void i2c_init_board(void)
-{
-#ifdef CONFIG_I2C0_ENABLE
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
-	clock_twi_onoff(0, 1);
-#elif defined(CONFIG_MACH_SUN6I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
-	sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
-	clock_twi_onoff(0, 1);
-#elif defined(CONFIG_MACH_SUN8I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
-	sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
-	clock_twi_onoff(0, 1);
-#endif
-#endif
-
-#ifdef CONFIG_I2C1_ENABLE
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
-	clock_twi_onoff(1, 1);
-#elif defined(CONFIG_MACH_SUN5I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
-	clock_twi_onoff(1, 1);
-#elif defined(CONFIG_MACH_SUN6I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
-	sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
-	clock_twi_onoff(1, 1);
-#elif defined(CONFIG_MACH_SUN8I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
-	sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
-	clock_twi_onoff(1, 1);
-#endif
-#endif
-
-#ifdef CONFIG_I2C2_ENABLE
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
-	clock_twi_onoff(2, 1);
-#elif defined(CONFIG_MACH_SUN5I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
-	clock_twi_onoff(2, 1);
-#elif defined(CONFIG_MACH_SUN6I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
-	sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
-	clock_twi_onoff(2, 1);
-#elif defined(CONFIG_MACH_SUN8I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
-	sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
-	clock_twi_onoff(2, 1);
-#endif
-#endif
-
-#ifdef CONFIG_I2C3_ENABLE
-#if defined(CONFIG_MACH_SUN6I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
-	sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
-	clock_twi_onoff(3, 1);
-#elif defined(CONFIG_MACH_SUN7I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
-	sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
-	clock_twi_onoff(3, 1);
-#endif
-#endif
-
-#ifdef CONFIG_I2C4_ENABLE
-#if defined(CONFIG_MACH_SUN7I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
-	sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
-	clock_twi_onoff(4, 1);
-#endif
-#endif
-
-#ifdef CONFIG_R_I2C_ENABLE
-	clock_twi_onoff(5, 1);
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
-#endif
-}
-
 #ifdef CONFIG_SPL_BUILD
 void sunxi_board_init(void)
 {
 	int power_failed = 0;
-	unsigned long ramsize;
 
 #ifdef CONFIG_SY8106A_POWER
 	power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
@@ -534,9 +573,9 @@ void sunxi_board_init(void)
 #endif
 #endif
 	printf("DRAM:");
-	ramsize = sunxi_dram_init();
-	printf(" %d MiB\n", (int)(ramsize >> 20));
-	if (!ramsize)
+	gd->ram_size = sunxi_dram_init();
+	printf(" %d MiB\n", (int)(gd->ram_size >> 20));
+	if (!gd->ram_size)
 		hang();
 
 	/*
@@ -719,3 +758,32 @@ int ft_board_setup(void *blob, bd_t *bd)
 #endif
 	return 0;
 }
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
+	const char *cmp_str = (void *)(ulong)SPL_ADDR;
+
+	/* Check if there is a DT name stored in the SPL header and use that. */
+	if (spl->dt_name_offset) {
+		cmp_str += spl->dt_name_offset;
+	} else {
+#ifdef CONFIG_DEFAULT_DEVICE_TREE
+		cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
+#else
+		return 0;
+#endif
+	};
+
+/* Differentiate the two Pine64 board DTs by their DRAM size. */
+	if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
+		if ((gd->ram_size > 512 * 1024 * 1024))
+			return !strstr(name, "plus");
+		else
+			return !!strstr(name, "plus");
+	} else {
+		return strcmp(name, cmp_str);
+	}
+}
+#endif
diff --git a/board/sunxi/mksunxi_fit_atf.sh b/board/sunxi/mksunxi_fit_atf.sh
new file mode 100755
index 0000000..b1d6e0e
--- /dev/null
+++ b/board/sunxi/mksunxi_fit_atf.sh
@@ -0,0 +1,81 @@
+#!/bin/sh
+#
+# script to generate FIT image source for 64-bit sunxi boards with
+# ARM Trusted Firmware and multiple device trees (given on the command line)
+#
+# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
+
+[ -z "$BL31" ] && BL31="bl31.bin"
+
+if [ ! -f $BL31 ]; then
+	echo "WARNING: BL31 file $BL31 NOT found, resulting binary is non-functional" >&2
+	echo "Please read the section on ARM Trusted Firmware (ATF) in board/sunxi/README.sunxi64" >&2
+	BL31=/dev/null
+fi
+
+cat << __HEADER_EOF
+/dts-v1/;
+
+/ {
+	description = "Configuration to load ATF before U-Boot";
+	#address-cells = <1>;
+
+	images {
+		uboot@1 {
+			description = "U-Boot (64-bit)";
+			data = /incbin/("u-boot-nodtb.bin");
+			type = "standalone";
+			arch = "arm64";
+			compression = "none";
+			load = <0x4a000000>;
+		};
+		atf@1 {
+			description = "ARM Trusted Firmware";
+			data = /incbin/("$BL31");
+			type = "firmware";
+			arch = "arm64";
+			compression = "none";
+			load = <0x44000>;
+			entry = <0x44000>;
+		};
+__HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+	cat << __FDT_IMAGE_EOF
+		fdt@$cnt {
+			description = "$(basename $dtname .dtb)";
+			data = /incbin/("$dtname");
+			type = "flat_dt";
+			compression = "none";
+		};
+__FDT_IMAGE_EOF
+	cnt=$((cnt+1))
+done
+
+cat << __CONF_HEADER_EOF
+	};
+	configurations {
+		default = "config@1";
+
+__CONF_HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+	cat << __CONF_SECTION_EOF
+		config@$cnt {
+			description = "$(basename $dtname .dtb)";
+			firmware = "uboot@1";
+			loadables = "atf@1";
+			fdt = "fdt@$cnt";
+		};
+__CONF_SECTION_EOF
+	cnt=$((cnt+1))
+done
+
+cat << __ITS_EOF
+	};
+};
+__ITS_EOF
diff --git a/board/synopsys/axs10x/Kconfig b/board/synopsys/axs10x/Kconfig
index c60b6a2..dd1305a 100644
--- a/board/synopsys/axs10x/Kconfig
+++ b/board/synopsys/axs10x/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_AXS10X
+if TARGET_AXS101 || TARGET_AXS103
 
 config SYS_BOARD
 	default "axs10x"
diff --git a/board/synopsys/axs10x/axs10x.c b/board/synopsys/axs10x/axs10x.c
index a5e774b..e6b69da 100644
--- a/board/synopsys/axs10x/axs10x.c
+++ b/board/synopsys/axs10x/axs10x.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <dwmmc.h>
 #include <malloc.h>
+#include <asm/arcregs.h>
 #include "axs10x.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -61,16 +62,32 @@ void smp_kick_all_cpus(void)
 {
 /* CPU start CREG */
 #define AXC003_CREG_CPU_START	0xF0001400
-
 /* Bits positions in CPU start CREG */
 #define BITS_START	0
-#define BITS_POLARITY	8
+#define BITS_START_MODE	4
 #define BITS_CORE_SEL	9
-#define BITS_MULTICORE	12
 
-#define CMD	(1 << BITS_MULTICORE) | (1 << BITS_CORE_SEL) | \
-		(1 << BITS_POLARITY) | (1 << BITS_START)
+/*
+ * In axs103 v1.1 START bits semantics has changed quite a bit.
+ * We used to have a generic START bit for all cores selected by CORE_SEL mask.
+ * But now we don't touch CORE_SEL at all because we have a dedicated START bit
+ * for each core:
+ *     bit 0: Core 0 (master)
+ *     bit 1: Core 1 (slave)
+ */
+#define BITS_START_CORE1	1
+
+#define ARCVER_HS38_3_0	0x53
+
+	int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
+	int cmd = readl((void __iomem *)AXC003_CREG_CPU_START);
 
-	writel(CMD, (void __iomem *)AXC003_CREG_CPU_START);
+	if (core_family < ARCVER_HS38_3_0) {
+		cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START);
+		cmd &= ~(1 << BITS_START_MODE);
+	} else {
+		cmd |= (1 << BITS_START_CORE1);
+	}
+	writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);
 }
 #endif
diff --git a/board/synopsys/hsdk/Kconfig b/board/synopsys/hsdk/Kconfig
new file mode 100644
index 0000000..e8c00a6
--- /dev/null
+++ b/board/synopsys/hsdk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_HSDK
+
+config SYS_BOARD
+	default "hsdk"
+
+config SYS_VENDOR
+	default "synopsys"
+
+config SYS_CONFIG_NAME
+	default "hsdk"
+
+endif
diff --git a/board/synopsys/hsdk/MAINTAINERS b/board/synopsys/hsdk/MAINTAINERS
new file mode 100644
index 0000000..d034bc4
--- /dev/null
+++ b/board/synopsys/hsdk/MAINTAINERS
@@ -0,0 +1,5 @@
+AXS10X BOARD
+M:	Alexey Brodkin <abrodkin@synopsys.com>
+S:	Maintained
+F:	board/synopsys/hsdk/
+F:	configs/hsdk_defconfig
diff --git a/board/synopsys/hsdk/Makefile b/board/synopsys/hsdk/Makefile
new file mode 100644
index 0000000..d84dd03
--- /dev/null
+++ b/board/synopsys/hsdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= hsdk.o
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
new file mode 100644
index 0000000..7b56255
--- /dev/null
+++ b/board/synopsys/hsdk/hsdk.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dwmmc.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define	CREG_BASE	(ARC_PERIPHERAL_BASE + 0x1000)
+#define	CREG_PAE	(CREG_BASE + 0x180)
+#define	CREG_PAE_UPDATE	(CREG_BASE + 0x194)
+#define	CREG_CPU_START	(CREG_BASE + 0x400)
+
+int board_early_init_f(void)
+{
+	/* In current chip PAE support for DMA is broken, disabling it. */
+	writel(0, (void __iomem *) CREG_PAE);
+
+	/* Really apply settings made above */
+	writel(1, (void __iomem *) CREG_PAE_UPDATE);
+
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	struct dwmci_host *host = NULL;
+
+	host = malloc(sizeof(struct dwmci_host));
+	if (!host) {
+		printf("dwmci_host malloc fail!\n");
+		return 1;
+	}
+
+	memset(host, 0, sizeof(struct dwmci_host));
+	host->name = "Synopsys Mobile storage";
+	host->ioaddr = (void *)ARC_DWMMC_BASE;
+	host->buswidth = 4;
+	host->dev_index = 0;
+	host->bus_hz = 100000000;
+
+	add_dwmci(host, host->bus_hz / 2, 400000);
+
+	return 0;
+}
+
+#define RESET_VECTOR_ADDR	0x0
+
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+	/* All cores have reset vector pointing to 0 */
+	writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
+
+	/* Make sure other cores see written value in memory */
+	flush_dcache_all();
+}
+
+void smp_kick_all_cpus(void)
+{
+#define BITS_START_CORE1	1
+#define BITS_START_CORE2	2
+#define BITS_START_CORE3	3
+
+	int cmd = readl((void __iomem *)CREG_CPU_START);
+
+	cmd |= (1 << BITS_START_CORE1) |
+	       (1 << BITS_START_CORE2) |
+	       (1 << BITS_START_CORE3);
+	writel(cmd, (void __iomem *)CREG_CPU_START);
+}
diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c
index 42b7c23..3bfe511 100644
--- a/board/sysam/amcore/amcore.c
+++ b/board/sysam/amcore/amcore.c
@@ -1,7 +1,7 @@
 /*
  * Board functions for Sysam AMCORE (MCF5307 based) board
  *
- * (C) Copyright 2015  Angelo Dureghello <angelo@sysam.it>
+ * (C) Copyright 2016  Angelo Dureghello <angelo@sysam.it>
  *
  * SPDX-License-Identifier:     GPL-2.0+
  *
@@ -11,6 +11,10 @@
 #include <common.h>
 #include <asm/immap.h>
 #include <asm/io.h>
+#include <dm.h>
+#include <dm/platform_data/serial_coldfire.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 void init_lcd(void)
 {
@@ -36,7 +40,7 @@ int checkboard(void)
 }
 
 /*
- * in initdram we are here executing from flash
+ * in dram_init we are here executing from flash
  * case 1:
  * is with no ACR/flash cache enabled
  * nop = 40ns (scope measured)
@@ -47,7 +51,7 @@ void fudelay(int usec)
 		asm volatile ("nop");
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	u32 dramsize, RC;
 
@@ -91,11 +95,25 @@ phys_size_t initdram(int board_type)
 	out_be32((u32 *)0x00000004, 0xbeaddeed);
 	/* issue AUTOREFRESH */
 	out_be32(&dc->dacr0, 0x0000b304);
-	/* let refresh occour */
+	/* let refresh occur */
 	fudelay(1);
 
 	out_be32(&dc->dacr0, 0x0000b344);
 	out_be32((u32 *)0x00000c00, 0xbeaddeed);
 
-	return get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
+	gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+
+	return 0;
 }
+
+static struct coldfire_serial_platdata mcf5307_serial_plat = {
+	.base = CONFIG_SYS_UART_BASE,
+	.port = 0,
+	.baudrate = CONFIG_BAUDRATE,
+};
+
+U_BOOT_DEVICE(coldfire_serial) = {
+	.name = "serial_coldfire",
+	.platdata = &mcf5307_serial_plat,
+};
diff --git a/board/t3corp/Kconfig b/board/t3corp/Kconfig
deleted file mode 100644
index 82ed4c9..0000000
--- a/board/t3corp/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_T3CORP
-
-config SYS_BOARD
-	default "t3corp"
-
-config SYS_CONFIG_NAME
-	default "t3corp"
-
-endif
diff --git a/board/t3corp/MAINTAINERS b/board/t3corp/MAINTAINERS
deleted file mode 100644
index eaf28c4..0000000
--- a/board/t3corp/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-T3CORP BOARD
-M:	Stefan Roese <sr@denx.de>
-S:	Maintained
-F:	board/t3corp/
-F:	include/configs/t3corp.h
-F:	configs/t3corp_defconfig
diff --git a/board/t3corp/Makefile b/board/t3corp/Makefile
deleted file mode 100644
index 928d895..0000000
--- a/board/t3corp/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2010
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= t3corp.o
-obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
-extra-y += init.o
diff --git a/board/t3corp/chip_config.c b/board/t3corp/chip_config.c
deleted file mode 100644
index 3a6c514..0000000
--- a/board/t3corp/chip_config.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx_config.h>
-
-struct ppc4xx_config ppc4xx_config_val[] = {
-	{
-		"600-67", "CPU: 600 PLB: 200 OPB:  67 EBC:  67",
-		{
-			0x86, 0x80, 0xce, 0x1f, 0x7d, 0x80, 0x00, 0xe0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"600-100", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"667", "CPU: 667 PLB: 166 OPB:  83 EBC:  83",
-		{
-			0x06, 0x80, 0xbb, 0x14, 0x99, 0x82, 0x00, 0xa0,
-			0x40, 0x88, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"800", "CPU: 800 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"1000", "CPU:1000 PLB: 200 OPB: 100 EBC: 100",
-		{
-			0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-	{
-		"1066", "CPU:1066 PLB: 266 OPB:  88 EBC:  88",
-		{
-			0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0,
-			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-		}
-	},
-};
-
-int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);
diff --git a/board/t3corp/config.mk b/board/t3corp/config.mk
deleted file mode 100644
index f7ac755..0000000
--- a/board/t3corp/config.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2010
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/t3corp/init.S b/board/t3corp/init.S
deleted file mode 100644
index 7ae9c43..0000000
--- a/board/t3corp/init.S
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-/*
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- */
-	.section .bootpg,"ax"
-	.globl tlbtab
-
-tlbtab:
-	tlbtab_start
-
-	/*
-	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
-	 * use the speed up boot process. It is patched after relocation to
-	 * enable SA_I
-	 */
-	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M,
-		 CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G)
-
-	/*
-	 * TLB entries for SDRAM are not needed on this platform.
-	 * They are dynamically generated in the DDR(2) detection
-	 * routine.
-	 */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
-	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0,
-		 AC_RWX | SA_G)
-#endif
-
-	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xc,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xc,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xd,
-		 AC_RW | SA_IG)
-
-	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xd,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xd,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xd,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xd,
-		 AC_RW | SA_IG)
-
-	/* PCIe UTL register */
-	tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG)
-
-	/* TLB-entry for FPGA(s) */
-	tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M,
-		 CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4,
-		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4,
-		 AC_RW | SA_IG)
-
-	/* TLB-entry for OCM */
-	tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
-		 AC_RWX | SA_I)
-
-	/* TLB-entry for Local Configuration registers => peripherals */
-	tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M,
-		 CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
-
-	tlbtab_end
diff --git a/board/t3corp/t3corp.c b/board/t3corp/t3corp.c
deleted file mode 100644
index 586c6f9..0000000
--- a/board/t3corp/t3corp.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc440.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <mtd/cfi_flash.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <asm/4xx_pcie.h>
-#include <asm/ppc4xx-gpio.h>
-
-int board_early_init_f(void)
-{
-	/*
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all */
-	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
-	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC1ER, 0x00000000);	/* disable all */
-	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC1PR, 0x7fffffff);	/* per ref-board manual */
-	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC2ER, 0x00000000);	/* disable all */
-	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC3ER, 0x00000000);	/* disable all */
-	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
-	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
-	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
-
-	/*
-	 * Configure PFC (Pin Function Control) registers
-	 * enable GPIO 49-63
-	 * UART0: 4 pins
-	 */
-	mtsdr(SDR0_PFC0, 0x00007fff);
-	mtsdr(SDR0_PFC1, 0x00040000);
-
-	/* Enable PCI host functionality in SDR0_PCI0 */
-	mtsdr(SDR0_PCI0, 0xe0000000);
-
-	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */
-
-	/* Setup PLB4-AHB bridge based on the system address map */
-	mtdcr(AHB_TOP, 0x8000004B);
-	mtdcr(AHB_BOT, 0x8000004B);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf("Board: T3CORP");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	/*
-	 * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
-	 * boot EBC mapping only supports a maximum of 16MBytes
-	 * (4.ff00.0000 - 4.ffff.ffff).
-	 * To solve this problem, the flash has to get remapped to another
-	 * EBC address which accepts bigger regions:
-	 *
-	 * 0xfn00.0000 -> 4.cn00.0000
-	 */
-
-	/* Remap the NOR flash to 0xcn00.0000 ... 0xcfff.ffff */
-	mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | EBC_BXCR_BS_64MB |
-	      EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
-
-	/* Remove TLB entry of boot EBC mapping */
-	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
-
-	/* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
-	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
-		    CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
-
-	/*
-	 * Now accessing of the whole 64Mbytes of NOR flash at virtual address
-	 * 0xfc00.0000 is possible
-	 */
-
-	/*
-	 * Clear potential errors resulting from auto-calibration.
-	 * If not done, then we could get an interrupt later on when
-	 * exceptions are enabled.
-	 */
-	set_mcsr(get_mcsr());
-
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	u32 sdr0_srst1 = 0;
-	u32 eth_cfg;
-
-	/*
-	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
-	 * This is board specific, so let's do it here.
-	 */
-	mfsdr(SDR0_ETH_CFG, eth_cfg);
-	/* disable SGMII mode */
-	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
-		     SDR0_ETH_CFG_SGMII1_ENABLE |
-		     SDR0_ETH_CFG_SGMII0_ENABLE);
-	/* Set the for 2 RGMII mode */
-	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
-	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
-	eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
-	mtsdr(SDR0_ETH_CFG, eth_cfg);
-
-	/*
-	 * The AHB Bridge core is held in reset after power-on or reset
-	 * so enable it now
-	 */
-	mfsdr(SDR0_SRST1, sdr0_srst1);
-	sdr0_srst1 &= ~SDR0_SRST1_AHB;
-	mtsdr(SDR0_SRST1, sdr0_srst1);
-
-	return 0;
-}
-
-int board_pcie_last(void)
-{
-	/*
-	 * Only PCIe0 for now, PCIe1 hangs on this board
-	 */
-	return 0;
-}
-
-/*
- * Board specific WRDTR and CLKTR values used by the auto-
- * calibration code (4xx_ibm_ddr2_autocalib.c).
- */
-static struct sdram_timing board_scan_options[] = {
-	{1, 2},
-	{-1, -1}
-};
-
-struct sdram_timing *ddr_scan_option(struct sdram_timing *default_val)
-{
-	return board_scan_options;
-}
-
-/*
- * Accessor functions replacing the "weak" functions in
- * drivers/mtd/cfi_flash.c
- *
- * The NOR flash devices "behind" the FPGA's (Xilinx DS617)
- * can only be read correctly in 16bit mode. We need to emulate
- * 8bit and 32bit reads here in the board specific code.
- */
-u8 flash_read8(void *addr)
-{
-	u16 val = __raw_readw((void *)((u32)addr & ~1));
-
-	if ((u32)addr & 1)
-		return val;
-
-	return val >> 8;
-}
-
-u32 flash_read32(void *addr)
-{
-	return (__raw_readw(addr) << 16) | __raw_readw((void *)((u32)addr + 2));
-}
-
-void flash_cmd_reset(flash_info_t *info)
-{
-	/*
-	 * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
-	 * needs the Spansion type reset commands. The other flash chip
-	 * is located behind a FPGA (Xilinx DS617) and needs the Intel type
-	 * reset command.
-	 */
-	if (info->start[0] == CONFIG_SYS_FLASH_BASE)
-		flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
-	else
-		flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
-}
diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index f784459..7a6657f 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -8,13 +8,13 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
@@ -359,6 +359,39 @@ static void setup_display(void)
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
 
+static int ar8035_phy_fixup(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* To enable AR8035 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	ar8035_phy_fixup(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
 int board_eth_init(bd_t *bis)
 {
 	setup_iomux_enet();
diff --git a/board/tcm-bf518/Kconfig b/board/tcm-bf518/Kconfig
deleted file mode 100644
index 558c2fe..0000000
--- a/board/tcm-bf518/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_TCM_BF518
-
-config SYS_BOARD
-	default "tcm-bf518"
-
-config SYS_CONFIG_NAME
-	default "tcm-bf518"
-
-endif
diff --git a/board/tcm-bf518/MAINTAINERS b/board/tcm-bf518/MAINTAINERS
deleted file mode 100644
index 1690122..0000000
--- a/board/tcm-bf518/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TCM-BF518 BOARD
-#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S:	Orphan (since 2014-03)
-F:	board/tcm-bf518/
-F:	include/configs/tcm-bf518.h
-F:	configs/tcm-bf518_defconfig
diff --git a/board/tcm-bf518/Makefile b/board/tcm-bf518/Makefile
deleted file mode 100644
index 1ce8f64..0000000
--- a/board/tcm-bf518/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= tcm-bf518.o
diff --git a/board/tcm-bf518/tcm-bf518.c b/board/tcm-bf518/tcm-bf518.c
deleted file mode 100644
index 7923eae..0000000
--- a/board/tcm-bf518/tcm-bf518.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/otp.h>
-#include <asm/sdh.h>
-
-int checkboard(void)
-{
-	printf("Board: Bluetechnix TCM-BF518 board\n");
-	printf("       Support: http://www.bluetechnix.com/\n");
-	printf("                http://blackfin.uclinux.org/\n");
-	return 0;
-}
-
-#if defined(CONFIG_BFIN_MAC)
-int board_eth_init(bd_t *bis)
-{
-	return bfin_EMAC_initialize(bis);
-}
-#endif
-
-#ifdef CONFIG_BFIN_SDH
-int board_mmc_init(bd_t *bis)
-{
-	return bfin_mmc_init(bis);
-}
-#endif
diff --git a/board/tcm-bf537/Kconfig b/board/tcm-bf537/Kconfig
deleted file mode 100644
index e0127c6..0000000
--- a/board/tcm-bf537/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_TCM_BF537
-
-config SYS_BOARD
-	default "tcm-bf537"
-
-config SYS_CONFIG_NAME
-	default "tcm-bf537"
-
-endif
diff --git a/board/tcm-bf537/MAINTAINERS b/board/tcm-bf537/MAINTAINERS
deleted file mode 100644
index 1cd4845..0000000
--- a/board/tcm-bf537/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-TCM-BF537 BOARD
-#M:	Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
-S:	Orphan (since 2014-03)
-F:	board/tcm-bf537/
-F:	include/configs/tcm-bf537.h
-F:	configs/tcm-bf537_defconfig
diff --git a/board/tcm-bf537/Makefile b/board/tcm-bf537/Makefile
deleted file mode 100644
index 0fe25e8..0000000
--- a/board/tcm-bf537/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= tcm-bf537.o gpio_cfi_flash.o
diff --git a/board/tcm-bf537/config.mk b/board/tcm-bf537/config.mk
deleted file mode 100644
index 7f9138b..0000000
--- a/board/tcm-bf537/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
diff --git a/board/tcm-bf537/gpio_cfi_flash.c b/board/tcm-bf537/gpio_cfi_flash.c
deleted file mode 100644
index c4fef9f..0000000
--- a/board/tcm-bf537/gpio_cfi_flash.c
+++ /dev/null
@@ -1,3 +0,0 @@
-#define GPIO_PIN_1 GPIO_PF4
-#define GPIO_PIN_2 GPIO_PF5
-#include "../cm-bf537e/gpio_cfi_flash.c"
diff --git a/board/tcm-bf537/tcm-bf537.c b/board/tcm-bf537/tcm-bf537.c
deleted file mode 100644
index 19df51a..0000000
--- a/board/tcm-bf537/tcm-bf537.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * U-Boot - main board file
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/blackfin.h>
-#include "../cm-bf537e/gpio_cfi_flash.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard(void)
-{
-	printf("Board: Bluetechnix TCM-BF537 board\n");
-	printf("       Support: http://www.bluetechnix.at/\n");
-	return 0;
-}
-
-#ifndef CONFIG_BFIN_MAC
-# define bfin_EMAC_initialize(x) 1
-#endif
-#ifndef CONFIG_SMC911X
-# define smc911x_initialize(n, x) 1
-#endif
-int board_eth_init(bd_t *bis)
-{
-	/* return ok if at least 1 eth device works */
-	return bfin_EMAC_initialize(bis) &
-	       smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-
-int misc_init_r(void)
-{
-	gpio_cfi_flash_init();
-
-	return 0;
-}
diff --git a/board/technexion/pico-imx6ul/imximage.cfg b/board/technexion/pico-imx6ul/imximage.cfg
index 9145b44..c753a71 100644
--- a/board/technexion/pico-imx6ul/imximage.cfg
+++ b/board/technexion/pico-imx6ul/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/technexion/pico-imx6ul/pico-imx6ul.c b/board/technexion/pico-imx6ul/pico-imx6ul.c
index 49aeb80..39f7e01 100644
--- a/board/technexion/pico-imx6ul/pico-imx6ul.c
+++ b/board/technexion/pico-imx6ul/pico-imx6ul.c
@@ -13,8 +13,8 @@
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/io.h>
 #include <common.h>
 #include <miiphy.h>
diff --git a/board/technexion/pico-imx7d/Kconfig b/board/technexion/pico-imx7d/Kconfig
new file mode 100644
index 0000000..f4ae18c
--- /dev/null
+++ b/board/technexion/pico-imx7d/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PICO_IMX7D
+
+config SYS_BOARD
+	default "pico-imx7d"
+
+config SYS_VENDOR
+	default "technexion"
+
+config SYS_SOC
+	default "mx7"
+
+config SYS_CONFIG_NAME
+	default "pico-imx7d"
+
+endif
diff --git a/board/technexion/pico-imx7d/MAINTAINERS b/board/technexion/pico-imx7d/MAINTAINERS
new file mode 100644
index 0000000..3ab1aa6
--- /dev/null
+++ b/board/technexion/pico-imx7d/MAINTAINERS
@@ -0,0 +1,6 @@
+Technexion PICO-IMX7D board
+M:	Vanessa Maegima <vanessa.maegima@nxp.com>
+S:	Maintained
+F:	board/technexion/pico-imx7d/
+F:	include/configs/pico-imx7d.h
+F:	configs/pico-imx7d_defconfig
diff --git a/board/technexion/pico-imx7d/Makefile b/board/technexion/pico-imx7d/Makefile
new file mode 100644
index 0000000..42cca47
--- /dev/null
+++ b/board/technexion/pico-imx7d/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2017 NXP Semiconductors
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := pico-imx7d.o
diff --git a/board/technexion/pico-imx7d/README b/board/technexion/pico-imx7d/README
new file mode 100644
index 0000000..a2805ee
--- /dev/null
+++ b/board/technexion/pico-imx7d/README
@@ -0,0 +1,49 @@
+How to update U-Boot on pico-imx7d board
+----------------------------------------
+
+Required software on the host PC:
+
+- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader
+
+Build U-Boot for pico:
+
+$ make mrproper
+$ make pico-imx7d_defconfig
+$ make
+
+This generates the U-Boot binary called u-boot.imx.
+
+Put pico board in USB download mode (refer to the PICO-iMX7D Quick Start Guide
+page 3)
+
+Connect a USB to serial adapter between the host PC and pico.
+
+Connect a USB cable between the OTG pico port and the host PC.
+
+Open a terminal program such as minicom.
+
+Copy u-boot.imx to the imx_usb_loader folder.
+
+Load u-boot.imx via USB:
+
+$ sudo ./imx_usb u-boot.imx
+
+Then U-Boot starts and its messages appear in the console program.
+
+Use the default environment variables:
+
+=> env default -f -a
+=> saveenv
+
+Run the UMS command:
+=> ums 0 mmc 0
+
+Transfer u-boot.imx to be flashed into the eMMC:
+
+$ sudo dd if=u-boot.imx of=/dev/sdX bs=1K seek=1; sync
+
+Remove power from the pico board.
+
+Put pico board into normal boot mode.
+
+Power up the board and the new updated U-Boot should boot from eMMC.
diff --git a/board/technexion/pico-imx7d/imximage.cfg b/board/technexion/pico-imx7d/imximage.cfg
new file mode 100644
index 0000000..202956a
--- /dev/null
+++ b/board/technexion/pico-imx7d/imximage.cfg
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2017 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+BOOT_FROM	sd
+
+/* Secure boot support */
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+/* Clear then set bit30 to ensure exit from DDR retention */
+DATA 4 0x30360388 0x40000000
+DATA 4 0x30360384 0x40000000
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x01040001
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0064 0x00400046
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00020083
+DATA 4 0x307a00d4 0x00690000
+DATA 4 0x307a00dc 0x09300004
+DATA 4 0x307a00e0 0x04080000
+DATA 4 0x307a00e4 0x00100004
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x09081109
+DATA 4 0x307a0104 0x0007020d
+DATA 4 0x307a0108 0x03040407
+DATA 4 0x307a010c 0x00002006
+DATA 4 0x307a0110 0x04020205
+DATA 4 0x307a0114 0x03030202
+DATA 4 0x307a0120 0x00000803
+DATA 4 0x307a0180 0x00800020
+DATA 4 0x307a0184 0x02000100
+DATA 4 0x307a0190 0x02098204
+DATA 4 0x307a0194 0x00030303
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00080808
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x07070707
+DATA 4 0x307a0218 0x0f070707
+DATA 4 0x307a0240 0x06000604
+DATA 4 0x307a0244 0x00000001
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17420f40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790010 0x00060807
+DATA 4 0x307900b0 0x1010007e
+DATA 4 0x3079009c 0x00000b24
+DATA 4 0x30790020 0x08080808
+DATA 4 0x30790030 0x08080808
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e407304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+DATA 4 0x30790018 0x0000000f
+
+CHECK_BITS_SET 4 0x307a0004 0x1
diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c
new file mode 100644
index 0000000..b4c9be7
--- /dev/null
+++ b/board/technexion/pico-imx7d/pico-imx7d.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright (C) 2017 NXP Semiconductors
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <usb.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../../freescale/common/pfuze.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
+	PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
+#define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
+
+#define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
+
+#ifdef CONFIG_SYS_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C4 for PMIC */
+static struct i2c_pads_info i2c_pad_info4 = {
+	.scl = {
+		.i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC,
+		.gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC,
+		.gp = IMX_GPIO_NR(6, 16),
+	},
+	.sda = {
+		.i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC,
+		.gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC,
+		.gp = IMX_GPIO_NR(6, 17),
+	},
+};
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC	3
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg, rev_id;
+
+	ret = power_pfuze3000_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	p = pmic_get("PFUZE3000");
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
+	pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
+	printf("PMIC:  PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
+
+	/* disable Low Power Mode during standby mode */
+	pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
+	reg |= 0x1;
+	pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
+
+	/* SW1A/1B mode set to APS/APS */
+	reg = 0x8;
+	pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
+	pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
+
+	/* SW1A/1B standby voltage set to 1.025V */
+	reg = 0xd;
+	pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
+	pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
+
+	/* decrease SW1B normal voltage to 0.975V */
+	pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
+	reg &= ~0x1f;
+	reg |= PFUZE3000_SW1AB_SETP(975);
+	pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
+
+	return 0;
+}
+#endif
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart5_pads[] = {
+	MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
+	MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+#ifdef CONFIG_FEC_MXC
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
+	MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
+	MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_SD3_STROBE__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#define FEC1_RST_GPIO	IMX_GPIO_NR(6, 11)
+
+static void setup_iomux_fec(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+
+	gpio_direction_output(FEC1_RST_GPIO, 0);
+	udelay(500);
+	gpio_set_value(FEC1_RST_GPIO, 1);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	setup_iomux_fec();
+
+	return fecmxc_initialize_multi(bis, 0,
+		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+			(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
+			IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
+
+	return set_clk_enet(ENET_125MHz);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* To enable AR8035 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe7;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	/* Assume uSDHC3 emmc is always present */
+	return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(
+			usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+#ifdef CONFIG_SYS_I2C_MXC
+	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	/*
+	 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
+	 * since we use PMIC_PWRON to reset the board.
+	 */
+	clrsetbits_le16(&wdog->wcr, 0, 0x10);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: i.MX7D PICOSOM\n");
+
+	return 0;
+}
+
+int board_usb_phy_mode(int port)
+{
+	return USB_INIT_DEVICE;
+}
diff --git a/board/technexion/tao3530/tao3530.c b/board/technexion/tao3530/tao3530.c
index d51b5d9..c5966e3 100644
--- a/board/technexion/tao3530/tao3530.c
+++ b/board/technexion/tao3530/tao3530.c
@@ -179,7 +179,7 @@ void set_muxconf_regs(void)
 #endif
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	omap_mmc_init(0, 0, 0, -1, -1);
@@ -188,14 +188,14 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-#if defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 void board_mmc_power_init(void)
 {
 	twl4030_power_mmc_init(0);
 }
 #endif
 
-#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
 /* Call usb_stop() before starting the kernel */
 void show_boot_progress(int val)
 {
@@ -219,4 +219,4 @@ int ehci_hcd_stop(int index)
 {
 	return omap_ehci_hcd_stop();
 }
-#endif /* CONFIG_USB_EHCI */
+#endif /* CONFIG_USB_EHCI_HCD */
diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c
index 48d207f..25aeebc 100644
--- a/board/technexion/twister/twister.c
+++ b/board/technexion/twister/twister.c
@@ -19,7 +19,7 @@
 #include <spl.h>
 #include <mmc.h>
 #include <asm/gpio.h>
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
 #include <usb.h>
 #include <asm/ehci-omap.h>
 #endif
@@ -46,7 +46,7 @@ static const u32 gpmc_XR16L2751[] = {
 	XR16L2751_GPMC_CONFIG6,
 };
 
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
 static struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
 	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
@@ -130,7 +130,7 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
-#if defined(CONFIG_OMAP_HSMMC) && \
+#if defined(CONFIG_MMC_OMAP_HS) && \
 	!defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
@@ -140,7 +140,7 @@ int board_mmc_init(bd_t *bis)
 
 #ifdef CONFIG_SPL_OS_BOOT
 /*
- * Do board specific preperation before SPL
+ * Do board specific preparation before SPL
  * Linux boot
  */
 void spl_board_prepare_for_linux(void)
diff --git a/board/technologic/ts4600/Kconfig b/board/technologic/ts4600/Kconfig
new file mode 100644
index 0000000..d0dc2e1
--- /dev/null
+++ b/board/technologic/ts4600/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TS4600
+
+config SYS_BOARD
+	default "ts4600"
+
+config SYS_VENDOR
+	default "technologic"
+
+config SYS_SOC
+	default "mxs"
+
+config SYS_CONFIG_NAME
+	default "ts4600"
+
+endif
diff --git a/board/technologic/ts4600/MAINTAINERS b/board/technologic/ts4600/MAINTAINERS
new file mode 100644
index 0000000..6f683b5
--- /dev/null
+++ b/board/technologic/ts4600/MAINTAINERS
@@ -0,0 +1,6 @@
+TS4600 BOARD
+M:	Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
+S:	Maintained
+F:	board/technologic/ts4600/
+F:	include/configs/ts4600.h
+F:	configs/ts4600_defconfig
diff --git a/board/technologic/ts4600/Makefile b/board/technologic/ts4600/Makefile
new file mode 100644
index 0000000..faa2970
--- /dev/null
+++ b/board/technologic/ts4600/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2016 Savoir-faire Linux
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifndef	CONFIG_SPL_BUILD
+obj-y	:= ts4600.o
+else
+obj-y	:= iomux.o
+endif
diff --git a/board/technologic/ts4600/iomux.c b/board/technologic/ts4600/iomux.c
new file mode 100644
index 0000000..1398bbe
--- /dev/null
+++ b/board/technologic/ts4600/iomux.c
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2016 Savoir-faire Linux Inc.
+ *
+ * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
+ *
+ * Based on work from TS7680 code by:
+ *   Kris Bahnsen <kris@embeddedarm.com>
+ *   Mark Featherston <mark@embeddedarm.com>
+ *   https://github.com/embeddedarm/u-boot/tree/master/board/technologic/ts7680
+ *
+ * Derived from MX28EVK code by
+ *   Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+	/* DUART */
+	MX28_PAD_PWM0__DUART_RX,
+	MX28_PAD_PWM1__DUART_TX,
+
+	/* MMC0 */
+	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_SCK__SSP0_SCK |
+		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+
+	/* MMC0 slot power enable */
+	MX28_PAD_PWM3__GPIO_3_28 |
+		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+
+	/* EMI */
+	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+	/* I2C */
+	MX28_PAD_I2C0_SCL__I2C0_SCL,
+	MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+};
+
+#define HW_DRAM_CTL29	(0x74 >> 2)
+#define CS_MAP		0xf
+#define COLUMN_SIZE	0x2
+#define ADDR_PINS	0x1
+#define APREBIT		0xa
+
+#define HW_DRAM_CTL29_CONFIG	(CS_MAP << 24 | COLUMN_SIZE << 16 | \
+					ADDR_PINS << 8 | APREBIT)
+
+#define HW_DRAM_CTL39	(0x9c >> 2)
+#define TFAW		0xb
+#define TDLL		0xc8
+
+#define HW_DRAM_CTL39_CONFIG	(TFAW << 24 | TDLL)
+
+#define HW_DRAM_CTL41	(0xa4 >> 2)
+#define TPDEX		0x2
+#define TRCD_INT	0x4
+#define TRC		0xd
+
+#define HW_DRAM_CTL41_CONFIG	(TPDEX << 24 | TRCD_INT << 8 | TRC)
+
+#define HW_DRAM_CTL42	(0xa8 >> 2)
+#define TRAS_MAX	0x36a6
+#define TRAS_MIN	0xa
+
+#define HW_DRAM_CTL42_CONFIG  (TRAS_MAX << 8 | TRAS_MIN)
+
+#define HW_DRAM_CTL43	(0xac >> 2)
+#define TRP		0x4
+#define TRFC		0x27
+#define TREF		0x2a0
+
+#define HW_DRAM_CTL43_CONFIG (TRP << 24 | TRFC << 16 | TREF)
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+	dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
+	dram_vals[HW_DRAM_CTL39] = HW_DRAM_CTL39_CONFIG;
+	dram_vals[HW_DRAM_CTL41] = HW_DRAM_CTL41_CONFIG;
+	dram_vals[HW_DRAM_CTL42] = HW_DRAM_CTL42_CONFIG;
+	dram_vals[HW_DRAM_CTL43] = HW_DRAM_CTL43_CONFIG;
+}
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/board/technologic/ts4600/ts4600.c b/board/technologic/ts4600/ts4600.c
new file mode 100644
index 0000000..70dfead
--- /dev/null
+++ b/board/technologic/ts4600/ts4600.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2016 Savoir-faire Linux Inc.
+ *
+ * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
+ *
+ * Based on work from TS7680 code by:
+ *   Kris Bahnsen <kris@embeddedarm.com>
+ *   Mark Featherston <mark@embeddedarm.com>
+ *   https://github.com/embeddedarm/u-boot/tree/master/board/technologic/ts7680
+ *
+ * Derived from MX28EVK code by
+ *   Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/* IO0 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK0, 480000);
+	/* IO1 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+	/* SSP0 clocks at 96MHz */
+	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return mxs_dram_init();
+}
+
+int board_init(void)
+{
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_MMC
+static int ts4600_mmc_cd(int id)
+{
+	return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	mxs_iomux_setup_pad(MX28_PAD_PWM3__GPIO_3_28);
+
+	/* Power-on SD */
+	gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 1);
+	udelay(1000);
+	gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
+
+	/* SD card */
+	ret = mxsmmc_initialize(bis, 0, NULL, ts4600_mmc_cd);
+	if(ret != 0) {
+		printf("SD controller initialized with %d\n", ret);
+	}
+
+	return ret;
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: TS4600\n");
+
+	return 0;
+}
diff --git a/board/technologic/ts4800/ts4800.c b/board/technologic/ts4800/ts4800.c
index 6ef15e1..94251c6 100644
--- a/board/technologic/ts4800/ts4800.c
+++ b/board/technologic/ts4800/ts4800.c
@@ -12,11 +12,11 @@
 #include <asm/gpio.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux-mx51.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
-#include <asm/imx-common/mx5_video.h>
+#include <asm/mach-imx/mx5_video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <mc13892.h>
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c
index c2de1fe..6e73ae1 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -23,7 +23,7 @@
 #include <i2c.h>
 #include <spartan3.h>
 #include <asm/gpio.h>
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
 #include <usb.h>
 #include <asm/ehci-omap.h>
 #endif
@@ -95,7 +95,7 @@ static const u32 gpmc_fpga[] = {
 	FPGA_GPMC_CONFIG6,
 };
 
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
 static struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
 	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
@@ -291,7 +291,7 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
-#if defined(CONFIG_OMAP_HSMMC) && \
+#if defined(CONFIG_MMC_OMAP_HS) && \
 	!defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
diff --git a/board/terasic/de0-nano-soc/MAINTAINERS b/board/terasic/de0-nano-soc/MAINTAINERS
index 351c456..7f4cf1e 100644
--- a/board/terasic/de0-nano-soc/MAINTAINERS
+++ b/board/terasic/de0-nano-soc/MAINTAINERS
@@ -1,5 +1,5 @@
 SOCFPGA ATLAS BOARD
-M:	Dinh Nguyen <dinguyen@opensource.altera.com>
+M:	Dinh Nguyen <dinguyen@kernel.org>
 S:	Maintained
 F:	include/configs/socfpga_de0_nano_soc.h
 F:	configs/socfpga_de0_nano_soc_defconfig
diff --git a/board/terasic/de0-nano-soc/qts/sdram_config.h b/board/terasic/de0-nano-soc/qts/sdram_config.h
index 7084797..d96b28a 100644
--- a/board/terasic/de0-nano-soc/qts/sdram_config.h
+++ b/board/terasic/de0-nano-soc/qts/sdram_config.h
@@ -42,6 +42,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
diff --git a/board/terasic/de1-soc/MAINTAINERS b/board/terasic/de1-soc/MAINTAINERS
new file mode 100644
index 0000000..bd7a8d5
--- /dev/null
+++ b/board/terasic/de1-soc/MAINTAINERS
@@ -0,0 +1,5 @@
+DE1-SoC BOARD
+M:	Anatolij Gustschin <agust@denx.de>
+S:	Maintained
+F:	include/configs/socfpga_de1_soc.h
+F:	configs/socfpga_de1_soc_defconfig
diff --git a/board/terasic/de1-soc/Makefile b/board/terasic/de1-soc/Makefile
new file mode 100644
index 0000000..86f9b78
--- /dev/null
+++ b/board/terasic/de1-soc/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= socfpga.o
diff --git a/board/terasic/de1-soc/qts/iocsr_config.h b/board/terasic/de1-soc/qts/iocsr_config.h
new file mode 100644
index 0000000..3ca1968
--- /dev/null
+++ b/board/terasic/de1-soc/qts/iocsr_config.h
@@ -0,0 +1,660 @@
+/*
+ * Altera SoCFPGA IOCSR configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00000000,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x00020000,
+	0x06018000,
+	0x06000000,
+	0x00000018,
+	0x00006018,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x00100000,
+	0x300C0000,
+	0x300000C0,
+	0x000000C0,
+	0x000300C0,
+	0x00008000,
+	0x00060180,
+	0x20000000,
+	0x00000000,
+	0x00000080,
+	0x00020000,
+	0x00004000,
+	0x000300C0,
+	0x10000000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x06018060,
+	0x06018000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x0000C030,
+	0x0300C000,
+	0x03000000,
+	0x0000300C,
+	0x0000300C,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x01800000,
+	0x00000006,
+	0x00002000,
+	0x00000400,
+	0x00000000,
+	0x00C03000,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x00000200,
+	0x00601806,
+	0x00000000,
+	0x80600000,
+	0x80000601,
+	0x00000601,
+	0x00000100,
+	0x00300C03,
+	0xC0300C00,
+	0xC0300000,
+	0xC0000300,
+	0x000C0300,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x300C0300,
+	0x00000000,
+	0x0FF00000,
+	0x00000000,
+	0x000300C0,
+	0x00008000,
+	0x00080000,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00020000,
+	0x00004000,
+	0x200300C0,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x00002000,
+	0x10018060,
+	0x06018000,
+	0x06000000,
+	0x00010018,
+	0x00006018,
+	0x00001000,
+	0x0000C030,
+	0x00000000,
+	0x03000000,
+	0x0000800C,
+	0x00C0300C,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x0C420D80,
+	0x082000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0xE4400000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x40680208,
+	0x41034051,
+	0x02081A00,
+	0x802080D0,
+	0x34010406,
+	0x01A02490,
+	0x080D0000,
+	0x51406802,
+	0x00410340,
+	0xD000001A,
+	0x06802080,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000FF0,
+	0x72200000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x1A870001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x40680C30,
+	0x49034010,
+	0x12481A02,
+	0x802080D0,
+	0x34051406,
+	0x01A00040,
+	0x080D0002,
+	0x51406802,
+	0x02490340,
+	0xD012481A,
+	0x06802080,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0xE3CF23DA,
+	0xF796591E,
+	0x0344E388,
+	0x821A0000,
+	0x0000D000,
+	0x01040680,
+	0xD271C47A,
+	0x1EE3CF23,
+	0x88F79659,
+	0x000344E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00600391,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x18864000,
+	0x49247A06,
+	0xA3CF23DA,
+	0xF796591E,
+	0x0344E388,
+	0x821A028A,
+	0x0000D000,
+	0x00000680,
+	0xD271C47A,
+	0x1EA2CB23,
+	0x88F79A69,
+	0x000344E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x04864000,
+	0x69A47A01,
+	0x9228A3D6,
+	0xF456591E,
+	0x03549248,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD669A47A,
+	0x1EE3CF23,
+	0x48F45659,
+	0x00035492,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x08864000,
+	0x71C47A02,
+	0xA2CB23D2,
+	0xF796591E,
+	0x0344A288,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xDA49247A,
+	0x1EE3CF23,
+	0x88F79659,
+	0x000344E3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x40002000,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x08000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x20001000,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/terasic/de1-soc/qts/pinmux_config.h b/board/terasic/de1-soc/qts/pinmux_config.h
new file mode 100644
index 0000000..9a83e85
--- /dev/null
+++ b/board/terasic/de1-soc/qts/pinmux_config.h
@@ -0,0 +1,219 @@
+/*
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	3, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	3, /* FLASHIO2 */
+	3, /* FLASHIO3 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	3, /* FLASHIO9 */
+	3, /* FLASHIO10 */
+	3, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	1, /* GENERALIO1 */
+	1, /* GENERALIO2 */
+	1, /* GENERALIO3 */
+	1, /* GENERALIO4 */
+	0, /* GENERALIO5 */
+	0, /* GENERALIO6 */
+	1, /* GENERALIO7 */
+	1, /* GENERALIO8 */
+	0, /* GENERALIO9 */
+	0, /* GENERALIO10 */
+	0, /* GENERALIO11 */
+	0, /* GENERALIO12 */
+	0, /* GENERALIO13 */
+	0, /* GENERALIO14 */
+	1, /* GENERALIO15 */
+	1, /* GENERALIO16 */
+	1, /* GENERALIO17 */
+	1, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	0, /* MIXED1IO14 */
+	3, /* MIXED1IO15 */
+	3, /* MIXED1IO16 */
+	3, /* MIXED1IO17 */
+	3, /* MIXED1IO18 */
+	3, /* MIXED1IO19 */
+	3, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	1, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	1, /* GPLMUX57 */
+	1, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	0, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/terasic/de1-soc/qts/pll_config.h b/board/terasic/de1-soc/qts/pll_config.h
new file mode 100644
index 0000000..543b8ea
--- /dev/null
+++ b/board/terasic/de1-soc/qts/pll_config.h
@@ -0,0 +1,91 @@
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/terasic/de1-soc/qts/sdram_config.h b/board/terasic/de1-soc/qts/sdram_config.h
new file mode 100644
index 0000000..171a1ad
--- /dev/null
+++ b/board/terasic/de1-soc/qts/sdram_config.h
@@ -0,0 +1,344 @@
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			18
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		3120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		200
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x49
+#define RW_MGR_GUARANTEED_READ	0x4C
+#define RW_MGR_GUARANTEED_READ_CONT	0x54
+#define RW_MGR_GUARANTEED_WRITE	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7B
+#define RW_MGR_IDLE_LOOP2	0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0	0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x59
+#define RW_MGR_READ_B2B_WAIT1	0x61
+#define RW_MGR_READ_B2B_WAIT2	0x6B
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7D
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	8
+#define CALIB_VFIFO_OFFSET	6
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	312
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x5555048d
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	4
+#define RW_MGR_MEM_DATA_WIDTH	32
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
+#define TINIT_CNTR0_VAL	99
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	99
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080431,
+	0x10080530,
+	0x10090044,
+	0x100a0010,
+	0x100b0000,
+	0x10380400,
+	0x10080449,
+	0x100804c8,
+	0x100a0024,
+	0x10090008,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/terasic/de1-soc/socfpga.c b/board/terasic/de1-soc/socfpga.c
new file mode 100644
index 0000000..0d29e44
--- /dev/null
+++ b/board/terasic/de1-soc/socfpga.c
@@ -0,0 +1,19 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <spl.h>
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	spl_boot_list[0] = spl_boot_device();
+
+	switch (spl_boot_list[0]) {
+	case BOOT_DEVICE_MMC1:
+		spl_boot_list[0] = BOOT_DEVICE_MMC1;
+		spl_boot_list[1] = BOOT_DEVICE_UART;
+		break;
+	}
+}
diff --git a/board/terasic/de10-nano/MAINTAINERS b/board/terasic/de10-nano/MAINTAINERS
new file mode 100644
index 0000000..f4dd0df
--- /dev/null
+++ b/board/terasic/de10-nano/MAINTAINERS
@@ -0,0 +1,5 @@
+DE10-NANO BOARD
+M:	Dalon Westergreen <dwesterg@gmail.com>
+S:	Maintained
+F:	include/configs/socfpga_de10_nano.h
+F:	configs/socfpga_de10_nano_defconfig
diff --git a/board/terasic/de10-nano/Makefile b/board/terasic/de10-nano/Makefile
new file mode 100644
index 0000000..ab38f42
--- /dev/null
+++ b/board/terasic/de10-nano/Makefile
@@ -0,0 +1,9 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+# Copyright (C) 2017, Intel Corporation
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= socfpga.o
diff --git a/board/terasic/de10-nano/qts/iocsr_config.h b/board/terasic/de10-nano/qts/iocsr_config.h
new file mode 100644
index 0000000..7e049bf
--- /dev/null
+++ b/board/terasic/de10-nano/qts/iocsr_config.h
@@ -0,0 +1,660 @@
+/*
+ * Altera SoCFPGA IOCSR configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00020080,
+	0x18060000,
+	0x08000000,
+	0x00018020,
+	0x00000000,
+	0x00004000,
+	0x00010040,
+	0x04010000,
+	0x04000000,
+	0x00000010,
+	0x00004010,
+	0x00002000,
+	0x00020000,
+	0x02008000,
+	0x02000000,
+	0x00000008,
+	0x00002008,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x00100000,
+	0x10040000,
+	0x100000C0,
+	0x00000040,
+	0x00010040,
+	0x00008000,
+	0x00060180,
+	0x20000000,
+	0x00000000,
+	0x00000080,
+	0x00020000,
+	0x00004000,
+	0x00010040,
+	0x10000000,
+	0x04000000,
+	0x00000010,
+	0x00004010,
+	0x00002000,
+	0x00020000,
+	0x06018000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x00010000,
+	0x04000000,
+	0x00000000,
+	0x00000010,
+	0x00004000,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000008,
+	0x00002000,
+	0x00000400,
+	0x00000000,
+	0x00401000,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x00000200,
+	0x00600802,
+	0x00000000,
+	0x80200000,
+	0x80000600,
+	0x00000200,
+	0x00000100,
+	0x00300401,
+	0xC0100400,
+	0x40100000,
+	0x40000300,
+	0x000C0100,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x300C0300,
+	0x00000000,
+	0x0FF00000,
+	0x00000000,
+	0x0C0300C0,
+	0x00008000,
+	0x00080000,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00020000,
+	0x00004000,
+	0x200300C0,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x00002000,
+	0x10018060,
+	0x06018000,
+	0x06000000,
+	0x00010018,
+	0x00006018,
+	0x00001000,
+	0x00010000,
+	0x00000000,
+	0x03000000,
+	0x0000800C,
+	0x00C01004,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x0C420D80,
+	0x082000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0xE4400000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680618,
+	0x45034071,
+	0x0A281A01,
+	0x806180D0,
+	0x34071C06,
+	0x01A034D0,
+	0x180D0000,
+	0x71C06806,
+	0x01450340,
+	0xD000001A,
+	0x0680E380,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000FF0,
+	0x72200000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x1A870001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680618,
+	0x45034071,
+	0x0A281A01,
+	0x806180D0,
+	0x34071C06,
+	0x01A00040,
+	0x180D0002,
+	0x71C06806,
+	0x01450340,
+	0xD00A281A,
+	0x06806180,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x0C864000,
+	0x79E47A03,
+	0xCAAAA3DD,
+	0xF6D5551E,
+	0x0352D348,
+	0x821A0000,
+	0x0000D000,
+	0x030C0680,
+	0xD559647A,
+	0x1ECAAAA3,
+	0xC8F6D965,
+	0x00034AB2,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00600391,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x0C864000,
+	0x79E47A03,
+	0x8B2CA3DD,
+	0xF6D9651E,
+	0x034AB2C8,
+	0x821A0041,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1E8B2CA3,
+	0xC8F6D965,
+	0x00034AB2,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0x8AAAA3D5,
+	0xF6D9651E,
+	0x034AB2C8,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1E8B2CA3,
+	0xC8F6D965,
+	0x00034AB2,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0x8B2CA3D5,
+	0xF6D9651E,
+	0x0352D348,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1E8B2CA3,
+	0x48F6D965,
+	0x000352D3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x40002000,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x08000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x20001000,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/terasic/de10-nano/qts/pinmux_config.h b/board/terasic/de10-nano/qts/pinmux_config.h
new file mode 100644
index 0000000..b8f5ea1
--- /dev/null
+++ b/board/terasic/de10-nano/qts/pinmux_config.h
@@ -0,0 +1,219 @@
+/*
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	3, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	3, /* FLASHIO2 */
+	3, /* FLASHIO3 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	3, /* FLASHIO9 */
+	3, /* FLASHIO10 */
+	3, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	1, /* GENERALIO1 */
+	1, /* GENERALIO2 */
+	1, /* GENERALIO3 */
+	1, /* GENERALIO4 */
+	0, /* GENERALIO5 */
+	0, /* GENERALIO6 */
+	1, /* GENERALIO7 */
+	1, /* GENERALIO8 */
+	0, /* GENERALIO9 */
+	0, /* GENERALIO10 */
+	0, /* GENERALIO11 */
+	0, /* GENERALIO12 */
+	0, /* GENERALIO13 */
+	0, /* GENERALIO14 */
+	1, /* GENERALIO15 */
+	1, /* GENERALIO16 */
+	1, /* GENERALIO17 */
+	1, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	0, /* MIXED1IO14 */
+	0, /* MIXED1IO15 */
+	0, /* MIXED1IO16 */
+	0, /* MIXED1IO17 */
+	0, /* MIXED1IO18 */
+	0, /* MIXED1IO19 */
+	0, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	1, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	1, /* GPLMUX57 */
+	1, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	0, /* RGMII0USEFPGA */
+	1, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	1, /* I2C3USEFPGA */
+	1, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	1 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/terasic/de10-nano/qts/pll_config.h b/board/terasic/de10-nano/qts/pll_config.h
new file mode 100644
index 0000000..3a46047
--- /dev/null
+++ b/board/terasic/de10-nano/qts/pll_config.h
@@ -0,0 +1,85 @@
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 3125000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/terasic/de10-nano/qts/sdram_config.h b/board/terasic/de10-nano/qts/sdram_config.h
new file mode 100644
index 0000000..34dacc7
--- /dev/null
+++ b/board/terasic/de10-nano/qts/sdram_config.h
@@ -0,0 +1,344 @@
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		3120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x1FF
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x10441
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x78
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x49
+#define RW_MGR_GUARANTEED_READ	0x4C
+#define RW_MGR_GUARANTEED_READ_CONT	0x54
+#define RW_MGR_GUARANTEED_WRITE	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7B
+#define RW_MGR_IDLE_LOOP2	0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0	0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x59
+#define RW_MGR_READ_B2B_WAIT1	0x61
+#define RW_MGR_READ_B2B_WAIT2	0x6B
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7D
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	8
+#define CALIB_VFIFO_OFFSET	6
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	312
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x555504a1
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	4
+#define RW_MGR_MEM_DATA_WIDTH	32
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
+#define TINIT_CNTR0_VAL	99
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	99
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080431,
+	0x10080530,
+	0x10090044,
+	0x100a0010,
+	0x100b0000,
+	0x10380400,
+	0x10080449,
+	0x100804c8,
+	0x100a0024,
+	0x10090008,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/terasic/de10-nano/socfpga.c b/board/terasic/de10-nano/socfpga.c
new file mode 100644
index 0000000..c5852e7
--- /dev/null
+++ b/board/terasic/de10-nano/socfpga.c
@@ -0,0 +1,6 @@
+/*
+ * Copyright (C) 2017, Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
diff --git a/board/terasic/sockit/qts/sdram_config.h b/board/terasic/sockit/qts/sdram_config.h
index 769aa77..9906436 100644
--- a/board/terasic/sockit/qts/sdram_config.h
+++ b/board/terasic/sockit/qts/sdram_config.h
@@ -49,6 +49,9 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x1FF
diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c
index c1db289..9b56620 100644
--- a/board/theadorable/theadorable.c
+++ b/board/theadorable/theadorable.c
@@ -115,6 +115,13 @@ MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
 	},
 };
 
+/*
+ * Define a board-specific detection pulse-width array for the SerDes PCIe
+ * interfaces. If not defined in the board code, the default of currently 2
+ * is used. Values from 0...3 are possible (2 bits).
+ */
+u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
+
 MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
 {
 	/* Only one mode supported for this board */
@@ -126,6 +133,12 @@ MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
 	return &theadorable_serdes_cfg[0];
 }
 
+u8 board_sat_r_get(u8 dev_num, u8 reg)
+{
+	/* Bit 0 enables PCI 2.0 link capabilities instead of PCI 1.x */
+	return 0x01;
+}
+
 int board_early_init_f(void)
 {
 	/* Configure MPP */
@@ -281,3 +294,44 @@ int board_late_init(void)
 	return 0;
 }
 #endif
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI)
+int do_pcie_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	pci_dev_t bdf;
+	u16 ven_id, dev_id;
+
+	if (argc != 3)
+		return cmd_usage(cmdtp);
+
+	ven_id = simple_strtoul(argv[1], NULL, 16);
+	dev_id = simple_strtoul(argv[2], NULL, 16);
+
+	printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n",
+	       ven_id, dev_id);
+
+	/*
+	 * Check if the PCIe device is detected (somtimes its not available
+	 * on the PCIe bus)
+	 */
+	bdf = pci_find_device(ven_id, dev_id, 0);
+	if (bdf == -1) {
+		/* PCIe device not found! */
+		printf("Failed to find PCIe device\n");
+	} else {
+		/* PCIe device found! */
+		printf("PCIe device found, resetting board...\n");
+
+		/* default handling: SOFT reset */
+		do_reset(NULL, 0, 0, NULL);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	pcie,   3,   0,     do_pcie_test,
+	"Test for presence of a PCIe device",
+	"<VendorID> <DeviceID>"
+);
+#endif
diff --git a/board/theobroma-systems/puma_rk3399/Kconfig b/board/theobroma-systems/puma_rk3399/Kconfig
new file mode 100644
index 0000000..a645590
--- /dev/null
+++ b/board/theobroma-systems/puma_rk3399/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PUMA_RK3399
+
+config SYS_BOARD
+	default "puma_rk3399"
+
+config SYS_VENDOR
+	default "theobroma-systems"
+
+config SYS_CONFIG_NAME
+	default "puma_rk3399"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/theobroma-systems/puma_rk3399/MAINTAINERS b/board/theobroma-systems/puma_rk3399/MAINTAINERS
new file mode 100644
index 0000000..ccec09c
--- /dev/null
+++ b/board/theobroma-systems/puma_rk3399/MAINTAINERS
@@ -0,0 +1,10 @@
+PUMA-RK3399
+M:	Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+M:	Klaus Goger <klaus.goger@theobroma-systems.com>
+S:	Maintained
+F:	board/theobroma-systems/puma_rk3399
+F:	include/configs/puma_rk3399.h
+F:	arch/arm/dts/rk3399-puma.dts
+F:	configs/puma-rk3399_defconfig
+W:	https://www.theobroma-systems.com/rk3399-q7/tech-specs
+T:	git git://git.theobroma-systems.com/puma-u-boot.git
diff --git a/board/theobroma-systems/puma_rk3399/Makefile b/board/theobroma-systems/puma_rk3399/Makefile
new file mode 100644
index 0000000..d962b56
--- /dev/null
+++ b/board/theobroma-systems/puma_rk3399/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= puma-rk3399.o
diff --git a/board/theobroma-systems/puma_rk3399/README b/board/theobroma-systems/puma_rk3399/README
new file mode 100644
index 0000000..250e345
--- /dev/null
+++ b/board/theobroma-systems/puma_rk3399/README
@@ -0,0 +1,72 @@
+Introduction
+============
+
+The RK3399-Q7 (Puma) is a system-on-module featuring the Rockchip
+RK3399 in a Qseven-compatible form-factor.
+
+RK3399-Q7 features:
+	* CPU: ARMv8 64bit Big-Little architecture,
+		* Big: dual-core Cortex-A72
+		* Little: quad-core Cortex-A53
+		* IRAM: 200KB
+	* DRAM: 4GB-128MB dual-channel
+	* eMMC: onboard eMMC
+	* SD/MMC
+	* GbE (onboard Micrel KSZ9031) Gigabit ethernet PHY
+	* USB:
+		* USB3.0 dual role port
+		* 2x USB3.0 host, 1x USB2.0 host via onboard USB3.0 hub
+	* Display: HDMI/eDP/MIPI
+	* Camera: 2x CSI (one on the edge connector, one on the Q7 specified CSI ZIF)
+	* NOR Flash: onboard SPI NOR
+	* Companion Controller: onboard additional Cortex-M0 microcontroller
+		* RTC
+		* fan controller
+		* CAN
+
+Here is the step-by-step to boot to U-Boot on rk3399.
+
+Get the Source and build ATF/Cortex-M0 binaries
+===============================================
+
+  > git clone git://git.theobroma-systems.com/arm-trusted-firmware.git
+  > git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git
+
+Compile the ATF
+===============
+
+  > cd arm-trusted-firmware
+  > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
+  > cp build/rk3399/release/bl31.bin ../u-boot
+
+Compile the M0 firmware
+=======================
+
+  > cd ../rk3399-cortex-m0
+  > make CROSS_COMPILE=arm-cortex_m0-eabi-
+  > cp rk3399m0.bin ../u-boot
+
+Compile the U-Boot
+==================
+
+  > cd ../u-boot
+  > make CROSS_COMPILE=aarch64-linux-gnu- puma-rk3399_defconfig all
+
+Package the image
+=================
+
+	> tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin spl.img
+	> make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb
+
+Flash the image
+===============
+
+Copy the SPL to offset 32k and the FIT image containing the payloads
+(U-Boot proper, ATF, M0 Firmware, devicetree) to offset 256k on a SD
+card.
+
+  > dd if=spl.img of=/dev/sdb seek=64
+  > dd if=u-boot.itb of=/dev/sdb seek=512
+
+After powering up the board (with the inserted SD card), you should see
+a U-Boot console on UART0 (115200n8).
diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
new file mode 100644
index 0000000..f93c251
--- /dev/null
+++ b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * Minimal dts for a SPL FIT image payload.
+ *
+ * SPDX-License-Identifier: GPL-2.0+  X11
+ */
+
+/dts-v1/;
+
+/ {
+	description = "FIT image with U-Boot proper, ATF bl31, M0 Firmware, DTB";
+	#address-cells = <1>;
+
+	images {
+		uboot@1 {
+			description = "U-Boot (64-bit)";
+			data = /incbin/("../../../u-boot-nodtb.bin");
+			type = "standalone";
+			arch = "arm64";
+			compression = "none";
+			load = <0x00200000>;
+		};
+		atf@1 {
+			description = "ARM Trusted Firmware";
+			data = /incbin/("../../../bl31.bin");
+			type = "firmware";
+			arch = "arm64";
+			compression = "none";
+			load = <0x00001000>;
+			entry = <0x00001000>;
+		};
+		pmu@1 {
+		        description = "Cortex-M0 firmware";
+			data = /incbin/("../../../rk3399m0.bin");
+			type = "pmu-firmware";
+			compression = "none";
+			load = <0xff8c0000>;
+                };
+		fdt@1 {
+			description = "RK3399-Q7 (Puma) flat device-tree";
+			data = /incbin/("../../../u-boot.dtb");
+			type = "flat_dt";
+			compression = "none";
+		};
+	};
+
+	configurations {
+		default = "conf@1";
+		conf@1 {
+			description = "Theobroma Systems RK3399-Q7 (Puma) SoM";
+			firmware = "uboot@1";
+			loadables = "atf@1";
+			fdt = "fdt@1";
+		};
+	};
+};
diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
new file mode 100644
index 0000000..9347329
--- /dev/null
+++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
@@ -0,0 +1,176 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <misc.h>
+#include <ram.h>
+#include <dm/pinctrl.h>
+#include <dm/uclass-internal.h>
+#include <asm/setup.h>
+#include <asm/arch/periph.h>
+#include <power/regulator.h>
+#include <u-boot/sha256.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	struct udevice *pinctrl, *regulator;
+	int ret;
+
+	/*
+	 * The PWM does not have decicated interrupt number in dts and can
+	 * not get periph_id by pinctrl framework, so let's init them here.
+	 * The PWM2 and PWM3 are for pwm regulators.
+	 */
+	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+	if (ret) {
+		debug("%s: Cannot find pinctrl device\n", __func__);
+		goto out;
+	}
+
+	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2);
+	if (ret) {
+		debug("%s PWM2 pinctrl init fail!\n", __func__);
+		goto out;
+	}
+
+	/* rk3399 need to init vdd_center to get the correct output voltage */
+	ret = regulator_get_by_platname("vdd_center", &regulator);
+	if (ret)
+		debug("%s: Cannot get vdd_center regulator\n", __func__);
+
+	ret = regulator_get_by_platname("vcc5v0_host", &regulator);
+	if (ret) {
+		debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret);
+		goto out;
+	}
+
+	ret = regulator_set_enable(regulator, true);
+	if (ret) {
+		debug("%s vcc5v0-host-en set fail!\n", __func__);
+		goto out;
+	}
+
+out:
+	return 0;
+}
+
+static void setup_macaddr(void)
+{
+#if CONFIG_IS_ENABLED(CMD_NET)
+	int ret;
+	const char *cpuid = getenv("cpuid#");
+	u8 hash[SHA256_SUM_LEN];
+	int size = sizeof(hash);
+	u8 mac_addr[6];
+
+	/* Only generate a MAC address, if none is set in the environment */
+	if (getenv("ethaddr"))
+		return;
+
+	if (!cpuid) {
+		debug("%s: could not retrieve 'cpuid#'\n", __func__);
+		return;
+	}
+
+	ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size);
+	if (ret) {
+		debug("%s: failed to calculate SHA256\n", __func__);
+		return;
+	}
+
+	/* Copy 6 bytes of the hash to base the MAC address on */
+	memcpy(mac_addr, hash, 6);
+
+	/* Make this a valid MAC address and set it */
+	mac_addr[0] &= 0xfe;  /* clear multicast bit */
+	mac_addr[0] |= 0x02;  /* set local assignment bit (IEEE802) */
+	eth_setenv_enetaddr("ethaddr", mac_addr);
+#endif
+
+	return;
+}
+
+static void setup_serial(void)
+{
+#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE)
+	const u32 cpuid_offset = 0x7;
+	const u32 cpuid_length = 0x10;
+
+	struct udevice *dev;
+	int ret, i;
+	u8 cpuid[cpuid_length];
+	u8 low[cpuid_length/2], high[cpuid_length/2];
+	char cpuid_str[cpuid_length * 2 + 1];
+	u64 serialno;
+	char serialno_str[16];
+
+	/* retrieve the device */
+	ret = uclass_get_device_by_driver(UCLASS_MISC,
+					  DM_GET_DRIVER(rockchip_efuse), &dev);
+	if (ret) {
+		debug("%s: could not find efuse device\n", __func__);
+		return;
+	}
+
+	/* read the cpu_id range from the efuses */
+	ret = misc_read(dev, cpuid_offset, &cpuid, sizeof(cpuid));
+	if (ret) {
+		debug("%s: reading cpuid from the efuses failed\n",
+		      __func__);
+		return;
+	}
+
+	memset(cpuid_str, 0, sizeof(cpuid_str));
+	for (i = 0; i < 16; i++)
+		sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]);
+
+	debug("cpuid: %s\n", cpuid_str);
+
+	/*
+	 * Mix the cpuid bytes using the same rules as in
+	 *   ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c
+	 */
+	for (i = 0; i < 8; i++) {
+		low[i] = cpuid[1 + (i << 1)];
+		high[i] = cpuid[i << 1];
+	}
+
+	serialno = crc32_no_comp(0, low, 8);
+	serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
+	snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno);
+
+	setenv("cpuid#", cpuid_str);
+	setenv("serial#", serialno_str);
+#endif
+
+	return;
+}
+
+int misc_init_r(void)
+{
+	setup_serial();
+	setup_macaddr();
+
+	return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	char *serial_string;
+	u64 serial = 0;
+
+	serial_string = getenv("serial#");
+
+	if (serial_string)
+		serial = simple_strtoull(serial_string, NULL, 16);
+
+	serialnr->high = (u32)(serial >> 32);
+	serialnr->low = (u32)(serial & 0xffffffff);
+}
+#endif
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 56f4984..0a16529 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -9,6 +9,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
 #include <spl.h>
 #include <serial.h>
@@ -25,6 +26,9 @@
 #include <asm/io.h>
 #include <asm/emif.h>
 #include <asm/gpio.h>
+#include <asm/omap_common.h>
+#include <asm/omap_sec_common.h>
+#include <asm/omap_mmc.h>
 #include <i2c.h>
 #include <miiphy.h>
 #include <cpsw.h>
@@ -46,19 +50,34 @@ DECLARE_GLOBAL_DATA_PTR;
 #define GPIO_MUX_MII_CTRL	GPIO_TO_PIN(3, 10)
 #define GPIO_FET_SWITCH_CTRL	GPIO_TO_PIN(0, 7)
 #define GPIO_PHY_RESET		GPIO_TO_PIN(2, 5)
+#define GPIO_ETH0_MODE		GPIO_TO_PIN(0, 11)
+#define GPIO_ETH1_MODE		GPIO_TO_PIN(1, 26)
 
-#if defined(CONFIG_SPL_BUILD) || \
-	(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-#endif
+
+#define GPIO0_RISINGDETECT	(AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
+#define GPIO1_RISINGDETECT	(AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
+
+#define GPIO0_IRQSTATUS1	(AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
+#define GPIO1_IRQSTATUS1	(AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
+
+#define GPIO0_IRQSTATUSRAW	(AM33XX_GPIO0_BASE + 0x024)
+#define GPIO1_IRQSTATUSRAW	(AM33XX_GPIO1_BASE + 0x024)
 
 /*
  * Read header information from EEPROM into global structure.
  */
-static inline int __maybe_unused read_eeprom(void)
+#ifdef CONFIG_TI_I2C_BOARD_DETECT
+void do_board_detect(void)
 {
-	return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
+	enable_i2c0_pin_mux();
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+
+	if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+				 CONFIG_EEPROM_CHIP_ADDRESS))
+		printf("ti_i2c_eeprom_init failed\n");
 }
+#endif
 
 #ifndef CONFIG_DM_SERIAL
 struct serial_device *default_serial_console(void)
@@ -94,6 +113,16 @@ static const struct emif_regs ddr2_emif_reg_data = {
 	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 };
 
+static const struct emif_regs ddr2_evm_emif_reg_data = {
+	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
+	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
+	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
+	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
+	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
+	.ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
+	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
+};
+
 static const struct ddr_data ddr3_data = {
 	.datardsratio0 = MT41J128MJT125_RD_DQS,
 	.datawdsratio0 = MT41J128MJT125_WR_DQS,
@@ -183,6 +212,7 @@ static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
 	.zq_config = MT41K256M16HA125E_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 };
@@ -193,6 +223,7 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
 	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
+	.ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 	.zq_config = MT41J512M8RH125_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 				PHY_EN_DYN_PWRDN,
@@ -227,171 +258,215 @@ int spl_start_uboot(void)
 }
 #endif
 
-#define OSC	(V_OSCK/1000000)
-const struct dpll_params dpll_ddr = {
-		266, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_evm_sk = {
-		303, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_bone_black = {
-		400, OSC-1, 1, -1, -1, -1, -1};
-
-void am33xx_spl_board_init(void)
+const struct dpll_params *get_dpll_ddr_params(void)
 {
-	int mpu_vdd;
-
-	if (read_eeprom() < 0)
-		puts("Could not get board ID.\n");
+	int ind = get_sys_clk_index();
 
-	/* Get the frequency */
-	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+	if (board_is_evm_sk())
+		return &dpll_ddr3_303MHz[ind];
+	else if (board_is_bone_lt() || board_is_icev2())
+		return &dpll_ddr3_400MHz[ind];
+	else if (board_is_evm_15_or_later())
+		return &dpll_ddr3_303MHz[ind];
+	else
+		return &dpll_ddr2_266MHz[ind];
+}
 
-	if (board_is_bone() || board_is_bone_lt()) {
-		/* BeagleBone PMIC Code */
-		int usb_cur_lim;
+static u8 bone_not_connected_to_ac_power(void)
+{
+	if (board_is_bone()) {
+		uchar pmic_status_reg;
+		if (tps65217_reg_read(TPS65217_STATUS,
+				      &pmic_status_reg))
+			return 1;
+		if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
+			puts("No AC power, switching to default OPP\n");
+			return 1;
+		}
+	}
+	return 0;
+}
 
-		/*
-		 * Only perform PMIC configurations if board rev > A1
-		 * on Beaglebone White
-		 */
-		if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
-			return;
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	int ind = get_sys_clk_index();
+	int freq = am335x_get_efuse_mpu_max_freq(cdev);
+
+	if (bone_not_connected_to_ac_power())
+		freq = MPUPLL_M_600;
+
+	if (board_is_bone_lt())
+		freq = MPUPLL_M_1000;
+
+	switch (freq) {
+	case MPUPLL_M_1000:
+		return &dpll_mpu_opp[ind][5];
+	case MPUPLL_M_800:
+		return &dpll_mpu_opp[ind][4];
+	case MPUPLL_M_720:
+		return &dpll_mpu_opp[ind][3];
+	case MPUPLL_M_600:
+		return &dpll_mpu_opp[ind][2];
+	case MPUPLL_M_500:
+		return &dpll_mpu_opp100;
+	case MPUPLL_M_300:
+		return &dpll_mpu_opp[ind][0];
+	}
 
-		if (i2c_probe(TPS65217_CHIP_PM))
-			return;
+	return &dpll_mpu_opp[ind][0];
+}
 
-		/*
-		 * On Beaglebone White we need to ensure we have AC power
-		 * before increasing the frequency.
-		 */
-		if (board_is_bone()) {
-			uchar pmic_status_reg;
-			if (tps65217_reg_read(TPS65217_STATUS,
-					      &pmic_status_reg))
-				return;
-			if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
-				puts("No AC power, disabling frequency switch\n");
-				return;
-			}
-		}
+static void scale_vcores_bone(int freq)
+{
+	int usb_cur_lim, mpu_vdd;
 
-		/*
-		 * Override what we have detected since we know if we have
-		 * a Beaglebone Black it supports 1GHz.
-		 */
-		if (board_is_bone_lt())
-			dpll_mpu_opp100.m = MPUPLL_M_1000;
+	/*
+	 * Only perform PMIC configurations if board rev > A1
+	 * on Beaglebone White
+	 */
+	if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
+		return;
 
-		/*
-		 * Increase USB current limit to 1300mA or 1800mA and set
-		 * the MPU voltage controller as needed.
-		 */
-		if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
-			usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
-			mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
-		} else {
-			usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
-			mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
-		}
+	if (i2c_probe(TPS65217_CHIP_PM))
+		return;
 
-		if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
-				       TPS65217_POWER_PATH,
-				       usb_cur_lim,
-				       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
-			puts("tps65217_reg_write failure\n");
+	/*
+	 * On Beaglebone White we need to ensure we have AC power
+	 * before increasing the frequency.
+	 */
+	if (bone_not_connected_to_ac_power())
+		freq = MPUPLL_M_600;
 
-		/* Set DCDC3 (CORE) voltage to 1.125V */
-		if (tps65217_voltage_update(TPS65217_DEFDCDC3,
-					    TPS65217_DCDC_VOLT_SEL_1125MV)) {
-			puts("tps65217_voltage_update failure\n");
-			return;
-		}
+	/*
+	 * Override what we have detected since we know if we have
+	 * a Beaglebone Black it supports 1GHz.
+	 */
+	if (board_is_bone_lt())
+		freq = MPUPLL_M_1000;
+
+	switch (freq) {
+	case MPUPLL_M_1000:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+		break;
+	case MPUPLL_M_800:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+		break;
+	case MPUPLL_M_720:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+		break;
+	case MPUPLL_M_600:
+	case MPUPLL_M_500:
+	case MPUPLL_M_300:
+	default:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
+		usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+		break;
+	}
 
-		/* Set CORE Frequencies to OPP100 */
-		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+			       TPS65217_POWER_PATH,
+			       usb_cur_lim,
+			       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+		puts("tps65217_reg_write failure\n");
 
-		/* Set DCDC2 (MPU) voltage */
-		if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
-			puts("tps65217_voltage_update failure\n");
-			return;
-		}
+	/* Set DCDC3 (CORE) voltage to 1.10V */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+				    TPS65217_DCDC_VOLT_SEL_1100MV)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
 
-		/*
-		 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
-		 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
-		 */
-		if (board_is_bone()) {
-			if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
-					       TPS65217_DEFLS1,
-					       TPS65217_LDO_VOLTAGE_OUT_3_3,
-					       TPS65217_LDO_MASK))
-				puts("tps65217_reg_write failure\n");
-		} else {
-			if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
-					       TPS65217_DEFLS1,
-					       TPS65217_LDO_VOLTAGE_OUT_1_8,
-					       TPS65217_LDO_MASK))
-				puts("tps65217_reg_write failure\n");
-		}
+	/* Set DCDC2 (MPU) voltage */
+	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
 
+	/*
+	 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
+	 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
+	 */
+	if (board_is_bone()) {
 		if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
-				       TPS65217_DEFLS2,
+				       TPS65217_DEFLS1,
 				       TPS65217_LDO_VOLTAGE_OUT_3_3,
 				       TPS65217_LDO_MASK))
 			puts("tps65217_reg_write failure\n");
 	} else {
-		int sil_rev;
+		if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+				       TPS65217_DEFLS1,
+				       TPS65217_LDO_VOLTAGE_OUT_1_8,
+				       TPS65217_LDO_MASK))
+			puts("tps65217_reg_write failure\n");
+	}
 
-		/*
-		 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
-		 * MPU frequencies we support we use a CORE voltage of
-		 * 1.1375V.  For MPU voltage we need to switch based on
-		 * the frequency we are running at.
-		 */
-		if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
-			return;
+	if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+			       TPS65217_DEFLS2,
+			       TPS65217_LDO_VOLTAGE_OUT_3_3,
+			       TPS65217_LDO_MASK))
+		puts("tps65217_reg_write failure\n");
+}
 
-		/*
-		 * Depending on MPU clock and PG we will need a different
-		 * VDD to drive at that speed.
-		 */
-		sil_rev = readl(&cdev->deviceid) >> 28;
-		mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
-						      dpll_mpu_opp100.m);
+void scale_vcores_generic(int freq)
+{
+	int sil_rev, mpu_vdd;
+
+	/*
+	 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
+	 * MPU frequencies we support we use a CORE voltage of
+	 * 1.10V.  For MPU voltage we need to switch based on
+	 * the frequency we are running at.
+	 */
+	if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
+		return;
 
-		/* Tell the TPS65910 to use i2c */
-		tps65910_set_i2c_control();
+	/*
+	 * Depending on MPU clock and PG we will need a different
+	 * VDD to drive at that speed.
+	 */
+	sil_rev = readl(&cdev->deviceid) >> 28;
+	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
 
-		/* First update MPU voltage. */
-		if (tps65910_voltage_update(MPU, mpu_vdd))
-			return;
+	/* Tell the TPS65910 to use i2c */
+	tps65910_set_i2c_control();
 
-		/* Second, update the CORE voltage. */
-		if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
-			return;
+	/* First update MPU voltage. */
+	if (tps65910_voltage_update(MPU, mpu_vdd))
+		return;
 
-		/* Set CORE Frequencies to OPP100 */
-		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
-	}
+	/* Second, update the CORE voltage. */
+	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
+		return;
 
-	/* Set MPU Frequency to what we detected now that voltages are set */
-	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 }
 
-const struct dpll_params *get_dpll_ddr_params(void)
+void gpi2c_init(void)
 {
-	enable_i2c0_pin_mux();
-	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
-	if (read_eeprom() < 0)
-		puts("Could not get board ID.\n");
+	/* When needed to be invoked prior to BSS initialization */
+	static bool first_time = true;
+
+	if (first_time) {
+		enable_i2c0_pin_mux();
+		i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
+			 CONFIG_SYS_OMAP24_I2C_SLAVE);
+		first_time = false;
+	}
+}
 
-	if (board_is_evm_sk())
-		return &dpll_ddr_evm_sk;
-	else if (board_is_bone_lt() || board_is_icev2())
-		return &dpll_ddr_bone_black;
-	else if (board_is_evm_15_or_later())
-		return &dpll_ddr_evm_sk;
+void scale_vcores(void)
+{
+	int freq;
+
+	gpi2c_init();
+	freq = am335x_get_efuse_mpu_max_freq(cdev);
+
+	if (board_is_beaglebonex())
+		scale_vcores_bone(freq);
 	else
-		return &dpll_ddr;
+		scale_vcores_generic(freq);
 }
 
 void set_uart_mux_conf(void)
@@ -413,9 +488,6 @@ void set_uart_mux_conf(void)
 
 void set_mux_conf_regs(void)
 {
-	if (read_eeprom() < 0)
-		puts("Could not get board ID.\n");
-
 	enable_board_pin_mux();
 }
 
@@ -453,9 +525,6 @@ const struct ctrl_ioregs ioregs = {
 
 void sdram_init(void)
 {
-	if (read_eeprom() < 0)
-		puts("Could not get board ID.\n");
-
 	if (board_is_evm_sk()) {
 		/*
 		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
@@ -485,15 +554,18 @@ void sdram_init(void)
 		config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
 			   &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
 			   0);
+	else if (board_is_gp_evm())
+		config_ddr(266, &ioregs, &ddr2_data,
+			   &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
 	else
 		config_ddr(266, &ioregs, &ddr2_data,
 			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 }
 #endif
 
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+#if !defined(CONFIG_SPL_BUILD) || \
 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-static void request_and_set_gpio(int gpio, char *name)
+static void request_and_set_gpio(int gpio, char *name, int val)
 {
 	int ret;
 
@@ -509,7 +581,7 @@ static void request_and_set_gpio(int gpio, char *name)
 		goto err_free_gpio;
 	}
 
-	gpio_set_value(gpio, 1);
+	gpio_set_value(gpio, val);
 
 	return;
 
@@ -517,7 +589,8 @@ err_free_gpio:
 	gpio_free(gpio);
 }
 
-#define REQUEST_AND_SET_GPIO(N)	request_and_set_gpio(N, #N);
+#define REQUEST_AND_SET_GPIO(N)	request_and_set_gpio(N, #N, 1);
+#define REQUEST_AND_CLR_GPIO(N)	request_and_set_gpio(N, #N, 0);
 
 /**
  * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
@@ -547,20 +620,76 @@ int board_init(void)
 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
 	gpmc_init();
 #endif
-#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD))
-	int rv;
 
+#if !defined(CONFIG_SPL_BUILD) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 	if (board_is_icev2()) {
+		int rv;
+		u32 reg;
+
 		REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
-		REQUEST_AND_SET_GPIO(GPIO_MUX_MII_CTRL);
+		/* Make J19 status available on GPIO1_26 */
+		REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
+
 		REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
+		/*
+		 * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
+		 * jumpers near the port. Read the jumper value and set
+		 * the pinmux, external mux and PHY clock accordingly.
+		 * As jumper line is overridden by PHY RX_DV pin immediately
+		 * after bootstrap (power-up/reset), we need to sample
+		 * it during PHY reset using GPIO rising edge detection.
+		 */
 		REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
+		/* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
+		reg = readl(GPIO0_RISINGDETECT) | BIT(11);
+		writel(reg, GPIO0_RISINGDETECT);
+		reg = readl(GPIO1_RISINGDETECT) | BIT(26);
+		writel(reg, GPIO1_RISINGDETECT);
+		/* Reset PHYs to capture the Jumper setting */
+		gpio_set_value(GPIO_PHY_RESET, 0);
+		udelay(2);	/* PHY datasheet states 1uS min. */
+		gpio_set_value(GPIO_PHY_RESET, 1);
+
+		reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
+		if (reg) {
+			writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
+			/* RMII mode */
+			printf("ETH0, CPSW\n");
+		} else {
+			/* MII mode */
+			printf("ETH0, PRU\n");
+			cdce913_data.pdiv3 = 4;	/* 25MHz PHY clk */
+		}
+
+		reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
+		if (reg) {
+			writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
+			/* RMII mode */
+			printf("ETH1, CPSW\n");
+			gpio_set_value(GPIO_MUX_MII_CTRL, 1);
+		} else {
+			/* MII mode */
+			printf("ETH1, PRU\n");
+			cdce913_data.pdiv2 = 4;	/* 25MHz PHY clk */
+		}
+
+		/* disable rising edge IRQs */
+		reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
+		writel(reg, GPIO0_RISINGDETECT);
+		reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
+		writel(reg, GPIO1_RISINGDETECT);
 
 		rv = setup_clock_synthesizer(&cdce913_data);
 		if (rv) {
 			printf("Clock synthesizer setup failed %d\n", rv);
 			return rv;
 		}
+
+		/* reset PHYs */
+		gpio_set_value(GPIO_PHY_RESET, 0);
+		udelay(2);	/* PHY datasheet states 1uS min. */
+		gpio_set_value(GPIO_PHY_RESET, 1);
 	}
 #endif
 
@@ -570,17 +699,72 @@ int board_init(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
+#if !defined(CONFIG_SPL_BUILD)
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+#endif
+
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	int rc;
 	char *name = NULL;
 
-	rc = read_eeprom();
-	if (rc)
-		puts("Could not get board ID.\n");
+	if (board_is_bone_lt()) {
+		/* BeagleBoard.org BeagleBone Black Wireless: */
+		if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
+			name = "BBBW";
+		}
+		/* SeeedStudio BeagleBone Green Wireless */
+		if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
+			name = "BBGW";
+		}
+		/* BeagleBoard.org BeagleBone Blue */
+		if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
+			name = "BBBL";
+		}
+	}
 
 	if (board_is_bbg1())
 		name = "BBG1";
 	set_board_info_env(name);
+
+	/*
+	 * Default FIT boot on HS devices. Non FIT images are not allowed
+	 * on HS devices.
+	 */
+	if (get_device_type() == HS_DEVICE)
+		setenv("boot_fit", "1");
+#endif
+
+#if !defined(CONFIG_SPL_BUILD)
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("ethaddr")) {
+		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+		if (is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+	}
+
+	mac_lo = readl(&cdev->macid1l);
+	mac_hi = readl(&cdev->macid1h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+	if (!getenv("eth1addr")) {
+		if (is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("eth1addr", mac_addr);
+	}
 #endif
 
 	return 0;
@@ -651,11 +835,15 @@ static struct cpsw_platform_data cpsw_data = {
 int board_eth_init(bd_t *bis)
 {
 	int rv, n = 0;
+#if defined(CONFIG_USB_ETHER) && \
+	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 	uint8_t mac_addr[6];
 	uint32_t mac_hi, mac_lo;
-	__maybe_unused struct ti_am_eeprom *header;
 
-	/* try reading mac address from efuse */
+	/*
+	 * use efuse mac address for USB ethernet as we know that
+	 * both CPSW and USB ethernet will never be active at the same time
+	 */
 	mac_lo = readl(&cdev->macid0l);
 	mac_hi = readl(&cdev->macid0h);
 	mac_addr[0] = mac_hi & 0xFF;
@@ -664,35 +852,13 @@ int board_eth_init(bd_t *bis)
 	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 	mac_addr[4] = mac_lo & 0xFF;
 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+#endif
+
 
 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
-	if (!getenv("ethaddr")) {
-		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
-
-		if (is_valid_ethaddr(mac_addr))
-			eth_setenv_enetaddr("ethaddr", mac_addr);
-	}
 
 #ifdef CONFIG_DRIVER_TI_CPSW
-
-	mac_lo = readl(&cdev->macid1l);
-	mac_hi = readl(&cdev->macid1h);
-	mac_addr[0] = mac_hi & 0xFF;
-	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
-	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
-	mac_addr[4] = mac_lo & 0xFF;
-	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
-	if (!getenv("eth1addr")) {
-		if (is_valid_ethaddr(mac_addr))
-			eth_setenv_enetaddr("eth1addr", mac_addr);
-	}
-
-	if (read_eeprom() < 0)
-		puts("Could not get board ID.\n");
-
 	if (board_is_bone() || board_is_bone_lt() ||
 	    board_is_idk()) {
 		writel(MII_MODE_ENABLE, &cdev->miisel);
@@ -775,3 +941,40 @@ int board_fit_config_name_match(const char *name)
 		return -1;
 }
 #endif
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+void board_fit_image_post_process(void **p_image, size_t *p_size)
+{
+	secure_boot_verify_image(p_image, p_size);
+}
+#endif
+
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
+	.base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
+	.cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
+	.cfg.f_min = 400000,
+	.cfg.f_max = 52000000,
+	.cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
+	.cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
+};
+
+U_BOOT_DEVICE(am335x_mmc0) = {
+	.name = "omap_hsmmc",
+	.platdata = &am335x_mmc0_platdata,
+};
+
+static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
+	.base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
+	.cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
+	.cfg.f_min = 400000,
+	.cfg.f_max = 52000000,
+	.cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
+	.cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
+};
+
+U_BOOT_DEVICE(am335x_mmc1) = {
+	.name = "omap_hsmmc",
+	.platdata = &am335x_mmc1_platdata,
+};
+#endif
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index 9776df7..e13fcff 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -11,6 +11,19 @@
 #ifndef _BOARD_H_
 #define _BOARD_H_
 
+/**
+ * AM335X (EMIF_4D) EMIF REG_COS_COUNT_1, REG_COS_COUNT_2, and
+ * REG_PR_OLD_COUNT values to avoid LCDC DMA FIFO underflows and Frame
+ * Synchronization Lost errors. The values are the biggest that work
+ * reliably with offered video modes and the memory subsystem on the
+ * boards. These register have are briefly documented in "7.3.3.5.2
+ * Command Starvation" section of AM335x TRM. The REG_COS_COUNT_1 and
+ * REG_COS_COUNT_2 do not have any effect on current versions of
+ * AM335x.
+ */
+#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK       0x00141414
+#define EMIF_OCP_CONFIG_AM335X_EVM             0x003d3d3d
+
 static inline int board_is_bone(void)
 {
 	return board_ti_is("A335BONE");
@@ -26,6 +39,11 @@ static inline int board_is_bbg1(void)
 	return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "BBG1", 4);
 }
 
+static inline int board_is_beaglebonex(void)
+{
+	return board_is_bone() || board_is_bone_lt() || board_is_bbg1();
+}
+
 static inline int board_is_evm_sk(void)
 {
 	return board_ti_is("A335X_SK");
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 8afa5f9..ad85b3a 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -397,7 +397,7 @@ void enable_board_pin_mux(void)
 		configure_module_pin_mux(rmii1_pin_mux);
 		configure_module_pin_mux(spi0_pin_mux);
 	} else {
-		puts("Unknown board, cannot configure pinmux.");
-		hang();
+		/* Unknown board. We might still be able to boot. */
+		puts("Bad EEPROM or unknown board, cannot configure pinmux.");
 	}
 }
diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c
index 8d1c390..136cc43 100644
--- a/board/ti/am3517crane/am3517crane.c
+++ b/board/ti/am3517crane/am3517crane.c
@@ -43,7 +43,7 @@ int board_init(void)
  */
 int misc_init_r(void)
 {
-#ifdef CONFIG_SYS_I2C_OMAP34XX
+#ifdef CONFIG_SYS_I2C_OMAP24XX
 	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 #endif
 
@@ -63,7 +63,7 @@ void set_muxconf_regs(void)
 	MUX_AM3517CRANE();
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 27c311e..933596d 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -10,7 +10,7 @@
 
 #include <common.h>
 #include <i2c.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <spl.h>
 #include <usb.h>
 #include <asm/omap_sec_common.h>
@@ -20,6 +20,7 @@
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/gpio.h>
 #include <asm/emif.h>
+#include <asm/omap_common.h>
 #include "../common/board_detect.h"
 #include "board.h"
 #include <power/pmic.h>
@@ -39,15 +40,17 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 /*
  * Read header information from EEPROM into global structure.
  */
-static inline int __maybe_unused read_eeprom(void)
+#ifdef CONFIG_TI_I2C_BOARD_DETECT
+void do_board_detect(void)
 {
-	return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
+	if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+				 CONFIG_EEPROM_CHIP_ADDRESS))
+		printf("ti_i2c_eeprom_init failed\n");
 }
+#endif
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 
-#define NUM_OPPS	6
-
 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
 	{	/* 19.2 MHz */
 		{125, 3, 2, -1, -1, -1, -1},	/* OPP 50 */
@@ -314,32 +317,10 @@ void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 	return;
 }
 
-/*
- * get_sys_clk_index : returns the index of the sys_clk read from
- *			ctrl status register. This value is either
- *			read from efuse or sysboot pins.
- */
-static u32 get_sys_clk_index(void)
-{
-	struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
-	u32 ind = readl(&ctrl->statusreg), src;
-
-	src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
-	if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
-		return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
-			CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
-	else /* Value read from SYS BOOT pins */
-		return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
-			CTRL_SYSBOOT_15_14_SHIFT);
-}
-
 const struct dpll_params *get_dpll_ddr_params(void)
 {
 	int ind = get_sys_clk_index();
 
-	if (read_eeprom() < 0)
-		return NULL;
-
 	if (board_is_eposevm())
 		return &epos_evm_dpll_ddr[ind];
 	else if (board_is_evm() || board_is_sk())
@@ -441,6 +422,13 @@ void scale_vcores_generic(u32 m)
 		printf("%s failure\n", __func__);
 		return;
 	}
+
+	/* Set DCDC3 (DDR) voltage */
+	if (tps65218_voltage_update(TPS65218_DCDC3,
+	    TPS65218_DCDC3_VOLT_SEL_1350MV)) {
+		printf("%s failure\n", __func__);
+		return;
+	}
 }
 
 void scale_vcores_idk(u32 m)
@@ -495,9 +483,6 @@ void scale_vcores(void)
 {
 	const struct dpll_params *mpu_params;
 
-	if (read_eeprom() < 0)
-		puts("Could not get board ID.\n");
-
 	/* Ensure I2C is initialized for PMIC configuration */
 	gpi2c_init();
 
@@ -537,8 +522,6 @@ static void enable_vtt_regulator(void)
 
 void sdram_init(void)
 {
-	if (read_eeprom() < 0)
-		return;
 	/*
 	 * EPOS EVM has 1GB LPDDR2 connected to EMIF.
 	 * GP EMV has 1GB DDR3 connected to EMIF
@@ -637,6 +620,13 @@ int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	set_board_info_env(NULL);
+
+	/*
+	 * Default FIT boot on HS devices. Non FIT images are not allowed
+	 * on HS devices.
+	 */
+	if (get_device_type() == HS_DEVICE)
+		setenv("boot_fit", "1");
 #endif
 	return 0;
 }
@@ -692,7 +682,7 @@ int usb_gadget_handle_interrupts(int index)
 #endif /* CONFIG_USB_DWC3 */
 
 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
-int board_usb_init(int index, enum usb_init_type init)
+int omap_xhci_board_usb_init(int index, enum usb_init_type init)
 {
 	enable_usb_clocks(index);
 #ifdef CONFIG_USB_DWC3
@@ -723,7 +713,7 @@ int board_usb_init(int index, enum usb_init_type init)
 	return 0;
 }
 
-int board_usb_cleanup(int index, enum usb_init_type init)
+int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
 {
 #ifdef CONFIG_USB_DWC3
 	switch (index) {
@@ -848,6 +838,15 @@ int board_eth_init(bd_t *bis)
 }
 #endif
 
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {
@@ -869,4 +868,11 @@ void board_fit_image_post_process(void **p_image, size_t *p_size)
 {
 	secure_boot_verify_image(p_image, p_size);
 }
+
+void board_tee_image_process(ulong tee_image, size_t tee_size)
+{
+	secure_tee_install((u32)tee_image);
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
 #endif
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 64de602..00a31a9 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -35,8 +35,16 @@
 #include "mux_data.h"
 
 #define board_is_x15()		board_ti_is("BBRDX15_")
+#define board_is_x15_revb1()	(board_ti_is("BBRDX15_") && \
+				 !strncmp("B.10", board_ti_get_rev(), 3))
+#define board_is_x15_revc()	(board_ti_is("BBRDX15_") && \
+				 !strncmp("C.00", board_ti_get_rev(), 3))
 #define board_is_am572x_evm()	board_ti_is("AM572PM_")
+#define board_is_am572x_evm_reva3()	\
+				(board_ti_is("AM572PM_") && \
+				 !strncmp("A.30", board_ti_get_rev(), 3))
 #define board_is_am572x_idk()	board_ti_is("AM572IDK")
+#define board_is_am571x_idk()	board_ti_is("AM571IDK")
 
 #ifdef CONFIG_DRIVER_TI_CPSW
 #include <cpsw.h>
@@ -44,11 +52,28 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define GPIO_ETH_LCD		GPIO_TO_PIN(2, 22)
 /* GPIO 7_11 */
 #define GPIO_DDR_VTT_EN 203
 
+/* Touch screen controller to identify the LCD */
+#define OSD_TS_FT_BUS_ADDRESS	0
+#define OSD_TS_FT_CHIP_ADDRESS	0x38
+#define OSD_TS_FT_REG_ID	0xA3
+/*
+ * Touchscreen IDs for various OSD panels
+ * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
+ */
+/* Used on newer osd101t2587 Panels */
+#define OSD_TS_FT_ID_5x46	0x54
+/* Used on older osd101t2045 Panels */
+#define OSD_TS_FT_ID_5606	0x08
+
 #define SYSINFO_BOARD_NAME_MAX_LEN	45
 
+#define TPS65903X_PRIMARY_SECONDARY_PAD2	0xFB
+#define TPS65903X_PAD2_POWERHOLD_MASK		0x20
+
 const struct omap_sysinfo sysinfo = {
 	"Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
 };
@@ -58,9 +83,17 @@ static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
 	.is_ma_present  = 0x1
 };
 
+static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
+	.dmm_lisa_map_3 = 0x80640100,
+	.is_ma_present  = 0x1
+};
+
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 {
-	*dmm_lisa_regs = &beagle_x15_lisa_regs;
+	if (board_is_am571x_idk())
+		*dmm_lisa_regs = &am571x_idk_lisa_regs;
+	else
+		*dmm_lisa_regs = &beagle_x15_lisa_regs;
 }
 
 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
@@ -217,35 +250,47 @@ void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 }
 
 struct vcores_data beagle_x15_volts = {
-	.mpu.value		= VDD_MPU_DRA7,
-	.mpu.efuse.reg		= STD_FUSE_OPP_VMIN_MPU,
+	.mpu.value[OPP_NOM]	= VDD_MPU_DRA7_NOM,
+	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
 	.mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 	.mpu.addr		= TPS659038_REG_ADDR_SMPS12,
 	.mpu.pmic		= &tps659038,
 	.mpu.abb_tx_done_mask	= OMAP_ABB_MPU_TXDONE_MASK,
 
-	.eve.value		= VDD_EVE_DRA7,
-	.eve.efuse.reg		= STD_FUSE_OPP_VMIN_DSPEVE,
+	.eve.value[OPP_NOM]	= VDD_EVE_DRA7_NOM,
+	.eve.value[OPP_OD]	= VDD_EVE_DRA7_OD,
+	.eve.value[OPP_HIGH]	= VDD_EVE_DRA7_HIGH,
+	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_DSPEVE_OD,
+	.eve.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.eve.addr		= TPS659038_REG_ADDR_SMPS45,
 	.eve.pmic		= &tps659038,
 	.eve.abb_tx_done_mask	= OMAP_ABB_EVE_TXDONE_MASK,
 
-	.gpu.value		= VDD_GPU_DRA7,
-	.gpu.efuse.reg		= STD_FUSE_OPP_VMIN_GPU,
+	.gpu.value[OPP_NOM]	= VDD_GPU_DRA7_NOM,
+	.gpu.value[OPP_OD]	= VDD_GPU_DRA7_OD,
+	.gpu.value[OPP_HIGH]	= VDD_GPU_DRA7_HIGH,
+	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_GPU_OD,
+	.gpu.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_GPU_HIGH,
 	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.gpu.addr		= TPS659038_REG_ADDR_SMPS45,
 	.gpu.pmic		= &tps659038,
 	.gpu.abb_tx_done_mask	= OMAP_ABB_GPU_TXDONE_MASK,
 
-	.core.value		= VDD_CORE_DRA7,
-	.core.efuse.reg		= STD_FUSE_OPP_VMIN_CORE,
+	.core.value[OPP_NOM]	= VDD_CORE_DRA7_NOM,
+	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
 	.core.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.core.addr		= TPS659038_REG_ADDR_SMPS6,
 	.core.pmic		= &tps659038,
 
-	.iva.value		= VDD_IVA_DRA7,
-	.iva.efuse.reg		= STD_FUSE_OPP_VMIN_IVA,
+	.iva.value[OPP_NOM]	= VDD_IVA_DRA7_NOM,
+	.iva.value[OPP_OD]	= VDD_IVA_DRA7_OD,
+	.iva.value[OPP_HIGH]	= VDD_IVA_DRA7_HIGH,
+	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_IVA_OD,
+	.iva.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_IVA_HIGH,
 	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.iva.addr		= TPS659038_REG_ADDR_SMPS45,
 	.iva.pmic		= &tps659038,
@@ -253,41 +298,129 @@ struct vcores_data beagle_x15_volts = {
 };
 
 struct vcores_data am572x_idk_volts = {
-	.mpu.value		= VDD_MPU_DRA7,
-	.mpu.efuse.reg		= STD_FUSE_OPP_VMIN_MPU,
+	.mpu.value[OPP_NOM]	= VDD_MPU_DRA7_NOM,
+	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
 	.mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 	.mpu.addr		= TPS659038_REG_ADDR_SMPS12,
 	.mpu.pmic		= &tps659038,
 	.mpu.abb_tx_done_mask	= OMAP_ABB_MPU_TXDONE_MASK,
 
-	.eve.value		= VDD_EVE_DRA7,
-	.eve.efuse.reg		= STD_FUSE_OPP_VMIN_DSPEVE,
+	.eve.value[OPP_NOM]	= VDD_EVE_DRA7_NOM,
+	.eve.value[OPP_OD]	= VDD_EVE_DRA7_OD,
+	.eve.value[OPP_HIGH]	= VDD_EVE_DRA7_HIGH,
+	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_DSPEVE_OD,
+	.eve.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.eve.addr		= TPS659038_REG_ADDR_SMPS45,
 	.eve.pmic		= &tps659038,
 	.eve.abb_tx_done_mask	= OMAP_ABB_EVE_TXDONE_MASK,
 
-	.gpu.value		= VDD_GPU_DRA7,
-	.gpu.efuse.reg		= STD_FUSE_OPP_VMIN_GPU,
+	.gpu.value[OPP_NOM]	= VDD_GPU_DRA7_NOM,
+	.gpu.value[OPP_OD]	= VDD_GPU_DRA7_OD,
+	.gpu.value[OPP_HIGH]	= VDD_GPU_DRA7_HIGH,
+	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_GPU_OD,
+	.gpu.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_GPU_HIGH,
 	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.gpu.addr		= TPS659038_REG_ADDR_SMPS6,
 	.gpu.pmic		= &tps659038,
 	.gpu.abb_tx_done_mask	= OMAP_ABB_GPU_TXDONE_MASK,
 
-	.core.value		= VDD_CORE_DRA7,
-	.core.efuse.reg		= STD_FUSE_OPP_VMIN_CORE,
+	.core.value[OPP_NOM]	= VDD_CORE_DRA7_NOM,
+	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
 	.core.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.core.addr		= TPS659038_REG_ADDR_SMPS7,
 	.core.pmic		= &tps659038,
 
-	.iva.value		= VDD_IVA_DRA7,
-	.iva.efuse.reg		= STD_FUSE_OPP_VMIN_IVA,
+	.iva.value[OPP_NOM]	= VDD_IVA_DRA7_NOM,
+	.iva.value[OPP_OD]	= VDD_IVA_DRA7_OD,
+	.iva.value[OPP_HIGH]	= VDD_IVA_DRA7_HIGH,
+	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_IVA_OD,
+	.iva.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_IVA_HIGH,
 	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.iva.addr		= TPS659038_REG_ADDR_SMPS8,
 	.iva.pmic		= &tps659038,
 	.iva.abb_tx_done_mask	= OMAP_ABB_IVA_TXDONE_MASK,
 };
 
+struct vcores_data am571x_idk_volts = {
+	.mpu.value[OPP_NOM]	= VDD_MPU_DRA7_NOM,
+	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+	.mpu.addr		= TPS659038_REG_ADDR_SMPS12,
+	.mpu.pmic		= &tps659038,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+	.eve.value[OPP_NOM]	= VDD_EVE_DRA7_NOM,
+	.eve.value[OPP_OD]	= VDD_EVE_DRA7_OD,
+	.eve.value[OPP_HIGH]	= VDD_EVE_DRA7_HIGH,
+	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_DSPEVE_OD,
+	.eve.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
+	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.eve.addr		= TPS659038_REG_ADDR_SMPS45,
+	.eve.pmic		= &tps659038,
+	.eve.abb_tx_done_mask	= OMAP_ABB_EVE_TXDONE_MASK,
+
+	.gpu.value[OPP_NOM]	= VDD_GPU_DRA7_NOM,
+	.gpu.value[OPP_OD]	= VDD_GPU_DRA7_OD,
+	.gpu.value[OPP_HIGH]	= VDD_GPU_DRA7_HIGH,
+	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_GPU_OD,
+	.gpu.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_GPU_HIGH,
+	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.gpu.addr		= TPS659038_REG_ADDR_SMPS6,
+	.gpu.pmic		= &tps659038,
+	.gpu.abb_tx_done_mask	= OMAP_ABB_GPU_TXDONE_MASK,
+
+	.core.value[OPP_NOM]	= VDD_CORE_DRA7_NOM,
+	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.core.addr		= TPS659038_REG_ADDR_SMPS7,
+	.core.pmic		= &tps659038,
+
+	.iva.value[OPP_NOM]	= VDD_IVA_DRA7_NOM,
+	.iva.value[OPP_OD]	= VDD_IVA_DRA7_OD,
+	.iva.value[OPP_HIGH]	= VDD_IVA_DRA7_HIGH,
+	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_IVA_OD,
+	.iva.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_IVA_HIGH,
+	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.iva.addr		= TPS659038_REG_ADDR_SMPS45,
+	.iva.pmic		= &tps659038,
+	.iva.abb_tx_done_mask	= OMAP_ABB_IVA_TXDONE_MASK,
+};
+
+int get_voltrail_opp(int rail_offset)
+{
+	int opp;
+
+	switch (rail_offset) {
+	case VOLT_MPU:
+		opp = DRA7_MPU_OPP;
+		break;
+	case VOLT_CORE:
+		opp = DRA7_CORE_OPP;
+		break;
+	case VOLT_GPU:
+		opp = DRA7_GPU_OPP;
+		break;
+	case VOLT_EVE:
+		opp = DRA7_DSPEVE_OPP;
+		break;
+	case VOLT_IVA:
+		opp = DRA7_IVA_OPP;
+		break;
+	default:
+		opp = OPP_NOM;
+	}
+
+	return opp;
+}
+
+
 #ifdef CONFIG_SPL_BUILD
 /* No env to setup for SPL */
 static inline void setup_board_eeprom_env(void) { }
@@ -322,6 +455,8 @@ void do_board_detect(void)
 		bname = "AM572x EVM";
 	else if (board_is_am572x_idk())
 		bname = "AM572x IDK";
+	else if (board_is_am571x_idk())
+		bname = "AM571x IDK";
 
 	if (bname)
 		snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
@@ -338,15 +473,26 @@ static void setup_board_eeprom_env(void)
 	if (rc)
 		goto invalid_eeprom;
 
-	if (board_is_x15())
-		name = "beagle_x15";
-	else if (board_is_am572x_evm())
-		name = "am57xx_evm";
-	else if (board_is_am572x_idk())
+	if (board_is_x15()) {
+		if (board_is_x15_revb1())
+			name = "beagle_x15_revb1";
+		else if (board_is_x15_revc())
+			name = "beagle_x15_revc";
+		else
+			name = "beagle_x15";
+	} else if (board_is_am572x_evm()) {
+		if (board_is_am572x_evm_reva3())
+			name = "am57xx_evm_reva3";
+		else
+			name = "am57xx_evm";
+	} else if (board_is_am572x_idk()) {
 		name = "am572x_idk";
-	else
+	} else if (board_is_am571x_idk()) {
+		name = "am571x_idk";
+	} else {
 		printf("Unidentified board claims %s in eeprom header\n",
 		       board_ti_get_name());
+	}
 
 invalid_eeprom:
 	set_board_info_env(name);
@@ -358,6 +504,8 @@ void vcores_init(void)
 {
 	if (board_is_am572x_idk())
 		*omap_vcores = &am572x_idk_volts;
+	else if (board_is_am571x_idk())
+		*omap_vcores = &am571x_idk_volts;
 	else
 		*omap_vcores = &beagle_x15_volts;
 }
@@ -369,6 +517,21 @@ void hw_data_init(void)
 	*ctrl = &dra7xx_ctrl;
 }
 
+bool am571x_idk_needs_lcd(void)
+{
+	bool needs_lcd;
+
+	gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
+	if (gpio_get_value(GPIO_ETH_LCD))
+		needs_lcd = false;
+	else
+		needs_lcd = true;
+
+	gpio_free(GPIO_ETH_LCD);
+
+	return needs_lcd;
+}
+
 int board_init(void)
 {
 	gpmc_init();
@@ -377,15 +540,101 @@ int board_init(void)
 	return 0;
 }
 
+void am57x_idk_lcd_detect(void)
+{
+	int r = -ENODEV;
+	char *idk_lcd = "no";
+	uint8_t buf = 0;
+
+	/* Only valid for IDKs */
+	if (board_is_x15() || board_is_am572x_evm())
+		return;
+
+	/* Only AM571x IDK has gpio control detect.. so check that */
+	if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
+		goto out;
+
+	r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS);
+	if (r) {
+		printf("%s: Failed to set bus address to %d: %d\n",
+		       __func__, OSD_TS_FT_BUS_ADDRESS, r);
+		goto out;
+	}
+	r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS);
+	if (r) {
+		/* AM572x IDK has no explicit settings for optional LCD kit */
+		if (board_is_am571x_idk()) {
+			printf("%s: Touch screen detect failed: %d!\n",
+			       __func__, r);
+		}
+		goto out;
+	}
+
+	/* Read FT ID */
+	r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1);
+	if (r) {
+		printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
+		       __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
+		       OSD_TS_FT_REG_ID, r);
+		goto out;
+	}
+
+	switch (buf) {
+	case OSD_TS_FT_ID_5606:
+		idk_lcd = "osd101t2045";
+		break;
+	case OSD_TS_FT_ID_5x46:
+		idk_lcd = "osd101t2587";
+		break;
+	default:
+		printf("%s: Unidentifed Touch screen ID 0x%02x\n",
+		       __func__, buf);
+		/* we will let default be "no lcd" */
+	}
+out:
+	setenv("idk_lcd", idk_lcd);
+	return;
+}
+
 int board_late_init(void)
 {
 	setup_board_eeprom_env();
+	u8 val;
 
 	/*
 	 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 	 * This is the POWERHOLD-in-Low behavior.
 	 */
 	palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
+
+	/*
+	 * Default FIT boot on HS devices. Non FIT images are not allowed
+	 * on HS devices.
+	 */
+	if (get_device_type() == HS_DEVICE)
+		setenv("boot_fit", "1");
+
+	/*
+	 * Set the GPIO7 Pad to POWERHOLD. This has higher priority
+	 * over DEV_CTRL.DEV_ON bit. This can be reset in case of
+	 * PMIC Power off. So to be on the safer side set it back
+	 * to POWERHOLD mode irrespective of the current state.
+	 */
+	palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
+			   &val);
+	val = val | TPS65903X_PAD2_POWERHOLD_MASK;
+	palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
+			    val);
+
+	omap_die_id_serial();
+	omap_set_fastboot_vars();
+
+	am57x_idk_lcd_detect();
+
+#if !defined(CONFIG_SPL_BUILD)
+	board_ti_set_ethaddr(2);
+#endif
+
 	return 0;
 }
 
@@ -399,27 +648,83 @@ void set_muxconf_regs(void)
 void recalibrate_iodelay(void)
 {
 	const struct pad_conf_entry *pconf;
-	const struct iodelay_cfg_entry *iod;
-	int pconf_sz, iod_sz;
+	const struct iodelay_cfg_entry *iod, *delta_iod;
+	int pconf_sz, iod_sz, delta_iod_sz = 0;
+	int ret;
 
 	if (board_is_am572x_idk()) {
 		pconf = core_padconf_array_essential_am572x_idk;
 		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 		iod = iodelay_cfg_array_am572x_idk;
 		iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
+	} else if (board_is_am571x_idk()) {
+		pconf = core_padconf_array_essential_am571x_idk;
+		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
+		iod = iodelay_cfg_array_am571x_idk;
+		iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
 	} else {
 		/* Common for X15/GPEVM */
 		pconf = core_padconf_array_essential_x15;
 		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
-		iod = iodelay_cfg_array_x15;
-		iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15);
+		/* There never was an SR1.0 X15.. So.. */
+		if (omap_revision() == DRA752_ES1_1) {
+			iod = iodelay_cfg_array_x15_sr1_1;
+			iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
+		} else {
+			/* Since full production should switch to SR2.0  */
+			iod = iodelay_cfg_array_x15_sr2_0;
+			iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
+		}
 	}
 
-	__recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz);
+	/* Setup I/O isolation */
+	ret = __recalibrate_iodelay_start();
+	if (ret)
+		goto err;
+
+	/* Do the muxing here */
+	do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
+
+	/* Now do the weird minor deltas that should be safe */
+	if (board_is_x15() || board_is_am572x_evm()) {
+		if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
+		    board_is_x15_revc()) {
+			pconf = core_padconf_array_delta_x15_sr2_0;
+			pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
+		} else {
+			pconf = core_padconf_array_delta_x15_sr1_1;
+			pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
+		}
+		do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
+	}
+
+	if (board_is_am571x_idk()) {
+		if (am571x_idk_needs_lcd()) {
+			pconf = core_padconf_array_vout_am571x_idk;
+			pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
+			delta_iod = iodelay_cfg_array_am571x_idk_4port;
+			delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
+
+		} else {
+			pconf = core_padconf_array_icss1eth_am571x_idk;
+			pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
+		}
+		do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
+	}
+
+	/* Setup IOdelay configuration */
+	ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
+	if (delta_iod_sz)
+		ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
+				     delta_iod_sz);
+
+err:
+	/* Closeup.. remove isolation */
+	__recalibrate_iodelay_end(ret);
 }
 #endif
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	omap_mmc_init(0, 0, 0, -1, -1);
@@ -447,26 +752,6 @@ int spl_start_uboot(void)
 #endif
 
 #ifdef CONFIG_USB_DWC3
-static struct dwc3_device usb_otg_ss1 = {
-	.maximum_speed = USB_SPEED_SUPER,
-	.base = DRA7_USB_OTG_SS1_BASE,
-	.tx_fifo_resize = false,
-	.index = 0,
-};
-
-static struct dwc3_omap_device usb_otg_ss1_glue = {
-	.base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
-	.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
-	.index = 0,
-};
-
-static struct ti_usb_phy_device usb_phy1_device = {
-	.pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
-	.usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
-	.usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
-	.index = 0,
-};
-
 static struct dwc3_device usb_otg_ss2 = {
 	.maximum_speed = USB_SPEED_HIGH,
 	.base = DRA7_USB_OTG_SS2_BASE,
@@ -498,7 +783,7 @@ int usb_gadget_handle_interrupts(int index)
 #endif /* CONFIG_USB_DWC3 */
 
 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
-int board_usb_init(int index, enum usb_init_type init)
+int omap_xhci_board_usb_init(int index, enum usb_init_type init)
 {
 	enable_usb_clocks(index);
 	switch (index) {
@@ -532,7 +817,7 @@ int board_usb_init(int index, enum usb_init_type init)
 	return 0;
 }
 
-int board_usb_cleanup(int index, enum usb_init_type init)
+int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
 {
 #ifdef CONFIG_USB_DWC3
 	switch (index) {
@@ -673,8 +958,8 @@ int board_eth_init(bd_t *bis)
 	ctrl_val |= 0x22;
 	writel(ctrl_val, (*ctrl)->control_core_control_io1);
 
-	/* The phy address for the AM572x IDK are different than x15 */
-	if (board_is_am572x_idk()) {
+	/* The phy address for the AM57xx IDK are different than x15 */
+	if (board_is_am572x_idk() || board_is_am571x_idk()) {
 		cpsw_data.slave_data[0].phy_addr = 0;
 		cpsw_data.slave_data[1].phy_addr = 1;
 	}
@@ -743,14 +1028,23 @@ int ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {
-	if (board_is_x15() && !strcmp(name, "am57xx-beagle-x15"))
+	if (board_is_x15()) {
+		if (board_is_x15_revb1()) {
+			if (!strcmp(name, "am57xx-beagle-x15-revb1"))
+				return 0;
+		} else if (!strcmp(name, "am57xx-beagle-x15")) {
+			return 0;
+		}
+	} else if (board_is_am572x_evm() &&
+		   !strcmp(name, "am57xx-beagle-x15")) {
 		return 0;
-	else if (board_is_am572x_evm() && !strcmp(name, "am57xx-beagle-x15"))
+	} else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
 		return 0;
-	else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk"))
+	} else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
 		return 0;
-	else
-		return -1;
+	}
+
+	return -1;
 }
 #endif
 
@@ -759,4 +1053,11 @@ void board_fit_image_post_process(void **p_image, size_t *p_size)
 {
 	secure_boot_verify_image(p_image, p_size);
 }
+
+void board_tee_image_process(ulong tee_image, size_t tee_size)
+{
+	secure_tee_install((u32)tee_image);
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
 #endif
diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h
index b5ea8ad..b4a71bd 100644
--- a/board/ti/am57xx/mux_data.h
+++ b/board/ti/am57xx/mux_data.h
@@ -13,22 +13,22 @@
 #include <asm/arch/mux_dra7xx.h>
 
 const struct pad_conf_entry core_padconf_array_essential_x15[] = {
-	{GPMC_AD0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad0.vin3a_d0 */
-	{GPMC_AD1, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad1.vin3a_d1 */
-	{GPMC_AD2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad2.vin3a_d2 */
-	{GPMC_AD3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad3.vin3a_d3 */
-	{GPMC_AD4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad4.vin3a_d4 */
-	{GPMC_AD5, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad5.vin3a_d5 */
-	{GPMC_AD6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad6.vin3a_d6 */
-	{GPMC_AD7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad7.vin3a_d7 */
-	{GPMC_AD8, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad8.vin3a_d8 */
-	{GPMC_AD9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad9.vin3a_d9 */
-	{GPMC_AD10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad10.vin3a_d10 */
-	{GPMC_AD11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad11.vin3a_d11 */
-	{GPMC_AD12, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad12.vin3a_d12 */
-	{GPMC_AD13, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad13.vin3a_d13 */
-	{GPMC_AD14, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad14.vin3a_d14 */
-	{GPMC_AD15, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad15.vin3a_d15 */
+	{GPMC_AD0, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad0.vin3a_d0 */
+	{GPMC_AD1, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad1.vin3a_d1 */
+	{GPMC_AD2, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad2.vin3a_d2 */
+	{GPMC_AD3, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad3.vin3a_d3 */
+	{GPMC_AD4, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad4.vin3a_d4 */
+	{GPMC_AD5, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad5.vin3a_d5 */
+	{GPMC_AD6, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad6.vin3a_d6 */
+	{GPMC_AD7, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad7.vin3a_d7 */
+	{GPMC_AD8, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad8.vin3a_d8 */
+	{GPMC_AD9, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad9.vin3a_d9 */
+	{GPMC_AD10, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad10.vin3a_d10 */
+	{GPMC_AD11, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad11.vin3a_d11 */
+	{GPMC_AD12, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad12.vin3a_d12 */
+	{GPMC_AD13, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad13.vin3a_d13 */
+	{GPMC_AD14, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad14.vin3a_d14 */
+	{GPMC_AD15, (M2 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_ad15.vin3a_d15 */
 	{GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a0.vin3a_d16 */
 	{GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a1.vin3a_d17 */
 	{GPMC_A2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a2.vin3a_d18 */
@@ -60,14 +60,14 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
 	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
 	{GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_cs0.gpio2_19 */
 	{GPMC_CS2, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_cs2.gpio2_20 */
-	{GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN)},	/* gpmc_cs3.vin3a_clk0 */
+	{GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_cs3.vin3a_clk0 */
 	{GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)},	/* gpmc_clk.dma_evt1 */
 	{GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_advn_ale.gpio2_23 */
 	{GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_oen_ren.gpio2_24 */
 	{GPMC_WEN, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_wen.gpio2_25 */
 	{GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)},	/* gpmc_ben0.dma_evt3 */
 	{GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)},	/* gpmc_ben1.dma_evt4 */
-	{GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_wait0.gpio2_28 */
+	{GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* gpmc_wait0.gpio2_28 */
 	{VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)},	/* vin1b_clk1.gpio2_31 */
 	{VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d2.gpio3_6 */
 	{VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d3.gpio3_7 */
@@ -83,94 +83,65 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
 	{VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d16.gpio3_20 */
 	{VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d19.gpio3_23 */
 	{VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d20.gpio3_24 */
-	{VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN)},	/* vin1a_d21.vin1a_d21 */
 	{VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d22.gpio3_26 */
 	{VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_clk0.gpio3_28 */
 	{VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_de0.gpio3_29 */
 	{VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_fld0.gpio3_30 */
-	{VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_hsync0.pr1_uart0_cts_n */
-	{VIN2A_VSYNC0, (M11 | PIN_INPUT_PULLUP)},	/* vin2a_vsync0.pr1_uart0_rts_n */
-	{VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d0.pr1_uart0_rxd */
-	{VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d1.pr1_uart0_txd */
-	{VIN2A_D2, (M8 | PIN_INPUT_PULLDOWN)},	/* vin2a_d2.uart10_rxd */
-	{VIN2A_D3, (M8 | PIN_INPUT_PULLDOWN)},	/* vin2a_d3.uart10_txd */
-	{VIN2A_D4, (M8 | PIN_INPUT_PULLDOWN)},	/* vin2a_d4.uart10_ctsn */
-	{VIN2A_D5, (M8 | PIN_INPUT_PULLDOWN)},	/* vin2a_d5.uart10_rtsn */
+	{VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLUP)},	/* vin2a_hsync0.pr1_uart0_cts_n */
+	{VIN2A_VSYNC0, (M11 | PIN_OUTPUT_PULLUP)},	/* vin2a_vsync0.pr1_uart0_rts_n */
+	{VIN2A_D0, (M11 | PIN_INPUT_PULLUP)},	/* vin2a_d0.pr1_uart0_rxd */
+	{VIN2A_D1, (M11 | PIN_OUTPUT)},	/* vin2a_d1.pr1_uart0_txd */
+	{VIN2A_D2, (M8 | PIN_INPUT_PULLUP)},	/* vin2a_d2.uart10_rxd */
+	{VIN2A_D3, (M8 | PIN_OUTPUT)},	/* vin2a_d3.uart10_txd */
+	{VIN2A_D4, (M8 | PIN_INPUT_PULLUP)},	/* vin2a_d4.uart10_ctsn */
+	{VIN2A_D5, (M8 | PIN_OUTPUT_PULLUP)},	/* vin2a_d5.uart10_rtsn */
 	{VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d6.gpio4_7 */
 	{VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d7.gpio4_8 */
 	{VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d8.gpio4_9 */
 	{VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d9.gpio4_10 */
-	{VIN2A_D10, (M10 | PIN_INPUT_PULLDOWN)},	/* vin2a_d10.ehrpwm2B */
+	{VIN2A_D10, (M10 | PIN_OUTPUT_PULLDOWN)},	/* vin2a_d10.ehrpwm2B */
 	{VIN2A_D11, (M10 | PIN_INPUT_PULLDOWN)},	/* vin2a_d11.ehrpwm2_tripzone_input */
-	{VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
-	{VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
-	{VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
-	{VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
-	{VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
-	{VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
-	{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
-	{VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
-	{VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
-	{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
-	{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
-	{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
-	{VOUT1_CLK, (M0 | PIN_OUTPUT)},		/* vout1_clk.vout1_clk */
-	{VOUT1_DE, (M0 | PIN_OUTPUT)},		/* vout1_de.vout1_de */
-	{VOUT1_FLD, (M14 | PIN_INPUT)},		/* vout1_fld.gpio4_21 */
-	{VOUT1_HSYNC, (M0 | PIN_OUTPUT)},	/* vout1_hsync.vout1_hsync */
-	{VOUT1_VSYNC, (M0 | PIN_OUTPUT)},	/* vout1_vsync.vout1_vsync */
-	{VOUT1_D0, (M0 | PIN_OUTPUT)},		/* vout1_d0.vout1_d0 */
-	{VOUT1_D1, (M0 | PIN_OUTPUT)},		/* vout1_d1.vout1_d1 */
-	{VOUT1_D2, (M0 | PIN_OUTPUT)},		/* vout1_d2.vout1_d2 */
-	{VOUT1_D3, (M0 | PIN_OUTPUT)},		/* vout1_d3.vout1_d3 */
-	{VOUT1_D4, (M0 | PIN_OUTPUT)},		/* vout1_d4.vout1_d4 */
-	{VOUT1_D5, (M0 | PIN_OUTPUT)},		/* vout1_d5.vout1_d5 */
-	{VOUT1_D6, (M0 | PIN_OUTPUT)},		/* vout1_d6.vout1_d6 */
-	{VOUT1_D7, (M0 | PIN_OUTPUT)},		/* vout1_d7.vout1_d7 */
-	{VOUT1_D8, (M0 | PIN_OUTPUT)},		/* vout1_d8.vout1_d8 */
-	{VOUT1_D9, (M0 | PIN_OUTPUT)},		/* vout1_d9.vout1_d9 */
-	{VOUT1_D10, (M0 | PIN_OUTPUT)},		/* vout1_d10.vout1_d10 */
-	{VOUT1_D11, (M0 | PIN_OUTPUT)},		/* vout1_d11.vout1_d11 */
-	{VOUT1_D12, (M0 | PIN_OUTPUT)},		/* vout1_d12.vout1_d12 */
-	{VOUT1_D13, (M0 | PIN_OUTPUT)},		/* vout1_d13.vout1_d13 */
-	{VOUT1_D14, (M0 | PIN_OUTPUT)},		/* vout1_d14.vout1_d14 */
-	{VOUT1_D15, (M0 | PIN_OUTPUT)},		/* vout1_d15.vout1_d15 */
-	{VOUT1_D16, (M0 | PIN_OUTPUT)},		/* vout1_d16.vout1_d16 */
-	{VOUT1_D17, (M0 | PIN_OUTPUT)},		/* vout1_d17.vout1_d17 */
-	{VOUT1_D18, (M0 | PIN_OUTPUT)},		/* vout1_d18.vout1_d18 */
-	{VOUT1_D19, (M0 | PIN_OUTPUT)},		/* vout1_d19.vout1_d19 */
-	{VOUT1_D20, (M0 | PIN_OUTPUT)},		/* vout1_d20.vout1_d20 */
-	{VOUT1_D21, (M0 | PIN_OUTPUT)},		/* vout1_d21.vout1_d21 */
-	{VOUT1_D22, (M0 | PIN_OUTPUT)},		/* vout1_d22.vout1_d22 */
-	{VOUT1_D23, (M0 | PIN_OUTPUT)},		/* vout1_d23.vout1_d23 */
-	{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)},	/* mdio_mclk.mdio_mclk */
-	{MDIO_D, (M0 | PIN_INPUT_PULLUP)},	/* mdio_d.mdio_d */
+	{VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+	{VOUT1_FLD, (M14 | PIN_INPUT)},	/* vout1_fld.gpio4_21 */
+	{MDIO_MCLK, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)},	/* mdio_d.mdio_d */
 	{RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)},	/* RMII_MHZ_50_CLK.gpio5_17 */
-	{UART3_RXD, (M14 | PIN_INPUT_PULLDOWN)},	/* uart3_rxd.gpio5_18 */
-	{UART3_TXD, (M14 | PIN_INPUT_PULLDOWN)},	/* uart3_txd.gpio5_19 */
-	{RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
-	{RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
-	{RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
-	{RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
-	{RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
-	{RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
-	{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
-	{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
-	{RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
-	{RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
-	{RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
-	{RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
-	{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb1_drvvbus.usb1_drvvbus */
-	{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb2_drvvbus.usb2_drvvbus */
+	{UART3_RXD, (M14 | PIN_INPUT_SLEW)},	/* uart3_rxd.gpio5_18 */
+	{UART3_TXD, (M14 | PIN_INPUT_SLEW)},	/* uart3_txd.gpio5_19 */
+	{RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)},	/* usb2_drvvbus.usb2_drvvbus */
 	{GPIO6_14, (M10 | PIN_INPUT_PULLUP)},	/* gpio6_14.timer1 */
 	{GPIO6_15, (M10 | PIN_INPUT_PULLUP)},	/* gpio6_15.timer2 */
 	{GPIO6_16, (M10 | PIN_INPUT_PULLUP)},	/* gpio6_16.timer3 */
-	{XREF_CLK0, (M9 | PIN_INPUT_PULLDOWN)},	/* xref_clk0.clkout2 */
+	{XREF_CLK0, (M9 | PIN_OUTPUT_PULLDOWN)},	/* xref_clk0.clkout2 */
 	{XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)},	/* xref_clk1.gpio6_18 */
 	{XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)},	/* xref_clk2.gpio6_19 */
-	{XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)},	/* xref_clk3.clkout3 */
+	{XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)},	/* xref_clk3.clkout3 */
 	{MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)},	/* mcasp1_aclkx.i2c3_sda */
-	{MCASP1_FSX, (M10 | PIN_INPUT_PULLUP)},	/* mcasp1_fsx.i2c3_scl */
+	{MCASP1_FSX, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_fsx.i2c3_scl */
 	{MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)},	/* mcasp1_aclkr.i2c4_sda */
 	{MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)},	/* mcasp1_fsr.i2c4_scl */
 	{MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr0.i2c5_sda */
@@ -181,109 +152,172 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
 	{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr5.gpio5_7 */
 	{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr6.gpio5_8 */
 	{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr7.gpio5_9 */
-	{MCASP1_AXR8, (M14 | PIN_INPUT_SLEW)},	/* mcasp1_axr8.gpio5_10 */
-	{MCASP1_AXR9, (M14 | PIN_INPUT_SLEW)},	/* mcasp1_axr9.gpio5_11 */
-	{MCASP1_AXR10, (M14 | PIN_INPUT_SLEW)},	/* mcasp1_axr10.gpio5_12 */
+	{MCASP1_AXR8, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mcasp1_axr8.gpio5_10 */
+	{MCASP1_AXR9, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mcasp1_axr9.gpio5_11 */
+	{MCASP1_AXR10, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mcasp1_axr10.gpio5_12 */
 	{MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr11.gpio4_17 */
-	{MCASP1_AXR12, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr12.mcasp7_axr0 */
-	{MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr13.mcasp7_axr1 */
-	{MCASP1_AXR14, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr14.mcasp7_aclkx */
-	{MCASP1_AXR15, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr15.mcasp7_fsx */
-	{MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_aclkx.mcasp2_aclkx */
-	{MCASP2_FSX, (M0 | PIN_INPUT_SLEW)},	/* mcasp2_fsx.mcasp2_fsx */
-	{MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_aclkr.mcasp2_aclkr */
-	{MCASP2_FSR, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_fsr.mcasp2_fsr */
-	{MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr0.mcasp2_axr0 */
-	{MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr1.mcasp2_axr1 */
-	{MCASP2_AXR2, (M0 | PIN_INPUT_SLEW)},	/* mcasp2_axr2.mcasp2_axr2 */
-	{MCASP2_AXR3, (M0 | PIN_INPUT_SLEW)},	/* mcasp2_axr3.mcasp2_axr3 */
-	{MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr4.mcasp2_axr4 */
-	{MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr5.mcasp2_axr5 */
-	{MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr6.mcasp2_axr6 */
-	{MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr7.mcasp2_axr7 */
+	{MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr12.mcasp7_axr0 */
+	{MCASP1_AXR13, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr13.mcasp7_axr1 */
+	{MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr14.mcasp7_aclkx */
+	{MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr15.mcasp7_fsx */
 	{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.mcasp3_aclkx */
-	{MCASP3_FSX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_fsx.mcasp3_fsx */
-	{MCASP3_AXR0, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_axr0.mcasp3_axr0 */
-	{MCASP3_AXR1, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_axr1.mcasp3_axr1 */
-	{MCASP4_ACLKX, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp4_aclkx.uart8_rxd */
-	{MCASP4_FSX, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp4_fsx.uart8_txd */
-	{MCASP4_AXR0, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp4_axr0.uart8_ctsn */
-	{MCASP4_AXR1, (M3 | PIN_INPUT_PULLUP)},	/* mcasp4_axr1.uart8_rtsn */
-	{MCASP5_ACLKX, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp5_aclkx.uart9_rxd */
-	{MCASP5_FSX, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp5_fsx.uart9_txd */
-	{MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp5_axr0.uart9_ctsn */
-	{MCASP5_AXR1, (M3 | PIN_INPUT_PULLUP)},	/* mcasp5_axr1.uart9_rtsn */
+	{MCASP3_FSX, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.mcasp3_fsx */
+	{MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_axr0.mcasp3_axr0 */
+	{MCASP3_AXR1, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_axr1.mcasp3_axr1 */
+	{MCASP4_ACLKX, (M3 | PIN_INPUT_PULLUP)},	/* mcasp4_aclkx.uart8_rxd */
+	{MCASP4_FSX, (M3 | PIN_OUTPUT)},	/* mcasp4_fsx.uart8_txd */
+	{MCASP4_AXR0, (M3 | PIN_INPUT_PULLUP)},	/* mcasp4_axr0.uart8_ctsn */
+	{MCASP4_AXR1, (M3 | PIN_OUTPUT_PULLUP)},	/* mcasp4_axr1.uart8_rtsn */
+	{MCASP5_ACLKX, (M3 | PIN_INPUT_PULLUP)},	/* mcasp5_aclkx.uart9_rxd */
+	{MCASP5_FSX, (M3 | PIN_OUTPUT)},	/* mcasp5_fsx.uart9_txd */
+	{MCASP5_AXR0, (M3 | PIN_INPUT_PULLUP)},	/* mcasp5_axr0.uart9_ctsn */
+	{MCASP5_AXR1, (M3 | PIN_OUTPUT_PULLUP)},	/* mcasp5_axr1.uart9_rtsn */
 	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
 	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
 	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
 	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
 	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
 	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
-	{MMC1_SDCD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_sdcd.mmc1_sdcd */
-	{MMC1_SDWP, (M14 | PIN_OUTPUT)},	/* mmc1_sdwp.gpio6_28 */
-	{GPIO6_10, (M10 | PIN_INPUT_PULLDOWN)},	/* gpio6_10.ehrpwm2A */
-	{GPIO6_11, (M14 | PIN_INPUT_PULLUP)},	/* gpio6_11.gpio6_11 */
-	{MMC3_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc3_clk.mmc3_clk */
-	{MMC3_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc3_cmd.mmc3_cmd */
-	{MMC3_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc3_dat0.mmc3_dat0 */
-	{MMC3_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc3_dat1.mmc3_dat1 */
-	{MMC3_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc3_dat2.mmc3_dat2 */
-	{MMC3_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc3_dat3.mmc3_dat3 */
-	{MMC3_DAT4, (M1 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat4.spi4_sclk */
-	{MMC3_DAT5, (M1 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat5.spi4_d1 */
-	{MMC3_DAT6, (M1 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat6.spi4_d0 */
-	{MMC3_DAT7, (M1 | PIN_INPUT_PULLUP)},	/* mmc3_dat7.spi4_cs0 */
+	{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mmc1_sdcd.gpio6_27 */
+	{GPIO6_10, (M10 | PIN_OUTPUT_PULLDOWN)},	/* gpio6_10.ehrpwm2A */
+	{GPIO6_11, (M0 | PIN_INPUT_PULLUP)},	/* gpio6_11.gpio6_11 */
+	{MMC3_CLK, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_clk.mmc3_clk */
+	{MMC3_CMD, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_cmd.mmc3_cmd */
+	{MMC3_DAT0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat0.mmc3_dat0 */
+	{MMC3_DAT1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat1.mmc3_dat1 */
+	{MMC3_DAT2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat2.mmc3_dat2 */
+	{MMC3_DAT3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat3.mmc3_dat3 */
+	{MMC3_DAT4, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat4.mmc3_dat4 */
+	{MMC3_DAT5, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat5.mmc3_dat5 */
+	{MMC3_DAT6, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat6.mmc3_dat6 */
+	{MMC3_DAT7, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* mmc3_dat7.mmc3_dat7 */
 	{SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_sclk.gpio7_7 */
 	{SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_d1.gpio7_8 */
 	{SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_d0.gpio7_9 */
-	{SPI1_CS0, (M14 | PIN_OUTPUT)},		/* spi1_cs0.gpio7_10 */
-	{SPI1_CS1, (M14 | PIN_OUTPUT_PULLUP)},	/* spi1_cs1.gpio7_11 */
-	{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_cs2.gpio7_12 */
+	{SPI1_CS0, (M14 | PIN_INPUT)},	/* spi1_cs0.gpio7_10 */
+	{SPI1_CS1, (M14 | PIN_INPUT)},	/* spi1_cs1.gpio7_11 */
+	{SPI1_CS2, (M14 | PIN_INPUT_SLEW)},	/* spi1_cs2.gpio7_12 */
 	{SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
 	{SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)},	/* spi2_sclk.gpio7_14 */
-	{SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)},	/* spi2_d1.gpio7_15 */
-	{SPI2_D0, (M14 | PIN_INPUT_PULLUP)},	/* spi2_d0.gpio7_16 */
+	{SPI2_D1, (M14 | PIN_INPUT_SLEW)},	/* spi2_d1.gpio7_15 */
+	{SPI2_D0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi2_d0.gpio7_16 */
 	{SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi2_cs0.gpio7_17 */
-	{DCAN1_TX, (M15 | PULL_UP)},	/* dcan1_tx.safe for dcan1_tx */
-	{DCAN1_RX, (M15 | PULL_UP)},	/* dcan1_rx.safe for dcan1_rx */
-	{UART1_RXD, (M0 | PIN_INPUT_SLEW)},	/* uart1_rxd.uart1_rxd */
-	{UART1_TXD, (M0 | PIN_INPUT_SLEW)},	/* uart1_txd.uart1_txd */
-	{UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)},	/* uart1_ctsn.Driveroff */
-	{UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)},	/* N/A.Driveroff */
-	{UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)},	/* uart2_txd.Driveroff */
-	{UART2_CTSN, (M2 | PIN_INPUT_SLEW)},	/* uart2_ctsn.uart3_rxd */
-	{UART2_RTSN, (M1 | PIN_INPUT_SLEW)},	/* uart2_rtsn.uart3_txd */
-	{I2C2_SDA, (M1 | PIN_INPUT)},		/* i2c2_sda.hdmi1_ddc_scl */
-	{I2C2_SCL, (M1 | PIN_INPUT)},		/* i2c2_scl.hdmi1_ddc_sda */
-	{WAKEUP0, (M0 | PULL_UP)},		/* Wakeup0.Wakeup0 */
-	{WAKEUP1, (M0)},			/* Wakeup1.Wakeup1 */
-	{WAKEUP2, (M0)},			/* Wakeup2.Wakeup2 */
-	{WAKEUP3, (M0 | PULL_UP)},		/* Wakeup3.Wakeup3 */
-	{ON_OFF, (M1 | PIN_OUTPUT_PULLUP)},	/* on_off.on_off */
-	{RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)},	/* rtc_porz.rtc_porz */
-	{RTCK, (M0 | PIN_INPUT_PULLDOWN)},	/* rtck.rtck */
+	{DCAN1_TX, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* dcan1_tx.dcan1_tx */
+	{DCAN1_RX, (M0 | PIN_INPUT | SLEWCONTROL)},	/* dcan1_rx.dcan1_rx */
+	{UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_rxd.uart1_rxd */
+	{UART1_TXD, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* uart1_txd.uart1_txd */
+	{UART1_CTSN, (M14 | PIN_INPUT_PULLDOWN)},	/* uart1_ctsn.gpio7_24 */
+	{UART1_RTSN, (M14 | PIN_INPUT)},	/* uart1_rtsn.gpio7_25 */
+	{UART2_RXD, (M14 | PIN_INPUT_PULLDOWN)},	/* uart2_rxd.gpio7_26 */
+	{UART2_TXD, (M14 | PIN_INPUT_PULLDOWN)},	/* uart2_txd.gpio7_27 */
+	{UART2_CTSN, (M2 | PIN_INPUT_PULLUP)},	/* uart2_ctsn.uart3_rxd */
+	{UART2_RTSN, (M1 | PIN_OUTPUT)},	/* uart2_rtsn.uart3_txd */
+	{I2C1_SDA, (M0 | PIN_INPUT_PULLUP)},	/* i2c1_sda.i2c1_sda */
+	{I2C1_SCL, (M0 | PIN_INPUT_PULLUP)},	/* i2c1_scl.i2c1_scl */
+	{I2C2_SDA, (M1 | PIN_INPUT_PULLUP)},	/* i2c2_sda.hdmi1_ddc_scl */
+	{I2C2_SCL, (M1 | PIN_INPUT_PULLUP)},	/* i2c2_scl.hdmi1_ddc_sda */
+	{WAKEUP0, (M0 | PIN_INPUT)},	/* Wakeup0.Wakeup0 */
+	{WAKEUP1, (M0 | PIN_INPUT)},	/* Wakeup1.Wakeup1 */
+	{WAKEUP2, (M0 | PIN_INPUT)},	/* Wakeup2.Wakeup2 */
+	{WAKEUP3, (M0 | PIN_INPUT)},	/* Wakeup3.Wakeup3 */
+	{ON_OFF, (M0 | PIN_OUTPUT)},	/* on_off.on_off */
+	{RTC_PORZ, (M0 | PIN_INPUT)},	/* rtc_porz.rtc_porz */
+	{TMS, (M0 | PIN_INPUT_PULLUP)},	/* tms.tms */
+	{TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* tdi.tdi */
+	{TDO, (M0 | PIN_OUTPUT)},	/* tdo.tdo */
+	{TCLK, (M0 | PIN_INPUT_PULLDOWN)},	/* tclk.tclk */
+	{TRSTN, (M0 | PIN_INPUT)},	/* trstn.trstn */
+	{RTCK, (M0 | PIN_OUTPUT)},	/* rtck.rtck */
+	{EMU0, (M0 | PIN_INPUT)},	/* emu0.emu0 */
+	{EMU1, (M0 | PIN_INPUT)},	/* emu1.emu1 */
+	{NMIN_DSP, (M0 | PIN_INPUT)},	/* nmin_dsp.nmin_dsp */
+	{RSTOUTN, (M0 | PIN_OUTPUT)},	/* rstoutn.rstoutn */
+};
+
+const struct pad_conf_entry core_padconf_array_delta_x15_sr1_1[] = {
+	{MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mmc1_sdwp.gpio6_28 */
+	{VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_de.vout1_de */
+	{VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d23.vout1_d23 */
+};
+
+const struct pad_conf_entry core_padconf_array_delta_x15_sr2_0[] = {
+	{VIN1A_CLK0, (M14 | PIN_INPUT)},	/* vin1a_clk0.gpio2_30 */
+	{VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_de.vout1_de */
+	{VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d23.vout1_d23 */
 };
 
 const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = {
-	{GPMC_A0, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a0.vin4b_d0 */
-	{GPMC_A1, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a1.vin4b_d1 */
-	{GPMC_A2, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a2.vin4b_d2 */
-	{GPMC_A3, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a3.vin4b_d3 */
-	{GPMC_A4, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a4.vin4b_d4 */
-	{GPMC_A5, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a5.vin4b_d5 */
-	{GPMC_A6, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a6.vin4b_d6 */
-	{GPMC_A7, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a7.vin4b_d7 */
-	{GPMC_A8, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a8.vin4b_hsync1 */
-	{GPMC_A9, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a9.vin4b_vsync1 */
-	{GPMC_A10, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a10.vin4b_clk1 */
-	{GPMC_A11, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a11.vin4b_de1 */
-	{GPMC_A12, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a12.vin4b_fld1 */
-	{GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a13.qspi1_rtclk */
-	{GPMC_A14, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a14.qspi1_d3 */
-	{GPMC_A15, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a15.qspi1_d2 */
-	{GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a16.qspi1_d0 */
-	{GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a17.qspi1_d1 */
-	{GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a18.qspi1_sclk */
+	{GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a0.vin4b_d0 */
+	{GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a1.vin4b_d1 */
+	{GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a2.vin4b_d2 */
+	{GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a3.vin4b_d3 */
+	{GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a4.vin4b_d4 */
+	{GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a5.vin4b_d5 */
+	{GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a6.vin4b_d6 */
+	{GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a7.vin4b_d7 */
+	{GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a8.vin4b_hsync1 */
+	{GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a9.vin4b_vsync1 */
+	{GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a10.vin4b_clk1 */
+	{GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a11.vin4b_de1 */
+	{GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a12.vin4b_fld1 */
+	{GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a13.qspi1_rtclk */
+	{GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a14.qspi1_d3 */
+	{GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a15.qspi1_d2 */
+	{GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a16.qspi1_d0 */
+	{GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a17.qspi1_d1 */
+	{GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)},	/* gpmc_a18.qspi1_sclk */
 	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a19.mmc2_dat4 */
 	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a20.mmc2_dat5 */
 	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a21.mmc2_dat6 */
@@ -294,190 +328,450 @@ const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = {
 	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a26.mmc2_dat2 */
 	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a27.mmc2_dat3 */
 	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
-	{GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_cs2.qspi1_cs0 */
-	{VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d5.gpio3_9 */
-	{VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d6.gpio3_10 */
-	{VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d7.gpio3_11 */
-	{VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d8.gpio3_12 */
+	{GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)},	/* gpmc_cs2.qspi1_cs0 */
+	{VIN1A_D5, (M14 | PIN_OUTPUT)},	/* vin1a_d5.gpio3_9 */
+	{VIN1A_D6, (M14 | PIN_OUTPUT)},	/* vin1a_d6.gpio3_10 */
+	{VIN1A_D7, (M14 | PIN_OUTPUT)},	/* vin1a_d7.gpio3_11 */
+	{VIN1A_D8, (M14 | PIN_OUTPUT)},	/* vin1a_d8.gpio3_12 */
 	{VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d10.gpio3_14 */
-	{VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d12.gpio3_16 */
-	{VIN1A_D13, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d13.gpio3_17 */
-	{VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d14.gpio3_18 */
-	{VIN1A_D15, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d15.gpio3_19 */
-	{VIN1A_D17, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d17.gpio3_21 */
-	{VIN1A_D18, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d18.gpio3_22 */
-	{VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d19.gpio3_23 */
-	{VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)},	/* vin1a_d22.gpio3_26 */
-	{VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)},		/* vin2a_clk0.gpio3_28 */
-	{VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)},		/* vin2a_de0.gpio3_29 */
-	{VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)},		/* vin2a_fld0.gpio3_30 */
+	{VIN1A_D12, (M14 | PIN_INPUT)},	/* vin1a_d12.gpio3_16 */
+	{VIN1A_D13, (M14 | PIN_OUTPUT)},	/* vin1a_d13.gpio3_17 */
+	{VIN1A_D14, (M14 | PIN_OUTPUT)},	/* vin1a_d14.gpio3_18 */
+	{VIN1A_D15, (M14 | PIN_OUTPUT)},	/* vin1a_d15.gpio3_19 */
+	{VIN1A_D17, (M14 | PIN_OUTPUT)},	/* vin1a_d17.gpio3_21 */
+	{VIN1A_D18, (M14 | PIN_OUTPUT_PULLDOWN)},	/* vin1a_d18.gpio3_22 */
+	{VIN1A_D19, (M14 | PIN_OUTPUT_PULLUP)},	/* vin1a_d19.gpio3_23 */
+	{VIN1A_D22, (M14 | PIN_INPUT)},	/* vin1a_d22.gpio3_26 */
+	{VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_clk0.gpio3_28 */
+	{VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_de0.gpio3_29 */
+	{VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_fld0.gpio3_30 */
 	{VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_hsync0.gpio3_31 */
-	{VIN2A_VSYNC0, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_vsync0.gpio4_0 */
-	{VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d0.pr1_uart0_rxd */
-	{VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d1.pr1_uart0_txd */
-	{VIN2A_D2, (M10 | PIN_INPUT_PULLDOWN)},	/* vin2a_d2.ecap1 */
-	{VIN2A_D3, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d3.gpio4_4 */
-	{VIN2A_D4, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d4.gpio4_5 */
-	{VIN2A_D5, (M13 | PIN_INPUT_PULLDOWN)},	/* vin2a_d5.pr1_pru1_gpo2 */
-	{VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d6.pr1_mii_mt1_clk */
-	{VIN2A_D7, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d7.pr1_mii_mii1_txen */
-	{VIN2A_D8, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d8.pr1_mii_mii1_txd3 */
-	{VIN2A_D9, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d9.pr1_mii_mii1_txd2 */
-	{VIN2A_D10, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d10.pr1_mdio_mdclk */
-	{VIN2A_D11, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d11.pr1_mdio_data */
-	{VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
-	{VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
-	{VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
-	{VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
-	{VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
-	{VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_VSYNC0, (M14 | PIN_INPUT)},	/* vin2a_vsync0.gpio4_0 */
+	{VIN2A_D0, (M11 | PIN_INPUT)},	/* vin2a_d0.pr1_uart0_rxd */
+	{VIN2A_D1, (M11 | PIN_OUTPUT)},	/* vin2a_d1.pr1_uart0_txd */
+	{VIN2A_D2, (M10 | PIN_OUTPUT)},	/* vin2a_d2.eCAP1_in_PWM1_out */
+	{VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)},	/* vin2a_d3.pr1_edc_latch0_in */
+	{VIN2A_D4, (M11 | PIN_OUTPUT)},	/* vin2a_d4.pr1_edc_sync0_out */
+	{VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d5.pr1_pru1_gpo2 */
+	{VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)},	/* vin2a_d10.pr1_mdio_mdclk */
+	{VIN2A_D11, (M11 | PIN_INPUT)},	/* vin2a_d11.pr1_mdio_data */
+	{VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
 	{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
-	{VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
 	{VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
 	{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
 	{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
 	{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
-	{VOUT1_CLK, (M0 | PIN_OUTPUT)},		/* vout1_clk.vout1_clk */
-	{VOUT1_DE, (M0 | PIN_OUTPUT)},		/* vout1_de.vout1_de */
-	{VOUT1_FLD, (M14 | PIN_INPUT)},		/* vout1_fld.gpio4_21 */
-	{VOUT1_HSYNC, (M0 | PIN_OUTPUT)},	/* vout1_hsync.vout1_hsync */
-	{VOUT1_VSYNC, (M0 | PIN_OUTPUT)},	/* vout1_vsync.vout1_vsync */
-	{VOUT1_D0, (M0 | PIN_OUTPUT)},		/* vout1_d0.vout1_d0 */
-	{VOUT1_D1, (M0 | PIN_OUTPUT)},		/* vout1_d1.vout1_d1 */
-	{VOUT1_D2, (M0 | PIN_OUTPUT)},		/* vout1_d2.vout1_d2 */
-	{VOUT1_D3, (M0 | PIN_OUTPUT)},		/* vout1_d3.vout1_d3 */
-	{VOUT1_D4, (M0 | PIN_OUTPUT)},		/* vout1_d4.vout1_d4 */
-	{VOUT1_D5, (M0 | PIN_OUTPUT)},		/* vout1_d5.vout1_d5 */
-	{VOUT1_D6, (M0 | PIN_OUTPUT)},		/* vout1_d6.vout1_d6 */
-	{VOUT1_D7, (M0 | PIN_OUTPUT)},		/* vout1_d7.vout1_d7 */
-	{VOUT1_D8, (M0 | PIN_OUTPUT)},		/* vout1_d8.vout1_d8 */
-	{VOUT1_D9, (M0 | PIN_OUTPUT)},		/* vout1_d9.vout1_d9 */
-	{VOUT1_D10, (M0 | PIN_OUTPUT)},		/* vout1_d10.vout1_d10 */
-	{VOUT1_D11, (M0 | PIN_OUTPUT)},		/* vout1_d11.vout1_d11 */
-	{VOUT1_D12, (M0 | PIN_OUTPUT)},		/* vout1_d12.vout1_d12 */
-	{VOUT1_D13, (M0 | PIN_OUTPUT)},		/* vout1_d13.vout1_d13 */
-	{VOUT1_D14, (M0 | PIN_OUTPUT)},		/* vout1_d14.vout1_d14 */
-	{VOUT1_D15, (M0 | PIN_OUTPUT)},		/* vout1_d15.vout1_d15 */
-	{VOUT1_D16, (M0 | PIN_OUTPUT)},		/* vout1_d16.vout1_d16 */
-	{VOUT1_D17, (M0 | PIN_OUTPUT)},		/* vout1_d17.vout1_d17 */
-	{VOUT1_D18, (M0 | PIN_OUTPUT)},		/* vout1_d18.vout1_d18 */
-	{VOUT1_D19, (M0 | PIN_OUTPUT)},		/* vout1_d19.vout1_d19 */
-	{VOUT1_D20, (M0 | PIN_OUTPUT)},		/* vout1_d20.vout1_d20 */
-	{VOUT1_D21, (M0 | PIN_OUTPUT)},		/* vout1_d21.vout1_d21 */
-	{VOUT1_D22, (M0 | PIN_OUTPUT)},		/* vout1_d22.vout1_d22 */
-	{VOUT1_D23, (M0 | PIN_OUTPUT)},		/* vout1_d23.vout1_d23 */
-	{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)},	/* mdio_mclk.mdio_mclk */
-	{MDIO_D, (M0 | PIN_INPUT_PULLUP)},	/* mdio_d.mdio_d */
-	{RMII_MHZ_50_CLK, (M13 | PIN_INPUT_PULLDOWN)},	/* RMII_MHZ_50_CLK.pr2_pru1_gpo2 */
-	{UART3_RXD, (M11 | PIN_INPUT_PULLDOWN)},	/* uart3_rxd.pr1_mii0_rxdv */
-	{UART3_TXD, (M11 | PIN_INPUT_PULLDOWN)},	/* uart3_txd.rp1_mii_mr0_clk */
-	{RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
-	{RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
-	{RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
-	{RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
-	{RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
-	{RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_de.vout1_de */
+	{VOUT1_FLD, (M14 | PIN_OUTPUT)},	/* vout1_fld.gpio4_21 */
+	{VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)},	/* vout1_d23.vout1_d23 */
+	{MDIO_MCLK, (M0 | PIN_INPUT_SLEW)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)},	/* mdio_d.mdio_d */
+	{RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
 	{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
 	{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
 	{RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
 	{RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
 	{RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
 	{RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
-	{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)},  /* usb1_drvvbus.usb1_drvvbus */
-	{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)},  /* usb2_drvvbus.usb2_drvvbus */
-	{GPIO6_14, (M14 | PIN_OUTPUT_PULLUP)},  /* gpio6_14.gpio6_14 */
-	{GPIO6_15, (M0  | PIN_OUTPUT_PULLUP)},  /* gpio6_15.gpio6_15 */
-	{GPIO6_16, (M0 | PIN_INPUT_PULLDOWN)},	/* gpio6_16.gpio6)_16 */
+	{USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* usb2_drvvbus.usb2_drvvbus */
+	{GPIO6_14, (M0 | PIN_OUTPUT)},	/* gpio6_14.gpio6_14 */
+	{GPIO6_15, (M0 | PIN_OUTPUT)},	/* gpio6_15.gpio6_15 */
+	{GPIO6_16, (M0 | PIN_INPUT_PULLUP)},	/* gpio6_16.gpio6_16 */
 	{XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)},	/* xref_clk0.pr2_mii1_col */
 	{XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)},	/* xref_clk1.pr2_mii1_crs */
-	{XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)},	/* xref_clk2.i6_19 */
-	{XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)},	/* xref_clk3.clkout3 */
-	{MCASP1_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp1_aclkx.pr2_mdio_mdclk */
-	{MCASP1_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_fsx.pr2_mdio_data */
-	{MCASP1_ACLKR, (M14 | PIN_INPUT_PULLUP)},	/* mcasp1_aclkr.gpio5_0 */
-	{MCASP1_FSR, (M14 | PIN_INPUT_PULLUP)},	/* mcasp1_fsr.gpio5_1 */
+	{XREF_CLK2, (M14 | PIN_OUTPUT)},	/* xref_clk2.gpio6_19 */
+	{XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)},	/* xref_clk3.clkout3 */
+	{MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)},	/* mcasp1_aclkx.pr2_mdio_mdclk */
+	{MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)},	/* mcasp1_fsx.pr2_mdio_data */
+	{MCASP1_ACLKR, (M14 | PIN_INPUT)},	/* mcasp1_aclkr.gpio5_0 */
+	{MCASP1_FSR, (M14 | PIN_INPUT)},	/* mcasp1_fsr.gpio5_1 */
 	{MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr0.pr2_mii0_rxer */
-	{MCASP1_AXR1, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr1.pr2_mii_mt0_clk */
-	{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr2.gpio5_4 */
-	{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr3.gpio5_5 */
-	{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr4.gpio5_6 */
-	{MCASP1_AXR5, (M14 | PIN_OUTPUT_PULLUP)},	/* mcasp1_axr5.gpio5_7 */
-	{MCASP1_AXR6, (M14 | PIN_OUTPUT_PULLUP)},	/* mcasp1_axr6.gpio5_8 */
-	{MCASP1_AXR7, (M14 | PIN_OUTPUT_PULLUP)},	/* mcasp1_axr7.gpio5_9 */
-	{MCASP1_AXR8, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr8.pr2_mii0_txen */
-	{MCASP1_AXR9, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr9.pr2_mii0_txd3 */
-	{MCASP1_AXR10, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr10.pr2_mii0_txd2 */
-	{MCASP1_AXR11, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr11.pr2_mii0_txd1 */
-	{MCASP1_AXR12, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr12.pr2_mii0_txd0 */
-	{MCASP1_AXR13, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr13.pr2_mii_mr0_clk */
-	{MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},	/* mcasp1_axr14.pr2_mii0_rxdv */
+	{MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr1.pr2_mii_mt0_clk */
+	{MCASP1_AXR2, (M14 | PIN_INPUT)},	/* mcasp1_axr2.gpio5_4 */
+	{MCASP1_AXR3, (M14 | PIN_INPUT)},	/* mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR4, (M14 | PIN_OUTPUT)},	/* mcasp1_axr4.gpio5_6 */
+	{MCASP1_AXR5, (M14 | PIN_OUTPUT)},	/* mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR6, (M14 | PIN_OUTPUT)},	/* mcasp1_axr6.gpio5_8 */
+	{MCASP1_AXR7, (M14 | PIN_OUTPUT)},	/* mcasp1_axr7.gpio5_9 */
+	{MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr8.pr2_mii0_txen */
+	{MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr9.pr2_mii0_txd3 */
+	{MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr10.pr2_mii0_txd2 */
+	{MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr11.pr2_mii0_txd1 */
+	{MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr12.pr2_mii0_txd0 */
+	{MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr13.pr2_mii_mr0_clk */
+	{MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr14.pr2_mii0_rxdv */
 	{MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr15.pr2_mii0_rxd3 */
-	{MCASP2_ACLKX, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_aclkx.pr2_mii0_rxd2 */
+	{MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp2_aclkx.pr2_mii0_rxd2 */
 	{MCASP2_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_fsx.pr2_mii0_rxd1 */
 	{MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_axr2.pr2_mii0_rxd0 */
-	{MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)},	/* mcasp2_axr3.pr2_mii0_rxlink */
-	{MCASP2_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr4.gpio1_4 */
-	{MCASP2_AXR5, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr5.gpio6_7 */
-	{MCASP2_AXR6, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr6.gpio2_29 */
-	{MCASP2_AXR7, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr7.gpio1_5 */
+	{MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_axr3.pr2_mii0_rxlink */
+	{MCASP2_AXR4, (M14 | PIN_OUTPUT)},	/* mcasp2_axr4.gpio1_4 */
+	{MCASP2_AXR5, (M14 | PIN_OUTPUT)},	/* mcasp2_axr5.gpio6_7 */
+	{MCASP2_AXR6, (M14 | PIN_OUTPUT)},	/* mcasp2_axr6.gpio2_29 */
+	{MCASP2_AXR7, (M14 | PIN_OUTPUT)},	/* mcasp2_axr7.gpio1_5 */
 	{MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.pr2_mii0_crs */
 	{MCASP3_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.pr2_mii0_col */
 	{MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp3_axr0.pr2_mii1_rxer */
 	{MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp3_axr1.pr2_mii1_rxlink */
-	{MCASP4_ACLKX, (M2 | PIN_INPUT_PULLDOWN)},	/* mcasp4_aclkx.spi3_sclk */
-	{MCASP4_FSX, (M2 | PIN_INPUT_PULLDOWN)},	/* mcasp4_fsx.spi3_d1 */
+	{MCASP4_ACLKX, (M2 | PIN_INPUT)},	/* mcasp4_aclkx.spi3_sclk */
+	{MCASP4_FSX, (M2 | PIN_INPUT)},	/* mcasp4_fsx.spi3_d1 */
 	{MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)},	/* mcasp4_axr1.spi3_cs0 */
-	{MCASP5_ACLKX, (M13 | PIN_INPUT_PULLDOWN)},	/* mcasp5_aclkx.pr2_pru1_gpo1 */
-	{MCASP5_FSX, (M12 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},/* mcasp5_fsx.pr2_pru1_gpi2 */
-	{MCASP5_AXR0, (M13 | PIN_INPUT_PULLDOWN)},	/* mcasp5_axr0.pr2_pru1_gpo3 */
-	{MCASP5_AXR1, (M13 | PIN_INPUT_PULLDOWN)},	/* mcasp5_axr1.pr2_pru1_gpo4 */
+	{MCASP5_ACLKX, (M13 | PIN_OUTPUT | MANUAL_MODE)},	/* mcasp5_aclkx.pr2_pru1_gpo1 */
+	{MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)},	/* mcasp5_fsx.pr2_pru1_gpi2 */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
+	{MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mmc1_sdcd.gpio6_27 */
+	{MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mmc1_sdwp.gpio6_28 */
 	{GPIO6_10, (M11 | PIN_INPUT_PULLUP)},	/* gpio6_10.pr2_mii_mt1_clk */
-	{GPIO6_11, (M11 | PIN_INPUT_PULLUP)},	/* gpio6_11.pr2_mii1_txen */
-	{MMC3_CLK, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_clk.pr2_mii1_txd3 */
-	{MMC3_CMD, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_cmd.pr2_mii1_txd2 */
-	{MMC3_DAT0, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_dat0.pr2_mii1_txd1 */
-	{MMC3_DAT1, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_dat1.pr2_mii1_txd0 */
+	{GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)},	/* gpio6_11.pr2_mii1_txen */
+	{MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_clk.pr2_mii1_txd3 */
+	{MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_cmd.pr2_mii1_txd2 */
+	{MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat0.pr2_mii1_txd1 */
+	{MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat1.pr2_mii1_txd0 */
 	{MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_dat2.pr2_mii_mr1_clk */
 	{MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat3.pr2_mii1_rxdv */
 	{MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat4.pr2_mii1_rxd3 */
 	{MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat5.pr2_mii1_rxd2 */
 	{MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat6.pr2_mii1_rxd1 */
 	{MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat7.pr2_mii1_rxd0 */
-	{SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_sclk.gpio7_7 */
-	{SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_d1.gpio7_8 */
-	{SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_d0.gpio7_9 */
-	{SPI1_CS0, (M14 | PIN_OUTPUT)},		/* spi1_cs0.gpio7_10 */
-	{SPI1_CS1, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_cs1.gpio7_11 */
+	{SPI1_SCLK, (M14 | PIN_OUTPUT)},	/* spi1_sclk.gpio7_7 */
+	{SPI1_D1, (M14 | PIN_OUTPUT)},	/* spi1_d1.gpio7_8 */
+	{SPI1_D0, (M14 | PIN_OUTPUT)},	/* spi1_d0.gpio7_9 */
+	{SPI1_CS0, (M14 | PIN_OUTPUT)},	/* spi1_cs0.gpio7_10 */
+	{SPI1_CS1, (M14 | PIN_OUTPUT)},	/* spi1_cs1.gpio7_11 */
+	{SPI1_CS2, (M14 | PIN_INPUT_SLEW)},	/* spi1_cs2.gpio7_12 */
+	{SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
+	{SPI2_SCLK, (M0 | PIN_INPUT)},	/* spi2_sclk.spi2_sclk */
+	{SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)},	/* spi2_d1.spi2_d1 */
+	{SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)},	/* spi2_d0.spi2_d0 */
+	{SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)},	/* spi2_cs0.spi2_cs0 */
+	{DCAN1_TX, (M15 | PULL_UP)},	/* dcan1_tx.safe for dcan1_tx */
+	{DCAN1_RX, (M15 | PULL_UP)},	/* dcan1_rx.safe for dcan1_rx */
+	{UART1_RXD, (M14 | PIN_OUTPUT | SLEWCONTROL)},	/* uart1_rxd.gpio7_22 */
+	{UART1_TXD, (M14 | PIN_OUTPUT | SLEWCONTROL)},	/* uart1_txd.gpio7_23 */
+	{UART2_RXD, (M4 | PIN_INPUT)},	/* uart2_rxd.uart2_rxd */
+	{UART2_TXD, (M0 | PIN_OUTPUT)},	/* uart2_txd.uart2_txd */
+	{UART2_CTSN, (M2 | PIN_INPUT)},	/* uart2_ctsn.uart3_rxd */
+	{UART2_RTSN, (M1 | PIN_OUTPUT)},	/* uart2_rtsn.uart3_txd */
+	{I2C1_SDA, (M0 | PIN_INPUT)},	/* i2c1_sda.i2c1_sda */
+	{I2C1_SCL, (M0 | PIN_INPUT)},	/* i2c1_scl.i2c1_scl */
+	{I2C2_SDA, (M1 | PIN_INPUT)},	/* i2c2_sda.hdmi1_ddc_scl */
+	{I2C2_SCL, (M1 | PIN_INPUT)},	/* i2c2_scl.hdmi1_ddc_sda */
+	{WAKEUP0, (M0 | PIN_INPUT)},	/* Wakeup0.Wakeup0 */
+	{WAKEUP1, (M0 | PIN_INPUT)},	/* Wakeup1.Wakeup1 */
+	{WAKEUP2, (M0 | PIN_INPUT)},	/* Wakeup2.Wakeup2 */
+	{WAKEUP3, (M0 | PIN_INPUT)},	/* Wakeup3.Wakeup3 */
+	{ON_OFF, (M0 | PIN_OUTPUT)},	/* on_off.on_off */
+	{RTC_PORZ, (M0 | PIN_INPUT)},	/* rtc_porz.rtc_porz */
+	{TMS, (M0 | PIN_INPUT_PULLUP)},	/* tms.tms */
+	{TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* tdi.tdi */
+	{TDO, (M0 | PIN_OUTPUT_PULLUP)},	/* tdo.tdo */
+	{TCLK, (M0 | PIN_INPUT_PULLUP)},	/* tclk.tclk */
+	{TRSTN, (M0 | PIN_INPUT_PULLDOWN)},	/* trstn.trstn */
+	{RTCK, (M0 | PIN_OUTPUT_PULLUP)},	/* rtck.rtck */
+	{EMU0, (M0 | PIN_INPUT_PULLUP)},	/* emu0.emu0 */
+	{EMU1, (M0 | PIN_INPUT_PULLUP)},	/* emu1.emu1 */
+	{RESETN, (M0 | PIN_INPUT)},	/* resetn.resetn */
+	{NMIN_DSP, (M0 | PIN_INPUT)},	/* nmin_dsp.nmin_dsp */
+	{RSTOUTN, (M0 | PIN_OUTPUT)},	/* rstoutn.rstoutn */
+};
+
+const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = {
+	{GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a0.vin1b_d0 */
+	{GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a1.vin1b_d1 */
+	{GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a2.vin1b_d2 */
+	{GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a3.vin1b_d3 */
+	{GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a4.vin1b_d4 */
+	{GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a5.vin1b_d5 */
+	{GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a6.vin1b_d6 */
+	{GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a7.vin1b_d7 */
+	{GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a8.vin1b_hsync1 */
+	{GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a9.vin1b_vsync1 */
+	{GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a10.vin1b_clk1 */
+	{GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a11.vin1b_de1 */
+	{GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a12.vin1b_fld1 */
+	{GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a13.qspi1_rtclk */
+	{GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a14.qspi1_d3 */
+	{GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a15.qspi1_d2 */
+	{GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a16.qspi1_d0 */
+	{GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)},	/* gpmc_a17.qspi1_d1 */
+	{GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)},	/* gpmc_a18.qspi1_sclk */
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
+	{GPMC_CS0, (M14 | PIN_OUTPUT)},	/* gpmc_cs0.gpio2_19 */
+	{GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)},	/* gpmc_cs2.qspi1_cs0 */
+	{GPMC_CS3, (M14 | PIN_OUTPUT)},	/* gpmc_cs3.gpio2_21 */
+	{GPMC_CLK, (M14 | PIN_INPUT)},	/* gpmc_clk.gpio2_22 */
+	{GPMC_ADVN_ALE, (M14 | PIN_OUTPUT)},	/* gpmc_advn_ale.gpio2_23 */
+	{GPMC_OEN_REN, (M14 | PIN_OUTPUT)},	/* gpmc_oen_ren.gpio2_24 */
+	{GPMC_WEN, (M14 | PIN_OUTPUT)},	/* gpmc_wen.gpio2_25 */
+	{GPMC_BEN0, (M14 | PIN_OUTPUT)},	/* gpmc_ben0.gpio2_26 */
+	{GPMC_BEN1, (M14 | PIN_OUTPUT)},	/* gpmc_ben1.gpio2_27 */
+	{GPMC_WAIT0, (M14 | PIN_OUTPUT | SLEWCONTROL)},	/* gpmc_wait0.gpio2_28 */
+	{VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_clk0.gpio3_28 */
+	{VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_de0.gpio3_29 */
+	{VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_fld0.gpio3_30 */
+	{VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_hsync0.gpio3_31 */
+	{VIN2A_VSYNC0, (M14 | PIN_OUTPUT)},	/* vin2a_vsync0.gpio4_0 */
+	{VIN2A_D0, (M11 | PIN_INPUT)},	/* vin2a_d0.pr1_uart0_rxd */
+	{VIN2A_D1, (M11 | PIN_OUTPUT)},	/* vin2a_d1.pr1_uart0_txd */
+	{VIN2A_D2, (M10 | PIN_OUTPUT)},	/* vin2a_d2.eCAP1_in_PWM1_out */
+	{VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)},	/* vin2a_d10.pr1_mdio_mdclk */
+	{VIN2A_D11, (M11 | PIN_INPUT)},	/* vin2a_d11.pr1_mdio_data */
+	{VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+	{VOUT1_FLD, (M14 | PIN_OUTPUT)},	/* vout1_fld.gpio4_21 */
+	{MDIO_MCLK, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)},	/* mdio_d.mdio_d */
+	{UART3_RXD, (M14 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* uart3_rxd.gpio5_18 */
+	{UART3_TXD, (M14 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)},	/* uart3_txd.gpio5_19 */
+	{RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* usb2_drvvbus.usb2_drvvbus */
+	{GPIO6_14, (M0 | PIN_OUTPUT)},	/* gpio6_14.gpio6_14 */
+	{GPIO6_15, (M0 | PIN_OUTPUT)},	/* gpio6_15.gpio6_15 */
+	{GPIO6_16, (M0 | PIN_INPUT_PULLUP)},	/* gpio6_16.gpio6_16 */
+	{XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)},	/* xref_clk0.pr2_mii1_col */
+	{XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)},	/* xref_clk1.pr2_mii1_crs */
+	{XREF_CLK2, (M14 | PIN_OUTPUT)},	/* xref_clk2.gpio6_19 */
+	{XREF_CLK3, (M7 | PIN_INPUT)},	/* xref_clk3.hdq0 */
+	{MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)},	/* mcasp1_aclkx.pr2_mdio_mdclk */
+	{MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)},	/* mcasp1_fsx.pr2_mdio_data */
+	{MCASP1_ACLKR, (M14 | PIN_INPUT)},	/* mcasp1_aclkr.gpio5_0 */
+	{MCASP1_FSR, (M14 | PIN_INPUT)},	/* mcasp1_fsr.gpio5_1 */
+	{MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr0.pr2_mii0_rxer */
+	{MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr1.pr2_mii_mt0_clk */
+	{MCASP1_AXR2, (M14 | PIN_INPUT)},	/* mcasp1_axr2.gpio5_4 */
+	{MCASP1_AXR3, (M14 | PIN_INPUT)},	/* mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr4.gpio5_6 */
+	{MCASP1_AXR5, (M14 | PIN_INPUT)},	/* mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR6, (M14 | PIN_OUTPUT)},	/* mcasp1_axr6.gpio5_8 */
+	{MCASP1_AXR7, (M14 | PIN_OUTPUT)},	/* mcasp1_axr7.gpio5_9 */
+	{MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr8.pr2_mii0_txen */
+	{MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr9.pr2_mii0_txd3 */
+	{MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr10.pr2_mii0_txd2 */
+	{MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr11.pr2_mii0_txd1 */
+	{MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr12.pr2_mii0_txd0 */
+	{MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr13.pr2_mii_mr0_clk */
+	{MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr14.pr2_mii0_rxdv */
+	{MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)},	/* mcasp1_axr15.pr2_mii0_rxd3 */
+	{MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp2_aclkx.pr2_mii0_rxd2 */
+	{MCASP2_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_fsx.pr2_mii0_rxd1 */
+	{MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_axr2.pr2_mii0_rxd0 */
+	{MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)},	/* mcasp2_axr3.pr2_mii0_rxlink */
+	{MCASP2_AXR4, (M14 | PIN_OUTPUT)},	/* mcasp2_axr4.gpio1_4 */
+	{MCASP2_AXR5, (M14 | PIN_OUTPUT)},	/* mcasp2_axr5.gpio6_7 */
+	{MCASP2_AXR6, (M14 | PIN_OUTPUT)},	/* mcasp2_axr6.gpio2_29 */
+	{MCASP2_AXR7, (M14 | PIN_OUTPUT)},	/* mcasp2_axr7.gpio1_5 */
+	{MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.pr2_mii0_crs */
+	{MCASP3_FSX, (M11 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.pr2_mii0_col */
+	{MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp3_axr0.pr2_mii1_rxer */
+	{MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp3_axr1.pr2_mii1_rxlink */
+	{MCASP4_ACLKX, (M2 | PIN_OUTPUT)},	/* mcasp4_aclkx.spi3_sclk */
+	{MCASP4_FSX, (M2 | PIN_INPUT)},	/* mcasp4_fsx.spi3_d1 */
+	{MCASP4_AXR1, (M2 | PIN_OUTPUT_PULLUP)},	/* mcasp4_axr1.spi3_cs0 */
+	{MCASP5_AXR0, (M4 | PIN_INPUT)},	/* mcasp5_axr0.uart3_rxd */
+	{MCASP5_AXR1, (M4 | PIN_OUTPUT)},	/* mcasp5_axr1.uart3_txd */
 	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
 	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
 	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
 	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
 	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
 	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
-	{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)},	/* mmc1_sdcd.gpio6_27 */
-	{MMC1_SDWP, (M14 | PIN_OUTPUT)},	/* mmc1_sdwp.gpio6_28 */
-	{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_cs2.gpio7_12 */
-	{SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
-	{DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_tx.dcan1_tx */
-	{DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_rx.dcan1_rx */
-	{UART2_CTSN, (M2 | PIN_INPUT_SLEW)},	/* uart2_ctsn.uart3_rxd */
-	{UART2_RTSN, (M1 | PIN_INPUT_SLEW)},	/* uart2_rtsn.uart3_txd */
-	{UART1_RXD, (M14 | PIN_INPUT_PULLDOWN)},	/* uart1_rxd.gpio7_22 */
-	{UART1_TXD, (M14 | PIN_INPUT_PULLDOWN)},	/* uart3_txd.gpio7_23 */
-	{I2C2_SDA, (M1 | PIN_INPUT)},		/* i2c2_sda.hdmi1_ddc_scl */
-	{I2C2_SCL, (M1 | PIN_INPUT)},		/* i2c2_scl.hdmi1_ddc_sda */
-	{ON_OFF, (M1 | PIN_OUTPUT_PULLUP)},	/* on_off.on_off */
-	{RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)},	/* rtc_porz.rtc_porz */
+	{MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mmc1_sdcd.gpio6_27 */
+	{MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)},	/* mmc1_sdwp.gpio6_28 */
+	{GPIO6_10, (M11 | PIN_INPUT_PULLUP)},	/* gpio6_10.pr2_mii_mt1_clk */
+	{GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)},	/* gpio6_11.pr2_mii1_txen */
+	{MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_clk.pr2_mii1_txd3 */
+	{MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_cmd.pr2_mii1_txd2 */
+	{MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat0.pr2_mii1_txd1 */
+	{MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat1.pr2_mii1_txd0 */
+	{MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)},	/* mmc3_dat2.pr2_mii_mr1_clk */
+	{MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat3.pr2_mii1_rxdv */
+	{MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat4.pr2_mii1_rxd3 */
+	{MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat5.pr2_mii1_rxd2 */
+	{MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat6.pr2_mii1_rxd1 */
+	{MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat7.pr2_mii1_rxd0 */
+	{SPI1_SCLK, (M14 | PIN_OUTPUT)},	/* spi1_sclk.gpio7_7 */
+	{SPI1_D1, (M14 | PIN_OUTPUT)},	/* spi1_d1.gpio7_8 */
+	{SPI1_D0, (M14 | PIN_OUTPUT)},	/* spi1_d0.gpio7_9 */
+	{SPI1_CS0, (M14 | PIN_OUTPUT)},	/* spi1_cs0.gpio7_10 */
+	{SPI1_CS1, (M14 | PIN_OUTPUT)},	/* spi1_cs1.gpio7_11 */
+	{SPI1_CS2, (M14 | PIN_INPUT_SLEW)},	/* spi1_cs2.gpio7_12 */
+	{SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
+	{SPI2_SCLK, (M0 | PIN_INPUT)},	/* spi2_sclk.spi2_sclk */
+	{SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)},	/* spi2_d1.spi2_d1 */
+	{SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)},	/* spi2_d0.spi2_d0 */
+	{SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)},	/* spi2_cs0.spi2_cs0 */
+	{DCAN1_TX, (M15 | PULL_UP)},	/* dcan1_tx.safe for dcan1_tx */
+	{DCAN1_RX, (M15 | PULL_UP)},	/* dcan1_rx.safe for dcan1_rx */
+	{UART1_RXD, (M14 | PIN_INPUT | SLEWCONTROL)},	/* uart1_rxd.gpio7_22 */
+	{UART1_CTSN, (M14 | PIN_OUTPUT)},	/* uart1_ctsn.gpio7_24 */
+	{UART1_RTSN, (M14 | PIN_OUTPUT)},	/* uart1_rtsn.gpio7_25 */
+	{I2C1_SDA, (M0 | PIN_INPUT)},	/* i2c1_sda.i2c1_sda */
+	{I2C1_SCL, (M0 | PIN_INPUT)},	/* i2c1_scl.i2c1_scl */
+	{I2C2_SDA, (M1 | PIN_INPUT)},	/* i2c2_sda.hdmi1_ddc_scl */
+	{I2C2_SCL, (M1 | PIN_INPUT)},	/* i2c2_scl.hdmi1_ddc_sda */
+	{WAKEUP0, (M0 | PIN_INPUT)},	/* Wakeup0.Wakeup0 */
+	{WAKEUP3, (M0 | PIN_INPUT)},	/* Wakeup3.Wakeup3 */
+	{ON_OFF, (M0 | PIN_OUTPUT)},	/* on_off.on_off */
+	{RTC_PORZ, (M0 | PIN_INPUT)},	/* rtc_porz.rtc_porz */
 	{TMS, (M0 | PIN_INPUT_PULLUP)},	/* tms.tms */
 	{TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* tdi.tdi */
-	{TDO, (M0 | PIN_INPUT_PULLUP)},	/* tdo.tdo */
+	{TDO, (M0 | PIN_OUTPUT_PULLUP)},	/* tdo.tdo */
 	{TCLK, (M0 | PIN_INPUT_PULLUP)},	/* tclk.tclk */
-	{TRSTN, (M0 | PIN_INPUT_PULLDOWN)},	/* trstn.trstn */
-	{RTCK, (M0 | PIN_INPUT)},	/* rtck.rtck */
-	{EMU0, (M0 | PIN_INPUT_PULLUP)},	/* emu0.emu0 */
-	{EMU1, (M0 | PIN_INPUT_PULLUP)},	/* emu1.emu1 */
-	{RESETN, (M0 | PIN_OUTPUT_PULLUP)},	/* resetn.resetn */
-	{RSTOUTN, (M0 | PIN_OUTPUT_PULLDOWN)},	/* rstoutn.rstoutn */
+	{TRSTN, (M0 | PIN_INPUT)},	/* trstn.trstn */
+	{RTCK, (M0 | PIN_OUTPUT_PULLUP)},	/* rtck.rtck */
+	{EMU0, (M0 | PIN_INPUT)},	/* emu0.emu0 */
+	{EMU1, (M0 | PIN_INPUT)},	/* emu1.emu1 */
+	{RESETN, (M0 | PIN_INPUT)},	/* resetn.resetn */
+	{RSTOUTN, (M0 | PIN_OUTPUT)},	/* rstoutn.rstoutn */
+};
+
+const struct pad_conf_entry core_padconf_array_icss1eth_am571x_idk[] = {
+	/* PR1 MII0 */
+	{VOUT1_D8, (M12 | PIN_INPUT_PULLUP)},	/* vout1_d8.pr1_mii_mt0_clk */
+	{VOUT1_D9, (M13 | PIN_OUTPUT_PULLUP)},	/* vout1_d9.pr1_mii0_txd3 */
+	{VOUT1_D10, (M13 | PIN_OUTPUT_PULLUP)},	/* vout1_d10.pr1_mii0_txd2 */
+	{VOUT1_D11, (M13 | PIN_OUTPUT_PULLUP)},	/* vout1_d11.pr1_mii0_txen */
+	{VOUT1_D12, (M13 | PIN_OUTPUT_PULLUP)},	/* vout1_d12.pr1_mii0_txd1 */
+	{VOUT1_D13, (M13 | PIN_OUTPUT_PULLUP)},	/* vout1_d13.pr1_mii0_txd0 */
+	{VOUT1_D14, (M12 | PIN_INPUT_PULLUP)},	/* vout1_d14.pr1_mii_mr0_clk */
+	{VOUT1_D15, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d15.pr1_mii0_rxdv */
+	{VOUT1_D16, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d16.pr1_mii0_rxd3 */
+	{VOUT1_D17, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d17.pr1_mii0_rxd2 */
+	{VOUT1_D18, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d18.pr1_mii0_rxd1 */
+	{VOUT1_D19, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d19.pr1_mii0_rxd0 */
+	{VOUT1_D20, (M12 | PIN_INPUT_PULLUP)},	/* vout1_d20.pr1_mii0_rxer */
+	{VOUT1_D21, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d21.pr1_mii0_rxlink */
+	{VOUT1_D22, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d22.pr1_mii0_col */
+	{VOUT1_D23, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d23.pr1_mii0_crs */
+
+	/* PR1 MII1 */
+	{VIN2A_D3, (M12 | PIN_INPUT_PULLDOWN)},	/* vin2a_d3.pr1_mii1_col */
+	{VIN2A_D4, (M13 | PIN_OUTPUT_PULLUP)},	/* vin2a_d4.pr1_mii1_txd1 */
+	{VIN2A_D5, (M13 | PIN_OUTPUT_PULLUP)},	/* vin2a_d5.pr1_mii1_txd0 */
+	{VIN2A_D6, (M11 | PIN_INPUT_PULLUP)},	/* vin2a_d6.pr1_mii_mt1_clk */
+	{VIN2A_D7, (M11 | PIN_OUTPUT_PULLUP)},	/* vin2a_d7.pr1_mii1_txen */
+	{VIN2A_D8, (M11 | PIN_OUTPUT_PULLUP)},	/* vin2a_d8.pr1_mii1_txd3 */
+	{VIN2A_D9, (M11 | PIN_OUTPUT_PULLUP)},	/* vin2a_d9.pr1_mii1_txd2 */
+	{VOUT1_VSYNC, (M12 | PIN_INPUT_PULLUP)},	/* vout1_vsync.pr1_mii1_rxer */
+	{VOUT1_D0, (M12 | PIN_INPUT_PULLUP)},	/* vout1_d0.pr1_mii1_rxlink */
+	{VOUT1_D1, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d1.pr1_mii1_crs */
+	{VOUT1_D2, (M12 | PIN_INPUT_PULLUP)},	/* vout1_d2.pr1_mii_mr1_clk */
+	{VOUT1_D3, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d3.pr1_mii1_rxdv */
+	{VOUT1_D4, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d4.pr1_mii1_rxd3 */
+	{VOUT1_D5, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d5.pr1_mii1_rxd2 */
+	{VOUT1_D6, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d6.pr1_mii1_rxd1 */
+	{VOUT1_D7, (M12 | PIN_INPUT_PULLDOWN)},	/* vout1_d7.pr1_mii1_rxd0 */
+};
+
+const struct pad_conf_entry core_padconf_array_vout_am571x_idk[] = {
+	{VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_clk.vout1_clk */
+	{VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_de.vout1_de */
+	{VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_hsync.vout1_hsync */
+	{VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_vsync.vout1_vsync */
+	{VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d0.vout1_d0 */
+	{VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d1.vout1_d1 */
+	{VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d2.vout1_d2 */
+	{VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d3.vout1_d3 */
+	{VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d4.vout1_d4 */
+	{VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d5.vout1_d5 */
+	{VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d6.vout1_d6 */
+	{VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d7.vout1_d7 */
+	{VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d8.vout1_d8 */
+	{VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d9.vout1_d9 */
+	{VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d10.vout1_d10 */
+	{VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d11.vout1_d11 */
+	{VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d12.vout1_d12 */
+	{VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d13.vout1_d13 */
+	{VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d14.vout1_d14 */
+	{VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d15.vout1_d15 */
+	{VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d16.vout1_d16 */
+	{VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d17.vout1_d17 */
+	{VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d18.vout1_d18 */
+	{VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d19.vout1_d19 */
+	{VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d20.vout1_d20 */
+	{VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d21.vout1_d21 */
+	{VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d22.vout1_d22 */
+	{VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL)},	/* vout1_d23.vout1_d23 */
+
+	{MCASP5_ACLKX, (M12 | PIN_INPUT | MANUAL_MODE)},	/* mcasp5_aclkx.pr2_pru1_gpi1 */
+	{MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)},	/* mcasp5_fsx.pr2_pru1_gpi2 */
+	{UART2_RXD, (M0 | PIN_INPUT)},	/* uart2_rxd.uart2_rxd */
+	{UART2_TXD, (M0 | PIN_OUTPUT)},	/* uart2_txd.uart2_txd */
+	{VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d5.pr1_pru1_gpo2 */
 };
 
 const struct pad_conf_entry early_padconf[] = {
@@ -488,7 +782,7 @@ const struct pad_conf_entry early_padconf[] = {
 };
 
 #ifdef CONFIG_IODELAY_RECALIBRATION
-const struct iodelay_cfg_entry iodelay_cfg_array_x15[] = {
+const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr1_1[] = {
 	{0x0114, 2980, 0},	/* CFG_GPMC_A0_IN */
 	{0x0120, 2648, 0},	/* CFG_GPMC_A10_IN */
 	{0x012C, 2918, 0},	/* CFG_GPMC_A11_IN */
@@ -517,6 +811,36 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15[] = {
 	{0x0300, 2389, 0},	/* CFG_GPMC_AD7_IN */
 	{0x030C, 2672, 0},	/* CFG_GPMC_AD8_IN */
 	{0x0318, 2334, 0},	/* CFG_GPMC_AD9_IN */
+	{0x0378, 0, 0},	/* CFG_GPMC_CS3_IN */
+	{0x0678, 406, 0},	/* CFG_MMC3_CLK_IN */
+	{0x0680, 659, 0},	/* CFG_MMC3_CLK_OUT */
+	{0x0684, 0, 0},	/* CFG_MMC3_CMD_IN */
+	{0x0688, 0, 0},	/* CFG_MMC3_CMD_OEN */
+	{0x068C, 0, 0},	/* CFG_MMC3_CMD_OUT */
+	{0x0690, 130, 0},	/* CFG_MMC3_DAT0_IN */
+	{0x0694, 0, 0},	/* CFG_MMC3_DAT0_OEN */
+	{0x0698, 0, 0},	/* CFG_MMC3_DAT0_OUT */
+	{0x069C, 169, 0},	/* CFG_MMC3_DAT1_IN */
+	{0x06A0, 0, 0},	/* CFG_MMC3_DAT1_OEN */
+	{0x06A4, 0, 0},	/* CFG_MMC3_DAT1_OUT */
+	{0x06A8, 0, 0},	/* CFG_MMC3_DAT2_IN */
+	{0x06AC, 0, 0},	/* CFG_MMC3_DAT2_OEN */
+	{0x06B0, 0, 0},	/* CFG_MMC3_DAT2_OUT */
+	{0x06B4, 457, 0},	/* CFG_MMC3_DAT3_IN */
+	{0x06B8, 0, 0},	/* CFG_MMC3_DAT3_OEN */
+	{0x06BC, 0, 0},	/* CFG_MMC3_DAT3_OUT */
+	{0x06C0, 702, 0},	/* CFG_MMC3_DAT4_IN */
+	{0x06C4, 0, 0},	/* CFG_MMC3_DAT4_OEN */
+	{0x06C8, 0, 0},	/* CFG_MMC3_DAT4_OUT */
+	{0x06CC, 738, 0},	/* CFG_MMC3_DAT5_IN */
+	{0x06D0, 0, 0},	/* CFG_MMC3_DAT5_OEN */
+	{0x06D4, 0, 0},	/* CFG_MMC3_DAT5_OUT */
+	{0x06D8, 856, 0},	/* CFG_MMC3_DAT6_IN */
+	{0x06DC, 0, 0},	/* CFG_MMC3_DAT6_OEN */
+	{0x06E0, 0, 0},	/* CFG_MMC3_DAT6_OUT */
+	{0x06E4, 610, 0},	/* CFG_MMC3_DAT7_IN */
+	{0x06E8, 0, 0},	/* CFG_MMC3_DAT7_OEN */
+	{0x06EC, 0, 0},	/* CFG_MMC3_DAT7_OUT */
 	{0x06F0, 480, 0},	/* CFG_RGMII0_RXC_IN */
 	{0x06FC, 111, 1641},	/* CFG_RGMII0_RXCTL_IN */
 	{0x0708, 272, 1116},	/* CFG_RGMII0_RXD0_IN */
@@ -524,17 +848,17 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15[] = {
 	{0x0720, 0, 1614},	/* CFG_RGMII0_RXD2_IN */
 	{0x072C, 105, 1673},	/* CFG_RGMII0_RXD3_IN */
 	{0x0740, 531, 120},	/* CFG_RGMII0_TXC_OUT */
-	{0x074C, 11, 60},	/* CFG_RGMII0_TXCTL_OUT */
-	{0x0758, 7, 120},	/* CFG_RGMII0_TXD0_OUT */
-	{0x0764, 0, 0},		/* CFG_RGMII0_TXD1_OUT */
-	{0x0770, 276, 120},	/* CFG_RGMII0_TXD2_OUT */
-	{0x077C, 440, 120},	/* CFG_RGMII0_TXD3_OUT */
+	{0x074C, 201, 60},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 229, 120},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 141, 0},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 495, 120},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 660, 120},	/* CFG_RGMII0_TXD3_OUT */
 	{0x0A70, 1551, 115},	/* CFG_VIN2A_D12_OUT */
 	{0x0A7C, 816, 0},	/* CFG_VIN2A_D13_OUT */
 	{0x0A88, 876, 0},	/* CFG_VIN2A_D14_OUT */
 	{0x0A94, 312, 0},	/* CFG_VIN2A_D15_OUT */
 	{0x0AA0, 58, 0},	/* CFG_VIN2A_D16_OUT */
-	{0x0AAC, 0, 0},		/* CFG_VIN2A_D17_OUT */
+	{0x0AAC, 0, 0},	/* CFG_VIN2A_D17_OUT */
 	{0x0AB0, 702, 0},	/* CFG_VIN2A_D18_IN */
 	{0x0ABC, 136, 976},	/* CFG_VIN2A_D19_IN */
 	{0x0AD4, 210, 1357},	/* CFG_VIN2A_D20_IN */
@@ -543,52 +867,250 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15[] = {
 	{0x0AF8, 0, 1397},	/* CFG_VIN2A_D23_IN */
 };
 
+const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr2_0[] = {
+	{0x0114, 2519, 702},	/* CFG_GPMC_A0_IN */
+	{0x0120, 2435, 411},	/* CFG_GPMC_A10_IN */
+	{0x012C, 2379, 755},	/* CFG_GPMC_A11_IN */
+	{0x0198, 2384, 778},	/* CFG_GPMC_A1_IN */
+	{0x0204, 2499, 1127},	/* CFG_GPMC_A2_IN */
+	{0x0210, 2455, 1181},	/* CFG_GPMC_A3_IN */
+	{0x021C, 2486, 1039},	/* CFG_GPMC_A4_IN */
+	{0x0228, 2456, 938},	/* CFG_GPMC_A5_IN */
+	{0x0234, 2463, 573},	/* CFG_GPMC_A6_IN */
+	{0x0240, 2608, 783},	/* CFG_GPMC_A7_IN */
+	{0x024C, 2430, 656},	/* CFG_GPMC_A8_IN */
+	{0x0258, 2465, 850},	/* CFG_GPMC_A9_IN */
+	{0x0264, 2316, 301},	/* CFG_GPMC_AD0_IN */
+	{0x0270, 2324, 406},	/* CFG_GPMC_AD10_IN */
+	{0x027C, 2278, 352},	/* CFG_GPMC_AD11_IN */
+	{0x0288, 2297, 160},	/* CFG_GPMC_AD12_IN */
+	{0x0294, 2278, 108},	/* CFG_GPMC_AD13_IN */
+	{0x02A0, 2035, 0},	/* CFG_GPMC_AD14_IN */
+	{0x02AC, 2279, 378},	/* CFG_GPMC_AD15_IN */
+	{0x02B8, 2440, 70},	/* CFG_GPMC_AD1_IN */
+	{0x02C4, 2404, 446},	/* CFG_GPMC_AD2_IN */
+	{0x02D0, 2343, 212},	/* CFG_GPMC_AD3_IN */
+	{0x02DC, 2355, 322},	/* CFG_GPMC_AD4_IN */
+	{0x02E8, 2337, 192},	/* CFG_GPMC_AD5_IN */
+	{0x02F4, 2270, 314},	/* CFG_GPMC_AD6_IN */
+	{0x0300, 2339, 259},	/* CFG_GPMC_AD7_IN */
+	{0x030C, 2308, 577},	/* CFG_GPMC_AD8_IN */
+	{0x0318, 2334, 166},	/* CFG_GPMC_AD9_IN */
+	{0x0378, 0, 0},	/* CFG_GPMC_CS3_IN */
+	{0x0678, 0, 386},	/* CFG_MMC3_CLK_IN */
+	{0x0680, 605, 0},	/* CFG_MMC3_CLK_OUT */
+	{0x0684, 0, 0},	/* CFG_MMC3_CMD_IN */
+	{0x0688, 0, 0},	/* CFG_MMC3_CMD_OEN */
+	{0x068C, 0, 0},	/* CFG_MMC3_CMD_OUT */
+	{0x0690, 171, 0},	/* CFG_MMC3_DAT0_IN */
+	{0x0694, 0, 0},	/* CFG_MMC3_DAT0_OEN */
+	{0x0698, 0, 0},	/* CFG_MMC3_DAT0_OUT */
+	{0x069C, 221, 0},	/* CFG_MMC3_DAT1_IN */
+	{0x06A0, 0, 0},	/* CFG_MMC3_DAT1_OEN */
+	{0x06A4, 0, 0},	/* CFG_MMC3_DAT1_OUT */
+	{0x06A8, 0, 0},	/* CFG_MMC3_DAT2_IN */
+	{0x06AC, 0, 0},	/* CFG_MMC3_DAT2_OEN */
+	{0x06B0, 0, 0},	/* CFG_MMC3_DAT2_OUT */
+	{0x06B4, 474, 0},	/* CFG_MMC3_DAT3_IN */
+	{0x06B8, 0, 0},	/* CFG_MMC3_DAT3_OEN */
+	{0x06BC, 0, 0},	/* CFG_MMC3_DAT3_OUT */
+	{0x06C0, 792, 0},	/* CFG_MMC3_DAT4_IN */
+	{0x06C4, 0, 0},	/* CFG_MMC3_DAT4_OEN */
+	{0x06C8, 0, 0},	/* CFG_MMC3_DAT4_OUT */
+	{0x06CC, 782, 0},	/* CFG_MMC3_DAT5_IN */
+	{0x06D0, 0, 0},	/* CFG_MMC3_DAT5_OEN */
+	{0x06D4, 0, 0},	/* CFG_MMC3_DAT5_OUT */
+	{0x06D8, 942, 0},	/* CFG_MMC3_DAT6_IN */
+	{0x06DC, 0, 0},	/* CFG_MMC3_DAT6_OEN */
+	{0x06E0, 0, 0},	/* CFG_MMC3_DAT6_OUT */
+	{0x06E4, 636, 0},	/* CFG_MMC3_DAT7_IN */
+	{0x06E8, 0, 0},	/* CFG_MMC3_DAT7_OEN */
+	{0x06EC, 0, 0},	/* CFG_MMC3_DAT7_OUT */
+	{0x06F0, 260, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 0, 1412},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 123, 1047},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 139, 1081},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 195, 1100},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 239, 1216},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 89, 0},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 15, 125},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 339, 162},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 146, 94},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 0, 27},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 291, 205},	/* CFG_RGMII0_TXD3_OUT */
+	{0x0A70, 0, 0},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 219, 101},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 92, 58},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 135, 100},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 154, 101},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 78, 27},	/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 411, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 0, 382},	/* CFG_VIN2A_D19_IN */
+	{0x0AD4, 320, 750},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 192, 836},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 294, 669},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 50, 700},	/* CFG_VIN2A_D23_IN */
+	{0x0B9C, 0, 706},	/* CFG_VOUT1_CLK_OUT */
+	{0x0BA8, 2313, 0},	/* CFG_VOUT1_D0_OUT */
+	{0x0BB4, 2199, 0},	/* CFG_VOUT1_D10_OUT */
+	{0x0BC0, 2266, 0},	/* CFG_VOUT1_D11_OUT */
+	{0x0BCC, 3159, 0},	/* CFG_VOUT1_D12_OUT */
+	{0x0BD8, 2100, 0},	/* CFG_VOUT1_D13_OUT */
+	{0x0BE4, 2229, 0},	/* CFG_VOUT1_D14_OUT */
+	{0x0BF0, 2202, 0},	/* CFG_VOUT1_D15_OUT */
+	{0x0BFC, 2084, 0},	/* CFG_VOUT1_D16_OUT */
+	{0x0C08, 2195, 0},	/* CFG_VOUT1_D17_OUT */
+	{0x0C14, 2342, 0},	/* CFG_VOUT1_D18_OUT */
+	{0x0C20, 2463, 0},	/* CFG_VOUT1_D19_OUT */
+	{0x0C2C, 2439, 0},	/* CFG_VOUT1_D1_OUT */
+	{0x0C38, 2304, 0},	/* CFG_VOUT1_D20_OUT */
+	{0x0C44, 2103, 0},	/* CFG_VOUT1_D21_OUT */
+	{0x0C50, 2145, 0},	/* CFG_VOUT1_D22_OUT */
+	{0x0C5C, 1932, 0},	/* CFG_VOUT1_D23_OUT */
+	{0x0C68, 2200, 0},	/* CFG_VOUT1_D2_OUT */
+	{0x0C74, 2355, 0},	/* CFG_VOUT1_D3_OUT */
+	{0x0C80, 3215, 0},	/* CFG_VOUT1_D4_OUT */
+	{0x0C8C, 2314, 0},	/* CFG_VOUT1_D5_OUT */
+	{0x0C98, 2238, 0},	/* CFG_VOUT1_D6_OUT */
+	{0x0CA4, 2381, 0},	/* CFG_VOUT1_D7_OUT */
+	{0x0CB0, 2138, 0},	/* CFG_VOUT1_D8_OUT */
+	{0x0CBC, 2383, 0},	/* CFG_VOUT1_D9_OUT */
+	{0x0CC8, 1984, 0},	/* CFG_VOUT1_DE_OUT */
+	{0x0CE0, 1947, 0},	/* CFG_VOUT1_HSYNC_OUT */
+	{0x0CEC, 2739, 0},	/* CFG_VOUT1_VSYNC_OUT */
+};
+
 const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = {
-	{0x0114, 2980, 0},	/* CFG_GPMC_A0_IN */
-	{0x0120, 2648, 0},	/* CFG_GPMC_A10_IN */
-	{0x012C, 2918, 0},	/* CFG_GPMC_A11_IN */
-	{0x0138, 2605, 45},	/* CFG_GPMC_A12_IN */
-	{0x0144, 0, 0},		/* CFG_GPMC_A13_IN */
-	{0x0150, 1976, 1389},	/* CFG_GPMC_A14_IN */
-	{0x015C, 1872, 1408},	/* CFG_GPMC_A15_IN */
-	{0x0168, 1914, 1506},	/* CFG_GPMC_A16_IN */
-	{0x0170, 57, 0},	/* CFG_GPMC_A16_OUT */
-	{0x0174, 1904, 1471},	/* CFG_GPMC_A17_IN */
-	{0x0188, 1690, 0},	/* CFG_GPMC_A18_OUT */
-	{0x0198, 2917, 0},	/* CFG_GPMC_A1_IN */
-	{0x0204, 3156, 178},	/* CFG_GPMC_A2_IN */
-	{0x0210, 3109, 246},	/* CFG_GPMC_A3_IN */
-	{0x021C, 3142, 100},	/* CFG_GPMC_A4_IN */
-	{0x0228, 3084, 33},	/* CFG_GPMC_A5_IN */
-	{0x0234, 2778, 0},	/* CFG_GPMC_A6_IN */
-	{0x0240, 3110, 0},	/* CFG_GPMC_A7_IN */
-	{0x024C, 2874, 0},	/* CFG_GPMC_A8_IN */
-	{0x0258, 3072, 0},	/* CFG_GPMC_A9_IN */
-	{0x0374, 0, 0},		/* CFG_GPMC_CS2_OUT */
-	{0x06F0, 480, 0},	/* CFG_RGMII0_RXC_IN */
-	{0x06FC, 111, 1641},	/* CFG_RGMII0_RXCTL_IN */
-	{0x0708, 272, 1116},	/* CFG_RGMII0_RXD0_IN */
-	{0x0714, 243, 1260},	/* CFG_RGMII0_RXD1_IN */
-	{0x0720, 0, 1614},	/* CFG_RGMII0_RXD2_IN */
-	{0x072C, 105, 1673},	/* CFG_RGMII0_RXD3_IN */
-	{0x0740, 531, 120},	/* CFG_RGMII0_TXC_OUT */
-	{0x074C, 201, 60},	/* CFG_RGMII0_TXCTL_OUT */
-	{0x0758, 229, 120},	/* CFG_RGMII0_TXD0_OUT */
-	{0x0764, 141, 0},	/* CFG_RGMII0_TXD1_OUT */
-	{0x0770, 495, 120},	/* CFG_RGMII0_TXD2_OUT */
-	{0x077C, 660, 120},	/* CFG_RGMII0_TXD3_OUT */
-	{0x0A70, 65, 70},	/* CFG_VIN2A_D12_OUT */
-	{0x0A7C, 125, 70},	/* CFG_VIN2A_D13_OUT */
-	{0x0A88, 0, 70},	/* CFG_VIN2A_D14_OUT */
-	{0x0A94, 0, 70},	/* CFG_VIN2A_D15_OUT */
-	{0x0AA0, 65, 70},	/* CFG_VIN2A_D16_OUT */
-	{0x0AAC, 0, 0},		/* CFG_VIN2A_D17_OUT */
-	{0x0AB0, 612, 0},	/* CFG_VIN2A_D18_IN */
-	{0x0ABC, 4, 927},	/* CFG_VIN2A_D19_IN */
-	{0x0AD4, 136, 1340},	/* CFG_VIN2A_D20_IN */
-	{0x0AE0, 130, 1450},	/* CFG_VIN2A_D21_IN */
-	{0x0AEC, 144, 1269},	/* CFG_VIN2A_D22_IN */
-	{0x0AF8, 0, 1330},	/* CFG_VIN2A_D23_IN */
+	{0x0114, 1861, 901},	/* CFG_GPMC_A0_IN */
+	{0x0120, 0, 0},	/* CFG_GPMC_A10_IN */
+	{0x012C, 1783, 1178},	/* CFG_GPMC_A11_IN */
+	{0x0138, 1903, 853},	/* CFG_GPMC_A12_IN */
+	{0x0144, 0, 0},	/* CFG_GPMC_A13_IN */
+	{0x0150, 2575, 966},	/* CFG_GPMC_A14_IN */
+	{0x015C, 2503, 889},	/* CFG_GPMC_A15_IN */
+	{0x0168, 2528, 1007},	/* CFG_GPMC_A16_IN */
+	{0x0170, 0, 0},	/* CFG_GPMC_A16_OUT */
+	{0x0174, 2533, 980},	/* CFG_GPMC_A17_IN */
+	{0x0188, 590, 0},	/* CFG_GPMC_A18_OUT */
+	{0x0198, 1652, 891},	/* CFG_GPMC_A1_IN */
+	{0x0204, 1888, 1212},	/* CFG_GPMC_A2_IN */
+	{0x0210, 1839, 1274},	/* CFG_GPMC_A3_IN */
+	{0x021C, 1868, 1113},	/* CFG_GPMC_A4_IN */
+	{0x0228, 1757, 1079},	/* CFG_GPMC_A5_IN */
+	{0x0234, 1800, 670},	/* CFG_GPMC_A6_IN */
+	{0x0240, 1967, 898},	/* CFG_GPMC_A7_IN */
+	{0x024C, 1731, 959},	/* CFG_GPMC_A8_IN */
+	{0x0258, 1766, 1150},	/* CFG_GPMC_A9_IN */
+	{0x0374, 0, 0},	/* CFG_GPMC_CS2_OUT */
+	{0x0590, 1000, 4200},	/* CFG_MCASP5_ACLKX_OUT */
+	{0x05AC, 800, 3800},	/* CFG_MCASP5_FSX_IN */
+	{0x06F0, 260, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 0, 1412},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 123, 1047},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 139, 1081},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 195, 1100},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 239, 1216},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 89, 0},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 15, 125},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 339, 162},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 146, 94},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 0, 27},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 291, 205},	/* CFG_RGMII0_TXD3_OUT */
+	{0x0A70, 0, 0},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 219, 101},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 92, 58},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 135, 100},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 154, 101},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 78, 27},	/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 411, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 0, 382},	/* CFG_VIN2A_D19_IN */
+	{0x0AD4, 320, 750},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 192, 836},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 294, 669},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 50, 700},	/* CFG_VIN2A_D23_IN */
+	{0x0B30, 0, 0},	/* CFG_VIN2A_D5_OUT */
+	{0x0B9C, 1126, 751},	/* CFG_VOUT1_CLK_OUT */
+	{0x0BA8, 395, 0},	/* CFG_VOUT1_D0_OUT */
+	{0x0BB4, 282, 0},	/* CFG_VOUT1_D10_OUT */
+	{0x0BC0, 348, 0},	/* CFG_VOUT1_D11_OUT */
+	{0x0BCC, 1240, 0},	/* CFG_VOUT1_D12_OUT */
+	{0x0BD8, 182, 0},	/* CFG_VOUT1_D13_OUT */
+	{0x0BE4, 311, 0},	/* CFG_VOUT1_D14_OUT */
+	{0x0BF0, 285, 0},	/* CFG_VOUT1_D15_OUT */
+	{0x0BFC, 166, 0},	/* CFG_VOUT1_D16_OUT */
+	{0x0C08, 278, 0},	/* CFG_VOUT1_D17_OUT */
+	{0x0C14, 425, 0},	/* CFG_VOUT1_D18_OUT */
+	{0x0C20, 516, 0},	/* CFG_VOUT1_D19_OUT */
+	{0x0C2C, 521, 0},	/* CFG_VOUT1_D1_OUT */
+	{0x0C38, 386, 0},	/* CFG_VOUT1_D20_OUT */
+	{0x0C44, 111, 0},	/* CFG_VOUT1_D21_OUT */
+	{0x0C50, 227, 0},	/* CFG_VOUT1_D22_OUT */
+	{0x0C5C, 0, 0},	/* CFG_VOUT1_D23_OUT */
+	{0x0C68, 282, 0},	/* CFG_VOUT1_D2_OUT */
+	{0x0C74, 438, 0},	/* CFG_VOUT1_D3_OUT */
+	{0x0C80, 1298, 0},	/* CFG_VOUT1_D4_OUT */
+	{0x0C8C, 397, 0},	/* CFG_VOUT1_D5_OUT */
+	{0x0C98, 321, 0},	/* CFG_VOUT1_D6_OUT */
+	{0x0CA4, 155, 309},	/* CFG_VOUT1_D7_OUT */
+	{0x0CB0, 212, 0},	/* CFG_VOUT1_D8_OUT */
+	{0x0CBC, 466, 0},	/* CFG_VOUT1_D9_OUT */
+	{0x0CC8, 0, 0},	/* CFG_VOUT1_DE_OUT */
+	{0x0CE0, 0, 0},	/* CFG_VOUT1_HSYNC_OUT */
+	{0x0CEC, 139, 701},	/* CFG_VOUT1_VSYNC_OUT */
+};
+
+const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk[] = {
+	{0x0114, 1873, 702},	/* CFG_GPMC_A0_IN */
+	{0x0120, 0, 0},	/* CFG_GPMC_A10_IN */
+	{0x012C, 1851, 1011},	/* CFG_GPMC_A11_IN */
+	{0x0138, 2009, 601},	/* CFG_GPMC_A12_IN */
+	{0x0144, 0, 0},	/* CFG_GPMC_A13_IN */
+	{0x0150, 2247, 1186},	/* CFG_GPMC_A14_IN */
+	{0x015C, 2176, 1197},	/* CFG_GPMC_A15_IN */
+	{0x0168, 2229, 1268},	/* CFG_GPMC_A16_IN */
+	{0x0170, 0, 0},	/* CFG_GPMC_A16_OUT */
+	{0x0174, 2251, 1217},	/* CFG_GPMC_A17_IN */
+	{0x0188, 0, 0},	/* CFG_GPMC_A18_OUT */
+	{0x0198, 1629, 772},	/* CFG_GPMC_A1_IN */
+	{0x0204, 1734, 898},	/* CFG_GPMC_A2_IN */
+	{0x0210, 1757, 1076},	/* CFG_GPMC_A3_IN */
+	{0x021C, 1794, 893},	/* CFG_GPMC_A4_IN */
+	{0x0228, 1726, 853},	/* CFG_GPMC_A5_IN */
+	{0x0234, 1792, 612},	/* CFG_GPMC_A6_IN */
+	{0x0240, 2117, 610},	/* CFG_GPMC_A7_IN */
+	{0x024C, 1758, 653},	/* CFG_GPMC_A8_IN */
+	{0x0258, 1705, 899},	/* CFG_GPMC_A9_IN */
+	{0x0374, 0, 0},	/* CFG_GPMC_CS2_OUT */
+	{0x06F0, 413, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 27, 2296},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 3, 1721},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 134, 1786},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 40, 1966},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 0, 2057},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 0, 60},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 0, 60},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 0, 60},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 0, 0},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 0, 60},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 0, 120},	/* CFG_RGMII0_TXD3_OUT */
+	{0x0A70, 0, 0},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 170, 0},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 150, 0},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 0, 0},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 60, 0},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 60, 0},	/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 530, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 71, 1099},	/* CFG_VIN2A_D19_IN */
+	{0x0AD4, 142, 1337},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 114, 1517},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 171, 1331},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 0, 1328},	/* CFG_VIN2A_D23_IN */
+};
+
+const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk_4port[] = {
+	{0x0588, 2100, 1959},	/* CFG_MCASP5_ACLKX_IN */
+	{0x05AC, 2100, 1780},	/* CFG_MCASP5_FSX_IN */
+	{0x0B30, 0, 400},	/* CFG_VIN2A_D5_OUT */
 };
 #endif
 #endif /* _MUX_DATA_BEAGLE_X15_H_ */
diff --git a/board/ti/beagle/Makefile b/board/ti/beagle/Makefile
index 7a858be..41b552a 100644
--- a/board/ti/beagle/Makefile
+++ b/board/ti/beagle/Makefile
@@ -6,4 +6,4 @@
 #
 
 obj-y	:= beagle.o
-obj-$(CONFIG_STATUS_LED) += led.o
+obj-$(CONFIG_LED_STATUS) += led.o
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 0ed4f52..887b577 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -16,7 +16,7 @@
 #include <common.h>
 #include <dm.h>
 #include <ns16550.h>
-#ifdef CONFIG_STATUS_LED
+#ifdef CONFIG_LED_STATUS
 #include <status_led.h>
 #endif
 #include <twl4030.h>
@@ -29,14 +29,14 @@
 #include <asm/gpio.h>
 #include <asm/mach-types.h>
 #include <asm/omap_musb.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 #include <linux/usb/musb.h>
 #include "beagle.h"
 #include <command.h>
 
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
 #include <usb.h>
 #include <asm/ehci-omap.h>
 #endif
@@ -75,7 +75,8 @@ static struct {
 static const struct ns16550_platdata beagle_serial = {
 	.base = OMAP34XX_UART3,
 	.reg_shift = 2,
-	.clock = V_NS16550_CLK
+	.clock = V_NS16550_CLK,
+	.fcr = UART_FCR_DEFVAL,
 };
 
 U_BOOT_DEVICE(beagle_uart) = {
@@ -95,8 +96,8 @@ int board_init(void)
 	/* boot param addr */
 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
 
-#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
-	status_led_set (STATUS_LED_BOOT, STATUS_LED_ON);
+#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
+	status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
 #endif
 
 	return 0;
@@ -442,13 +443,13 @@ int misc_init_r(void)
 		printf("Recognized BeagleBoardToys WiFi board\n");
 		MUX_BBTOYS_WIFI()
 		setenv("buddy", "bbtoys-wifi");
-		break;;
+		break;
 	case BBTOYS_VGA:
 		printf("Recognized BeagleBoardToys VGA board\n");
-		break;;
+		break;
 	case BBTOYS_LCD:
 		printf("Recognized BeagleBoardToys LCD board\n");
-		break;;
+		break;
 	case BCT_BRETTL3:
 		printf("Recognized bct electronic GmbH brettl3 board\n");
 		break;
@@ -523,21 +524,21 @@ void set_muxconf_regs(void)
 	MUX_BEAGLE();
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
 }
 #endif
 
-#if defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 void board_mmc_power_init(void)
 {
 	twl4030_power_mmc_init(0);
 }
 #endif
 
-#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
 /* Call usb_stop() before starting the kernel */
 void show_boot_progress(int val)
 {
@@ -562,7 +563,7 @@ int ehci_hcd_stop(int index)
 	return omap_ehci_hcd_stop();
 }
 
-#endif /* CONFIG_USB_EHCI */
+#endif /* CONFIG_USB_EHCI_HCD */
 
 #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)
 int board_eth_init(bd_t *bis)
diff --git a/board/ti/beagle/led.c b/board/ti/beagle/led.c
index a913a4c..30b8b93 100644
--- a/board/ti/beagle/led.c
+++ b/board/ti/beagle/led.c
@@ -15,26 +15,26 @@
 #define BEAGLE_LED_USR0	150
 #define BEAGLE_LED_USR1	149
 
-#ifdef STATUS_LED_GREEN
+#ifdef CONFIG_LED_STATUS_GREEN
 void green_led_off(void)
 {
-	__led_set (STATUS_LED_GREEN, 0);
+	__led_set(CONFIG_LED_STATUS_GREEN, 0);
 }
 
 void green_led_on(void)
 {
-	__led_set (STATUS_LED_GREEN, 1);
+	__led_set(CONFIG_LED_STATUS_GREEN, 1);
 }
 #endif
 
 static int get_led_gpio(led_id_t mask)
 {
-#ifdef STATUS_LED_BIT
-	if (STATUS_LED_BIT & mask)
+#ifdef CONFIG_LED_STATUS0
+	if (CONFIG_LED_STATUS_BIT & mask)
 		return BEAGLE_LED_USR0;
 #endif
-#ifdef STATUS_LED_BIT1
-	if (STATUS_LED_BIT1 & mask)
+#ifdef CONFIG_LED_STATUS1
+	if (CONFIG_LED_STATUS_BIT1 & mask)
 		return BEAGLE_LED_USR1;
 #endif
 
diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig
index adf73ab..c81baa1 100644
--- a/board/ti/common/Kconfig
+++ b/board/ti/common/Kconfig
@@ -3,3 +3,43 @@ config TI_I2C_BOARD_DETECT
 	help
 	   Support for detection board information on Texas Instrument's
 	   Evaluation Boards which have I2C based EEPROM detection
+
+config EEPROM_BUS_ADDRESS
+	int "Board EEPROM's I2C bus address"
+	range 0 8
+	default 0
+
+config EEPROM_CHIP_ADDRESS
+	hex "Board EEPROM's I2C chip address"
+	range 0 0xff
+	default 0x50
+
+config TI_COMMON_CMD_OPTIONS
+	bool "Enable cmd options on TI platforms"
+	imply CMD_ASKENV
+	imply CMD_BOOTZ
+	imply CRC32_VERIFY if ARCH_KEYSTONE
+	imply CMD_DFU if USB_GADGET_DOWNLOAD
+	imply CMD_DHCP
+	imply CMD_EEPROM
+	imply CMD_EXT2
+	imply CMD_EXT4
+	imply CMD_EXT4_WRITE
+	imply CMD_FASTBOOT if FASTBOOT
+	imply CMD_FAT
+	imply FAT_WRITE if CMD_FAT
+	imply CMD_FS_GENERIC
+	imply CMD_GPIO
+	imply CMD_GPT
+	imply CMD_I2C
+	imply CMD_MII
+	imply CMD_MMC
+	imply CMD_PART
+	imply CMD_PING
+	imply CMD_PMIC if DM_PMIC
+	imply CMD_REGULATOR if DM_REGULATOR
+	imply CMD_SF if SPI_FLASH
+	imply CMD_SPI
+	imply CMD_TIME
+	imply CMD_USB if USB
+	imply ENV_IS_IN_FAT if MMC_OMAP_HS
diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c
index e0ae1a5..1da5ace 100644
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -10,10 +10,47 @@
 
 #include <common.h>
 #include <asm/omap_common.h>
+#include <dm/uclass.h>
 #include <i2c.h>
 
 #include "board_detect.h"
 
+#if defined(CONFIG_DM_I2C_COMPAT)
+/**
+ * ti_i2c_set_alen - Set chip's i2c address length
+ * @bus_addr - I2C bus number
+ * @dev_addr - I2C eeprom id
+ * @alen     - I2C address length in bytes
+ *
+ * DM_I2C by default sets the address length to be used to 1. This
+ * function allows this address length to be changed to match the
+ * eeprom used for board detection.
+ */
+int __maybe_unused ti_i2c_set_alen(int bus_addr, int dev_addr, int alen)
+{
+	struct udevice *dev;
+	struct udevice *bus;
+	int rc;
+
+	rc = uclass_get_device_by_seq(UCLASS_I2C, bus_addr, &bus);
+	if (rc)
+		return rc;
+	rc = i2c_get_chip(bus, dev_addr, 1, &dev);
+	if (rc)
+		return rc;
+	rc = i2c_set_chip_offset_len(dev, alen);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+#else
+int __maybe_unused ti_i2c_set_alen(int bus_addr, int dev_addr, int alen)
+{
+	return 0;
+}
+#endif
+
 /**
  * ti_i2c_eeprom_init - Initialize an i2c bus and probe for a device
  * @i2c_bus: i2c bus number to initialize
@@ -46,7 +83,17 @@ static int __maybe_unused ti_i2c_eeprom_init(int i2c_bus, int dev_addr)
 static int __maybe_unused ti_i2c_eeprom_read(int dev_addr, int offset,
 					     uchar *ep, int epsize)
 {
-	return i2c_read(dev_addr, offset, 2, ep, epsize);
+	int bus_num, rc, alen;
+
+	bus_num = i2c_get_bus_num();
+
+	alen = 2;
+
+	rc = ti_i2c_set_alen(bus_num, dev_addr, alen);
+	if (rc)
+		return rc;
+
+	return i2c_read(dev_addr, offset, alen, ep, epsize);
 }
 
 /**
@@ -88,6 +135,11 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
 	 * Read the header first then only read the other contents.
 	 */
 	byte = 2;
+
+	rc = ti_i2c_set_alen(bus_addr, dev_addr, byte);
+	if (rc)
+		return rc;
+
 	rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read, 4);
 	if (rc)
 		return rc;
@@ -100,9 +152,14 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
 		 * 1 byte address (some legacy boards need this..)
 		 */
 		byte = 1;
-		if (rc)
+		if (rc) {
+			rc = ti_i2c_set_alen(bus_addr, dev_addr, byte);
+			if (rc)
+				return rc;
+
 			rc = i2c_read(dev_addr, 0x0, byte, (uint8_t *)&hdr_read,
 				      4);
+		}
 		if (rc)
 			return rc;
 	}
@@ -116,6 +173,30 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr,
 	return 0;
 }
 
+int __maybe_unused ti_i2c_eeprom_am_set(const char *name, const char *rev)
+{
+	struct ti_common_eeprom *ep;
+
+	if (!name || !rev)
+		return -1;
+
+	ep = TI_EEPROM_DATA;
+	if (ep->header == TI_EEPROM_HEADER_MAGIC)
+		goto already_set;
+
+	/* Set to 0 all fields */
+	memset(ep, 0, sizeof(*ep));
+	strncpy(ep->name, name, TI_EEPROM_HDR_NAME_LEN);
+	strncpy(ep->version, rev, TI_EEPROM_HDR_REV_LEN);
+	/* Some dummy serial number to identify the platform */
+	strncpy(ep->serial, "0000", TI_EEPROM_HDR_SERIAL_LEN);
+	/* Mark it with a valid header */
+	ep->header = TI_EEPROM_HEADER_MAGIC;
+
+already_set:
+	return 0;
+}
+
 int __maybe_unused ti_i2c_eeprom_am_get(int bus_addr, int dev_addr)
 {
 	int rc;
@@ -123,14 +204,17 @@ int __maybe_unused ti_i2c_eeprom_am_get(int bus_addr, int dev_addr)
 	struct ti_common_eeprom *ep;
 
 	ep = TI_EEPROM_DATA;
+#ifndef CONFIG_SPL_BUILD
 	if (ep->header == TI_EEPROM_HEADER_MAGIC)
-		goto already_read;
+		return 0; /* EEPROM has already been read */
+#endif
 
 	/* Initialize with a known bad marker for i2c fails.. */
 	ep->header = TI_DEAD_EEPROM_MAGIC;
 	ep->name[0] = 0x0;
 	ep->version[0] = 0x0;
 	ep->serial[0] = 0x0;
+	ep->config[0] = 0x0;
 
 	rc = ti_i2c_eeprom_get(bus_addr, dev_addr, TI_EEPROM_HEADER_MAGIC,
 			       sizeof(am_ep), (uint8_t *)&am_ep);
@@ -156,7 +240,6 @@ int __maybe_unused ti_i2c_eeprom_am_get(int bus_addr, int dev_addr)
 	memcpy(ep->mac_addr, am_ep.mac_addr,
 	       TI_EEPROM_HDR_NO_OF_MAC_ADDR * TI_EEPROM_HDR_ETH_ALEN);
 
-already_read:
 	return 0;
 }
 
@@ -167,14 +250,17 @@ int __maybe_unused ti_i2c_eeprom_dra7_get(int bus_addr, int dev_addr)
 	struct ti_common_eeprom *ep;
 
 	ep = TI_EEPROM_DATA;
+#ifndef CONFIG_SPL_BUILD
 	if (ep->header == DRA7_EEPROM_HEADER_MAGIC)
-		goto already_read;
+		return 0; /* EEPROM has already been read */
+#endif
 
 	/* Initialize with a known bad marker for i2c fails.. */
-	ep->header = 0xADEAD12C;
+	ep->header = TI_DEAD_EEPROM_MAGIC;
 	ep->name[0] = 0x0;
 	ep->version[0] = 0x0;
 	ep->serial[0] = 0x0;
+	ep->config[0] = 0x0;
 	ep->emif1_size = 0;
 	ep->emif2_size = 0;
 
@@ -200,7 +286,6 @@ int __maybe_unused ti_i2c_eeprom_dra7_get(int bus_addr, int dev_addr)
 	strlcpy(ep->config, dra7_ep.config, TI_EEPROM_HDR_CONFIG_LEN + 1);
 	ti_eeprom_string_cleanup(ep->config);
 
-already_read:
 	return 0;
 }
 
@@ -229,9 +314,7 @@ char * __maybe_unused board_ti_get_rev(void)
 {
 	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
 
-	if (ep->header == TI_DEAD_EEPROM_MAGIC)
-		return NULL;
-
+	/* if ep->header == TI_DEAD_EEPROM_MAGIC, this is empty already */
 	return ep->version;
 }
 
@@ -239,9 +322,7 @@ char * __maybe_unused board_ti_get_config(void)
 {
 	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
 
-	if (ep->header == TI_DEAD_EEPROM_MAGIC)
-		return NULL;
-
+	/* if ep->header == TI_DEAD_EEPROM_MAGIC, this is empty already */
 	return ep->config;
 }
 
@@ -249,9 +330,7 @@ char * __maybe_unused board_ti_get_name(void)
 {
 	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
 
-	if (ep->header == TI_DEAD_EEPROM_MAGIC)
-		return NULL;
-
+	/* if ep->header == TI_DEAD_EEPROM_MAGIC, this is empty already */
 	return ep->name;
 }
 
@@ -316,3 +395,75 @@ void __maybe_unused set_board_info_env(char *name)
 	else
 		setenv("board_serial", unknown);
 }
+
+static u64 mac_to_u64(u8 mac[6])
+{
+	int i;
+	u64 addr = 0;
+
+	for (i = 0; i < 6; i++) {
+		addr <<= 8;
+		addr |= mac[i];
+	}
+
+	return addr;
+}
+
+static void u64_to_mac(u64 addr, u8 mac[6])
+{
+	mac[5] = addr;
+	mac[4] = addr >> 8;
+	mac[3] = addr >> 16;
+	mac[2] = addr >> 24;
+	mac[1] = addr >> 32;
+	mac[0] = addr >> 40;
+}
+
+void board_ti_set_ethaddr(int index)
+{
+	uint8_t mac_addr[6];
+	int i;
+	u64 mac1, mac2;
+	u8 mac_addr1[6], mac_addr2[6];
+	int num_macs;
+	/*
+	 * Export any Ethernet MAC addresses from EEPROM.
+	 * The 2 MAC addresses in EEPROM define the address range.
+	 */
+	board_ti_get_eth_mac_addr(0, mac_addr1);
+	board_ti_get_eth_mac_addr(1, mac_addr2);
+
+	if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
+		mac1 = mac_to_u64(mac_addr1);
+		mac2 = mac_to_u64(mac_addr2);
+
+		/* must contain an address range */
+		num_macs = mac2 - mac1 + 1;
+		if (num_macs <= 0)
+			return;
+
+		if (num_macs > 50) {
+			printf("%s: Too many MAC addresses: %d. Limiting to 50\n",
+			       __func__, num_macs);
+			num_macs = 50;
+		}
+
+		for (i = 0; i < num_macs; i++) {
+			u64_to_mac(mac1 + i, mac_addr);
+			if (is_valid_ethaddr(mac_addr)) {
+				eth_setenv_enetaddr_by_index("eth", i + index,
+							     mac_addr);
+			}
+		}
+	}
+}
+
+bool __maybe_unused board_ti_was_eeprom_read(void)
+{
+	struct ti_common_eeprom *ep = TI_EEPROM_DATA;
+
+	if (ep->header == TI_EEPROM_HEADER_MAGIC)
+		return true;
+	else
+		return false;
+}
diff --git a/board/ti/common/board_detect.h b/board/ti/common/board_detect.h
index eb17f6f..893e1ed 100644
--- a/board/ti/common/board_detect.h
+++ b/board/ti/common/board_detect.h
@@ -98,7 +98,7 @@ struct ti_common_eeprom {
 };
 
 #define TI_EEPROM_DATA ((struct ti_common_eeprom *)\
-				OMAP_SRAM_SCRATCH_BOARD_EEPROM_START)
+				TI_SRAM_SCRATCH_BOARD_EEPROM_START)
 
 /**
  * ti_i2c_eeprom_am_get() - Consolidated eeprom data collection for AM* TI EVMs
@@ -133,7 +133,7 @@ bool board_ti_is(char *name_tag);
  *
  * NOTE: revision information is often messed up (hence the str len match) :(
  *
- * Return: false if board information does not match OR eeprom was'nt read.
+ * Return: false if board information does not match OR eeprom wasn't read.
  *	   true otherwise
  */
 bool board_ti_rev_is(char *rev_tag, int cmp_len);
@@ -141,7 +141,7 @@ bool board_ti_rev_is(char *rev_tag, int cmp_len);
 /**
  * board_ti_get_rev() - Get board revision for TI EVMs
  *
- * Return: NULL if eeprom was'nt read.
+ * Return: Empty string if eeprom wasn't read.
  *	   Board revision otherwise
  */
 char *board_ti_get_rev(void);
@@ -149,7 +149,7 @@ char *board_ti_get_rev(void);
 /**
  * board_ti_get_config() - Get board config for TI EVMs
  *
- * Return: NULL if eeprom was'nt read.
+ * Return: Empty string if eeprom wasn't read.
  *	   Board config otherwise
  */
 char *board_ti_get_config(void);
@@ -157,7 +157,7 @@ char *board_ti_get_config(void);
 /**
  * board_ti_get_name() - Get board name for TI EVMs
  *
- * Return: NULL if eeprom was'nt read.
+ * Return: Empty string if eeprom wasn't read.
  *	   Board name otherwise
  */
 char *board_ti_get_name(void);
@@ -174,14 +174,14 @@ void board_ti_get_eth_mac_addr(int index, u8 mac_addr[TI_EEPROM_HDR_ETH_ALEN]);
 /**
  * board_ti_get_emif1_size() - Get size of the DDR on emif1 for TI EVMs
  *
- * Return: NULL if eeprom was'nt read or emif1_size is not available.
+ * Return: NULL if eeprom wasn't read or emif1_size is not available.
  */
 u64 board_ti_get_emif1_size(void);
 
 /**
  * board_ti_get_emif2_size() - Get size of the DDR on emif2 for TI EVMs
  *
- * Return: NULL if eeprom was'nt read or emif2_size is not available.
+ * Return: NULL if eeprom wasn't read or emif2_size is not available.
  */
 u64 board_ti_get_emif2_size(void);
 
@@ -193,4 +193,42 @@ u64 board_ti_get_emif2_size(void);
  */
 void set_board_info_env(char *name);
 
+/**
+ * board_ti_set_ethaddr- Sets the ethaddr environment from EEPROM
+ * @index: The first eth<index>addr environment variable to set
+ *
+ * EEPROM should be already read before calling this function.
+ * The EEPROM contains 2 MAC addresses which define the MAC address
+ * range (i.e. first and last MAC address).
+ * This function sets the ethaddr environment variable for all
+ * the available MAC addresses starting from eth<index>addr.
+ */
+void board_ti_set_ethaddr(int index);
+
+/**
+ * board_ti_was_eeprom_read() - Check to see if the eeprom contents have been read
+ *
+ * This function is useful to determine if the eeprom has already been read and
+ * its contents have already been loaded into memory. It utiltzes the magic
+ * number that the header value is set to upon successful eeprom read.
+ */
+bool board_ti_was_eeprom_read(void);
+
+/**
+ * ti_i2c_eeprom_am_set() - Setup the eeprom data with predefined values
+ * @name:	Name of the board
+ * @rev:	Revision of the board
+ *
+ * In some cases such as in RTC-only mode, we are able to skip reading eeprom
+ * and wasting i2c based initialization time by using predefined flags for
+ * detecting what platform we are booting on. For those platforms, provide
+ * a handy function to pre-program information.
+ *
+ * NOTE: many eeprom information such as serial number, mac address etc is not
+ * available.
+ *
+ * Return: 0 if all went fine, else return error.
+ */
+int ti_i2c_eeprom_am_set(const char *name, const char *rev);
+
 #endif	/* __BOARD_DETECT_H */
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 99e8254..7d36f03 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -36,10 +36,11 @@
 
 #define board_is_dra74x_evm()		board_ti_is("5777xCPU")
 #define board_is_dra72x_evm()		board_ti_is("DRA72x-T")
-#define board_is_dra74x_revh_or_later() board_is_dra74x_evm() &&	\
-				(strncmp("H", board_ti_get_rev(), 1) <= 0)
-#define board_is_dra72x_revc_or_later() board_is_dra72x_evm() &&	\
-				(strncmp("C", board_ti_get_rev(), 1) <= 0)
+#define board_is_dra71x_evm()		board_ti_is("DRA79x,D")
+#define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() &&	\
+				(strncmp("H", board_ti_get_rev(), 1) <= 0))
+#define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() &&	\
+				(strncmp("C", board_ti_get_rev(), 1) <= 0))
 #define board_ti_get_emif_size()	board_ti_get_emif1_size() +	\
 					board_ti_get_emif2_size()
 
@@ -308,35 +309,47 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 }
 
 struct vcores_data dra752_volts = {
-	.mpu.value	= VDD_MPU_DRA7,
-	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU,
+	.mpu.value[OPP_NOM]	= VDD_MPU_DRA7_NOM,
+	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
 	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.mpu.addr	= TPS659038_REG_ADDR_SMPS12,
 	.mpu.pmic	= &tps659038,
 	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
-	.eve.value	= VDD_EVE_DRA7,
-	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE,
+	.eve.value[OPP_NOM]	= VDD_EVE_DRA7_NOM,
+	.eve.value[OPP_OD]	= VDD_EVE_DRA7_OD,
+	.eve.value[OPP_HIGH]	= VDD_EVE_DRA7_HIGH,
+	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_DSPEVE_OD,
+	.eve.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.eve.addr	= TPS659038_REG_ADDR_SMPS45,
 	.eve.pmic	= &tps659038,
 	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
-	.gpu.value	= VDD_GPU_DRA7,
-	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU,
+	.gpu.value[OPP_NOM]	= VDD_GPU_DRA7_NOM,
+	.gpu.value[OPP_OD]	= VDD_GPU_DRA7_OD,
+	.gpu.value[OPP_HIGH]	= VDD_GPU_DRA7_HIGH,
+	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_GPU_OD,
+	.gpu.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_GPU_HIGH,
 	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.gpu.addr	= TPS659038_REG_ADDR_SMPS6,
 	.gpu.pmic	= &tps659038,
 	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
-	.core.value	= VDD_CORE_DRA7,
-	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE,
+	.core.value[OPP_NOM]	= VDD_CORE_DRA7_NOM,
+	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
 	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.core.addr	= TPS659038_REG_ADDR_SMPS7,
 	.core.pmic	= &tps659038,
 
-	.iva.value	= VDD_IVA_DRA7,
-	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA,
+	.iva.value[OPP_NOM]	= VDD_IVA_DRA7_NOM,
+	.iva.value[OPP_OD]	= VDD_IVA_DRA7_OD,
+	.iva.value[OPP_HIGH]	= VDD_IVA_DRA7_HIGH,
+	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_IVA_OD,
+	.iva.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_IVA_HIGH,
 	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.iva.addr	= TPS659038_REG_ADDR_SMPS8,
 	.iva.pmic	= &tps659038,
@@ -344,15 +357,15 @@ struct vcores_data dra752_volts = {
 };
 
 struct vcores_data dra722_volts = {
-	.mpu.value	= VDD_MPU_DRA7,
-	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU,
+	.mpu.value[OPP_NOM]	= VDD_MPU_DRA7_NOM,
+	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
 	.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.mpu.addr	= TPS65917_REG_ADDR_SMPS1,
 	.mpu.pmic	= &tps659038,
 	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
-	.core.value	= VDD_CORE_DRA7,
-	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE,
+	.core.value[OPP_NOM]	= VDD_CORE_DRA7_NOM,
+	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
 	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.core.addr	= TPS65917_REG_ADDR_SMPS2,
 	.core.pmic	= &tps659038,
@@ -361,28 +374,138 @@ struct vcores_data dra722_volts = {
 	 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
 	 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
 	 */
-	.gpu.value	= VDD_GPU_DRA7,
-	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU,
+	.gpu.value[OPP_NOM]	= VDD_GPU_DRA7_NOM,
+	.gpu.value[OPP_OD]	= VDD_GPU_DRA7_OD,
+	.gpu.value[OPP_HIGH]	= VDD_GPU_DRA7_HIGH,
+	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_GPU_OD,
+	.gpu.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_GPU_HIGH,
 	.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.gpu.addr	= TPS65917_REG_ADDR_SMPS3,
 	.gpu.pmic	= &tps659038,
 	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
-	.eve.value	= VDD_EVE_DRA7,
-	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE,
+	.eve.value[OPP_NOM]	= VDD_EVE_DRA7_NOM,
+	.eve.value[OPP_OD]	= VDD_EVE_DRA7_OD,
+	.eve.value[OPP_HIGH]	= VDD_EVE_DRA7_HIGH,
+	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_DSPEVE_OD,
+	.eve.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.eve.addr	= TPS65917_REG_ADDR_SMPS3,
 	.eve.pmic	= &tps659038,
 	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
-	.iva.value	= VDD_IVA_DRA7,
-	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA,
+	.iva.value[OPP_NOM]	= VDD_IVA_DRA7_NOM,
+	.iva.value[OPP_OD]	= VDD_IVA_DRA7_OD,
+	.iva.value[OPP_HIGH]	= VDD_IVA_DRA7_HIGH,
+	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_IVA_OD,
+	.iva.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_IVA_HIGH,
 	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.iva.addr	= TPS65917_REG_ADDR_SMPS3,
 	.iva.pmic	= &tps659038,
 	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
 };
 
+struct vcores_data dra718_volts = {
+	/*
+	 * In the case of dra71x GPU MPU and CORE
+	 * are all powered up by BUCK0 of LP873X PMIC
+	 */
+	.mpu.value[OPP_NOM]	= VDD_MPU_DRA7_NOM,
+	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.mpu.addr	= LP873X_REG_ADDR_BUCK0,
+	.mpu.pmic	= &lp8733,
+	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+	.core.value[OPP_NOM]		= VDD_CORE_DRA7_NOM,
+	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.core.addr	= LP873X_REG_ADDR_BUCK0,
+	.core.pmic	= &lp8733,
+
+	.gpu.value[OPP_NOM]	= VDD_GPU_DRA7_NOM,
+	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.gpu.addr	= LP873X_REG_ADDR_BUCK0,
+	.gpu.pmic	= &lp8733,
+	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+	/*
+	 * The DSPEVE and IVA rails are grouped on DRA71x-evm
+	 * and are powered by BUCK1 of LP873X PMIC
+	 */
+	.eve.value[OPP_NOM]	= VDD_EVE_DRA7_NOM,
+	.eve.value[OPP_HIGH]	= VDD_EVE_DRA7_HIGH,
+	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
+	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.eve.addr	= LP873X_REG_ADDR_BUCK1,
+	.eve.pmic	= &lp8733,
+	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+	.iva.value[OPP_NOM]	= VDD_IVA_DRA7_NOM,
+	.iva.value[OPP_HIGH]	= VDD_IVA_DRA7_HIGH,
+	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
+	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+	.iva.addr	= LP873X_REG_ADDR_BUCK1,
+	.iva.pmic	= &lp8733,
+	.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
+int get_voltrail_opp(int rail_offset)
+{
+	int opp;
+
+	switch (rail_offset) {
+	case VOLT_MPU:
+		opp = DRA7_MPU_OPP;
+		/* DRA71x supports only OPP_NOM for MPU */
+		if (board_is_dra71x_evm())
+			opp = OPP_NOM;
+		break;
+	case VOLT_CORE:
+		opp = DRA7_CORE_OPP;
+		/* DRA71x supports only OPP_NOM for CORE */
+		if (board_is_dra71x_evm())
+			opp = OPP_NOM;
+		break;
+	case VOLT_GPU:
+		opp = DRA7_GPU_OPP;
+		/* DRA71x supports only OPP_NOM for GPU */
+		if (board_is_dra71x_evm())
+			opp = OPP_NOM;
+		break;
+	case VOLT_EVE:
+		opp = DRA7_DSPEVE_OPP;
+		/*
+		 * DRA71x does not support OPP_OD for EVE.
+		 * If OPP_OD is selected by menuconfig, fallback
+		 * to OPP_NOM.
+		 */
+		if (board_is_dra71x_evm() && opp == OPP_OD)
+			opp = OPP_NOM;
+		break;
+	case VOLT_IVA:
+		opp = DRA7_IVA_OPP;
+		/*
+		 * DRA71x does not support OPP_OD for IVA.
+		 * If OPP_OD is selected by menuconfig, fallback
+		 * to OPP_NOM.
+		 */
+		if (board_is_dra71x_evm() && opp == OPP_OD)
+			opp = OPP_NOM;
+		break;
+	default:
+		opp = OPP_NOM;
+	}
+
+	return opp;
+}
+
 /**
  * @brief board_init
  *
@@ -396,7 +519,7 @@ int board_init(void)
 	return 0;
 }
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	u64 ram_size;
 
@@ -408,6 +531,8 @@ void dram_init_banksize(void)
 		gd->bd->bi_dram[1].start = 0x200000000;
 		gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
 	}
+
+	return 0;
 }
 
 int board_late_init(void)
@@ -418,6 +543,8 @@ int board_late_init(void)
 	if (is_dra72x()) {
 		if (board_is_dra72x_revc_or_later())
 			name = "dra72x-revc";
+		else if (board_is_dra71x_evm())
+			name = "dra71x";
 		else
 			name = "dra72x";
 	} else {
@@ -426,7 +553,15 @@ int board_late_init(void)
 
 	set_board_info_env(name);
 
+	/*
+	 * Default FIT boot on HS devices. Non FIT images are not allowed
+	 * on HS devices.
+	 */
+	if (get_device_type() == HS_DEVICE)
+		setenv("boot_fit", "1");
+
 	omap_die_id_serial();
+	omap_set_fastboot_vars();
 #endif
 	return 0;
 }
@@ -458,6 +593,8 @@ void do_board_detect(void)
 		bname = "DRA74x EVM";
 	} else if (board_is_dra72x_evm()) {
 		bname = "DRA72x EVM";
+	} else if (board_is_dra71x_evm()) {
+		bname = "DRA71x EVM";
 	} else {
 		/* If EEPROM is not populated */
 		if (is_dra72x())
@@ -478,6 +615,8 @@ void vcores_init(void)
 		*omap_vcores = &dra752_volts;
 	} else if (board_is_dra72x_evm()) {
 		*omap_vcores = &dra722_volts;
+	} else if (board_is_dra71x_evm()) {
+		*omap_vcores = &dra718_volts;
 	} else {
 		/* If EEPROM is not populated */
 		if (is_dra72x())
@@ -506,7 +645,12 @@ void recalibrate_iodelay(void)
 	case DRA722_ES2_0:
 		pads = dra72x_core_padconf_array_common;
 		npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
-		if (board_is_dra72x_revc_or_later()) {
+		if (board_is_dra71x_evm()) {
+			pads = dra71x_core_padconf_array;
+			npads = ARRAY_SIZE(dra71x_core_padconf_array);
+			iodelay = dra71_iodelay_cfg_array;
+			niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
+		} else if (board_is_dra72x_revc_or_later()) {
 			delta_pads = dra72x_rgmii_padconf_array_revc;
 			delta_npads =
 				ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
@@ -559,7 +703,7 @@ err:
 }
 #endif
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	omap_mmc_init(0, 0, 0, -1, -1);
@@ -607,7 +751,7 @@ static struct ti_usb_phy_device usb_phy2_device = {
 	.index = 1,
 };
 
-int board_usb_init(int index, enum usb_init_type init)
+int omap_xhci_board_usb_init(int index, enum usb_init_type init)
 {
 	enable_usb_clocks(index);
 	switch (index) {
@@ -644,7 +788,7 @@ int board_usb_init(int index, enum usb_init_type init)
 	return 0;
 }
 
-int board_usb_cleanup(int index, enum usb_init_type init)
+int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
 {
 	switch (index) {
 	case 0:
@@ -828,12 +972,21 @@ int ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {
-	if (is_dra72x() && !strcmp(name, "dra72-evm"))
-		return 0;
-	else if (!is_dra72x() && !strcmp(name, "dra7-evm"))
+	if (is_dra72x()) {
+		if (board_is_dra71x_evm()) {
+			if (!strcmp(name, "dra71-evm"))
+				return 0;
+		}else if(board_is_dra72x_revc_or_later()) {
+			if (!strcmp(name, "dra72-evm-revc"))
+				return 0;
+		} else if (!strcmp(name, "dra72-evm")) {
+			return 0;
+		}
+	} else if (!is_dra72x() && !strcmp(name, "dra7-evm")) {
 		return 0;
-	else
-		return -1;
+	}
+
+	return -1;
 }
 #endif
 
@@ -842,4 +995,11 @@ void board_fit_image_post_process(void **p_image, size_t *p_size)
 {
 	secure_boot_verify_image(p_image, p_size);
 }
+
+void board_tee_image_process(ulong tee_image, size_t tee_size)
+{
+	secure_tee_install((u32)tee_image);
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
 #endif
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 34a05dd..2cc4be3 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -193,33 +193,184 @@ const struct pad_conf_entry dra72x_rgmii_padconf_array_revb[] = {
 
 const struct pad_conf_entry dra72x_rgmii_padconf_array_revc[] = {
 	{VIN2A_FLD0, (M14 | PIN_INPUT)},	/* vin2a_fld0.gpio3_30 */
-	{RGMII0_TXC, (M0 | PIN_OUTPUT)},	/* rgmii0_txc.rgmii0_txc */
-	{RGMII0_TXCTL, (M0 | PIN_OUTPUT)},	/* rgmii0_txctl.rgmii0_txctl */
-	{RGMII0_TXD3, (M0 | PIN_OUTPUT)},	/* rgmii0_txd3.rgmii0_txd3 */
-	{RGMII0_TXD2, (M0 | PIN_OUTPUT)},	/* rgmii0_txd2.rgmii0_txd2 */
-	{RGMII0_TXD1, (M0 | PIN_OUTPUT)},	/* rgmii0_txd1.rgmii0_txd1 */
-	{RGMII0_TXD0, (M0 | PIN_OUTPUT)},	/* rgmii0_txd0.rgmii0_txd0 */
-	{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN)},	/* rgmii0_rxc.rgmii0_rxc */
-	{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN)},	/* rgmii0_rxctl.rgmii0_rxctl */
-	{RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN)},	/* rgmii0_rxd3.rgmii0_rxd3 */
-	{RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN)},	/* rgmii0_rxd2.rgmii0_rxd2 */
-	{RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN)},	/* rgmii0_rxd1.rgmii0_rxd1 */
-	{RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN)},	/* rgmii0_rxd0.rgmii0_rxd0 */
-	{VIN2A_D12, (M3 | PIN_OUTPUT)},	/* vin2a_d12.rgmii1_txc */
-	{VIN2A_D13, (M3 | PIN_OUTPUT)},	/* vin2a_d13.rgmii1_txctl */
-	{VIN2A_D14, (M3 | PIN_OUTPUT)},	/* vin2a_d14.rgmii1_txd3 */
-	{VIN2A_D15, (M3 | PIN_OUTPUT)},	/* vin2a_d15.rgmii1_txd2 */
-	{VIN2A_D16, (M3 | PIN_OUTPUT)},	/* vin2a_d16.rgmii1_txd1 */
-	{VIN2A_D17, (M3 | PIN_OUTPUT)},	/* vin2a_d17.rgmii1_txd0 */
-	{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN)},	/* vin2a_d18.rgmii1_rxc */
-	{VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN)},	/* vin2a_d19.rgmii1_rxctl */
-	{VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN)},	/* vin2a_d20.rgmii1_rxd3 */
-	{VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN)},	/* vin2a_d21.rgmii1_rxd2 */
-	{VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN)},	/* vin2a_d22.rgmii1_rxd1 */
-	{VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN)},	/* vin2a_d23.rgmii1_rxd0 */
+	{RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
 	{XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)},	/* xref_clk2.atl_clk2 */
 };
 
+const struct pad_conf_entry dra71x_core_padconf_array[] = {
+	{GPMC_AD0, (M3 | PIN_INPUT)},	/* gpmc_ad0.vout3_d0 */
+	{GPMC_AD1, (M3 | PIN_INPUT)},	/* gpmc_ad1.vout3_d1 */
+	{GPMC_AD2, (M3 | PIN_INPUT)},	/* gpmc_ad2.vout3_d2 */
+	{GPMC_AD3, (M3 | PIN_INPUT)},	/* gpmc_ad3.vout3_d3 */
+	{GPMC_AD4, (M3 | PIN_INPUT)},	/* gpmc_ad4.vout3_d4 */
+	{GPMC_AD5, (M3 | PIN_INPUT)},	/* gpmc_ad5.vout3_d5 */
+	{GPMC_AD6, (M3 | PIN_INPUT)},	/* gpmc_ad6.vout3_d6 */
+	{GPMC_AD7, (M3 | PIN_INPUT)},	/* gpmc_ad7.vout3_d7 */
+	{GPMC_AD8, (M3 | PIN_INPUT)},	/* gpmc_ad8.vout3_d8 */
+	{GPMC_AD9, (M3 | PIN_INPUT)},	/* gpmc_ad9.vout3_d9 */
+	{GPMC_AD10, (M3 | PIN_INPUT)},	/* gpmc_ad10.vout3_d10 */
+	{GPMC_AD11, (M3 | PIN_INPUT)},	/* gpmc_ad11.vout3_d11 */
+	{GPMC_AD12, (M3 | PIN_INPUT)},	/* gpmc_ad12.vout3_d12 */
+	{GPMC_AD13, (M3 | PIN_INPUT)},	/* gpmc_ad13.vout3_d13 */
+	{GPMC_AD14, (M3 | PIN_INPUT)},	/* gpmc_ad14.vout3_d14 */
+	{GPMC_AD15, (M3 | PIN_INPUT)},	/* gpmc_ad15.vout3_d15 */
+	{GPMC_A0, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a0.vout3_d16 */
+	{GPMC_A1, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a1.vout3_d17 */
+	{GPMC_A2, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a2.vout3_d18 */
+	{GPMC_A3, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a3.vout3_d19 */
+	{GPMC_A4, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a4.vout3_d20 */
+	{GPMC_A5, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a5.vout3_d21 */
+	{GPMC_A6, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a6.vout3_d22 */
+	{GPMC_A7, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a7.vout3_d23 */
+	{GPMC_A8, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a8.vout3_hsync */
+	{GPMC_A9, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a9.vout3_vsync */
+	{GPMC_A10, (M3 | PIN_INPUT_PULLDOWN)},	/* gpmc_a10.vout3_de */
+	{GPMC_A11, (M14 | PIN_INPUT)},	/* gpmc_a11.gpio2_1 */
+	{GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a13.qspi1_rtclk */
+	{GPMC_A14, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a14.qspi1_d3 */
+	{GPMC_A15, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_a15.qspi1_d2 */
+	{GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a16.qspi1_d0 */
+	{GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a17.qspi1_d1 */
+	{GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a18.qspi1_sclk */
+	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a19.mmc2_dat4 */
+	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a20.mmc2_dat5 */
+	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a21.mmc2_dat6 */
+	{GPMC_A22, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a22.mmc2_dat7 */
+	{GPMC_A23, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a23.mmc2_clk */
+	{GPMC_A24, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a24.mmc2_dat0 */
+	{GPMC_A25, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a25.mmc2_dat1 */
+	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a26.mmc2_dat2 */
+	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a27.mmc2_dat3 */
+	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
+	{GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_cs2.qspi1_cs0 */
+	{GPMC_CS3, (M3 | PIN_INPUT_PULLUP)},	/* gpmc_cs3.vout3_clk */
+	{VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)},	/* vin2a_clk0.vin2a_clk0 */
+	{VIN2A_FLD0, (M14 | PIN_INPUT)},	/* vin2a_fld0.gpio3_30 */
+	{VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)},	/* vin2a_hsync0.vin2a_hsync0 */
+	{VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)},	/* vin2a_vsync0.vin2a_vsync0 */
+	{VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},	/* vin2a_d0.vin2a_d0 */
+	{VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},	/* vin2a_d1.vin2a_d1 */
+	{VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},	/* vin2a_d2.vin2a_d2 */
+	{VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)},	/* vin2a_d3.vin2a_d3 */
+	{VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)},	/* vin2a_d4.vin2a_d4 */
+	{VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE8)},	/* vin2a_d5.vin2a_d5 */
+	{VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)},	/* vin2a_d6.vin2a_d6 */
+	{VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE6)},	/* vin2a_d7.vin2a_d7 */
+	{VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)},	/* vin2a_d8.vin2a_d8 */
+	{VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE2)},	/* vin2a_d9.vin2a_d9 */
+	{VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)},	/* vin2a_d10.vin2a_d10 */
+	{VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE5)},	/* vin2a_d11.vin2a_d11 */
+	{VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+	{VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)},	/* N/A.N/A */
+	{VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)},	/* N/A.N/A */
+	{VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)},	/* N/A.N/A */
+	{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_mclk.mdio_mclk */
+	{MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mdio_d.mdio_d */
+	{RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	{RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
+	{RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
+	{RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
+	{RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
+	{RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
+	{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	{RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
+	{RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
+	{RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb1_drvvbus.usb1_drvvbus */
+	{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb2_drvvbus.usb2_drvvbus */
+	{GPIO6_14, (M9 | PIN_INPUT_PULLUP)},	/* gpio6_14.i2c3_sda */
+	{GPIO6_15, (M9 | PIN_INPUT_PULLUP)},	/* gpio6_15.i2c3_scl */
+	{GPIO6_16, (M14 | PIN_INPUT_PULLUP)},	/* gpio6_16.gpio6_16 */
+	{XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)},	/* xref_clk2.atl_clk2 */
+	{MCASP1_ACLKX, (M14 | PIN_INPUT)},	/* mcasp1_aclkx.gpio7_31 */
+	{MCASP1_FSX, (M14 | 0x000d0000)},	/* mcasp1_fsx.gpio7_30 */
+	{MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr0.i2c5_sda */
+	{MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr1.i2c5_scl */
+	{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr2.gpio5_4 */
+	{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr3.gpio5_5 */
+	{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr4.gpio5_6 */
+	{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr5.gpio5_7 */
+	{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr6.gpio5_8 */
+	{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr7.gpio5_9 */
+	{MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr12.mcasp7_axr0 */
+	{MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr13.mcasp7_axr1 */
+	{MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr14.mcasp7_aclkx */
+	{MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},	/* mcasp1_axr15.mcasp7_fsx */
+	{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.mcasp3_aclkx */
+	{MCASP3_FSX, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_fsx.mcasp3_fsx */
+	{MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)},	/* mcasp3_axr0.mcasp3_axr0 */
+	{MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)},	/* mcasp3_axr1.mcasp3_axr1 */
+	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
+	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
+	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
+	{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat2.mmc1_dat2 */
+	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
+	{MMC1_SDCD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mmc1_sdcd.gpio6_27 */
+	{MMC1_SDWP, (M14 | PIN_INPUT_SLEW)},	/* mmc1_sdwp.gpio6_28 */
+	{SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_sclk.spi1_sclk */
+	{SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_d1.spi1_d1 */
+	{SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)},	/* spi1_d0.spi1_d0 */
+	{SPI1_CS0, (M0 | PIN_INPUT_PULLUP)},	/* spi1_cs0.spi1_cs0 */
+	{SPI1_CS1, (M14 | PIN_INPUT_PULLUP)},	/* spi1_cs1.gpio7_11 */
+	{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_cs2.gpio7_12 */
+	{SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
+	{SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)},	/* spi2_sclk.uart3_rxd */
+	{SPI2_D1, (M1 | PIN_INPUT_SLEW)},	/* spi2_d1.uart3_txd */
+	{SPI2_D0, (M1 | PIN_INPUT_SLEW)},	/* spi2_d0.uart3_ctsn */
+	{SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi2_cs0.uart3_rtsn */
+	{DCAN1_TX, (M15 | PULL_UP)},	/* dcan1_tx.safe for dcan1_tx */
+	{DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* dcan1_rx.gpio1_15 */
+	{UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_rxd.uart1_rxd */
+	{UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* uart1_txd.uart1_txd */
+	{UART1_CTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart1_ctsn.mmc4_clk */
+	{UART1_RTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart1_rtsn.mmc4_cmd */
+	{UART2_RXD, (M3 | PIN_INPUT_PULLUP)},	/* uart2_rxd.mmc4_dat0 */
+	{UART2_TXD, (M3 | PIN_INPUT_PULLUP)},	/* uart2_txd.mmc4_dat1 */
+	{UART2_CTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart2_ctsn.mmc4_dat2 */
+	{UART2_RTSN, (M3 | PIN_INPUT_PULLUP)},	/* uart2_rtsn.mmc4_dat3 */
+	{I2C2_SDA, (M1 | PIN_INPUT_PULLUP)},	/* i2c2_sda.hdmi1_ddc_scl */
+	{I2C2_SCL, (M1 | PIN_INPUT_PULLUP)},	/* i2c2_scl.hdmi1_ddc_sda */
+	{WAKEUP0, (M15 | PULL_UP)},	/* Wakeup0.safe for dcan1_rx */
+	{WAKEUP3, (M1 | PULL_ENA | PULL_UP)},	/* Wakeup3.sys_nirq1 */
+};
+
 const struct pad_conf_entry early_padconf[] = {
 #if (CONFIG_CONS_INDEX == 1)
 	{UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */
@@ -277,9 +428,83 @@ const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revc[] = {
 	{0x0170, 0, 0},	/* CFG_GPMC_A16_OUT */
 	{0x0174, 2251, 1217},	/* CFG_GPMC_A17_IN */
 	{0x0188, 0, 0},	/* CFG_GPMC_A18_OUT */
-	{0x0374, 0, 0},	/* CFG_GPMC_CS2_OUT */
+	{0x0374, 121, 0},	/* CFG_GPMC_CS2_OUT */
+	{0x06F0, 413, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 27, 2296},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 3, 1721},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 134, 1786},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 40, 1966},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 0, 2057},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 0, 60},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 0, 60},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 0, 60},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 0, 0},		/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 0, 60},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 0, 120},	/* CFG_RGMII0_TXD3_OUT */
+	{0x0A70, 0, 0},		/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 170, 0},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 150, 0},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 0, 0},		/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 60, 0},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 60, 0},	/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 530, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 71, 1099},	/* CFG_VIN2A_D19_IN */
+	{0x0AC8, 2229, 10},	/* CFG_VIN2A_D1_IN */
+	{0x0AD4, 142, 1337},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 114, 1517},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 171, 1331},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 0, 1328},	/* CFG_VIN2A_D23_IN */
 };
 
+const struct iodelay_cfg_entry dra71_iodelay_cfg_array[] = {
+	{0x0144, 0, 0},	/* CFG_GPMC_A13_IN */
+	{0x0150, 2247, 1186},	/* CFG_GPMC_A14_IN */
+	{0x015C, 2176, 1197},	/* CFG_GPMC_A15_IN */
+	{0x0168, 2229, 1268},	/* CFG_GPMC_A16_IN */
+	{0x0170, 0, 0},	/* CFG_GPMC_A16_OUT */
+	{0x0174, 2251, 1217},	/* CFG_GPMC_A17_IN */
+	{0x0188, 0, 0},	/* CFG_GPMC_A18_OUT */
+	{0x0374, 0, 0},	/* CFG_GPMC_CS2_OUT */
+	{0x06F0, 413, 0},	/* CFG_RGMII0_RXC_IN */
+	{0x06FC, 27, 2296},	/* CFG_RGMII0_RXCTL_IN */
+	{0x0708, 3, 1721},	/* CFG_RGMII0_RXD0_IN */
+	{0x0714, 134, 1786},	/* CFG_RGMII0_RXD1_IN */
+	{0x0720, 40, 1966},	/* CFG_RGMII0_RXD2_IN */
+	{0x072C, 0, 2057},	/* CFG_RGMII0_RXD3_IN */
+	{0x0740, 0, 60},	/* CFG_RGMII0_TXC_OUT */
+	{0x074C, 0, 60},	/* CFG_RGMII0_TXCTL_OUT */
+	{0x0758, 0, 60},	/* CFG_RGMII0_TXD0_OUT */
+	{0x0764, 0, 0},	/* CFG_RGMII0_TXD1_OUT */
+	{0x0770, 0, 60},	/* CFG_RGMII0_TXD2_OUT */
+	{0x077C, 0, 120},	/* CFG_RGMII0_TXD3_OUT */
+	{0x0A38, 0, 0},	/* CFG_VIN2A_CLK0_IN */
+	{0x0A44, 1936, 0},	/* CFG_VIN2A_D0_IN */
+	{0x0A50, 2031, 0},	/* CFG_VIN2A_D10_IN */
+	{0x0A5C, 1702, 0},	/* CFG_VIN2A_D11_IN */
+	{0x0A70, 0, 0},	/* CFG_VIN2A_D12_OUT */
+	{0x0A7C, 170, 0},	/* CFG_VIN2A_D13_OUT */
+	{0x0A88, 150, 0},	/* CFG_VIN2A_D14_OUT */
+	{0x0A94, 0, 0},	/* CFG_VIN2A_D15_OUT */
+	{0x0AA0, 60, 0},	/* CFG_VIN2A_D16_OUT */
+	{0x0AAC, 60, 0},	/* CFG_VIN2A_D17_OUT */
+	{0x0AB0, 530, 0},	/* CFG_VIN2A_D18_IN */
+	{0x0ABC, 71, 1099},	/* CFG_VIN2A_D19_IN */
+	{0x0AC8, 2229, 10},	/* CFG_VIN2A_D1_IN */
+	{0x0AD4, 142, 1337},	/* CFG_VIN2A_D20_IN */
+	{0x0AE0, 114, 1517},	/* CFG_VIN2A_D21_IN */
+	{0x0AEC, 171, 1331},	/* CFG_VIN2A_D22_IN */
+	{0x0AF8, 0, 1328},	/* CFG_VIN2A_D23_IN */
+	{0x0B04, 1736, 0},	/* CFG_VIN2A_D2_IN */
+	{0x0B10, 1943, 0},	/* CFG_VIN2A_D3_IN */
+	{0x0B1C, 1601, 0},	/* CFG_VIN2A_D4_IN */
+	{0x0B28, 2052, 0},	/* CFG_VIN2A_D5_IN */
+	{0x0B34, 1571, 0},	/* CFG_VIN2A_D6_IN */
+	{0x0B40, 1855, 0},	/* CFG_VIN2A_D7_IN */
+	{0x0B4C, 1224, 618},	/* CFG_VIN2A_D8_IN */
+	{0x0B58, 1373, 509},	/* CFG_VIN2A_D9_IN */
+	{0x0B7C, 1943, 0},	/* CFG_VIN2A_HSYNC0_IN */
+	{0x0B88, 1612, 0},	/* CFG_VIN2A_VSYNC0_IN */
+};
 #endif
 
 const struct pad_conf_entry dra74x_core_padconf_array[] = {
diff --git a/board/ti/evm/MAINTAINERS b/board/ti/evm/MAINTAINERS
index 612a08a..cd315c1 100644
--- a/board/ti/evm/MAINTAINERS
+++ b/board/ti/evm/MAINTAINERS
@@ -1,5 +1,5 @@
 EVM BOARD
-M:	Tom Rini <trini@konsulko.com>
+M:	Derald D. Woods <woods.technical@gmail.com>
 S:	Maintained
 F:	board/ti/evm/
 F:	include/configs/omap3_evm.h
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index ff3971d..6f75bd1 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -12,6 +12,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <dm.h>
+#include <ns16550.h>
 #include <netdev.h>
 #include <asm/io.h>
 #include <asm/arch/mem.h>
@@ -22,14 +24,35 @@
 #include <i2c.h>
 #include <twl4030.h>
 #include <asm/mach-types.h>
+#include <asm/omap_musb.h>
 #include <linux/mtd/nand.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/musb.h>
 #include "evm.h"
 
-#define OMAP3EVM_GPIO_ETH_RST_GEN1		64
-#define OMAP3EVM_GPIO_ETH_RST_GEN2		7
+#ifdef CONFIG_USB_EHCI_HCD
+#include <usb.h>
+#include <asm/ehci-omap.h>
+#endif
+
+#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
+#define OMAP3EVM_GPIO_ETH_RST_GEN2 7
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static const struct ns16550_platdata omap3_evm_serial = {
+	.base = OMAP34XX_UART1,
+	.reg_shift = 2,
+	.clock = V_NS16550_CLK,
+	.fcr = UART_FCR_DEFVAL,
+};
+
+U_BOOT_DEVICE(omap3_evm_uart) = {
+	"ns16550_serial",
+	&omap3_evm_serial
+};
+
 static u32 omap3_evm_version;
 
 u32 get_omap3_evm_rev(void)
@@ -60,25 +83,19 @@ static void omap3_evm_get_revision(void)
 	default:
 		omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
        }
-#else
+#else /* !CONFIG_CMD_NET */
 #if defined(CONFIG_STATIC_BOARD_REV)
-	/*
-	 * Look for static defintion of the board revision
-	 */
+	/* Look for static defintion of the board revision */
 	omap3_evm_version = CONFIG_STATIC_BOARD_REV;
 #else
-	/*
-	 * Fallback to the default above.
-	 */
+	/* Fallback to the default above */
 	omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
-#endif
-#endif	/* CONFIG_CMD_NET */
+#endif /* CONFIG_STATIC_BOARD_REV */
+#endif /* CONFIG_CMD_NET */
 }
 
-#ifdef CONFIG_USB_OMAP3
-/*
- * MUSB port on OMAP3EVM Rev >= E requires extvbus programming.
- */
+#if defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)
+/* MUSB port on OMAP3EVM Rev >= E requires extvbus programming. */
 u8 omap3_evm_need_extvbus(void)
 {
 	u8 retval = 0;
@@ -88,7 +105,7 @@ u8 omap3_evm_need_extvbus(void)
 
 	return retval;
 }
-#endif
+#endif /* CONFIG_USB_MUSB_{GADGET,HOST} */
 
 /*
  * Routine: board_init
@@ -105,7 +122,7 @@ int board_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD)
 /*
  * Routine: get_board_mem_timings
  * Description: If we use SPL then there is no x-loader nor config header
@@ -138,7 +155,34 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
 	timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 	timings->mr = MICRON_V_MR_165;
 }
-#endif
+#endif /* CONFIG_SPL_BUILD */
+
+#if defined(CONFIG_USB_MUSB_OMAP2PLUS)
+static struct musb_hdrc_config musb_config = {
+	.multipoint     = 1,
+	.dyn_fifo       = 1,
+	.num_eps        = 16,
+	.ram_bits       = 12,
+};
+
+static struct omap_musb_board_data musb_board_data = {
+	.interface_type	= MUSB_INTERFACE_ULPI,
+};
+
+static struct musb_hdrc_platform_data musb_plat = {
+#if defined(CONFIG_USB_MUSB_HOST)
+	.mode           = MUSB_HOST,
+#elif defined(CONFIG_USB_MUSB_GADGET)
+	.mode		= MUSB_PERIPHERAL,
+#else
+#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
+#endif /* CONFIG_USB_MUSB_{GADGET,HOST} */
+	.config         = &musb_config,
+	.power          = 100,
+	.platform_ops	= &omap2430_ops,
+	.board_data	= &musb_board_data,
+};
+#endif /* CONFIG_USB_MUSB_OMAP2PLUS */
 
 /*
  * Routine: misc_init_r
@@ -146,8 +190,9 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
  */
 int misc_init_r(void)
 {
+	twl4030_power_init();
 
-#ifdef CONFIG_SYS_I2C_OMAP34XX
+#ifdef CONFIG_SYS_I2C_OMAP24XX
 	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 #endif
 
@@ -161,6 +206,13 @@ int misc_init_r(void)
 #endif
 	omap_die_id_display();
 
+#if defined(CONFIG_USB_MUSB_OMAP2PLUS)
+	musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
+#endif
+
+#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)
+	omap_die_id_usbethaddr();
+#endif
 	return 0;
 }
 
@@ -175,7 +227,7 @@ void set_muxconf_regs(void)
 	MUX_EVM();
 }
 
-#ifdef CONFIG_CMD_NET
+#if defined(CONFIG_CMD_NET)
 /*
  * Routine: setup_net_chip
  * Description: Setting up the configuration GPMC registers specific to the
@@ -237,7 +289,7 @@ static void reset_net_chip(void)
 int board_eth_init(bd_t *bis)
 {
 	int rc = 0;
-#ifdef CONFIG_SMC911X
+#if defined(CONFIG_SMC911X)
 #define STR_ENV_ETHADDR	"ethaddr"
 
 	struct eth_device *dev;
@@ -254,21 +306,45 @@ int board_eth_init(bd_t *bis)
 			rc = -1;
 		}
 	}
-#endif
+#endif /* CONFIG_SMC911X */
 	return rc;
 }
 #endif /* CONFIG_CMD_NET */
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
 }
-#endif
 
-#if defined(CONFIG_GENERIC_MMC)
 void board_mmc_power_init(void)
 {
 	twl4030_power_mmc_init(0);
 }
-#endif
+#endif /* CONFIG_MMC */
+
+#if defined(CONFIG_USB_EHCI_HCD)
+static struct omap_usbhs_board_data usbhs_bdata = {
+	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
+};
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+	return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(int index)
+{
+	return omap_ehci_hcd_stop();
+}
+#endif /* CONFIG_USB_EHCI_HCD */
+
+#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) && !defined(CONFIG_CMD_NET)
+int board_eth_init(bd_t *bis)
+{
+	return usb_eth_initialize(bis);
+}
+#endif /* CONFIG_USB_ETHER */
diff --git a/board/ti/evm/evm.h b/board/ti/evm/evm.h
index 91e9b88..0f8268b 100644
--- a/board/ti/evm/evm.h
+++ b/board/ti/evm/evm.h
@@ -278,12 +278,19 @@ static void reset_net_chip(void);
 								 /* TS_PEN_IRQ */\
 	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | DIS | M4)) /*GPIO_176*/\
 								 /* - LAN_INTR*/\
-	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M0)) /*McSPI1_CS3*/\
-	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) /*McSPI2_CLK*/\
-	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI2_SIMO*/\
-	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI2_SOMI*/\
-	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M0)) /*McSPI2_CS0*/\
-	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M0)) /*McSPI2_CS1*/\
+ /* USB EHCI (port 2) */\
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA2*/\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA7*/\
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA4*/\
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA5*/\
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA6*/\
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA3*/\
+	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
+	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DIR*/\
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | EN  | M3)) /*HSUSB2_NXT*/\
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA0*/\
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | EN  | M3)) /*HSUSB2_DATA1*/\
  /*Control and debug */\
 	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
 	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
@@ -318,12 +325,6 @@ static void reset_net_chip(void);
 	MUX_VAL(CP(ETK_D7_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D7*/\
 	MUX_VAL(CP(ETK_D8_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D8*/\
 	MUX_VAL(CP(ETK_D9_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D9*/\
-	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D10*/\
-	MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D11*/\
-	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D12*/\
-	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D13*/\
-	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D14*/\
-	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D15*/\
  /*Die to Die */\
 	MUX_VAL(CP(D2D_MCAD1),		(IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
 	MUX_VAL(CP(D2D_MCAD2),		(IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig
index c0568ec..9477f53 100644
--- a/board/ti/ks2_evm/Kconfig
+++ b/board/ti/ks2_evm/Kconfig
@@ -49,3 +49,5 @@ config SYS_CONFIG_NAME
 	default "k2g_evm"
 
 endif
+
+source "board/ti/common/Kconfig"
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
index 7ef2d2b..879f8b5 100644
--- a/board/ti/ks2_evm/Makefile
+++ b/board/ti/ks2_evm/Makefile
@@ -6,12 +6,12 @@
 #
 
 obj-y += board.o
-obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
-obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
-obj-$(CONFIG_K2E_EVM) += board_k2e.o
-obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
-obj-$(CONFIG_K2L_EVM) += board_k2l.o
-obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o
-obj-$(CONFIG_K2L_EVM) += ddr3_cfg.o
-obj-$(CONFIG_K2G_EVM) += board_k2g.o
-obj-$(CONFIG_K2G_EVM) += ddr3_k2g.o
+obj-$(CONFIG_TARGET_K2HK_EVM) += board_k2hk.o
+obj-$(CONFIG_TARGET_K2HK_EVM) += ddr3_k2hk.o
+obj-$(CONFIG_TARGET_K2E_EVM) += board_k2e.o
+obj-$(CONFIG_TARGET_K2E_EVM) += ddr3_k2e.o
+obj-$(CONFIG_TARGET_K2L_EVM) += board_k2l.o
+obj-$(CONFIG_TARGET_K2L_EVM) += ddr3_k2l.o
+obj-$(CONFIG_TARGET_K2L_EVM) += ddr3_cfg.o
+obj-$(CONFIG_TARGET_K2G_EVM) += board_k2g.o
+obj-$(CONFIG_TARGET_K2G_EVM) += ddr3_k2g.o
diff --git a/board/ti/ks2_evm/README b/board/ti/ks2_evm/README
index 5430c7d..a26b7f8 100644
--- a/board/ti/ks2_evm/README
+++ b/board/ti/ks2_evm/README
@@ -61,7 +61,7 @@ configs/k2g_evm_defconfig
 
 Supported boot modes:
  - SPI NOR boot
- - AEMIF NAND boot
+ - AEMIF NAND boot (K2E, K2L and K2HK)
  - UART boot
  - MMC boot (Only on K2G)
 
@@ -69,7 +69,7 @@ Supported image formats:
  - u-boot.bin: for loading and running u-boot.bin through
 		Texas Instruments code composure studio (CCS) and for UART boot.
  - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot
- - MLO: gpimage for programming AEMIF NAND flash for NAND boot, MMC boot.
+ - MLO: gpimage for programming NAND flash for NAND boot, MMC boot.
 
 Build instructions:
 ===================
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 1de7df0..c61baee 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -45,11 +45,18 @@ int dram_init(void)
 	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 				    CONFIG_MAX_RAM_BANK_SIZE);
 #if defined(CONFIG_TI_AEMIF)
-	aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
+	if (!board_is_k2g_ice())
+		aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
 #endif
 
-	if (ddr3_size)
-		ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
+	if (!board_is_k2g_ice()) {
+		if (ddr3_size)
+			ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
+		else
+			ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
+				      gd->ram_size >> 30);
+	}
+
 	return 0;
 }
 
@@ -274,3 +281,10 @@ void ft_board_setup_ex(void *blob, bd_t *bd)
 	ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
 }
 #endif /* CONFIG_OF_BOARD_SETUP */
+
+#if defined(CONFIG_DTB_RESELECT)
+int __weak embedded_dtb_select(void)
+{
+	return 0;
+}
+#endif
diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h
index 2bbd792..b3ad188 100644
--- a/board/ti/ks2_evm/board.h
+++ b/board/ti/ks2_evm/board.h
@@ -11,9 +11,30 @@
 #define _KS2_BOARD
 
 #include <asm/ti-common/keystone_net.h>
+#include "../common/board_detect.h"
 
 extern struct eth_priv_t eth_priv_cfg[];
 
+#if defined(CONFIG_TI_I2C_BOARD_DETECT)
+static inline int board_is_k2g_gp(void)
+{
+	return board_ti_is("66AK2GGP");
+}
+static inline int board_is_k2g_ice(void)
+{
+	return board_ti_is("66AK2GIC");
+}
+#else
+static inline int board_is_k2g_gp(void)
+{
+	return false;
+}
+static inline int board_is_k2g_ice(void)
+{
+	return false;
+}
+#endif
+
 int get_num_eth_ports(void);
 void spl_init_keystone_plls(void);
 
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index cbb3077..266a66b 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -14,12 +14,30 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-unsigned int external_clk[ext_clk_count] = {
-	[sys_clk]	= 100000000,
-	[alt_core_clk]	= 100000000,
-	[pa_clk]	= 100000000,
-	[ddr3a_clk]	= 100000000,
-};
+unsigned int get_external_clk(u32 clk)
+{
+	unsigned int clk_freq;
+
+	switch (clk) {
+	case sys_clk:
+		clk_freq = 100000000;
+		break;
+	case alt_core_clk:
+		clk_freq = 100000000;
+		break;
+	case pa_clk:
+		clk_freq = 100000000;
+		break;
+	case ddr3a_clk:
+		clk_freq = 100000000;
+		break;
+	default:
+		clk_freq = 0;
+		break;
+	}
+
+	return clk_freq;
+}
 
 static struct pll_init_data core_pll_config[NUM_SPDS] = {
 	[SPD800]	= CORE_PLL_800,
@@ -148,6 +166,16 @@ int get_num_eth_ports(void)
 }
 #endif
 
+#if defined(CONFIG_FIT_EMBED)
+int board_fit_config_name_match(const char *name)
+{
+	if (!strcmp(name, "keystone-k2e-evm"))
+		return 0;
+
+	return -1;
+}
+#endif
+
 #if defined(CONFIG_BOARD_EARLY_INIT_F)
 int board_early_init_f(void)
 {
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index 8f16845..2160576 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -11,18 +11,49 @@
 #include <asm/ti-common/keystone_net.h>
 #include <asm/arch/psc_defs.h>
 #include <asm/arch/mmc_host_def.h>
+#include <fdtdec.h>
+#include <i2c.h>
 #include "mux-k2g.h"
+#include "../common/board_detect.h"
 
-#define SYS_CLK		24000000
+#define K2G_GP_AUDIO_CODEC_ADDRESS	0x1B
 
-unsigned int external_clk[ext_clk_count] = {
-	[sys_clk]	=	SYS_CLK,
-	[pa_clk]	=	SYS_CLK,
-	[tetris_clk]	=	SYS_CLK,
-	[ddr3a_clk]	=	SYS_CLK,
-	[uart_clk]	=	SYS_CLK,
+const unsigned int sysclk_array[MAX_SYSCLK] = {
+	19200000,
+	24000000,
+	25000000,
+	26000000,
 };
 
+unsigned int get_external_clk(u32 clk)
+{
+	unsigned int clk_freq;
+	u8 sysclk_index = get_sysclk_index();
+
+	switch (clk) {
+	case sys_clk:
+		clk_freq = sysclk_array[sysclk_index];
+		break;
+	case pa_clk:
+		clk_freq = sysclk_array[sysclk_index];
+		break;
+	case tetris_clk:
+		clk_freq = sysclk_array[sysclk_index];
+		break;
+	case ddr3a_clk:
+		clk_freq = sysclk_array[sysclk_index];
+		break;
+	case uart_clk:
+		clk_freq = sysclk_array[sysclk_index];
+		break;
+	default:
+		clk_freq = 0;
+		break;
+	}
+
+	return clk_freq;
+}
+
 static int arm_speeds[DEVSPEED_NUMSPDS] = {
 	SPD400,
 	SPD600,
@@ -47,49 +78,116 @@ static int dev_speeds[DEVSPEED_NUMSPDS] = {
 	SPD400,
 };
 
-static struct pll_init_data main_pll_config[NUM_SPDS] = {
-	[SPD400]	= {MAIN_PLL, 100, 3, 2},
-	[SPD600]	= {MAIN_PLL, 300, 6, 2},
-	[SPD800]	= {MAIN_PLL, 200, 3, 2},
-	[SPD900] =	{TETRIS_PLL, 75, 1, 2},
-	[SPD1000] =	{TETRIS_PLL, 250, 3, 2},
+static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
+	[SYSCLK_19MHz] = {
+		[SPD400]	= {MAIN_PLL, 125, 3, 2},
+		[SPD600]	= {MAIN_PLL, 125, 2, 2},
+		[SPD800]	= {MAIN_PLL, 250, 3, 2},
+		[SPD900]	= {MAIN_PLL, 187, 2, 2},
+		[SPD1000]	= {MAIN_PLL, 104, 1, 2},
+	},
+	[SYSCLK_24MHz] = {
+		[SPD400]	= {MAIN_PLL, 100, 3, 2},
+		[SPD600]	= {MAIN_PLL, 300, 6, 2},
+		[SPD800]	= {MAIN_PLL, 200, 3, 2},
+		[SPD900]	= {MAIN_PLL, 75, 1, 2},
+		[SPD1000]	= {MAIN_PLL, 250, 3, 2},
+	},
+	[SYSCLK_25MHz] = {
+		[SPD400]	= {MAIN_PLL, 32, 1, 2},
+		[SPD600]	= {MAIN_PLL, 48, 1, 2},
+		[SPD800]	= {MAIN_PLL, 64, 1, 2},
+		[SPD900]	= {MAIN_PLL, 72, 1, 2},
+		[SPD1000]	= {MAIN_PLL, 80, 1, 2},
+	},
+	[SYSCLK_26MHz] = {
+		[SPD400]	= {MAIN_PLL, 400, 13, 2},
+		[SPD600]	= {MAIN_PLL, 230, 5, 2},
+		[SPD800]	= {MAIN_PLL, 123, 2, 2},
+		[SPD900]	= {MAIN_PLL, 69, 1, 2},
+		[SPD1000]	= {MAIN_PLL, 384, 5, 2},
+	},
+};
+
+static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
+	[SYSCLK_19MHz] = {
+		[SPD200]	= {TETRIS_PLL, 625, 6, 10},
+		[SPD400]	= {TETRIS_PLL, 125, 1, 6},
+		[SPD600]	= {TETRIS_PLL, 125, 1, 4},
+		[SPD800]	= {TETRIS_PLL, 333, 2, 4},
+		[SPD900]	= {TETRIS_PLL, 187, 2, 2},
+		[SPD1000]	= {TETRIS_PLL, 104, 1, 2},
+	},
+	[SYSCLK_24MHz] = {
+		[SPD200]	= {TETRIS_PLL, 250, 3, 10},
+		[SPD400]	= {TETRIS_PLL, 100, 1, 6},
+		[SPD600]	= {TETRIS_PLL, 100, 1, 4},
+		[SPD800]	= {TETRIS_PLL, 400, 3, 4},
+		[SPD900]	= {TETRIS_PLL, 75, 1, 2},
+		[SPD1000]	= {TETRIS_PLL, 250, 3, 2},
+	},
+	[SYSCLK_25MHz] = {
+		[SPD200]	= {TETRIS_PLL, 80, 1, 10},
+		[SPD400]	= {TETRIS_PLL, 96, 1, 6},
+		[SPD600]	= {TETRIS_PLL, 96, 1, 4},
+		[SPD800]	= {TETRIS_PLL, 128, 1, 4},
+		[SPD900]	= {TETRIS_PLL, 72, 1, 2},
+		[SPD1000]	= {TETRIS_PLL, 80, 1, 2},
+	},
+	[SYSCLK_26MHz] = {
+		[SPD200]	= {TETRIS_PLL, 307, 4, 10},
+		[SPD400]	= {TETRIS_PLL, 369, 4, 6},
+		[SPD600]	= {TETRIS_PLL, 369, 4, 4},
+		[SPD800]	= {TETRIS_PLL, 123, 1, 4},
+		[SPD900]	= {TETRIS_PLL, 69, 1, 2},
+		[SPD1000]	= {TETRIS_PLL, 384, 5, 2},
+	},
+};
+
+static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
+	[SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
+	[SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
+	[SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
+	[SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
 };
 
-static struct pll_init_data tetris_pll_config[NUM_SPDS] = {
-	[SPD200] =	{TETRIS_PLL, 250, 3, 10},
-	[SPD400] =	{TETRIS_PLL, 100, 1, 6},
-	[SPD600] =	{TETRIS_PLL, 100, 1, 4},
-	[SPD800] =	{TETRIS_PLL, 400, 3, 4},
-	[SPD900] =	{TETRIS_PLL, 75, 1, 2},
-	[SPD1000] =	{TETRIS_PLL, 250, 3, 2},
+static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
+	[SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
+	[SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
+	[SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
+	[SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
 };
 
-static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
-static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
-static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};
+static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = {
+	[SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
+	[SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
+	[SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
+	[SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
+};
 
 struct pll_init_data *get_pll_init_data(int pll)
 {
 	int speed;
 	struct pll_init_data *data = NULL;
+	u8 sysclk_index = get_sysclk_index();
 
 	switch (pll) {
 	case MAIN_PLL:
 		speed = get_max_dev_speed(dev_speeds);
-		data = &main_pll_config[speed];
+		data = &main_pll_config[sysclk_index][speed];
 		break;
 	case TETRIS_PLL:
 		speed = get_max_arm_speed(arm_speeds);
-		data = &tetris_pll_config[speed];
+		data = &tetris_pll_config[sysclk_index][speed];
 		break;
 	case NSS_PLL:
-		data = &nss_pll_config;
+		data = &nss_pll_config[sysclk_index];
 		break;
 	case UART_PLL:
-		data = &uart_pll_config;
+		data = &uart_pll_config[sysclk_index];
 		break;
 	case DDR3_PLL:
-		data = &ddr3_pll_config;
+		data = &ddr3_pll_config[sysclk_index];
 		break;
 	default:
 		data = NULL;
@@ -102,7 +200,7 @@ s16 divn_val[16] = {
 	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 };
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	if (psc_enable_module(KS2_LPSC_MMC)) {
@@ -110,13 +208,47 @@ int board_mmc_init(bd_t *bis)
 		return -1;
 	}
 
-	omap_mmc_init(0, 0, 0, -1, -1);
+	if (board_is_k2g_gp())
+		omap_mmc_init(0, 0, 0, -1, -1);
+
 	omap_mmc_init(1, 0, 0, -1, -1);
 	return 0;
 }
 #endif
 
-#ifdef CONFIG_BOARD_EARLY_INIT_F
+#if defined(CONFIG_FIT_EMBED)
+int board_fit_config_name_match(const char *name)
+{
+	bool eeprom_read = board_ti_was_eeprom_read();
+
+	if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
+		return 0;
+	else if (!strcmp(name, "keystone-k2g-evm") && board_ti_is("66AK2GGP"))
+		return 0;
+	else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
+		return 0;
+	else
+		return -1;
+}
+#endif
+
+#if defined(CONFIG_DTB_RESELECT)
+static int k2g_alt_board_detect(void)
+{
+	int rc;
+
+	rc = i2c_set_bus_num(1);
+	if (rc)
+		return rc;
+
+	rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
+	if (rc)
+		return rc;
+
+	ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
+
+	return 0;
+}
 
 static void k2g_reset_mux_config(void)
 {
@@ -131,19 +263,67 @@ static void k2g_reset_mux_config(void)
 	setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
 }
 
-int board_early_init_f(void)
+int embedded_dtb_select(void)
 {
-	init_plls();
+	int rc;
+	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+			CONFIG_EEPROM_CHIP_ADDRESS);
+	if (rc) {
+		rc = k2g_alt_board_detect();
+		if (rc) {
+			printf("Unable to do board detection\n");
+			return -1;
+		}
+	}
+
+	fdtdec_setup();
 
 	k2g_mux_config();
 
 	k2g_reset_mux_config();
 
-	/* deassert FLASH_HOLD */
-	clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
-		     BIT(9));
-	setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
-		     BIT(9));
+	if (board_is_k2g_gp()) {
+		/* deassert FLASH_HOLD */
+		clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
+			     BIT(9));
+		setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
+			     BIT(9));
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
+	int rc;
+
+	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+			CONFIG_EEPROM_CHIP_ADDRESS);
+	if (rc)
+		printf("ti_i2c_eeprom_init failed %d\n", rc);
+
+	board_ti_set_ethaddr(1);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	if (board_is_k2g_gp())
+		setenv("board_name", "66AK2GGP\0");
+	else if (board_is_k2g_ice())
+		setenv("board_name", "66AK2GIC\0");
+#endif
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	init_plls();
+
+	k2g_mux_config();
 
 	return 0;
 }
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
index e217bea..c733099 100644
--- a/board/ti/ks2_evm/board_k2hk.c
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -23,6 +23,37 @@ unsigned int external_clk[ext_clk_count] = {
 	[ddr3b_clk]	=	100000000,
 };
 
+unsigned int get_external_clk(u32 clk)
+{
+	unsigned int clk_freq;
+
+	switch (clk) {
+	case sys_clk:
+		clk_freq = 122880000;
+		break;
+	case alt_core_clk:
+		clk_freq = 125000000;
+		break;
+	case pa_clk:
+		clk_freq = 122880000;
+		break;
+	case tetris_clk:
+		clk_freq = 125000000;
+		break;
+	case ddr3a_clk:
+		clk_freq = 100000000;
+		break;
+	case ddr3b_clk:
+		clk_freq = 100000000;
+		break;
+	default:
+		clk_freq = 0;
+		break;
+	}
+
+	return clk_freq;
+}
+
 static struct pll_init_data core_pll_config[NUM_SPDS] = {
 	[SPD800]	= CORE_PLL_799,
 	[SPD1000]	= CORE_PLL_999,
@@ -119,6 +150,16 @@ int board_early_init_f(void)
 }
 #endif
 
+#if defined(CONFIG_FIT_EMBED)
+int board_fit_config_name_match(const char *name)
+{
+	if (!strcmp(name, "keystone-k2hk-evm"))
+		return 0;
+
+	return -1;
+}
+#endif
+
 #ifdef CONFIG_SPL_BUILD
 void spl_init_keystone_plls(void)
 {
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
index 2a2e005..166367b 100644
--- a/board/ti/ks2_evm/board_k2l.c
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -14,13 +14,33 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-unsigned int external_clk[ext_clk_count] = {
-	[sys_clk]	= 122880000,
-	[alt_core_clk]	= 100000000,
-	[pa_clk]	= 122880000,
-	[tetris_clk]	= 122880000,
-	[ddr3a_clk]	= 100000000,
-};
+unsigned int get_external_clk(u32 clk)
+{
+	unsigned int clk_freq;
+
+	switch (clk) {
+	case sys_clk:
+		clk_freq = 122880000;
+		break;
+	case alt_core_clk:
+		clk_freq = 100000000;
+		break;
+	case pa_clk:
+		clk_freq = 122880000;
+		break;
+	case tetris_clk:
+		clk_freq = 122880000;
+		break;
+	case ddr3a_clk:
+		clk_freq = 100000000;
+		break;
+	default:
+		clk_freq = 0;
+		break;
+	}
+
+	return clk_freq;
+}
 
 static struct pll_init_data core_pll_config[NUM_SPDS] = {
 	[SPD800]	= CORE_PLL_799,
@@ -118,6 +138,16 @@ int board_early_init_f(void)
 }
 #endif
 
+#if defined(CONFIG_FIT_EMBED)
+int board_fit_config_name_match(const char *name)
+{
+	if (!strcmp(name, "keystone-k2l-evm"))
+		return 0;
+
+	return -1;
+}
+#endif
+
 #ifdef CONFIG_SPL_BUILD
 void spl_init_keystone_plls(void)
 {
diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c
index 344961d..44db335 100644
--- a/board/ti/ks2_evm/ddr3_k2g.c
+++ b/board/ti/ks2_evm/ddr3_k2g.c
@@ -10,7 +10,9 @@
 #include <common.h>
 #include "ddr3_cfg.h"
 #include <asm/arch/ddr3.h>
+#include "board.h"
 
+/* K2G GP EVM DDR3 Configuration */
 struct ddr3_phy_config ddr3phy_800_2g = {
 	.pllcr          = 0x000DC000ul,
 	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
@@ -27,13 +29,27 @@ struct ddr3_phy_config ddr3phy_800_2g = {
 	.dtpr2          = 0x50022A00ul,
 	.mr0            = 0x00001430ul,
 	.mr1            = 0x00000006ul,
-	.mr2            = 0x00000018ul,
+	.mr2            = 0x00000000ul,
 	.dtcr           = 0x710035C7ul,
 	.pgcr2          = 0x00F03D09ul,
 	.zq0cr1         = 0x0001005Dul,
 	.zq1cr1         = 0x0001005Bul,
 	.zq2cr1         = 0x0001005Bul,
 	.pir_v1         = 0x00000033ul,
+	.datx8_2_mask   = 0,
+	.datx8_2_val    = 0,
+	.datx8_3_mask   = 0,
+	.datx8_3_val    = 0,
+	.datx8_4_mask   = 0,
+	.datx8_4_val    = ((1 << 0)),
+	.datx8_5_mask   = DXEN_MASK,
+	.datx8_5_val    = 0,
+	.datx8_6_mask   = DXEN_MASK,
+	.datx8_6_val    = 0,
+	.datx8_7_mask   = DXEN_MASK,
+	.datx8_7_val    = 0,
+	.datx8_8_mask   = DXEN_MASK,
+	.datx8_8_val    = 0,
 	.pir_v2         = 0x00000F81ul,
 };
 
@@ -47,13 +63,69 @@ struct ddr3_emif_config ddr3_800_2g = {
 	.sdrfc          = 0x00000C34ul,
 };
 
+/* K2G ICE evm DDR3 Configuration */
+struct ddr3_phy_config ddr3phy_800_512mb = {
+	.pllcr          = 0x000DC000ul,
+	.pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
+	.pgcr1_val      = ((1 << 2) | (2 << 7) | (1 << 23)),
+	.ptr0           = 0x42C21590ul,
+	.ptr1           = 0xD05612C0ul,
+	.ptr2           = 0,
+	.ptr3           = 0x06C30D40ul,
+	.ptr4           = 0x06413880ul,
+	.dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+	.dcr_val        = ((1 << 10)),
+	.dtpr0          = 0x550E6644ul,
+	.dtpr1          = 0x32834200ul,
+	.dtpr2          = 0x50022A00ul,
+	.mr0            = 0x00001430ul,
+	.mr1            = 0x00000006ul,
+	.mr2            = 0x00000008ul,
+	.dtcr           = 0x710035C7ul,
+	.pgcr2          = 0x00F03D09ul,
+	.zq0cr1         = 0x0001005Dul,
+	.zq1cr1         = 0x0001005Bul,
+	.zq2cr1         = 0x0001005Bul,
+	.pir_v1         = 0x00000033ul,
+	.datx8_2_mask   = DXEN_MASK,
+	.datx8_2_val    = 0,
+	.datx8_3_mask   = DXEN_MASK,
+	.datx8_3_val    = 0,
+	.datx8_4_mask   = DXEN_MASK,
+	.datx8_4_val    = 0,
+	.datx8_5_mask   = DXEN_MASK,
+	.datx8_5_val    = 0,
+	.datx8_6_mask   = DXEN_MASK,
+	.datx8_6_val    = 0,
+	.datx8_7_mask   = DXEN_MASK,
+	.datx8_7_val    = 0,
+	.datx8_8_mask   = DXEN_MASK,
+	.datx8_8_val    = 0,
+	.pir_v2         = 0x00000F81ul,
+};
+
+struct ddr3_emif_config ddr3_800_512mb = {
+	.sdcfg          = 0x62006662ul,
+	.sdtim1         = 0x0A385033ul,
+	.sdtim2         = 0x00001CA5ul,
+	.sdtim3         = 0x21ADFF32ul,
+	.sdtim4         = 0x533F067Ful,
+	.zqcfg          = 0x70073200ul,
+	.sdrfc          = 0x00000C34ul,
+};
+
 u32 ddr3_init(void)
 {
 	/* Reset DDR3 PHY after PLL enabled */
 	ddr3_reset_ddrphy();
 
-	ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
-	ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
+	if (board_is_k2g_gp()) {
+		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
+		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
+	} else if (board_is_k2g_ice()) {
+		ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_512mb);
+		ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_512mb);
+	}
 
 	return 0;
 }
diff --git a/board/ti/ks2_evm/mux-k2g.h b/board/ti/ks2_evm/mux-k2g.h
index 773f9b7..630103d 100644
--- a/board/ti/ks2_evm/mux-k2g.h
+++ b/board/ti/ks2_evm/mux-k2g.h
@@ -11,6 +11,22 @@
 #include <asm/io.h>
 #include <asm/arch/mux-k2g.h>
 #include <asm/arch/hardware.h>
+#include "board.h"
+
+struct pin_cfg k2g_generic_pin_cfg[] = {
+	/* UART0 */
+	{ 115,  MODE(0) },	/* SOC_UART0_RXD */
+	{ 116,  MODE(0) },	/* SOC_UART0_TXD */
+
+	/* I2C 0 */
+	{ 223,  MODE(0) },	/* SOC_I2C0_SCL */
+	{ 224,  MODE(0) },	/* SOC_I2C0_SDA */
+
+	/* I2C 1 */
+	{ 225,  MODE(0) },	/* SOC_I2C1_SCL */
+	{ 226,  MODE(0) },	/* SOC_I2C1_SDA */
+	{ MAX_PIN_N, }
+};
 
 struct pin_cfg k2g_evm_pin_cfg[] = {
 	/* GPMC */
@@ -307,7 +323,34 @@ struct pin_cfg k2g_evm_pin_cfg[] = {
 	{ MAX_PIN_N, }
 };
 
+struct pin_cfg k2g_ice_evm_pin_cfg[] = {
+	/* MMC 1 */
+	{ 63, MODE(0) | PIN_PTD },	/* MMC1_DAT3.MMC1_DAT3 */
+	{ 64, MODE(0) | PIN_PTU },	/* MMC1_DAT2.MMC1_DAT2 */
+	{ 65, MODE(0) | PIN_PTU },	/* MMC1_DAT1.MMC1_DAT1 */
+	{ 66, MODE(0) | PIN_PTD },	/* MMC1_DAT0.MMC1_DAT0 */
+	{ 67, MODE(0) | PIN_PTD },	/* MMC1_CLK.MMC1_CLK   */
+	{ 68, MODE(0) | PIN_PTD },	/* MMC1_CMD.MMC1_CMD   */
+	{ 69, MODE(3) | PIN_PTU },	/* MMC1_SDCD.GPIO0_69  */
+	{ 70, MODE(0) | PIN_PTU },	/* MMC1_SDWP.MMC1_SDWP */
+	{ 71, MODE(0) | PIN_PTD },	/* MMC1_POW.MMC1_POW   */
+
+	/* I2C 0 */
+	{ 223,  MODE(0) },		/* SOC_I2C0_SCL */
+	{ 224,  MODE(0) },		/* SOC_I2C0_SDA */
+	{ MAX_PIN_N, }
+};
+
 void k2g_mux_config(void)
 {
-	configure_pin_mux(k2g_evm_pin_cfg);
+	if (!board_ti_was_eeprom_read()) {
+		configure_pin_mux(k2g_generic_pin_cfg);
+	} else if (board_is_k2g_gp()) {
+		configure_pin_mux(k2g_evm_pin_cfg);
+	} else if (board_is_k2g_ice()) {
+		configure_pin_mux(k2g_ice_evm_pin_cfg);
+	} else {
+		puts("Unknown board, cannot configure pinmux.");
+		hang();
+	}
 }
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index 50da410..4b25cc2 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -20,10 +20,11 @@
 
 #include "mux_data.h"
 
-#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
+#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
 #include <sata.h>
 #include <usb.h>
 #include <asm/gpio.h>
+#include <asm/mach-types.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/ehci.h>
 #include <asm/ehci-omap.h>
@@ -151,7 +152,7 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
-#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP)
+#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
 static void enable_host_clocks(void)
 {
 	int auxclk;
@@ -211,7 +212,7 @@ void set_muxconf_regs(void)
 		   sizeof(struct pad_conf_entry));
 }
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	omap_mmc_init(0, 0, 0, -1, -1);
@@ -220,7 +221,7 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
 static struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
 	.port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
@@ -245,10 +246,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
 int ehci_hcd_stop(void)
 {
-	int ret;
-
-	ret = omap_ehci_hcd_stop();
-	return ret;
+	return omap_ehci_hcd_stop();
 }
 
 void usb_hub_reset_devices(int port)
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 13b5daf..6ffb53c 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -6,6 +6,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <asm/mach-types.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/clock.h>
@@ -15,7 +16,7 @@
 
 #include "panda_mux_data.h"
 
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
 #include <usb.h>
 #include <asm/arch/ehci.h>
 #include <asm/ehci-omap.h>
@@ -287,19 +288,21 @@ void set_muxconf_regs(void)
 			   sizeof(struct pad_conf_entry));
 }
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
 }
 
+#if !defined(CONFIG_SPL_BUILD)
 void board_mmc_power_init(void)
 {
 	twl6030_power_mmc_init(0);
 }
 #endif
+#endif
 
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
 
 static struct omap_usbhs_board_data usbhs_bdata = {
 	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
diff --git a/board/ti/sdp4430/Kconfig b/board/ti/sdp4430/Kconfig
index 5826d8f..36f1852 100644
--- a/board/ti/sdp4430/Kconfig
+++ b/board/ti/sdp4430/Kconfig
@@ -9,4 +9,7 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "omap4_sdp4430"
 
+config CMD_BAT
+	bool "Enable board-specific battery command"
+
 endif
diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index 6037cdd..bc8d32f 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -73,7 +73,7 @@ void set_muxconf_regs(void)
 				 sizeof(struct pad_conf_entry));
 }
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	omap_mmc_init(0, 0, 0, -1, -1);
@@ -81,12 +81,14 @@ int board_mmc_init(bd_t *bis)
 	return 0;
 }
 
+#if !defined(CONFIG_SPL_BUILD)
 void board_mmc_power_init(void)
 {
 	twl6030_power_mmc_init(0);
 	twl6030_power_mmc_init(1);
 }
 #endif
+#endif
 
 /*
  * get_board_rev() - get board revision
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index e406dab..055a29d 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -111,7 +111,7 @@ int board_init(void)
 	return 0;
 }
 
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	omap_mmc_init(1, 0, 0, -1, -1);
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
index b6bf162..9d6c3d6 100644
--- a/board/ti/ti816x/evm.c
+++ b/board/ti/ti816x/evm.c
@@ -9,6 +9,7 @@
 
 #include <common.h>
 #include <spl.h>
+#include <netdev.h>
 #include <asm/cache.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -24,12 +25,41 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
-	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_NAND)
+	gpmc_init();
+#endif
 	return 0;
 }
 
-#ifdef CONFIG_SPL_BUILD
+int board_eth_init(bd_t *bis)
+{
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+		printf("<ethaddr> not set. Reading from E-fuse\n");
+		/* try reading mac address from efuse */
+		mac_lo = readl(&cdev->macid0l);
+		mac_hi = readl(&cdev->macid0h);
+		mac_addr[0] = mac_hi & 0xFF;
+		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+		mac_addr[4] = mac_lo & 0xFF;
+		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+		if (is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+		else
+			printf("Unable to read MAC address. Set <ethaddr>\n");
+	}
+
+	return davinci_emac_initialize();
+}
 
+#ifdef CONFIG_SPL_BUILD
 static struct module_pin_mux mmc_pin_mux[] = {
 	{ OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
 	{ OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
@@ -41,176 +71,68 @@ static struct module_pin_mux mmc_pin_mux[] = {
 	{ -1 },
 };
 
-const struct dmm_lisa_map_regs evm_lisa_map_regs = {
-	.dmm_lisa_map_0 = 0x00000000,
-	.dmm_lisa_map_1 = 0x00000000,
-	.dmm_lisa_map_2 = 0x80640300,
-	.dmm_lisa_map_3 = 0xC0640320,
-};
-
-/*
- * DDR2 related definitions
- */
-#ifdef CONFIG_TI816X_EVM_DDR2
-static struct ddr_data ddr2_data = {
-	.datardsratio0		= ((0x40<<10) | (0x40<<0)),
-	.datawdsratio0		= ((0x4A<<10) | (0x4A<<0)),
-	.datawiratio0		= ((0x0<<10) | (0x0<<0)),
-	.datagiratio0		= ((0x0<<10) | (0x0<<0)),
-	.datafwsratio0		= ((0x13A<<10) | (0x13A<<0)),
-	.datawrsratio0		= ((0x8A<<10) | (0x8A<<0)),
-};
-
-static struct cmd_control ddr2_ctrl = {
-	.cmd0csratio	= 0x80,
-	.cmd0iclkout	= 0x00,
-
-	.cmd1csratio	= 0x80,
-	.cmd1iclkout	= 0x00,
-
-	.cmd2csratio	= 0x80,
-	.cmd2iclkout	= 0x00,
-
-};
-
-static struct emif_regs ddr2_emif0_regs = {
-	.sdram_config		= 0x43801A3A,
-	.ref_ctrl		= 0x10000C30,
-	.sdram_tim1		= 0x0AAB15E2,
-	.sdram_tim2		= 0x423631D2,
-	.sdram_tim3		= 0x0080032F,
-	.emif_ddr_phy_ctlr_1	= 0x0, /* depend on cpu rev, set later */
-};
+void set_uart_mux_conf(void) {}
 
-static struct emif_regs ddr2_emif1_regs = {
-	.sdram_config		= 0x43801A3A,
-	.ref_ctrl		= 0x10000C30,
-	.sdram_tim1		= 0x0AAB15E2,
-	.sdram_tim2		= 0x423631D2,
-	.sdram_tim3		= 0x0080032F,
-	.emif_ddr_phy_ctlr_1	= 0x0, /* depend on cpu rev, set later */
-};
-#endif
+void set_mux_conf_regs(void)
+{
+	configure_module_pin_mux(mmc_pin_mux);
+}
 
 /*
- * DDR3 related definitions
+ * EMIF Paramters.  Refer the EMIF register documentation and the
+ * memory datasheet for details.  This is for 796 MHz.
  */
-
-#if defined(CONFIG_TI816X_DDR_PLL_400)
-#define RD_DQS		0x03B
-#define WR_DQS		0x0A6
-#define RD_DQS_GATE	0x12A
-#define EMIF_SDCFG	0x62A41032
-#define EMIF_SDREF	0x10000C30
-#define EMIF_TIM1	0x0CCCE524
-#define EMIF_TIM2	0x30308023
-#define EMIF_TIM3	0x009F82CF
-#define EMIF_PHYCFG	0x0000010B
-#elif defined(CONFIG_TI816X_DDR_PLL_531)
-#define RD_DQS		0x039
-#define WR_DQS		0x0B4
-#define RD_DQS_GATE	0x13D
-#define EMIF_SDCFG	0x62A51832
-#define EMIF_SDREF	0x1000102E
-#define EMIF_TIM1	0x0EF136AC
-#define EMIF_TIM2	0x30408063
-#define EMIF_TIM3	0x009F83AF
-#define EMIF_PHYCFG	0x0000010C
-#elif defined(CONFIG_TI816X_DDR_PLL_675)
-#define RD_DQS		0x039
-#define WR_DQS		0x091
-#define RD_DQS_GATE	0x196
-#define EMIF_SDCFG	0x62A63032
-#define EMIF_SDREF	0x10001491
-#define EMIF_TIM1	0x13358875
-#define EMIF_TIM2	0x5051806C
-#define EMIF_TIM3	0x009F84AF
-#define EMIF_PHYCFG	0x0000010F
-#elif defined(CONFIG_TI816X_DDR_PLL_796)
-#define RD_DQS		0x035
-#define WR_DQS		0x093
-#define RD_DQS_GATE	0x1B3
-#define EMIF_SDCFG	0x62A73832
-#define EMIF_SDREF	0x10001841
-#define EMIF_TIM1	0x1779C9FE
-#define EMIF_TIM2	0x50608074
-#define EMIF_TIM3	0x009F857F
-#define EMIF_PHYCFG	0x00000110
-#endif
-
-static struct ddr_data ddr3_data = {
-	.datardsratio0		= ((RD_DQS<<10) | (RD_DQS<<0)),
-	.datawdsratio0		= ((WR_DQS<<10) | (WR_DQS<<0)),
-	.datawiratio0		= ((0x20<<10) | 0x20<<0),
-	.datagiratio0		= ((0x20<<10) | 0x20<<0),
-	.datafwsratio0		= ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
-	.datawrsratio0		= (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
+#define EMIF_TIM1   0x1779C9FE
+#define EMIF_TIM2   0x50608074
+#define EMIF_TIM3   0x009F857F
+#define EMIF_SDREF  0x10001841
+#define EMIF_SDCFG  0x62A73832
+#define EMIF_PHYCFG 0x00000110
+static const struct emif_regs ddr3_emif_regs = {
+	.sdram_config		= EMIF_SDCFG,
+	.ref_ctrl		= EMIF_SDREF,
+	.sdram_tim1		= EMIF_TIM1,
+	.sdram_tim2		= EMIF_TIM2,
+	.sdram_tim3		= EMIF_TIM3,
+	.emif_ddr_phy_ctlr_1	= EMIF_PHYCFG,
 };
 
 static const struct cmd_control ddr3_ctrl = {
 	.cmd0csratio	= 0x100,
 	.cmd0iclkout	= 0x001,
-
 	.cmd1csratio	= 0x100,
 	.cmd1iclkout	= 0x001,
-
 	.cmd2csratio	= 0x100,
 	.cmd2iclkout	= 0x001,
 };
 
-static const struct emif_regs ddr3_emif0_regs = {
-	.sdram_config		= EMIF_SDCFG,
-	.ref_ctrl		= EMIF_SDREF,
-	.sdram_tim1		= EMIF_TIM1,
-	.sdram_tim2		= EMIF_TIM2,
-	.sdram_tim3		= EMIF_TIM3,
-	.emif_ddr_phy_ctlr_1	= EMIF_PHYCFG,
+/* These values are obtained from the CCS app */
+#define RD_DQS_GATE	(0x1B3)
+#define RD_DQS		(0x35)
+#define WR_DQS		(0x93)
+static struct ddr_data ddr3_data = {
+	.datardsratio0		= ((RD_DQS<<10) | (RD_DQS<<0)),
+	.datawdsratio0		= ((WR_DQS<<10) | (WR_DQS<<0)),
+	.datawiratio0		= ((0x20<<10) | 0x20<<0),
+	.datagiratio0		= ((0x20<<10) | 0x20<<0),
+	.datafwsratio0		= ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
+	.datawrsratio0		= (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
 };
 
-static const struct emif_regs ddr3_emif1_regs = {
-	.sdram_config		= EMIF_SDCFG,
-	.ref_ctrl		= EMIF_SDREF,
-	.sdram_tim1		= EMIF_TIM1,
-	.sdram_tim2		= EMIF_TIM2,
-	.sdram_tim3		= EMIF_TIM3,
-	.emif_ddr_phy_ctlr_1	= EMIF_PHYCFG,
+static const struct dmm_lisa_map_regs evm_lisa_map_regs = {
+	.dmm_lisa_map_0 = 0x00000000,
+	.dmm_lisa_map_1 = 0x00000000,
+	.dmm_lisa_map_2 = 0x80640300,
+	.dmm_lisa_map_3 = 0xC0640320,
 };
 
-void set_uart_mux_conf(void) {}
-
-void set_mux_conf_regs(void)
-{
-	configure_module_pin_mux(mmc_pin_mux);
-}
-
 void sdram_init(void)
 {
-	config_dmm(&evm_lisa_map_regs);
-
-#ifdef CONFIG_TI816X_EVM_DDR2
-	if (CONFIG_TI816X_USE_EMIF0) {
-		ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
-			(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
-		config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs,
-			   0);
-	}
-
-	if (CONFIG_TI816X_USE_EMIF1) {
-		ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
-			(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
-		config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs,
-			   1);
-	}
-#endif
-
-#ifdef CONFIG_TI816X_EVM_DDR3
-	if (CONFIG_TI816X_USE_EMIF0)
-		config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs,
-			   0);
-
-	if (CONFIG_TI816X_USE_EMIF1)
-		config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs,
-			   1);
-#endif
+	/*
+	 * Pass in our DDR3 config information and that we have 2 EMIFs to
+	 * configure.
+	 */
+	config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs,
+			&evm_lisa_map_regs, 2);
 }
 #endif /* CONFIG_SPL_BUILD */
diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
index 965252f..d31eeb8 100644
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -48,7 +48,8 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = {
 static const struct ns16550_platdata devkit8000_serial = {
 	.base = OMAP34XX_UART3,
 	.reg_shift = 2,
-	.clock = V_NS16550_CLK
+	.clock = V_NS16550_CLK,
+	.fcr = UART_FCR_DEFVAL,
 };
 
 U_BOOT_DEVICE(devkit8000_uart) = {
@@ -130,14 +131,14 @@ void set_muxconf_regs(void)
 	MUX_DEVKIT8000();
 }
 
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_MMC)
 int board_mmc_init(bd_t *bis)
 {
 	return omap_mmc_init(0, 0, 0, -1, -1);
 }
 #endif
 
-#if defined(CONFIG_GENERIC_MMC)
+#if defined(CONFIG_MMC)
 void board_mmc_power_init(void)
 {
 	twl4030_power_mmc_init(0);
@@ -157,7 +158,7 @@ int board_eth_init(bd_t *bis)
 
 #ifdef CONFIG_SPL_OS_BOOT
 /*
- * Do board specific preperation before SPL
+ * Do board specific preparation before SPL
  * Linux boot
  */
 void spl_board_prepare_for_linux(void)
diff --git a/board/topic/zynq/MAINTAINERS b/board/topic/zynq/MAINTAINERS
new file mode 100644
index 0000000..d795b30
--- /dev/null
+++ b/board/topic/zynq/MAINTAINERS
@@ -0,0 +1,6 @@
+TOPIC BOARD
+M:	Mike Looijmans <mike.looijmans@topic.nl>
+S:	Maintained
+F:	board/topic/zynq/
+F:	include/configs/topic*.h
+F:	configs/topic_*_defconfig
diff --git a/board/topic/zynq/Makefile b/board/topic/zynq/Makefile
new file mode 100644
index 0000000..eaf59cd
--- /dev/null
+++ b/board/topic/zynq/Makefile
@@ -0,0 +1,10 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= board.o
+
+# Remove quotes
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
+
+obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o ps7_init_common.o
diff --git a/board/topic/zynq/board.c b/board/topic/zynq/board.c
new file mode 100644
index 0000000..a95c9d1
--- /dev/null
+++ b/board/topic/zynq/board.c
@@ -0,0 +1 @@
+#include "../../xilinx/zynq/board.c"
diff --git a/board/topic/zynq/ps7_init_common.c b/board/topic/zynq/ps7_init_common.c
new file mode 100644
index 0000000..b1d45c2
--- /dev/null
+++ b/board/topic/zynq/ps7_init_common.c
@@ -0,0 +1,117 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "ps7_init_gpl.h"
+#include <asm/io.h>
+
+/* For delay calculation using global registers*/
+#define SCU_GLOBAL_TIMER_COUNT_L32	0xF8F00200
+#define SCU_GLOBAL_TIMER_COUNT_U32	0xF8F00204
+#define SCU_GLOBAL_TIMER_CONTROL	0xF8F00208
+#define SCU_GLOBAL_TIMER_AUTO_INC	0xF8F00218
+#define APU_FREQ  666666666
+
+#define PS7_MASK_POLL_TIME 100000000
+
+/* IO accessors. No memory barriers desired. */
+static inline void iowrite(unsigned long val, unsigned long addr)
+{
+	__raw_writel(val, addr);
+}
+
+static inline unsigned long ioread(unsigned long addr)
+{
+	return __raw_readl(addr);
+}
+
+/* start timer */
+static void perf_start_clock(void)
+{
+	iowrite((1 << 0) | /* Timer Enable */
+		(1 << 3) | /* Auto-increment */
+		(0 << 8), /* Pre-scale */
+		SCU_GLOBAL_TIMER_CONTROL);
+}
+
+/* Compute mask for given delay in miliseconds*/
+static int get_number_of_cycles_for_delay(unsigned int delay)
+{
+	return (APU_FREQ / (2 * 1000)) * delay;
+}
+
+/* stop timer */
+static void perf_disable_clock(void)
+{
+	iowrite(0, SCU_GLOBAL_TIMER_CONTROL);
+}
+
+/* stop timer and reset timer count regs */
+static void perf_reset_clock(void)
+{
+	perf_disable_clock();
+	iowrite(0, SCU_GLOBAL_TIMER_COUNT_L32);
+	iowrite(0, SCU_GLOBAL_TIMER_COUNT_U32);
+}
+
+static void perf_reset_and_start_timer(void)
+{
+	perf_reset_clock();
+	perf_start_clock();
+}
+
+int ps7_config(unsigned long *ps7_config_init)
+{
+	unsigned long *ptr = ps7_config_init;
+	unsigned long opcode;
+	unsigned long addr;
+	unsigned long val;
+	unsigned long mask;
+	unsigned int numargs;
+	int i;
+	int delay;
+
+	for (;;) {
+		opcode = ptr[0];
+		if (opcode == OPCODE_EXIT)
+			return PS7_INIT_SUCCESS;
+		addr = (opcode & OPCODE_ADDRESS_MASK);
+
+		switch (opcode & ~OPCODE_ADDRESS_MASK) {
+		case OPCODE_MASKWRITE:
+			numargs = 3;
+			mask = ptr[1];
+			val = ptr[2];
+			iowrite((ioread(addr) & ~mask) | (val & mask), addr);
+			break;
+
+		case OPCODE_MASKPOLL:
+			numargs = 2;
+			mask = ptr[1];
+			i = 0;
+			while (!(ioread(addr) & mask)) {
+				if (i == PS7_MASK_POLL_TIME)
+					return PS7_INIT_TIMEOUT;
+				i++;
+			}
+			break;
+
+		case OPCODE_MASKDELAY:
+			numargs = 2;
+			mask = ptr[1];
+			delay = get_number_of_cycles_for_delay(mask);
+			perf_reset_and_start_timer();
+			while (ioread(addr) < delay)
+				;
+			break;
+
+		default:
+			return PS7_INIT_CORRUPT;
+		}
+
+		ptr += numargs;
+	}
+}
diff --git a/board/topic/zynq/ps7_init_gpl.h b/board/topic/zynq/ps7_init_gpl.h
new file mode 100644
index 0000000..ef719ac
--- /dev/null
+++ b/board/topic/zynq/ps7_init_gpl.h
@@ -0,0 +1,34 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define OPCODE_EXIT       0U
+#define OPCODE_MASKWRITE  0U
+#define OPCODE_MASKPOLL   1U
+#define OPCODE_MASKDELAY  2U
+#define OPCODE_ADDRESS_MASK (~3U)
+
+/* Sentinel */
+#define EMIT_EXIT()                     OPCODE_EXIT
+/* Opcode is in lower 2 bits of address, address is always 4-byte aligned */
+#define EMIT_MASKWRITE(addr, mask, val) OPCODE_MASKWRITE | addr, mask, val
+#define EMIT_MASKPOLL(addr, mask)       OPCODE_MASKPOLL | addr, mask
+#define EMIT_MASKDELAY(addr, mask)      OPCODE_MASKDELAY | addr, mask
+
+/* Returns codes of ps7_init* */
+#define PS7_INIT_SUCCESS   (0)
+#define PS7_INIT_CORRUPT   (1)
+#define PS7_INIT_TIMEOUT   (2)
+#define PS7_POLL_FAILED_DDR_INIT (3)
+#define PS7_POLL_FAILED_DMA      (4)
+#define PS7_POLL_FAILED_PLL      (5)
+
+/* Called by spl.c */
+int ps7_init(void);
+int ps7_post_config(void);
+
+/* Defined in ps7_init_common.c */
+int ps7_config(unsigned long *ps7_config_init);
diff --git a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
new file mode 100644
index 0000000..b195d7a
--- /dev/null
+++ b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c
@@ -0,0 +1,227 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "../ps7_init_gpl.h"
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x00113220U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00024000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100141U),
+	EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00100141U),
+	EMIT_MASKWRITE(0XF8000148, 0x00003F31U, 0x00000C01U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000601U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001803U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000C03U),
+	EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U),
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U),
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U),
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FC4C4DU),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00025010U),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00026400U),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00029418U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00027820U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000090U),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000098U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x000000A0U),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E9U),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000EEU),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000FAU),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000F3U),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000D0U),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000D8U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000E0U),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000E60U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
diff --git a/board/topic/zynq/zynq-topic-miami/ps7_regs.txt b/board/topic/zynq/zynq-topic-miami/ps7_regs.txt
new file mode 100644
index 0000000..2ad9da6
--- /dev/null
+++ b/board/topic/zynq/zynq-topic-miami/ps7_regs.txt
@@ -0,0 +1,61 @@
+0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?)
+0xf8000700 0x1210     // MIO configuration
+0xf8000704 0x202
+0xf8000708 0x202
+0xf800070c 0x202
+0xf8000710 0x202
+0xf8000714 0x202
+0xf8000718 0x202
+0xf800071c 0x210
+0xf8000720 0x202
+0xf8000724 0x1210
+0xf8000728 0x1210
+0xf800072c 0x1210
+0xf8000730 0x1210
+0xf8000734 0x1210
+0xf8000738 0x1211
+0xf800073c 0x1200
+0xf8000740 0x1210
+0xf8000744 0x1210
+0xf8000748 0x1210
+0xf800074c 0x1210
+0xf8000750 0x1210
+0xf8000754 0x1210
+0xf8000758 0x1210
+0xf800075c 0x1210
+0xf8000760 0x1201
+0xf8000764 0x200
+0xf8000768 0x12e1
+0xf800076c 0x2e0
+0xf8000770 0x304
+0xf8000774 0x305
+0xf8000778 0x304
+0xf800077c 0x305
+0xf8000780 0x304
+0xf8000784 0x304
+0xf8000788 0x304
+0xf800078c 0x304
+0xf8000790 0x305
+0xf8000794 0x304
+0xf8000798 0x304
+0xf800079c 0x304
+0xf80007a0 0x380
+0xf80007a4 0x380
+0xf80007a8 0x380
+0xf80007ac 0x380
+0xf80007b0 0x380
+0xf80007b4 0x380
+0xf80007b8 0x1261
+0xf80007bc 0x1260
+0xf80007c0 0x1261
+0xf80007c4 0x1261
+0xf80007c8 0x1240
+0xf80007cc 0x1240
+0xf80007d0 0x1240
+0xf80007d4 0x1240
+0xf8000830 0x180037
+0xf8000834 0x3a0039
+0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 (200 MHz)
+0xE000D000 0x800238C1 // QSPI config - divide-by-2
+0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay
+0xE000D0A0 0x82FF04EB // LQSPI_CFG - QIOREAD mode, Numonyx/Micron
diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
new file mode 100644
index 0000000..ec0cc7d
--- /dev/null
+++ b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c
@@ -0,0 +1,227 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "../ps7_init_gpl.h"
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x00113220U),
+	EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x00024000U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0xF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00302301U),
+	EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0xF800013C, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100141U),
+	EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100141U),
+	EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000C01U),
+	EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000601U),
+	EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001803U),
+	EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000C03U),
+	EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000601U),
+	EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00100C00U),
+	EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00100C00U),
+	EMIT_MASKWRITE(0xF8000190, 0x03F03F30U, 0x00100600U),
+	EMIT_MASKWRITE(0xF80001A0, 0x03F03F30U, 0x00101800U),
+	EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FC4C4DU),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004281AU),
+	EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+	EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003482CU),
+	EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00033032U),
+	EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0002E81FU),
+	EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x0002F81AU),
+	EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ACU),
+	EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B2U),
+	EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009FU),
+	EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009AU),
+	EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000127U),
+	EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000121U),
+	EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000010FU),
+	EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000113U),
+	EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000ECU),
+	EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F2U),
+	EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DFU),
+	EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DAU),
+	EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x1002E080U),
+	EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0xF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000E60U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0xE000D000, 0x000800FFU, 0x000800C1U),
+	EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_MASKDELAY(0xF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt b/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt
new file mode 100644
index 0000000..db6e642
--- /dev/null
+++ b/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt
@@ -0,0 +1,61 @@
+0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?)
+0xf8000700 0x202
+0xf8000704 0x202
+0xf8000708 0x202
+0xf800070c 0x202
+0xf8000710 0x202
+0xf8000714 0x202
+0xf8000718 0x202
+0xf800071c 0x200
+0xf8000720 0x202
+0xf8000724 0x202
+0xf8000728 0x202
+0xf800072c 0x202
+0xf8000730 0x202
+0xf8000734 0x202
+0xf8000738 0x12e1
+0xf800073c 0x12e0
+0xf8000740 0x1200
+0xf8000744 0x1200
+0xf8000748 0x1200
+0xf800074c 0x1200
+0xf8000750 0x1200
+0xf8000754 0x1200
+0xf8000758 0x1200
+0xf800075c 0x1200
+0xf8000760 0x1200
+0xf8000764 0x200
+0xf8000768 0x1200
+0xf800076c 0x200
+0xf8000770 0x304
+0xf8000774 0x305
+0xf8000778 0x304
+0xf800077c 0x305
+0xf8000780 0x304
+0xf8000784 0x304
+0xf8000788 0x304
+0xf800078c 0x304
+0xf8000790 0x305
+0xf8000794 0x304
+0xf8000798 0x304
+0xf800079c 0x304
+0xf80007a0 0x380
+0xf80007a4 0x380
+0xf80007a8 0x380
+0xf80007ac 0x380
+0xf80007b0 0x380
+0xf80007b4 0x380
+0xf80007b8 0x1200
+0xf80007bc 0x1200
+0xf80007c0 0x1240
+0xf80007c4 0x1240
+0xf80007c8 0x1240
+0xf80007cc 0x1240
+0xf80007d0 0x1200
+0xf80007d4 0x1200
+0xf8000830 0x380037
+0xf8000834 0x3a0039
+0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 (200 MHz)
+0xE000D000 0x800238C1 // QSPI config - divide-by-2
+0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay
+0xE000D0A0 0xE2FF06EB // LQSPI_CFG - Quad read, dual flash
diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
new file mode 100644
index 0000000..5a92336
--- /dev/null
+++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c
@@ -0,0 +1,233 @@
+/*
+ * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
+ * (c) Copyright 2016 Topic Embedded Products.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "../ps7_init_gpl.h"
+
+static unsigned long ps7_pll_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x000FA220U),
+	EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x00028000U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
+	EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x0012C220U),
+	EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000002U),
+	EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
+	EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x00113220U),
+	EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00024000U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
+	EMIT_MASKPOLL(0XF800010C, 0x00000004U),
+	EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_clock_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
+	EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
+	EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100141U),
+	EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00100141U),
+	EMIT_MASKWRITE(0XF8000148, 0x00003F31U, 0x00000C01U),
+	EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000601U),
+	EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001803U),
+	EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000C03U),
+	EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U),
+	EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U),
+	EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U),
+	EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U),
+	EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U),
+	EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U),
+	EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FC4C4DU),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_ddr_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
+	EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
+	EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
+	EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
+	EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
+	EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E458D2U),
+	EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
+	EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
+	EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
+	EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
+	EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
+	EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
+	EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
+	EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
+	EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
+	EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
+	EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
+	EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
+	EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
+	EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
+	EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
+	EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
+	EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
+	EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
+	EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
+	EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
+	EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
+	EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
+	EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
+	EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
+	EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
+	EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
+	EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00025010U),
+	EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00026400U),
+	EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00029418U),
+	EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00027820U),
+	EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
+	EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000090U),
+	EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x00000080U),
+	EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000098U),
+	EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x000000A0U),
+	EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E9U),
+	EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000EEU),
+	EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000FAU),
+	EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000F3U),
+	EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000D0U),
+	EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000C0U),
+	EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000D8U),
+	EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000E0U),
+	EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
+	EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
+	EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
+	EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
+	EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
+	EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
+	EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
+	EMIT_MASKPOLL(0XF8006054, 0x00000007U),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_mio_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
+	EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
+	EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
+	EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
+	EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000E60U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
+	EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
+	EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_peripherals_init_data_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
+	EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
+	EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
+	EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
+	EMIT_MASKWRITE(0XE000D000, 0x000800FFU, 0x000800C1U),
+	EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_MASKDELAY(0XF8F00200, 1),
+	EMIT_EXIT(),
+};
+
+static unsigned long ps7_post_config_3_0[] = {
+	EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
+	EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
+	EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
+	EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
+	EMIT_EXIT(),
+};
+
+int ps7_init(void)
+{
+	int ret;
+
+	ret = ps7_config(ps7_mio_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_pll_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_clock_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_ddr_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+	ret = ps7_config(ps7_peripherals_init_data_3_0);
+	if (ret != PS7_INIT_SUCCESS)
+		return ret;
+
+	return PS7_INIT_SUCCESS;
+}
+
+int ps7_post_config(void)
+{
+	return ps7_config(ps7_post_config_3_0);
+}
diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt b/board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt
new file mode 100644
index 0000000..7b102de
--- /dev/null
+++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt
@@ -0,0 +1,61 @@
+0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 (433 MHz)
+0xf8000700 0x1202     // MIO configuration
+0xf8000704 0x1202
+0xf8000708 0x202
+0xf800070c 0x202
+0xf8000710 0x202
+0xf8000714 0x202
+0xf8000718 0x202
+0xf800071c 0x200
+0xf8000720 0x202
+0xf8000724 0x202
+0xf8000728 0x202
+0xf800072c 0x202
+0xf8000730 0x202
+0xf8000734 0x202
+0xf8000738 0x12e1
+0xf800073c 0x12e0
+0xf8000740 0x1202
+0xf8000744 0x1202
+0xf8000748 0x1202
+0xf800074c 0x1202
+0xf8000750 0x1202
+0xf8000754 0x1202
+0xf8000758 0x1203
+0xf800075c 0x1203
+0xf8000760 0x1203
+0xf8000764 0x203
+0xf8000768 0x1203
+0xf800076c 0x203
+0xf8000770 0x304
+0xf8000774 0x305
+0xf8000778 0x304
+0xf800077c 0x305
+0xf8000780 0x304
+0xf8000784 0x304
+0xf8000788 0x304
+0xf800078c 0x304
+0xf8000790 0x305
+0xf8000794 0x304
+0xf8000798 0x304
+0xf800079c 0x304
+0xf80007a0 0x380
+0xf80007a4 0x380
+0xf80007a8 0x380
+0xf80007ac 0x380
+0xf80007b0 0x380
+0xf80007b4 0x380
+0xf80007b8 0x1200
+0xf80007bc 0x1201
+0xf80007c0 0x1240
+0xf80007c4 0x1240
+0xf80007c8 0x1240
+0xf80007cc 0x1240
+0xf80007d0 0x1280
+0xf80007d4 0x1280
+0xf8000830 0x2f0037
+0xf8000834 0x3a0039
+0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6
+0xE000D000 0x800238C1 // QSPI config - divide-by-2
+0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay
+0xE000D0A0 0xE2FF06EB // LQSPI_CFG - Quad read, dual flash
diff --git a/board/toradex/apalis-tk1/Kconfig b/board/toradex/apalis-tk1/Kconfig
new file mode 100644
index 0000000..05407ad
--- /dev/null
+++ b/board/toradex/apalis-tk1/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_APALIS_TK1
+
+config SYS_BOARD
+	default "apalis-tk1"
+
+config SYS_VENDOR
+	default "toradex"
+
+config SYS_CONFIG_NAME
+	default "apalis-tk1"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/board/toradex/apalis-tk1/MAINTAINERS b/board/toradex/apalis-tk1/MAINTAINERS
new file mode 100644
index 0000000..3c908e1
--- /dev/null
+++ b/board/toradex/apalis-tk1/MAINTAINERS
@@ -0,0 +1,7 @@
+Apalis TK1
+M:	Marcel Ziswiler <marcel.ziswiler@toradex.com>
+S:	Maintained
+F:	board/toradex/apalis-tk1/
+F:	include/configs/apalis-tk1.h
+F:	configs/apalis-tk1_defconfig
+F:	arch/arm/dts/tegra124-apalis.dtb
diff --git a/board/toradex/apalis-tk1/Makefile b/board/toradex/apalis-tk1/Makefile
new file mode 100644
index 0000000..9ef06dd
--- /dev/null
+++ b/board/toradex/apalis-tk1/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2016 Toradex, Inc.
+# SPDX-License-Identifier:      GPL-2.0+
+
+obj-y	+= as3722_init.o
+obj-y	+= apalis-tk1.o
diff --git a/board/toradex/apalis-tk1/apalis-tk1.c b/board/toradex/apalis-tk1/apalis-tk1.c
new file mode 100644
index 0000000..5de61e7
--- /dev/null
+++ b/board/toradex/apalis-tk1/apalis-tk1.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <power/as3722.h>
+
+#include "../common/tdx-common.h"
+#include "pinmux-config-apalis-tk1.h"
+
+#define LAN_RESET_N TEGRA_GPIO(S, 2)
+
+int arch_misc_init(void)
+{
+	if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
+	    NVBOOTTYPE_RECOVERY)
+		printf("USB recovery mode\n");
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Model: Toradex Apalis TK1 2GB\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+	pinmux_clear_tristate_input_clamping();
+
+	gpio_config_table(apalis_tk1_gpio_inits,
+			  ARRAY_SIZE(apalis_tk1_gpio_inits));
+
+	pinmux_config_pingrp_table(apalis_tk1_pingrps,
+				   ARRAY_SIZE(apalis_tk1_pingrps));
+
+	pinmux_config_drvgrp_table(apalis_tk1_drvgrps,
+				   ARRAY_SIZE(apalis_tk1_drvgrps));
+}
+
+#ifdef CONFIG_PCI_TEGRA
+int tegra_pcie_board_init(void)
+{
+	/* TODO: Convert to driver model
+	struct udevice *pmic;
+	int err;
+
+	err = as3722_init(&pmic);
+	if (err) {
+		error("failed to initialize AS3722 PMIC: %d\n", err);
+		return err;
+	}
+
+	err = as3722_sd_enable(pmic, 4);
+	if (err < 0) {
+		error("failed to enable SD4: %d\n", err);
+		return err;
+	}
+
+	err = as3722_sd_set_voltage(pmic, 4, 0x24);
+	if (err < 0) {
+		error("failed to set SD4 voltage: %d\n", err);
+		return err;
+	}
+
+	err = as3722_gpio_configure(pmic, 1, AS3722_GPIO_OUTPUT_VDDH |
+					     AS3722_GPIO_INVERT);
+	if (err < 0) {
+		error("failed to configure GPIO#1 as output: %d\n", err);
+		return err;
+	}
+
+	err = as3722_gpio_direction_output(pmic, 2, 1);
+	if (err < 0) {
+		error("failed to set GPIO#2 high: %d\n", err);
+		return err;
+	}
+	*/
+
+	/* Reset I210 Gigabit Ethernet Controller */
+	gpio_request(LAN_RESET_N, "LAN_RESET_N");
+	gpio_direction_output(LAN_RESET_N, 0);
+
+	/*
+	 * Make sure we don't get any back feeding from LAN_WAKE_N resp.
+	 * DEV_OFF_N
+	 */
+	gpio_request(TEGRA_GPIO(O, 5), "LAN_WAKE_N");
+	gpio_direction_output(TEGRA_GPIO(O, 5), 0);
+
+	gpio_request(TEGRA_GPIO(O, 6), "LAN_DEV_OFF_N");
+	gpio_direction_output(TEGRA_GPIO(O, 6), 0);
+
+	/* Make sure LDO9 and LDO10 are initially enabled @ 0V */
+	/* TODO: Convert to driver model
+	err = as3722_ldo_enable(pmic, 9);
+	if (err < 0) {
+		error("failed to enable LDO9: %d\n", err);
+		return err;
+	}
+	err = as3722_ldo_enable(pmic, 10);
+	if (err < 0) {
+		error("failed to enable LDO10: %d\n", err);
+		return err;
+	}
+	err = as3722_ldo_set_voltage(pmic, 9, 0x80);
+	if (err < 0) {
+		error("failed to set LDO9 voltage: %d\n", err);
+		return err;
+	}
+	err = as3722_ldo_set_voltage(pmic, 10, 0x80);
+	if (err < 0) {
+		error("failed to set LDO10 voltage: %d\n", err);
+		return err;
+	}
+	*/
+
+	mdelay(100);
+
+	/* Make sure controller gets enabled by disabling DEV_OFF_N */
+	gpio_set_value(TEGRA_GPIO(O, 6), 1);
+
+	/* Enable LDO9 and LDO10 for +V3.3_ETH on patched prototypes */
+	/* TODO: Convert to driver model
+	err = as3722_ldo_set_voltage(pmic, 9, 0xff);
+	if (err < 0) {
+		error("failed to set LDO9 voltage: %d\n", err);
+		return err;
+	}
+	err = as3722_ldo_set_voltage(pmic, 10, 0xff);
+	if (err < 0) {
+		error("failed to set LDO10 voltage: %d\n", err);
+		return err;
+	}
+	*/
+
+	mdelay(100);
+	gpio_set_value(LAN_RESET_N, 1);
+
+#ifdef APALIS_TK1_PCIE_EVALBOARD_INIT
+#define PEX_PERST_N	TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
+#define RESET_MOCI_CTRL	TEGRA_GPIO(U, 4)
+
+	/* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis Evaluation
+	   Board */
+	gpio_request(PEX_PERST_N, "PEX_PERST_N");
+	gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
+	gpio_direction_output(PEX_PERST_N, 0);
+	gpio_direction_output(RESET_MOCI_CTRL, 0);
+	/* Must be asserted for 100 ms after power and clocks are stable */
+	mdelay(100);
+	gpio_set_value(PEX_PERST_N, 1);
+	/* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed Until
+	   900 us After PEX_PERST# De-assertion */
+	mdelay(1);
+	gpio_set_value(RESET_MOCI_CTRL, 1);
+#endif /* APALIS_T30_PCIE_EVALBOARD_INIT */
+
+	return 0;
+}
+#endif /* CONFIG_PCI_TEGRA */
diff --git a/board/toradex/apalis-tk1/as3722_init.c b/board/toradex/apalis-tk1/as3722_init.c
new file mode 100644
index 0000000..4917034
--- /dev/null
+++ b/board/toradex/apalis-tk1/as3722_init.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2012-2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include "as3722_init.h"
+
+/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
+
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(addr, &reg->cmd_addr0);
+	writel(config, &reg->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+	struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+	writel(data, &reg->cmd_data1);
+	writel(config, &reg->cnfg);
+}
+
+void pmic_enable_cpu_vdd(void)
+{
+	debug("%s entry\n", __func__);
+
+#ifdef AS3722_SD1VOLTAGE_DATA
+	/* Set up VDD_CORE, for boards where OTP is incorrect*/
+	debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
+	/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+#endif
+
+	debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
+	/*
+	 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.0V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
+	/*
+	 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.0V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
+	/*
+	 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
+	 * First set VDD to 1.2V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Set VDD_SDMMC1 to 3.3V via AS3722 reg 0x11/4E\n", __func__);
+	/*
+	 * Bring up VDD_SDMMC1 via the AS3722 PMIC on the PWR I2C bus.
+	 * First set it to value closest to 3.3V, then enable the regulator
+	 *
+	 * NOTE: We do this early because doing it later seems to hose the CPU
+	 * power rail/partition startup. Need to debug.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_LDO1VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_LDO1CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+
+	debug("%s: Set VDD_SDMMC3 to 3.3V via AS3722 reg 0x16/4E\n", __func__);
+	/*
+	 * Bring up VDD_SDMMC3 via the AS3722 PMIC on the PWR I2C bus.
+	 * First set it to bypass 3.3V straight thru, then enable the regulator
+	 *
+	 * NOTE: We do this early because doing it later seems to hose the CPU
+	 * power rail/partition startup. Need to debug.
+	 */
+	tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+	tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
+	/*
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
+	 */
+	udelay(10 * 1000);
+}
diff --git a/board/toradex/apalis-tk1/as3722_init.h b/board/toradex/apalis-tk1/as3722_init.h
new file mode 100644
index 0000000..64898a3
--- /dev/null
+++ b/board/toradex/apalis-tk1/as3722_init.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2012-2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* AS3722-PMIC-specific early init regs */
+
+#define AS3722_I2C_ADDR		0x80
+
+#define AS3722_SD0VOLTAGE_REG	0x00	/* CPU */
+#define AS3722_SD1VOLTAGE_REG	0x01	/* CORE, already set by OTP */
+#define AS3722_SD6VOLTAGE_REG	0x06	/* GPU */
+#define AS3722_SDCONTROL_REG	0x4D
+
+#define AS3722_LDO1VOLTAGE_REG	0x11	/* VDD_SDMMC1 */
+#define AS3722_LDO2VOLTAGE_REG	0x12	/* VPP_FUSE */
+#define AS3722_LDO6VOLTAGE_REG	0x16	/* VDD_SDMMC3 */
+#define AS3722_LDCONTROL_REG	0x4E
+
+#define AS3722_SD0VOLTAGE_DATA	(0x3C00 | AS3722_SD0VOLTAGE_REG)
+#define AS3722_SD0CONTROL_DATA	(0x0100 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD1VOLTAGE_DATA	(0x3200 | AS3722_SD1VOLTAGE_REG)
+#define AS3722_SD1CONTROL_DATA	(0x0200 | AS3722_SDCONTROL_REG)
+
+#define AS3722_SD6CONTROL_DATA	(0x4000 | AS3722_SDCONTROL_REG)
+#define AS3722_SD6VOLTAGE_DATA	(0x2800 | AS3722_SD6VOLTAGE_REG)
+
+#define AS3722_LDO1CONTROL_DATA	(0x0200 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO1VOLTAGE_DATA	(0x7F00 | AS3722_LDO1VOLTAGE_REG)
+
+#define AS3722_LDO2CONTROL_DATA	(0x0400 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO2VOLTAGE_DATA	(0x1000 | AS3722_LDO2VOLTAGE_REG)
+
+#define AS3722_LDO6CONTROL_DATA	(0x4000 | AS3722_LDCONTROL_REG)
+#define AS3722_LDO6VOLTAGE_DATA	(0x3F00 | AS3722_LDO6VOLTAGE_REG)
+
+#define I2C_SEND_2_BYTES	0x0A02
+
+void pmic_enable_cpu_vdd(void);
diff --git a/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h b/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h
new file mode 100644
index 0000000..5ed0da3
--- /dev/null
+++ b/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h
@@ -0,0 +1,287 @@
+/*
+ * Copyright (c) 2016, Toradex, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_APALIS_TK1_H_
+#define _PINMUX_CONFIG_APALIS_TK1_H_
+
+#define GPIO_INIT(_port, _gpio, _init)			\
+	{						\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
+		.init	= TEGRA_GPIO_INIT_##_init,	\
+	}
+
+static const struct tegra_gpio_config apalis_tk1_gpio_inits[] = {
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    1,   IN),
+	GPIO_INIT(B,    1,   IN),
+	GPIO_INIT(C,    0,   OUT0),
+	GPIO_INIT(I,    5,   IN),
+	GPIO_INIT(I,    6,   IN),
+	GPIO_INIT(J,    0,   IN),
+	GPIO_INIT(J,    2,   IN),
+	GPIO_INIT(K,    2,   IN),
+	GPIO_INIT(K,    7,   IN),
+	GPIO_INIT(N,    2,   OUT1),
+	GPIO_INIT(N,    4,   OUT1),
+	GPIO_INIT(N,    5,   OUT1),
+	GPIO_INIT(N,    7,   IN),
+	GPIO_INIT(O,    5,   IN),
+	GPIO_INIT(Q,    0,   OUT0), /* Shift_CTRL_OE[0] */
+	GPIO_INIT(Q,    1,   OUT0), /* Shift_CTRL_OE[1] */
+	GPIO_INIT(Q,    2,   OUT0), /* Shift_CTRL_OE[2] */
+	GPIO_INIT(Q,    4,   OUT0), /* Shift_CTRL_OE[4] */
+	GPIO_INIT(Q,    5,   OUT1), /* Shift_CTRL_Dir_Out[0] */
+	GPIO_INIT(Q,    6,   OUT1), /* Shift_CTRL_Dir_Out[1] */
+	GPIO_INIT(Q,    7,   OUT1), /* Shift_CTRL_Dir_Out[2] */
+	GPIO_INIT(R,    0,   OUT0), /* Shift_CTRL_Dir_In[0] */
+	GPIO_INIT(R,    1,   OUT0), /* Shift_CTRL_Dir_In[1] */
+	GPIO_INIT(R,    2,   OUT0), /* Shift_CTRL_OE[3] */
+	GPIO_INIT(S,    3,   OUT0), /* Shift_CTRL_Dir_In[2] */
+	GPIO_INIT(U,    4,   OUT1),
+	GPIO_INIT(W,    3,   IN),
+	GPIO_INIT(W,    5,   IN),
+	GPIO_INIT(BB,   0,  IN),
+	GPIO_INIT(BB,   3,  OUT0),
+	GPIO_INIT(BB,   4,  IN),
+	GPIO_INIT(BB,   5,  OUT1),
+	GPIO_INIT(BB,   6,  OUT0),
+	GPIO_INIT(CC,   5,  IN),
+	GPIO_INIT(DD,   3,  IN),
+	GPIO_INIT(EE,   3,  IN),
+	GPIO_INIT(EE,   5,  IN),
+	GPIO_INIT(FF,   1,  IN),
+};
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel)	\
+	{							\
+		.pingrp		= PMUX_PINGRP_##_pingrp,	\
+		.func		= PMUX_FUNC_##_mux,		\
+		.pull		= PMUX_PULL_##_pull,		\
+		.tristate	= PMUX_TRI_##_tri,		\
+		.io		= PMUX_PIN_##_io,		\
+		.od		= PMUX_PIN_OD_##_od,		\
+		.rcv_sel	= PMUX_PIN_RCV_SEL_##_rcv_sel,	\
+		.lock		= PMUX_PIN_LOCK_DEFAULT,	\
+		.ioreset	= PMUX_PIN_IO_RESET_DEFAULT,	\
+	}
+
+static const struct pmux_pingrp_config apalis_tk1_pingrps[] = {
+	/*     pingrp,                 mux,          pull,   tri,      e_input, od,      rcv_sel */
+	PINCFG(CLK_32K_OUT_PA0,        SOC,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART3_CTS_N_PA1,        GMI,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_FS_PA2,            HDA,          NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_SCLK_PA3,          HDA,          NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_DIN_PA4,           HDA,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP2_DOUT_PA5,          HDA,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CLK_PA6,         SDMMC3,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CMD_PA7,         SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PB0,                    UARTD,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PB1,                    RSVD2,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT3_PB4,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT2_PB5,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT1_PB6,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_DAT0_PB7,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART3_RTS_N_PC0,        GMI,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_TXD_PC2,          IRDA,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART2_RXD_PC3,          IRDA,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(GEN1_I2C_SCL_PC4,       I2C1,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(GEN1_I2C_SDA_PC5,       I2C1,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PC7,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG0,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG1,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG2,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG3,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG4,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG5,                    SPI4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG6,                    SPI4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PG7,                    SPI4,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PH0,                    PWM0,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH1,                    PWM1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH2,                    PWM2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH3,                    PWM3,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH4,                    RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH5,                    RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH6,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PH7,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI0,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI1,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI2,                    RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI3,                    SPI4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI4,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PI5,                    RSVD2,        UP,     TRISTATE, INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PI6,                    RSVD1,        UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PI7,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PJ0,                    RSVD1,        UP,     TRISTATE, INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PJ2,                    RSVD1,        UP,     TRISTATE, INPUT,   ENABLE,  DEFAULT),
+	PINCFG(UART2_CTS_N_PJ5,        UARTB,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART2_RTS_N_PJ6,        UARTB,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PJ7,                    UARTD,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK0,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK1,                    RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK2,                    RSVD1,        UP,     TRISTATE, INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PK3,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PK4,                    RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SPDIF_OUT_PK5,          SPDIF,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SPDIF_IN_PK6,           SPDIF,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PK7,                    RSVD2,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP1_FS_PN0,            RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_DIN_PN1,           RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_DOUT_PN2,          SATA,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP1_SCLK_PN3,          RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(USB_VBUS_EN0_PN4,       RSVD2,        NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+	PINCFG(USB_VBUS_EN1_PN5,       RSVD2,        NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+	PINCFG(HDMI_INT_PN7,           RSVD1,        DOWN,   TRISTATE, INPUT,   DEFAULT, NORMAL),
+	PINCFG(ULPI_DATA7_PO0,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA0_PO1,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA1_PO2,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA2_PO3,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA3_PO4,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA4_PO5,         ULPI,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA5_PO6,         ULPI,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DATA6_PO7,         ULPI,         DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_FS_PP0,            I2S2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_DIN_PP1,           I2S2,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP3_DOUT_PP2,          I2S2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP3_SCLK_PP3,          I2S2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_FS_PP4,            RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_DIN_PP5,           RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_DOUT_PP6,          RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP4_SCLK_PP7,          RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL0_PQ0,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL1_PQ1,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL2_PQ2,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL3_PQ3,            KBC,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL4_PQ4,            KBC,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL5_PQ5,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL6_PQ6,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_COL7_PQ7,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW0_PR0,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW1_PR1,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW2_PR2,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW3_PR3,            KBC,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW4_PR4,            RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW5_PR5,            RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW6_PR6,            KBC,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW7_PR7,            RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW8_PS0,            RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW9_PS1,            RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW10_PS2,           RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW11_PS3,           RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW12_PS4,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW13_PS5,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW14_PS6,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW15_PS7,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW16_PT0,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(KB_ROW17_PT1,           RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GEN2_I2C_SCL_PT5,       I2C2,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(GEN2_I2C_SDA_PT6,       I2C2,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(SDMMC4_CMD_PT7,         SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU0,                    UARTA,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU1,                    UARTA,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU2,                    UARTA,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PU3,                    UARTA,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU4,                    GMI,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU5,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PU6,                    PWM3,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PV0,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PV1,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CD_N_PV2,        RSVD3,        UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_WP_N_PV3,        SDMMC1,       UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DDC_SCL_PV4,            RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DDC_SDA_PV5,            RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(GPIO_W2_AUD_PW2,        SPI2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_W3_AUD_PW3,        SPI6,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DAP_MCLK1_PW4,          EXTPERIPH1,   NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CLK2_OUT_PW5,           RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(UART3_TXD_PW6,          UARTC,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(UART3_RXD_PW7,          UARTC,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DVFS_PWM_PX0,           CLDVFS,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X1_AUD_PX1,        RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DVFS_CLK_PX2,           CLDVFS,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X3_AUD_PX3,        RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X4_AUD_PX4,        SPI2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X5_AUD_PX5,        SPI2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X6_AUD_PX6,        SPI2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(GPIO_X7_AUD_PX7,        SPI2,         NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_CLK_PY0,           SPI1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_DIR_PY1,           SPI1,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(ULPI_NXT_PY2,           SPI1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(ULPI_STP_PY3,           SPI1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT3_PY4,        SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT2_PY5,        SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT1_PY6,        SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_DAT0_PY7,        SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_CLK_PZ0,         SDMMC1,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC1_CMD_PZ1,         SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PWR_I2C_SCL_PZ6,        I2CPWR,       NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PWR_I2C_SDA_PZ7,        I2CPWR,       NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(SDMMC4_DAT0_PAA0,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT1_PAA1,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT2_PAA2,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT3_PAA3,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT4_PAA4,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT5_PAA5,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT6_PAA6,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_DAT7_PAA7,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PBB0,                   VGP6,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(CAM_I2C_SCL_PBB1,       I2C3,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(CAM_I2C_SDA_PBB2,       I2C3,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+	PINCFG(PBB3,                   VGP3,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB4,                   VGP4,         NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PBB5,                   VGP5,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB6,                   RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PBB7,                   RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CAM_MCLK_PCC0,          VI_ALT3,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PCC1,                   RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PCC2,                   RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(SDMMC4_CLK_PCC4,        SDMMC4,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(CLK2_REQ_PCC5,          RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_L0_RST_N_PDD1,      RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_L0_CLKREQ_N_PDD2,   RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_WAKE_N_PDD3,        RSVD2,        NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_L1_RST_N_PDD5,      RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(PEX_L1_CLKREQ_N_PDD6,   RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(CLK3_OUT_PEE0,          EXTPERIPH3,   NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CLK3_REQ_PEE1,          RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(DAP_MCLK1_REQ_PEE2,     RSVD4,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(HDMI_CEC_PEE3,          CEC,          NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+	/*
+	 * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output driver enabled aka not
+	 * tristated and input driver enabled as well as it features some magic
+	 * properties even though the external loopback is disabled and the internal
+	 * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits
+	 * being set to 0xfffd according to the TRM!
+	 */
+	PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(SDMMC3_CLK_LB_IN_PEE5,  RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(DP_HPD_PFF0,            DP,           NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(USB_VBUS_EN2_PFF1,      RSVD2,        NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+	PINCFG(PFF2,                   RSVD2,        NORMAL, NORMAL,   INPUT,   DISABLE, DEFAULT),
+	PINCFG(CORE_PWR_REQ,           PWRON,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(CPU_PWR_REQ,            CPU,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+	PINCFG(PWR_INT_N,              PMI,          UP,     TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(RESET_OUT_N,            RESET_OUT_N,  NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+	PINCFG(OWR,                    RSVD2,        NORMAL, TRISTATE, OUTPUT,  DEFAULT, NORMAL),
+	PINCFG(CLK_32K_IN,             CLK,          NORMAL, TRISTATE, INPUT,   DEFAULT, DEFAULT),
+	PINCFG(JTAG_RTCK,              RTCK,         UP,     NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+	{						\
+		.drvgrp = PMUX_DRVGRP_##_drvgrp,	\
+		.slwf   = _slwf,			\
+		.slwr   = _slwr,			\
+		.drvup  = _drvup,			\
+		.drvdn  = _drvdn,			\
+		.lpmd   = PMUX_LPMD_##_lpmd,		\
+		.schmt  = PMUX_SCHMT_##_schmt,		\
+		.hsm    = PMUX_HSM_##_hsm,		\
+	}
+
+static const struct pmux_drvgrp_config apalis_tk1_drvgrps[] = {
+};
+
+#endif /* PINMUX_CONFIG_APALIS_TK1_H */
diff --git a/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg
new file mode 100644
index 0000000..5cfda26
--- /dev/null
+++ b/board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016 Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7954
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB328F64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09555050
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
+
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x432A0338
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03260324
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43340344
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x031E027C
+
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37
+
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4336453F
+
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E
+
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg b/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg
new file mode 100644
index 0000000..3707910
--- /dev/null
+++ b/board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016 Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E78f5
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xff328f64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
+DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x02888032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
+
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03300338
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03240324
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x03440350
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x032C0308
+
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46
+
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x403E463E
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46
+
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00060015
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E
+
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/apalis_imx6/Kconfig b/board/toradex/apalis_imx6/Kconfig
new file mode 100644
index 0000000..14f8c10
--- /dev/null
+++ b/board/toradex/apalis_imx6/Kconfig
@@ -0,0 +1,55 @@
+if TARGET_APALIS_IMX6
+
+config SYS_BOARD
+	default "apalis_imx6"
+
+config SYS_CONFIG_NAME
+	default "apalis_imx6"
+
+config SYS_CPU
+	default "armv7"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_VENDOR
+	default "toradex"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+config TDX_CMD_IMX_MFGR
+	bool "Enable factory testing commands for Toradex iMX 6 modules"
+	help
+	  This adds the commands
+	    pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100
+	  If executed on already fused modules it doesn't change any fuse setting.
+	default y
+
+config TDX_APALIS_IMX6_V1_0
+	bool "Apalis iMX6 V1.0 HW"
+	help
+	  Apalis iMX6 V1.0 HW has a different pinout for the UART.
+	    The UARTs must be used in DCE mode, RTS/CTS are swapped and
+	    thus unusable on standard carrier boards.
+	    This option configures DCE mode unconditionally. Whithout this
+	    option the config block stating V1.0 HW selects DCE mode,
+	    otherwise the UARTs are configuered in DTE mode.
+	default n
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/board/toradex/apalis_imx6/MAINTAINERS b/board/toradex/apalis_imx6/MAINTAINERS
new file mode 100644
index 0000000..2c70ab4
--- /dev/null
+++ b/board/toradex/apalis_imx6/MAINTAINERS
@@ -0,0 +1,9 @@
+Apalis iMX6
+M:	Max Krummenacher <max.krummenacher@toradex.com>
+W:	http://developer.toradex.com/software/linux/linux-software
+S:	Maintained
+F:	board/toradex/apalis_imx6/
+F:	include/configs/apalis_imx6.h
+F:	configs/apalis_imx6_defconfig
+F:	configs/apalis_imx6_nospl_com_defconfig
+F:	configs/apalis_imx6_nospl_it_defconfig
diff --git a/board/toradex/apalis_imx6/Makefile b/board/toradex/apalis_imx6/Makefile
new file mode 100644
index 0000000..128f179
--- /dev/null
+++ b/board/toradex/apalis_imx6/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2012-2014 Toradex, Inc.
+# SPDX-License-Identifier:      GPL-2.0+
+
+obj-y  := apalis_imx6.o do_fuse.o
+obj-$(CONFIG_TDX_CMD_IMX_MFGR)  += pf0100.o
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
new file mode 100644
index 0000000..8e5613c
--- /dev/null
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -0,0 +1,1246 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ * Copyright (C) 2014-2016, Toradex AG
+ * copied from nitrogen6x
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/bootm.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
+#include <dm/platform_data/serial_mxc.h>
+#include <dm/platdata.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <imx_thermal.h>
+#include <linux/errno.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+#include "../common/tdx-cfg-block.h"
+#ifdef CONFIG_TDX_CMD_IMX_MFGR
+#include "pf0100.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
+
+#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define WEAK_PULLUP	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_SRE_SLOW)
+
+#define NO_PULLUP	(					\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_SRE_SLOW)
+
+#define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
+
+#define TRISTATE	(PAD_CTL_HYS | PAD_CTL_SPEED_MED)
+
+#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
+
+#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
+
+int dram_init(void)
+{
+	/* use the DDR controllers configured size */
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    (ulong)imx_ddr_size());
+
+	return 0;
+}
+
+/* Apalis UART1 */
+iomux_v3_cfg_t const uart1_pads_dce[] = {
+	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+iomux_v3_cfg_t const uart1_pads_dte[] = {
+	MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* Apalis I2C1 */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
+		.gp = IMX_GPIO_NR(5, 27)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
+		.gp = IMX_GPIO_NR(5, 26)
+	}
+};
+
+/* Apalis local, PMIC, SGTL5000, STMPE811 */
+struct i2c_pads_info i2c_pad_info_loc = {
+	.scl = {
+		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+/* Apalis I2C3 / CAM */
+struct i2c_pads_info i2c_pad_info3 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
+		.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
+		.gp = IMX_GPIO_NR(3, 17)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
+		.gp = IMX_GPIO_NR(3, 18)
+	}
+};
+
+/* Apalis I2C2 / DDC */
+struct i2c_pads_info i2c_pad_info_ddc = {
+	.scl = {
+		.i2c_mode = MX6_PAD_EIM_EB2__HDMI_TX_DDC_SCL | PC,
+		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
+		.gp = IMX_GPIO_NR(2, 30)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_EIM_D16__HDMI_TX_DDC_SDA | PC,
+		.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
+		.gp = IMX_GPIO_NR(3, 16)
+	}
+};
+
+/* Apalis MMC1 */
+iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D0__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D1__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D2__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D3__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_DI0_PIN4__GPIO4_IO20   | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+#	define GPIO_MMC_CD IMX_GPIO_NR(4, 20)
+};
+
+/* Apalis SD1 */
+iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__SD2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__SD2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_CS1__GPIO6_IO14  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+#	define GPIO_SD_CD IMX_GPIO_NR(6, 14)
+};
+
+/* eMMC */
+iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP),
+};
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+	/* control data pad skew - devaddr = 0x02, register = 0x04 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* tx data pad skew - devaddr = 0x02, register = 0x05 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+	/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
+	ksz9031_phy_extended_write(phydev, 0x02,
+				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
+	return 0;
+}
+
+iomux_v3_cfg_t const enet_pads[] = {
+	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TXC__RGMII_TXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RXC__RGMII_RXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	/* KSZ9031 PHY Reset */
+	MX6_PAD_ENET_CRS_DV__GPIO1_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL),
+#	define GPIO_ENET_PHY_RESET IMX_GPIO_NR(1, 25)
+};
+
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
+static int reset_enet_phy(struct mii_dev *bus)
+{
+	/* Reset KSZ9031 PHY */
+	gpio_direction_output(GPIO_ENET_PHY_RESET, 0);
+	mdelay(10);
+	gpio_set_value(GPIO_ENET_PHY_RESET, 1);
+
+	return 0;
+}
+
+/* mux the Apalis GPIO pins, so they can be used from the U-Boot cmdline */
+iomux_v3_cfg_t const gpio_pads[] = {
+	/* Apalis GPIO1 - GPIO8 */
+	MX6_PAD_NANDF_D4__GPIO2_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_D5__GPIO2_IO05	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_D6__GPIO2_IO06	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_D7__GPIO2_IO07	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_RB0__GPIO6_IO10	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_WP_B__GPIO6_IO09	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(WEAK_PULLDOWN),
+	MX6_PAD_GPIO_6__GPIO1_IO06	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
+};
+
+static void setup_iomux_gpio(void)
+{
+	imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
+}
+
+iomux_v3_cfg_t const usb_pads[] = {
+	/* USBH_EN */
+	MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#	define GPIO_USBH_EN IMX_GPIO_NR(1, 0)
+	/* USB_VBUS_DET */
+	MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#	define GPIO_USB_VBUS_DET IMX_GPIO_NR(3, 28)
+	/* USBO1_ID */
+	MX6_PAD_ENET_RX_ER__USB_OTG_ID	| MUX_PAD_CTRL(WEAK_PULLUP),
+	/* USBO1_EN */
+	MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#	define GPIO_USBO_EN IMX_GPIO_NR(3, 22)
+};
+
+/*
+ * UARTs are used in DTE mode, switch the mode on all UARTs before
+ * any pinmuxing connects a (DCE) output to a transceiver output.
+ */
+#define UFCR		0x90	/* FIFO Control Register */
+#define UFCR_DCEDTE	(1<<6)	/* DCE=0 */
+
+static void setup_dtemode_uart(void)
+{
+	setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
+	setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
+	setbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
+	setbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
+}
+static void setup_dcemode_uart(void)
+{
+	clrbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
+	clrbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
+	clrbits_le32((u32 *)(UART4_BASE + UFCR), UFCR_DCEDTE);
+	clrbits_le32((u32 *)(UART5_BASE + UFCR), UFCR_DCEDTE);
+}
+
+static void setup_iomux_dte_uart(void)
+{
+	setup_dtemode_uart();
+	imx_iomux_v3_setup_multiple_pads(uart1_pads_dte,
+					 ARRAY_SIZE(uart1_pads_dte));
+}
+
+static void setup_iomux_dce_uart(void)
+{
+	setup_dcemode_uart();
+	imx_iomux_v3_setup_multiple_pads(uart1_pads_dce,
+					 ARRAY_SIZE(uart1_pads_dce));
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	switch (port) {
+	case 0:
+		/* control OTG power */
+		gpio_direction_output(GPIO_USBO_EN, on);
+		mdelay(100);
+		break;
+	case 1:
+		/* Control MXM USBH */
+		gpio_direction_output(GPIO_USBH_EN, on);
+		mdelay(2);
+		/* Control onboard USB Hub VBUS */
+		gpio_direction_output(GPIO_USB_VBUS_DET, on);
+		mdelay(100);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+/* use the following sequence: eMMC, MMC, SD */
+struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+	{USDHC3_BASE_ADDR},
+	{USDHC1_BASE_ADDR},
+	{USDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = true; /* default: assume inserted */
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		gpio_direction_input(GPIO_MMC_CD);
+		ret = !gpio_get_value(GPIO_MMC_CD);
+		break;
+	case USDHC2_BASE_ADDR:
+		gpio_direction_input(GPIO_SD_CD);
+		ret = !gpio_get_value(GPIO_SD_CD);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifndef CONFIG_SPL_BUILD
+	s32 status = 0;
+	u32 index = 0;
+
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+	usdhc_cfg[0].max_bus_width = 8;
+	usdhc_cfg[1].max_bus_width = 8;
+	usdhc_cfg[2].max_bus_width = 4;
+
+	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+		switch (index) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			break;
+		case 1:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			break;
+		case 2:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
+			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return status;
+		}
+
+		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+	}
+
+	return status;
+#else
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned reg = readl(&psrc->sbmr1) >> 11;
+	/*
+	 * Upon reading BOOT_CFG register the following map is done:
+	 * Bit 11 and 12 of BOOT_CFG register can determine the current
+	 * mmc port
+	 * 0x1                  SD1
+	 * 0x2                  SD2
+	 * 0x3                  SD4
+	 */
+
+	switch (reg & 0x3) {
+	case 0x0:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	case 0x1:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	case 0x2:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	default:
+		puts("MMC boot device not available");
+	}
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+#endif
+}
+#endif
+
+int board_phy_config(struct phy_device *phydev)
+{
+	mx6_rgmii_rework(phydev);
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	uint32_t base = IMX_FEC_BASE;
+	struct mii_dev *bus = NULL;
+	struct phy_device *phydev = NULL;
+	int ret;
+
+	setup_iomux_enet();
+
+#ifdef CONFIG_FEC_MXC
+	bus = fec_get_miibus(base, -1);
+	if (!bus)
+		return 0;
+	bus->reset = reset_enet_phy;
+	/* scan PHY 4,5,6,7 */
+	phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
+	if (!phydev) {
+		free(bus);
+		puts("no PHY found\n");
+		return 0;
+	}
+	printf("using PHY at %d\n", phydev->addr);
+	ret = fec_probe(bis, -1, base, bus, phydev);
+	if (ret) {
+		printf("FEC MXC: %s:failed\n", __func__);
+		free(phydev);
+		free(bus);
+	}
+#endif
+	return 0;
+}
+
+static iomux_v3_cfg_t const pwr_intb_pads[] = {
+	/*
+	 * the bootrom sets the iomux to vselect, potentially connecting
+	 * two outputs. Set this back to GPIO
+	 */
+	MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static iomux_v3_cfg_t const backlight_pads[] = {
+	/* Backlight on RGB connector: J15 */
+	MX6_PAD_EIM_DA13__GPIO3_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 13)
+	/* additional CPU pin on BKL_PWM, keep in tristate */
+	MX6_PAD_EIM_DA14__GPIO3_IO14 | MUX_PAD_CTRL(TRISTATE),
+	/* Backlight PWM, used as GPIO in U-Boot */
+	MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 10)
+	/* buffer output enable 0: buffer enabled */
+	MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
+#define RGB_BACKLIGHTPWM_OE IMX_GPIO_NR(5, 2)
+	/* PSAVE# integrated VDAC */
+	MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define VGA_PSAVE_NOT_GP IMX_GPIO_NR(6, 31)
+};
+
+static iomux_v3_cfg_t const rgb_pads[] = {
+	MX6_PAD_EIM_A16__IPU1_DI1_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA10__IPU1_DI1_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA11__IPU1_DI1_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA12__IPU1_DI1_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA9__IPU1_DISP1_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA8__IPU1_DISP1_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA7__IPU1_DISP1_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA6__IPU1_DISP1_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA5__IPU1_DISP1_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA4__IPU1_DISP1_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA3__IPU1_DISP1_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA2__IPU1_DISP1_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA1__IPU1_DISP1_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_DA0__IPU1_DISP1_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_EB1__IPU1_DISP1_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_EB0__IPU1_DISP1_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_A17__IPU1_DISP1_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_A18__IPU1_DISP1_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_A19__IPU1_DISP1_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_A20__IPU1_DISP1_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_A21__IPU1_DISP1_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_A22__IPU1_DISP1_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_A23__IPU1_DISP1_DATA18 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_A24__IPU1_DISP1_DATA19 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_D26__IPU1_DISP1_DATA22 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_D27__IPU1_DISP1_DATA23 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_D30__IPU1_DISP1_DATA21 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_EIM_D31__IPU1_DISP1_DATA20 | MUX_PAD_CTRL(OUTPUT_RGB),
+};
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+static int detect_i2c(struct display_info_t const *dev)
+{
+	return (0 == i2c_set_bus_num(dev->bus)) &&
+	       (0 == i2c_probe(dev->addr));
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)
+				IOMUXC_BASE_ADDR;
+	u32 reg = readl(&iomux->gpr[2]);
+	reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
+	writel(reg, &iomux->gpr[2]);
+	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
+	gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
+}
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+	imx_iomux_v3_setup_multiple_pads(
+		rgb_pads,
+		ARRAY_SIZE(rgb_pads));
+	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
+	gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
+}
+
+static int detect_default(struct display_info_t const *dev)
+{
+	(void) dev;
+	return 1;
+}
+
+struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.di	= 1,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_default,
+	.enable	= enable_rgb,
+	.mode	= {
+		.name           = "vga-rgb",
+		.refresh        = 60,
+		.xres           = 640,
+		.yres           = 480,
+		.pixclock       = 33000,
+		.left_margin    = 48,
+		.right_margin   = 16,
+		.upper_margin   = 31,
+		.lower_margin   = 11,
+		.hsync_len      = 96,
+		.vsync_len      = 2,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.di	= 1,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.enable	= enable_rgb,
+	.mode	= {
+		.name           = "wvga-rgb",
+		.refresh        = 60,
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 25000,
+		.left_margin    = 40,
+		.right_margin   = 88,
+		.upper_margin   = 33,
+		.lower_margin   = 10,
+		.hsync_len      = 128,
+		.vsync_len      = 2,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_LVDS666,
+	.detect	= detect_i2c,
+	.enable	= enable_lvds,
+	.mode	= {
+		.name           = "wsvga-lvds",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 600,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+	/* Turn on LDB0,IPU,IPU DI0 clocks */
+	reg = __raw_readl(&mxc_ccm->CCGR3);
+	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* set LDB0, LDB1 clk select to 011/011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+		 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+	      |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+	     |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+	     |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+	     |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+	     |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+	     |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+	     |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+	     |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+	     |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
+			|IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+	       <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+
+	/* backlight unconditionally on for now */
+	imx_iomux_v3_setup_multiple_pads(backlight_pads,
+					 ARRAY_SIZE(backlight_pads));
+	/* use 0 for EDT 7", use 1 for LG fullHD panel */
+	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
+	gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
+	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+}
+#endif /* defined(CONFIG_VIDEO_IPUV3) */
+
+int board_early_init_f(void)
+{
+	imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
+					 ARRAY_SIZE(pwr_intb_pads));
+#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
+	setup_iomux_dte_uart();
+#else
+	setup_iomux_dce_uart();
+#endif
+
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+
+#ifdef CONFIG_TDX_CMD_IMX_MFGR
+	(void) pmic_init();
+#endif
+
+#ifdef CONFIG_SATA
+	setup_sata();
+#endif
+
+	setup_iomux_gpio();
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if defined(CONFIG_REVISION_TAG) && \
+    defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+	char env_str[256];
+	u32 rev;
+
+	rev = get_board_rev();
+	snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
+	setenv("board_rev", env_str);
+
+#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
+	if ((rev & 0xfff0) == 0x0100) {
+		char *fdt_env;
+
+		/* reconfigure the UART to DCE mode dynamically if on V1.0 HW */
+		setup_iomux_dce_uart();
+
+		/* if using the default device tree, use version for V1.0 HW */
+		fdt_env = getenv("fdt_file");
+		if ((fdt_env != NULL) && (strcmp(FDT_FILE, fdt_env) == 0)) {
+			setenv("fdt_file", FDT_FILE_V1_0);
+			printf("patching fdt_file to " FDT_FILE_V1_0 "\n");
+#ifndef CONFIG_ENV_IS_NOWHERE
+			saveenv();
+#endif
+		}
+	}
+#endif /* CONFIG_TDX_APALIS_IMX6_V1_0 */
+#endif /* CONFIG_REVISION_TAG */
+
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
+int ft_system_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	char it[] = " IT";
+	int minc, maxc;
+
+	switch (get_cpu_temp_grade(&minc, &maxc)) {
+	case TEMP_AUTOMOTIVE:
+	case TEMP_INDUSTRIAL:
+		break;
+	case TEMP_EXTCOMMERCIAL:
+	default:
+		it[0] = 0;
+	};
+	printf("Model: Toradex Apalis iMX6 %s %s%s\n",
+	       is_cpu_type(MXC_CPU_MX6D) ? "Dual" : "Quad",
+	       (gd->ram_size == 0x80000000) ? "2GB" :
+	       (gd->ram_size == 0x40000000) ? "1GB" : "512MB", it);
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4-bit bus width */
+	{"mmc",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+	{"sd",	MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{NULL,	0},
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+/* TODO, use external pmic, for now always ldo_enable */
+void ldo_mode_set(int ldo_bypass)
+{
+	return;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <libfdt.h>
+#include "asm/arch/mx6q-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+static int mx6_com_dcd_table[] = {
+/* ddr-setup.cfg */
+MX6_IOM_DRAM_SDQS0, 0x00000030,
+MX6_IOM_DRAM_SDQS1, 0x00000030,
+MX6_IOM_DRAM_SDQS2, 0x00000030,
+MX6_IOM_DRAM_SDQS3, 0x00000030,
+MX6_IOM_DRAM_SDQS4, 0x00000030,
+MX6_IOM_DRAM_SDQS5, 0x00000030,
+MX6_IOM_DRAM_SDQS6, 0x00000030,
+MX6_IOM_DRAM_SDQS7, 0x00000030,
+
+MX6_IOM_GRP_B0DS, 0x00000030,
+MX6_IOM_GRP_B1DS, 0x00000030,
+MX6_IOM_GRP_B2DS, 0x00000030,
+MX6_IOM_GRP_B3DS, 0x00000030,
+MX6_IOM_GRP_B4DS, 0x00000030,
+MX6_IOM_GRP_B5DS, 0x00000030,
+MX6_IOM_GRP_B6DS, 0x00000030,
+MX6_IOM_GRP_B7DS, 0x00000030,
+MX6_IOM_GRP_ADDDS, 0x00000030,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_CTLDS, 0x00000030,
+
+MX6_IOM_DRAM_DQM0, 0x00020030,
+MX6_IOM_DRAM_DQM1, 0x00020030,
+MX6_IOM_DRAM_DQM2, 0x00020030,
+MX6_IOM_DRAM_DQM3, 0x00020030,
+MX6_IOM_DRAM_DQM4, 0x00020030,
+MX6_IOM_DRAM_DQM5, 0x00020030,
+MX6_IOM_DRAM_DQM6, 0x00020030,
+MX6_IOM_DRAM_DQM7, 0x00020030,
+
+MX6_IOM_DRAM_CAS, 0x00020030,
+MX6_IOM_DRAM_RAS, 0x00020030,
+MX6_IOM_DRAM_SDCLK_0, 0x00020030,
+MX6_IOM_DRAM_SDCLK_1, 0x00020030,
+
+MX6_IOM_DRAM_RESET, 0x00020030,
+MX6_IOM_DRAM_SDCKE0, 0x00003000,
+MX6_IOM_DRAM_SDCKE1, 0x00003000,
+
+MX6_IOM_DRAM_SDODT0, 0x00003030,
+MX6_IOM_DRAM_SDODT1, 0x00003030,
+
+/* (differential input) */
+MX6_IOM_DDRMODE_CTL, 0x00020000,
+/* (differential input) */
+MX6_IOM_GRP_DDRMODE, 0x00020000,
+/* disable ddr pullups */
+MX6_IOM_GRP_DDRPKE, 0x00000000,
+MX6_IOM_DRAM_SDBA2, 0x00000000,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
+
+/* Read data DQ Byte0-3 delay */
+MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
+
+/*
+ * MDMISC	mirroring	interleaved (row/bank/col)
+ */
+MX6_MMDC_P0_MDMISC, 0x00081740,
+
+/*
+ * MDSCR	con_req
+ */
+MX6_MMDC_P0_MDSCR, 0x00008000,
+
+/* 1066mhz_4x128mx16.cfg */
+
+MX6_MMDC_P0_MDPDC, 0x00020036,
+MX6_MMDC_P0_MDCFG0, 0x555A7954,
+MX6_MMDC_P0_MDCFG1, 0xDB328F64,
+MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
+MX6_MMDC_P0_MDRWD, 0x000026D2,
+MX6_MMDC_P0_MDOR, 0x005A1023,
+MX6_MMDC_P0_MDOTC, 0x09555050,
+MX6_MMDC_P0_MDPDC, 0x00025576,
+MX6_MMDC_P0_MDASP, 0x00000027,
+MX6_MMDC_P0_MDCTL, 0x831A0000,
+MX6_MMDC_P0_MDSCR, 0x04088032,
+MX6_MMDC_P0_MDSCR, 0x00008033,
+MX6_MMDC_P0_MDSCR, 0x00428031,
+MX6_MMDC_P0_MDSCR, 0x19308030,
+MX6_MMDC_P0_MDSCR, 0x04008040,
+MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P0_MDREF, 0x00005800,
+MX6_MMDC_P0_MPODTCTRL, 0x00000000,
+MX6_MMDC_P1_MPODTCTRL, 0x00000000,
+
+MX6_MMDC_P0_MPDGCTRL0, 0x432A0338,
+MX6_MMDC_P0_MPDGCTRL1, 0x03260324,
+MX6_MMDC_P1_MPDGCTRL0, 0x43340344,
+MX6_MMDC_P1_MPDGCTRL1, 0x031E027C,
+
+MX6_MMDC_P0_MPRDDLCTL, 0x33272D2E,
+MX6_MMDC_P1_MPRDDLCTL, 0x2F312B37,
+
+MX6_MMDC_P0_MPWRDLCTL, 0x3A35433C,
+MX6_MMDC_P1_MPWRDLCTL, 0x4336453F,
+
+MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
+MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
+MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
+MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
+
+MX6_MMDC_P0_MPMUR0, 0x00000800,
+MX6_MMDC_P1_MPMUR0, 0x00000800,
+MX6_MMDC_P0_MDSCR, 0x00000000,
+MX6_MMDC_P0_MAPSR, 0x00011006,
+};
+
+static int mx6_it_dcd_table[] = {
+/* ddr-setup.cfg */
+MX6_IOM_DRAM_SDQS0, 0x00000030,
+MX6_IOM_DRAM_SDQS1, 0x00000030,
+MX6_IOM_DRAM_SDQS2, 0x00000030,
+MX6_IOM_DRAM_SDQS3, 0x00000030,
+MX6_IOM_DRAM_SDQS4, 0x00000030,
+MX6_IOM_DRAM_SDQS5, 0x00000030,
+MX6_IOM_DRAM_SDQS6, 0x00000030,
+MX6_IOM_DRAM_SDQS7, 0x00000030,
+
+MX6_IOM_GRP_B0DS, 0x00000030,
+MX6_IOM_GRP_B1DS, 0x00000030,
+MX6_IOM_GRP_B2DS, 0x00000030,
+MX6_IOM_GRP_B3DS, 0x00000030,
+MX6_IOM_GRP_B4DS, 0x00000030,
+MX6_IOM_GRP_B5DS, 0x00000030,
+MX6_IOM_GRP_B6DS, 0x00000030,
+MX6_IOM_GRP_B7DS, 0x00000030,
+MX6_IOM_GRP_ADDDS, 0x00000030,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_CTLDS, 0x00000030,
+
+MX6_IOM_DRAM_DQM0, 0x00020030,
+MX6_IOM_DRAM_DQM1, 0x00020030,
+MX6_IOM_DRAM_DQM2, 0x00020030,
+MX6_IOM_DRAM_DQM3, 0x00020030,
+MX6_IOM_DRAM_DQM4, 0x00020030,
+MX6_IOM_DRAM_DQM5, 0x00020030,
+MX6_IOM_DRAM_DQM6, 0x00020030,
+MX6_IOM_DRAM_DQM7, 0x00020030,
+
+MX6_IOM_DRAM_CAS, 0x00020030,
+MX6_IOM_DRAM_RAS, 0x00020030,
+MX6_IOM_DRAM_SDCLK_0, 0x00020030,
+MX6_IOM_DRAM_SDCLK_1, 0x00020030,
+
+MX6_IOM_DRAM_RESET, 0x00020030,
+MX6_IOM_DRAM_SDCKE0, 0x00003000,
+MX6_IOM_DRAM_SDCKE1, 0x00003000,
+
+MX6_IOM_DRAM_SDODT0, 0x00003030,
+MX6_IOM_DRAM_SDODT1, 0x00003030,
+
+/* (differential input) */
+MX6_IOM_DDRMODE_CTL, 0x00020000,
+/* (differential input) */
+MX6_IOM_GRP_DDRMODE, 0x00020000,
+/* disable ddr pullups */
+MX6_IOM_GRP_DDRPKE, 0x00000000,
+MX6_IOM_DRAM_SDBA2, 0x00000000,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
+
+/* Read data DQ Byte0-3 delay */
+MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
+
+/*
+ * MDMISC	mirroring	interleaved (row/bank/col)
+ */
+MX6_MMDC_P0_MDMISC, 0x00081740,
+
+/*
+ * MDSCR	con_req
+ */
+MX6_MMDC_P0_MDSCR, 0x00008000,
+
+/* 1066mhz_4x256mx16.cfg */
+
+MX6_MMDC_P0_MDPDC, 0x00020036,
+MX6_MMDC_P0_MDCFG0, 0x898E78f5,
+MX6_MMDC_P0_MDCFG1, 0xff328f64,
+MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
+MX6_MMDC_P0_MDRWD, 0x000026D2,
+MX6_MMDC_P0_MDOR, 0x008E1023,
+MX6_MMDC_P0_MDOTC, 0x09444040,
+MX6_MMDC_P0_MDPDC, 0x00025576,
+MX6_MMDC_P0_MDASP, 0x00000047,
+MX6_MMDC_P0_MDCTL, 0x841A0000,
+MX6_MMDC_P0_MDSCR, 0x02888032,
+MX6_MMDC_P0_MDSCR, 0x00008033,
+MX6_MMDC_P0_MDSCR, 0x00048031,
+MX6_MMDC_P0_MDSCR, 0x19408030,
+MX6_MMDC_P0_MDSCR, 0x04008040,
+MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P0_MDREF, 0x00007800,
+MX6_MMDC_P0_MPODTCTRL, 0x00022227,
+MX6_MMDC_P1_MPODTCTRL, 0x00022227,
+
+MX6_MMDC_P0_MPDGCTRL0, 0x03300338,
+MX6_MMDC_P0_MPDGCTRL1, 0x03240324,
+MX6_MMDC_P1_MPDGCTRL0, 0x03440350,
+MX6_MMDC_P1_MPDGCTRL1, 0x032C0308,
+
+MX6_MMDC_P0_MPRDDLCTL, 0x40363C3E,
+MX6_MMDC_P1_MPRDDLCTL, 0x3C3E3C46,
+
+MX6_MMDC_P0_MPWRDLCTL, 0x403E463E,
+MX6_MMDC_P1_MPWRDLCTL, 0x4A384C46,
+
+MX6_MMDC_P0_MPWLDECTRL0, 0x0009000E,
+MX6_MMDC_P0_MPWLDECTRL1, 0x0018000B,
+MX6_MMDC_P1_MPWLDECTRL0, 0x00060015,
+MX6_MMDC_P1_MPWLDECTRL1, 0x0006000E,
+
+MX6_MMDC_P0_MPMUR0, 0x00000800,
+MX6_MMDC_P1_MPMUR0, 0x00000800,
+MX6_MMDC_P0_MDSCR, 0x00000000,
+MX6_MMDC_P0_MAPSR, 0x00011006,
+};
+
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFFFF3, &ccm->CCGR2);
+	writel(0x3FF0300F, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000F3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1	   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+	writel(0x000000FB, &ccm->ccosr);
+}
+
+static void gpr_init(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* enable AXI cache for VDOA/VPU/IPU */
+	writel(0xF00000CF, &iomux->gpr[4]);
+	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+	writel(0x007F007F, &iomux->gpr[6]);
+	writel(0x007F007F, &iomux->gpr[7]);
+}
+
+static void ddr_init(int *table, int size)
+{
+	int i;
+
+	for (i = 0; i < size / 2 ; i++)
+		writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+	int minc, maxc;
+
+	switch (get_cpu_temp_grade(&minc, &maxc)) {
+	case TEMP_COMMERCIAL:
+	case TEMP_EXTCOMMERCIAL:
+		puts("Commercial temperature grade DDR3 timings.\n");
+		ddr_init(mx6_com_dcd_table, ARRAY_SIZE(mx6_com_dcd_table));
+		break;
+	case TEMP_INDUSTRIAL:
+	case TEMP_AUTOMOTIVE:
+	default:
+		puts("Industrial temperature grade DDR3 timings.\n");
+		ddr_init(mx6_it_dcd_table, ARRAY_SIZE(mx6_it_dcd_table));
+		break;
+	};
+	udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* iomux and setup of i2c */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
+	/* Make sure we use dte mode */
+	setup_dtemode_uart();
+#endif
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
+
+#endif
+
+static struct mxc_serial_platdata mxc_serial_plat = {
+	.reg = (struct mxc_uart *)UART1_BASE,
+	.use_dte = true,
+};
+
+U_BOOT_DEVICE(mxc_serial) = {
+	.name = "serial_mxc",
+	.platdata = &mxc_serial_plat,
+};
diff --git a/board/toradex/apalis_imx6/apalis_imx6q.cfg b/board/toradex/apalis_imx6/apalis_imx6q.cfg
new file mode 100644
index 0000000..b775010
--- /dev/null
+++ b/board/toradex/apalis_imx6/apalis_imx6q.cfg
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#if CONFIG_DDR_MB == 2048
+#include "1066mhz_4x256mx16.cfg"
+#else
+#include "1066mhz_4x128mx16.cfg"
+#endif
+#include "clocks.cfg"
diff --git a/board/toradex/apalis_imx6/clocks.cfg b/board/toradex/apalis_imx6/clocks.cfg
new file mode 100644
index 0000000..be96094
--- /dev/null
+++ b/board/toradex/apalis_imx6/clocks.cfg
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1	   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/toradex/apalis_imx6/ddr-setup.cfg b/board/toradex/apalis_imx6/ddr-setup.cfg
new file mode 100644
index 0000000..de7cdd6
--- /dev/null
+++ b/board/toradex/apalis_imx6/ddr-setup.cfg
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+/*
+ * DDR3 settings
+ * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
+ *	   memory bus width: 64 bits	x16/x32/x64
+ * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 64 bits	x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 32 bits	x16/x32
+ */
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+
+/* (differential input) */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+/* (differential input) */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+/* disable ddr pullups */
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+
+/* Read data DQ Byte0-3 delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+/*
+ * MDMISC	mirroring	interleaved (row/bank/col)
+ */
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
+
+/*
+ * MDSCR	con_req
+ */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
diff --git a/board/toradex/apalis_imx6/do_fuse.c b/board/toradex/apalis_imx6/do_fuse.c
new file mode 100644
index 0000000..cff07e9
--- /dev/null
+++ b/board/toradex/apalis_imx6/do_fuse.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Helpers for i.MX OTP fusing during module production
+*/
+
+#include <common.h>
+#ifndef CONFIG_SPL_BUILD
+#include <console.h>
+#include <fuse.h>
+
+static int mfgr_fuse(void)
+{
+	unsigned val, val6;
+
+	fuse_sense(0, 5, &val);
+	printf("Fuse 0, 5: %8x\n", val);
+	fuse_sense(0, 6, &val6);
+	printf("Fuse 0, 6: %8x\n", val6);
+	fuse_sense(4, 3, &val);
+	printf("Fuse 4, 3: %8x\n", val);
+	fuse_sense(4, 2, &val);
+	printf("Fuse 4, 2: %8x\n", val);
+	if (val6 & 0x10) {
+		puts("BT_FUSE_SEL already fused, will do nothing\n");
+		return CMD_RET_FAILURE;
+	}
+	/* boot cfg */
+	fuse_prog(0, 5, 0x00005072);
+	/* BT_FUSE_SEL */
+	fuse_prog(0, 6, 0x00000010);
+	return CMD_RET_SUCCESS;
+}
+
+int do_mfgr_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
+		char * const argv[])
+{
+	int ret;
+	puts("Fusing...\n");
+	ret = mfgr_fuse();
+	if (ret == CMD_RET_SUCCESS)
+		puts("done.\n");
+	else
+		puts("failed.\n");
+	return ret;
+}
+
+int do_updt_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
+		char * const argv[])
+{
+	unsigned val;
+	int ret;
+	int confirmed = argc >= 1 && !strcmp(argv[1], "-y");
+
+	/* can be used in scripts for command availability check */
+	if (argc >= 1 && !strcmp(argv[1], "-n"))
+		return CMD_RET_SUCCESS;
+
+	/* boot cfg */
+	fuse_sense(0, 5, &val);
+	printf("Fuse 0, 5: %8x\n", val);
+	if (val & 0x10) {
+		puts("Fast boot mode already fused, no need to fuse\n");
+		return CMD_RET_SUCCESS;
+	}
+	if (!confirmed) {
+		puts("Warning: Programming fuses is an irreversible operation!\n"
+				"         Updating to fast boot mode prevents easy\n"
+				"         downgrading to previous BSP versions.\n"
+				"\nReally perform this fuse programming? <y/N>\n");
+		if (!confirm_yesno())
+			return CMD_RET_FAILURE;
+	}
+	puts("Fusing fast boot mode...\n");
+	ret = fuse_prog(0, 5, 0x00005072);
+	if (ret == CMD_RET_SUCCESS)
+		puts("done.\n");
+	else
+		puts("failed.\n");
+	return ret;
+}
+
+U_BOOT_CMD(
+	mfgr_fuse, 1, 0, do_mfgr_fuse,
+	"OTP fusing during module production",
+	""
+);
+
+U_BOOT_CMD(
+	updt_fuse, 2, 0, do_updt_fuse,
+	"OTP fusing during module update",
+	"updt_fuse [-n] [-y] - boot cfg fast boot mode fusing"
+);
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/toradex/apalis_imx6/pf0100.c b/board/toradex/apalis_imx6/pf0100.c
new file mode 100644
index 0000000..5eaf9c0
--- /dev/null
+++ b/board/toradex/apalis_imx6/pf0100.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Helpers for Freescale PMIC PF0100
+*/
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+
+#include "pf0100_otp.inc"
+#include "pf0100.h"
+
+/* define for PMIC register dump */
+/*#define DEBUG */
+
+/* use Apalis GPIO1 to switch on VPGM, ON: 1 */
+static iomux_v3_cfg_t const pmic_prog_pads[] = {
+	MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#	define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 4)
+};
+
+unsigned pmic_init(void)
+{
+	unsigned programmed = 0;
+	uchar bus = 1;
+	uchar devid, revid, val;
+
+	puts("PMIC: ");
+	if (!((0 == i2c_set_bus_num(bus)) &&
+	      (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
+		puts("i2c bus failed\n");
+		return 0;
+	}
+	/* get device ident */
+	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) {
+		puts("i2c pmic devid read failed\n");
+		return 0;
+	}
+	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) {
+		puts("i2c pmic revid read failed\n");
+		return 0;
+	}
+	printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid);
+
+#ifdef DEBUG
+	{
+		unsigned i, j;
+
+		for (i = 0; i < 16; i++)
+			printf("\t%x", i);
+		for (j = 0; j < 0x80; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\nEXT Page 1");
+
+		val = PFUZE100_PAGE_REGISTER_PAGE1;
+		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
+			      &val, 1)) {
+			puts("i2c write failed\n");
+			return 0;
+		}
+
+		for (j = 0x80; j < 0x100; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\nEXT Page 2");
+
+		val = PFUZE100_PAGE_REGISTER_PAGE2;
+		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
+			      &val, 1)) {
+			puts("i2c write failed\n");
+			return 0;
+		}
+
+		for (j = 0x80; j < 0x100; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\n");
+	}
+#endif
+	/* get device programmed state */
+	val = PFUZE100_PAGE_REGISTER_PAGE1;
+	if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) {
+		puts("i2c write failed\n");
+		return 0;
+	}
+	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) {
+		puts("i2c fuse_por read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) {
+		puts("i2c fuse_por read failed\n");
+		return programmed;
+	}
+	if (val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) {
+		puts("i2c fuse_por read failed\n");
+		return programmed;
+	}
+	if (val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	switch (programmed) {
+	case 0:
+		printf("PMIC: not programmed\n");
+		break;
+	case 3:
+		printf("PMIC: programmed\n");
+		break;
+	default:
+		printf("PMIC: undefined programming state\n");
+		break;
+	}
+
+	/* The following is needed during production */
+	if (programmed != 3) {
+		/* set VGEN1 to 1.2V */
+		val = PFUZE100_VGEN1_VAL;
+		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_VGEN1CTL, 1,
+			      &val, 1)) {
+			puts("i2c write failed\n");
+			return programmed;
+		}
+
+		/* set SWBST to 5.0V */
+		val = PFUZE100_SWBST_VAL;
+		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_SWBSTCTL, 1,
+			      &val, 1)) {
+			puts("i2c write failed\n");
+		}
+	}
+	return programmed;
+}
+
+int pf0100_prog(void)
+{
+	unsigned char bus = 1;
+	unsigned char val;
+	unsigned int i;
+
+	if (pmic_init() == 3) {
+		puts("PMIC already programmed, exiting\n");
+		return CMD_RET_FAILURE;
+	}
+	/* set up gpio to manipulate vprog, initially off */
+	imx_iomux_v3_setup_multiple_pads(pmic_prog_pads,
+					 ARRAY_SIZE(pmic_prog_pads));
+	gpio_direction_output(PMIC_PROG_VOLTAGE, 0);
+
+	if (!((0 == i2c_set_bus_num(bus)) &&
+	      (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
+		puts("i2c bus failed\n");
+		return CMD_RET_FAILURE;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(pmic_otp_prog); i++) {
+		switch (pmic_otp_prog[i].cmd) {
+		case pmic_i2c:
+			val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
+			if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg,
+				      1, &val, 1)) {
+				printf("i2c write failed, reg 0x%2x, value 0x%2x\n",
+				       pmic_otp_prog[i].reg, val);
+				return CMD_RET_FAILURE;
+			}
+			break;
+		case pmic_delay:
+			udelay(pmic_otp_prog[i].value * 1000);
+			break;
+		case pmic_vpgm:
+			gpio_direction_output(PMIC_PROG_VOLTAGE,
+					      pmic_otp_prog[i].value);
+			break;
+		case pmic_pwr:
+			/* TODO */
+			break;
+		}
+	}
+	return CMD_RET_SUCCESS;
+}
+
+int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
+		char * const argv[])
+{
+	int ret;
+	puts("Programming PMIC OTP...");
+	ret = pf0100_prog();
+	if (ret == CMD_RET_SUCCESS)
+		puts("done.\n");
+	else
+		puts("failed.\n");
+	return ret;
+}
+
+U_BOOT_CMD(
+	pf0100_otp_prog, 1, 0, do_pf0100_prog,
+	"Program the OTP fuses on the PMIC PF0100",
+	""
+);
diff --git a/board/toradex/apalis_imx6/pf0100.h b/board/toradex/apalis_imx6/pf0100.h
new file mode 100644
index 0000000..c84cab8
--- /dev/null
+++ b/board/toradex/apalis_imx6/pf0100.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Helpers for Freescale PMIC PF0100
+*/
+
+#ifndef PF0100_H_
+#define PF0100_H_
+
+/* 7-bit I2C bus slave address */
+#define PFUZE100_I2C_ADDR		(0x08)
+/* Register Addresses */
+#define PFUZE100_DEVICEID		(0x0)
+#define PFUZE100_REVID			(0x3)
+#define PFUZE100_SW1AMODE		(0x23)
+#define PFUZE100_SW1ACON		36
+#define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1ACON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1CCON		49
+#define PFUZE100_SW1CCON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1CCON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1AVOL		32
+#define PFUZE100_SW1AVOL_VSEL_M		(0x3f<<0)
+#define PFUZE100_SW1CVOL		46
+#define PFUZE100_SW1CVOL_VSEL_M		(0x3f<<0)
+#define PFUZE100_VGEN1CTL		(0x6c)
+#define PFUZE100_VGEN1_VAL		(0x30 + 0x08) /* Always ON, 1.2V */
+#define PFUZE100_SWBSTCTL		(0x66)
+/* Always ON, Auto Switching Mode, 5.0V */
+#define PFUZE100_SWBST_VAL		(0x40 + 0x08 + 0x00)
+
+/* chooses the extended page (registers 0x80..0xff) */
+#define PFUZE100_PAGE_REGISTER		0x7f
+#define PFUZE100_PAGE_REGISTER_PAGE_M	(0x1f << 0)
+#define PFUZE100_PAGE_REGISTER_PAGE1	(0x01 & PFUZE100_PAGE_REGISTER_PAGE_M)
+#define PFUZE100_PAGE_REGISTER_PAGE2	(0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
+
+/* extended page 1 */
+#define PFUZE100_FUSE_POR1		0xe4
+#define PFUZE100_FUSE_POR2		0xe5
+#define PFUZE100_FUSE_POR3		0xe6
+#define PFUZE100_FUSE_POR_M		(0x1 << 1)
+
+
+/* output some informational messages, return the number FUSE_POR=1 */
+/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
+unsigned pmic_init(void);
+
+/* programmes OTP fuses to values required on a Toradex Apalis iMX6 */
+int pf0100_prog(void);
+
+#endif /* PF0100_H_ */
diff --git a/board/toradex/apalis_imx6/pf0100_otp.inc b/board/toradex/apalis_imx6/pf0100_otp.inc
new file mode 100644
index 0000000..59e0587
--- /dev/null
+++ b/board/toradex/apalis_imx6/pf0100_otp.inc
@@ -0,0 +1,191 @@
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+// Register Output for PF0100 programmer
+// Customer: Toradex AG
+// Program: Apalis iMX6
+// Sample marking:
+// Date: 12.02.2014
+// Time: 17:16:41
+// Generated from Spreadsheet Revision: P1.8
+
+/* sed commands to get from programmer script to struct */
+/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp.txt > pf0100_otp.inc
+   sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
+   sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */
+
+enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
+struct pmic_otp_prog_t{
+	unsigned char cmd;
+	unsigned char reg;
+	unsigned short value;
+};
+
+struct pmic_otp_prog_t pmic_otp_prog[] = {
+{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1
+{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
+{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
+{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
+{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
+{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
+{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
+{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
+{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
+{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110
+{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111
+{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112
+{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114
+{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115
+{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116
+{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118
+{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120
+{pmic_i2c, 0xBD, 0x1F}, // Auto gen from Row123
+{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126
+{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130
+{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
+{pmic_i2c, 0xC9, 0x08}, // Auto gen from Row135
+{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
+{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
+{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142
+{pmic_i2c, 0xD1, 0x05}, // Auto gen from Row143
+{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
+{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
+{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
+{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154
+{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155
+{pmic_i2c, 0xE0, 0x07}, // Auto gen from Row158
+
+#if 0 /* TBB mode */
+{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1
+{pmic_delay, 0, 10},
+#else
+// Write OTP
+{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1
+{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1
+{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1
+{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register
+{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
+{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2
+{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
+{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST
+//VPGM:DOWN:n
+//VPGM:UP:n
+{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up
+//-----------------------------------------------------------------------------------
+// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
+//-----------------------------------------------------------------------------------
+// BANK 1
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 2
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 3
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 4
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 5
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 6
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 7
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 8
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 9
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 10
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+{pmic_vpgm, 0, 0}, // Turn off 8V SWBST
+{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off
+{pmic_i2c, 0xD0, 0x00}, // Clear
+{pmic_i2c, 0xD1, 0x00}, // Clear
+{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data
+{pmic_delay, 0, 500},
+{pmic_pwr, 0, 1},
+#endif
+};
\ No newline at end of file
diff --git a/board/toradex/apalis_t30/Kconfig b/board/toradex/apalis_t30/Kconfig
index f1dcda5..16224da 100644
--- a/board/toradex/apalis_t30/Kconfig
+++ b/board/toradex/apalis_t30/Kconfig
@@ -9,4 +9,22 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "apalis_t30"
 
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+source "board/toradex/common/Kconfig"
+
 endif
diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c
index 3f56971..827eefd 100644
--- a/board/toradex/apalis_t30/apalis_t30.c
+++ b/board/toradex/apalis_t30/apalis_t30.c
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2014
+ *  (C) Copyright 2014-2016
  *  Marcel Ziswiler <marcel@ziswiler.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -14,9 +14,12 @@
 #include <asm/io.h>
 #include <dm.h>
 #include <i2c.h>
+#include "../common/tdx-common.h"
 
 #include "pinmux-config-apalis_t30.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define PMU_I2C_ADDRESS		0x2D
 #define MAX_I2C_RETRY		3
 
@@ -29,6 +32,21 @@ int arch_misc_init(void)
 	return 0;
 }
 
+int checkboard(void)
+{
+	printf("Model: Toradex Apalis T30 %dGB\n",
+	       (gd->ram_size == 0x40000000) ? 1 : 2);
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
 /*
  * Routine: pinmux_init
  * Description: Do individual peripheral pinmux configs
diff --git a/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg
new file mode 100644
index 0000000..660f9d3
--- /dev/null
+++ b/board/toradex/colibri_imx6/800mhz_2x64mx16.cfg
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00301023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
+/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+/* DDR3 DATA BUS SIZE: 64BIT */
+/* DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 */
+/* DDR3 DATA BUS SIZE: 32BIT */
+DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000
+
+/* Write commands to DDR */
+/* Load Mode Registers */
+/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
+/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
+/* ZQ calibration */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
+
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218
+
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930
+
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D
+
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg b/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg
new file mode 100644
index 0000000..3bd8576
--- /dev/null
+++ b/board/toradex/colibri_imx6/800mhz_4x64mx16.cfg
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00301023
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
+/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+/* DDR3 DATA BUS SIZE: 64BIT */
+DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000
+/* DDR3 DATA BUS SIZE: 32BIT */
+/* DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 */
+
+/* Write commands to DDR */
+/* Load Mode Registers */
+/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
+/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
+/* ZQ calibration */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
+
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218
+
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930
+
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D
+
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
diff --git a/board/toradex/colibri_imx6/Kconfig b/board/toradex/colibri_imx6/Kconfig
new file mode 100644
index 0000000..d2ad1ce
--- /dev/null
+++ b/board/toradex/colibri_imx6/Kconfig
@@ -0,0 +1,44 @@
+if TARGET_COLIBRI_IMX6
+
+config SYS_BOARD
+	default "colibri_imx6"
+
+config SYS_CONFIG_NAME
+	default "colibri_imx6"
+
+config SYS_CPU
+	default "armv7"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_VENDOR
+	default "toradex"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+config TDX_CMD_IMX_MFGR
+	bool "Enable factory testing commands for Toradex iMX 6 modules"
+	help
+	  This adds the commands
+	    pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100
+	  If executed on already fused modules it doesn't change any fuse setting.
+	default y
+
+source "board/toradex/common/Kconfig"
+
+endif
diff --git a/board/toradex/colibri_imx6/MAINTAINERS b/board/toradex/colibri_imx6/MAINTAINERS
new file mode 100644
index 0000000..1cc7ef2
--- /dev/null
+++ b/board/toradex/colibri_imx6/MAINTAINERS
@@ -0,0 +1,8 @@
+Colibri iMX6
+M:	Max Krummenacher <max.krummenacher@toradex.com>
+W:	http://developer.toradex.com/software/linux/linux-software
+S:	Maintained
+F:	board/toradex/colibri_imx6/
+F:	include/configs/colibri_imx6.h
+F:	configs/colibri_imx6_defconfig
+F:	configs/colibri_imx6_nospl_defconfig
diff --git a/board/toradex/colibri_imx6/Makefile b/board/toradex/colibri_imx6/Makefile
new file mode 100644
index 0000000..c81bc2d
--- /dev/null
+++ b/board/toradex/colibri_imx6/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2012-2014 Toradex, Inc.
+# SPDX-License-Identifier:      GPL-2.0+
+
+obj-y  := colibri_imx6.o do_fuse.o
+obj-$(CONFIG_TDX_CMD_IMX_MFGR)  += pf0100.o
diff --git a/board/toradex/colibri_imx6/clocks.cfg b/board/toradex/colibri_imx6/clocks.cfg
new file mode 100644
index 0000000..be96094
--- /dev/null
+++ b/board/toradex/colibri_imx6/clocks.cfg
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1	   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
new file mode 100644
index 0000000..cbf7aa9
--- /dev/null
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -0,0 +1,1131 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ * Copyright (C) 2014-2016, Toradex AG
+ * copied from nitrogen6x
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/bootm.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
+#include <asm/io.h>
+#include <dm/platform_data/serial_mxc.h>
+#include <dm/platdata.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <imx_thermal.h>
+#include <linux/errno.h>
+#include <malloc.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+
+#include "../common/tdx-cfg-block.h"
+#ifdef CONFIG_TDX_CMD_IMX_MFGR
+#include "pf0100.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
+
+#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define WEAK_PULLUP	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_SRE_SLOW)
+
+#define NO_PULLUP	(					\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_SRE_SLOW)
+
+#define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
+
+#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
+
+#define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
+
+int dram_init(void)
+{
+	/* use the DDR controllers configured size */
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    (ulong)imx_ddr_size());
+
+	return 0;
+}
+
+/* Colibri UARTA */
+iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* Colibri I2C */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
+		.gp = IMX_GPIO_NR(1, 6)
+	}
+};
+
+/* Colibri local, PMIC, SGTL5000, STMPE811 */
+struct i2c_pads_info i2c_pad_info_loc = {
+	.scl = {
+		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
+		.gp = IMX_GPIO_NR(2, 30)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
+		.gp = IMX_GPIO_NR(3, 16)
+	}
+};
+
+/* Apalis MMC */
+iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+#	define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
+};
+
+/* eMMC */
+iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet_pads[] = {
+	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_RXD0__ENET_RX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_RXD1__ENET_RX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_RX_ER__ENET_RX_ER		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_TX_EN__ENET_TX_EN		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_TXD0__ENET_TX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_TXD1__ENET_TX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_CRS_DV__ENET_RX_EN		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_GPIO_16__ENET_REF_CLK		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
+/* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
+iomux_v3_cfg_t const gpio_pads[] = {
+	/* ADDRESS[17:18] [25] used as GPIO */
+	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_KEY_COL2__GPIO4_IO10	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_D1__GPIO2_IO01	| MUX_PAD_CTRL(WEAK_PULLUP),
+	/* ADDRESS[19:24] used as GPIO */
+	MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
+	/* DATA[16:29] [31]	 used as GPIO */
+	MX6_PAD_EIM_LBA__GPIO2_IO27	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_CS3__GPIO6_IO16	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_CS1__GPIO6_IO14	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_RB0__GPIO6_IO10	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_ALE__GPIO6_IO08	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_WP_B__GPIO6_IO09	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_CS0__GPIO6_IO11	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_CLE__GPIO6_IO07	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_GPIO_19__GPIO4_IO05	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_CSI0_MCLK__GPIO5_IO19	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_GPIO_5__GPIO1_IO05	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(WEAK_PULLUP),
+	/* DQM[0:3]	 used as GPIO */
+	MX6_PAD_EIM_EB0__GPIO2_IO28	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_EB1__GPIO2_IO29	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_SD2_DAT2__GPIO1_IO13	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_D0__GPIO2_IO00	| MUX_PAD_CTRL(WEAK_PULLUP),
+	/* RDY	used as GPIO */
+	MX6_PAD_EIM_WAIT__GPIO5_IO00	| MUX_PAD_CTRL(WEAK_PULLUP),
+	/* ADDRESS[16] DATA[30]	 used as GPIO */
+	MX6_PAD_KEY_ROW4__GPIO4_IO15	| MUX_PAD_CTRL(WEAK_PULLDOWN),
+	MX6_PAD_KEY_COL4__GPIO4_IO14	| MUX_PAD_CTRL(WEAK_PULLUP),
+	/* CSI pins used as GPIO */
+	MX6_PAD_EIM_A24__GPIO5_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_SD2_CMD__GPIO1_IO11	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_CS2__GPIO6_IO15	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_D18__GPIO3_IO18	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_A19__GPIO2_IO19	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_D29__GPIO3_IO29	| MUX_PAD_CTRL(WEAK_PULLDOWN),
+	MX6_PAD_EIM_A23__GPIO6_IO06	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_A20__GPIO2_IO18	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_A17__GPIO2_IO21	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_A18__GPIO2_IO20	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_EB3__GPIO2_IO31	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_D17__GPIO3_IO17	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_SD2_DAT0__GPIO1_IO15	| MUX_PAD_CTRL(WEAK_PULLUP),
+	/* GPIO */
+	MX6_PAD_EIM_D26__GPIO3_IO26	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_EIM_D27__GPIO3_IO27	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_D6__GPIO2_IO06	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_D3__GPIO2_IO03	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_DI0_PIN4__GPIO4_IO20	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_SD4_DAT3__GPIO2_IO11	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_NANDF_D4__GPIO2_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_SD4_DAT0__GPIO2_IO08	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_GPIO_7__GPIO1_IO07	| MUX_PAD_CTRL(WEAK_PULLUP),
+	MX6_PAD_GPIO_8__GPIO1_IO08	| MUX_PAD_CTRL(WEAK_PULLUP),
+	/* USBH_OC */
+	MX6_PAD_EIM_D30__GPIO3_IO30	| MUX_PAD_CTRL(WEAK_PULLUP),
+	/* USBC_ID */
+	MX6_PAD_NANDF_D2__GPIO2_IO02	| MUX_PAD_CTRL(WEAK_PULLUP),
+	/* USBC_DET */
+	MX6_PAD_GPIO_17__GPIO7_IO12	| MUX_PAD_CTRL(WEAK_PULLUP),
+};
+
+static void setup_iomux_gpio(void)
+{
+	imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
+}
+
+iomux_v3_cfg_t const usb_pads[] = {
+	/* USB_PE */
+	MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#	define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
+};
+
+/*
+ * UARTs are used in DTE mode, switch the mode on all UARTs before
+ * any pinmuxing connects a (DCE) output to a transceiver output.
+ */
+#define UFCR		0x90	/* FIFO Control Register */
+#define UFCR_DCEDTE	(1<<6)	/* DCE=0 */
+
+static void setup_dtemode_uart(void)
+{
+	setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
+	setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
+	setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
+}
+
+static void setup_iomux_uart(void)
+{
+	setup_dtemode_uart();
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	switch (port) {
+	case 0:
+		/* control OTG power */
+		/* No special PE for USBC, always on when ID pin signals
+		   host mode */
+		break;
+	case 1:
+		/* Control MXM USBH */
+		/* Set MXM USBH power enable, '0' means on */
+		gpio_direction_output(GPIO_USBH_EN, !on);
+		mdelay(100);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+/* use the following sequence: eMMC, MMC */
+struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+	{USDHC3_BASE_ADDR},
+	{USDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = true; /* default: assume inserted */
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		gpio_direction_input(GPIO_MMC_CD);
+		ret = !gpio_get_value(GPIO_MMC_CD);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifndef CONFIG_SPL_BUILD
+	s32 status = 0;
+	u32 index = 0;
+
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	usdhc_cfg[0].max_bus_width = 8;
+	usdhc_cfg[1].max_bus_width = 4;
+
+	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+		switch (index) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			break;
+		case 1:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
+			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return status;
+		}
+
+		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+	}
+
+	return status;
+#else
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned reg = readl(&psrc->sbmr1) >> 11;
+	/*
+	 * Upon reading BOOT_CFG register the following map is done:
+	 * Bit 11 and 12 of BOOT_CFG register can determine the current
+	 * mmc port
+	 * 0x1                  SD1
+	 * 0x2                  SD2
+	 * 0x3                  SD4
+	 */
+
+	switch (reg & 0x3) {
+	case 0x0:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	case 0x2:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+		break;
+	default:
+		puts("MMC boot device not available");
+	}
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+#endif
+}
+#endif
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	uint32_t base = IMX_FEC_BASE;
+	struct mii_dev *bus = NULL;
+	struct phy_device *phydev = NULL;
+	int ret;
+
+	/* provide the PHY clock from the i.MX 6 */
+	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+	if (ret)
+		return ret;
+	/* set gpr1[ENET_CLK_SEL] */
+	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
+	setup_iomux_enet();
+
+#ifdef CONFIG_FEC_MXC
+	bus = fec_get_miibus(base, -1);
+	if (!bus)
+		return 0;
+	/* scan PHY 1..7 */
+	phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
+	if (!phydev) {
+		free(bus);
+		puts("no PHY found\n");
+		return 0;
+	}
+	phy_reset(phydev);
+	printf("using PHY at %d\n", phydev->addr);
+	ret = fec_probe(bis, -1, base, bus, phydev);
+	if (ret) {
+		printf("FEC MXC: %s:failed\n", __func__);
+		free(phydev);
+		free(bus);
+	}
+#endif
+	return 0;
+}
+
+static iomux_v3_cfg_t const pwr_intb_pads[] = {
+	/*
+	 * the bootrom sets the iomux to vselect, potentially connecting
+	 * two outputs. Set this back to GPIO
+	 */
+	MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static iomux_v3_cfg_t const backlight_pads[] = {
+	/* Backlight On */
+	MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
+	/* Backlight PWM, used as GPIO in U-Boot */
+	MX6_PAD_EIM_A22__GPIO2_IO16  | MUX_PAD_CTRL(NO_PULLUP),
+	MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
+};
+
+static iomux_v3_cfg_t const rgb_pads[] = {
+	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
+	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
+};
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+	imx_iomux_v3_setup_multiple_pads(
+		rgb_pads,
+		ARRAY_SIZE(rgb_pads));
+	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
+}
+
+static int detect_default(struct display_info_t const *dev)
+{
+	(void) dev;
+	return 1;
+}
+
+struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB666,
+	.detect	= detect_default,
+	.enable	= enable_rgb,
+	.mode	= {
+		.name           = "vga-rgb",
+		.refresh        = 60,
+		.xres           = 640,
+		.yres           = 480,
+		.pixclock       = 33000,
+		.left_margin    = 48,
+		.right_margin   = 16,
+		.upper_margin   = 31,
+		.lower_margin   = 11,
+		.hsync_len      = 96,
+		.vsync_len      = 2,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB666,
+	.enable	= enable_rgb,
+	.mode	= {
+		.name           = "wvga-rgb",
+		.refresh        = 60,
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 25000,
+		.left_margin    = 40,
+		.right_margin   = 88,
+		.upper_margin   = 33,
+		.lower_margin   = 10,
+		.hsync_len      = 128,
+		.vsync_len      = 2,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+	/* Turn on LDB0,IPU,IPU DI0 clocks */
+	reg = __raw_readl(&mxc_ccm->CCGR3);
+	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* set LDB0, LDB1 clk select to 011/011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+		 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+	      |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+	     |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+	     |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+	     |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+	     |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+	     |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+	     |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+	     |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+	     |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+
+	reg = readl(&iomux->gpr[3]);
+	reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
+			|IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+	       <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+	writel(reg, &iomux->gpr[3]);
+
+	/* backlight unconditionally on for now */
+	imx_iomux_v3_setup_multiple_pads(backlight_pads,
+					 ARRAY_SIZE(backlight_pads));
+	/* use 0 for EDT 7", use 1 for LG fullHD panel */
+	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
+	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+}
+#endif /* defined(CONFIG_VIDEO_IPUV3) */
+
+int board_early_init_f(void)
+{
+	imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
+					 ARRAY_SIZE(pwr_intb_pads));
+	setup_iomux_uart();
+
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
+
+#ifdef CONFIG_TDX_CMD_IMX_MFGR
+	(void) pmic_init();
+#endif
+
+#ifdef CONFIG_SATA
+	setup_sata();
+#endif
+
+	setup_iomux_gpio();
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#if defined(CONFIG_REVISION_TAG) && \
+    defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+	char env_str[256];
+	u32 rev;
+
+	rev = get_board_rev();
+	snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
+	setenv("board_rev", env_str);
+#endif
+
+	return 0;
+}
+#endif /* CONFIG_BOARD_LATE_INIT */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
+int ft_system_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	char it[] = " IT";
+	int minc, maxc;
+
+	switch (get_cpu_temp_grade(&minc, &maxc)) {
+	case TEMP_AUTOMOTIVE:
+	case TEMP_INDUSTRIAL:
+		break;
+	case TEMP_EXTCOMMERCIAL:
+	default:
+		it[0] = 0;
+	};
+	printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
+	       is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
+	       (gd->ram_size == 0x20000000) ? "512" : "256", it);
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	{"mmc",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+	{NULL,	0},
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+/* TODO, use external pmic, for now always ldo_enable */
+void ldo_mode_set(int ldo_bypass)
+{
+	return;
+}
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <libfdt.h>
+#include "asm/arch/mx6dl-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+static int mx6s_dcd_table[] = {
+/* ddr-setup.cfg */
+
+MX6_IOM_DRAM_SDQS0, 0x00000030,
+MX6_IOM_DRAM_SDQS1, 0x00000030,
+MX6_IOM_DRAM_SDQS2, 0x00000030,
+MX6_IOM_DRAM_SDQS3, 0x00000030,
+MX6_IOM_DRAM_SDQS4, 0x00000030,
+MX6_IOM_DRAM_SDQS5, 0x00000030,
+MX6_IOM_DRAM_SDQS6, 0x00000030,
+MX6_IOM_DRAM_SDQS7, 0x00000030,
+
+MX6_IOM_GRP_B0DS, 0x00000030,
+MX6_IOM_GRP_B1DS, 0x00000030,
+MX6_IOM_GRP_B2DS, 0x00000030,
+MX6_IOM_GRP_B3DS, 0x00000030,
+MX6_IOM_GRP_B4DS, 0x00000030,
+MX6_IOM_GRP_B5DS, 0x00000030,
+MX6_IOM_GRP_B6DS, 0x00000030,
+MX6_IOM_GRP_B7DS, 0x00000030,
+MX6_IOM_GRP_ADDDS, 0x00000030,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_CTLDS, 0x00000030,
+
+MX6_IOM_DRAM_DQM0, 0x00020030,
+MX6_IOM_DRAM_DQM1, 0x00020030,
+MX6_IOM_DRAM_DQM2, 0x00020030,
+MX6_IOM_DRAM_DQM3, 0x00020030,
+MX6_IOM_DRAM_DQM4, 0x00020030,
+MX6_IOM_DRAM_DQM5, 0x00020030,
+MX6_IOM_DRAM_DQM6, 0x00020030,
+MX6_IOM_DRAM_DQM7, 0x00020030,
+
+MX6_IOM_DRAM_CAS, 0x00020030,
+MX6_IOM_DRAM_RAS, 0x00020030,
+MX6_IOM_DRAM_SDCLK_0, 0x00020030,
+MX6_IOM_DRAM_SDCLK_1, 0x00020030,
+
+MX6_IOM_DRAM_RESET, 0x00020030,
+MX6_IOM_DRAM_SDCKE0, 0x00003000,
+MX6_IOM_DRAM_SDCKE1, 0x00003000,
+
+MX6_IOM_DRAM_SDODT0, 0x00003030,
+MX6_IOM_DRAM_SDODT1, 0x00003030,
+
+/* (differential input) */
+MX6_IOM_DDRMODE_CTL, 0x00020000,
+/* (differential input) */
+MX6_IOM_GRP_DDRMODE, 0x00020000,
+/* disable ddr pullups */
+MX6_IOM_GRP_DDRPKE, 0x00000000,
+MX6_IOM_DRAM_SDBA2, 0x00000000,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
+
+/* Read data DQ Byte0-3 delay */
+MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
+
+/*
+ * MDMISC	mirroring	interleaved (row/bank/col)
+ */
+/* TODO: check what the RALAT field does */
+MX6_MMDC_P0_MDMISC, 0x00081740,
+
+/*
+ * MDSCR	con_req
+ */
+MX6_MMDC_P0_MDSCR, 0x00008000,
+
+
+/* 800mhz_2x64mx16.cfg */
+
+MX6_MMDC_P0_MDPDC, 0x0002002D,
+MX6_MMDC_P0_MDCFG0, 0x2C305503,
+MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
+MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
+MX6_MMDC_P0_MDRWD, 0x000026D2,
+MX6_MMDC_P0_MDOR, 0x00301023,
+MX6_MMDC_P0_MDOTC, 0x00333030,
+MX6_MMDC_P0_MDPDC, 0x0002556D,
+/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
+MX6_MMDC_P0_MDASP, 0x00000017,
+/* DDR3 DATA BUS SIZE: 64BIT */
+/* MX6_MMDC_P0_MDCTL, 0x821A0000, */
+/* DDR3 DATA BUS SIZE: 32BIT */
+MX6_MMDC_P0_MDCTL, 0x82190000,
+
+/* Write commands to DDR */
+/* Load Mode Registers */
+/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
+/* MX6_MMDC_P0_MDSCR, 0x04408032, */
+MX6_MMDC_P0_MDSCR, 0x04008032,
+MX6_MMDC_P0_MDSCR, 0x00008033,
+MX6_MMDC_P0_MDSCR, 0x00048031,
+MX6_MMDC_P0_MDSCR, 0x13208030,
+/* ZQ calibration */
+MX6_MMDC_P0_MDSCR, 0x04008040,
+
+MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P0_MDREF, 0x00005800,
+
+MX6_MMDC_P0_MPODTCTRL, 0x00000000,
+MX6_MMDC_P1_MPODTCTRL, 0x00000000,
+
+MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
+MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
+MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
+MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
+
+MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
+MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
+MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
+MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
+
+MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
+MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
+MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
+MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
+
+MX6_MMDC_P0_MPMUR0, 0x00000800,
+MX6_MMDC_P1_MPMUR0, 0x00000800,
+MX6_MMDC_P0_MDSCR, 0x00000000,
+MX6_MMDC_P0_MAPSR, 0x00011006,
+};
+
+static int mx6dl_dcd_table[] = {
+/* ddr-setup.cfg */
+
+MX6_IOM_DRAM_SDQS0, 0x00000030,
+MX6_IOM_DRAM_SDQS1, 0x00000030,
+MX6_IOM_DRAM_SDQS2, 0x00000030,
+MX6_IOM_DRAM_SDQS3, 0x00000030,
+MX6_IOM_DRAM_SDQS4, 0x00000030,
+MX6_IOM_DRAM_SDQS5, 0x00000030,
+MX6_IOM_DRAM_SDQS6, 0x00000030,
+MX6_IOM_DRAM_SDQS7, 0x00000030,
+
+MX6_IOM_GRP_B0DS, 0x00000030,
+MX6_IOM_GRP_B1DS, 0x00000030,
+MX6_IOM_GRP_B2DS, 0x00000030,
+MX6_IOM_GRP_B3DS, 0x00000030,
+MX6_IOM_GRP_B4DS, 0x00000030,
+MX6_IOM_GRP_B5DS, 0x00000030,
+MX6_IOM_GRP_B6DS, 0x00000030,
+MX6_IOM_GRP_B7DS, 0x00000030,
+MX6_IOM_GRP_ADDDS, 0x00000030,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_CTLDS, 0x00000030,
+
+MX6_IOM_DRAM_DQM0, 0x00020030,
+MX6_IOM_DRAM_DQM1, 0x00020030,
+MX6_IOM_DRAM_DQM2, 0x00020030,
+MX6_IOM_DRAM_DQM3, 0x00020030,
+MX6_IOM_DRAM_DQM4, 0x00020030,
+MX6_IOM_DRAM_DQM5, 0x00020030,
+MX6_IOM_DRAM_DQM6, 0x00020030,
+MX6_IOM_DRAM_DQM7, 0x00020030,
+
+MX6_IOM_DRAM_CAS, 0x00020030,
+MX6_IOM_DRAM_RAS, 0x00020030,
+MX6_IOM_DRAM_SDCLK_0, 0x00020030,
+MX6_IOM_DRAM_SDCLK_1, 0x00020030,
+
+MX6_IOM_DRAM_RESET, 0x00020030,
+MX6_IOM_DRAM_SDCKE0, 0x00003000,
+MX6_IOM_DRAM_SDCKE1, 0x00003000,
+
+MX6_IOM_DRAM_SDODT0, 0x00003030,
+MX6_IOM_DRAM_SDODT1, 0x00003030,
+
+/* (differential input) */
+MX6_IOM_DDRMODE_CTL, 0x00020000,
+/* (differential input) */
+MX6_IOM_GRP_DDRMODE, 0x00020000,
+/* disable ddr pullups */
+MX6_IOM_GRP_DDRPKE, 0x00000000,
+MX6_IOM_DRAM_SDBA2, 0x00000000,
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
+
+/* Read data DQ Byte0-3 delay */
+MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
+MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
+
+/*
+ * MDMISC	mirroring	interleaved (row/bank/col)
+ */
+/* TODO: check what the RALAT field does */
+MX6_MMDC_P0_MDMISC, 0x00081740,
+
+/*
+ * MDSCR	con_req
+ */
+MX6_MMDC_P0_MDSCR, 0x00008000,
+
+
+/* 800mhz_2x64mx16.cfg */
+
+MX6_MMDC_P0_MDPDC, 0x0002002D,
+MX6_MMDC_P0_MDCFG0, 0x2C305503,
+MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
+MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
+MX6_MMDC_P0_MDRWD, 0x000026D2,
+MX6_MMDC_P0_MDOR, 0x00301023,
+MX6_MMDC_P0_MDOTC, 0x00333030,
+MX6_MMDC_P0_MDPDC, 0x0002556D,
+/* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
+MX6_MMDC_P0_MDASP, 0x00000017,
+/* DDR3 DATA BUS SIZE: 64BIT */
+MX6_MMDC_P0_MDCTL, 0x821A0000,
+/* DDR3 DATA BUS SIZE: 32BIT */
+/* MX6_MMDC_P0_MDCTL, 0x82190000, */
+
+/* Write commands to DDR */
+/* Load Mode Registers */
+/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
+/* MX6_MMDC_P0_MDSCR, 0x04408032, */
+MX6_MMDC_P0_MDSCR, 0x04008032,
+MX6_MMDC_P0_MDSCR, 0x00008033,
+MX6_MMDC_P0_MDSCR, 0x00048031,
+MX6_MMDC_P0_MDSCR, 0x13208030,
+/* ZQ calibration */
+MX6_MMDC_P0_MDSCR, 0x04008040,
+
+MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
+MX6_MMDC_P0_MDREF, 0x00005800,
+
+MX6_MMDC_P0_MPODTCTRL, 0x00000000,
+MX6_MMDC_P1_MPODTCTRL, 0x00000000,
+
+MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
+MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
+MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
+MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
+
+MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
+MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
+MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
+MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
+
+MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
+MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
+MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
+MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
+
+MX6_MMDC_P0_MPMUR0, 0x00000800,
+MX6_MMDC_P1_MPMUR0, 0x00000800,
+MX6_MMDC_P0_MDSCR, 0x00000000,
+MX6_MMDC_P0_MAPSR, 0x00011006,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFFFF3, &ccm->CCGR2);
+	writel(0x3FF0300F, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000F3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1	   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+	writel(0x000000FB, &ccm->ccosr);
+}
+
+static void gpr_init(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* enable AXI cache for VDOA/VPU/IPU */
+	writel(0xF00000CF, &iomux->gpr[4]);
+	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+	writel(0x007F007F, &iomux->gpr[6]);
+	writel(0x007F007F, &iomux->gpr[7]);
+}
+
+static void ddr_init(int *table, int size)
+{
+	int i;
+
+	for (i = 0; i < size / 2 ; i++)
+		writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+	int minc, maxc;
+
+	switch (get_cpu_temp_grade(&minc, &maxc)) {
+	case TEMP_COMMERCIAL:
+	case TEMP_EXTCOMMERCIAL:
+		if (is_cpu_type(MXC_CPU_MX6DL)) {
+			puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
+			ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
+		} else {
+			puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
+			ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
+		}
+		break;
+	case TEMP_INDUSTRIAL:
+	case TEMP_AUTOMOTIVE:
+	default:
+		if (is_cpu_type(MXC_CPU_MX6DL)) {
+			ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
+		} else {
+			puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
+			ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
+		}
+		break;
+	};
+	udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* iomux and setup of i2c */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* Make sure we use dte mode */
+	setup_dtemode_uart();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
+
+#endif
+
+static struct mxc_serial_platdata mxc_serial_plat = {
+	.reg = (struct mxc_uart *)UART1_BASE,
+	.use_dte = true,
+};
+
+U_BOOT_DEVICE(mxc_serial) = {
+	.name = "serial_mxc",
+	.platdata = &mxc_serial_plat,
+};
diff --git a/board/toradex/colibri_imx6/colibri_imx6.cfg b/board/toradex/colibri_imx6/colibri_imx6.cfg
new file mode 100644
index 0000000..e7886de
--- /dev/null
+++ b/board/toradex/colibri_imx6/colibri_imx6.cfg
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014 Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+
+#if CONFIG_DDR_MB == 256
+#include "800mhz_2x64mx16.cfg"
+#elif CONFIG_DDR_MB == 512
+#include "800mhz_4x64mx16.cfg"
+#else
+#error "unknown DDR size"
+#endif
+
+#include "clocks.cfg"
diff --git a/board/toradex/colibri_imx6/ddr-setup.cfg b/board/toradex/colibri_imx6/ddr-setup.cfg
new file mode 100644
index 0000000..f46ae55
--- /dev/null
+++ b/board/toradex/colibri_imx6/ddr-setup.cfg
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+
+/*
+ * DDR3 settings
+ * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
+ *	   memory bus width: 64 bits	x16/x32/x64
+ * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 64 bits	x16/x32/x64
+ * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
+ *	   memory bus width: 32 bits	x16/x32
+ */
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
+
+DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+
+/* (differential input) */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+/* (differential input) */
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+/* disable ddr pullups */
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+
+/* Read data DQ Byte0-3 delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+/*
+ * MDMISC	mirroring	interleaved (row/bank/col)
+ */
+/* TODO: check what the RALAT field does */
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
+
+/*
+ * MDSCR	con_req
+ */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
diff --git a/board/toradex/colibri_imx6/do_fuse.c b/board/toradex/colibri_imx6/do_fuse.c
new file mode 100644
index 0000000..cff07e9
--- /dev/null
+++ b/board/toradex/colibri_imx6/do_fuse.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Helpers for i.MX OTP fusing during module production
+*/
+
+#include <common.h>
+#ifndef CONFIG_SPL_BUILD
+#include <console.h>
+#include <fuse.h>
+
+static int mfgr_fuse(void)
+{
+	unsigned val, val6;
+
+	fuse_sense(0, 5, &val);
+	printf("Fuse 0, 5: %8x\n", val);
+	fuse_sense(0, 6, &val6);
+	printf("Fuse 0, 6: %8x\n", val6);
+	fuse_sense(4, 3, &val);
+	printf("Fuse 4, 3: %8x\n", val);
+	fuse_sense(4, 2, &val);
+	printf("Fuse 4, 2: %8x\n", val);
+	if (val6 & 0x10) {
+		puts("BT_FUSE_SEL already fused, will do nothing\n");
+		return CMD_RET_FAILURE;
+	}
+	/* boot cfg */
+	fuse_prog(0, 5, 0x00005072);
+	/* BT_FUSE_SEL */
+	fuse_prog(0, 6, 0x00000010);
+	return CMD_RET_SUCCESS;
+}
+
+int do_mfgr_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
+		char * const argv[])
+{
+	int ret;
+	puts("Fusing...\n");
+	ret = mfgr_fuse();
+	if (ret == CMD_RET_SUCCESS)
+		puts("done.\n");
+	else
+		puts("failed.\n");
+	return ret;
+}
+
+int do_updt_fuse(cmd_tbl_t *cmdtp, int flag, int argc,
+		char * const argv[])
+{
+	unsigned val;
+	int ret;
+	int confirmed = argc >= 1 && !strcmp(argv[1], "-y");
+
+	/* can be used in scripts for command availability check */
+	if (argc >= 1 && !strcmp(argv[1], "-n"))
+		return CMD_RET_SUCCESS;
+
+	/* boot cfg */
+	fuse_sense(0, 5, &val);
+	printf("Fuse 0, 5: %8x\n", val);
+	if (val & 0x10) {
+		puts("Fast boot mode already fused, no need to fuse\n");
+		return CMD_RET_SUCCESS;
+	}
+	if (!confirmed) {
+		puts("Warning: Programming fuses is an irreversible operation!\n"
+				"         Updating to fast boot mode prevents easy\n"
+				"         downgrading to previous BSP versions.\n"
+				"\nReally perform this fuse programming? <y/N>\n");
+		if (!confirm_yesno())
+			return CMD_RET_FAILURE;
+	}
+	puts("Fusing fast boot mode...\n");
+	ret = fuse_prog(0, 5, 0x00005072);
+	if (ret == CMD_RET_SUCCESS)
+		puts("done.\n");
+	else
+		puts("failed.\n");
+	return ret;
+}
+
+U_BOOT_CMD(
+	mfgr_fuse, 1, 0, do_mfgr_fuse,
+	"OTP fusing during module production",
+	""
+);
+
+U_BOOT_CMD(
+	updt_fuse, 2, 0, do_updt_fuse,
+	"OTP fusing during module update",
+	"updt_fuse [-n] [-y] - boot cfg fast boot mode fusing"
+);
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/toradex/colibri_imx6/pf0100.c b/board/toradex/colibri_imx6/pf0100.c
new file mode 100644
index 0000000..6889287
--- /dev/null
+++ b/board/toradex/colibri_imx6/pf0100.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Helpers for Freescale PMIC PF0100
+*/
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+
+#include "pf0100_otp.inc"
+#include "pf0100.h"
+
+/* define for PMIC register dump */
+/*#define DEBUG */
+
+/* use GPIO: EXT_IO1 to switch on VPGM, ON: 1 */
+static iomux_v3_cfg_t const pmic_prog_pads[] = {
+	MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#	define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 3)
+};
+
+unsigned pmic_init(void)
+{
+	unsigned programmed = 0;
+	uchar bus = 1;
+	uchar devid, revid, val;
+
+	puts("PMIC: ");
+	if (!((0 == i2c_set_bus_num(bus)) &&
+	      (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
+		puts("i2c bus failed\n");
+		return 0;
+	}
+	/* get device ident */
+	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_DEVICEID, 1, &devid, 1) < 0) {
+		puts("i2c pmic devid read failed\n");
+		return 0;
+	}
+	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_REVID, 1, &revid, 1) < 0) {
+		puts("i2c pmic revid read failed\n");
+		return 0;
+	}
+	printf("device id: 0x%.2x, revision id: 0x%.2x\n", devid, revid);
+
+#ifdef DEBUG
+	{
+		unsigned i, j;
+
+		for (i = 0; i < 16; i++)
+			printf("\t%x", i);
+		for (j = 0; j < 0x80; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\nEXT Page 1");
+
+		val = PFUZE100_PAGE_REGISTER_PAGE1;
+		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
+			      &val, 1)) {
+			puts("i2c write failed\n");
+			return 0;
+		}
+
+		for (j = 0x80; j < 0x100; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\nEXT Page 2");
+
+		val = PFUZE100_PAGE_REGISTER_PAGE2;
+		if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1,
+			      &val, 1)) {
+			puts("i2c write failed\n");
+			return 0;
+		}
+
+		for (j = 0x80; j < 0x100; ) {
+			printf("\n%2x", j);
+			for (i = 0; i < 16; i++) {
+				i2c_read(PFUZE100_I2C_ADDR, j+i, 1, &val, 1);
+				printf("\t%2x", val);
+			}
+			j += 0x10;
+		}
+		printf("\n");
+	}
+#endif
+	/* get device programmed state */
+	val = PFUZE100_PAGE_REGISTER_PAGE1;
+	if (i2c_write(PFUZE100_I2C_ADDR, PFUZE100_PAGE_REGISTER, 1, &val, 1)) {
+		puts("i2c write failed\n");
+		return 0;
+	}
+	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR1, 1, &val, 1) < 0) {
+		puts("i2c fuse_por read failed\n");
+		return 0;
+	}
+	if (val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR2, 1, &val, 1) < 0) {
+		puts("i2c fuse_por read failed\n");
+		return programmed;
+	}
+	if (val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	if (i2c_read(PFUZE100_I2C_ADDR, PFUZE100_FUSE_POR3, 1, &val, 1) < 0) {
+		puts("i2c fuse_por read failed\n");
+		return programmed;
+	}
+	if (val & PFUZE100_FUSE_POR_M)
+		programmed++;
+
+	switch (programmed) {
+	case 0:
+		printf("PMIC: not programmed\n");
+		break;
+	case 3:
+		printf("PMIC: programmed\n");
+		break;
+	default:
+		printf("PMIC: undefined programming state\n");
+		break;
+	}
+
+	return programmed;
+}
+
+int pf0100_prog(void)
+{
+	unsigned char bus = 1;
+	unsigned char val;
+	unsigned int i;
+
+	if (pmic_init() == 3) {
+		puts("PMIC already programmed, exiting\n");
+		return CMD_RET_FAILURE;
+	}
+	/* set up gpio to manipulate vprog, initially off */
+	imx_iomux_v3_setup_multiple_pads(pmic_prog_pads,
+					 ARRAY_SIZE(pmic_prog_pads));
+	gpio_direction_output(PMIC_PROG_VOLTAGE, 0);
+
+	if (!((0 == i2c_set_bus_num(bus)) &&
+	      (0 == i2c_probe(PFUZE100_I2C_ADDR)))) {
+		puts("i2c bus failed\n");
+		return CMD_RET_FAILURE;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(pmic_otp_prog); i++) {
+		switch (pmic_otp_prog[i].cmd) {
+		case pmic_i2c:
+			val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
+			if (i2c_write(PFUZE100_I2C_ADDR, pmic_otp_prog[i].reg,
+				      1, &val, 1)) {
+				printf("i2c write failed, reg 0x%2x, value 0x%2x\n",
+				       pmic_otp_prog[i].reg, val);
+				return CMD_RET_FAILURE;
+			}
+			break;
+		case pmic_delay:
+			udelay(pmic_otp_prog[i].value * 1000);
+			break;
+		case pmic_vpgm:
+			gpio_direction_output(PMIC_PROG_VOLTAGE,
+					      pmic_otp_prog[i].value);
+			break;
+		case pmic_pwr:
+			/* TODO */
+			break;
+		}
+	}
+	return CMD_RET_SUCCESS;
+}
+
+int do_pf0100_prog(cmd_tbl_t *cmdtp, int flag, int argc,
+		char * const argv[])
+{
+	int ret;
+	puts("Programming PMIC OTP...");
+	ret = pf0100_prog();
+	if (ret == CMD_RET_SUCCESS)
+		puts("done.\n");
+	else
+		puts("failed.\n");
+	return ret;
+}
+
+U_BOOT_CMD(
+	pf0100_otp_prog, 1, 0, do_pf0100_prog,
+	"Program the OTP fuses on the PMIC PF0100",
+	""
+);
diff --git a/board/toradex/colibri_imx6/pf0100.h b/board/toradex/colibri_imx6/pf0100.h
new file mode 100644
index 0000000..c84cab8
--- /dev/null
+++ b/board/toradex/colibri_imx6/pf0100.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Helpers for Freescale PMIC PF0100
+*/
+
+#ifndef PF0100_H_
+#define PF0100_H_
+
+/* 7-bit I2C bus slave address */
+#define PFUZE100_I2C_ADDR		(0x08)
+/* Register Addresses */
+#define PFUZE100_DEVICEID		(0x0)
+#define PFUZE100_REVID			(0x3)
+#define PFUZE100_SW1AMODE		(0x23)
+#define PFUZE100_SW1ACON		36
+#define PFUZE100_SW1ACON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1ACON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1CCON		49
+#define PFUZE100_SW1CCON_SPEED_VAL	(0x1<<6)	/*default */
+#define PFUZE100_SW1CCON_SPEED_M	(0x3<<6)
+#define PFUZE100_SW1AVOL		32
+#define PFUZE100_SW1AVOL_VSEL_M		(0x3f<<0)
+#define PFUZE100_SW1CVOL		46
+#define PFUZE100_SW1CVOL_VSEL_M		(0x3f<<0)
+#define PFUZE100_VGEN1CTL		(0x6c)
+#define PFUZE100_VGEN1_VAL		(0x30 + 0x08) /* Always ON, 1.2V */
+#define PFUZE100_SWBSTCTL		(0x66)
+/* Always ON, Auto Switching Mode, 5.0V */
+#define PFUZE100_SWBST_VAL		(0x40 + 0x08 + 0x00)
+
+/* chooses the extended page (registers 0x80..0xff) */
+#define PFUZE100_PAGE_REGISTER		0x7f
+#define PFUZE100_PAGE_REGISTER_PAGE_M	(0x1f << 0)
+#define PFUZE100_PAGE_REGISTER_PAGE1	(0x01 & PFUZE100_PAGE_REGISTER_PAGE_M)
+#define PFUZE100_PAGE_REGISTER_PAGE2	(0x02 & PFUZE100_PAGE_REGISTER_PAGE_M)
+
+/* extended page 1 */
+#define PFUZE100_FUSE_POR1		0xe4
+#define PFUZE100_FUSE_POR2		0xe5
+#define PFUZE100_FUSE_POR3		0xe6
+#define PFUZE100_FUSE_POR_M		(0x1 << 1)
+
+
+/* output some informational messages, return the number FUSE_POR=1 */
+/* i.e. 0: unprogrammed, 3: programmed, other: undefined prog. state */
+unsigned pmic_init(void);
+
+/* programmes OTP fuses to values required on a Toradex Apalis iMX6 */
+int pf0100_prog(void);
+
+#endif /* PF0100_H_ */
diff --git a/board/toradex/colibri_imx6/pf0100_otp.inc b/board/toradex/colibri_imx6/pf0100_otp.inc
new file mode 100644
index 0000000..255392b
--- /dev/null
+++ b/board/toradex/colibri_imx6/pf0100_otp.inc
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2014-2016, Toradex AG
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+// Register Output for PF0100 programmer
+// Customer: Toradex AG
+// Program: Colibri iMX6
+// Sample marking:
+// Date: 24.07.2015
+// Time: 10:52:58
+// Generated from Spreadsheet Revision: P1.8
+
+/* sed commands to get from programmer script to struct */
+/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp_Colibri_iMX6.txt > pf0100_otp.inc
+   sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
+   sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */
+
+enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
+struct pmic_otp_prog_t{
+	unsigned char cmd;
+	unsigned char reg;
+	unsigned short value;
+};
+
+struct pmic_otp_prog_t pmic_otp_prog[] = {
+{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1
+{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
+{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
+{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
+{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
+{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
+{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
+{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
+{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
+{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110
+{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111
+{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112
+{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114
+{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115
+{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116
+{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118
+{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120
+{pmic_i2c, 0xBD, 0x0E}, // Auto gen from Row123
+{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126
+{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130
+{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
+{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
+{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
+{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142
+{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
+{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
+{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
+{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154
+{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155
+{pmic_i2c, 0xE0, 0x05}, // Auto gen from Row158
+
+#if 0 /* TBB mode */
+{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1
+{pmic_delay, 0, 10},
+#else
+// Write OTP
+{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1
+{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1
+{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1
+{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register
+{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
+{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2
+{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
+{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST
+//VPGM:DOWN:n
+//VPGM:UP:n
+{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up
+//-----------------------------------------------------------------------------------
+// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
+//-----------------------------------------------------------------------------------
+// BANK 1
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
+{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 2
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
+{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 3
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
+{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 4
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
+{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 5
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
+{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 6
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
+{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 7
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
+{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 8
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
+{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 9
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
+{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+// BANK 10
+//-----------------------------------------------------------------------------------
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
+{pmic_delay, 0, 10}, // Allow time for bank programming to complete
+{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
+{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
+//-----------------------------------------------------------------------------------
+{pmic_vpgm, 0, 0}, // Turn off 8V SWBST
+{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off
+{pmic_i2c, 0xD0, 0x00}, // Clear
+{pmic_i2c, 0xD1, 0x00}, // Clear
+{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data
+{pmic_delay, 0, 500},
+{pmic_pwr, 0, 1},
+#endif
+};
\ No newline at end of file
diff --git a/board/toradex/colibri_imx7/Kconfig b/board/toradex/colibri_imx7/Kconfig
index 7bba26b..414a600 100644
--- a/board/toradex/colibri_imx7/Kconfig
+++ b/board/toradex/colibri_imx7/Kconfig
@@ -16,5 +16,21 @@ config COLIBRI_IMX7_EXT_PHYCLK
 	  clock source.
 	default y
 
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_NAND
+	default y
+
+config TDX_CFG_BLOCK_OFFSET
+	default "2048"
+
+config TDX_CFG_BLOCK_OFFSET2
+	default "133120"
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+	default y
+
+source "board/toradex/common/Kconfig"
 
 endif
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c
index 8eedd65..5cb14b4 100644
--- a/board/toradex/colibri_imx7/colibri_imx7.c
+++ b/board/toradex/colibri_imx7/colibri_imx7.c
@@ -10,20 +10,25 @@
 #include <asm/arch/mx7-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
 #include <asm/io.h>
 #include <common.h>
 #include <dm.h>
 #include <dm/platform_data/serial_mxc.h>
+#include <fdt_support.h>
 #include <fsl_esdhc.h>
-#include <i2c.h>
+#include <jffs2/load_kernel.h>
 #include <linux/sizes.h>
 #include <mmc.h>
 #include <miiphy.h>
+#include <mtd_node.h>
 #include <netdev.h>
+#include <power/pmic.h>
+#include <power/rn5t567_pmic.h>
+#include <usb.h>
 #include <usb/ehci-ci.h>
+#include "../common/tdx-common.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -38,9 +43,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
 
-#define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
-	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
-
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
 	PAD_CTL_DSE_3P3V_49OHM)
 
@@ -48,35 +50,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
 
-#ifdef CONFIG_SYS_I2C_MXC
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-/* I2C1 for PMIC */
-static struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX7D_PAD_GPIO1_IO04__I2C1_SCL | PC,
-		.gpio_mode = MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | PC,
-		.gp = IMX_GPIO_NR(1, 4),
-	},
-	.sda = {
-		.i2c_mode = MX7D_PAD_GPIO1_IO05__I2C1_SDA | PC,
-		.gpio_mode = MX7D_PAD_GPIO1_IO05__GPIO1_IO5 | PC,
-		.gp = IMX_GPIO_NR(1, 5),
-	},
-};
-/* I2C4 for Colibri I2C */
-static struct i2c_pads_info i2c_pad_info4 = {
-	.scl = {
-		.i2c_mode = MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL | PC,
-		.gpio_mode = MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 | PC,
-		.gp = IMX_GPIO_NR(7, 8),
-	},
-	.sda = {
-		.i2c_mode = MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA | PC,
-		.gpio_mode = MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 | PC,
-		.gp = IMX_GPIO_NR(7, 9),
-	},
-};
-#endif
+#define USB_CDET_GPIO	IMX_GPIO_NR(7, 14)
 
 int dram_init(void)
 {
@@ -103,6 +77,12 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
 	MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
+#ifdef CONFIG_USB_EHCI_MX7
+static iomux_v3_cfg_t const usb_cdet_pads[] = {
+	MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#endif
+
 #ifdef CONFIG_NAND_MXS
 static iomux_v3_cfg_t const gpmi_pads[] = {
 	MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
@@ -131,22 +111,6 @@ static void setup_gpmi_nand(void)
 }
 #endif
 
-static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
-	MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-	MX7D_PAD_SD3_STROBE__SD3_STROBE	 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-
-	MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
 #ifdef CONFIG_VIDEO_MXS
 static iomux_v3_cfg_t const lcd_pads[] = {
 	MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
@@ -331,11 +295,6 @@ int board_early_init_f(void)
 {
 	setup_iomux_uart();
 
-#ifdef CONFIG_SYS_I2C_MXC
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
-#endif
-
 	return 0;
 }
 
@@ -356,6 +315,11 @@ int board_init(void)
 	setup_lcd();
 #endif
 
+#ifdef CONFIG_USB_EHCI_MX7
+	imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
+	gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
+#endif
+
 	return 0;
 }
 
@@ -377,6 +341,62 @@ int board_late_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_DM_PMIC
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int reg, ver;
+	int ret;
+
+
+	ret = pmic_get("rn5t567", &dev);
+	if (ret)
+		return ret;
+	ver = pmic_reg_read(dev, RN5T567_LSIVER);
+	reg = pmic_reg_read(dev, RN5T567_OTPVER);
+
+	printf("PMIC:  RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
+
+	/* set judge and press timer of N_OE to minimal values */
+	pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
+
+	/* configure sleep slot for 3.3V Ethernet */
+	reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
+	reg = (reg & 0xf0) | reg >> 4;
+	pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
+
+	/* disable DCDC2 discharge to avoid backfeeding through VFB2 */
+	pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
+
+	/* configure sleep slot for ARM rail */
+	reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
+	reg = (reg & 0xf0) | reg >> 4;
+	pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
+
+	/* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
+	pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+	struct udevice *dev;
+
+	pmic_get("rn5t567", &dev);
+
+	/* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
+	pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
+	pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
+
+	/*
+	 * Re-power factor detection on PMIC side is not instant. 1ms
+	 * proved to be enough time until reset takes effect.
+	 */
+	mdelay(1);
+}
+#endif
+
 int checkboard(void)
 {
 	printf("Model: Toradex Colibri iMX7%c\n",
@@ -385,6 +405,23 @@ int checkboard(void)
 	return 0;
 }
 
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
+	static struct node_info nodes[] = {
+		{ "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
+	};
+
+	/* Update partition nodes using info from mtdparts env var */
+	puts("   Updating MTD partitions...\n");
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
 #ifdef CONFIG_USB_EHCI_MX7
 static iomux_v3_cfg_t const usb_otg2_pads[] = {
 	MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -407,14 +444,18 @@ int board_ehci_hcd_init(int port)
 	}
 	return 0;
 }
-#endif
 
-static struct mxc_serial_platdata mxc_serial_plat = {
-	.reg = (struct mxc_uart *)UART1_IPS_BASE_ADDR,
-	.use_dte = true,
-};
-
-U_BOOT_DEVICE(mxc_serial) = {
-	.name = "serial_mxc",
-	.platdata = &mxc_serial_plat,
-};
+int board_usb_phy_mode(int port)
+{
+	switch (port) {
+	case 0:
+		if (gpio_get_value(USB_CDET_GPIO))
+			return USB_INIT_DEVICE;
+		else
+			return USB_INIT_HOST;
+	case 1:
+	default:
+		return USB_INIT_HOST;
+	}
+}
+#endif
diff --git a/board/toradex/colibri_imx7/imximage.cfg b/board/toradex/colibri_imx7/imximage.cfg
index d891e82..ca3cd89 100644
--- a/board/toradex/colibri_imx7/imximage.cfg
+++ b/board/toradex/colibri_imx7/imximage.cfg
@@ -4,7 +4,7 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/toradex/colibri_pxa270/Kconfig b/board/toradex/colibri_pxa270/Kconfig
index 949407a..f646baa 100644
--- a/board/toradex/colibri_pxa270/Kconfig
+++ b/board/toradex/colibri_pxa270/Kconfig
@@ -9,4 +9,15 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "colibri_pxa270"
 
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_NOR
+	default y
+
+config TDX_CFG_BLOCK_OFFSET
+	default "262144"
+
+source "board/toradex/common/Kconfig"
+
 endif
diff --git a/board/toradex/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c
index 3def0a6..85afecf 100644
--- a/board/toradex/colibri_pxa270/colibri_pxa270.c
+++ b/board/toradex/colibri_pxa270/colibri_pxa270.c
@@ -2,18 +2,25 @@
  * Toradex Colibri PXA270 Support
  *
  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
+#include <dm.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/regs-mmc.h>
 #include <asm/arch/pxa.h>
-#include <netdev.h>
+#include <asm/arch/regs-mmc.h>
+#include <asm/arch/regs-uart.h>
 #include <asm/io.h>
+#include <dm/platdata.h>
+#include <dm/platform_data/serial_pxa.h>
+#include <netdev.h>
 #include <serial.h>
 #include <usb.h>
+#include <asm/mach-types.h>
+#include "../common/tdx-common.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -32,6 +39,20 @@ int board_init(void)
 	return 0;
 }
 
+int checkboard(void)
+{
+	puts("Model: Toradex Colibri PXA270\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
 int dram_init(void)
 {
 	pxa2xx_dram_init();
@@ -105,3 +126,14 @@ int board_mmc_init(bd_t *bis)
 	return 0;
 }
 #endif
+
+static const struct pxa_serial_platdata serial_platdata = {
+	.base = (struct pxa_uart_regs *)FFUART_BASE,
+	.port = FFUART_INDEX,
+	.baudrate = CONFIG_BAUDRATE,
+};
+
+U_BOOT_DEVICE(pxa_serials) = {
+	.name = "serial_pxa",
+	.platdata = &serial_platdata,
+};
diff --git a/board/toradex/colibri_t20/Kconfig b/board/toradex/colibri_t20/Kconfig
index 7f373b2..a43acdd 100644
--- a/board/toradex/colibri_t20/Kconfig
+++ b/board/toradex/colibri_t20/Kconfig
@@ -9,4 +9,15 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "colibri_t20"
 
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_NAND
+	default y
+
+config TDX_CFG_BLOCK_OFFSET
+	default "3145728"
+
+source "board/toradex/common/Kconfig"
+
 endif
diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c
index 68fbf49..71b8fd3 100644
--- a/board/toradex/colibri_t20/colibri_t20.c
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -14,6 +14,10 @@
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <i2c.h>
+#include <nand.h>
+#include "../common/tdx-common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
 
 #define PMU_I2C_ADDRESS		0x34
 #define MAX_I2C_RETRY		3
@@ -61,7 +65,24 @@ int arch_misc_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_TEGRA_MMC
+int checkboard(void)
+{
+	printf("Model: Toradex Colibri T20 %dMB V%s\n",
+	       (gd->ram_size == 0x10000000) ? 256 : 512,
+	       (get_nand_dev_by_index(0)->erasesize >> 10 == 512) ?
+	       ((gd->ram_size == 0x10000000) ? "1.1B" : "1.1C") : "1.2A");
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_MMC_SDHCI_TEGRA
 /*
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
diff --git a/board/toradex/colibri_t30/Kconfig b/board/toradex/colibri_t30/Kconfig
index 3e436a2..68ef82b 100644
--- a/board/toradex/colibri_t30/Kconfig
+++ b/board/toradex/colibri_t30/Kconfig
@@ -9,4 +9,22 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "colibri_t30"
 
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+# Toradex config block in eMMC, at the end of 1st "boot sector"
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+source "board/toradex/common/Kconfig"
+
 endif
diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c
index e32362a..b68d3ca 100644
--- a/board/toradex/colibri_t30/colibri_t30.c
+++ b/board/toradex/colibri_t30/colibri_t30.c
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2014
+ *  (C) Copyright 2014-2016
  *  Stefan Agner <stefan@agner.ch>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -14,6 +14,7 @@
 #include <asm/io.h>
 #include <i2c.h>
 #include "pinmux-config-colibri_t30.h"
+#include "../common/tdx-common.h"
 
 int arch_misc_init(void)
 {
@@ -24,6 +25,20 @@ int arch_misc_init(void)
 	return 0;
 }
 
+int checkboard(void)
+{
+	puts("Model: Toradex Colibri T30 1GB\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
 /*
  * Routine: pinmux_init
  * Description: Do individual peripheral pinmux configs
diff --git a/board/toradex/colibri_vf/Kconfig b/board/toradex/colibri_vf/Kconfig
index 2c3cb30..5f7129d 100644
--- a/board/toradex/colibri_vf/Kconfig
+++ b/board/toradex/colibri_vf/Kconfig
@@ -1,18 +1,26 @@
 if TARGET_COLIBRI_VF
 
-config SYS_CPU
-	default "armv7"
-
 config SYS_BOARD
 	default "colibri_vf"
 
 config SYS_VENDOR
 	default "toradex"
 
-config SYS_SOC
-	default "vf610"
-
 config SYS_CONFIG_NAME
 	default "colibri_vf"
 
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_HAVE_NAND
+	default y
+
+config TDX_CFG_BLOCK_OFFSET
+	default "2048"
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+	default y
+
+source "board/toradex/common/Kconfig"
+
 endif
diff --git a/board/toradex/colibri_vf/Makefile b/board/toradex/colibri_vf/Makefile
index c7e5134..4d6287f 100644
--- a/board/toradex/colibri_vf/Makefile
+++ b/board/toradex/colibri_vf/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	:= colibri_vf.o
+obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c
index c65ccb3..46dd15b 100644
--- a/board/toradex/colibri_vf/colibri_vf.c
+++ b/board/toradex/colibri_vf/colibri_vf.c
@@ -15,13 +15,18 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 #include <mmc.h>
+#include <fdt_support.h>
 #include <fsl_esdhc.h>
+#include <fsl_dcu_fb.h>
+#include <jffs2/load_kernel.h>
 #include <miiphy.h>
+#include <mtd_node.h>
 #include <netdev.h>
 #include <i2c.h>
 #include <g_dnl.h>
 #include <asm/gpio.h>
 #include <usb.h>
+#include "../common/tdx-common.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -291,6 +296,49 @@ static void setup_iomux_gpio(void)
 }
 #endif
 
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+static void setup_iomux_fsl_dcu(void)
+{
+	static const iomux_v3_cfg_t dcu0_pads[] = {
+		VF610_PAD_PTE0__DCU0_HSYNC,
+		VF610_PAD_PTE1__DCU0_VSYNC,
+		VF610_PAD_PTE2__DCU0_PCLK,
+		VF610_PAD_PTE4__DCU0_DE,
+		VF610_PAD_PTE5__DCU0_R0,
+		VF610_PAD_PTE6__DCU0_R1,
+		VF610_PAD_PTE7__DCU0_R2,
+		VF610_PAD_PTE8__DCU0_R3,
+		VF610_PAD_PTE9__DCU0_R4,
+		VF610_PAD_PTE10__DCU0_R5,
+		VF610_PAD_PTE11__DCU0_R6,
+		VF610_PAD_PTE12__DCU0_R7,
+		VF610_PAD_PTE13__DCU0_G0,
+		VF610_PAD_PTE14__DCU0_G1,
+		VF610_PAD_PTE15__DCU0_G2,
+		VF610_PAD_PTE16__DCU0_G3,
+		VF610_PAD_PTE17__DCU0_G4,
+		VF610_PAD_PTE18__DCU0_G5,
+		VF610_PAD_PTE19__DCU0_G6,
+		VF610_PAD_PTE20__DCU0_G7,
+		VF610_PAD_PTE21__DCU0_B0,
+		VF610_PAD_PTE22__DCU0_B1,
+		VF610_PAD_PTE23__DCU0_B2,
+		VF610_PAD_PTE24__DCU0_B3,
+		VF610_PAD_PTE25__DCU0_B4,
+		VF610_PAD_PTE26__DCU0_B5,
+		VF610_PAD_PTE27__DCU0_B6,
+		VF610_PAD_PTE28__DCU0_B7,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads));
+}
+
+static void setup_tcon(void)
+{
+	setbits_le32(TCON0_BASE_ADDR, (1 << 29));
+}
+#endif
+
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 	{ESDHC1_BASE_ADDR},
@@ -364,12 +412,18 @@ static void clock_init(void)
 	clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
 			CCM_CCGR10_NFC_CTRL_MASK);
 
-#ifdef CONFIG_CI_UDC
+#ifdef CONFIG_USB_EHCI_VF
 	setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK);
-#endif
-
-#ifdef CONFIG_USB_EHCI
 	setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK);
+
+	clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS |
+			ANADIG_PLL3_CTRL_POWERDOWN |
+			ANADIG_PLL3_CTRL_DIV_SELECT,
+			ANADIG_PLL3_CTRL_ENABLE);
+	clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS |
+			ANADIG_PLL7_CTRL_POWERDOWN |
+			ANADIG_PLL7_CTRL_DIV_SELECT,
+			ANADIG_PLL7_CTRL_ENABLE);
 #endif
 
 	clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
@@ -418,9 +472,14 @@ static void clock_init(void)
 			CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
 			CCM_CSCDR2_NFC_EN);
 	clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
-			CCM_CSCDR3_NFC_PRE_DIV(5));
+			CCM_CSCDR3_NFC_PRE_DIV(3));
 	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
 			CCM_CSCMR2_RMII_CLK_SEL(2));
+
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+		setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK);
+		setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK);
+#endif
 }
 
 static void mscm_init(void)
@@ -460,6 +519,11 @@ int board_early_init_f(void)
 	setup_iomux_dspi();
 #endif
 
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+	setup_tcon();
+	setup_iomux_fsl_dcu();
+#endif
+
 	return 0;
 }
 
@@ -468,22 +532,6 @@ int board_late_init(void)
 {
 	struct src *src = (struct src *)SRC_BASE_ADDR;
 
-	/* Default memory arguments */
-	if (!getenv("memargs")) {
-		switch (gd->ram_size) {
-		case 0x08000000:
-			/* 128 MB */
-			setenv("memargs", "mem=128M");
-			break;
-		case 0x10000000:
-			/* 256 MB */
-			setenv("memargs", "mem=256M");
-			break;
-		default:
-			printf("Failed detecting RAM size.\n");
-		}
-	}
-
 	if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
 			== SRC_SBMR2_BMOD_SERIAL) {
 		printf("Serial Downloader recovery mode, disable autoboot\n");
@@ -528,21 +576,28 @@ int checkboard(void)
 	return 0;
 }
 
-int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
 {
-	unsigned short usb_pid;
-
-	put_unaligned(CONFIG_TRDX_VID, &dev->idVendor);
-
-	if (is_colibri_vf61())
-		usb_pid = CONFIG_TRDX_PID_COLIBRI_VF61IT;
-	else
-		usb_pid = CONFIG_TRDX_PID_COLIBRI_VF50IT;
+	int ret = 0;
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+	static struct node_info nodes[] = {
+		{ "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */
+	};
 
-	put_unaligned(usb_pid, &dev->idProduct);
+	/* Update partition nodes using info from mtdparts env var */
+	puts("   Updating MTD partitions...\n");
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+	ret = fsl_dcu_fixedfb_setup(blob);
+	if (ret)
+		return ret;
+#endif
 
-	return 0;
+	return ft_common_board_setup(blob, bd);
 }
+#endif
 
 #ifdef CONFIG_USB_EHCI_VF
 int board_ehci_hcd_init(int port)
diff --git a/board/toradex/colibri_vf/dcu.c b/board/toradex/colibri_vf/dcu.c
new file mode 100644
index 0000000..3fa6a76
--- /dev/null
+++ b/board/toradex/colibri_vf/dcu.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * FSL DCU platform driver
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include "div64.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	unsigned long long div;
+
+	clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL);
+	clrsetbits_le32(&ccm->cscdr3,
+			CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN,
+			CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN);
+	div = (unsigned long long)(PLL1_PFD2_FREQ / 1000);
+	do_div(div, pixclock);
+
+	return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+		      const char *port,
+		      struct fb_videomode *dcu_fb_videomode)
+{
+	fsl_dcu_init(xres, yres, 32);
+
+	return 0;
+}
diff --git a/board/toradex/colibri_vf/imximage.cfg b/board/toradex/colibri_vf/imximage.cfg
index 8c52886..6d032ed 100644
--- a/board/toradex/colibri_vf/imximage.cfg
+++ b/board/toradex/colibri_vf/imximage.cfg
@@ -3,12 +3,12 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
  */
-#include <asm/imx-common/imximage.cfg>
+#include <asm/mach-imx/imximage.cfg>
 
 /* image version */
 IMAGE_VERSION	2
diff --git a/board/toradex/common/Kconfig b/board/toradex/common/Kconfig
new file mode 100644
index 0000000..b33baef
--- /dev/null
+++ b/board/toradex/common/Kconfig
@@ -0,0 +1,69 @@
+# Copyright (c) 2016 Toradex, Inc.
+# SPDX-License-Identifier:	GPL-2.0+
+
+menuconfig TDX_CFG_BLOCK
+	bool "Enable Toradex config block support"
+	select OF_BOARD_SETUP
+	help
+	  The Toradex config block stored production data on the on-module
+	  flash device (NAND, NOR or eMMC). The area is normally preserved by
+	  software and contains the serial number (out of which the MAC
+	  address is generated) and the exact module type.
+
+# Helper config to determine the correct default location of the cfg block
+config TDX_HAVE_MMC
+	bool
+
+config TDX_HAVE_NAND
+	bool
+
+config TDX_HAVE_NOR
+	bool
+
+if TDX_CFG_BLOCK
+
+config TDX_CFG_BLOCK_IS_IN_MMC
+	bool
+	depends on TDX_HAVE_MMC
+	default y
+
+config TDX_CFG_BLOCK_IS_IN_NAND
+	bool
+	depends on TDX_HAVE_NAND
+	default y
+
+config TDX_CFG_BLOCK_IS_IN_NOR
+	bool
+	depends on TDX_HAVE_NOR
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	int "Toradex config block eMMC device ID"
+	depends on TDX_CFG_BLOCK_IS_IN_MMC
+
+config TDX_CFG_BLOCK_PART
+	int "Toradex config block eMMC partition ID"
+	depends on TDX_CFG_BLOCK_IS_IN_MMC
+
+config TDX_CFG_BLOCK_OFFSET
+	int "Toradex config block offset"
+	help
+	  Specify the byte offset of the Toradex config block within the flash
+	  device the config block is stored on.
+
+config TDX_CFG_BLOCK_OFFSET2
+	int "Toradex config block offset, second instance"
+	default 0
+	help
+	  Specify the byte offset of the 2nd instance of the Toradex config block
+	  within the flash device the config block is stored on.
+	  Set to 0 on modules which have no 2nd instance.
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+	bool "Set the second Ethernet address"
+	help
+	  For each serial number two Ethernet addresses are available for dual
+	  Ethernet carrier boards. This options enables the code to set the
+	  second Ethernet address as environment variable (eth1addr).
+
+endif
diff --git a/board/toradex/common/Makefile b/board/toradex/common/Makefile
new file mode 100644
index 0000000..d645f5a
--- /dev/null
+++ b/board/toradex/common/Makefile
@@ -0,0 +1,11 @@
+# Copyright (c) 2016 Toradex, Inc.
+# SPDX-License-Identifier:	GPL-2.0+
+
+# Common for all Toradex modules
+ifeq ($(CONFIG_SPL_BUILD),y)
+# Necessary to create built-in.o
+obj- := __dummy__.o
+else
+obj-$(CONFIG_TDX_CFG_BLOCK) += tdx-cfg-block.o
+obj-y += tdx-common.o
+endif
diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c
new file mode 100644
index 0000000..1bf8ca8
--- /dev/null
+++ b/board/toradex/common/tdx-cfg-block.c
@@ -0,0 +1,549 @@
+/*
+ * Copyright (c) 2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include "tdx-cfg-block.h"
+
+#if defined(CONFIG_TARGET_APALIS_IMX6) || defined(CONFIG_TARGET_COLIBRI_IMX6)
+#include <asm/arch/sys_proto.h>
+#else
+#define is_cpu_type(cpu) (0)
+#endif
+#if defined(CONFIG_CPU_PXA27X)
+#include <asm/arch-pxa/pxa.h>
+#else
+#define cpu_is_pxa27x(cpu) (0)
+#endif
+#include <cli.h>
+#include <console.h>
+#include <flash.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <nand.h>
+#include <asm/mach-types.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TAG_VALID	0xcf01
+#define TAG_MAC		0x0000
+#define TAG_HW		0x0008
+#define TAG_INVALID	0xffff
+
+#define TAG_FLAG_VALID	0x1
+
+#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC)
+#define TDX_CFG_BLOCK_MAX_SIZE 512
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
+#define TDX_CFG_BLOCK_MAX_SIZE 64
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
+#define TDX_CFG_BLOCK_MAX_SIZE 64
+#else
+#error Toradex config block location not set
+#endif
+
+struct toradex_tag {
+	u32 len:14;
+	u32 flags:2;
+	u32 id:16;
+};
+
+bool valid_cfgblock;
+struct toradex_hw tdx_hw_tag;
+struct toradex_eth_addr tdx_eth_addr;
+u32 tdx_serial;
+
+const char * const toradex_modules[] = {
+	 [0] = "UNKNOWN MODULE",
+	 [1] = "Colibri PXA270 312MHz",
+	 [2] = "Colibri PXA270 520MHz",
+	 [3] = "Colibri PXA320 806MHz",
+	 [4] = "Colibri PXA300 208MHz",
+	 [5] = "Colibri PXA310 624MHz",
+	 [6] = "Colibri PXA320 806MHz IT",
+	 [7] = "Colibri PXA300 208MHz XT",
+	 [8] = "Colibri PXA270 312MHz",
+	 [9] = "Colibri PXA270 520MHz",
+	[10] = "Colibri VF50 128MB", /* not currently on sale */
+	[11] = "Colibri VF61 256MB",
+	[12] = "Colibri VF61 256MB IT",
+	[13] = "Colibri VF50 128MB IT",
+	[14] = "Colibri iMX6 Solo 256MB",
+	[15] = "Colibri iMX6 DualLite 512MB",
+	[16] = "Colibri iMX6 Solo 256MB IT",
+	[17] = "Colibri iMX6 DualLite 512MB IT",
+	[18] = "UNKNOWN MODULE",
+	[19] = "UNKNOWN MODULE",
+	[20] = "Colibri T20 256MB",
+	[21] = "Colibri T20 512MB",
+	[22] = "Colibri T20 512MB IT",
+	[23] = "Colibri T30 1GB",
+	[24] = "Colibri T20 256MB IT",
+	[25] = "Apalis T30 2GB",
+	[26] = "Apalis T30 1GB",
+	[27] = "Apalis iMX6 Quad 1GB",
+	[28] = "Apalis iMX6 Quad 2GB IT",
+	[29] = "Apalis iMX6 Dual 512MB",
+	[30] = "Colibri T30 1GB IT",
+	[31] = "Apalis T30 1GB IT",
+	[32] = "Colibri iMX7 Solo 256MB",
+	[33] = "Colibri iMX7 Dual 512MB",
+	[34] = "Apalis TK1 2GB",
+	[35] = "Apalis iMX6 Dual 1GB IT",
+};
+
+#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC
+static int tdx_cfg_block_mmc_storage(u8 *config_block, int write)
+{
+	struct mmc *mmc;
+	int dev = CONFIG_TDX_CFG_BLOCK_DEV;
+	int offset = CONFIG_TDX_CFG_BLOCK_OFFSET;
+	uint part = CONFIG_TDX_CFG_BLOCK_PART;
+	uint blk_start;
+	int ret = 0;
+
+	/* Read production parameter config block from eMMC */
+	mmc = find_mmc_device(dev);
+	if (!mmc) {
+		puts("No MMC card found\n");
+		ret = -ENODEV;
+		goto out;
+	}
+	if (part != mmc_get_blk_desc(mmc)->hwpart) {
+		if (blk_select_hwpart_devnum(IF_TYPE_MMC, dev, part)) {
+			puts("MMC partition switch failed\n");
+			ret = -ENODEV;
+			goto out;
+		}
+	}
+	if (offset < 0)
+		offset += mmc->capacity;
+	blk_start = ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len;
+
+	if (!write) {
+		/* Careful reads a whole block of 512 bytes into config_block */
+		if (blk_dread(mmc_get_blk_desc(mmc), blk_start, 1,
+			      (unsigned char *)config_block) != 1) {
+			ret = -EIO;
+			goto out;
+		}
+		/* Flush cache after read */
+		flush_cache((ulong)(unsigned char *)config_block, 512);
+	} else {
+		/* Just writing one 512 byte block */
+		if (blk_dwrite(mmc_get_blk_desc(mmc), blk_start, 1,
+			       (unsigned char *)config_block) != 1) {
+			ret = -EIO;
+			goto out;
+		}
+	}
+
+out:
+	/* Switch back to regular eMMC user partition */
+	blk_select_hwpart_devnum(IF_TYPE_MMC, 0, 0);
+
+	return ret;
+}
+#endif
+
+#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_NAND
+static int read_tdx_cfg_block_from_nand(unsigned char *config_block)
+{
+	size_t size = TDX_CFG_BLOCK_MAX_SIZE;
+
+	/* Read production parameter config block from NAND page */
+	return nand_read_skip_bad(get_nand_dev_by_index(0),
+				  CONFIG_TDX_CFG_BLOCK_OFFSET,
+				  &size, NULL, TDX_CFG_BLOCK_MAX_SIZE,
+				  config_block);
+}
+
+static int write_tdx_cfg_block_to_nand(unsigned char *config_block)
+{
+	size_t size = TDX_CFG_BLOCK_MAX_SIZE;
+
+	/* Write production parameter config block to NAND page */
+	return nand_write_skip_bad(get_nand_dev_by_index(0),
+				   CONFIG_TDX_CFG_BLOCK_OFFSET,
+				   &size, NULL, TDX_CFG_BLOCK_MAX_SIZE,
+				   config_block, WITH_WR_VERIFY);
+}
+#endif
+
+#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_NOR
+static int read_tdx_cfg_block_from_nor(unsigned char *config_block)
+{
+	/* Read production parameter config block from NOR flash */
+	memcpy(config_block, (void *)CONFIG_TDX_CFG_BLOCK_OFFSET,
+	       TDX_CFG_BLOCK_MAX_SIZE);
+	return 0;
+}
+
+static int write_tdx_cfg_block_to_nor(unsigned char *config_block)
+{
+	/* Write production parameter config block to NOR flash */
+	return flash_write((void *)config_block, CONFIG_TDX_CFG_BLOCK_OFFSET,
+			   TDX_CFG_BLOCK_MAX_SIZE);
+}
+#endif
+
+int read_tdx_cfg_block(void)
+{
+	int ret = 0;
+	u8 *config_block = NULL;
+	struct toradex_tag *tag;
+	size_t size = TDX_CFG_BLOCK_MAX_SIZE;
+	int offset;
+
+	/* Allocate RAM area for config block */
+	config_block = memalign(ARCH_DMA_MINALIGN, size);
+	if (!config_block) {
+		printf("Not enough malloc space available!\n");
+		return -ENOMEM;
+	}
+
+	memset(config_block, 0, size);
+
+#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC)
+	ret = tdx_cfg_block_mmc_storage(config_block, 0);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
+	ret = read_tdx_cfg_block_from_nand(config_block);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
+	ret = read_tdx_cfg_block_from_nor(config_block);
+#else
+	ret = -EINVAL;
+#endif
+	if (ret)
+		goto out;
+
+	/* Expect a valid tag first */
+	tag = (struct toradex_tag *)config_block;
+	if (tag->flags != TAG_FLAG_VALID || tag->id != TAG_VALID) {
+		valid_cfgblock = false;
+		ret = -EINVAL;
+		goto out;
+	}
+	valid_cfgblock = true;
+	offset = 4;
+
+	while (offset < TDX_CFG_BLOCK_MAX_SIZE) {
+		tag = (struct toradex_tag *)(config_block + offset);
+		offset += 4;
+		if (tag->id == TAG_INVALID)
+			break;
+
+		if (tag->flags == TAG_FLAG_VALID) {
+			switch (tag->id) {
+			case TAG_MAC:
+				memcpy(&tdx_eth_addr, config_block + offset,
+				       6);
+
+				/* NIC part of MAC address is serial number */
+				tdx_serial = ntohl(tdx_eth_addr.nic) >> 8;
+				break;
+			case TAG_HW:
+				memcpy(&tdx_hw_tag, config_block + offset, 8);
+				break;
+			}
+		}
+
+		/* Get to next tag according to current tags length */
+		offset += tag->len * 4;
+	}
+
+	/* Cap product id to avoid issues with a yet unknown one */
+	if (tdx_hw_tag.prodid > (sizeof(toradex_modules) /
+				  sizeof(toradex_modules[0])))
+		tdx_hw_tag.prodid = 0;
+
+out:
+	free(config_block);
+	return ret;
+}
+
+static int get_cfgblock_interactive(void)
+{
+	char message[CONFIG_SYS_CBSIZE];
+	char *soc;
+	char it = 'n';
+	int len;
+
+	if (cpu_is_pxa27x())
+		sprintf(message, "Is the module the 312 MHz version? [y/N] ");
+	else
+		sprintf(message, "Is the module an IT version? [y/N] ");
+
+	len = cli_readline(message);
+	it = console_buffer[0];
+
+	soc = getenv("soc");
+	if (!strcmp("mx6", soc)) {
+#ifdef CONFIG_MACH_TYPE
+		if (it == 'y' || it == 'Y')
+			if (is_cpu_type(MXC_CPU_MX6Q))
+				tdx_hw_tag.prodid = APALIS_IMX6Q_IT;
+			else
+				tdx_hw_tag.prodid = APALIS_IMX6D_IT;
+		else
+			if (is_cpu_type(MXC_CPU_MX6Q))
+				tdx_hw_tag.prodid = APALIS_IMX6Q;
+			else
+				tdx_hw_tag.prodid = APALIS_IMX6D;
+#else
+		if (it == 'y' || it == 'Y')
+			if (is_cpu_type(MXC_CPU_MX6DL))
+				tdx_hw_tag.prodid = COLIBRI_IMX6DL_IT;
+			else
+				tdx_hw_tag.prodid = COLIBRI_IMX6S_IT;
+		else
+			if (is_cpu_type(MXC_CPU_MX6DL))
+				tdx_hw_tag.prodid = COLIBRI_IMX6DL;
+			else
+				tdx_hw_tag.prodid = COLIBRI_IMX6S;
+#endif /* CONFIG_MACH_TYPE */
+	} else if (!strcmp("imx7d", soc)) {
+		tdx_hw_tag.prodid = COLIBRI_IMX7D;
+	} else if (!strcmp("imx7s", soc)) {
+		tdx_hw_tag.prodid = COLIBRI_IMX7S;
+	} else if (!strcmp("tegra20", soc)) {
+		if (it == 'y' || it == 'Y')
+			if (gd->ram_size == 0x10000000)
+				tdx_hw_tag.prodid = COLIBRI_T20_256MB_IT;
+			else
+				tdx_hw_tag.prodid = COLIBRI_T20_512MB_IT;
+		else
+			if (gd->ram_size == 0x10000000)
+				tdx_hw_tag.prodid = COLIBRI_T20_256MB;
+			else
+				tdx_hw_tag.prodid = COLIBRI_T20_512MB;
+	} else if (cpu_is_pxa27x()) {
+		if (it == 'y' || it == 'Y')
+			tdx_hw_tag.prodid = COLIBRI_PXA270_312MHZ;
+		else
+			tdx_hw_tag.prodid = COLIBRI_PXA270_520MHZ;
+#ifdef CONFIG_MACH_TYPE
+	} else if (!strcmp("tegra30", soc)) {
+		if (CONFIG_MACH_TYPE == MACH_TYPE_APALIS_T30) {
+			if (it == 'y' || it == 'Y')
+				tdx_hw_tag.prodid = APALIS_T30_IT;
+			else
+				if (gd->ram_size == 0x40000000)
+					tdx_hw_tag.prodid = APALIS_T30_1GB;
+				else
+					tdx_hw_tag.prodid = APALIS_T30_2GB;
+		} else {
+			if (it == 'y' || it == 'Y')
+				tdx_hw_tag.prodid = COLIBRI_T30_IT;
+			else
+				tdx_hw_tag.prodid = COLIBRI_T30;
+		}
+#endif /* CONFIG_MACH_TYPE */
+	} else if (!strcmp("tegra124", soc)) {
+		tdx_hw_tag.prodid = APALIS_TK1_2GB;
+	} else if (!strcmp("vf500", soc)) {
+		if (it == 'y' || it == 'Y')
+			tdx_hw_tag.prodid = COLIBRI_VF50_IT;
+		else
+			tdx_hw_tag.prodid = COLIBRI_VF50;
+	} else if (!strcmp("vf610", soc)) {
+		if (it == 'y' || it == 'Y')
+			tdx_hw_tag.prodid = COLIBRI_VF61_IT;
+		else
+			tdx_hw_tag.prodid = COLIBRI_VF61;
+	} else {
+		printf("Module type not detectable due to unknown SoC\n");
+		return -1;
+	}
+
+	while (len < 4) {
+		sprintf(message, "Enter the module version (e.g. V1.1B): V");
+		len = cli_readline(message);
+	}
+
+	tdx_hw_tag.ver_major = console_buffer[0] - '0';
+	tdx_hw_tag.ver_minor = console_buffer[2] - '0';
+	tdx_hw_tag.ver_assembly = console_buffer[3] - 'A';
+
+	if (cpu_is_pxa27x() && (tdx_hw_tag.ver_major == 1))
+		tdx_hw_tag.prodid -= (COLIBRI_PXA270_312MHZ -
+				       COLIBRI_PXA270_V1_312MHZ);
+
+	while (len < 8) {
+		sprintf(message, "Enter module serial number: ");
+		len = cli_readline(message);
+	}
+
+	tdx_serial = simple_strtoul(console_buffer, NULL, 10);
+
+	return 0;
+}
+
+static int get_cfgblock_barcode(char *barcode)
+{
+	if (strlen(barcode) < 16) {
+		printf("Argument too short, barcode is 16 chars long\n");
+		return -1;
+	}
+
+	/* Get hardware information from the first 8 digits */
+	tdx_hw_tag.ver_major = barcode[4] - '0';
+	tdx_hw_tag.ver_minor = barcode[5] - '0';
+	tdx_hw_tag.ver_assembly = barcode[7] - '0';
+
+	barcode[4] = '\0';
+	tdx_hw_tag.prodid = simple_strtoul(barcode, NULL, 10);
+
+	/* Parse second part of the barcode (serial number */
+	barcode += 8;
+	tdx_serial = simple_strtoul(barcode, NULL, 10);
+
+	return 0;
+}
+
+static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc,
+			      char * const argv[])
+{
+	u8 *config_block;
+	struct toradex_tag *tag;
+	size_t size = TDX_CFG_BLOCK_MAX_SIZE;
+	int offset = 0;
+	int ret = CMD_RET_SUCCESS;
+	int err;
+
+	/* Allocate RAM area for config block */
+	config_block = memalign(ARCH_DMA_MINALIGN, size);
+	if (!config_block) {
+		printf("Not enough malloc space available!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	memset(config_block, 0xff, size);
+
+	read_tdx_cfg_block();
+	if (valid_cfgblock) {
+#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
+		/*
+		 * On NAND devices, recreation is only allowed if the page is
+		 * empty (config block invalid...)
+		 */
+		printf("NAND erase block %d need to be erased before creating a Toradex config block\n",
+		       CONFIG_TDX_CFG_BLOCK_OFFSET /
+		       get_nand_dev_by_index(0)->erasesize);
+		goto out;
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
+		/*
+		 * On NOR devices, recreation is only allowed if the sector is
+		 * empty and write protection is off (config block invalid...)
+		 */
+		printf("NOR sector at offset 0x%02x need to be erased and unprotected before creating a Toradex config block\n",
+		       CONFIG_TDX_CFG_BLOCK_OFFSET);
+		goto out;
+#else
+		char message[CONFIG_SYS_CBSIZE];
+		sprintf(message,
+			"A valid Toradex config block is present, still recreate? [y/N] ");
+
+		if (!cli_readline(message))
+			goto out;
+
+		if (console_buffer[0] != 'y' && console_buffer[0] != 'Y')
+			goto out;
+#endif
+	}
+
+	/* Parse new Toradex config block data... */
+	if (argc < 3)
+		err = get_cfgblock_interactive();
+	else
+		err = get_cfgblock_barcode(argv[2]);
+
+	if (err) {
+		ret = CMD_RET_FAILURE;
+		goto out;
+	}
+
+	/* Convert serial number to MAC address (the storage format) */
+	tdx_eth_addr.oui = htonl(0x00142dUL << 8);
+	tdx_eth_addr.nic = htonl(tdx_serial << 8);
+
+	/* Valid Tag */
+	tag = (struct toradex_tag *)config_block;
+	tag->id = TAG_VALID;
+	tag->flags = TAG_FLAG_VALID;
+	tag->len = 0;
+	offset += 4;
+
+	/* Product Tag */
+	tag = (struct toradex_tag *)(config_block + offset);
+	tag->id = TAG_HW;
+	tag->flags = TAG_FLAG_VALID;
+	tag->len = 2;
+	offset += 4;
+
+	memcpy(config_block + offset, &tdx_hw_tag, 8);
+	offset += 8;
+
+	/* MAC Tag */
+	tag = (struct toradex_tag *)(config_block + offset);
+	tag->id = TAG_MAC;
+	tag->flags = TAG_FLAG_VALID;
+	tag->len = 2;
+	offset += 4;
+
+	memcpy(config_block + offset, &tdx_eth_addr, 6);
+	offset += 6;
+	memset(config_block + offset, 0, 32 - offset);
+
+#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC)
+	err = tdx_cfg_block_mmc_storage(config_block, 1);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
+	err = write_tdx_cfg_block_to_nand(config_block);
+#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
+	err = write_tdx_cfg_block_to_nor(config_block);
+#else
+	err = -EINVAL;
+#endif
+	if (err) {
+		printf("Failed to write Toradex config block: %d\n", ret);
+		ret = CMD_RET_FAILURE;
+		goto out;
+	}
+
+	printf("Toradex config block successfully written\n");
+
+out:
+	free(config_block);
+	return ret;
+}
+
+static int do_cfgblock(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	int ret;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	if (!strcmp(argv[1], "create")) {
+		return do_cfgblock_create(cmdtp, flag, argc, argv);
+	} else if (!strcmp(argv[1], "reload")) {
+		ret = read_tdx_cfg_block();
+		if (ret) {
+			printf("Failed to reload Toradex config block: %d\n",
+			       ret);
+			return CMD_RET_FAILURE;
+		}
+		return CMD_RET_SUCCESS;
+	}
+
+	return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+	cfgblock, 3, 0, do_cfgblock,
+	"Toradex config block handling commands",
+	"create [barcode] - (Re-)create Toradex config block\n"
+	"cfgblock reload - Reload Toradex config block from flash"
+);
diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h
new file mode 100644
index 0000000..fd7c362
--- /dev/null
+++ b/board/toradex/common/tdx-cfg-block.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TDX_CFG_BLOCK_H
+#define _TDX_CFG_BLOCK_H
+
+#include "tdx-common.h"
+
+struct toradex_hw {
+	u16 ver_major;
+	u16 ver_minor;
+	u16 ver_assembly;
+	u16 prodid;
+};
+
+struct toradex_eth_addr {
+	u32 oui:24;
+	u32 nic:24;
+} __attribute__((__packed__));
+
+enum {
+	COLIBRI_PXA270_V1_312MHZ = 1,
+	COLIBRI_PXA270_V1_520MHZ,
+	COLIBRI_PXA320,
+	COLIBRI_PXA300,
+	COLIBRI_PXA310,
+	COLIBRI_PXA320_IT,
+	COLIBRI_PXA300_XT,
+	COLIBRI_PXA270_312MHZ,
+	COLIBRI_PXA270_520MHZ,
+	COLIBRI_VF50, /* not currently on sale */
+	COLIBRI_VF61,
+	COLIBRI_VF61_IT,
+	COLIBRI_VF50_IT,
+	COLIBRI_IMX6S,
+	COLIBRI_IMX6DL,
+	COLIBRI_IMX6S_IT,
+	COLIBRI_IMX6DL_IT,
+	COLIBRI_T20_256MB = 20,
+	COLIBRI_T20_512MB,
+	COLIBRI_T20_512MB_IT,
+	COLIBRI_T30,
+	COLIBRI_T20_256MB_IT,
+	APALIS_T30_2GB,
+	APALIS_T30_1GB,
+	APALIS_IMX6Q,
+	APALIS_IMX6Q_IT,
+	APALIS_IMX6D,
+	COLIBRI_T30_IT,
+	APALIS_T30_IT,
+	COLIBRI_IMX7S,
+	COLIBRI_IMX7D,
+	APALIS_TK1_2GB,
+	APALIS_IMX6D_IT,
+};
+
+extern const char * const toradex_modules[];
+extern bool valid_cfgblock;
+extern struct toradex_hw tdx_hw_tag;
+extern struct toradex_eth_addr tdx_eth_addr;
+extern u32 tdx_serial;
+
+int read_tdx_cfg_block(void);
+
+#endif /* _TDX_CFG_BLOCK_H */
diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c
new file mode 100644
index 0000000..0d26787
--- /dev/null
+++ b/board/toradex/common/tdx-common.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <g_dnl.h>
+#include <libfdt.h>
+
+#include "tdx-cfg-block.h"
+#include <asm/setup.h>
+#include "tdx-common.h"
+
+#ifdef CONFIG_TDX_CFG_BLOCK
+static char tdx_serial_str[9];
+static char tdx_board_rev_str[6];
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+	/* Check validity */
+	if (!tdx_hw_tag.ver_major)
+		return 0;
+
+	return ((tdx_hw_tag.ver_major & 0xff) << 8) |
+		((tdx_hw_tag.ver_minor & 0xf) << 4) |
+		((tdx_hw_tag.ver_assembly & 0xf) + 0xa);
+}
+#endif /* CONFIG_TDX_CFG_BLOCK */
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	int array[8];
+	unsigned int serial = tdx_serial;
+	int i;
+
+	serialnr->low = 0;
+	serialnr->high = 0;
+
+	/* Check validity */
+	if (serial) {
+		/*
+		 * Convert to Linux serial number format (hexadecimal coded
+		 * decimal)
+		 */
+		i = 7;
+		while (serial) {
+			array[i--] = serial % 10;
+			serial /= 10;
+		}
+		while (i >= 0)
+			array[i--] = 0;
+		serial = array[0];
+		for (i = 1; i < 8; i++) {
+			serial *= 16;
+			serial += array[i];
+		}
+
+		serialnr->low = serial;
+	}
+}
+#endif /* CONFIG_SERIAL_TAG */
+
+int show_board_info(void)
+{
+	unsigned char ethaddr[6];
+
+	if (read_tdx_cfg_block()) {
+		printf("Missing Toradex config block\n");
+		checkboard();
+		return 0;
+	}
+
+	/* board serial-number */
+	sprintf(tdx_serial_str, "%08u", tdx_serial);
+	sprintf(tdx_board_rev_str, "V%1d.%1d%c",
+		tdx_hw_tag.ver_major,
+		tdx_hw_tag.ver_minor,
+		(char)tdx_hw_tag.ver_assembly + 'A');
+
+	setenv("serial#", tdx_serial_str);
+
+	/*
+	 * Check if environment contains a valid MAC address,
+	 * set the one from config block if not
+	 */
+	if (!eth_getenv_enetaddr("ethaddr", ethaddr))
+		eth_setenv_enetaddr("ethaddr", (u8 *)&tdx_eth_addr);
+
+#ifdef CONFIG_TDX_CFG_BLOCK_2ND_ETHADDR
+	if (!eth_getenv_enetaddr("eth1addr", ethaddr)) {
+		/*
+		 * Secondary MAC address is allocated from block
+		 * 0x100000 higher then the first MAC address
+		 */
+		memcpy(ethaddr, &tdx_eth_addr, 6);
+		ethaddr[3] += 0x10;
+		eth_setenv_enetaddr("eth1addr", ethaddr);
+	}
+#endif
+
+	printf("Model: Toradex %s %s, Serial# %s\n",
+	       toradex_modules[tdx_hw_tag.prodid],
+	       tdx_board_rev_str,
+	       tdx_serial_str);
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_GADGET_DOWNLOAD
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+	unsigned short usb_pid;
+
+	usb_pid = TORADEX_USB_PRODUCT_NUM_OFFSET + tdx_hw_tag.prodid;
+	put_unaligned(usb_pid, &dev->idProduct);
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT)
+int ft_common_board_setup(void *blob, bd_t *bd)
+{
+	if (tdx_serial) {
+		fdt_setprop(blob, 0, "serial-number", tdx_serial_str,
+			    strlen(tdx_serial_str) + 1);
+	}
+
+	if (tdx_hw_tag.ver_major) {
+		char prod_id[5];
+
+		sprintf(prod_id, "%04u", tdx_hw_tag.prodid);
+		fdt_setprop(blob, 0, "toradex,product-id", prod_id, 5);
+
+		fdt_setprop(blob, 0, "toradex,board-rev", tdx_board_rev_str,
+			    strlen(tdx_board_rev_str) + 1);
+	}
+
+	return 0;
+}
+#endif
+
+#else /* CONFIG_TDX_CFG_BLOCK */
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+	return 0;
+}
+#endif /* CONFIG_REVISION_TAG */
+
+#ifdef CONFIG_SERIAL_TAG
+u32 get_board_serial(void)
+{
+	return 0;
+}
+#endif /* CONFIG_SERIAL_TAG */
+
+int ft_common_board_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
+
+#endif /* CONFIG_TDX_CFG_BLOCK */
diff --git a/board/toradex/common/tdx-common.h b/board/toradex/common/tdx-common.h
new file mode 100644
index 0000000..f8d78f0
--- /dev/null
+++ b/board/toradex/common/tdx-common.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2016 Toradex, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TDX_COMMON_H
+#define _TDX_COMMON_H
+
+#define TORADEX_USB_PRODUCT_NUM_OFFSET	0x4000
+#define TDX_USB_VID			0x1B67
+
+int ft_common_board_setup(void *blob, bd_t *bd);
+
+#endif /* _TDX_COMMON_H */
diff --git a/board/tplink/wdr4300/wdr4300.c b/board/tplink/wdr4300/wdr4300.c
index 6e070fd..0f59648 100644
--- a/board/tplink/wdr4300/wdr4300.c
+++ b/board/tplink/wdr4300/wdr4300.c
@@ -34,8 +34,7 @@ static void wdr4300_usb_start(void)
 static inline void wdr4300_usb_start(void) {}
 #endif
 
-#ifdef CONFIG_BOARD_EARLY_INIT_F
-int board_early_init_f(void)
+void wdr4300_pinmux_config(void)
 {
 	void __iomem *regs;
 
@@ -56,9 +55,20 @@ int board_early_init_f(void)
 	writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC3);
 	writel(0x0000004d, regs + AR934X_GPIO_REG_OUT_FUNC4);
 	writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC5);
+}
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+	wdr4300_pinmux_config();
+}
+#endif
 
-#ifdef CONFIG_DEBUG_UART
-	debug_uart_init();
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifndef CONFIG_DEBUG_UART_BOARD_INIT
+	wdr4300_pinmux_config();
 #endif
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/board/tqc/tqm5200/Kconfig b/board/tqc/tqm5200/Kconfig
deleted file mode 100644
index 738dc80..0000000
--- a/board/tqc/tqm5200/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-if TARGET_CHARON
-
-config SYS_BOARD
-	default "tqm5200"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "charon"
-
-endif
-
-if TARGET_TQM5200
-
-config SYS_BOARD
-	default "tqm5200"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM5200"
-
-endif
diff --git a/board/tqc/tqm5200/MAINTAINERS b/board/tqc/tqm5200/MAINTAINERS
deleted file mode 100644
index 12d143d..0000000
--- a/board/tqc/tqm5200/MAINTAINERS
+++ /dev/null
@@ -1,23 +0,0 @@
-TQM5200 BOARD
-#M:	-
-S:	Maintained
-F:	board/tqc/tqm5200/
-F:	include/configs/aev.h
-F:	configs/aev_defconfig
-F:	include/configs/TQM5200.h
-F:	configs/cam5200_defconfig
-F:	configs/cam5200_niosflash_defconfig
-F:	configs/fo300_defconfig
-F:	configs/MiniFAP_defconfig
-F:	configs/TQM5200_defconfig
-F:	configs/TQM5200_B_defconfig
-F:	configs/TQM5200_B_HIGHBOOT_defconfig
-F:	configs/TQM5200_STK100_defconfig
-F:	configs/TQM5200S_defconfig
-F:	configs/TQM5200S_HIGHBOOT_defconfig
-
-CHARON BOARD
-M:	Heiko Schocher <hs@denx.de>
-S:	Maintained
-F:	include/configs/charon.h
-F:	configs/charon_defconfig
diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile
deleted file mode 100644
index f7c97b7..0000000
--- a/board/tqc/tqm5200/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= tqm5200.o cmd_stk52xx.o cam5200_flash.o
diff --git a/board/tqc/tqm5200/cam5200_flash.c b/board/tqc/tqm5200/cam5200_flash.c
deleted file mode 100644
index c3ae5c0..0000000
--- a/board/tqc/tqm5200/cam5200_flash.c
+++ /dev/null
@@ -1,768 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <asm/processor.h>
-
-#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
-
-#if 0
-#define DEBUGF(x...) printf(x)
-#else
-#define DEBUGF(x...)
-#endif
-
-#define swap16(x) __swab16(x)
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
-
-/*
- * CAM5200 is a TQM5200B based board. Additionally it also features
- * a NIOS cpu. The NIOS CPU peripherals are accessible through MPC5xxx
- * Local Bus on CS5. This includes 32 bit wide RAM and SRAM as well as
- * 16 bit wide flash device. Big Endian order on a 32 bit CS5 makes
- * access to flash chip slightly more complicated as additional byte
- * swapping is necessary within each 16 bit wide flash 'word'.
- *
- * This driver's task is to handle both flash devices: 32 bit TQM5200B
- * flash chip and 16 bit NIOS cpu flash chip. In the below
- * flash_addr_table table we use least significant address bit to mark
- * 16 bit flash bank and two sets of routines *_32 and *_16 to handle
- * specifics of both flashes.
- */
-static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
-	{CONFIG_SYS_BOOTCS_START, CONFIG_SYS_CS5_START | 1}
-};
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word(flash_info_t * info, ulong dest, ulong data);
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static int write_word_32(flash_info_t * info, ulong dest, ulong data);
-static int write_word_16(flash_info_t * info, ulong dest, ulong data);
-static int flash_erase_32(flash_info_t * info, int s_first, int s_last);
-static int flash_erase_16(flash_info_t * info, int s_first, int s_last);
-static ulong flash_get_size_32(vu_long * addr, flash_info_t * info);
-static ulong flash_get_size_16(vu_long * addr, flash_info_t * info);
-#endif
-
-void flash_print_info(flash_info_t * info)
-{
-	int i, k;
-	int size, erased;
-	volatile unsigned long *flash;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-		case FLASH_MAN_AMD:
-			printf("AMD ");
-			break;
-		case FLASH_MAN_FUJ:
-			printf("FUJITSU ");
-			break;
-		default:
-			printf("Unknown Vendor ");
-			break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-		case FLASH_S29GL128N:
-			printf ("S29GL128N (256 Mbit, uniform sector size)\n");
-			break;
-		case FLASH_AM320B:
-			printf ("29LV320B (32 Mbit, bottom boot sect)\n");
-			break;
-		case FLASH_AM320T:
-			printf ("29LV320T (32 Mbit, top boot sect)\n");
-			break;
-		default:
-			printf("Unknown Chip Type\n");
-			break;
-	}
-
-	printf("  Size: %ld KB in %d Sectors\n",
-			info->size >> 10, info->sector_count);
-
-	printf("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		/*
-		 * Check if whole sector is erased
-		 */
-		if (i != (info->sector_count - 1))
-			size = info->start[i + 1] - info->start[i];
-		else
-			size = info->start[0] + info->size - info->start[i];
-
-		erased = 1;
-		flash = (volatile unsigned long *)info->start[i];
-		size = size >> 2;	/* divide by 4 for longword access */
-
-		for (k = 0; k < size; k++) {
-			if (*flash++ != 0xffffffff) {
-				erased = 0;
-				break;
-			}
-		}
-
-		if ((i % 5) == 0)
-			printf("\n   ");
-
-		printf(" %08lX%s%s", info->start[i],
-				erased ? " E" : "  ",
-				info->protect[i] ? "RO " : "   ");
-	}
-	printf("\n");
-	return;
-}
-
-
-/*
- * The following code cannot be run from FLASH!
- */
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-{
-
-	DEBUGF("get_size: FLASH ADDR %08lx\n", addr);
-
-	/* bit 0 used for big flash marking */
-	if ((ulong)addr & 0x1)
-		return flash_get_size_16((vu_long *)((ulong)addr & 0xfffffffe), info);
-	else
-		return flash_get_size_32(addr, info);
-}
-
-static ulong flash_get_size_32(vu_long * addr, flash_info_t * info)
-#else
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-#endif
-{
-	short i;
-	CONFIG_SYS_FLASH_WORD_SIZE value;
-	ulong base = (ulong) addr;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
-
-	DEBUGF("get_size32: FLASH ADDR: %08x\n", (unsigned)addr);
-
-	/* Write auto select command: read Manufacturer ID */
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
-	udelay(1000);
-
-	value = addr2[0];
-	DEBUGF("FLASH MANUFACT: %x\n", value);
-
-	switch (value) {
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
-			info->flash_id = FLASH_MAN_AMD;
-			break;
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			info->sector_count = 0;
-			info->size = 0;
-			return (0);	/* no or unknown flash  */
-	}
-
-	value = addr2[1];	/* device ID            */
-	DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
-	switch (value) {
-		case AMD_ID_MIRROR:
-			DEBUGF("Mirror Bit flash: addr[14] = %08lX  addr[15] = %08lX\n",
-					addr[14], addr[15]);
-			switch(addr[14]) {
-				case AMD_ID_GL128N_2:
-					if (addr[15] != AMD_ID_GL128N_3) {
-						DEBUGF("Chip: S29GL128N -> unknown\n");
-						info->flash_id = FLASH_UNKNOWN;
-					} else {
-						DEBUGF("Chip: S29GL128N\n");
-						info->flash_id += FLASH_S29GL128N;
-						info->sector_count = 128;
-						info->size = 0x02000000;
-					}
-					break;
-				default:
-					info->flash_id = FLASH_UNKNOWN;
-					return(0);
-			}
-			break;
-
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			return (0);	/* => no or unknown flash */
-	}
-
-	/* set up sector start address table */
-	for (i = 0; i < info->sector_count; i++)
-		info->start[i] = base + (i * 0x00040000);
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
-
-		info->protect[i] = addr2[2] & 1;
-	}
-
-	/* issue bank reset to return to read mode */
-	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
-
-	return (info->size);
-}
-
-static int wait_for_DQ7_32(flash_info_t * info, int sect)
-{
-	ulong start, now, last;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
-		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-	start = get_timer(0);
-	last = start;
-	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
-			(CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf("Timeout\n");
-			return -1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc('.');
-			last = now;
-		}
-	}
-	return 0;
-}
-
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
-		return flash_erase_16(info, s_first, s_last);
-	} else {
-		return flash_erase_32(info, s_first, s_last);
-	}
-}
-
-static int flash_erase_32(flash_info_t * info, int s_first, int s_last)
-#else
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-#endif
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
-	int flag, prot, sect;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN)
-			printf("- missing\n");
-		else
-			printf("- no sectors to erase\n");
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect])
-			prot++;
-	}
-
-	if (prot)
-		printf("- Warning: %d protected sectors will not be erased!", prot);
-
-	printf("\n");
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
-
-			/*
-			 * Wait for each sector to complete, it's more
-			 * reliable.  According to AMD Spec, you must
-			 * issue all erase commands within a specified
-			 * timeout.  This has been seen to fail, especially
-			 * if printf()s are included (for debug)!!
-			 */
-			wait_for_DQ7_32(info, sect);
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay(1000);
-
-	/* reset to read mode */
-	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
-
-	printf(" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp)
-			data = (data << 8) | (*(uchar *) cp);
-
-		for (; i < 4 && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-
-		for (; cnt == 0 && i < 4; ++i, ++cp)
-			data = (data << 8) | (*(uchar *) cp);
-
-		if ((rc = write_word(info, wp, data)) != 0)
-			return (rc);
-
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i = 0; i < 4; ++i)
-			data = (data << 8) | *src++;
-
-		if ((rc = write_word(info, wp, data)) != 0)
-			return (rc);
-
-		wp += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0)
-		return (0);
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < 4; ++i, ++cp)
-		data = (data << 8) | (*(uchar *) cp);
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-static int write_word(flash_info_t * info, ulong dest, ulong data)
-{
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
-		return write_word_16(info, dest, data);
-	} else {
-		return write_word_32(info, dest, data);
-	}
-}
-
-static int write_word_32(flash_info_t * info, ulong dest, ulong data)
-#else
-static int write_word(flash_info_t * info, ulong dest, ulong data)
-#endif
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
-	ulong *datap = &data;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 =
-			(volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap;
-	ulong start;
-	int i, flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *)dest) & data) != data)
-		return (2);
-
-	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
-
-		dest2[i] = data2[i];
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		/* data polling for D7 */
-		start = get_timer(0);
-		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
-				(data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
-
-			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
-				return (1);
-		}
-	}
-
-	return (0);
-}
-
-#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
-
-#undef  CONFIG_SYS_FLASH_WORD_SIZE
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size_16(vu_long * addr, flash_info_t * info)
-{
-	short i;
-	CONFIG_SYS_FLASH_WORD_SIZE value;
-	ulong base = (ulong) addr;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
-
-	DEBUGF("get_size16: FLASH ADDR: %08x\n", (unsigned)addr);
-
-	/* issue bank reset to return to read mode */
-	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
-	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
-	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90009000;
-	udelay(1000);
-
-	value = swap16(addr2[0]);
-	DEBUGF("FLASH MANUFACT: %x\n", value);
-
-	switch (value) {
-		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
-			info->flash_id = FLASH_MAN_AMD;
-			break;
-		case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
-			info->flash_id = FLASH_MAN_FUJ;
-			break;
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			info->sector_count = 0;
-			info->size = 0;
-			return (0);	/* no or unknown flash  */
-	}
-
-	value = swap16(addr2[1]);	/* device ID            */
-	DEBUGF("\nFLASH DEVICEID: %x\n", value);
-
-	switch (value) {
-		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
-			info->flash_id += FLASH_AM320B;
-			info->sector_count = 71;
-			info->size = 0x00400000;
-			break;	/* => 4 MB	*/
-		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
-			info->flash_id += FLASH_AM320T;
-			info->sector_count = 71;
-			info->size = 0x00400000;
-			break;	/* => 4 MB	*/
-		default:
-			info->flash_id = FLASH_UNKNOWN;
-			return (0);	/* => no or unknown flash */
-	}
-
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type        */
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00002000;
-		info->start[2] = base + 0x00004000;
-		info->start[3] = base + 0x00006000;
-		info->start[4] = base + 0x00008000;
-		info->start[5] = base + 0x0000a000;
-		info->start[6] = base + 0x0000c000;
-		info->start[7] = base + 0x0000e000;
-
-		for (i = 8; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00010000) - 0x00070000;
-	} else {
-		/* set sector offsets for top boot block type           */
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00002000;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000a000;
-		info->start[i--] = base + info->size - 0x0000c000;
-		info->start[i--] = base + info->size - 0x0000e000;
-
-		for (; i >= 0; i--)
-			info->start[i] = base + i * 0x00010000;
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
-
-		info->protect[i] = addr2[2] & 1;
-	}
-
-	/* issue bank reset to return to read mode */
-	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;
-
-	return (info->size);
-}
-
-static int wait_for_DQ7_16(flash_info_t * info, int sect)
-{
-	ulong start, now, last;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
-		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-	start = get_timer(0);
-	last = start;
-	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) !=
-			(CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf("Timeout\n");
-			return -1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc('.');
-			last = now;
-		}
-	}
-	return 0;
-}
-
-static int flash_erase_16(flash_info_t * info, int s_first, int s_last)
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
-	int flag, prot, sect;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN)
-			printf("- missing\n");
-		else
-			printf("- no sectors to erase\n");
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect])
-			prot++;
-	}
-
-	if (prot)
-		printf("- Warning: %d protected sectors will not be erased!",	prot);
-
-	printf("\n");
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
-
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000;
-			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
-			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
-			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30003000;	/* sector erase */
-
-			/*
-			 * Wait for each sector to complete, it's more
-			 * reliable.  According to AMD Spec, you must
-			 * issue all erase commands within a specified
-			 * timeout.  This has been seen to fail, especially
-			 * if printf()s are included (for debug)!!
-			 */
-			wait_for_DQ7_16(info, sect);
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay(1000);
-
-	/* reset to read mode */
-	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;	/* reset bank */
-
-	printf(" done\n");
-	return 0;
-}
-
-static int write_word_16(flash_info_t * info, ulong dest, ulong data)
-{
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
-	ulong *datap = &data;
-	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 =
-			(volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap;
-	ulong start;
-	int i;
-
-	/* Check if Flash is (sufficiently) erased */
-	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
-		if ((dest2[i] & swap16(data2[i])) != swap16(data2[i]))
-			return (2);
-	}
-
-	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
-		int flag;
-
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts();
-
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
-		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
-		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA000A000;
-
-		dest2[i] = swap16(data2[i]);
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		/* data polling for D7 */
-		start = get_timer(0);
-		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) !=
-				(swap16(data2[i]) & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000)) {
-
-			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-				return (1);
-			}
-		}
-	}
-
-	return (0);
-}
-#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static int write_word(flash_info_t * info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
-	unsigned long total_b = 0;
-	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
-	unsigned short index = 0;
-	int i;
-
-	DEBUGF("\n");
-	DEBUGF("FLASH: Index: %d\n", index);
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-		flash_info[i].sector_count = -1;
-		flash_info[i].size = 0;
-
-		/* check whether the address is 0 */
-		if (flash_addr_table[index][i] == 0)
-			continue;
-
-		/* call flash_get_size() to initialize sector address */
-		size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
-				&flash_info[i]);
-
-		flash_info[i].size = size_b[i];
-
-		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
-					i+1, size_b[i], size_b[i] << 20);
-			flash_info[i].sector_count = -1;
-			flash_info[i].size = 0;
-		}
-
-		/* Monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
-				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
-				    &flash_info[i]);
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
-				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[i]);
-#if defined(CONFIG_ENV_ADDR_REDUND)
-		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
-				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-				    &flash_info[i]);
-#endif
-#endif
-		total_b += flash_info[i].size;
-	}
-
-	return total_b;
-}
-#endif /* if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) */
diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c
deleted file mode 100644
index dc22ee4..0000000
--- a/board/tqc/tqm5200/cmd_stk52xx.c
+++ /dev/null
@@ -1,1228 +0,0 @@
-/*
- * (C) Copyright 2005
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * STK52XX specific functions
- */
-/*#define DEBUG*/
-
-#include <common.h>
-#include <command.h>
-#include <console.h>
-
-#if defined(CONFIG_CMD_BSP)
-
-#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
-#define DEFAULT_VOL	45
-#define DEFAULT_FREQ	500
-#define DEFAULT_DURATION	200
-#define LEFT		1
-#define RIGHT		2
-#define LEFT_RIGHT	3
-#define BL_OFF		0
-#define BL_ON		1
-
-#define SM501_GPIO_CTRL_LOW		0x00000008UL
-#define SM501_GPIO_CTRL_HIGH		0x0000000CUL
-#define SM501_POWER_MODE0_GATE		0x00000040UL
-#define SM501_POWER_MODE1_GATE		0x00000048UL
-#define POWER_MODE_GATE_GPIO_PWM_I2C	0x00000040UL
-#define SM501_GPIO_DATA_LOW		0x00010000UL
-#define SM501_GPIO_DATA_HIGH		0x00010004UL
-#define SM501_GPIO_DATA_DIR_LOW		0x00010008UL
-#define SM501_GPIO_DATA_DIR_HIGH	0x0001000CUL
-#define SM501_PANEL_DISPLAY_CONTROL	0x00080000UL
-
-static int i2s_squarewave(unsigned long duration, unsigned int freq,
-			  unsigned int channel);
-static int i2s_sawtooth(unsigned long duration, unsigned int freq,
-			unsigned int channel);
-static void spi_init(void);
-static int spi_transmit(unsigned char data);
-static void pcm1772_write_reg(unsigned char addr, unsigned char data);
-static void set_attenuation(unsigned char attenuation);
-
-static void spi_init(void)
-{
-	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-
-	/* PSC3 as SPI and GPIOs */
-	gpio->port_config &= 0xFFFFF0FF;
-	gpio->port_config |= 0x00000800;
-	/*
-	 * Its important to use the correct order when initializing the
-	 * registers
-	 */
-	spi->ddr = 0x0F; /* set all SPI pins as output */
-	spi->pdr = 0x08; /* set SS high */
-	spi->cr1 = 0x50; /* SPI is master, SS is general purpose output */
-	spi->cr2 = 0x00; /* normal operation */
-	spi->brr = 0xFF; /* baud rate: IPB clock / 2048 */
-}
-
-static int spi_transmit(unsigned char data)
-{
-	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
-
-	spi->dr = data;
-	/* wait for SPI transmission completed */
-	while (!(spi->sr & 0x80)) {
-		if (spi->sr & 0x40) {	/* if write collision occurred */
-			int dummy;
-
-			/* do dummy read to clear status register */
-			dummy = spi->dr;
-			printf("SPI write collision: dr=0x%x\n", dummy);
-			return -1;
-		}
-	}
-	return (spi->dr);
-}
-
-static void pcm1772_write_reg(unsigned char addr, unsigned char data)
-{
-	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
-
-	spi->pdr = 0x00; /* Set SS low */
-	spi_transmit(addr);
-	spi_transmit(data);
-	/* wait some time to meet MS# hold time of PCM1772 */
-	udelay (1);
-	spi->pdr = 0x08; /* set SS high */
-}
-
-static void set_attenuation(unsigned char attenuation)
-{
-	pcm1772_write_reg(0x01, attenuation); /* left channel */
-	debug ("PCM1772 attenuation left set to %d.\n", attenuation);
-	pcm1772_write_reg(0x02, attenuation); /* right channel */
-	debug ("PCM1772 attenuation right set to %d.\n", attenuation);
-}
-
-void amplifier_init(void)
-{
-	static int init_done = 0;
-	int i;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-
-	/* Do this only once, because of the long time delay */
-	if (!init_done) {
-		/* configure PCM1772 audio format as I2S */
-		pcm1772_write_reg(0x03, 0x01);
-		/* enable audio amplifier */
-		gpio->sint_gpioe |=  0x02;	/* PSC3_5 as GPIO */
-		gpio->sint_ode &= ~0x02;	/* PSC3_5 is not open Drain */
-		gpio->sint_dvo &= ~0x02;	/* PSC3_5 is LOW */
-		gpio->sint_ddr |=  0x02;	/* PSC3_5 as output */
-		/*
-		 * wait some time to allow amplifier to recover from shutdown
-		 * mode.
-		 */
-		for(i = 0; i < 350; i++)
-			udelay(1000);
-		/*
-		 * The used amplifier (LM4867) has a so called "pop and click"
-		 * elmination filter. The input signal of the amplifier must
-		 * exceed a certain level once after power up to activate the
-		 * generation of the output signal. This is achieved by
-		 * sending a low frequent (nearly inaudible) sawtooth with a
-		 * sufficient signal level.
-		 */
-		set_attenuation(50);
-		i2s_sawtooth (200, 5, LEFT_RIGHT);
-		init_done = 1;
-	}
-}
-
-static void i2s_init(void)
-{
-	unsigned long i;
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-
-	gpio->port_config |= 0x00000070; /* PSC2 ports as Codec with MCLK */
-	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
-	psc->sicr = 0x22E00000;		/* 16 bit data; I2S */
-
-	*(vu_long *)(CONFIG_SYS_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK
-						  * 5.617 MHz */
-	*(vu_long *)(CONFIG_SYS_MBAR + 0x214) |= 0x00000040; /* CDM clock enable
-						       * register */
-	psc->ccr = 0x1F03;	/* 16 bit data width; 5.617MHz MCLK */
-	psc->ctur = 0x0F;	/* 16 bit frame width */
-
-	for (i = 0; i < 128; i++)
-		psc->psc_buffer_32 = 0; /* clear tx fifo */
-}
-
-static int i2s_play_wave(unsigned long addr, unsigned long len)
-{
-	unsigned long i;
-	unsigned char *wave_file = (uchar *)addr + 44;	/* quick'n dirty: skip
-							 * wav header*/
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
-
-	/*
-	 * play wave file in memory; bytes/words are be swapped
-	 */
-	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
-
-	for(i = 0;i < (len / 4); i++) {
-		unsigned char swapped[4];
-		unsigned long *p = (unsigned long*)swapped;
-
-		swapped[3] = *wave_file++;
-		swapped[2] = *wave_file++;
-		swapped[1] = *wave_file++;
-		swapped[0] = *wave_file++;
-
-		psc->psc_buffer_32 =  *p;
-
-		while (psc->tfnum > 400) {
-			if(ctrlc())
-				return 0;
-		}
-	}
-	while (psc->tfnum > 0);		/* wait for fifo empty */
-	udelay (100);
-	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
-	return 0;
-}
-
-static int i2s_sawtooth(unsigned long duration, unsigned int freq,
-			unsigned int channel)
-{
-	long i,j;
-	unsigned long data;
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
-
-	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
-
-	/*
-	 * Generate sawtooth. Start with middle level up to highest level. Then
-	 * go to lowest level and back to middle level.
-	 */
-	for(j = 0; j < ((duration * freq) / 1000); j++)	{
-		for(i = 0; i <= 0x7FFF; i += (0x7FFF/(44100/(freq*4))))	{
-			data = (i & 0xFFFF);
-			/* data format: right data left data) */
-			if (channel == LEFT_RIGHT)
-				data |= (data<<16);
-			if (channel == RIGHT)
-				data = (data<<16);
-			psc->psc_buffer_32 = data;
-			while (psc->tfnum > 400);
-		}
-		for(i = 0x7FFF; i >= -0x7FFF; i -= (0xFFFF/(44100/(freq*2)))) {
-			data = (i & 0xFFFF);
-			/* data format: right data left data) */
-			if (channel == LEFT_RIGHT)
-				data |= (data<<16);
-			if (channel == RIGHT)
-				data = (data<<16);
-			psc->psc_buffer_32 = data;
-			while (psc->tfnum > 400);
-		}
-		for(i = -0x7FFF; i <= 0; i += (0x7FFF/(44100/(freq*4)))) {
-			data = (i & 0xFFFF);
-			/* data format: right data left data) */
-			if (channel == LEFT_RIGHT)
-				data |= (data<<16);
-			if (channel == RIGHT)
-				data = (data<<16);
-			psc->psc_buffer_32 = data;
-			while (psc->tfnum > 400);
-		}
-	}
-	while (psc->tfnum > 0);		/* wait for fifo empty */
-	udelay (100);
-	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
-
-	return 0;
-}
-
-static int i2s_squarewave(unsigned long duration, unsigned int freq,
-			 unsigned int channel)
-{
-	long i,j;
-	unsigned long data;
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
-
-	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
-
-	/*
-	 * Generate sqarewave. Start with high level, duty cycle 1:1.
-	 */
-	for(j = 0; j < ((duration * freq) / 1000); j++)	{
-		for(i = 0; i < (44100/(freq*2)); i ++) {
-			data = 0x7FFF;
-			/* data format: right data left data) */
-			if (channel == LEFT_RIGHT)
-				data |= (data<<16);
-			if (channel == RIGHT)
-				data = (data<<16);
-			psc->psc_buffer_32 = data;
-			while (psc->tfnum > 400);
-		}
-		for(i = 0; i < (44100/(freq*2)); i ++) {
-			data = 0x8000;
-			/* data format: right data left data) */
-			if (channel == LEFT_RIGHT)
-				data |= (data<<16);
-			if (channel == RIGHT)
-				data = (data<<16);
-			psc->psc_buffer_32 = data;
-			while (psc->tfnum > 400);
-		}
-	}
-	while (psc->tfnum > 0);		/* wait for fifo empty */
-	udelay (100);
-	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
-
-	return 0;
-}
-
-static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	unsigned long reg, val, duration;
-	char *tmp;
-	unsigned int freq, channel;
-	unsigned char volume;
-	int rcode = 1;
-
-#ifdef CONFIG_STK52XX_REV100
-	printf ("Revision 100 of STK52XX not supported!\n");
-	return 1;
-#endif
-	spi_init();
-	i2s_init();
-	amplifier_init();
-
-	if ((tmp = getenv ("volume")) != NULL) {
-		volume = simple_strtoul (tmp, NULL, 10);
-	} else {
-		volume = DEFAULT_VOL;
-	}
-	set_attenuation(volume);
-
-	switch (argc) {
-	case 0:
-	case 1:
-		return cmd_usage(cmdtp);
-	case 2:
-		if (strncmp(argv[1],"saw",3) == 0) {
-			printf ("Play sawtooth\n");
-			rcode = i2s_sawtooth (DEFAULT_DURATION, DEFAULT_FREQ,
-					      LEFT_RIGHT);
-			return rcode;
-		} else if (strncmp(argv[1],"squ",3) == 0) {
-			printf ("Play squarewave\n");
-			rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ,
-						LEFT_RIGHT);
-			return rcode;
-		}
-
-		return cmd_usage(cmdtp);
-	case 3:
-		if (strncmp(argv[1],"saw",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			printf ("Play sawtooth\n");
-			rcode = i2s_sawtooth (duration, DEFAULT_FREQ,
-					      LEFT_RIGHT);
-			return rcode;
-		} else if (strncmp(argv[1],"squ",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			printf ("Play squarewave\n");
-			rcode = i2s_squarewave (duration, DEFAULT_FREQ,
-						LEFT_RIGHT);
-			return rcode;
-		}
-		return cmd_usage(cmdtp);
-	case 4:
-		if (strncmp(argv[1],"saw",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
-			printf ("Play sawtooth\n");
-			rcode = i2s_sawtooth (duration, freq,
-					      LEFT_RIGHT);
-			return rcode;
-		} else if (strncmp(argv[1],"squ",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
-			printf ("Play squarewave\n");
-			rcode = i2s_squarewave (duration, freq,
-						LEFT_RIGHT);
-			return rcode;
-		} else if (strcmp(argv[1],"pcm1772") == 0) {
-			reg = simple_strtoul(argv[2], NULL, 10);
-			val = simple_strtoul(argv[3], NULL, 10);
-			printf("Set PCM1772 %lu. %lu\n", reg, val);
-			pcm1772_write_reg((uchar)reg, (uchar)val);
-			return 0;
-		}
-		return cmd_usage(cmdtp);
-	case 5:
-		if (strncmp(argv[1],"saw",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
-			if (strncmp(argv[4],"l",1) == 0)
-				channel = LEFT;
-			else if (strncmp(argv[4],"r",1) == 0)
-				channel = RIGHT;
-			else
-				channel = LEFT_RIGHT;
-			printf ("Play squarewave\n");
-			rcode = i2s_sawtooth (duration, freq,
-					      channel);
-			return rcode;
-		} else if (strncmp(argv[1],"squ",3) == 0) {
-			duration = simple_strtoul(argv[2], NULL, 10);
-			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
-			if (strncmp(argv[4],"l",1) == 0)
-				channel = LEFT;
-			else if (strncmp(argv[4],"r",1) == 0)
-				channel = RIGHT;
-			else
-				channel = LEFT_RIGHT;
-			printf ("Play squarewave\n");
-			rcode = i2s_squarewave (duration, freq,
-						channel);
-			return rcode;
-		}
-		return cmd_usage(cmdtp);
-	}
-	printf ("Usage:\nsound cmd [arg1] [arg2] ...\n");
-	return 1;
-}
-
-static int cmd_wav(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	unsigned long length, addr;
-	unsigned char volume;
-	int rcode = 1;
-	char *tmp;
-
-#ifdef CONFIG_STK52XX_REV100
-	printf ("Revision 100 of STK52XX not supported!\n");
-	return 1;
-#endif
-	spi_init();
-	i2s_init();
-	amplifier_init();
-
-	switch (argc) {
-
-	case 3:
-		length = simple_strtoul(argv[2], NULL, 16);
-		addr = simple_strtoul(argv[1], NULL, 16);
-		break;
-
-	case 2:
-		if ((tmp = getenv ("filesize")) != NULL) {
-			length = simple_strtoul (tmp, NULL, 16);
-		} else {
-			puts ("No filesize provided\n");
-			return 1;
-		}
-		addr = simple_strtoul(argv[1], NULL, 16);
-
-	case 1:
-		if ((tmp = getenv ("filesize")) != NULL) {
-			length = simple_strtoul (tmp, NULL, 16);
-		} else {
-			puts ("No filesize provided\n");
-			return 1;
-		}
-		if ((tmp = getenv ("loadaddr")) != NULL) {
-			addr = simple_strtoul (tmp, NULL, 16);
-		} else {
-			puts ("No loadaddr provided\n");
-			return 1;
-		}
-		break;
-
-	default:
-		printf("Usage:\nwav <addr> <length[s]\n");
-		return 1;
-		break;
-	}
-
-	if ((tmp = getenv ("volume")) != NULL) {
-		volume = simple_strtoul (tmp, NULL, 10);
-	} else {
-		volume = DEFAULT_VOL;
-	}
-	set_attenuation(volume);
-
-	printf("Play wave file at %lX with length %lX\n", addr, length);
-	rcode = i2s_play_wave(addr, length);
-
-	return rcode;
-}
-
-static int cmd_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	unsigned char volume;
-	unsigned int channel;
-	int rcode;
-	char *tmp;
-
-#ifdef CONFIG_STK52XX_REV100
-	printf ("Revision 100 of STK52XX not supported!\n");
-	return 1;
-#endif
-	spi_init();
-	i2s_init();
-	amplifier_init();
-
-	switch (argc) {
-	case 0:
-	case 1:
-		channel = LEFT_RIGHT;
-		break;
-	case 2:
-		if (strncmp(argv[1],"l",1) == 0)
-			channel = LEFT;
-		else if (strncmp(argv[1],"r",1) == 0)
-			channel = RIGHT;
-		else
-			channel = LEFT_RIGHT;
-		break;
-	default:
-		return cmd_usage(cmdtp);
-	}
-
-	if ((tmp = getenv ("volume")) != NULL) {
-		volume = simple_strtoul (tmp, NULL, 10);
-	} else {
-		volume = DEFAULT_VOL;
-	}
-	set_attenuation(volume);
-
-	printf("Beep on ");
-	if (channel == LEFT)
-		printf ("left ");
-	else if (channel == RIGHT)
-		printf ("right ");
-	else
-		printf ("left and right ");
-	printf ("channel\n");
-
-	rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, channel);
-
-	return rcode;
-}
-#endif
-
-#if defined(CONFIG_STK52XX)
-void led_init(void)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-
-	/* configure PSC3 for SPI and GPIO */
-	gpio->port_config &= ~(0x00000F00);
-	gpio->port_config |=   0x00000800;
-
-	gpio->simple_gpioe &= ~(0x00000F00);
-	gpio->simple_gpioe |=   0x00000F00;
-
-	gpio->simple_ddr &= ~(0x00000F00);
-	gpio->simple_ddr |=   0x00000F00;
-
-	/* configure timer 4-7 for simple GPIO output */
-	gpt->gpt4.emsr |=  0x00000024;
-	gpt->gpt5.emsr |=  0x00000024;
-	gpt->gpt6.emsr |=  0x00000024;
-	gpt->gpt7.emsr |=  0x00000024;
-
-#ifndef CONFIG_TQM5200S
-	/* enable SM501 GPIO control (in both power modes) */
-	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
-		POWER_MODE_GATE_GPIO_PWM_I2C;
-	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
-		POWER_MODE_GATE_GPIO_PWM_I2C;
-
-	/* configure SM501 gpio pins 24-27 as output */
-	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_CTRL_LOW) &= ~(0xF << 24);
-	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_LOW) |= (0xF << 24);
-
-	/* configure SM501 gpio pins 48-51 as output */
-	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16);
-#endif /* !CONFIG_TQM5200S */
-}
-
-/*
- * return 1 if led number unknown
- * return 0 else
- */
-int do_led(char * const argv[])
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-
-	switch	(simple_strtoul(argv[2], NULL, 10)) {
-
-	case 0:
-		if (strcmp (argv[3], "on") == 0) {
-			gpio->simple_dvo |=   (1 << 8);
-		} else {
-			gpio->simple_dvo &= ~(1 << 8);
-		}
-		break;
-
-	case 1:
-		if (strcmp (argv[3], "on") == 0) {
-			gpio->simple_dvo |=   (1 << 9);
-		} else {
-			gpio->simple_dvo &= ~(1 << 9);
-		}
-		break;
-
-	case 2:
-		if (strcmp (argv[3], "on") == 0) {
-			gpio->simple_dvo |=   (1 << 10);
-		} else {
-			gpio->simple_dvo &= ~(1 << 10);
-		}
-		break;
-
-	case 3:
-		if (strcmp (argv[3], "on") == 0) {
-			gpio->simple_dvo |=   (1 << 11);
-		} else {
-			gpio->simple_dvo &= ~(1 << 11);
-		}
-		break;
-
-	case 4:
-		if (strcmp (argv[3], "on") == 0) {
-			gpt->gpt4.emsr |=  (1 << 4);
-		} else {
-			gpt->gpt4.emsr &=  ~(1 << 4);
-		}
-		break;
-
-	case 5:
-		if (strcmp (argv[3], "on") == 0) {
-			gpt->gpt5.emsr |=  (1 << 4);
-		} else {
-			gpt->gpt5.emsr &=  ~(1 << 4);
-		}
-		break;
-
-	case 6:
-		if (strcmp (argv[3], "on") == 0) {
-			gpt->gpt6.emsr |=  (1 << 4);
-		} else {
-			gpt->gpt6.emsr &=  ~(1 << 4);
-		}
-		break;
-
-	case 7:
-		if (strcmp (argv[3], "on") == 0) {
-			gpt->gpt7.emsr |=  (1 << 4);
-		} else {
-			gpt->gpt7.emsr &=  ~(1 << 4);
-		}
-		break;
-#ifndef CONFIG_TQM5200S
-	case 24:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
-				(0x1 << 24);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
-				~(0x1 << 24);
-		}
-		break;
-
-	case 25:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
-				(0x1 << 25);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
-				~(0x1 << 25);
-		}
-		break;
-
-	case 26:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
-				(0x1 << 26);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
-				~(0x1 << 26);
-		}
-		break;
-
-	case 27:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
-				(0x1 << 27);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
-				~(0x1 << 27);
-		}
-		break;
-
-	case 48:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
-				(0x1 << 16);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
-				~(0x1 << 16);
-		}
-		break;
-
-	case 49:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
-				(0x1 << 17);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
-				~(0x1 << 17);
-		}
-		break;
-
-	case 50:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
-				(0x1 << 18);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
-				~(0x1 << 18);
-		}
-		break;
-
-	case 51:
-		if (strcmp (argv[3], "on") == 0) {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
-				(0x1 << 19);
-		} else {
-			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
-				~(0x1 << 19);
-		}
-		break;
-#endif /* !CONFIG_TQM5200S */
-	default:
-		printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]);
-		return 1;
-	}
-
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
-/*
- * return 1 on CAN initialization failure
- * return 0 if no failure
- */
-int can_init(void)
-{
-	static int init_done = 0;
-	int i;
-	struct mpc5xxx_mscan *can1 =
-		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900);
-	struct mpc5xxx_mscan *can2 =
-		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980);
-
-	/* GPIO configuration of the CAN pins is done in TQM5200.h */
-
-	if (!init_done) {
-		/* init CAN 1 */
-		can1->canctl1 |= 0x80;	/* CAN enable */
-		udelay(100);
-
-		i = 0;
-		can1->canctl0 |= 0x02;	/* sleep mode */
-		/* wait until sleep mode reached */
-		while (!(can1->canctl1 & 0x02)) {
-			udelay(10);
-		i++;
-		if (i == 10) {
-			printf ("%s: CAN1 initialize error, "
-				"can not enter sleep mode!\n",
-				__FUNCTION__);
-			return 1;
-		}
-		}
-		i = 0;
-		can1->canctl0 = 0x01;	/* enter init mode */
-		/* wait until init mode reached */
-		while (!(can1->canctl1 & 0x01)) {
-			udelay(10);
-			i++;
-			if (i == 10) {
-				printf ("%s: CAN1 initialize error, "
-					"can not enter init mode!\n",
-					__FUNCTION__);
-				return 1;
-			}
-		}
-		can1->canctl1 = 0x80;
-		can1->canctl1 |= 0x40;
-		can1->canbtr0 = 0x0F;
-		can1->canbtr1 = 0x7F;
-		can1->canidac &= ~(0x30);
-		can1->canidar1 = 0x00;
-		can1->canidar3 = 0x00;
-		can1->canidar5 = 0x00;
-		can1->canidar7 = 0x00;
-		can1->canidmr0 = 0xFF;
-		can1->canidmr1 = 0xFF;
-		can1->canidmr2 = 0xFF;
-		can1->canidmr3 = 0xFF;
-		can1->canidmr4 = 0xFF;
-		can1->canidmr5 = 0xFF;
-		can1->canidmr6 = 0xFF;
-		can1->canidmr7 = 0xFF;
-
-		i = 0;
-		can1->canctl0 &= ~(0x01);	/* leave init mode */
-		can1->canctl0 &= ~(0x02);
-		/* wait until init and sleep mode left */
-		while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) {
-			udelay(10);
-			i++;
-			if (i == 10) {
-				printf ("%s: CAN1 initialize error, "
-					"can not leave init/sleep mode!\n",
-					__FUNCTION__);
-				return 1;
-			}
-		}
-
-		/* init CAN 2 */
-		can2->canctl1 |= 0x80;	/* CAN enable */
-		udelay(100);
-
-		i = 0;
-		can2->canctl0 |= 0x02;	/* sleep mode */
-		/* wait until sleep mode reached */
-		while (!(can2->canctl1 & 0x02))	{
-			udelay(10);
-			i++;
-			if (i == 10) {
-				printf ("%s: CAN2 initialize error, "
-					"can not enter sleep mode!\n",
-					__FUNCTION__);
-				return 1;
-			}
-		}
-		i = 0;
-		can2->canctl0 = 0x01;	/* enter init mode */
-		/* wait until init mode reached */
-		while (!(can2->canctl1 & 0x01))	{
-			udelay(10);
-			i++;
-			if (i == 10) {
-				printf ("%s: CAN2 initialize error, "
-					"can not enter init mode!\n",
-					__FUNCTION__);
-				return 1;
-			}
-		}
-		can2->canctl1 = 0x80;
-		can2->canctl1 |= 0x40;
-		can2->canbtr0 = 0x0F;
-		can2->canbtr1 = 0x7F;
-		can2->canidac &= ~(0x30);
-		can2->canidar1 = 0x00;
-		can2->canidar3 = 0x00;
-		can2->canidar5 = 0x00;
-		can2->canidar7 = 0x00;
-		can2->canidmr0 = 0xFF;
-		can2->canidmr1 = 0xFF;
-		can2->canidmr2 = 0xFF;
-		can2->canidmr3 = 0xFF;
-		can2->canidmr4 = 0xFF;
-		can2->canidmr5 = 0xFF;
-		can2->canidmr6 = 0xFF;
-		can2->canidmr7 = 0xFF;
-		can2->canctl0 &= ~(0x01);	/* leave init mode */
-		can2->canctl0 &= ~(0x02);
-
-		i = 0;
-		/* wait until init mode left */
-		while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) {
-			udelay(10);
-			i++;
-			if (i == 10) {
-				printf ("%s: CAN2 initialize error, "
-					"can not leave init/sleep mode!\n",
-					__FUNCTION__);
-				return 1;
-			}
-		}
-		init_done = 1;
-	}
-	return 0;
-}
-
-/*
- * return 1 on CAN failure
- * return 0 if no failure
- */
-int do_can(char * const argv[])
-{
-	int i;
-	struct mpc5xxx_mscan *can1 =
-		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900);
-	struct mpc5xxx_mscan *can2 =
-		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980);
-
-	/* send a message on CAN1 */
-	can1->cantbsel = 0x01;
-	can1->cantxfg.idr[0] = 0x55;
-	can1->cantxfg.idr[1] = 0x00;
-	can1->cantxfg.idr[1] &= ~0x8;
-	can1->cantxfg.idr[1] &= ~0x10;
-	can1->cantxfg.dsr[0] = 0xCC;
-	can1->cantxfg.dlr = 1;
-	can1->cantxfg.tbpr = 0;
-	can1->cantflg = 0x01;
-
-	i = 0;
-	while ((can1->cantflg & 0x01) == 0) {
-		i++;
-		if (i == 10) {
-			printf ("%s: CAN1 send timeout, "
-				"can not send message!\n",
-				__FUNCTION__);
-			return 1;
-		}
-		udelay(1000);
-	}
-	udelay(1000);
-
-	i = 0;
-	while (!(can2->canrflg & 0x01))	{
-		i++;
-		if (i == 10) {
-			printf ("%s: CAN2 receive timeout, "
-				"no message received!\n",
-				__FUNCTION__);
-			return 1;
-		}
-		udelay(1000);
-	}
-
-	if (can2->canrxfg.dsr[0] != 0xCC) {
-		printf ("%s: CAN2 receive error, "
-			 "data mismatch!\n",
-			__FUNCTION__);
-		return 1;
-	}
-
-	/* send a message on CAN2 */
-	can2->cantbsel = 0x01;
-	can2->cantxfg.idr[0] = 0x55;
-	can2->cantxfg.idr[1] = 0x00;
-	can2->cantxfg.idr[1] &= ~0x8;
-	can2->cantxfg.idr[1] &= ~0x10;
-	can2->cantxfg.dsr[0] = 0xCC;
-	can2->cantxfg.dlr = 1;
-	can2->cantxfg.tbpr = 0;
-	can2->cantflg = 0x01;
-
-	i = 0;
-	while ((can2->cantflg & 0x01) == 0) {
-		i++;
-		if (i == 10) {
-			printf ("%s: CAN2 send error, "
-				"can not send message!\n",
-				__FUNCTION__);
-			return 1;
-		}
-		udelay(1000);
-	}
-	udelay(1000);
-
-	i = 0;
-	while (!(can1->canrflg & 0x01))	{
-		i++;
-		if (i == 10) {
-			printf ("%s: CAN1 receive timeout, "
-				"no message received!\n",
-				__FUNCTION__);
-			return 1;
-		}
-		udelay(1000);
-	}
-
-	if (can1->canrxfg.dsr[0] != 0xCC) {
-		printf ("%s: CAN1 receive error 0x%02x\n",
-			__FUNCTION__, (can1->canrxfg.dsr[0]));
-		return 1;
-	}
-
-	return 0;
-}
-
-/*
- * return 1 if rs232 port unknown
- * return 2 on txd/rxd failure (only rs232 2)
- * return 3 on rts/cts failure
- * return 0 if no failure
- */
-int do_rs232(char * const argv[])
-{
-	int error_status = 0;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
-
-	switch	(simple_strtoul(argv[2], NULL, 10)) {
-
-	case 1:
-		/* check RTS <-> CTS loop */
-		/* set rts to 0 */
-		psc1->op1 |= 0x01;
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		/* check status at cts */
-		if ((psc1->ip & 0x01) != 0) {
-			error_status = 3;
-			printf ("%s: failure at rs232_1, cts status is %d "
-				"(should be 0)\n",
-				__FUNCTION__, (psc1->ip & 0x01));
-		}
-
-		/* set rts to 1 */
-		psc1->op0 |= 0x01;
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		/* check status at cts */
-		if ((psc1->ip & 0x01) != 1) {
-			error_status = 3;
-			printf ("%s: failure at rs232_1, cts status is %d "
-				"(should be 1)\n",
-				__FUNCTION__, (psc1->ip & 0x01));
-		}
-
-		break;
-
-	case 2:
-		/* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */
-		gpio->simple_ddr &= ~(0x00000F00);
-		gpio->simple_ddr |=   0x00000500;
-
-		/* check TXD <-> RXD loop */
-		/* set TXD to 1 */
-		gpio->simple_dvo |=   (1 << 8);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000200) != 0x00000200) {
-			error_status = 2;
-			printf ("%s: failure at rs232_2, rxd status is %d "
-				"(should be 1)\n",
-				__FUNCTION__,
-				(gpio->simple_ival & 0x00000200) >> 9);
-		}
-
-		/* set TXD to 0 */
-		gpio->simple_dvo &= ~(1 << 8);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000200) != 0x00000000) {
-			error_status = 2;
-			printf ("%s: failure at rs232_2, rxd status is %d "
-				"(should be 0)\n",
-				__FUNCTION__,
-				(gpio->simple_ival & 0x00000200) >> 9);
-		}
-
-		/* check RTS <-> CTS loop */
-		/* set RTS to 1 */
-		gpio->simple_dvo |=   (1 << 10);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000800) != 0x00000800) {
-			error_status = 3;
-			printf ("%s: failure at rs232_2, cts status is %d "
-				"(should be 1)\n",
-				__FUNCTION__,
-				(gpio->simple_ival & 0x00000800) >> 11);
-		}
-
-		/* set RTS to 0 */
-		gpio->simple_dvo &= ~(1 << 10);
-
-		/* wait some time before requesting status */
-		udelay(10);
-
-		if ((gpio->simple_ival & 0x00000800) != 0x00000000) {
-			error_status = 3;
-			printf ("%s: failure at rs232_2, cts status is %d "
-				"(should be 0)\n",
-				__FUNCTION__,
-				(gpio->simple_ival & 0x00000800) >> 11);
-		}
-
-		/* set PSC3_0, PSC3_1, PSC3_2 and PSC3_3 as output */
-		gpio->simple_ddr &= ~(0x00000F00);
-		gpio->simple_ddr |=   0x00000F00;
-		break;
-
-	default:
-		printf ("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]);
-		error_status = 1;
-		break;
-	}
-
-	return error_status;
-}
-
-#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S)
-static void sm501_backlight (unsigned int state)
-{
-	if (state == BL_ON) {
-		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |=
-			(1 << 26) | (1 << 27);
-	} else if (state == BL_OFF)
-		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
-			~((1 << 26) | (1 << 27));
-}
-#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */
-
-int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int rcode;
-
-#ifdef CONFIG_STK52XX_REV100
-	printf ("Revision 100 of STK52XX not supported!\n");
-	return 1;
-#endif
-#if defined(CONFIG_STK52XX)
-	led_init();
-#endif
-	can_init();
-
-	switch (argc) {
-
-	case 0:
-	case 1:
-		break;
-
-	case 2:
-		if (strncmp (argv[1], "can", 3) == 0) {
-			rcode = do_can (argv);
-			if (rcode == 0)
-				printf ("OK\n");
-			else
-				printf ("Error\n");
-			return rcode;
-		}
-		break;
-
-	case 3:
-		if (strncmp (argv[1], "rs232", 3) == 0) {
-			rcode = do_rs232 (argv);
-			if (rcode == 0)
-				printf ("OK\n");
-			else
-				printf ("Error\n");
-			return rcode;
-#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S)
-		} else if (strncmp (argv[1], "backlight", 4) == 0) {
-			if (strncmp (argv[2], "on", 2) == 0) {
-				sm501_backlight (BL_ON);
-				return 0;
-			}
-			else if (strncmp (argv[2], "off", 3) == 0) {
-				sm501_backlight (BL_OFF);
-				return 0;
-			}
-#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */
-		}
-		break;
-
-#if defined(CONFIG_STK52XX)
-	case 4:
-		if (strcmp (argv[1], "led") == 0) {
-			return (do_led (argv));
-		}
-		break;
-#endif
-
-	default:
-		break;
-	}
-
-	printf ("Usage:\nfkt cmd [arg1] [arg2] ...\n");
-	return 1;
-}
-
-
-U_BOOT_CMD(
-	sound ,    5,    1,     cmd_sound,
-	"Sound sub-system",
-	"saw [duration] [freq] [channel]\n"
-	"    - generate sawtooth for 'duration' ms with frequency 'freq'\n"
-	"      on left \"l\" or right \"r\" channel\n"
-	"sound square [duration] [freq] [channel]\n"
-	"    - generate squarewave for 'duration' ms with frequency 'freq'\n"
-	"      on left \"l\" or right \"r\" channel\n"
-	"pcm1772 reg val"
-);
-
-U_BOOT_CMD(
-	wav ,    3,    1,     cmd_wav,
-	"play wav file",
-	"[addr] [bytes]\n"
-	"    - play wav file at address 'addr' with length 'bytes'"
-);
-
-U_BOOT_CMD(
-	beep ,    2,    1,     cmd_beep,
-	"play short beep",
-	"[channel]\n"
-	"    - play short beep on \"l\"eft or \"r\"ight channel"
-);
-#endif /* CONFIG_STK52XX  || CONFIG_FO300 */
-
-#if defined(CONFIG_STK52XX)
-U_BOOT_CMD(
-	fkt ,	4,	1,	cmd_fkt,
-	"Function test routines",
-	"led number on/off\n"
-	"     - 'number's like printed on STK52XX board\n"
-	"fkt can\n"
-	"     - loopback plug for X83 required\n"
-	"fkt rs232 number\n"
-	"     - loopback plug(s) for X2 required"
-#ifndef CONFIG_TQM5200S
-	"\n"
-	"fkt backlight on/off\n"
-	"     - switch backlight on or off"
-#endif /* !CONFIG_TQM5200S */
-);
-#elif defined(CONFIG_FO300)
-U_BOOT_CMD(
-	fkt ,	3,	1,	cmd_fkt,
-	"Function test routines",
-	"fkt can\n"
-	"     - loopback plug for X16/X29 required\n"
-	"fkt rs232 number\n"
-	"     - loopback plug(s) for X21/X22 required"
-);
-#endif
-#endif
diff --git a/board/tqc/tqm5200/mt48lc16m16a2-75.h b/board/tqc/tqm5200/mt48lc16m16a2-75.h
deleted file mode 100644
index 3d99796..0000000
--- a/board/tqc/tqm5200/mt48lc16m16a2-75.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SDRAM_DDR	0		/* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE	0x00CD0000
-/* #define SDRAM_MODE	0x008D0000 */ /* CAS latency 2 */
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-/* #define SDRAM_CONFIG1	0xD2222800 */ /* CAS latency 2 */
-/*#define SDRAM_CONFIG1	0xD7322800 */ /* SDRAM controller bug workaround */
-#define SDRAM_CONFIG2	0x8AD70000
-/*#define SDRAM_CONFIG2	0xDDD70000 */ /* SDRAM controller bug workaround */
diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c
deleted file mode 100644
index 8b82c34..0000000
--- a/board/tqc/tqm5200/tqm5200.c
+++ /dev/null
@@ -1,882 +0,0 @@
-/*
- * (C) Copyright 2003-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2004-2006
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <console.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <libfdt.h>
-#include <netdev.h>
-
-#ifdef CONFIG_VIDEO_SM501
-#include <sm501.h>
-#endif
-
-#if defined(CONFIG_MPC5200_DDR)
-#include "mt46v16m16-75.h"
-#else
-#include "mt48lc16m16a2-75.h"
-#endif
-
-#ifdef CONFIG_OF_LIBFDT
-#include <fdt_support.h>
-#endif /* CONFIG_OF_LIBFDT */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_PS2MULT
-void ps2mult_early_init(void);
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) && \
-    defined(CONFIG_VIDEO)
-/*
- * EDID block has been generated using Phoenix EDID Designer 1.3.
- * This tool creates a text file containing:
- *
- * EDID BYTES:
- *
- * 0x   00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
- *     ------------------------------------------------
- *     00 | 00 FF FF FF FF FF FF 00 04 21 00 00 00 00 00 00
- *     10 | 01 00 01 03 00 00 00 00 00 00 00 00 00 00 00 00
- *     20 | 00 00 00 21 00 00 01 01 01 01 01 01 01 01 01 01
- *     30 | 01 01 01 01 01 01 64 00 00 00 00 00 00 00 00 00
- *     40 | 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 00
- *     50 | 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00
- *     60 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10
- *     70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 17
- *
- * Then this data has been manually converted to the char
- * array below.
- */
-static unsigned char edid_buf[128] = {
-	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
-	0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01,
-	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
-	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,
-};
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
-		hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
-		hi_addr_bit;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-#endif
-
-	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
-		hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
-		hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- *	      is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set tap delay */
-	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-#endif
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else {
-		dramsize = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20)) {
-		dramsize = 0;
-	}
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
-			__builtin_ffs(dramsize >> 20) - 1;
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-	}
-
-	/* let SDRAM CS1 start right after CS0 */
-	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
-	}
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else {
-		dramsize2 = test2;
-	}
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20)) {
-		dramsize2 = 0;
-	}
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0) {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
-			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-	} else {
-		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13) {
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	} else {
-		dramsize = 0;
-	}
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
-	if (dramsize2 >= 0x13) {
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	} else {
-		dramsize2 = 0;
-	}
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
-		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
-		__asm__ volatile ("sync");
-	}
-
-#if defined(CONFIG_TQM5200_B)
-	return dramsize + dramsize2;
-#else
-	return dramsize;
-#endif /* CONFIG_TQM5200_B */
-}
-
-int checkboard (void)
-{
-#if defined(CONFIG_TQM5200S)
-# define MODULE_NAME	"TQM5200S"
-#else
-# define MODULE_NAME	"TQM5200"
-#endif
-
-#if defined(CONFIG_STK52XX)
-# define CARRIER_NAME	"STK52xx"
-#elif defined(CONFIG_CAM5200)
-# define CARRIER_NAME	"CAM5200"
-#elif defined(CONFIG_FO300)
-# define CARRIER_NAME	"FO300"
-#elif defined(CONFIG_CHARON)
-# define CARRIER_NAME	"CHARON"
-#else
-# error "UNKNOWN"
-#endif
-
-	puts (	"Board: " MODULE_NAME " (TQ-Components GmbH)\n"
-		"       on a " CARRIER_NAME " carrier board\n");
-
-	return 0;
-}
-
-#undef MODULE_NAME
-#undef CARRIER_NAME
-
-void flash_preinit(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-}
-
-
-#ifdef	CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-#if defined (CONFIG_MINIFAP)
-#define SM501_POWER_MODE0_GATE		0x00000040UL
-#define SM501_POWER_MODE1_GATE		0x00000048UL
-#define POWER_MODE_GATE_GPIO_PWM_I2C	0x00000040UL
-#define SM501_GPIO_DATA_DIR_HIGH	0x0001000CUL
-#define SM501_GPIO_DATA_HIGH		0x00010004UL
-#define SM501_GPIO_51			0x00080000UL
-#endif /* CONFIG MINIFAP */
-
-void init_ide_reset (void)
-{
-	debug ("init_ide_reset\n");
-
-#if defined (CONFIG_MINIFAP)
-	/* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
-
-	/* enable GPIO control (in both power modes) */
-	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
-		POWER_MODE_GATE_GPIO_PWM_I2C;
-	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
-		POWER_MODE_GATE_GPIO_PWM_I2C;
-	/* configure GPIO51 as output */
-	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
-		SM501_GPIO_51;
-#else
-	/* Configure PSC1_4 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
-
-	/* by default the ATA reset is de-asserted */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
-#endif
-}
-
-void ide_set_reset (int idereset)
-{
-	debug ("ide_reset(%d)\n", idereset);
-
-#if defined (CONFIG_MINIFAP)
-	if (idereset) {
-		*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
-			~SM501_GPIO_51;
-	} else {
-		*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
-			SM501_GPIO_51;
-	}
-#else
-	if (idereset) {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
-	} else {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
-	}
-#endif
-}
-#endif
-
-#ifdef CONFIG_POST
-/*
- * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
- * is left open, no keypress is detected.
- */
-int post_hotkeys_pressed(void)
-{
-#ifdef CONFIG_STK52XX
-	struct mpc5xxx_gpio *gpio;
-
-	gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
-
-	/*
-	 * Configure PSC6_0 through PSC6_3 as GPIO.
-	 */
-	gpio->port_config &= ~(0x00700000);
-
-	/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
-	gpio->simple_gpioe |= 0x20000000;
-
-	/* Configure GPIO_IRDA_1 as input */
-	gpio->simple_ddr &= ~(0x20000000);
-
-	return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
-#else
-	return 0;
-#endif
-}
-#endif
-
-#ifdef CONFIG_BOARD_EARLY_INIT_R
-int board_early_init_r (void)
-{
-
-	extern int usb_cpu_init(void);
-
-#ifdef CONFIG_PS2MULT
-	ps2mult_early_init();
-#endif /* CONFIG_PS2MULT */
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-	/* Low level USB init, required for proper kernel operation */
-	usb_cpu_init();
-#endif
-
-	return (0);
-}
-#endif
-
-#ifdef CONFIG_FO300
-int silent_boot (void)
-{
-	vu_long timer3_status;
-
-	/* Configure GPT3 as GPIO input */
-	*(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
-
-	/* Read in TIMER_3 pin status */
-	timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
-
-#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
-	/* Force silent console mode if S1 switch
-	 * is in closed position (TIMER_3 pin status is LOW). */
-	if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
-		return 1;
-#else
-	/* Force silent console mode if S1 switch
-	 * is in open position (TIMER_3 pin status is HIGH). */
-	if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
-		return 1;
-#endif
-
-	return 0;
-}
-
-int board_early_init_f (void)
-{
-	if (silent_boot())
-		gd->flags |= GD_FLG_SILENT;
-
-	return 0;
-}
-#endif	/* CONFIG_FO300 */
-
-#if defined(CONFIG_CHARON)
-#include <i2c.h>
-#include <asm/io.h>
-
-/* The TFP410 registers */
-#define TFP410_REG_VEN_ID_L 0x00
-#define TFP410_REG_VEN_ID_H 0x01
-#define TFP410_REG_DEV_ID_L 0x02
-#define TFP410_REG_DEV_ID_H 0x03
-#define TFP410_REG_REV_ID 0x04
-
-#define TFP410_REG_CTL_1_MODE 0x08
-#define TFP410_REG_CTL_2_MODE 0x09
-#define TFP410_REG_CTL_3_MODE 0x0A
-
-#define TFP410_REG_CFG 0x0B
-
-#define TFP410_REG_DE_DLY 0x32
-#define TFP410_REG_DE_CTL 0x33
-#define TFP410_REG_DE_TOP 0x34
-#define TFP410_REG_DE_CNT_L 0x36
-#define TFP410_REG_DE_CNT_H 0x37
-#define TFP410_REG_DE_LIN_L 0x38
-#define TFP410_REG_DE_LIN_H 0x39
-
-#define TFP410_REG_H_RES_L 0x3A
-#define TFP410_REG_H_RES_H 0x3B
-#define TFP410_REG_V_RES_L 0x3C
-#define TFP410_REG_V_RES_H 0x3D
-
-static int tfp410_read_reg(int reg, uchar *buf)
-{
-	if (i2c_read(CONFIG_SYS_TFP410_ADDR, reg, 1, buf, 1) != 0) {
-		puts ("Error reading the chip.\n");
-		return 1;
-	}
-	return 0;
-}
-
-static int tfp410_write_reg(int reg, uchar buf)
-{
-	if (i2c_write(CONFIG_SYS_TFP410_ADDR, reg, 1, &buf, 1) != 0) {
-		puts ("Error writing the chip.\n");
-		return 1;
-	}
-	return 0;
-}
-
-typedef struct _tfp410_config {
-	int	reg;
-	uchar	val;
-}TFP410_CONFIG;
-
-static TFP410_CONFIG tfp410_configtbl[] = {
-	{TFP410_REG_CTL_1_MODE, 0x37},
-	{TFP410_REG_CTL_2_MODE, 0x20},
-	{TFP410_REG_CTL_3_MODE, 0x80},
-	{TFP410_REG_DE_DLY, 0x90},
-	{TFP410_REG_DE_CTL, 0x00},
-	{TFP410_REG_DE_TOP, 0x23},
-	{TFP410_REG_DE_CNT_H, 0x02},
-	{TFP410_REG_DE_CNT_L, 0x80},
-	{TFP410_REG_DE_LIN_H, 0x01},
-	{TFP410_REG_DE_LIN_L, 0xe0},
-	{-1, 0},
-};
-
-static int charon_last_stage_init(void)
-{
-	volatile struct mpc5xxx_lpb *lpb =
-		(struct mpc5xxx_lpb *) MPC5XXX_LPB;
-	int	oldbus = i2c_get_bus_num();
-	uchar	buf;
-	int	i = 0;
-
-	i2c_set_bus_num(CONFIG_SYS_TFP410_BUS);
-
-	/* check version */
-	if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)
-		return -1;
-	if (!(buf & 0x04))
-		return -1;
-	if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0)
-		return -1;
-	if (!(buf & 0x10))
-		return -1;
-	/* OK, now init the chip */
-	while (tfp410_configtbl[i].reg != -1) {
-		int ret;
-
-		ret = tfp410_write_reg(tfp410_configtbl[i].reg,
-				tfp410_configtbl[i].val);
-		if (ret != 0)
-			return -1;
-		i++;
-	}
-	printf("TFP410 initialized.\n");
-	i2c_set_bus_num(oldbus);
-
-	/* set deadcycle for cs3 to 0 */
-	setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);
-	return 0;
-}
-#endif
-
-int last_stage_init (void)
-{
-	/*
-	 * auto scan for really existing devices and re-set chip select
-	 * configuration.
-	 */
-	u16 save, tmp;
-	int restore;
-
-	/*
-	 * Check for SRAM and SRAM size
-	 */
-
-	/* save original SRAM content  */
-	save = *(volatile u16 *)CONFIG_SYS_CS2_START;
-	restore = 1;
-
-	/* write test pattern to SRAM */
-	*(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
-	__asm__ volatile ("sync");
-	/*
-	 * Put a different pattern on the data lines: otherwise they may float
-	 * long enough to read back what we wrote.
-	 */
-	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
-	if (tmp == 0xA5A5)
-		puts ("!! possible error in SRAM detection\n");
-
-	if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
-		/* no SRAM at all, disable cs */
-		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
-		*(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
-		*(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
-		restore = 0;
-		__asm__ volatile ("sync");
-	} else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
-		/* make sure that we access a mirrored address */
-		*(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
-		__asm__ volatile ("sync");
-		if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
-			/* SRAM size = 512 kByte */
-			*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
-								0x80000);
-			__asm__ volatile ("sync");
-			puts ("SRAM:  512 kB\n");
-		}
-		else
-			puts ("!! possible error in SRAM detection\n");
-	} else {
-		puts ("SRAM:  1 MB\n");
-	}
-	/* restore origianl SRAM content  */
-	if (restore) {
-		*(volatile u16 *)CONFIG_SYS_CS2_START = save;
-		__asm__ volatile ("sync");
-	}
-
-#ifndef CONFIG_TQM5200S	/* The TQM5200S has no SM501 grafic controller */
-	/*
-	 * Check for Grafic Controller
-	 */
-
-	/* save origianl FB content  */
-	save = *(volatile u16 *)CONFIG_SYS_CS1_START;
-	restore = 1;
-
-	/* write test pattern to FB memory */
-	*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
-	__asm__ volatile ("sync");
-	/*
-	 * Put a different pattern on the data lines: otherwise they may float
-	 * long enough to read back what we wrote.
-	 */
-	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
-	if (tmp == 0xA5A5)
-		puts ("!! possible error in grafic controller detection\n");
-
-	if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
-		/* no grafic controller at all, disable cs */
-		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
-		*(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
-		*(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
-		restore = 0;
-		__asm__ volatile ("sync");
-	} else {
-		puts ("VGA:   SMI501 (Voyager) with 8 MB\n");
-	}
-	/* restore origianl FB content  */
-	if (restore) {
-		*(volatile u16 *)CONFIG_SYS_CS1_START = save;
-		__asm__ volatile ("sync");
-	}
-
-#ifdef CONFIG_FO300
-	if (silent_boot()) {
-		setenv("bootdelay", "0");
-		disable_ctrlc(1);
-	}
-#endif
-#endif /* !CONFIG_TQM5200S */
-
-#if defined(CONFIG_CHARON)
-	charon_last_stage_init();
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_VIDEO_SM501
-
-#ifdef CONFIG_FO300
-#define DISPLAY_WIDTH   800
-#else
-#define DISPLAY_WIDTH   640
-#endif
-#define DISPLAY_HEIGHT  480
-
-#ifdef CONFIG_VIDEO_SM501_8BPP
-#error CONFIG_VIDEO_SM501_8BPP not supported.
-#endif /* CONFIG_VIDEO_SM501_8BPP */
-
-#ifdef CONFIG_VIDEO_SM501_16BPP
-#error CONFIG_VIDEO_SM501_16BPP not supported.
-#endif /* CONFIG_VIDEO_SM501_16BPP */
-#ifdef CONFIG_VIDEO_SM501_32BPP
-static const SMI_REGS init_regs [] =
-{
-#if 0 /* CRT only */
-	{0x00004, 0x0},
-	{0x00048, 0x00021807},
-	{0x0004C, 0x10090a01},
-	{0x00054, 0x1},
-	{0x00040, 0x00021807},
-	{0x00044, 0x10090a01},
-	{0x00054, 0x0},
-	{0x80200, 0x00010000},
-	{0x80204, 0x0},
-	{0x80208, 0x0A000A00},
-	{0x8020C, 0x02fa027f},
-	{0x80210, 0x004a028b},
-	{0x80214, 0x020c01df},
-	{0x80218, 0x000201e9},
-	{0x80200, 0x00013306},
-#else  /* panel + CRT */
-#ifdef CONFIG_FO300
-	{0x00004, 0x0},
-	{0x00048, 0x00021807},
-	{0x0004C, 0x301a0a01},
-	{0x00054, 0x1},
-	{0x00040, 0x00021807},
-	{0x00044, 0x091a0a01},
-	{0x00054, 0x0},
-	{0x80000, 0x0f013106},
-	{0x80004, 0xc428bb17},
-	{0x8000C, 0x00000000},
-	{0x80010, 0x0C800C80},
-	{0x80014, 0x03200000},
-	{0x80018, 0x01e00000},
-	{0x8001C, 0x00000000},
-	{0x80020, 0x01e00320},
-	{0x80024, 0x042a031f},
-	{0x80028, 0x0086034a},
-	{0x8002C, 0x020c01df},
-	{0x80030, 0x000201ea},
-	{0x80200, 0x00010000},
-#else
-	{0x00004, 0x0},
-	{0x00048, 0x00021807},
-	{0x0004C, 0x091a0a01},
-	{0x00054, 0x1},
-	{0x00040, 0x00021807},
-	{0x00044, 0x091a0a01},
-	{0x00054, 0x0},
-	{0x80000, 0x0f013106},
-	{0x80004, 0xc428bb17},
-	{0x8000C, 0x00000000},
-	{0x80010, 0x0a000a00},
-	{0x80014, 0x02800000},
-	{0x80018, 0x01e00000},
-	{0x8001C, 0x00000000},
-	{0x80020, 0x01e00280},
-	{0x80024, 0x02fa027f},
-	{0x80028, 0x004a028b},
-	{0x8002C, 0x020c01df},
-	{0x80030, 0x000201e9},
-	{0x80200, 0x00010000},
-#endif /* #ifdef CONFIG_FO300 */
-#endif
-	{0, 0}
-};
-#endif /* CONFIG_VIDEO_SM501_32BPP */
-
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-/*
- * Return text to be printed besides the logo.
- */
-void video_get_info_str (int line_number, char *info)
-{
-	if (line_number == 1) {
-	strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
-#if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
-	defined(CONFIG_STK52XX)
-	} else if (line_number == 2) {
-#if defined (CONFIG_CHARON)
-		strcpy (info, "        on a CHARON carrier board");
-#endif
-#if defined (CONFIG_STK52XX)
-		strcpy (info, "        on a STK52xx carrier board");
-#endif
-#if defined (CONFIG_FO300)
-		strcpy (info, "        on a FO300 carrier board");
-#endif
-#endif
-	}
-	else {
-		info [0] = '\0';
-	}
-}
-#endif
-
-/*
- * Returns SM501 register base address. First thing called in the
- * driver. Checks if SM501 is physically present.
- */
-unsigned int board_video_init (void)
-{
-	u16 save, tmp;
-	int restore, ret;
-
-	/*
-	 * Check for Grafic Controller
-	 */
-
-	/* save origianl FB content  */
-	save = *(volatile u16 *)CONFIG_SYS_CS1_START;
-	restore = 1;
-
-	/* write test pattern to FB memory */
-	*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
-	__asm__ volatile ("sync");
-	/*
-	 * Put a different pattern on the data lines: otherwise they may float
-	 * long enough to read back what we wrote.
-	 */
-	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
-	if (tmp == 0xA5A5)
-		puts ("!! possible error in grafic controller detection\n");
-
-	if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
-		/* no grafic controller found */
-		restore = 0;
-		ret = 0;
-	} else {
-		ret = SM501_MMIO_BASE;
-	}
-
-	if (restore) {
-		*(volatile u16 *)CONFIG_SYS_CS1_START = save;
-		__asm__ volatile ("sync");
-	}
-	return ret;
-}
-
-/*
- * Returns SM501 framebuffer address
- */
-unsigned int board_video_get_fb (void)
-{
-	return SM501_FB_BASE;
-}
-
-/*
- * Called after initializing the SM501 and before clearing the screen.
- */
-void board_validate_screen (unsigned int base)
-{
-}
-
-/*
- * Return a pointer to the initialization sequence.
- */
-const SMI_REGS *board_get_regs (void)
-{
-	return init_regs;
-}
-
-int board_get_width (void)
-{
-	return DISPLAY_WIDTH;
-}
-
-int board_get_height (void)
-{
-	return DISPLAY_HEIGHT;
-}
-
-#endif /* CONFIG_VIDEO_SM501 */
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#if defined(CONFIG_VIDEO)
-	fdt_add_edid(blob, "smi,sm501", edid_buf);
-#endif
-
-	return 0;
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-#if defined(CONFIG_RESET_PHY_R)
-#include <miiphy.h>
-
-void reset_phy(void)
-{
-	/* init Micrel KSZ8993 PHY */
-	miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09);
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-	cpu_eth_init(bis); /* Built in FEC comes first */
-	return pci_eth_init(bis);
-}
diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c
index eca218c..4642342 100644
--- a/board/tqc/tqm834x/tqm834x.c
+++ b/board/tqc/tqm834x/tqm834x.c
@@ -66,7 +66,7 @@ int board_early_init_r (void) {
 /**************************************************************************
  * DRAM initalization and size detection
  */
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
 	long bank_size;
 	long size;
@@ -112,7 +112,9 @@ phys_size_t initdram (int board_type)
 		if(size < DDR_MAX_SIZE_PER_CS) break;
 	}
 
-	return size;
+	gd->ram_size = size;
+
+	return 0;
 }
 
 /**************************************************************************
diff --git a/board/tqc/tqm8xx/Kconfig b/board/tqc/tqm8xx/Kconfig
deleted file mode 100644
index 857fedb..0000000
--- a/board/tqc/tqm8xx/Kconfig
+++ /dev/null
@@ -1,155 +0,0 @@
-if TARGET_TQM823L
-
-config SYS_BOARD
-	default "tqm8xx"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM823L"
-
-endif
-
-if TARGET_TQM823M
-
-config SYS_BOARD
-	default "tqm8xx"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM823M"
-
-endif
-
-if TARGET_TQM850L
-
-config SYS_BOARD
-	default "tqm8xx"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM850L"
-
-endif
-
-if TARGET_TQM850M
-
-config SYS_BOARD
-	default "tqm8xx"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM850M"
-
-endif
-
-if TARGET_TQM855L
-
-config SYS_BOARD
-	default "tqm8xx"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM855L"
-
-endif
-
-if TARGET_TQM855M
-
-config SYS_BOARD
-	default "tqm8xx"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM855M"
-
-endif
-
-if TARGET_TQM860L
-
-config SYS_BOARD
-	default "tqm8xx"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM860L"
-
-endif
-
-if TARGET_TQM860M
-
-config SYS_BOARD
-	default "tqm8xx"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM860M"
-
-endif
-
-if TARGET_TQM862L
-
-config SYS_BOARD
-	default "tqm8xx"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM862L"
-
-endif
-
-if TARGET_TQM862M
-
-config SYS_BOARD
-	default "tqm8xx"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM862M"
-
-endif
-
-if TARGET_TQM866M
-
-config SYS_BOARD
-	default "tqm8xx"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM866M"
-
-endif
-
-if TARGET_TQM885D
-
-config SYS_BOARD
-	default "tqm8xx"
-
-config SYS_VENDOR
-	default "tqc"
-
-config SYS_CONFIG_NAME
-	default "TQM885D"
-
-endif
diff --git a/board/tqc/tqm8xx/MAINTAINERS b/board/tqc/tqm8xx/MAINTAINERS
deleted file mode 100644
index f3ddc6a..0000000
--- a/board/tqc/tqm8xx/MAINTAINERS
+++ /dev/null
@@ -1,31 +0,0 @@
-TQM8XX BOARD
-M:	Wolfgang Denk <wd@denx.de>
-S:	Maintained
-F:	board/tqc/tqm8xx/
-F:	include/configs/TQM823L.h
-F:	configs/TQM823L_defconfig
-F:	configs/TQM823L_LCD_defconfig
-F:	include/configs/TQM823M.h
-F:	configs/TQM823M_defconfig
-F:	include/configs/TQM850L.h
-F:	configs/TQM850L_defconfig
-F:	include/configs/TQM850M.h
-F:	configs/TQM850M_defconfig
-F:	include/configs/TQM855L.h
-F:	configs/TQM855L_defconfig
-F:	include/configs/TQM855M.h
-F:	configs/TQM855M_defconfig
-F:	include/configs/TQM860L.h
-F:	configs/TQM860L_defconfig
-F:	include/configs/TQM860M.h
-F:	configs/TQM860M_defconfig
-F:	include/configs/TQM862L.h
-F:	configs/TQM862L_defconfig
-F:	include/configs/TQM862M.h
-F:	configs/TQM862M_defconfig
-F:	include/configs/TQM866M.h
-F:	configs/TQM866M_defconfig
-F:	include/configs/TQM885D.h
-F:	configs/TQM885D_defconfig
-F:	configs/TTTech_defconfig
-F:	configs/wtk_defconfig
diff --git a/board/tqc/tqm8xx/Makefile b/board/tqc/tqm8xx/Makefile
deleted file mode 100644
index 2651a2f..0000000
--- a/board/tqc/tqm8xx/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= tqm8xx.o load_sernum_ethaddr.o
diff --git a/board/tqc/tqm8xx/load_sernum_ethaddr.c b/board/tqc/tqm8xx/load_sernum_ethaddr.c
deleted file mode 100644
index 0070da1..0000000
--- a/board/tqc/tqm8xx/load_sernum_ethaddr.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * (C) Copyright 2000, 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-/*-----------------------------------------------------------------------
- * Process Hardware Information Block:
- *
- * If we boot on a system fresh from factory, check if the Hardware
- * Information Block exists and save the information it contains.
- *
- * The TQM8xxL / TQM82xx Hardware Information Block is defined as
- * follows:
- * - located in first flash bank
- * - starts at offset 0x0003FFC0
- * - size 0x00000040
- *
- * Internal structure:
- * - sequence of ASCII character strings
- * - fields separated by a single space character (0x20)
- * - last field terminated by NUL character (0x00)
- * - remaining space filled with NUL characters (0x00)
- *
- * Fields in Hardware Information Block:
- * 1) Module Type
- * 2) Serial Number
- * 3) First MAC Address
- * 4) Number of additional MAC addresses
- */
-
-void load_sernum_ethaddr (void)
-{
-	unsigned char *hwi;
-	unsigned char  serial [CONFIG_SYS_HWINFO_SIZE];
-	unsigned char  ethaddr[CONFIG_SYS_HWINFO_SIZE];
-	unsigned short ih, is, ie, part;
-
-	hwi = (unsigned char *)(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_HWINFO_OFFSET);
-	ih = is = ie = 0;
-
-	if (*((unsigned long *)hwi) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
-		return;
-	}
-
-	part = 1;
-
-	/* copy serial # / MAC address */
-	while ((hwi[ih] != '\0') && (ih < CONFIG_SYS_HWINFO_SIZE)) {
-		if (hwi[ih] < ' ' || hwi[ih] > '~') { /* ASCII strings! */
-			return;
-		}
-		switch (part) {
-		default:		/* Copy serial # */
-			if (hwi[ih] == ' ') {
-				++part;
-			}
-			serial[is++] = hwi[ih];
-			break;
-		case 3:			/* Copy MAC address */
-			if (hwi[ih] == ' ') {
-				++part;
-				break;
-			}
-			ethaddr[ie++] = hwi[ih];
-			if ((ie % 3) == 2)
-				ethaddr[ie++] = ':';
-			break;
-		}
-		++ih;
-	}
-	serial[is]  = '\0';
-	if (ie && ethaddr[ie-1] == ':')
-		--ie;
-	ethaddr[ie] = '\0';
-
-	/* set serial# and ethaddr if not yet defined */
-	if (getenv("serial#") == NULL) {
-		setenv ((char *)"serial#", (char *)serial);
-	}
-
-	if (getenv("ethaddr") == NULL) {
-		setenv ((char *)"ethaddr", (char *)ethaddr);
-	}
-}
diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c
deleted file mode 100644
index 6d17830..0000000
--- a/board/tqc/tqm8xx/tqm8xx.c
+++ /dev/null
@@ -1,674 +0,0 @@
-/*
- * (C) Copyright 2000-2008
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <hwconfig.h>
-#include <mpc8xx.h>
-#ifdef CONFIG_PS2MULT
-#include <ps2mult.h>
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#endif
-
-extern flash_info_t flash_info[];	/* FLASH chips info */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static long int dram_size (long int, long int *, long int);
-
-#define	_NOT_USED_	0xFFFFFFFF
-
-/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
-const uint sdram_table[] =
-{
-	/*
-	 * Single Read. (Offset 0 in UPMA RAM)
-	 */
-	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
-	0x1FF5FC47, /* last */
-	/*
-	 * SDRAM Initialization (offset 5 in UPMA RAM)
-	 *
-	 * This is no UPM entry point. The following definition uses
-	 * the remaining space to establish an initialization
-	 * sequence, which is executed by a RUN command.
-	 *
-	 */
-		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
-	/*
-	 * Burst Read. (Offset 8 in UPMA RAM)
-	 */
-	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
-	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Single Write. (Offset 18 in UPMA RAM)
-	 */
-	0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
-	0x1FF5FC47, /* last */
-		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Burst Write. (Offset 20 in UPMA RAM)
-	 */
-	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
-	0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Refresh  (Offset 30 in UPMA RAM)
-	 */
-	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
-	0xFFFFFC84, 0xFFFFFC07, /* last */
-				_NOT_USED_, _NOT_USED_,
-	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-	/*
-	 * Exception. (Offset 3c in UPMA RAM)
-	 */
-	0xFFFFFC07, /* last */
-		    _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- *
- * Test TQ ID string (TQM8xx...)
- * If present, check for "L" type (no second DRAM bank),
- * otherwise "L" type is assumed as default.
- *
- * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
- */
-
-int checkboard (void)
-{
-	char buf[64];
-	int i;
-	int l = getenv_f("serial#", buf, sizeof(buf));
-
-	puts ("Board: ");
-
-	if (l < 0 || strncmp(buf, "TQM8", 4)) {
-		puts ("### No HW ID - assuming TQM8xxL\n");
-		return (0);
-	}
-
-	if ((buf[6] == 'L')) {	/* a TQM8xxL type */
-		gd->board_type = 'L';
-	}
-
-	if ((buf[6] == 'M')) {	/* a TQM8xxM type */
-		gd->board_type = 'M';
-	}
-
-	if ((buf[6] == 'D')) {	/* a TQM885D type */
-		gd->board_type = 'D';
-	}
-
-	for (i = 0; i < l; ++i) {
-		if (buf[i] == ' ')
-			break;
-		putc (buf[i]);
-	}
-
-	putc ('\n');
-
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	long int size8, size9, size10;
-	long int size_b0 = 0;
-	long int size_b1 = 0;
-
-	upmconfig (UPMA, (uint *) sdram_table,
-			   sizeof (sdram_table) / sizeof (uint));
-
-	/*
-	 * Preliminary prescaler for refresh (depends on number of
-	 * banks): This value is selected for four cycles every 62.4 us
-	 * with two SDRAM banks or four cycles every 31.2 us with one
-	 * bank. It will be adjusted after memory sizing.
-	 */
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
-
-	/*
-	 * The following value is used as an address (i.e. opcode) for
-	 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
-	 * the port size is 32bit the SDRAM does NOT "see" the lower two
-	 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
-	 * MICRON SDRAMs:
-	 * ->    0 00 010 0 010
-	 *       |  |   | |   +- Burst Length = 4
-	 *       |  |   | +----- Burst Type   = Sequential
-	 *       |  |   +------- CAS Latency  = 2
-	 *       |  +----------- Operating Mode = Standard
-	 *       +-------------- Write Burst Mode = Programmed Burst Length
-	 */
-	memctl->memc_mar = 0x00000088;
-
-	/*
-	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
-	 * preliminary addresses - these have to be modified after the
-	 * SDRAM size has been determined.
-	 */
-	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
-	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
-
-#ifndef	CONFIG_CAN_DRIVER
-	if ((board_type != 'L') &&
-	    (board_type != 'M') &&
-	    (board_type != 'D') ) {	/* only one SDRAM bank on L, M and D modules */
-		memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
-		memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-	}
-#endif							/* CONFIG_CAN_DRIVER */
-
-	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
-
-	udelay (200);
-
-	/* perform SDRAM initializsation sequence */
-
-	memctl->memc_mcr = 0x80004105;	/* SDRAM bank 0 */
-	udelay (1);
-	memctl->memc_mcr = 0x80004230;	/* SDRAM bank 0 - execute twice */
-	udelay (1);
-
-#ifndef	CONFIG_CAN_DRIVER
-	if ((board_type != 'L') &&
-	    (board_type != 'M') &&
-	    (board_type != 'D') ) {	/* only one SDRAM bank on L, M and D modules */
-		memctl->memc_mcr = 0x80006105;	/* SDRAM bank 1 */
-		udelay (1);
-		memctl->memc_mcr = 0x80006230;	/* SDRAM bank 1 - execute twice */
-		udelay (1);
-	}
-#endif							/* CONFIG_CAN_DRIVER */
-
-	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
-
-	udelay (1000);
-
-	/*
-	 * Check Bank 0 Memory Size for re-configuration
-	 *
-	 * try 8 column mode
-	 */
-	size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
-	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
-
-	udelay (1000);
-
-	/*
-	 * try 9 column mode
-	 */
-	size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
-	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
-
-	udelay(1000);
-
-#if defined(CONFIG_SYS_MAMR_10COL)
-	/*
-	 * try 10 column mode
-	 */
-	size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
-	debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
-#else
-	size10 = 0;
-#endif /* CONFIG_SYS_MAMR_10COL */
-
-	if ((size8 < size10) && (size9 < size10)) {
-		size_b0 = size10;
-	} else if ((size8 < size9) && (size10 < size9)) {
-		size_b0 = size9;
-		memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
-		udelay (500);
-	} else {
-		size_b0 = size8;
-		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
-		udelay (500);
-	}
-	debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
-
-#ifndef	CONFIG_CAN_DRIVER
-	if ((board_type != 'L') &&
-	    (board_type != 'M') &&
-	    (board_type != 'D') ) {	/* only one SDRAM bank on L, M and D modules */
-		/*
-		 * Check Bank 1 Memory Size
-		 * use current column settings
-		 * [9 column SDRAM may also be used in 8 column mode,
-		 *  but then only half the real size will be used.]
-		 */
-		size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
-				     SDRAM_MAX_SIZE);
-		debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
-	} else {
-		size_b1 = 0;
-	}
-#endif	/* CONFIG_CAN_DRIVER */
-
-	udelay (1000);
-
-	/*
-	 * Adjust refresh rate depending on SDRAM type, both banks
-	 * For types > 128 MBit leave it at the current (fast) rate
-	 */
-	if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
-		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
-		udelay (1000);
-	}
-
-	/*
-	 * Final mapping: map bigger bank first
-	 */
-	if (size_b1 > size_b0) {	/* SDRAM Bank 1 is bigger - map first   */
-
-		memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-		memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
-		if (size_b0 > 0) {
-			/*
-			 * Position Bank 0 immediately above Bank 1
-			 */
-			memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-			memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
-					   + size_b1;
-		} else {
-			unsigned long reg;
-
-			/*
-			 * No bank 0
-			 *
-			 * invalidate bank
-			 */
-			memctl->memc_br2 = 0;
-
-			/* adjust refresh rate depending on SDRAM type, one bank */
-			reg = memctl->memc_mptpr;
-			reg >>= 1;			/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
-			memctl->memc_mptpr = reg;
-		}
-
-	} else {					/* SDRAM Bank 0 is bigger - map first   */
-
-		memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-		memctl->memc_br2 =
-				(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
-		if (size_b1 > 0) {
-			/*
-			 * Position Bank 1 immediately above Bank 0
-			 */
-			memctl->memc_or3 =
-					((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
-			memctl->memc_br3 =
-					((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
-					+ size_b0;
-		} else {
-			unsigned long reg;
-
-#ifndef	CONFIG_CAN_DRIVER
-			/*
-			 * No bank 1
-			 *
-			 * invalidate bank
-			 */
-			memctl->memc_br3 = 0;
-#endif							/* CONFIG_CAN_DRIVER */
-
-			/* adjust refresh rate depending on SDRAM type, one bank */
-			reg = memctl->memc_mptpr;
-			reg >>= 1;			/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
-			memctl->memc_mptpr = reg;
-		}
-	}
-
-	udelay (10000);
-
-#ifdef	CONFIG_CAN_DRIVER
-	/* UPM initialization for CAN @ CLKOUT <= 66 MHz */
-
-	/* Initialize OR3 / BR3 */
-	memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
-	memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
-
-	/* Initialize MBMR */
-	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* GPL_B4 ouput line Disable */
-
-	/* Initialize UPMB for CAN: single read */
-	memctl->memc_mdr = 0xFFFFCC04;
-	memctl->memc_mcr = 0x0100 | UPMB;
-
-	memctl->memc_mdr = 0x0FFFD004;
-	memctl->memc_mcr = 0x0101 | UPMB;
-
-	memctl->memc_mdr = 0x0FFFC000;
-	memctl->memc_mcr = 0x0102 | UPMB;
-
-	memctl->memc_mdr = 0x3FFFC004;
-	memctl->memc_mcr = 0x0103 | UPMB;
-
-	memctl->memc_mdr = 0xFFFFDC07;
-	memctl->memc_mcr = 0x0104 | UPMB;
-
-	/* Initialize UPMB for CAN: single write */
-	memctl->memc_mdr = 0xFFFCCC04;
-	memctl->memc_mcr = 0x0118 | UPMB;
-
-	memctl->memc_mdr = 0xCFFCDC04;
-	memctl->memc_mcr = 0x0119 | UPMB;
-
-	memctl->memc_mdr = 0x3FFCC000;
-	memctl->memc_mcr = 0x011A | UPMB;
-
-	memctl->memc_mdr = 0xFFFCC004;
-	memctl->memc_mcr = 0x011B | UPMB;
-
-	memctl->memc_mdr = 0xFFFDC405;
-	memctl->memc_mcr = 0x011C | UPMB;
-#endif							/* CONFIG_CAN_DRIVER */
-
-#ifdef	CONFIG_ISP1362_USB
-	/* Initialize OR5 / BR5 */
-	memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362;
-	memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362;
-#endif							/* CONFIG_ISP1362_USB */
-	return (size_b0 + size_b1);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	memctl->memc_mamr = mamr_value;
-
-	return (get_ram_size(base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_MISC_INIT_R
-extern void load_sernum_ethaddr(void);
-int misc_init_r (void)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	load_sernum_ethaddr();
-
-#ifdef	CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
-	int scy, trlx, flash_or_timing, clk_diff;
-
-	scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
-	if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
-		trlx = OR_TRLX;
-		scy *= 2;
-	} else {
-		trlx = 0;
-	}
-
-	/*
-	 * We assume that each 10MHz of bus clock require 1-clk SCY
-	 * adjustment.
-	 */
-	clk_diff = (gd->bus_clk / 1000000) - 50;
-
-	/*
-	 * We need proper rounding here. This is what the "+5" and "-5"
-	 * are here for.
-	 */
-	if (clk_diff >= 0)
-		scy += (clk_diff + 5) / 10;
-	else
-		scy += (clk_diff - 5) / 10;
-
-	/*
-	 * For bus frequencies above 50MHz, we want to use relaxed timing
-	 * (OR_TRLX).
-	 */
-	if (gd->bus_clk >= 50000000)
-		trlx = OR_TRLX;
-	else
-		trlx = 0;
-
-	if (trlx)
-		scy /= 2;
-
-	if (scy > 0xf)
-		scy = 0xf;
-	if (scy < 1)
-		scy = 1;
-
-	flash_or_timing = (scy << 4) | trlx |
-		(CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
-
-	memctl->memc_or0 =
-		flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
-#else
-	memctl->memc_or0 =
-		CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
-#endif
-	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
-	debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
-	       memctl->memc_br0, memctl->memc_or0);
-
-	if (flash_info[1].size) {
-#ifdef	CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
-		memctl->memc_or1 = flash_or_timing |
-			(-flash_info[1].size & 0xFFFF8000);
-#else
-		memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH |
-			(-flash_info[1].size & 0xFFFF8000);
-#endif
-		memctl->memc_br1 =
-			((CONFIG_SYS_FLASH_BASE +
-			  flash_info[0].
-			  size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
-		debug ("## BR1: 0x%08x    OR1: 0x%08x\n",
-		       memctl->memc_br1, memctl->memc_or1);
-	} else {
-		memctl->memc_br1 = 0;	/* invalidate bank */
-
-		debug ("## DISABLE BR1: 0x%08x    OR1: 0x%08x\n",
-		       memctl->memc_br1, memctl->memc_or1);
-	}
-
-# ifdef CONFIG_IDE_LED
-	/* Configure PA15 as output port */
-	immap->im_ioport.iop_padir |= 0x0001;
-	immap->im_ioport.iop_paodr |= 0x0001;
-	immap->im_ioport.iop_papar &= ~0x0001;
-	immap->im_ioport.iop_padat &= ~0x0001;	/* turn it off */
-# endif
-
-	return (0);
-}
-#endif	/* CONFIG_MISC_INIT_R */
-
-
-# ifdef CONFIG_IDE_LED
-void ide_led (uchar led, uchar status)
-{
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
-	/* We have one led for both pcmcia slots */
-	if (status) {				/* led on */
-		immap->im_ioport.iop_padat |= 0x0001;
-	} else {
-		immap->im_ioport.iop_padat &= ~0x0001;
-	}
-}
-# endif
-
-#ifdef CONFIG_LCD_INFO
-#include <lcd.h>
-#include <version.h>
-#include <timestamp.h>
-
-void lcd_show_board_info(void)
-{
-	char temp[32];
-
-	lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
-	lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n");
-	lcd_printf ("    Wolfgang DENK, wd@denx.de\n");
-#ifdef CONFIG_LCD_INFO_BELOW_LOGO
-	lcd_printf ("MPC823 CPU at %s MHz\n",
-		strmhz(temp, gd->cpu_clk));
-	lcd_printf ("  %ld MB RAM, %ld MB Flash\n",
-		gd->ram_size >> 20,
-		gd->bd->bi_flashsize >> 20 );
-#else
-	/* leave one blank line */
-	lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n",
-		strmhz(temp, gd->cpu_clk),
-		gd->ram_size >> 20,
-		gd->bd->bi_flashsize >> 20 );
-#endif /* CONFIG_LCD_INFO_BELOW_LOGO */
-}
-#endif /* CONFIG_LCD_INFO */
-
-/*
- * Device Tree Support
- */
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-int fdt_set_node_and_value (void *blob,
-				char *nodename,
-				char *regname,
-				void *var,
-				int size)
-{
-	int ret = 0;
-	int nodeoffset = 0;
-
-	nodeoffset = fdt_path_offset (blob, nodename);
-	if (nodeoffset >= 0) {
-		ret = fdt_setprop (blob, nodeoffset, regname, var,
-					size);
-		if (ret < 0) {
-			printf("ft_blob_update(): "
-				"cannot set %s/%s property; err: %s\n",
-				nodename, regname, fdt_strerror (ret));
-		}
-	} else {
-		printf("ft_blob_update(): "
-			"cannot find %s node err:%s\n",
-			nodename, fdt_strerror (nodeoffset));
-	}
-	return ret;
-}
-
-int fdt_del_node_name (void *blob, char *nodename)
-{
-	int ret = 0;
-	int nodeoffset = 0;
-
-	nodeoffset = fdt_path_offset (blob, nodename);
-	if (nodeoffset >= 0) {
-		ret = fdt_del_node (blob, nodeoffset);
-		if (ret < 0) {
-			printf("%s: cannot delete %s; err: %s\n",
-				__func__, nodename, fdt_strerror (ret));
-		}
-	} else {
-		printf("%s: cannot find %s node err:%s\n",
-			__func__, nodename, fdt_strerror (nodeoffset));
-	}
-	return ret;
-}
-
-int fdt_del_prop_name (void *blob, char *nodename, char *propname)
-{
-	int ret = 0;
-	int nodeoffset = 0;
-
-	nodeoffset = fdt_path_offset (blob, nodename);
-	if (nodeoffset >= 0) {
-		ret = fdt_delprop (blob, nodeoffset, propname);
-		if (ret < 0) {
-			printf("%s: cannot delete %s %s; err: %s\n",
-				__func__, nodename, propname,
-				fdt_strerror (ret));
-		}
-	} else {
-		printf("%s: cannot find %s node err:%s\n",
-			__func__, nodename, fdt_strerror (nodeoffset));
-	}
-	return ret;
-}
-
-/*
- * update "brg" property in the blob
- */
-void ft_blob_update (void *blob, bd_t *bd)
-{
-	uchar enetaddr[6];
-	ulong brg_data = 0;
-
-	/* BRG */
-	brg_data = cpu_to_be32(bd->bi_busfreq);
-	fdt_set_node_and_value(blob,
-				"/soc/cpm", "brg-frequency",
-				&brg_data, sizeof(brg_data));
-
-	/* MAC addr */
-	if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
-		fdt_set_node_and_value(blob,
-					"ethernet0", "local-mac-address",
-					enetaddr, sizeof(u8) * 6);
-	}
-
-	if (hwconfig_arg_cmp("fec", "off")) {
-		/* no FEC on this plattform, delete DTS nodes */
-		fdt_del_node_name (blob, "ethernet1");
-		fdt_del_node_name (blob, "mdio1");
-		/* also the aliases entries */
-		fdt_del_prop_name (blob, "/aliases", "ethernet1");
-		fdt_del_prop_name (blob, "/aliases", "mdio1");
-	} else {
-		/* adjust local-mac-address for FEC ethernet */
-		if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
-			fdt_set_node_and_value(blob,
-					"ethernet1", "local-mac-address",
-					enetaddr, sizeof(u8) * 6);
-		}
-	}
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-	ft_blob_update(blob, bd);
-
-	return 0;
-}
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds
deleted file mode 100644
index 44dfafa..0000000
--- a/board/tqc/tqm8xx/u-boot.lds
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * (C) Copyright 2000-2012
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/built-in.o	(.text*)
-    arch/powerpc/lib/built-in.o		(.text*)
-    board/tqc/tqm8xx/built-in.o		(.text*)
-    disk/built-in.o			(.text*)
-    drivers/net/built-in.o		(.text*)
-    drivers/built-in.o			(.text.pcmcia_on)
-    drivers/built-in.o			(.text.pcmcia_hardware_enable)
-
-    . = DEFINED(env_offset) ? env_offset : .;
-    common/env_embedded.o	(.ppcenv*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/tqc/tqma6/Kconfig b/board/tqc/tqma6/Kconfig
index 5dafa38..6df4134 100644
--- a/board/tqc/tqma6/Kconfig
+++ b/board/tqc/tqma6/Kconfig
@@ -22,6 +22,12 @@ config TQMA6Q
 	help
 	  select TQMa6Q / TQMa6D with i.MX6Q/D and 1GiB DRAM
 
+config TQMA6DL
+	bool "TQMa6DL"
+	select MX6DL
+	help
+	  select TQMa6DL with i.MX6DL and 1GiB DRAM
+
 config TQMA6S
 	bool "TQMa6S"
 	select MX6S
@@ -70,6 +76,7 @@ endchoice
 
 config IMX_CONFIG
 	default "board/tqc/tqma6/tqma6q.cfg" if TQMA6Q
+	default "board/tqc/tqma6/tqma6dl.cfg" if TQMA6DL
 	default "board/tqc/tqma6/tqma6s.cfg" if TQMA6S
 
 endif
diff --git a/board/tqc/tqma6/README b/board/tqc/tqma6/README
index 2c012e7..c47cb21 100644
--- a/board/tqc/tqma6/README
+++ b/board/tqc/tqma6/README
@@ -21,6 +21,7 @@ To build U-Boot for the TQ Systems TQMa6 modules:
 
 x is a placeholder for the CPU variant
 q - means i.MX6Q/D: TQMa6Q (i.MX6Q) and TQMa6D  (i.MX6D)
+dl - means i.MX6DL: TQMa6DL  (i.MX6DL)
 s - means i.MX6S: TQMa6S  (i.MX6S)
 
 baseboard is a placeholder for the boot device
@@ -31,5 +32,7 @@ This gives the following configurations:
 
 tqma6q_mba6_mmc_config
 tqma6q_mba6_spi_config
+tqma6dl_mba6_mmc_config
+tqma6dl_mba6_spi_config
 tqma6s_mba6_mmc_config
 tqma6s_mba6_spi_config
diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c
index 7fc57da..fcdea34 100644
--- a/board/tqc/tqma6/tqma6.c
+++ b/board/tqc/tqma6/tqma6.c
@@ -13,11 +13,11 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/spi.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
 #include <common.h>
 #include <fsl_esdhc.h>
 #include <libfdt.h>
@@ -47,7 +47,7 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
 
 #define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
-	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_DSE_80ohm | PAD_CTL_HYS |			\
 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 
 int dram_init(void)
@@ -232,25 +232,27 @@ static const char *tqma6_get_boardname(void)
 	};
 }
 
-int board_late_init(void)
+/* setup board specific PMIC */
+int power_init_board(void)
 {
 	struct pmic *p;
-	u32 reg;
-
-	setenv("board_name", tqma6_get_boardname());
+	u32 reg, rev;
 
-	/*
-	 * configure PFUZE100 PMIC:
-	 * TODO: should go to power_init_board if bus switching is
-	 * fixed in generic power code
-	 */
 	power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
 	p = pmic_get("PFUZE100");
 	if (p && !pmic_probe(p)) {
 		pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
-		printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+		pmic_reg_read(p, PFUZE100_REVID, &rev);
+		printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev);
 	}
 
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("board_name", tqma6_get_boardname());
+
 	tqma6_bb_board_late_init();
 
 	return 0;
@@ -267,8 +269,15 @@ int checkboard(void)
  * Device Tree Support
  */
 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#define MODELSTRLEN 32u
 int ft_board_setup(void *blob, bd_t *bd)
 {
+	char modelstr[MODELSTRLEN];
+
+	snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(),
+		 tqma6_bb_get_boardname());
+	do_fixup_by_path_string(blob, "/", "model", modelstr);
+	fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size);
 	/* bring in eMMC dsr settings */
 	do_fixup_by_path_u32(blob,
 			     "/soc/aips-bus@02100000/usdhc@02198000",
diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c
index e58b714..1188215 100644
--- a/board/tqc/tqma6/tqma6_mba6.c
+++ b/board/tqc/tqma6/tqma6_mba6.c
@@ -14,9 +14,9 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
 
 #include <common.h>
 #include <fsl_esdhc.h>
@@ -51,22 +51,22 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
 
 #define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
-	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_DSE_80ohm | PAD_CTL_HYS |			\
 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 
-#if defined(CONFIG_MX6Q)
+#if defined(CONFIG_TQMA6Q)
 
 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII	0x02e0790
 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM	0x02e07ac
 
-#elif defined(CONFIG_MX6S)
+#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
 
 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII	0x02e0768
 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM	0x02e0788
 
 #else
 
-#error "need to define target CPU"
+#error "need to select module"
 
 #endif
 
@@ -114,6 +114,11 @@ static iomux_v3_cfg_t const mba6_enet_pads[] = {
 
 static void mba6_setup_iomuxc_enet(void)
 {
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* clear gpr1[ENET_CLK_SEL] for externel clock */
+	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+
 	__raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
 		     (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
 	__raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
@@ -125,7 +130,7 @@ static void mba6_setup_iomuxc_enet(void)
 	/* Reset PHY */
 	gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
 	/* Need delay 10ms after power on according to KSZ9031 spec */
-	udelay(1000 * 10);
+	mdelay(10);
 	gpio_set_value(ENET_PHY_RESET_GPIO, 1);
 	/*
 	 * KSZ9031 manual: 100 usec wait time after reset before communication
@@ -133,7 +138,7 @@ static void mba6_setup_iomuxc_enet(void)
 	 * BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on
 	 * reset before the phy sees a high level
 	 */
-	udelay(200);
+	mdelay(15);
 }
 
 static iomux_v3_cfg_t const mba6_uart2_pads[] = {
@@ -234,39 +239,20 @@ static void mba6_setup_i2c(void)
 		printf("setup I2C1 failed: %d\n", ret);
 }
 
-
-static iomux_v3_cfg_t const mba6_ecspi1_pads[] = {
-	NEW_PAD_CTRL(MX6_PAD_EIM_D24__GPIO3_IO24, SPI_PAD_CTRL),
-	NEW_PAD_CTRL(MX6_PAD_EIM_D25__GPIO3_IO25, SPI_PAD_CTRL),
-};
-
-static unsigned const mba6_ecspi1_cs[] = {
-	IMX_GPIO_NR(3, 24),
-	IMX_GPIO_NR(3, 25),
-};
-
-static void mba6_setup_iomuxc_spi(void)
-{
-	unsigned i;
-
-	for (i = 0; i < ARRAY_SIZE(mba6_ecspi1_cs); ++i)
-		gpio_direction_output(mba6_ecspi1_cs[i], 1);
-	imx_iomux_v3_setup_multiple_pads(mba6_ecspi1_pads,
-					 ARRAY_SIZE(mba6_ecspi1_pads));
-}
-
 int board_phy_config(struct phy_device *phydev)
 {
 /*
  * optimized pad skew values depends on CPU variant on the TQMa6x module:
- * i.MX6Q/D or i.MX6DL/S
+ * CONFIG_TQMA6Q: i.MX6Q/D
+ * CONFIG_TQMA6S: i.MX6S
+ * CONFIG_TQMA6DL: i.MX6DL
  */
-#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q)
+#if defined(CONFIG_TQMA6Q)
 #define MBA6X_KSZ9031_CTRL_SKEW	0x0032
 #define MBA6X_KSZ9031_CLK_SKEW	0x03ff
 #define MBA6X_KSZ9031_RX_SKEW	0x3333
 #define MBA6X_KSZ9031_TX_SKEW	0x2036
-#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
 #define MBA6X_KSZ9031_CTRL_SKEW	0x0030
 #define MBA6X_KSZ9031_CLK_SKEW	0x03ff
 #define MBA6X_KSZ9031_RX_SKEW	0x3333
@@ -341,7 +327,6 @@ int tqma6_bb_board_early_init_f(void)
 int tqma6_bb_board_init(void)
 {
 	mba6_setup_i2c();
-	mba6_setup_iomuxc_spi();
 	/* do it here - to have reset completed */
 	mba6_setup_iomuxc_enet();
 
diff --git a/board/tqc/tqma6/tqma6_wru4.c b/board/tqc/tqma6/tqma6_wru4.c
index c9a7ab7..2360cff 100644
--- a/board/tqc/tqma6/tqma6_wru4.c
+++ b/board/tqc/tqma6/tqma6_wru4.c
@@ -16,10 +16,10 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
 
 #include <common.h>
 #include <fsl_esdhc.h>
diff --git a/board/tqc/tqma6/tqma6dl.cfg b/board/tqc/tqma6/tqma6dl.cfg
new file mode 100644
index 0000000..716033f
--- /dev/null
+++ b/board/tqc/tqma6/tqma6dl.cfg
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2014 - 2015 Markus Niebel <Markus.Niebel@tq-group.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+#if defined(CONFIG_TQMA6X_MMC_BOOT)
+BOOT_FROM      sd
+#elif defined(CONFIG_TQMA6X_SPI_BOOT)
+BOOT_FROM      spi
+#endif
+
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* TQMa6DL DDR config Rev. 0100E */
+/* IOMUX configuration */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
+DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
+
+/* memory interface calibration values */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00440048
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x003D003F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0029002D
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x002B0043
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x424C0250
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02300234
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4234023C
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0224022C
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x48484C4C
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4C4E4E4C
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36382C36
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x34343630
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+
+/* configure memory interface */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00408032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
+#include "clocks.cfg"
diff --git a/board/udoo/README b/board/udoo/README
new file mode 100644
index 0000000..6fbcc59
--- /dev/null
+++ b/board/udoo/README
@@ -0,0 +1,21 @@
+How to use U-Boot on MX6Q/DL Udoo boards
+----------------------------------------
+
+- Build U-Boot for MX6Q/DL Udoo boards:
+
+$ make mrproper
+$ make udoo_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot.img.
+
+- Flash the SPL image into the SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot.img image into the SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Insert the SD card in the board, power it up and U-Boot messages should
+come up.
diff --git a/board/udoo/neo/Kconfig b/board/udoo/neo/Kconfig
new file mode 100644
index 0000000..8f474df
--- /dev/null
+++ b/board/udoo/neo/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_UDOO_NEO
+
+config SYS_VENDOR
+	default "udoo"
+
+config SYS_BOARD
+	default "neo"
+
+config SYS_CONFIG_NAME
+	default "udoo_neo"
+
+endif
diff --git a/board/udoo/neo/MAINTAINERS b/board/udoo/neo/MAINTAINERS
new file mode 100644
index 0000000..743fe33
--- /dev/null
+++ b/board/udoo/neo/MAINTAINERS
@@ -0,0 +1,7 @@
+UDOO NEO BOARD
+M:	Breno Lima <breno.lima@nxp.com>
+M:	Francesco Montefoschi <francesco.montefoschi@udoo.org>
+S:	Maintained
+F:	board/udoo/neo/
+F:	include/configs/udoo_neo.h
+F:	configs/udoo_neo_defconfig
diff --git a/board/udoo/neo/Makefile b/board/udoo/neo/Makefile
new file mode 100644
index 0000000..150cbc1
--- /dev/null
+++ b/board/udoo/neo/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2015 UDOO Team
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := neo.o
diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
new file mode 100644
index 0000000..276c625
--- /dev/null
+++ b/board/udoo/neo/neo.c
@@ -0,0 +1,596 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright (C) Jasbir Matharu
+ * Copyright (C) UDOO Team
+ *
+ * Author: Breno Lima <breno.lima@nxp.com>
+ * Author: Francesco Montefoschi <francesco.monte@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	UDOO_NEO_TYPE_BASIC,
+	UDOO_NEO_TYPE_BASIC_KS,
+	UDOO_NEO_TYPE_FULL,
+	UDOO_NEO_TYPE_EXTENDED,
+};
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
+	PAD_CTL_ODE)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_SPEED_MED   |                                   \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
+	PAD_CTL_SPEED_MED   | PAD_CTL_SRE_FAST)
+
+#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_40ohm)
+
+#define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+#define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) |	\
+	MUX_MODE_SION)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_MXC
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
+		.gp = IMX_GPIO_NR(1, 0),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
+		.gp = IMX_GPIO_NR(1, 1),
+	},
+};
+#endif
+
+#ifdef CONFIG_POWER
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg, rev_id;
+
+	ret = power_pfuze3000_init(PFUZE3000_I2C_BUS);
+	if (ret)
+		return ret;
+
+	p = pmic_get("PFUZE3000");
+	ret = pmic_probe(p);
+	if (ret)
+		return ret;
+
+	pmic_reg_read(p, PFUZE3000_DEVICEID, &reg);
+	pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
+	printf("PMIC:  PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
+
+	/* disable Low Power Mode during standby mode */
+	pmic_reg_read(p, PFUZE3000_LDOGCTL, &reg);
+	reg |= 0x1;
+	ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
+	if (ret)
+		return ret;
+
+	ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc);
+	if (ret)
+		return ret;
+
+	ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc);
+	if (ret)
+		return ret;
+
+	ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc);
+	if (ret)
+		return ret;
+
+	ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc);
+	if (ret)
+		return ret;
+
+	/* set SW1A standby voltage 0.975V */
+	pmic_reg_read(p, PFUZE3000_SW1ASTBY, &reg);
+	reg &= ~0x3f;
+	reg |= PFUZE3000_SW1AB_SETP(9750);
+	ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
+	if (ret)
+		return ret;
+
+	/* set SW1B standby voltage 0.975V */
+	pmic_reg_read(p, PFUZE3000_SW1BSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= PFUZE3000_SW1AB_SETP(9750);
+	ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
+	if (ret)
+		return ret;
+
+	/* set SW1A/VDD_ARM_IN step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE3000_SW1ACONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg);
+	if (ret)
+		return ret;
+
+	/* set SW1B/VDD_SOC_IN step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE3000_SW1BCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg);
+	if (ret)
+		return ret;
+
+	/* set VDD_ARM_IN to 1.350V */
+	pmic_reg_read(p, PFUZE3000_SW1AVOLT, &reg);
+	reg &= ~0x3f;
+	reg |= PFUZE3000_SW1AB_SETP(13500);
+	ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg);
+	if (ret)
+		return ret;
+
+	/* set VDD_SOC_IN to 1.350V */
+	pmic_reg_read(p, PFUZE3000_SW1BVOLT, &reg);
+	reg &= ~0x3f;
+	reg |= PFUZE3000_SW1AB_SETP(13500);
+	ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
+	if (ret)
+		return ret;
+
+	/* set DDR_1_5V to 1.350V */
+	pmic_reg_read(p, PFUZE3000_SW3VOLT, &reg);
+	reg &= ~0x0f;
+	reg |= PFUZE3000_SW3_SETP(13500);
+	ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg);
+	if (ret)
+		return ret;
+
+	/* set VGEN2_1V5 to 1.5V */
+	pmic_reg_read(p, PFUZE3000_VLDO2CTL, &reg);
+	reg &= ~0x0f;
+	reg |= PFUZE3000_VLDO_SETP(15000);
+	/*  enable  */
+	reg |= 0x10;
+	ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+#endif
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* CD pin */
+	MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* Power */
+	MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const phy_control_pads[] = {
+	/* 25MHz Ethernet PHY Clock */
+	MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
+	MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const board_recognition_pads[] = {
+	/*Connected to R184*/
+	MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
+	/*Connected to R185*/
+	MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
+};
+
+static iomux_v3_cfg_t const wdog_b_pad = {
+	MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const peri_3v3_pads[] = {
+	MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static int setup_fec(int fec_id)
+{
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	int reg;
+
+	imx_iomux_v3_setup_multiple_pads(phy_control_pads,
+					 ARRAY_SIZE(phy_control_pads));
+
+	/* Reset PHY */
+	gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
+	udelay(10000);
+	gpio_set_value(IMX_GPIO_NR(2, 1), 1);
+	udelay(100);
+
+	reg = readl(&anatop->pll_enet);
+	reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
+	writel(reg, &anatop->pll_enet);
+
+	return enable_fec_anatop_clock(fec_id, ENET_25MHZ);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	uint32_t base = IMX_FEC_BASE;
+	struct mii_dev *bus = NULL;
+	struct phy_device *phydev = NULL;
+	int ret;
+
+	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+
+	setup_fec(CONFIG_FEC_ENET_DEV);
+
+	bus = fec_get_miibus(base, CONFIG_FEC_ENET_DEV);
+	if (!bus)
+		return -EINVAL;
+
+	phydev = phy_find_by_mask(bus, (0x1 << CONFIG_FEC_MXC_PHYADDR),
+					PHY_INTERFACE_MODE_RMII);
+	if (!phydev) {
+		free(bus);
+		return -EINVAL;
+	}
+
+	ret  = fec_probe(bis, CONFIG_FEC_ENET_DEV, base, bus, phydev);
+	if (ret) {
+		free(bus);
+		free(phydev);
+		return ret;
+	}
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/*
+	 * Because kernel set WDOG_B mux before pad with the commone pinctrl
+	 * framwork now and wdog reset will be triggered once set WDOG_B mux
+	 * with default pad setting, we set pad setting here to workaround this.
+	 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
+	 * as GPIO mux firstly here to workaround it.
+	 */
+	imx_iomux_v3_setup_pad(wdog_b_pad);
+
+	/* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
+	imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
+					 ARRAY_SIZE(peri_3v3_pads));
+
+	/* Active high for ncp692 */
+	gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
+
+#ifdef CONFIG_SYS_I2C_MXC
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+	return 0;
+}
+
+static int get_board_value(void)
+{
+	int r184, r185;
+
+	imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
+					 ARRAY_SIZE(board_recognition_pads));
+
+	gpio_direction_input(IMX_GPIO_NR(4, 13));
+	gpio_direction_input(IMX_GPIO_NR(4, 0));
+
+	r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
+	r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
+
+	/*
+	 * Machine selection -
+	 * Machine          r184,    r185
+	 * ---------------------------------
+	 * Basic              0        0
+	 * Basic Ks           0        1
+	 * Full               1        0
+	 * Extended           1        1
+	 */
+
+	return (r184 << 1) + r185;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(6, 2)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return !gpio_get_value(USDHC2_CD_GPIO);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+	gpio_direction_input(USDHC2_CD_GPIO);
+	gpio_direction_output(USDHC2_PWR_GPIO, 1);
+
+	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+static char *board_string(void)
+{
+	switch (get_board_value()) {
+	case UDOO_NEO_TYPE_BASIC:
+		return "BASIC";
+	case UDOO_NEO_TYPE_BASIC_KS:
+		return "BASICKS";
+	case UDOO_NEO_TYPE_FULL:
+		return "FULL";
+	case UDOO_NEO_TYPE_EXTENDED:
+		return "EXTENDED";
+	}
+	return "UNDEFINED";
+}
+
+int checkboard(void)
+{
+	printf("Board: UDOO Neo %s\n", board_string());
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	setenv("board_name", board_string());
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+
+#include <libfdt.h>
+#include <asm/arch/mx6-ddr.h>
+
+static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000028,
+	.dram_dqm1 = 0x00000028,
+	.dram_dqm2 = 0x00000028,
+	.dram_dqm3 = 0x00000028,
+	.dram_ras = 0x00000020,
+	.dram_cas = 0x00000020,
+	.dram_odt0 = 0x00000020,
+	.dram_odt1 = 0x00000020,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdcke0 = 0x00003000,
+	.dram_sdcke1 = 0x00003000,
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdqs0 = 0x00000028,
+	.dram_sdqs1 = 0x00000028,
+	.dram_sdqs2 = 0x00000028,
+	.dram_sdqs3 = 0x00000028,
+	.dram_reset = 0x00000020,
+};
+
+static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds = 0x00000020,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = 0x00000028,
+	.grp_b1ds = 0x00000028,
+	.grp_ctlds = 0x00000020,
+	.grp_ddr_type = 0x000c0000,
+	.grp_b2ds = 0x00000028,
+	.grp_b3ds = 0x00000028,
+};
+
+static const struct mx6_mmdc_calibration neo_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x000E000B,
+	.p0_mpwldectrl1 = 0x000E0010,
+	.p0_mpdgctrl0 = 0x41600158,
+	.p0_mpdgctrl1 = 0x01500140,
+	.p0_mprddlctl = 0x3A383E3E,
+	.p0_mpwrdlctl = 0x3A383C38,
+};
+
+static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x001E0022,
+	.p0_mpwldectrl1 = 0x001C0019,
+	.p0_mpdgctrl0 = 0x41540150,
+	.p0_mpdgctrl1 = 0x01440138,
+	.p0_mprddlctl = 0x403E4644,
+	.p0_mpwrdlctl = 0x3C3A4038,
+};
+
+/* MT41K256M16 */
+static struct mx6_ddr3_cfg neo_mem_ddr = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+/* MT41K128M16 */
+static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
+	.mem_speed = 1600,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+	writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+	int board = get_board_value();
+
+	struct mx6_ddr_sysinfo sysinfo = {
+		.dsize = 1, /* width of data bus: 1 = 32 bits */
+		.cs_density = 24,
+		.ncs = 1,
+		.cs1_mirror = 0,
+		.rtt_wr = 2,
+		.rtt_nom = 2,		/* RTT_Nom = RZQ/2 */
+		.walat = 1,		/* Write additional latency */
+		.ralat = 5,		/* Read additional latency */
+		.mif3_mode = 3,		/* Command prediction working mode */
+		.bi_on = 1,		/* Bank interleaving enabled */
+		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	};
+
+	mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
+		mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
+			     &neo_basic_mem_ddr);
+	else
+		mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+
+#endif
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
index a574a2f..7534935 100644
--- a/board/udoo/udoo.c
+++ b/board/udoo/udoo.c
@@ -11,10 +11,10 @@
 #include <asm/arch/iomux.h>
 #include <malloc.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sata.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <asm/arch/crm_regs.h>
@@ -244,7 +244,7 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-#ifdef CONFIG_CMD_SATA
+#ifdef CONFIG_SATA
 	if (is_cpu_type(MXC_CPU_MX6Q))
 		setup_sata();
 #endif
diff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c
index 592e69b..e83e7c3 100644
--- a/board/udoo/udoo_spl.c
+++ b/board/udoo/udoo_spl.c
@@ -10,10 +10,10 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <asm/arch/crm_regs.h>
diff --git a/board/v38b/Kconfig b/board/v38b/Kconfig
deleted file mode 100644
index 653bfc1..0000000
--- a/board/v38b/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_V38B
-
-config SYS_BOARD
-	default "v38b"
-
-config SYS_CONFIG_NAME
-	default "v38b"
-
-endif
diff --git a/board/v38b/MAINTAINERS b/board/v38b/MAINTAINERS
deleted file mode 100644
index d1a6ae6..0000000
--- a/board/v38b/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-V38B BOARD
-#M:	-
-S:	Maintained
-F:	board/v38b/
-F:	include/configs/v38b.h
-F:	configs/v38b_defconfig
diff --git a/board/v38b/Makefile b/board/v38b/Makefile
deleted file mode 100644
index a20a5ef..0000000
--- a/board/v38b/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= v38b.o ethaddr.o
diff --git a/board/v38b/ethaddr.c b/board/v38b/ethaddr.c
deleted file mode 100644
index 982998f..0000000
--- a/board/v38b/ethaddr.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-
-/* For the V38B board the pin is GPIO_PSC_6 */
-#define GPIO_PIN	GPIO_PSC6_0
-
-#define NO_ERROR	0
-#define ERR_NO_NUMBER	1
-#define ERR_BAD_NUMBER	2
-
-static int is_high(void);
-static int check_device(void);
-static void io_out(int value);
-static void io_input(void);
-static void io_output(void);
-static void init_gpio(void);
-static void read_byte(unsigned char *data);
-static void write_byte(unsigned char command);
-
-void read_2501_memory(unsigned char *psernum, unsigned char *perr);
-void board_get_enetaddr(uchar *enetaddr);
-
-
-static int is_high()
-{
-	return (*((vu_long *) MPC5XXX_WU_GPIO_DATA_I) & GPIO_PIN);
-}
-
-static void io_out(int value)
-{
-	if (value)
-		*((vu_long *) MPC5XXX_WU_GPIO_DATA_O) |= GPIO_PIN;
-	else
-		*((vu_long *) MPC5XXX_WU_GPIO_DATA_O) &= ~GPIO_PIN;
-}
-
-static void io_input()
-{
-	*((vu_long *) MPC5XXX_WU_GPIO_DIR) &= ~GPIO_PIN;
-	udelay(3);	/* allow input to settle */
-}
-
-static void io_output()
-{
-	*((vu_long *) MPC5XXX_WU_GPIO_DIR) |= GPIO_PIN;
-}
-
-static void init_gpio()
-{
-	*((vu_long *) MPC5XXX_WU_GPIO_ENABLE) |= GPIO_PIN;	/* Enable appropriate pin */
-}
-
-void read_2501_memory(unsigned char *psernum, unsigned char *perr)
-{
-#define NBYTES 28
-	unsigned char crcval, i;
-	unsigned char buf[NBYTES];
-
-	*perr = 0;
-	crcval = 0;
-
-	for (i = 0; i < NBYTES; i++)
-		buf[i] = 0;
-
-	if (!check_device())
-		*perr = ERR_NO_NUMBER;
-	else {
-		*perr = NO_ERROR;
-		write_byte(0xCC);		/* skip ROM (0xCC) */
-		write_byte(0xF0);		/* Read memory command 0xF0 */
-		write_byte(0x00);		/* Address TA1=0, TA2=0 */
-		write_byte(0x00);
-		read_byte(&crcval);		/* Read CRC of address and command */
-
-		for (i = 0; i < NBYTES; i++)
-			read_byte(&buf[i]);
-	}
-	if (strncmp((const char *) &buf[11], "MAREL IEEE 802.3", 16)) {
-		*perr = ERR_BAD_NUMBER;
-		psernum[0] = 0x00;
-		psernum[1] = 0xE0;
-		psernum[2] = 0xEE;
-		psernum[3] = 0xFF;
-		psernum[4] = 0xFF;
-		psernum[5] = 0xFF;
-	} else {
-		psernum[0] = 0x00;
-		psernum[1] = 0xE0;
-		psernum[2] = 0xEE;
-		psernum[3] = buf[7];
-		psernum[4] = buf[6];
-		psernum[5] = buf[5];
-	}
-}
-
-static int check_device()
-{
-	int found;
-
-	io_output();
-	io_out(0);
-	udelay(500);  /* must be at least 480 us low pulse */
-
-	io_input();
-	udelay(60);
-
-	found = (is_high() == 0) ? 1 : 0;
-	udelay(500);  /* must be at least 480 us low pulse */
-
-	return found;
-}
-
-static void write_byte(unsigned char command)
-{
-	char i;
-
-	for (i = 0; i < 8; i++) {
-		/* 1 us to 15 us low pulse starts bit slot */
-		/* Start with high pulse for 3 us */
-		io_input();
-		udelay(3);
-
-		io_out(0);
-		io_output();
-		udelay(3);
-
-		if (command & 0x01) {
-			/* 60 us high for 1-bit */
-			io_input();
-			udelay(60);
-		} else
-			/* 60 us low for 0-bit */
-			udelay(60);
-		/*  Leave pin as input */
-		io_input();
-
-		command = command >> 1;
-	}
-}
-
-static void read_byte(unsigned char *data)
-{
-	unsigned char i, rdat = 0;
-
-	for (i = 0; i < 8; i++) {
-		/* read one bit from one-wire device */
-
-		/* 1 - 15 us low starts bit slot */
-		io_out(0);
-		io_output();
-		udelay(0);
-
-		/* allow line to be pulled high */
-		io_input();
-
-		/* delay 10 us */
-		udelay(10);
-
-		/* now sample input status */
-		if (is_high())
-			rdat = (rdat >> 1) | 0x80;
-		else
-			rdat = rdat >> 1;
-
-		udelay(60);	/* at least 60 us */
-	}
-	/* copy the return value */
-	*data = rdat;
-}
-
-void board_get_enetaddr(uchar *enetaddr)
-{
-	unsigned char sn[6], err = NO_ERROR;
-
-	init_gpio();
-
-	read_2501_memory(sn, &err);
-
-	if (err == NO_ERROR) {
-		sprintf((char *)enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x",
-				sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]);
-		printf("MAC address: %s\n", enetaddr);
-		setenv("ethaddr", (char *)enetaddr);
-	} else {
-		sprintf((char *)enetaddr, "00:01:02:03:04:05");
-		printf("Error reading MAC address.\n");
-		printf("Setting default to %s\n", enetaddr);
-		setenv("ethaddr", (char *)enetaddr);
-	}
-}
diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c
deleted file mode 100644
index a337729..0000000
--- a/board/v38b/v38b.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * (C) Copyright 2003-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <net.h>
-#include <asm/processor.h>
-
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start(int hi_addr)
-{
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* precharge all banks */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set mode register: extended mode */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
-	__asm__ volatile ("sync");
-
-	/* set mode register: reset DLL */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
-	__asm__ volatile ("sync");
-#endif /* SDRAM_DDR */
-
-	/* precharge all banks */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* auto refresh */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
-	__asm__ volatile ("sync");
-
-	/* set mode register */
-	*(vu_long *) MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-	__asm__ volatile ("sync");
-
-	/* normal operation */
-	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-	__asm__ volatile ("sync");
-}
-#endif /* !CONFIG_SYS_RAMBOOT */
-
-
-phys_size_t initdram(int board_type)
-{
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-	uint svr, pvr;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-	*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
-	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
-	__asm__ volatile ("sync");
-
-	/* setup config registers */
-	*(vu_long *) MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
-	*(vu_long *) MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-	__asm__ volatile ("sync");
-
-#if SDRAM_DDR
-	/* set tap delay */
-	*(vu_long *) MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
-	__asm__ volatile ("sync");
-#endif /* SDRAM_DDR */
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else
-		dramsize = test2;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0)
-		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
-	else
-		*(vu_long *) MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-
-	/* let SDRAM CS1 start right after CS0 */
-	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
-	/* find RAM size using SDRAM CS1 only */
-	if (!dramsize)
-		sdram_start(0);
-	test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	if (!dramsize) {
-		sdram_start(1);
-		test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
-	}
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize2 = test1;
-	} else
-		dramsize2 = test2;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize2 < (1 << 20))
-		dramsize2 = 0;
-
-	/* set SDRAM CS1 size according to the amount of RAM found */
-	if (dramsize2 > 0)
-		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize
-			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
-	else
-		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = *(vu_long *) MPC5XXX_SDRAM_CS1CFG & 0xFF;
-	if (dramsize2 >= 0x13)
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	else
-		dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/*
-	 * On MPC5200B we need to set the special configuration delay in the
-	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
-	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
-	 *
-	 * "The SDelay should be written to a value of 0x00000004. It is
-	 * required to account for changes caused by normal wafer processing
-	 * parameters."
-	 */
-	svr = get_svr();
-	pvr = get_pvr();
-	if ((SVR_MJREV(svr) >= 2) &&
-		(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
-		*(vu_long *) MPC5XXX_SDRAM_SDELAY = 0x04;
-		__asm__ volatile ("sync");
-	}
-
-	return dramsize + dramsize2;
-}
-
-
-int checkboard (void)
-{
-	puts("Board: MarelV38B\n");
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-#ifdef CONFIG_HW_WATCHDOG
-	/*
-	 * Enable and configure the direction (output) of PSC3_9 - watchdog
-	 * reset input. Refer to 7.3.2.2.[1,3,4] of the MPC5200B User's
-	 * Manual.
-	 */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
-#endif /* CONFIG_HW_WATCHDOG */
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write access for the
-	 * detection process.  Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	*(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
-
-	/*
-	 * Enable GPIO_WKUP_7 to "read the status of the actual power
-	 * situation". Default direction is input, so no need to set it
-	 * explicitly.
-	 */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WKUP_7;
-	return 0;
-}
-
-extern void board_get_enetaddr(uchar *enetaddr);
-int misc_init_r(void)
-{
-	uchar enetaddr[6];
-
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
-		board_get_enetaddr(enetaddr);
-		eth_setenv_enetaddr("ethaddr", enetaddr);
-	}
-
-	return 0;
-}
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-void init_ide_reset(void)
-{
-	debug("init_ide_reset\n");
-
-	/* Configure PSC1_4 as GPIO output for ATA reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
-	*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
-	/* Deassert reset */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
-}
-
-
-void ide_set_reset(int idereset)
-{
-	debug("ide_reset(%d)\n", idereset);
-
-	if (idereset) {
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
-		/* Make a delay. MPC5200 spec says 25 usec min */
-		udelay(500000);
-	} else
-		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
-}
-#endif
-
-
-#ifdef CONFIG_HW_WATCHDOG
-void hw_watchdog_reset(void)
-{
-	/*
-	 * MarelV38B has a TPS3705 watchdog. Spec says that to kick the dog
-	 * we need a positive or negative transition on WDI i.e., our PSC3_9.
-	 */
-	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O ^= GPIO_PSC3_9;
-}
-#endif /* CONFIG_HW_WATCHDOG */
diff --git a/board/varisys/cyrus/Kconfig b/board/varisys/cyrus/Kconfig
index d9ea7ef..a0389f8 100644
--- a/board/varisys/cyrus/Kconfig
+++ b/board/varisys/cyrus/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_CYRUS
+if TARGET_CYRUS_P5020 || TARGET_CYRUS_P5040
 
 config SYS_BOARD
 	default "cyrus"
@@ -9,4 +9,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "cyrus"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/varisys/cyrus/cyrus.c b/board/varisys/cyrus/cyrus.c
index 79c363c..74f4473 100644
--- a/board/varisys/cyrus/cyrus.c
+++ b/board/varisys/cyrus/cyrus.c
@@ -97,7 +97,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 #endif
 
 	fdt_fixup_liodn(blob);
-	fdt_fixup_dr_usb(blob, bd);
+	fsl_fdt_fixup_dr_usb(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_ethernet(blob);
diff --git a/board/varisys/cyrus/ddr.c b/board/varisys/cyrus/ddr.c
index bb1d29a..2ba7b3a 100644
--- a/board/varisys/cyrus/ddr.c
+++ b/board/varisys/cyrus/ddr.c
@@ -168,7 +168,7 @@ found:
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -184,5 +184,7 @@ phys_size_t initdram(int board_type)
 	dram_size *= 0x100000;
 
 	debug("    DDR: ");
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/varisys/cyrus/eth.c b/board/varisys/cyrus/eth.c
index bcadc67..fc2192a 100644
--- a/board/varisys/cyrus/eth.c
+++ b/board/varisys/cyrus/eth.c
@@ -19,7 +19,7 @@
 #define FIRST_PORT_ADDR 3
 #define SECOND_PORT_ADDR 7
 
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
 #define FIRST_PORT FM1_DTSEC5
 #define SECOND_PORT FM2_DTSEC5
 #else
@@ -83,7 +83,7 @@ int board_eth_init(bd_t *bis)
 			fm_disable_port(i);
 	}
 
-#ifdef CONFIG_PPC_P5040
+#ifdef CONFIG_ARCH_P5040
 	for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
 		if (!IS_VALID_PORT(i))
 			fm_disable_port(i);
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
index 7f24a30..3818ab9 100644
--- a/board/ve8313/ve8313.c
+++ b/board/ve8313/ve8313.c
@@ -88,7 +88,7 @@ static long fixed_sdram(void)
 	return msize;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile fsl_lbc_t *lbc = &im->im_lbc;
@@ -106,7 +106,9 @@ phys_size_t initdram(int board_type)
 	sync();
 
 	/* return total bus SDRAM size(bytes)  -- DDR */
-	return msize;
+	gd->ram_size = msize;
+
+	return 0;
 }
 
 #define VE8313_WDT_EN	0x00020000
diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c
index 27056e1..d3b1f15 100644
--- a/board/vscom/baltos/board.c
+++ b/board/vscom/baltos/board.c
@@ -39,6 +39,7 @@ DECLARE_GLOBAL_DATA_PTR;
 /* GPIO that controls power to DDR on EVM-SK */
 #define GPIO_DDR_VTT_EN		7
 #define DIP_S1			44
+#define MPCIE_SW		100
 
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
@@ -330,6 +331,11 @@ int ft_board_setup(void *blob, bd_t *bd)
 	return 0;
 }
 
+static struct module_pin_mux pcie_sw_pin_mux[] = {
+	{OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )},     /* GPIO3_4 */
+	{-1},
+};
+
 static struct module_pin_mux dip_pin_mux[] = {
 	{OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )},	/* GPIO1_12 */
 	{OFFSET(gpmc_ad13), (MODE(7)  | RXACTIVE )},	/* GPIO1_13 */
@@ -355,6 +361,18 @@ int board_late_init(void)
 			baltos_set_console();
 		}
 	}
+
+	/* turn power for the mPCIe slot */
+	configure_module_pin_mux(pcie_sw_pin_mux);
+	if (gpio_request(MPCIE_SW, "mpcie_sw")) {
+		printf("failed to export GPIO %d\n", MPCIE_SW);
+		return -ENODEV;
+	}
+	if (gpio_direction_output(MPCIE_SW, 1)) {
+		printf("failed to set GPIO %d direction\n", MPCIE_SW);
+		return -ENODEV;
+	}
+
 	setenv("board_name", model);
 #endif
 
@@ -415,7 +433,6 @@ int board_eth_init(bd_t *bis)
 	int rv, n = 0;
 	uint8_t mac_addr[6];
 	uint32_t mac_hi, mac_lo;
-	__maybe_unused struct am335x_baseboard_id header;
 
 	/*
 	 * Note here that we're using CPSW1 since that has a 1Gbit PHY while
diff --git a/board/vscom/baltos/board.h b/board/vscom/baltos/board.h
index bcdb648..40ddd90 100644
--- a/board/vscom/baltos/board.h
+++ b/board/vscom/baltos/board.h
@@ -11,24 +11,6 @@
 #ifndef _BOARD_H_
 #define _BOARD_H_
 
-/*
- * TI AM335x parts define a system EEPROM that defines certain sub-fields.
- * We use these fields to in turn see what board we are on, and what
- * that might require us to set or not set.
- */
-#define HDR_NO_OF_MAC_ADDR	3
-#define HDR_ETH_ALEN		6
-#define HDR_NAME_LEN		8
-
-struct am335x_baseboard_id {
-	unsigned int  magic;
-	char name[HDR_NAME_LEN];
-	char version[4];
-	char serial[12];
-	char config[32];
-	char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
-};
-
 typedef struct _BSP_VS_HWPARAM    // v1.0
 {
 	uint32_t Magic;
@@ -41,37 +23,6 @@ typedef struct _BSP_VS_HWPARAM    // v1.0
 	uint8_t MAC3[6];        // WL1271 WLAN
 } __attribute__ ((packed)) BSP_VS_HWPARAM;
 
-static inline int board_is_bone(struct am335x_baseboard_id *header)
-{
-	return !strncmp(header->name, "A335BONE", HDR_NAME_LEN);
-}
-
-static inline int board_is_bone_lt(struct am335x_baseboard_id *header)
-{
-	return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN);
-}
-
-static inline int board_is_evm_sk(struct am335x_baseboard_id *header)
-{
-	return !strncmp("A335X_SK", header->name, HDR_NAME_LEN);
-}
-
-static inline int board_is_idk(struct am335x_baseboard_id *header)
-{
-	return !strncmp(header->config, "SKU#02", 6);
-}
-
-static inline int board_is_gp_evm(struct am335x_baseboard_id *header)
-{
-	return !strncmp("A33515BB", header->name, HDR_NAME_LEN);
-}
-
-static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header)
-{
-	return (board_is_gp_evm(header) &&
-		strncmp("1.5", header->version, 3) <= 0);
-}
-
 /*
  * We have three pin mux functions that must exist.  We must be able to enable
  * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
@@ -79,12 +30,6 @@ static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header)
  * is required on the board.
  */
 void enable_uart0_pin_mux(void);
-void enable_uart1_pin_mux(void);
-void enable_uart2_pin_mux(void);
-void enable_uart3_pin_mux(void);
-void enable_uart4_pin_mux(void);
-void enable_uart5_pin_mux(void);
-void enable_i2c0_pin_mux(void);
 void enable_i2c1_pin_mux(void);
 void enable_board_pin_mux(void);
 #endif
diff --git a/board/vscom/baltos/mux.c b/board/vscom/baltos/mux.c
index 8783b25..94410ae 100644
--- a/board/vscom/baltos/mux.c
+++ b/board/vscom/baltos/mux.c
@@ -27,36 +27,6 @@ static struct module_pin_mux uart0_pin_mux[] = {
 	{-1},
 };
 
-static struct module_pin_mux uart1_pin_mux[] = {
-	{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART1_RXD */
-	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},		/* UART1_TXD */
-	{-1},
-};
-
-static struct module_pin_mux uart2_pin_mux[] = {
-	{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART2_RXD */
-	{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)},		/* UART2_TXD */
-	{-1},
-};
-
-static struct module_pin_mux uart3_pin_mux[] = {
-	{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
-	{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)},	/* UART3_TXD */
-	{-1},
-};
-
-static struct module_pin_mux uart4_pin_mux[] = {
-	{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)},	/* UART4_RXD */
-	{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)},		/* UART4_TXD */
-	{-1},
-};
-
-static struct module_pin_mux uart5_pin_mux[] = {
-	{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)},	/* UART5_RXD */
-	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)},		/* UART5_TXD */
-	{-1},
-};
-
 static struct module_pin_mux mmc0_pin_mux[] = {
 	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
 	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
@@ -68,14 +38,6 @@ static struct module_pin_mux mmc0_pin_mux[] = {
 	{-1},
 };
 
-static struct module_pin_mux i2c0_pin_mux[] = {
-	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
-			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
-	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
-			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
-	{-1},
-};
-
 static struct module_pin_mux i2c1_pin_mux[] = {
 	{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
 			PULLUDEN | SLEWCTRL)},	/* I2C_DATA */
@@ -144,36 +106,6 @@ void enable_uart0_pin_mux(void)
 	configure_module_pin_mux(uart0_pin_mux);
 }
 
-void enable_uart1_pin_mux(void)
-{
-	configure_module_pin_mux(uart1_pin_mux);
-}
-
-void enable_uart2_pin_mux(void)
-{
-	configure_module_pin_mux(uart2_pin_mux);
-}
-
-void enable_uart3_pin_mux(void)
-{
-	configure_module_pin_mux(uart3_pin_mux);
-}
-
-void enable_uart4_pin_mux(void)
-{
-	configure_module_pin_mux(uart4_pin_mux);
-}
-
-void enable_uart5_pin_mux(void)
-{
-	configure_module_pin_mux(uart5_pin_mux);
-}
-
-void enable_i2c0_pin_mux(void)
-{
-	configure_module_pin_mux(i2c0_pin_mux);
-}
-
 void enable_i2c1_pin_mux(void)
 {
 	configure_module_pin_mux(i2c1_pin_mux);
@@ -181,7 +113,6 @@ void enable_i2c1_pin_mux(void)
 
 void enable_board_pin_mux()
 {
-	/* Baltos */
 	configure_module_pin_mux(i2c1_pin_mux);
 	configure_module_pin_mux(gpio0_7_pin_mux);
 	configure_module_pin_mux(rgmii2_pin_mux);
diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
index 085095c..47082a8 100644
--- a/board/wandboard/spl.c
+++ b/board/wandboard/spl.c
@@ -9,10 +9,10 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <asm/arch/crm_regs.h>
@@ -188,7 +188,7 @@ static struct mx6_ddr_sysinfo mem_q = {
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
 	.refsel = 1,	/* Refresh cycles at 32KHz */
-	.refr = 7,	/* 8 refresh commands per refresh cycle */
+	.refr = 3,	/* 4 refresh commands per refresh cycle */
 };
 
 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
@@ -231,7 +231,7 @@ static struct mx6_ddr_sysinfo mem_dl = {
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
 	.refsel = 1,	/* Refresh cycles at 32KHz */
-	.refr = 7,	/* 8 refresh commands per refresh cycle */
+	.refr = 3,	/* 4 refresh commands per refresh cycle */
 };
 
 /* DDR 32bit 512MB */
@@ -250,7 +250,7 @@ static struct mx6_ddr_sysinfo mem_s = {
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
 	.refsel = 1,	/* Refresh cycles at 32KHz */
-	.refr = 7,	/* 8 refresh commands per refresh cycle */
+	.refr = 3,	/* 4 refresh commands per refresh cycle */
 };
 
 static void ccgr_init(void)
@@ -289,8 +289,6 @@ static void spl_dram_init(void)
 		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 		mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
 	}
-
-	udelay(100);
 }
 
 void board_init_f(ulong dummy)
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 1de1e0b..1dbc966 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -15,11 +15,11 @@
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
-#include <asm/imx-common/sata.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
+#include <asm/mach-imx/sata.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
@@ -189,6 +189,39 @@ int board_mmc_init(bd_t *bis)
 	return 0;
 }
 
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	ar8031_phy_fixup(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
 #if defined(CONFIG_VIDEO_IPUV3)
 struct i2c_pads_info mx6q_i2c2_pad_info = {
 	.scl = {
@@ -346,7 +379,7 @@ int board_early_init_f(void)
 #if defined(CONFIG_VIDEO_IPUV3)
 	setup_display();
 #endif
-#ifdef CONFIG_CMD_SATA
+#ifdef CONFIG_SATA
 	/* Only mx6q wandboard has SATA */
 	if (is_cpu_type(MXC_CPU_MX6Q))
 		setup_sata();
@@ -409,11 +442,13 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#if defined(CONFIG_VIDEO_IPUV3)
 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
 	if (is_mx6dq())
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
 	else
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
+#endif
 
 	return 0;
 }
diff --git a/board/warp/imximage.cfg b/board/warp/imximage.cfg
index 7b1d6b7..771dbb3 100644
--- a/board/warp/imximage.cfg
+++ b/board/warp/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/warp/warp.c b/board/warp/warp.c
index 0bc0a6a..52319b3 100644
--- a/board/warp/warp.c
+++ b/board/warp/warp.c
@@ -14,8 +14,8 @@
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
@@ -62,7 +62,7 @@ static void setup_iomux_uart(void)
 }
 
 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
-	{USDHC2_BASE_ADDR},
+	{USDHC2_BASE_ADDR, 0, 0, 0, 1},
 };
 
 int board_mmc_getcd(struct mmc *mmc)
diff --git a/board/warp7/MAINTAINERS b/board/warp7/MAINTAINERS
index 1d3ee29..0fc9746 100644
--- a/board/warp7/MAINTAINERS
+++ b/board/warp7/MAINTAINERS
@@ -4,3 +4,4 @@ S:	Maintained
 F:	board/warp7/
 F:	include/configs/warp7.h
 F:	configs/warp7_defconfig
+F:	configs/warp7_secure_defconfig
diff --git a/board/warp7/imximage.cfg b/board/warp7/imximage.cfg
index e7b6d30..5b42793 100644
--- a/board/warp7/imximage.cfg
+++ b/board/warp7/imximage.cfg
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:	GPL-2.0
  *
- * Refer docs/README.imxmage for more details about how-to configure
+ * Refer doc/README.imximage for more details about how-to configure
  * and create imximage boot image
  *
  * The syntax is taken as close as possible with the kwbimage
diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c
index da9afb4..d422d63 100644
--- a/board/warp7/warp7.c
+++ b/board/warp7/warp7.c
@@ -10,8 +10,8 @@
 #include <asm/arch/mx7-pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/io.h>
 #include <common.h>
 #include <fsl_esdhc.h>
@@ -19,6 +19,7 @@
 #include <mmc.h>
 #include <asm/arch/crm_regs.h>
 #include <usb.h>
+#include <netdev.h>
 #include <power/pmic.h>
 #include <power/pfuze3000_pmic.h>
 #include "../freescale/common/pfuze.h"
@@ -138,6 +139,19 @@ int power_init_board(void)
 }
 #endif
 
+int board_eth_init(bd_t *bis)
+{
+	int ret = 0;
+
+#ifdef CONFIG_USB_ETHER
+	ret = usb_eth_initialize(bis);
+	if (ret < 0)
+		printf("Error %d registering USB ether.\n", ret);
+#endif
+
+	return ret;
+}
+
 int board_init(void)
 {
 	/* address of boot parameters */
diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c
index 3da61a4..972e74e 100644
--- a/board/woodburn/woodburn.c
+++ b/board/woodburn/woodburn.c
@@ -8,7 +8,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
diff --git a/board/work-microwave/work_92105/Kconfig b/board/work-microwave/work_92105/Kconfig
index 74f004f..4bc34ed 100644
--- a/board/work-microwave/work_92105/Kconfig
+++ b/board/work-microwave/work_92105/Kconfig
@@ -12,4 +12,16 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "work_92105"
 
+config CMD_HD44760
+	bool "Enable 'hd44780' LCD-control comand"
+	help
+	  This controls the LCD driver.
+
+config CMD_MAX6957
+	bool "Enable 'max6957aax' PMIC command"
+	help
+	  DEPRECATED: Needs conversion to driver model.
+
+	  This allows PMIC registers to be read and written.
+
 endif
diff --git a/board/work-microwave/work_92105/work_92105_display.c b/board/work-microwave/work_92105/work_92105_display.c
index 3d7438e..37a7363 100644
--- a/board/work-microwave/work_92105/work_92105_display.c
+++ b/board/work-microwave/work_92105/work_92105_display.c
@@ -346,4 +346,4 @@ U_BOOT_CMD(
 	"HD44780 LCD driver control",
 	hd44780_help_text
 );
-#endif /* CONFIG_CMD_HD44780 */
+#endif /* CONFIG_CMD_HD44760 */
diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile
index 65d321a..db1f029 100644
--- a/board/xes/common/Makefile
+++ b/board/xes/common/Makefile
@@ -6,9 +6,9 @@
 #
 
 obj-$(CONFIG_FSL_PCI_INIT)	+= fsl_8xxx_pci.o
-obj-$(CONFIG_MPC8572)		+= fsl_8xxx_clk.o
+obj-$(CONFIG_ARCH_MPC8572)		+= fsl_8xxx_clk.o
 obj-$(CONFIG_MPC86xx)		+= fsl_8xxx_clk.o
-obj-$(CONFIG_P2020)		+= fsl_8xxx_clk.o
+obj-$(CONFIG_ARCH_P2020)		+= fsl_8xxx_clk.o
 obj-$(CONFIG_MPC85xx)		+= fsl_8xxx_misc.o board.o
 obj-$(CONFIG_MPC86xx)		+= fsl_8xxx_misc.o board.o
 obj-$(CONFIG_NAND_ACTL)	+= actl_nand.o
diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c
index 2a604d4..e102b0c 100644
--- a/board/xes/common/fsl_8xxx_clk.c
+++ b/board/xes/common/fsl_8xxx_clk.c
@@ -22,7 +22,7 @@ unsigned long get_board_sys_clk(ulong dummy)
 	if (in_be32(&gur->gpporcr) & 0x10000)
 		return 66666666;
 	else
-#ifdef CONFIG_P2020
+#ifdef CONFIG_ARCH_P2020
 		return 100000000;
 #else
 		return 50000000;
@@ -42,7 +42,7 @@ unsigned long get_board_ddr_clk(ulong dummy)
 	if (ddr_ratio == 0x7)
 		return get_board_sys_clk(dummy);
 
-#ifdef CONFIG_P2020
+#ifdef CONFIG_ARCH_P2020
 	if (in_be32(&gur->gpporcr) & 0x20000)
 		return 66666666;
 	else
diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c
index 510f638..6237571 100644
--- a/board/xes/common/fsl_8xxx_pci.c
+++ b/board/xes/common/fsl_8xxx_pci.c
@@ -55,7 +55,7 @@ void pci_init_board(void)
 	} else {
 		printf("PCI1: disabled\n");
 	}
-#elif defined CONFIG_MPC8548
+#elif defined CONFIG_ARCH_MPC8548
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	/* PCI1 not present on MPC8572 */
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
diff --git a/board/xes/xpedite1000/Kconfig b/board/xes/xpedite1000/Kconfig
deleted file mode 100644
index 4d0ab2f..0000000
--- a/board/xes/xpedite1000/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_XPEDITE1000
-
-config SYS_BOARD
-	default "xpedite1000"
-
-config SYS_VENDOR
-	default "xes"
-
-config SYS_CONFIG_NAME
-	default "xpedite1000"
-
-endif
diff --git a/board/xes/xpedite1000/MAINTAINERS b/board/xes/xpedite1000/MAINTAINERS
deleted file mode 100644
index 055ce6a..0000000
--- a/board/xes/xpedite1000/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-XPEDITE1000 BOARD
-M:	Peter Tyser <ptyser@xes-inc.com>
-S:	Maintained
-F:	board/xes/xpedite1000/
-F:	include/configs/xpedite1000.h
-F:	configs/xpedite1000_defconfig
diff --git a/board/xes/xpedite1000/Makefile b/board/xes/xpedite1000/Makefile
deleted file mode 100644
index 308de91..0000000
--- a/board/xes/xpedite1000/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= xpedite1000.o
-extra-y	+= init.o
diff --git a/board/xes/xpedite1000/README b/board/xes/xpedite1000/README
deleted file mode 100644
index 1da8b80..0000000
--- a/board/xes/xpedite1000/README
+++ /dev/null
@@ -1,82 +0,0 @@
-			   XES XPedite1000 Board
-
-		    Last Update: December 29, 2003
-=======================================================================
-
-This file contains some handy info regarding U-Boot and the XES
-XPedite1000 PPC440GX PrPMC board. See the README.ppc440 for additional
-information.
-
-
-SWITCH SETTINGS & JUMPERS
-==========================
-
-Jumpers selected for AMD29LV040B flash part as the boot flash.
-
-
-I2C Strap EEPROM & Environment Settings
-=======================================
-
-The XPedite1000 uses a single I2C eeprom for the 440 strappings and for
-the environment variables.  The first page (256 bytes) contains the
-strappings and the 2 EMAC HW Ethernet addresses.  Be careful not to
-change the 1st page of the EEPROM!  Unpopulated jumper J560 can get you
-out of trouble as it disables the strapping read from EEPROM.
-
-I2C probe
-=====================
-
-The i2c utilities work and have been tested on Rev B. of the 440GX. See
-README.ebony for more information about i2c probing with the 440.
-
-
-GETTING OUT OF I2C TROUBLE
-===========================
-
-(Direct quote from README.ebony)
-If you're like me ... you may have screwed up your bootstrap serial
-eeprom ... or worse, your SPD eeprom when experimenting with the
-i2c commands. If so, here are some ideas on how to get out of
-trouble:
-
-Serial bootstrap eeprom corruption:
------------------------------------
-Power down the board and set the following straps:
-
-J560 - closed
-
-This will select the default sys0 and sys1 settings (the serial
-eeproms are not used). Then power up the board and fix the serial
-eeprom using the 'i2c mm' command. Here are the values I currently
-use:
-
-=> i2c md 50 0 10
-
-0000: 85 7d 42 06 07 80 11 00 00 00 00 00 00 00 00 00    .}B.............
-
-Once you have the eeproms set correctly change the
-J560 straps as you desire.
-
-
-PPC440GX Ethernet EMACs
-=======================
-
-The XES XPedite1000 uses emac 2 & 3 and ignores emac 0 & 1.  PHYs are connected
-only to emac 2 & 3.  The HW Ethernet addresses are read from the i2c eeprom and
-placed in the bd info structure for enet2addr and enet3addr.  The ethernet driver
-senses that enetaddr and enet1addr are 0's and does not use them.
-
-As of this writing gigabit ethernet and the TCPIP acceleration hardware is not
-supported.
-
-
-Flash Support
-=============
-
-As of this writing, there is support for the 1/2mb boot flash only.  User flash
-is not yet supported.
-
-
-Regards,
---Travis
-<travis.sawyer@sandburst.com>
diff --git a/board/xes/xpedite1000/config.mk b/board/xes/xpedite1000/config.mk
deleted file mode 100644
index ec7651e..0000000
--- a/board/xes/xpedite1000/config.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# (C) Copyright 2002-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-#
-# XES XPedite1000 PPC440GX
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/xes/xpedite1000/init.S b/board/xes/xpedite1000/init.S
deleted file mode 100644
index 9708ecc..0000000
--- a/board/xes/xpedite1000/init.S
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
-* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
- * SPDX-License-Identifier:	GPL-2.0+
-*/
-
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-/*
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- */
-
-	.section .bootpg,"ax"
-	.globl tlbtab
-
-tlbtab:
-	tlbtab_start
-	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
-	tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
-	tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
-	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
-	tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
-	tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
-	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
-	tlbtab_end
diff --git a/board/xes/xpedite1000/u-boot.lds.debug b/board/xes/xpedite1000/u-boot.lds.debug
deleted file mode 100644
index 04089ae..0000000
--- a/board/xes/xpedite1000/u-boot.lds.debug
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * (C) Copyright 2002-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)		}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)		}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)		}
-  .rela.got      : { *(.rela.got)		}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)		}
-  .rela.bss      : { *(.rela.bss)		}
-  .rel.plt       : { *(.rel.plt)		}
-  .rela.plt      : { *(.rela.plt)		}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/ppc4xx/start.o	(.text)
-    board/xes/xpedite1000/init.o (.text)
-    arch/powerpc/cpu/ppc4xx/kgdb.o	(.text)
-    arch/powerpc/cpu/ppc4xx/traps.o	(.text)
-    arch/powerpc/cpu/ppc4xx/interrupts.o	(.text)
-    arch/powerpc/cpu/ppc4xx/4xx_uart.o	(.text)
-    arch/powerpc/cpu/ppc4xx/cpu_init.o	(.text)
-    arch/powerpc/cpu/ppc4xx/speed.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib/crc32.o		(.text)
-    arch/powerpc/lib/extable.o	(.text)
-    lib/zlib.o		(.text)
-
-/*    common/env_embedded.o(.text) */
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.eh_frame)
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/xes/xpedite1000/xpedite1000.c b/board/xes/xpedite1000/xpedite1000.c
deleted file mode 100644
index 3b8a668..0000000
--- a/board/xes/xpedite1000/xpedite1000.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <console.h>
-#include <asm/processor.h>
-#include <spd_sdram.h>
-#include <i2c.h>
-#include <net.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	unsigned long sdrreg;
-
-	/*
-	 * Enable GPIO for pins 18 - 24
-	 * 18 = SEEPROM_WP
-	 * 19 = #M_RST
-	 * 20 = #MONARCH
-	 * 21 = #LED_ALARM
-	 * 22 = #LED_ACT
-	 * 23 = #LED_STATUS1
-	 * 24 = #LED_STATUS2
-	 */
-	mfsdr(SDR0_PFC0, sdrreg);
-	mtsdr(SDR0_PFC0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00);
-	out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
-	LED0_OFF();
-	LED1_OFF();
-	LED2_OFF();
-	LED3_OFF();
-
-	/* Setup the external bus controller/chip selects */
-	mtebc(PB0AP, 0x04055200);	/* 16MB Strata FLASH */
-	mtebc(PB0CR, 0xff098000);	/* BAS=0xff0 16MB R/W 8-bit */
-	mtebc(PB1AP, 0x04055200);	/* 512KB Socketed AMD FLASH */
-	mtebc(PB1CR, 0xfe018000);	/* BAS=0xfe0 1MB R/W 8-bit */
-	mtebc(PB6AP, 0x05006400);	/* 32-64MB AMD MirrorBit FLASH */
-	mtebc(PB6CR, 0xf00da000);	/* BAS=0xf00 64MB R/W i6-bit */
-	mtebc(PB7AP, 0x05006400);	/* 32-64MB AMD MirrorBit FLASH */
-	mtebc(PB7CR, 0xf40da000);	/* BAS=0xf40 64MB R/W 16-bit */
-
-	/*
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 *
-	 * Because of the interrupt handling rework to handle 440GX interrupts
-	 * with the common code, we needed to change names of the UIC registers.
-	 * Here the new relationship:
-	 *
-	 * U-Boot name	440GX name
-	 * -----------------------
-	 * UIC0		UICB0
-	 * UIC1		UIC0
-	 * UIC2		UIC1
-	 * UIC3		UIC2
-	 */
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC1ER, 0x00000000);	/* disable all */
-	mtdcr(UIC1CR, 0x00000003);	/* SMI & UIC1 crit are critical */
-	mtdcr(UIC1PR, 0xfffffe00);	/* per ref-board manual */
-	mtdcr(UIC1TR, 0x01c00000);	/* per ref-board manual */
-	mtdcr(UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC2ER, 0x00000000);	/* disable all */
-	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC2PR, 0xffffc0ff);	/* per ref-board manual */
-	mtdcr(UIC2TR, 0x00ff8000);	/* per ref-board manual */
-	mtdcr(UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
-	mtdcr(UIC3ER, 0x00000000);	/* disable all */
-	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
-	mtdcr(UIC3TR, 0x00ff8c0f);	/* per ref-board manual */
-	mtdcr(UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
-
-	mtdcr(UIC0SR, 0xfc000000);	/* clear all */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all */
-	mtdcr(UIC0CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC0PR, 0xfc000000);	/* */
-	mtdcr(UIC0TR, 0x00000000);	/* */
-	mtdcr(UIC0VR, 0x00000001);	/* */
-
-	LED0_ON();
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	char buf[64];
-	int i;
-
-	printf("Board: X-ES %s PMC SBC\n", CONFIG_SYS_BOARD_NAME);
-	printf("       ");
-	i = getenv_f("board_rev", buf, sizeof(buf));
-	if (i > 0)
-		printf("Rev %s, ", buf);
-	i = getenv_f("serial#", buf, sizeof(buf));
-	if (i > 0)
-		printf("Serial# %s, ", buf);
-	i = getenv_f("board_cfg", buf, sizeof(buf));
-	if (i > 0)
-		printf("Cfg %s", buf);
-	printf("\n");
-
-	return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
-	return spd_sdram();
-}
-
-/*
- * Override weak pci_pre_init()
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- */
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller * hose)
-{
-	unsigned long strap;
-
-	/* See if we're supposed to setup the pci */
-	mfsdr(SDR0_SDSTP1, strap);
-	if ((strap & 0x00010000) == 0)
-		return 0;
-
-#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
-	/* Setup System Device Register PCIL0_XCR */
-	mfsdr(SDR0_XCR, strap);
-	strap &= 0x0f000000;
-	mtsdr(SDR0_XCR, strap);
-#endif
-
-	return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-#if defined(CONFIG_PCI)
-/*
- * Override weak is_pci_host()
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
- */
-int is_pci_host(struct pci_controller *hose)
-{
-	return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0);
-}
-#endif /* defined(CONFIG_PCI) */
-
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
-	return ctrlc();
-}
-#endif
diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c
index 0028870..19b96f6 100644
--- a/board/xes/xpedite517x/xpedite517x.c
+++ b/board/xes/xpedite517x/xpedite517x.c
@@ -13,6 +13,8 @@
 #include <pca953x.h>
 #include "../common/fsl_8xxx_misc.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
 extern void ft_board_pci_setup(void *blob, bd_t *bd);
 #endif
@@ -56,7 +58,7 @@ int board_early_init_r(void)
 	return 0;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size = fsl_ddr_sdram();
 
@@ -65,7 +67,9 @@ phys_size_t initdram(int board_type)
 	ddr_enable_ecc(dram_size);
 #endif
 
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
 
 #if defined(CONFIG_OF_BOARD_SETUP)
diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig
index 02ac65c..6e93a3d 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -7,7 +7,12 @@ config SYS_VENDOR
 	default "xilinx"
 
 config SYS_CONFIG_NAME
+	string "Board configuration name"
 	default "microblaze-generic"
+	help
+	  This option contains information about board configuration name.
+	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+	  will be used for board configuration.
 
 config XILINX_MICROBLAZE0_USE_MSR_INSTR
 	int "USE_MSR_INSTR range (0:1)"
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
index ccd4ec9..aa55eba 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -25,10 +25,12 @@ static int reset_pin = -1;
 
 ulong ram_base;
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = ram_base;
 	gd->bd->bi_dram[0].size = get_effective_memsize();
+
+	return 0;
 }
 
 int dram_init(void)
diff --git a/board/xilinx/ppc405-generic/Kconfig b/board/xilinx/ppc405-generic/Kconfig
deleted file mode 100644
index dfbc07b..0000000
--- a/board/xilinx/ppc405-generic/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_XILINX_PPC405_GENERIC
-
-config SYS_BOARD
-	default "ppc405-generic"
-
-config SYS_VENDOR
-	default "xilinx"
-
-config SYS_CONFIG_NAME
-	default "xilinx-ppc405-generic"
-
-endif
diff --git a/board/xilinx/ppc405-generic/MAINTAINERS b/board/xilinx/ppc405-generic/MAINTAINERS
deleted file mode 100644
index ba48f50..0000000
--- a/board/xilinx/ppc405-generic/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-PPC405-GENERIC BOARD
-M:	Ricardo Ribalda <ricardo.ribalda@gmail.com>
-S:	Maintained
-F:	board/xilinx/ppc405-generic/
-F:	include/configs/xilinx-ppc405-generic.h
-F:	configs/xilinx-ppc405-generic_defconfig
-F:	configs/xilinx-ppc405-generic_flash_defconfig
diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile
deleted file mode 100644
index 2800f68..0000000
--- a/board/xilinx/ppc405-generic/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
-# Work supported by Qtechnology http://www.qtec.com
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= xilinx_ppc405_generic.o
diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
deleted file mode 100644
index 3729f07..0000000
--- a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * This work has been supported by: QTechnology  http://qtec.com/
- *
- * SPDX-License-Identifier:	GPL-2.0+
-*/
-
-#include <config.h>
-#include <common.h>
-#include <asm/processor.h>
-
-ulong get_PCI_freq(void)
-{
-	return 0;
-}
-
-int checkboard(void)
-{
-	puts("Xilinx PPC405 Generic Board\n");
-	return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
-	return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
-			    CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
-}
-
-void get_sys_info(sys_info_t *sys_info)
-{
-	sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
-	sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
-	sys_info->freqPCI = 0;
-
-	return;
-}
-
-int get_serial_clock(void){
-	return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
-}
diff --git a/board/xilinx/ppc405-generic/xparameters.h b/board/xilinx/ppc405-generic/xparameters.h
deleted file mode 100644
index c3df9e5..0000000
--- a/board/xilinx/ppc405-generic/xparameters.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * This work has been supported by: QTechnology  http://qtec.com/
- * based on xparameters-ml507.h by Xilinx
- *
- * SPDX-License-Identifier:	GPL-2.0+
-*/
-
-#ifndef XPARAMETER_H
-#define XPARAMETER_H
-
-#define XPAR_DDR2_SDRAM_MEM_BASEADDR	0x00000000
-#define XPAR_IIC_EEPROM_BASEADDR	0x81600000
-#define XPAR_INTC_0_BASEADDR		0x81800000
-#define XPAR_SPI_0_BASEADDR             0x83400000
-#define XPAR_FLASH_MEM0_BASEADDR	0xFE000000
-#define XPAR_PLB_CLOCK_FREQ_HZ		100000000
-#define XPAR_CORE_CLOCK_FREQ_HZ		400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS	32
-#define XPAR_SPI_0_NUM_TRANSFER_BITS	8
-#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ	100000000
-
-#endif
diff --git a/board/xilinx/ppc440-generic/Kconfig b/board/xilinx/ppc440-generic/Kconfig
deleted file mode 100644
index d40783a..0000000
--- a/board/xilinx/ppc440-generic/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_XILINX_PPC440_GENERIC
-
-config SYS_BOARD
-	default "ppc440-generic"
-
-config SYS_VENDOR
-	default "xilinx"
-
-config SYS_CONFIG_NAME
-	default "xilinx-ppc440-generic"
-
-endif
diff --git a/board/xilinx/ppc440-generic/MAINTAINERS b/board/xilinx/ppc440-generic/MAINTAINERS
deleted file mode 100644
index 0258c82..0000000
--- a/board/xilinx/ppc440-generic/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-PPC440-GENERIC BOARD
-M:	Ricardo Ribalda <ricardo.ribalda@gmail.com>
-S:	Maintained
-F:	board/xilinx/ppc440-generic/
-F:	include/configs/xilinx-ppc440-generic.h
-F:	configs/xilinx-ppc440-generic_defconfig
-F:	configs/xilinx-ppc440-generic_flash_defconfig
diff --git a/board/xilinx/ppc440-generic/Makefile b/board/xilinx/ppc440-generic/Makefile
deleted file mode 100644
index 4d5f410..0000000
--- a/board/xilinx/ppc440-generic/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
-# Work supported by Qtechnology http://www.qtec.com
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= xilinx_ppc440_generic.o
-extra-y += init.o
diff --git a/board/xilinx/ppc440-generic/init.S b/board/xilinx/ppc440-generic/init.S
deleted file mode 100644
index f9ff35f..0000000
--- a/board/xilinx/ppc440-generic/init.S
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- *  (C) Copyright 2008
- *  Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- *  This work has been supported by: QTechnology  http://qtec.com/
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <ppc_asm.tmpl>
-#include <config.h>
-#include <asm/mmu.h>
-
-.section .bootpg,"ax"
-.globl tlbtab
-
-tlbtab:
-tlbtab_start
-tlbentry(0x00000000, SZ_256M, 0x00000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x10000000, SZ_256M, 0x10000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x20000000, SZ_256M, 0x20000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x30000000, SZ_256M, 0x30000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x40000000, SZ_256M, 0x40000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x50000000, SZ_256M, 0x50000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x60000000, SZ_256M, 0x60000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x70000000, SZ_256M, 0x70000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x80000000, SZ_256M, 0x80000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0x90000000, SZ_256M, 0x90000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0xa0000000, SZ_256M, 0xa0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0xb0000000, SZ_256M, 0xb0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0xc0000000, SZ_256M, 0xc0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0xd0000000, SZ_256M, 0xd0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0xe0000000, SZ_256M, 0xe0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbentry(0xf0000000, SZ_256M, 0xf0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I)
-tlbtab_end
diff --git a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
deleted file mode 100644
index d823352..0000000
--- a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * This work has been supported by: QTechnology  http://qtec.com/
- *
- * SPDX-License-Identifier:	GPL-2.0+
-*/
-
-#include <config.h>
-#include <common.h>
-#include <netdev.h>
-#include <asm/processor.h>
-
-int checkboard(void)
-{
-	puts("Xilinx PPC440 Generic Board\n");
-	return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
-	return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
-			    CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
-}
-
-void get_sys_info(sys_info_t *sys_info)
-{
-	sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
-	sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
-	sys_info->freqPCI = 0;
-
-	return;
-}
-
-int get_serial_clock(void){
-	return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int ret = 0;
-
-	puts("Init xilinx temac\n");
-#ifdef XPAR_LLTEMAC_0_BASEADDR
-	ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_0_BASEADDR,
-			XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
-			XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR);
-
-#endif
-
-#ifdef XPAR_LLTEMAC_1_BASEADDR
-	ret |= xilinx_ll_temac_eth_init(bis, XPAR_LLTEMAC_1_BASEADDR,
-			XILINX_LL_TEMAC_M_SDMA_DCR | XILINX_LL_TEMAC_M_SDMA_PLB,
-			XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR);
-#endif
-
-	return ret;
-}
diff --git a/board/xilinx/ppc440-generic/xparameters.h b/board/xilinx/ppc440-generic/xparameters.h
deleted file mode 100644
index b45a6a1..0000000
--- a/board/xilinx/ppc440-generic/xparameters.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
- * This work has been supported by: QTechnology  http://qtec.com/
- * based on xparameters-ml507.h by Xilinx
- *
- * SPDX-License-Identifier:	GPL-2.0+
-*/
-
-#ifndef XPARAMETER_H
-#define XPARAMETER_H
-
-#define XPAR_DDR2_SDRAM_MEM_BASEADDR	0x00000000
-#define XPAR_IIC_EEPROM_BASEADDR	0x81600000
-#define XPAR_INTC_0_BASEADDR		0x87000000
-#define XPAR_FLASH_MEM0_BASEADDR	0xF0000000
-#define XPAR_PLB_CLOCK_FREQ_HZ		100000000
-#define XPAR_CORE_CLOCK_FREQ_HZ		400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS	32
-#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ	100000000
-#define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x80
-#define XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR 0x98
-#define XPAR_LLTEMAC_0_BASEADDR		0x83000000
-#define XPAR_LLTEMAC_1_BASEADDR		0x83000040
-
-#endif
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 183f642..b2fbecf 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -19,7 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
 static xilinx_desc fpga;
 
 /* It can be done differently */
+static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
 static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
+static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
 static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
 static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
 static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
@@ -37,9 +40,18 @@ int board_init(void)
 	idcode = zynq_slcr_get_idcode();
 
 	switch (idcode) {
+	case XILINX_ZYNQ_7007S:
+		fpga = fpga007s;
+		break;
 	case XILINX_ZYNQ_7010:
 		fpga = fpga010;
 		break;
+	case XILINX_ZYNQ_7012S:
+		fpga = fpga012s;
+		break;
+	case XILINX_ZYNQ_7014S:
+		fpga = fpga014s;
+		break;
 	case XILINX_ZYNQ_7015:
 		fpga = fpga015;
 		break;
@@ -73,6 +85,12 @@ int board_init(void)
 int board_late_init(void)
 {
 	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+	case ZYNQ_BM_QSPI:
+		setenv("modeboot", "qspiboot");
+		break;
+	case ZYNQ_BM_NAND:
+		setenv("modeboot", "nandboot");
+		break;
 	case ZYNQ_BM_NOR:
 		setenv("modeboot", "norboot");
 		break;
@@ -112,121 +130,17 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 }
 
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
-/*
- * fdt_get_reg - Fill buffer by information from DT
- */
-static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
-			       const u32 *cell, int n)
+int dram_init_banksize(void)
 {
-	int i = 0, b, banks;
-	int parent_offset = fdt_parent_offset(fdt, nodeoffset);
-	int address_cells = fdt_address_cells(fdt, parent_offset);
-	int size_cells = fdt_size_cells(fdt, parent_offset);
-	char *p = buf;
-	u64 val;
-	u64 vals;
-
-	debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
-	      __func__, address_cells, size_cells, buf, cell);
-
-	/* Check memory bank setup */
-	banks = n % (address_cells + size_cells);
-	if (banks)
-		panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
-		      n, address_cells, size_cells);
-
-	banks = n / (address_cells + size_cells);
-
-	for (b = 0; b < banks; b++) {
-		debug("%s: Bank #%d:\n", __func__, b);
-		if (address_cells == 2) {
-			val = cell[i + 1];
-			val <<= 32;
-			val |= cell[i];
-			val = fdt64_to_cpu(val);
-			debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
-			      __func__, val, p, &cell[i]);
-			*(phys_addr_t *)p = val;
-		} else {
-			debug("%s: addr32=%x, ptr=%p\n",
-			      __func__, fdt32_to_cpu(cell[i]), p);
-			*(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
-		}
-		p += sizeof(phys_addr_t);
-		i += address_cells;
-
-		debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
-		      sizeof(phys_addr_t));
-
-		if (size_cells == 2) {
-			vals = cell[i + 1];
-			vals <<= 32;
-			vals |= cell[i];
-			vals = fdt64_to_cpu(vals);
-
-			debug("%s: size64=%llx, ptr=%p, cell=%p\n",
-			      __func__, vals, p, &cell[i]);
-			*(phys_size_t *)p = vals;
-		} else {
-			debug("%s: size32=%x, ptr=%p\n",
-			      __func__, fdt32_to_cpu(cell[i]), p);
-			*(phys_size_t *)p = fdt32_to_cpu(cell[i]);
-		}
-		p += sizeof(phys_size_t);
-		i += size_cells;
-
-		debug("%s: ps=%p, i=%x, size=%zu\n",
-		      __func__, p, i, sizeof(phys_size_t));
-	}
-
-	/* Return the first address size */
-	return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
-}
-
-#define FDT_REG_SIZE  sizeof(u32)
-/* Temp location for sharing data for storing */
-/* Up to 64-bit address + 64-bit size */
-static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
+	fdtdec_setup_memory_banksize();
 
-void dram_init_banksize(void)
-{
-	int bank;
-
-	memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
-
-	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-		debug("Bank #%d: start %llx\n", bank,
-		      (unsigned long long)gd->bd->bi_dram[bank].start);
-		debug("Bank #%d: size %llx\n", bank,
-		      (unsigned long long)gd->bd->bi_dram[bank].size);
-	}
+	return 0;
 }
 
 int dram_init(void)
 {
-	int node, len;
-	const void *blob = gd->fdt_blob;
-	const u32 *cell;
-
-	memset(&tmp, 0, sizeof(tmp));
-
-	/* find or create "/memory" node. */
-	node = fdt_subnode_offset(blob, 0, "memory");
-	if (node < 0) {
-		printf("%s: Can't get memory node\n", __func__);
-		return node;
-	}
-
-	/* Get pointer to cells and lenght of it */
-	cell = fdt_getprop(blob, node, "reg", &len);
-	if (!cell) {
-		printf("%s: Can't get reg property\n", __func__);
-		return -1;
-	}
-
-	gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
-
-	debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
+	if (fdtdec_setup_memory_size() != 0)
+		return -EINVAL;
 
 	zynq_ddrc_init();
 
diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 90f00c6..75aab92 100644
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -7,7 +7,7 @@
 
 obj-y	:= zynqmp.o
 
-hw-platform-y :=$(shell echo $(CONFIG_SYS_CONFIG_NAME))
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
 
 init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\
 	$(hw-platform-y)/psu_init_gpl.o)
@@ -20,10 +20,17 @@ $(warning Put custom psu_init_gpl.c/h to board/xilinx/zynqmp/custom_hw_platform/
 endif
 endif
 
-obj-$(CONFIG_SPL_BUILD) += $(init-objs)
+ifdef_any_of = $(filter-out undefined,$(foreach v,$(1),$(origin $(v))))
+
+ifneq ($(call ifdef_any_of, CONFIG_ZYNQMP_PSU_INIT_ENABLED CONFIG_SPL_BUILD),)
+obj-y += $(init-objs)
+endif
 
 # Suppress "warning: function declaration isn't a prototype"
 CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes
 
 # To include xil_io.h
 CFLAGS_psu_init_gpl.o := -I$(srctree)/$(src)
+
+# To suppress "warning: cast to pointer from integer of different size"
+CFLAGS_psu_init_gpl.o += -Wno-int-to-pointer-cast
diff --git a/board/xilinx/zynqmp/sleep.h b/board/xilinx/zynqmp/sleep.h
new file mode 100644
index 0000000..a962319
--- /dev/null
+++ b/board/xilinx/zynqmp/sleep.h
@@ -0,0 +1 @@
+/* Intentionally empty file for psu_init* */
diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h
index 57ca4ad..679d234 100644
--- a/board/xilinx/zynqmp/xil_io.h
+++ b/board/xilinx/zynqmp/xil_io.h
@@ -7,6 +7,7 @@
 
 /* FIXME remove this when vivado is fixed */
 #include <asm/io.h>
+#include <common.h>
 
 #define xil_printf(...)
 
@@ -32,4 +33,9 @@ int Xil_In32(unsigned long addr)
 	return readl(addr);
 }
 
+void usleep(u32 sleep)
+{
+	udelay(sleep);
+}
+
 #endif /* XIL_IO_H */
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 0c5d997..aebd3df 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -16,14 +16,172 @@
 #include <asm/io.h>
 #include <usb.h>
 #include <dwc3-uboot.h>
+#include <zynqmppl.h>
 #include <i2c.h>
+#include <g_dnl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
+    !defined(CONFIG_SPL_BUILD)
+static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
+
+static const struct {
+	uint32_t id;
+	char *name;
+} zynqmp_devices[] = {
+	{
+		.id = 0x10,
+		.name = "3eg",
+	},
+	{
+		.id = 0x11,
+		.name = "2eg",
+	},
+	{
+		.id = 0x20,
+		.name = "5ev",
+	},
+	{
+		.id = 0x21,
+		.name = "4ev",
+	},
+	{
+		.id = 0x30,
+		.name = "7ev",
+	},
+	{
+		.id = 0x38,
+		.name = "9eg",
+	},
+	{
+		.id = 0x39,
+		.name = "6eg",
+	},
+	{
+		.id = 0x40,
+		.name = "11eg",
+	},
+	{
+		.id = 0x50,
+		.name = "15eg",
+	},
+	{
+		.id = 0x58,
+		.name = "19eg",
+	},
+	{
+		.id = 0x59,
+		.name = "17eg",
+	},
+};
+#endif
+
+int chip_id(unsigned char id)
+{
+	struct pt_regs regs;
+	int val = -EINVAL;
+
+	if (current_el() != 3) {
+		regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
+		regs.regs[1] = 0;
+		regs.regs[2] = 0;
+		regs.regs[3] = 0;
+
+		smc_call(&regs);
+
+		/*
+		 * SMC returns:
+		 * regs[0][31:0]  = status of the operation
+		 * regs[0][63:32] = CSU.IDCODE register
+		 * regs[1][31:0]  = CSU.version register
+		 */
+		switch (id) {
+		case IDCODE:
+			regs.regs[0] = upper_32_bits(regs.regs[0]);
+			regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
+					ZYNQMP_CSU_IDCODE_SVD_MASK;
+			regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
+			val = regs.regs[0];
+			break;
+		case VERSION:
+			regs.regs[1] = lower_32_bits(regs.regs[1]);
+			regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
+			val = regs.regs[1];
+			break;
+		default:
+			printf("%s, Invalid Req:0x%x\n", __func__, id);
+		}
+	} else {
+		switch (id) {
+		case IDCODE:
+			val = readl(ZYNQMP_CSU_IDCODE_ADDR);
+			val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
+			       ZYNQMP_CSU_IDCODE_SVD_MASK;
+			val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
+			break;
+		case VERSION:
+			val = readl(ZYNQMP_CSU_VER_ADDR);
+			val &= ZYNQMP_CSU_SILICON_VER_MASK;
+			break;
+		default:
+			printf("%s, Invalid Req:0x%x\n", __func__, id);
+		}
+	}
+
+	return val;
+}
+
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
+	!defined(CONFIG_SPL_BUILD)
+static char *zynqmp_get_silicon_idcode_name(void)
+{
+	uint32_t i, id;
+
+	id = chip_id(IDCODE);
+	for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
+		if (zynqmp_devices[i].id == id)
+			return zynqmp_devices[i].name;
+	}
+	return "unknown";
+}
+#endif
+
+int board_early_init_f(void)
+{
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
+	zynqmp_pmufw_version();
+#endif
+
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
+	psu_init();
+#endif
+
+	return 0;
+}
+
+#define ZYNQMP_VERSION_SIZE	9
+
 int board_init(void)
 {
 	printf("EL Level:\tEL%d\n", current_el());
 
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
+    !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
+    defined(CONFIG_SPL_BUILD))
+	if (current_el() != 3) {
+		static char version[ZYNQMP_VERSION_SIZE];
+
+		strncat(version, "xczu", 4);
+		zynqmppl.name = strncat(version,
+					zynqmp_get_silicon_idcode_name(),
+					ZYNQMP_VERSION_SIZE - 5);
+		printf("Chip ID:\t%s\n", zynqmppl.name);
+		fpga_init();
+		fpga_add(fpga_xilinx, &zynqmppl);
+	}
+#endif
+
 	return 0;
 }
 
@@ -31,7 +189,10 @@ int board_early_init_r(void)
 {
 	u32 val;
 
-	if (current_el() == 3) {
+	val = readl(&crlapb_base->timestamp_ref_ctrl);
+	val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
+
+	if (current_el() == 3 && !val) {
 		val = readl(&crlapb_base->timestamp_ref_ctrl);
 		val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 		writel(val, &crlapb_base->timestamp_ref_ctrl);
@@ -43,12 +204,6 @@ int board_early_init_r(void)
 		writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 		       &iou_scntr_secure->counter_control_register);
 	}
-	/* Program freq register in System counter and enable system counter */
-	writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
-	writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
-	       ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
-	       &iou_scntr->counter_control_register);
-
 	return 0;
 }
 
@@ -69,121 +224,17 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 }
 
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
-/*
- * fdt_get_reg - Fill buffer by information from DT
- */
-static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
-			       const u32 *cell, int n)
+int dram_init_banksize(void)
 {
-	int i = 0, b, banks;
-	int parent_offset = fdt_parent_offset(fdt, nodeoffset);
-	int address_cells = fdt_address_cells(fdt, parent_offset);
-	int size_cells = fdt_size_cells(fdt, parent_offset);
-	char *p = buf;
-	u64 val;
-	u64 vals;
-
-	debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
-	      __func__, address_cells, size_cells, buf, cell);
-
-	/* Check memory bank setup */
-	banks = n % (address_cells + size_cells);
-	if (banks)
-		panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
-		      n, address_cells, size_cells);
-
-	banks = n / (address_cells + size_cells);
-
-	for (b = 0; b < banks; b++) {
-		debug("%s: Bank #%d:\n", __func__, b);
-		if (address_cells == 2) {
-			val = cell[i + 1];
-			val <<= 32;
-			val |= cell[i];
-			val = fdt64_to_cpu(val);
-			debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
-			      __func__, val, p, &cell[i]);
-			*(phys_addr_t *)p = val;
-		} else {
-			debug("%s: addr32=%x, ptr=%p\n",
-			      __func__, fdt32_to_cpu(cell[i]), p);
-			*(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
-		}
-		p += sizeof(phys_addr_t);
-		i += address_cells;
-
-		debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
-		      sizeof(phys_addr_t));
-
-		if (size_cells == 2) {
-			vals = cell[i + 1];
-			vals <<= 32;
-			vals |= cell[i];
-			vals = fdt64_to_cpu(vals);
-
-			debug("%s: size64=%llx, ptr=%p, cell=%p\n",
-			      __func__, vals, p, &cell[i]);
-			*(phys_size_t *)p = vals;
-		} else {
-			debug("%s: size32=%x, ptr=%p\n",
-			      __func__, fdt32_to_cpu(cell[i]), p);
-			*(phys_size_t *)p = fdt32_to_cpu(cell[i]);
-		}
-		p += sizeof(phys_size_t);
-		i += size_cells;
+	fdtdec_setup_memory_banksize();
 
-		debug("%s: ps=%p, i=%x, size=%zu\n",
-		      __func__, p, i, sizeof(phys_size_t));
-	}
-
-	/* Return the first address size */
-	return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
-}
-
-#define FDT_REG_SIZE  sizeof(u32)
-/* Temp location for sharing data for storing */
-/* Up to 64-bit address + 64-bit size */
-static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
-
-void dram_init_banksize(void)
-{
-	int bank;
-
-	memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
-
-	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
-		debug("Bank #%d: start %llx\n", bank,
-		      (unsigned long long)gd->bd->bi_dram[bank].start);
-		debug("Bank #%d: size %llx\n", bank,
-		      (unsigned long long)gd->bd->bi_dram[bank].size);
-	}
+	return 0;
 }
 
 int dram_init(void)
 {
-	int node, len;
-	const void *blob = gd->fdt_blob;
-	const u32 *cell;
-
-	memset(&tmp, 0, sizeof(tmp));
-
-	/* find or create "/memory" node. */
-	node = fdt_subnode_offset(blob, 0, "memory");
-	if (node < 0) {
-		printf("%s: Can't get memory node\n", __func__);
-		return node;
-	}
-
-	/* Get pointer to cells and lenght of it */
-	cell = fdt_getprop(blob, node, "reg", &len);
-	if (!cell) {
-		printf("%s: Can't get reg property\n", __func__);
-		return -1;
-	}
-
-	gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
-
-	debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
+	if (fdtdec_setup_memory_size() != 0)
+		return -EINVAL;
 
 	return 0;
 }
@@ -200,17 +251,6 @@ void reset_cpu(ulong addr)
 {
 }
 
-#ifdef CONFIG_SCSI_AHCI_PLAT
-void scsi_init(void)
-{
-#if defined(CONFIG_SATA_CEVA)
-	init_sata(0);
-#endif
-	ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
-	scsi_scan(1);
-}
-#endif
-
 int board_late_init(void)
 {
 	u32 reg = 0;
@@ -224,10 +264,17 @@ int board_late_init(void)
 	}
 
 	reg = readl(&crlapb_base->boot_mode);
+	if (reg >> BOOT_MODE_ALT_SHIFT)
+		reg >>= BOOT_MODE_ALT_SHIFT;
+
 	bootmode = reg & BOOT_MODES_MASK;
 
 	puts("Bootmode: ");
 	switch (bootmode) {
+	case USB_MODE:
+		puts("USB_MODE\n");
+		mode = "usb";
+		break;
 	case JTAG_MODE:
 		puts("JTAG_MODE\n");
 		mode = "pxe dhcp";
@@ -245,6 +292,9 @@ int board_late_init(void)
 		puts("SD_MODE\n");
 		mode = "mmc0";
 		break;
+	case SD1_LSHFT_MODE:
+		puts("LVL_SHFT_");
+		/* fall through */
 	case SD_MODE1:
 		puts("SD_MODE1\n");
 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
@@ -283,22 +333,42 @@ int checkboard(void)
 }
 
 #ifdef CONFIG_USB_DWC3
-static struct dwc3_device dwc3_device_data = {
+static struct dwc3_device dwc3_device_data0 = {
 	.maximum_speed = USB_SPEED_HIGH,
 	.base = ZYNQMP_USB0_XHCI_BASEADDR,
 	.dr_mode = USB_DR_MODE_PERIPHERAL,
 	.index = 0,
 };
 
-int usb_gadget_handle_interrupts(void)
+static struct dwc3_device dwc3_device_data1 = {
+	.maximum_speed = USB_SPEED_HIGH,
+	.base = ZYNQMP_USB1_XHCI_BASEADDR,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 1,
+};
+
+int usb_gadget_handle_interrupts(int index)
 {
-	dwc3_uboot_handle_interrupt(0);
+	dwc3_uboot_handle_interrupt(index);
 	return 0;
 }
 
 int board_usb_init(int index, enum usb_init_type init)
 {
-	return dwc3_uboot_init(&dwc3_device_data);
+	debug("%s: index %x\n", __func__, index);
+
+#if defined(CONFIG_USB_GADGET_DOWNLOAD)
+	g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
+#endif
+
+	switch (index) {
+	case 0:
+		return dwc3_uboot_init(&dwc3_device_data0);
+	case 1:
+		return dwc3_uboot_init(&dwc3_device_data1);
+	};
+
+	return -1;
 }
 
 int board_usb_cleanup(int index, enum usb_init_type init)
@@ -307,8 +377,3 @@ int board_usb_cleanup(int index, enum usb_init_type init)
 	return 0;
 }
 #endif
-
-void reset_misc(void)
-{
-	psci_system_reset(true);
-}
diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c
index d3ca939..8a15c30 100644
--- a/board/zipitz2/zipitz2.c
+++ b/board/zipitz2/zipitz2.c
@@ -16,6 +16,7 @@
 #include <spi.h>
 #include <asm/io.h>
 #include <usb.h>
+#include <asm/mach-types.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -69,10 +70,12 @@ void usb_board_stop(void)
 }
 #endif
 
-void dram_init_banksize(void)
+int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
 }
 
 #ifdef	CONFIG_CMD_MMC