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-rw-r--r--board/aristainetos/Kconfig19
-rw-r--r--board/aristainetos/MAINTAINERS6
-rw-r--r--board/aristainetos/Makefile9
-rw-r--r--board/aristainetos/aristainetos.c519
-rw-r--r--board/aristainetos/aristainetos.cfg33
-rw-r--r--board/aristainetos/clocks.cfg24
-rw-r--r--board/aristainetos/ddr-setup.cfg61
-rw-r--r--board/aristainetos/mt41j128M.cfg70
-rw-r--r--board/boundary/nitrogen6x/nitrogen6x.c3
-rw-r--r--board/davinci/dm355evm/MAINTAINERS2
-rw-r--r--board/davinci/dm355leopard/MAINTAINERS2
-rw-r--r--board/davinci/dm365evm/MAINTAINERS2
-rw-r--r--board/davinci/dm6467evm/MAINTAINERS2
-rw-r--r--board/embest/mx6boards/mx6boards.c1
-rw-r--r--board/flagadm/Kconfig11
-rw-r--r--board/flagadm/MAINTAINERS6
-rw-r--r--board/flagadm/Makefile8
-rw-r--r--board/flagadm/flagadm.c134
-rw-r--r--board/flagadm/flash.c687
-rw-r--r--board/flagadm/u-boot.lds82
-rw-r--r--board/flagadm/u-boot.lds.debug121
-rw-r--r--board/freescale/common/Makefile2
-rw-r--r--board/freescale/common/diu_ch7301.c136
-rw-r--r--board/freescale/common/diu_ch7301.h13
-rw-r--r--board/freescale/mx31pdk/MAINTAINERS2
-rw-r--r--board/freescale/mx6sabresd/mx6sabresd.c2
-rw-r--r--board/freescale/mx6slevk/mx6slevk.c3
-rw-r--r--board/freescale/mx6sxsabresd/Kconfig (renamed from board/ti/omap5912osk/Kconfig)12
-rw-r--r--board/freescale/mx6sxsabresd/MAINTAINERS6
-rw-r--r--board/freescale/mx6sxsabresd/Makefile6
-rw-r--r--board/freescale/mx6sxsabresd/imximage.cfg132
-rw-r--r--board/freescale/mx6sxsabresd/mx6sxsabresd.c295
-rw-r--r--board/freescale/t1040qds/diu.c134
-rw-r--r--board/freescale/t104xrdb/Makefile1
-rw-r--r--board/freescale/t104xrdb/diu.c84
-rw-r--r--board/freescale/t104xrdb/spl.c19
-rw-r--r--board/freescale/t4qds/README194
-rw-r--r--board/freescale/t4qds/eth.c136
-rw-r--r--board/gateworks/gw_ventana/eeprom.c168
-rw-r--r--board/gateworks/gw_ventana/gsc.c2
-rw-r--r--board/gateworks/gw_ventana/gw_ventana.c271
-rw-r--r--board/gateworks/gw_ventana/ventana_eeprom.h11
-rw-r--r--board/gen860t/Kconfig11
-rw-r--r--board/gen860t/MAINTAINERS7
-rw-r--r--board/gen860t/Makefile8
-rw-r--r--board/gen860t/README131
-rw-r--r--board/gen860t/beeper.c183
-rw-r--r--board/gen860t/beeper.h13
-rw-r--r--board/gen860t/flash.c628
-rw-r--r--board/gen860t/fpga.c362
-rw-r--r--board/gen860t/fpga.h26
-rw-r--r--board/gen860t/gen860t.c278
-rw-r--r--board/gen860t/ioport.c331
-rw-r--r--board/gen860t/ioport.h26
-rw-r--r--board/gen860t/u-boot-flashenv.lds92
-rw-r--r--board/gen860t/u-boot.lds87
-rw-r--r--board/keymile/kmp204x/kmp204x.c8
-rw-r--r--board/prodrive/alpr/nand.c4
-rw-r--r--board/psyent/common/AMDLV065D.c170
-rw-r--r--board/psyent/pci5441/Kconfig15
-rw-r--r--board/psyent/pci5441/MAINTAINERS6
-rw-r--r--board/psyent/pci5441/Makefile8
-rw-r--r--board/psyent/pci5441/config.mk14
-rw-r--r--board/psyent/pci5441/pci5441.c24
-rw-r--r--board/psyent/pk1c20/Kconfig15
-rw-r--r--board/psyent/pk1c20/MAINTAINERS6
-rw-r--r--board/psyent/pk1c20/Makefile8
-rw-r--r--board/psyent/pk1c20/config.mk14
-rw-r--r--board/psyent/pk1c20/led.c46
-rw-r--r--board/psyent/pk1c20/pk1c20.c36
-rw-r--r--board/samsung/common/Makefile2
-rw-r--r--board/samsung/common/gadget.c (renamed from board/samsung/common/thor.c)3
-rw-r--r--board/sixnet/Kconfig11
-rw-r--r--board/sixnet/MAINTAINERS6
-rw-r--r--board/sixnet/Makefile8
-rw-r--r--board/sixnet/flash.c774
-rw-r--r--board/sixnet/fpgadata.c1719
-rw-r--r--board/sixnet/sixnet.c578
-rw-r--r--board/sixnet/sixnet.h20
-rw-r--r--board/sixnet/u-boot.lds82
-rw-r--r--board/socrates/nand.c6
-rw-r--r--board/solidrun/hummingboard/hummingboard.c3
-rw-r--r--board/stx/stxxtc/Kconfig15
-rw-r--r--board/stx/stxxtc/MAINTAINERS6
-rw-r--r--board/stx/stxxtc/Makefile8
-rw-r--r--board/stx/stxxtc/README.stxxtc59
-rw-r--r--board/stx/stxxtc/stxxtc.c592
-rw-r--r--board/stx/stxxtc/u-boot.lds82
-rw-r--r--board/stx/stxxtc/u-boot.lds.debug121
-rw-r--r--board/sunxi/Kconfig33
-rw-r--r--board/svm_sc8xx/Kconfig11
-rw-r--r--board/svm_sc8xx/MAINTAINERS6
-rw-r--r--board/svm_sc8xx/Makefile8
-rw-r--r--board/svm_sc8xx/flash.c666
-rw-r--r--board/svm_sc8xx/svm_sc8xx.c144
-rw-r--r--board/svm_sc8xx/u-boot.lds99
-rw-r--r--board/svm_sc8xx/u-boot.lds.debug114
-rw-r--r--board/ti/omap5912osk/MAINTAINERS6
-rw-r--r--board/ti/omap5912osk/Makefile9
-rw-r--r--board/ti/omap5912osk/config.mk30
-rw-r--r--board/ti/omap5912osk/lowlevel_init.S477
-rw-r--r--board/ti/omap5912osk/omap5912osk.c307
-rw-r--r--board/tqc/tqm8272/nand.c4
-rw-r--r--board/tqc/tqma6/Makefile9
-rw-r--r--board/tqc/tqma6/README35
-rw-r--r--board/tqc/tqma6/clocks.cfg24
-rw-r--r--board/tqc/tqma6/tqma6.c262
-rw-r--r--board/tqc/tqma6/tqma6_bb.h30
-rw-r--r--board/tqc/tqma6/tqma6_mba6.c361
-rw-r--r--board/tqc/tqma6/tqma6q.cfg125
-rw-r--r--board/tqc/tqma6/tqma6s.cfg125
111 files changed, 3066 insertions, 9902 deletions
diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig
new file mode 100644
index 0000000..58078ea
--- /dev/null
+++ b/board/aristainetos/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_ARISTAINETOS
+
+config SYS_CPU
+ string
+ default "armv7"
+
+config SYS_BOARD
+ string
+ default "aristainetos"
+
+config SYS_SOC
+ string
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ string
+ default "aristainetos"
+
+endif
diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS
new file mode 100644
index 0000000..d45d423
--- /dev/null
+++ b/board/aristainetos/MAINTAINERS
@@ -0,0 +1,6 @@
+ARISTAINETOS BOARD
+M: Heiko Schocher <hs@denx.de>
+S: Maintained
+F: board/aristainetos/
+F: include/configs/aristainetos.h
+F: configs/aristainetos_defconfig
diff --git a/board/aristainetos/Makefile b/board/aristainetos/Makefile
new file mode 100644
index 0000000..5de48bc
--- /dev/null
+++ b/board/aristainetos/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := aristainetos.o
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
new file mode 100644
index 0000000..3bfcf5b
--- /dev/null
+++ b/board/aristainetos/aristainetos.c
@@ -0,0 +1,519 @@
+/*
+ * (C) Copyright 2014
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <pwm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+#define DISP_PAD_CTRL (0x10)
+
+#define ECSPI4_CS1 IMX_GPIO_NR(5, 2)
+
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
+ .gp = IMX_GPIO_NR(5, 27)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
+ .gp = IMX_GPIO_NR(5, 26)
+ }
+};
+
+struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+struct i2c_pads_info i2c_pad_info3 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
+ .gp = IMX_GPIO_NR(3, 17)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
+ .gp = IMX_GPIO_NR(3, 18)
+ }
+};
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart5_pads[] = {
+ MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const gpio_pads[] = {
+ /* LED enable */
+ MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* spi flash WP protect */
+ MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* backlight enable */
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED yellow */
+ MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED red */
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED green */
+ MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED blue */
+ MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* i2c4 scl */
+ MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* i2c4 sda */
+ MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* spi CS 1 */
+ MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const misc_pads[] = {
+ MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* OTG Power enable */
+ MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(0x4001b0a8),
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+ /* set GPIO_16 as ENET_REF_CLK_OUT */
+ setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+}
+
+iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const ecspi4_pads[] = {
+ MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const display_pads[] = {
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
+ MX6_PAD_DI0_PIN4__GPIO4_IO20,
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
+};
+
+static iomux_v3_cfg_t const backlight_pads[] = {
+ MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_spi(void)
+{
+ int i;
+
+ imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
+ for (i = 0; i < 3; i++)
+ enable_spi_clk(true, i);
+
+ /* set cs1 to high */
+ gpio_direction_output(ECSPI4_CS1, 1);
+}
+
+static void setup_iomux_gpio(void)
+{
+ imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
+}
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC1_BASE_ADDR},
+ {USDHC2_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+ imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]) |
+ fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+}
+#endif
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct iomuxc *iomuxc_regs =
+ (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int ret;
+
+ setup_iomux_enet();
+ /* clear gpr1[14], gpr1[18:17] to select anatop clock */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
+
+ ret = enable_fec_anatop_clock(ENET_50MHz);
+ if (ret)
+ return ret;
+
+ return cpu_eth_init(bis);
+}
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+ imx_iomux_v3_setup_multiple_pads(
+ display_pads,
+ ARRAY_SIZE(display_pads));
+ imx_iomux_v3_setup_multiple_pads(
+ backlight_pads,
+ ARRAY_SIZE(backlight_pads));
+
+ /* enable backlight PWM 3 */
+ if (pwm_init(2, 0, 0))
+ goto error;
+ /* duty cycle 200ns, period: 3000ns */
+ if (pwm_config(2, 200, 3000))
+ goto error;
+ if (pwm_enable(2))
+ goto error;
+ return;
+
+error:
+ puts("error init pwm for backlight\n");
+ return;
+}
+
+struct display_info_t const displays[] = {
+ {
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = NULL,
+ .enable = enable_lvds,
+ .mode = {
+ .name = "lb07wv8",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 33246,
+ .left_margin = 88,
+ .right_margin = 88,
+ .upper_margin = 10,
+ .lower_margin = 10,
+ .hsync_len = 25,
+ .vsync_len = 1,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+ }
+ }
+};
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int reg;
+
+ enable_ipu_clock();
+
+ reg = readl(&mxc_ccm->cs2cdr);
+ /* select pll 5 clock */
+ reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
+ reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ imx_iomux_v3_setup_multiple_pads(backlight_pads,
+ ARRAY_SIZE(backlight_pads));
+}
+
+/* no console on this board */
+int board_cfb_skip(void)
+{
+ return 1;
+}
+#endif
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_gpio();
+
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display();
+#endif
+ return 0;
+}
+
+iomux_v3_cfg_t nfc_pads[] = {
+ MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ imx_iomux_v3_setup_multiple_pads(nfc_pads,
+ ARRAY_SIZE(nfc_pads));
+
+ /* config gpmi and bch clock to 100 MHz */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+ /* enable gpmi and bch clock gating */
+ setbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+
+int board_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ setup_spi();
+
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
+ &i2c_pad_info1);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
+ &i2c_pad_info2);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
+ &i2c_pad_info3);
+
+ /* i2c4 not used, set it to gpio input */
+ gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl");
+ gpio_direction_input(IMX_GPIO_NR(1, 7));
+ gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda");
+ gpio_direction_input(IMX_GPIO_NR(1, 8));
+
+ /* SPI NOR Flash read only */
+ gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor");
+ gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0);
+ gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH);
+
+ /* enable LED */
+ gpio_request(IMX_GPIO_NR(2, 13), "LED ena");
+ gpio_direction_output(IMX_GPIO_NR(2, 13), 0);
+
+ gpio_request(IMX_GPIO_NR(1, 3), "LED yellow");
+ gpio_direction_output(IMX_GPIO_NR(1, 3), 1);
+ gpio_request(IMX_GPIO_NR(1, 4), "LED red");
+ gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
+ gpio_request(IMX_GPIO_NR(1, 5), "LED green");
+ gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
+ gpio_request(IMX_GPIO_NR(1, 6), "LED blue");
+ gpio_direction_output(IMX_GPIO_NR(1, 6), 1);
+
+ setup_gpmi_nand();
+
+ /* GPIO_1 for USB_OTG_ID */
+ setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK);
+ imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: aristaitenos\n");
+ return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+ int ret;
+
+ ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr");
+ if (!ret)
+ gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1);
+ ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr");
+ if (!ret)
+ gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1);
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ if (port)
+ gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on);
+ else
+ gpio_set_value(ARISTAINETOS_USB_H1_PWR, on);
+ return 0;
+}
+#endif
diff --git a/board/aristainetos/aristainetos.cfg b/board/aristainetos/aristainetos.cfg
new file mode 100644
index 0000000..2290180
--- /dev/null
+++ b/board/aristainetos/aristainetos.cfg
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2014
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd
+ */
+BOOT_FROM spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup.cfg"
+#include "mt41j128M.cfg"
+#include "clocks.cfg"
diff --git a/board/aristainetos/clocks.cfg b/board/aristainetos/clocks.cfg
new file mode 100644
index 0000000..651449e
--- /dev/null
+++ b/board/aristainetos/clocks.cfg
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00c03f3f
+DATA 4, CCM_CCGR1, 0x0030fcff
+DATA 4, CCM_CCGR2, 0x0fffcfc0
+DATA 4, CCM_CCGR3, 0x3ff0300f
+DATA 4, CCM_CCGR4, 0xfffff30c /* enable NAND/GPMI/BCH clocks */
+DATA 4, CCM_CCGR5, 0x0f0000c3
+DATA 4, CCM_CCGR6, 0x000003ff
diff --git a/board/aristainetos/ddr-setup.cfg b/board/aristainetos/ddr-setup.cfg
new file mode 100644
index 0000000..c72a3ef
--- /dev/null
+++ b/board/aristainetos/ddr-setup.cfg
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* DDR IO TYPE */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+/* Clock */
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
+/* Address */
+DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+/* Control */
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+/* Data Strobe */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
diff --git a/board/aristainetos/mt41j128M.cfg b/board/aristainetos/mt41j128M.cfg
new file mode 100644
index 0000000..3561655
--- /dev/null
+++ b/board/aristainetos/mt41j128M.cfg
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/* ZQ Calibration */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
+/*
+ * DQS gating, read delay, write delay calibration values
+ * based on calibration compare of 0x00ffff00
+ */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E
+/* read data bit delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+/* Complete calibration by forced measurment */
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+/* in DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00440e21
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
+/* MR2 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x0400803a
+/* MR3 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b
+/* MR1 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
+/* MR0 */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x07208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x07208038
+/* ZQ calibration */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
+/* final ddr setup */
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000007
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
+DATA 4, MX6_MMDC_P1_MAPSR, 0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 84294db..60a09f4 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -644,8 +644,7 @@ int overwrite_console(void)
int board_init(void)
{
- struct iomuxc_base_regs *const iomuxc_regs
- = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
clrsetbits_le32(&iomuxc_regs->gpr[1],
IOMUXC_GPR1_OTG_ID_MASK,
diff --git a/board/davinci/dm355evm/MAINTAINERS b/board/davinci/dm355evm/MAINTAINERS
index b823785..ef586b3 100644
--- a/board/davinci/dm355evm/MAINTAINERS
+++ b/board/davinci/dm355evm/MAINTAINERS
@@ -1,6 +1,6 @@
DM355EVM BOARD
M: Sandeep Paulraj <s-paulraj@ti.com>
-S: Maintained
+S: Orphan (since 2014-08)
F: board/davinci/dm355evm/
F: include/configs/davinci_dm355evm.h
F: configs/davinci_dm355evm_defconfig
diff --git a/board/davinci/dm355leopard/MAINTAINERS b/board/davinci/dm355leopard/MAINTAINERS
index f17fea2..2fc1e00 100644
--- a/board/davinci/dm355leopard/MAINTAINERS
+++ b/board/davinci/dm355leopard/MAINTAINERS
@@ -1,6 +1,6 @@
DM355LEOPARD BOARD
M: Sandeep Paulraj <s-paulraj@ti.com>
-S: Maintained
+S: Orphan (since 2014-08)
F: board/davinci/dm355leopard/
F: include/configs/davinci_dm355leopard.h
F: configs/davinci_dm355leopard_defconfig
diff --git a/board/davinci/dm365evm/MAINTAINERS b/board/davinci/dm365evm/MAINTAINERS
index 5adb4e0..0bfe02d 100644
--- a/board/davinci/dm365evm/MAINTAINERS
+++ b/board/davinci/dm365evm/MAINTAINERS
@@ -1,6 +1,6 @@
DM365EVM BOARD
M: Sandeep Paulraj <s-paulraj@ti.com>
-S: Maintained
+S: Orphan (since 2014-08)
F: board/davinci/dm365evm/
F: include/configs/davinci_dm365evm.h
F: configs/davinci_dm365evm_defconfig
diff --git a/board/davinci/dm6467evm/MAINTAINERS b/board/davinci/dm6467evm/MAINTAINERS
index 4030bf3..bb40536 100644
--- a/board/davinci/dm6467evm/MAINTAINERS
+++ b/board/davinci/dm6467evm/MAINTAINERS
@@ -1,6 +1,6 @@
DM6467EVM BOARD
M: Sandeep Paulraj <s-paulraj@ti.com>
-S: Maintained
+S: Orphan (since 2014-08)
F: board/davinci/dm6467evm/
F: include/configs/davinci_dm6467evm.h
F: configs/davinci_dm6467evm_defconfig
diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c
index d06b57d..530ea4f 100644
--- a/board/embest/mx6boards/mx6boards.c
+++ b/board/embest/mx6boards/mx6boards.c
@@ -246,6 +246,7 @@ int board_mmc_init(bd_t *bis)
riotboard_usdhc3_pads,
ARRAY_SIZE(riotboard_usdhc3_pads));
gpio_direction_input(USDHC3_CD_GPIO);
+ } else {
gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
udelay(250);
gpio_set_value(IMX_GPIO_NR(7, 8), 1);
diff --git a/board/flagadm/Kconfig b/board/flagadm/Kconfig
deleted file mode 100644
index bc0657e..0000000
--- a/board/flagadm/Kconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-if TARGET_FLAGADM
-
-config SYS_BOARD
- string
- default "flagadm"
-
-config SYS_CONFIG_NAME
- string
- default "FLAGADM"
-
-endif
diff --git a/board/flagadm/MAINTAINERS b/board/flagadm/MAINTAINERS
deleted file mode 100644
index 606989c..0000000
--- a/board/flagadm/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-FLAGADM BOARD
-M: Kári Davíðsson <kd@flaga.is>
-S: Orphan (since 2014-06)
-F: board/flagadm/
-F: include/configs/FLAGADM.h
-F: configs/FLAGADM_defconfig
diff --git a/board/flagadm/Makefile b/board/flagadm/Makefile
deleted file mode 100644
index f2377c8..0000000
--- a/board/flagadm/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = flagadm.o flash.o
diff --git a/board/flagadm/flagadm.c b/board/flagadm/flagadm.c
deleted file mode 100644
index 343cb77..0000000
--- a/board/flagadm/flagadm.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-/*Orginal table, GPL4 disabled*/
-const uint sdram_table[] =
-{
- /* single read (offset 0x00 in upm ram) */
- 0x1f07cc04, 0xeeaeec04, 0x11adcc04, 0xefbbac00,
- 0x1ff74c47,
- /* Precharge */
- 0x1FF74C05,
- _NOT_USED_,
- _NOT_USED_,
- /* burst read (offset 0x08 in upm ram) */
- 0x1f07cc04, 0xeeaeec04, 0x00adcc04, 0x00afcc00,
- 0x00afcc00, 0x01afcc00, 0x0fbb8c00, 0x1ff74c47,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* single write (offset 0x18 in upm ram) */
- 0x1f27cc04, 0xeeaeac00, 0x01b90c04, 0x1ff74c47,
- /* Load moderegister */
- 0x1FF74C34, /*Precharge*/
- 0xEFEA8C34, /*NOP*/
- 0x1FB54C35, /*Load moderegister*/
- _NOT_USED_,
-
- /* burst write (offset 0x20 in upm ram) */
- 0x1f07cc04, 0xeeaeac00, 0x00ad4c00, 0x00afcc00,
- 0x00afcc00, 0x01bb8c04, 0x1ff74c47, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* refresh (offset 0x30 in upm ram) */
- 0x1ff5cc84, 0xffffec04, 0xffffec04, 0xffffec04,
- 0xffffec84, 0xffffec07, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* exception (offset 0x3C in upm ram) */
- 0x7fffec07, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-/* GPL5 driven every cycle */
-/* the display and the DSP */
-const uint dsp_disp_table[] =
-{
- /* single read (offset 0x00 in upm ram) */
- 0xffffc80c, 0xffffc004, 0x0fffc004, 0x0fffd004,
- 0x0fffc000, 0x0fffc004, 0x3fffc004, 0xffffcc05,
- /* burst read (offset 0x08 in upm ram) */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* single write (offset 0x18 in upm ram) */
- 0xffffcc0c, 0xffffc004, 0x0fffc004, 0x0fffd004,
- 0x0fffc000, 0x0fffc004, 0x7fffc004, 0xfffffc05,
- /* burst write (offset 0x20 in upm ram) */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* refresh (offset 0x30 in upm ram) */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- /* exception (offset 0x3C in upm ram) */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-int checkboard (void)
-{
- puts ("Board: FlagaDM V3.0\n");
- return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size_b0;
-
- memctl->memc_or2 = CONFIG_SYS_OR2;
- memctl->memc_br2 = CONFIG_SYS_BR2;
-
- udelay(100);
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
- memctl->memc_mptpr = MPTPR_PTP_DIV16;
- memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_1X;
-
- /*Do the initialization of the SDRAM*/
- /*Start with the precharge cycle*/
- memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
- MCR_MLCF(1) | MCR_MAD(0x5));
-
- /*Then we need two refresh cycles*/
- memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_2X;
- memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
- MCR_MLCF(2) | MCR_MAD(0x30));
-
- /*Mode register programming*/
- memctl->memc_mar = 0x00000088; /*CAS Latency = 2 and burst length = 4*/
- memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
- MCR_MLCF(1) | MCR_MAD(0x1C));
-
- /* That should do it, just enable the periodic refresh in burst of 4*/
- memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_4X;
- memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS);
-
- size_b0 = 16*1024*1024;
-
- /*
- * No bank 1 or 3
- * invalidate bank
- */
- memctl->memc_br1 = 0;
- memctl->memc_br3 = 0;
-
- upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint));
-
- memctl->memc_mbmr = MBMR_GPL_B4DIS;
-
- memctl->memc_or4 = CONFIG_SYS_OR4;
- memctl->memc_br4 = CONFIG_SYS_BR4;
-
- return (size_b0);
-}
diff --git a/board/flagadm/flash.c b/board/flagadm/flash.c
deleted file mode 100644
index 46a2c9a..0000000
--- a/board/flagadm/flash.c
+++ /dev/null
@@ -1,687 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <flash.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-ulong flash_recognize (vu_long *base);
-int write_word (flash_info_t *info, ulong dest, ulong data);
-void flash_get_geometry (vu_long *base, flash_info_t *info);
-void flash_unprotect(flash_info_t *info);
-int _flash_real_protect(flash_info_t *info, long idx, int on);
-
-
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- int i;
- int rec;
-
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- *((vu_short*)CONFIG_SYS_FLASH_BASE) = 0xffff;
-
- flash_get_geometry ((vu_long*)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
- (memctl->memc_br0 & ~(BR_BA_MSK));
-
- rec = flash_recognize((vu_long*)CONFIG_SYS_FLASH_BASE);
-
- if (rec == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- flash_info[0].size, flash_info[0].size<<20);
- }
-
-#if CONFIG_SYS_FLASH_PROTECTION
- /*Unprotect all the flash memory*/
- flash_unprotect(&flash_info[0]);
-#endif
-
- *((vu_short*)CONFIG_SYS_FLASH_BASE) = 0xffff;
-
- return (flash_info[0].size);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_OFFSET,
- CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE-1,
- &flash_info[0]);
-#endif
- return (flash_info[0].size);
-}
-
-
-int flash_get_protect_status(flash_info_t * info, long idx)
-{
- vu_short * base;
- ushort res;
-
-#ifdef DEBUG
- printf("\n Attempting to set protection info with %d sectors\n", info->sector_count);
-#endif
-
-
- base = (vu_short*)info->start[idx];
-
- *(base) = 0xffff;
-
- *(base + 0x55) = 0x0098;
- res = base[0x2];
-
- *(base) = 0xffff;
-
- if(res != 0)
- res = 1;
- else
- res = 0;
-
- return res;
-}
-
-void flash_get_geometry (vu_long *base, flash_info_t *info)
-{
- int i,j;
- ulong ner = 0;
- vu_short * sb = (vu_short*)base;
- ulong offset = (ulong)base;
-
- /* Read Device geometry */
-
- *sb = 0xffff;
-
- *sb = 0x0090;
-
- info->flash_id = ((ulong)base[0x0]);
-#ifdef DEBUG
- printf("Id is %x\n", (uint)(ulong)info->flash_id);
-#endif
-
- *sb = 0xffff;
-
- *(sb+0x55) = 0x0098;
-
- info->size = 1 << (sb[0x27]); /* Read flash size */
-
-#ifdef DEBUG
- printf("Size is %x\n", (uint)(ulong)info->size);
-#endif
-
- *sb = 0xffff;
-
- *(sb + 0x55) = 0x0098;
- ner = sb[0x2c] ; /*Number of erase regions*/
-
-#ifdef DEBUG
- printf("Number of erase regions %x\n", (uint)ner);
-#endif
-
- info->sector_count = 0;
-
- for(i = 0; i < ner; i++)
- {
- uint s;
- uint count;
- uint t1,t2,t3,t4;
-
- *sb = 0xffff;
-
- *(sb + 0x55) = 0x0098;
-
- t1 = sb[0x2d + i*4];
- t2 = sb[0x2e + i*4];
- t3 = sb[0x2f + i*4];
- t4 = sb[0x30 + i*4];
-
- count = ((t1 & 0x00ff) | (((t2 & 0x00ff) << 8) & 0xff00) )+ 1; /*sector count*/
- s = ((t3 & 0x00ff) | (((t4 & 0x00ff) << 8) & 0xff00)) * 256;; /*Sector size*/
-
-#ifdef DEBUG
- printf("count and size %x, %x\n", count, s);
- printf("sector count for erase region %d is %d\n", i, count);
-#endif
- for(j = 0; j < count; j++)
- {
-#ifdef DEBUG
- printf("%x, ", (uint)offset);
-#endif
- info->start[ info->sector_count + j] = offset;
- offset += s;
- }
- info->sector_count += count;
- }
-
- if ((offset - (ulong)base) != info->size)
- printf("WARNING reported size %x does not match to calculted size %x.\n"
- , (uint)info->size, (uint)(offset - (ulong)base) );
-
- /* Next check if there are any sectors protected.*/
-
- for(i = 0; i < info->sector_count; i++)
- info->protect[i] = flash_get_protect_status(info, i);
-
- *sb = 0xffff;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return ;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case INTEL_MANUFACT & FLASH_VENDMASK:
- printf ("Intel ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case INTEL_ID_28F320C3B & FLASH_TYPEMASK:
- printf ("28F320RC3(4 MB)\n");
- break;
- case INTEL_ID_28F320J3A:
- printf("28F320J3A (4 MB)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 4) == 0)
- printf ("\n ");
- printf (" %02d %08lX%s",
- i, info->start[i],
- info->protect[i]!=0 ? " (RO)" : " "
- );
- }
- printf ("\n");
- return ;
-}
-
-ulong flash_recognize (vu_long *base)
-{
- ulong id;
- ulong res = FLASH_UNKNOWN;
- vu_short * sb = (vu_short*)base;
-
- *sb = 0xffff;
-
- *sb = 0x0090;
- id = base[0];
-
- switch (id & 0x00FF0000)
- {
- case (MT_MANUFACT & 0x00FF0000): /* MT or => Intel */
- case (INTEL_ALT_MANU & 0x00FF0000):
- res = FLASH_MAN_INTEL;
- break;
- default:
- res = FLASH_UNKNOWN;
- }
-
- *sb = 0xffff;
-
- return res;
-}
-
-/*-----------------------------------------------------------------------*/
-#define INTEL_FLASH_STATUS_BLS 0x02
-#define INTEL_FLASH_STATUS_PSS 0x04
-#define INTEL_FLASH_STATUS_VPPS 0x08
-#define INTEL_FLASH_STATUS_PS 0x10
-#define INTEL_FLASH_STATUS_ES 0x20
-#define INTEL_FLASH_STATUS_ESS 0x40
-#define INTEL_FLASH_STATUS_WSMS 0x80
-
-int flash_decode_status_bits(char status)
-{
- int err = 0;
-
- if(!(status & INTEL_FLASH_STATUS_WSMS)) {
- printf("Busy\n");
- err = -1;
- }
-
- if(status & INTEL_FLASH_STATUS_ESS) {
- printf("Erase suspended\n");
- err = -1;
- }
-
- if(status & INTEL_FLASH_STATUS_ES) {
- printf("Error in block erase\n");
- err = -1;
- }
-
- if(status & INTEL_FLASH_STATUS_PS) {
- printf("Error in programming\n");
- err = -1;
- }
-
- if(status & INTEL_FLASH_STATUS_VPPS) {
- printf("Vpp low, operation aborted\n");
- err = -1;
- }
-
- if(status & INTEL_FLASH_STATUS_PSS) {
- printf("Program is suspended\n");
- err = -1;
- }
-
- if(status & INTEL_FLASH_STATUS_BLS) {
- printf("Attempting to program/erase a locked sector\n");
- err = -1;
- }
-
- if((status & INTEL_FLASH_STATUS_PS) &&
- (status & INTEL_FLASH_STATUS_ES) &&
- (status & INTEL_FLASH_STATUS_ESS)) {
- printf("A command sequence error\n");
- return -1;
- }
-
- return err;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_short *addr;
- int flag, prot, sect;
- ulong start, now;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- char tmp;
-
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_short *)(info->start[sect]);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Single Block Erase Command */
- *addr = 0x0020;
- /* Confirm */
- *addr = 0x00D0;
- /* Resume Command, as per errata update */
- *addr = 0x00D0;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- *addr = 0x70; /*Read status register command*/
- tmp = (short)*addr & 0x00FF; /* Read the status */
- while (!(tmp & INTEL_FLASH_STATUS_WSMS)) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- *addr = 0x0050; /* Reset the status register */
- *addr = 0xffff;
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - start) > 1000) { /* every second */
- putc ('.');
- }
- udelay(100000); /* 100 ms */
- *addr = 0x0070; /*Read status register command*/
- tmp = (short)*addr & 0x00FF; /* Read status */
- start = get_timer(0);
- }
- if( tmp & INTEL_FLASH_STATUS_ES )
- flash_decode_status_bits(tmp);
-
- *addr = 0x0050; /* Reset the status register */
- *addr = 0xffff; /* Reset to read mode */
- }
- }
-
-
- printf (" done\n");
- return rcode;
-}
-
-void flash_unprotect (flash_info_t *info)
-{
- /*We can only unprotect the whole flash at once*/
- /*Therefore we must prevent the _flash_real_protect()*/
- /*from re-protecting sectors, that ware protected before */
- /*we called flash_real_protect();*/
-
- int i;
-
- for(i = 0; i < info->sector_count; i++)
- info->protect[i] = 0;
-
-#ifdef CONFIG_SYS_FLASH_PROTECTION
- _flash_real_protect(info, 0, 0);
-#endif
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_word (flash_info_t *info, ulong dest, ulong da)
-{
- vu_short *addr = (vu_short *)dest;
- ulong start;
- char csr;
- int flag;
- int i;
- union {
- u32 data32;
- u16 data16[2];
- } data;
-
- data.data32 = da;
-
- /* Check if Flash is (sufficiently) erased */
- if (((*addr & data.data16[0]) != data.data16[0]) ||
- ((*(addr+1) & data.data16[1]) != data.data16[1])) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- for(i = 0; i < 2; i++)
- {
- /* Write Command */
- *addr = 0x0010;
-
- /* Write Data */
- *addr = data.data16[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- flag = 0;
- *addr = 0x0070; /*Read statusregister command */
- while (((csr = *addr) & INTEL_FLASH_STATUS_WSMS)!=INTEL_FLASH_STATUS_WSMS) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- flag = 1;
- break;
- }
- *addr = 0x0070; /*Read statusregister command */
- }
- if (csr & INTEL_FLASH_STATUS_PSS) {
- printf ("CSR indicates write error (%0x) at %08lx\n",
- csr, (ulong)addr);
- flag = 1;
- }
-
- /* Clear Status Registers Command */
- *addr = 0x0050;
- /* Reset to read array mode */
- *addr = 0xffff;
- addr++;
- }
-
- return (flag);
-}
-
-int flash_real_protect(flash_info_t *info, long offset, int prot)
-{
- int i, idx;
-
- for(idx = 0; idx < info->sector_count; idx++)
- if(info->start[idx] == offset)
- break;
-
- if(idx==info->sector_count)
- return -1;
-
- if(prot == 0) {
- /* Unprotect one sector, which means unprotect all flash
- * and reprotect the other protected sectors.
- */
- _flash_real_protect(info, 0, 0); /* Unprotects the whole flash*/
- info->protect[idx] = 0;
-
- for(i = 0; i < info->sector_count; i++)
- if(info->protect[i])
- _flash_real_protect(info, i, 1);
- }
- else {
- /* We can protect individual sectors */
- _flash_real_protect(info, idx, 1);
- }
-
- for( i = 0; i < info->sector_count; i++)
- info->protect[i] = flash_get_protect_status(info, i);
-
- return 0;
-}
-
-int _flash_real_protect(flash_info_t *info, long idx, int prot)
-{
- vu_short *addr;
- int flag;
- ushort cmd;
- ushort tmp;
- ulong now, start;
-
- if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) {
- printf ("Can't change protection for unknown flash type %08lx - aborted\n",
- info->flash_id);
- return -1;
- }
-
- if(prot == 0) {
- /*Unlock the sector*/
- cmd = 0x00D0;
- }
- else {
- /*Lock the sector*/
- cmd = 0x0001;
- }
-
- addr = (vu_short *)(info->start[idx]);
-
- /* If chip is busy, wait for it */
- start = get_timer(0);
- *addr = 0x0070; /*Read status register command*/
- tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/
- while(!(tmp & INTEL_FLASH_STATUS_WSMS)) {
- /*Write State Machine Busy*/
- /*Wait untill done or timeout.*/
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = 0x0050; /* Reset the status register */
- *addr = 0xffff; /* Reset the chip */
- printf ("TTimeout\n");
- return 1;
- }
- *addr = 0x0070;
- tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/
- start = get_timer(0);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Unlock block*/
- *addr = 0x0060;
-
- *addr = cmd;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer(0);
- *addr = 0x0070; /*Read status register command*/
- tmp = ((ushort)(*addr)) & 0x00FF; /* Read the status */
- while (!(tmp & INTEL_FLASH_STATUS_WSMS)) {
- /* Write State Machine Busy */
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = 0x0050; /* Reset the status register */
- *addr = 0xffff;
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - start) > 1000) { /* every second */
- putc ('.');
- }
- udelay(100000); /* 100 ms */
- *addr = 0x70; /*Read status register command*/
- tmp = (short)*addr & 0x00FF; /* Read status */
- start = get_timer(0);
- }
- if( tmp & INTEL_FLASH_STATUS_PS )
- flash_decode_status_bits(tmp);
-
- *addr =0x0050; /*Clear status register*/
-
- /* reset to read mode */
- *addr = 0xffff;
-
- return 0;
-}
diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds
deleted file mode 100644
index 7ae91ff..0000000
--- a/board/flagadm/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2001-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug
deleted file mode 100644
index b0091db..0000000
--- a/board/flagadm/u-boot.lds.debug
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 22b57cc..50d7731 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -34,6 +34,8 @@ ifndef CONFIG_RAMBOOT_PBL
obj-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o
endif
+obj-$(CONFIG_FSL_DIU_CH7301) += diu_ch7301.o
+
obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
obj-$(CONFIG_MPC8548CDS) += cds_pci_ft.o
obj-$(CONFIG_MPC8555CDS) += cds_pci_ft.o
diff --git a/board/freescale/common/diu_ch7301.c b/board/freescale/common/diu_ch7301.c
new file mode 100644
index 0000000..82ce870
--- /dev/null
+++ b/board/freescale/common/diu_ch7301.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Authors: Priyanka Jain <Priyanka.Jain@freescale.com>
+ * Wang Dongsheng <dongsheng.wang@freescale.com>
+ *
+ * This file is copied and modified from the original t1040qds/diu.c.
+ * Encoder can be used in T104x and LSx Platform.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <stdio_dev.h>
+#include <i2c.h>
+
+#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F
+#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33
+#define I2C_DVI_PLL_DIVIDER_REG 0x34
+#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35
+#define I2C_DVI_PLL_FILTER_REG 0x36
+#define I2C_DVI_TEST_PATTERN_REG 0x48
+#define I2C_DVI_POWER_MGMT_REG 0x49
+#define I2C_DVI_LOCK_STATE_REG 0x4D
+#define I2C_DVI_SYNC_POLARITY_REG 0x56
+
+/*
+ * Set VSYNC/HSYNC to active high. This is polarity of sync signals
+ * from DIU->DVI. The DIU default is active igh, so DVI is set to
+ * active high.
+ */
+#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98
+
+#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06
+#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26
+#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0
+#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08
+#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16
+#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60
+
+/* Clear test pattern */
+#define I2C_DVI_TEST_PATTERN_VAL 0x18
+/* Exit Power-down mode */
+#define I2C_DVI_POWER_MGMT_VAL 0xC0
+
+/* Monitor polarity is handled via DVI Sync Polarity Register */
+#define I2C_DVI_SYNC_POLARITY_VAL 0x00
+
+/* Programming of HDMI Chrontel CH7301 connector */
+int diu_set_dvi_encoder(unsigned int pixclock)
+{
+ int ret;
+ u8 temp;
+
+ temp = I2C_DVI_TEST_PATTERN_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
+ &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select proper dvi test pattern\n");
+ return ret;
+ }
+ temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
+ 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi input data format\n");
+ return ret;
+ }
+
+ /* Set Sync polarity register */
+ temp = I2C_DVI_SYNC_POLARITY_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
+ &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi syc polarity\n");
+ return ret;
+ }
+
+ /* Set PLL registers based on pixel clock rate*/
+ if (pixclock > 65000000) {
+ temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll charge_cntl\n");
+ return ret;
+ }
+ temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll divider\n");
+ return ret;
+ }
+ temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll filter\n");
+ return ret;
+ }
+ } else {
+ temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll charge_cntl\n");
+ return ret;
+ }
+ temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll divider\n");
+ return ret;
+ }
+ temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
+ I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi pll filter\n");
+ return ret;
+ }
+ }
+
+ temp = I2C_DVI_POWER_MGMT_VAL;
+ ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
+ &temp, 1);
+ if (ret) {
+ puts("I2C: failed to select dvi power mgmt\n");
+ return ret;
+ }
+
+ udelay(500);
+
+ return 0;
+}
diff --git a/board/freescale/common/diu_ch7301.h b/board/freescale/common/diu_ch7301.h
new file mode 100644
index 0000000..8b6ead0
--- /dev/null
+++ b/board/freescale/common/diu_ch7301.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DIU_HDMI_CH7301__
+#define __DIU_HDMI_CH7301__
+
+/* Programming of HDMI Chrontel CH7301 connector */
+int diu_set_dvi_encoder(unsigned int pixclock);
+
+#endif
diff --git a/board/freescale/mx31pdk/MAINTAINERS b/board/freescale/mx31pdk/MAINTAINERS
index 2e057db..ec2a320 100644
--- a/board/freescale/mx31pdk/MAINTAINERS
+++ b/board/freescale/mx31pdk/MAINTAINERS
@@ -1,5 +1,5 @@
MX31PDK BOARD
-M: Fabio Estevam <fabio.estevam@freescale.com>
+M: Magnus Lilja <lilja.magnus@gmail.com>
S: Maintained
F: board/freescale/mx31pdk/
F: include/configs/mx31pdk.h
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index d7c4b4f..80c8ebd 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -466,7 +466,7 @@ static int pfuze_init(void)
if (ret)
return ret;
- p = pmic_get("PFUZE100_PMIC");
+ p = pmic_get("PFUZE100");
ret = pmic_probe(p);
if (ret)
return ret;
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index d2b64cc..a990b4c 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -130,8 +130,7 @@ int board_eth_init(bd_t *bis)
static int setup_fec(void)
{
- struct iomuxc_base_regs *iomuxc_regs =
- (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
/* clear gpr1[14], gpr1[18:17] to select anatop clock */
diff --git a/board/ti/omap5912osk/Kconfig b/board/freescale/mx6sxsabresd/Kconfig
index 9f7493a..ee8f4a6 100644
--- a/board/ti/omap5912osk/Kconfig
+++ b/board/freescale/mx6sxsabresd/Kconfig
@@ -1,23 +1,23 @@
-if TARGET_OMAP5912OSK
+if TARGET_MX6SXSABRESD
config SYS_CPU
string
- default "arm926ejs"
+ default "armv7"
config SYS_BOARD
string
- default "omap5912osk"
+ default "mx6sxsabresd"
config SYS_VENDOR
string
- default "ti"
+ default "freescale"
config SYS_SOC
string
- default "omap"
+ default "mx6"
config SYS_CONFIG_NAME
string
- default "omap5912osk"
+ default "mx6sxsabresd"
endif
diff --git a/board/freescale/mx6sxsabresd/MAINTAINERS b/board/freescale/mx6sxsabresd/MAINTAINERS
new file mode 100644
index 0000000..f52f300
--- /dev/null
+++ b/board/freescale/mx6sxsabresd/MAINTAINERS
@@ -0,0 +1,6 @@
+MX6SXSABRESD BOARD
+M: Fabio Estevam <fabio.estevam@freescale.com>
+S: Maintained
+F: board/freescale/mx6sxsabresd/
+F: include/configs/mx6sxsabresd.h
+F: configs/mx6sxsabresd_defconfig
diff --git a/board/freescale/mx6sxsabresd/Makefile b/board/freescale/mx6sxsabresd/Makefile
new file mode 100644
index 0000000..97dbfda
--- /dev/null
+++ b/board/freescale/mx6sxsabresd/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := mx6sxsabresd.o
diff --git a/board/freescale/mx6sxsabresd/imximage.cfg b/board/freescale/mx6sxsabresd/imximage.cfg
new file mode 100644
index 0000000..c862617
--- /dev/null
+++ b/board/freescale/mx6sxsabresd/imximage.cfg
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* IOMUX - DDR IO Type */
+DATA 4 0x020e0618 0x000c0000
+DATA 4 0x020e05fc 0x00000000
+
+/* Clock */
+DATA 4 0x020e032c 0x00000030
+
+/* Address */
+DATA 4 0x020e0300 0x00000020
+DATA 4 0x020e02fc 0x00000020
+DATA 4 0x020e05f4 0x00000020
+
+/* Control */
+DATA 4 0x020e0340 0x00000020
+
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000020
+DATA 4 0x020e0314 0x00000020
+DATA 4 0x020e0614 0x00000020
+
+/* Data Strobe */
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00000028
+DATA 4 0x020e0334 0x00000028
+DATA 4 0x020e0338 0x00000028
+DATA 4 0x020e033c 0x00000028
+
+/* Data */
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000028
+DATA 4 0x020e0610 0x00000028
+DATA 4 0x020e061c 0x00000028
+DATA 4 0x020e0620 0x00000028
+DATA 4 0x020e02ec 0x00000028
+DATA 4 0x020e02f0 0x00000028
+DATA 4 0x020e02f4 0x00000028
+DATA 4 0x020e02f8 0x00000028
+
+/* Calibrations - ZQ */
+DATA 4 0x021b0800 0xa1390003
+
+/* Write leveling */
+DATA 4 0x021b080c 0x00290025
+DATA 4 0x021b0810 0x00220022
+
+/* DQS Read Gate */
+DATA 4 0x021b083c 0x41480144
+DATA 4 0x021b0840 0x01340130
+
+/* Read/Write Delay */
+DATA 4 0x021b0848 0x3C3E4244
+DATA 4 0x021b0850 0x34363638
+
+/* Read data bit delay */
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+/* Complete calibration by forced measurement */
+DATA 4 0x021b08b8 0x00000800
+
+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333030
+DATA 4 0x021b000c 0x676b52f3
+DATA 4 0x021b0010 0xb66d8b63
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00011740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006b1023
+DATA 4 0x021b0040 0x0000005f
+DATA 4 0x021b0000 0x84190000
+
+/* Initialize MT41K256M16HA-125 - MR2 */
+DATA 4 0x021b001c 0x04008032
+/* MR3 */
+DATA 4 0x021b001c 0x00008033
+/* MR1 */
+DATA 4 0x021b001c 0x00048031
+/* MR0 */
+DATA 4 0x021b001c 0x05208030
+/* DDR device ZQ calibration */
+DATA 4 0x021b001c 0x04008040
+
+/* Final DDR setup, before operation start */
+DATA 4 0x021b0020 0x00000800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b001c 0x00000000
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
new file mode 100644
index 0000000..5eaec1b
--- /dev/null
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -0,0 +1,295 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE)
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec1_pads[] = {
+ MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+ MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const peri_3v3_pads[] = {
+ MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const phy_control_pads[] = {
+ /* 25MHz Ethernet PHY Clock */
+ MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+
+ /* ENET PHY Power */
+ MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+ /* AR8031 PHY Reset */
+ MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+ int ret;
+ int reg;
+
+ /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
+
+ imx_iomux_v3_setup_multiple_pads(phy_control_pads,
+ ARRAY_SIZE(phy_control_pads));
+
+ /* Enable the ENET power, active low */
+ gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
+
+ /* Reset AR8031 PHY */
+ gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
+ udelay(500);
+ gpio_set_value(IMX_GPIO_NR(2, 7), 1);
+
+ reg = readl(&anatop->pll_enet);
+ reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
+ writel(reg, &anatop->pll_enet);
+
+ ret = enable_fec_anatop_clock(ENET_125MHz);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+ setup_fec();
+
+ return cpu_eth_init(bis);
+}
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
+ .gp = IMX_GPIO_NR(1, 0),
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
+ .gp = IMX_GPIO_NR(1, 1),
+ },
+};
+
+static int pfuze_init(void)
+{
+ struct pmic *p;
+ int ret;
+ unsigned int reg;
+
+ ret = power_pfuze100_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get("PFUZE100");
+ ret = pmic_probe(p);
+ if (ret)
+ return ret;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+
+ /* Set SW1AB standby voltage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+ reg &= ~0x3f;
+ reg |= 0x1b;
+ pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+ /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
+ reg &= ~0xc0;
+ reg |= 0x40;
+ pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+ /* Set SW1C standby voltage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+ reg &= ~0x3f;
+ reg |= 0x1b;
+ pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+ /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+ reg &= ~0xc0;
+ reg |= 0x40;
+ pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+ /* Enable power of VGEN5 3V3, needed for SD3 */
+ pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
+ reg &= ~0x1F;
+ reg |= 0x1F;
+ pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /*
+ * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
+ * Phy control debug reg 0
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ /* rgmii tx clock delay enable */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+ /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
+ imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
+ ARRAY_SIZE(peri_3v3_pads));
+
+ /* Active high for ncp692 */
+ gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
+
+ return 0;
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC4_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1; /* Assume boot SD always present */
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+int board_init(void)
+{
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ pfuze_init();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX6SX SABRE SDB\n");
+
+ return 0;
+}
diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c
index ffd074b..0214224 100644
--- a/board/freescale/t1040qds/diu.c
+++ b/board/freescale/t1040qds/diu.c
@@ -13,42 +13,9 @@
#include <video_fb.h>
#include <fsl_diu_fb.h>
#include "../common/qixis.h"
+#include "../common/diu_ch7301.h"
#include "t1040qds.h"
#include "t1040qds_qixis.h"
-#include <i2c.h>
-
-
-#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F
-#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33
-#define I2C_DVI_PLL_DIVIDER_REG 0x34
-#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35
-#define I2C_DVI_PLL_FILTER_REG 0x36
-#define I2C_DVI_TEST_PATTERN_REG 0x48
-#define I2C_DVI_POWER_MGMT_REG 0x49
-#define I2C_DVI_LOCK_STATE_REG 0x4D
-#define I2C_DVI_SYNC_POLARITY_REG 0x56
-
-/*
- * Set VSYNC/HSYNC to active high. This is polarity of sync signals
- * from DIU->DVI. The DIU default is active igh, so DVI is set to
- * active high.
- */
-#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98
-
-#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06
-#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26
-#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0
-#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08
-#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16
-#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60
-
-/* Clear test pattern */
-#define I2C_DVI_TEST_PATTERN_VAL 0x18
-/* Exit Power-down mode */
-#define I2C_DVI_POWER_MGMT_VAL 0xC0
-
-/* Monitor polarity is handled via DVI Sync Polarity Register */
-#define I2C_DVI_SYNC_POLARITY_VAL 0x00
/*
* DIU Area Descriptor
@@ -69,98 +36,6 @@
#define AD_COMP_1_SHIFT 4
#define AD_COMP_0_SHIFT 0
-/* Programming of HDMI Chrontel CH7301 connector */
-int diu_set_dvi_encoder(unsigned int pixclock)
-{
- int ret;
- u8 temp;
- select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
-
- temp = I2C_DVI_TEST_PATTERN_VAL;
- ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
- &temp, 1);
- if (ret) {
- puts("I2C: failed to select proper dvi test pattern\n");
- return ret;
- }
- temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
- ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
- 1, &temp, 1);
- if (ret) {
- puts("I2C: failed to select dvi input data format\n");
- return ret;
- }
-
- /* Set Sync polarity register */
- temp = I2C_DVI_SYNC_POLARITY_VAL;
- ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
- &temp, 1);
- if (ret) {
- puts("I2C: failed to select dvi syc polarity\n");
- return ret;
- }
-
- /* Set PLL registers based on pixel clock rate*/
- if (pixclock > 65000000) {
- temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
- ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
- I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
- if (ret) {
- puts("I2C: failed to select dvi pll charge_cntl\n");
- return ret;
- }
- temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
- ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
- I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
- if (ret) {
- puts("I2C: failed to select dvi pll divider\n");
- return ret;
- }
- temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
- ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
- I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
- if (ret) {
- puts("I2C: failed to select dvi pll filter\n");
- return ret;
- }
- } else {
- temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
- ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
- I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
- if (ret) {
- puts("I2C: failed to select dvi pll charge_cntl\n");
- return ret;
- }
- temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
- ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
- I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
- if (ret) {
- puts("I2C: failed to select dvi pll divider\n");
- return ret;
- }
- temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
- ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
- I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
- if (ret) {
- puts("I2C: failed to select dvi pll filter\n");
- return ret;
- }
- }
-
- temp = I2C_DVI_POWER_MGMT_VAL;
- ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
- &temp, 1);
- if (ret) {
- puts("I2C: failed to select dvi power mgmt\n");
- return ret;
- }
-
- udelay(500);
-
- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
- return 0;
-}
-
void diu_set_pixel_clock(unsigned int pixclock)
{
unsigned long speed_ccb, temp;
@@ -172,12 +47,19 @@ void diu_set_pixel_clock(unsigned int pixclock)
pixval = speed_ccb / temp;
/* Program HDMI encoder */
+ /* Switch channel to DIU */
+ select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
+
+ /* Set dispaly encoder */
ret = diu_set_dvi_encoder(temp);
if (ret) {
puts("Failed to set DVI encoder\n");
return;
}
+ /* Switch channel to default */
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
/* Program pixel clock */
out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
((pixval << PXCK_BITS_START) & PXCK_MASK));
diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile
index 6cd304c..b9ef17f 100644
--- a/board/freescale/t104xrdb/Makefile
+++ b/board/freescale/t104xrdb/Makefile
@@ -11,6 +11,7 @@ obj-y += t104xrdb.o
obj-y += cpld.o
obj-y += eth.o
obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_FSL_DIU_FB)+= diu.o
endif
obj-y += ddr.o
obj-y += law.o
diff --git a/board/freescale/t104xrdb/diu.c b/board/freescale/t104xrdb/diu.c
new file mode 100644
index 0000000..3285bef
--- /dev/null
+++ b/board/freescale/t104xrdb/diu.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <command.h>
+#include <fsl_diu_fb.h>
+#include <linux/ctype.h>
+#include <video_fb.h>
+
+#include "../common/diu_ch7301.h"
+
+#include "cpld.h"
+#include "t104xrdb.h"
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register. So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F 0x10000000
+#define AD_ALPHA_C_SHIFT 25
+#define AD_BLUE_C_SHIFT 23
+#define AD_GREEN_C_SHIFT 21
+#define AD_RED_C_SHIFT 19
+#define AD_PIXEL_S_SHIFT 16
+#define AD_COMP_3_SHIFT 12
+#define AD_COMP_2_SHIFT 8
+#define AD_COMP_1_SHIFT 4
+#define AD_COMP_0_SHIFT 0
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+ unsigned long speed_ccb, temp;
+ u32 pixval;
+ int ret;
+
+ speed_ccb = get_bus_freq(0);
+ temp = 1000000000 / pixclock;
+ temp *= 1000;
+ pixval = speed_ccb / temp;
+
+ /* Program HDMI encoder */
+ ret = diu_set_dvi_encoder(temp);
+ if (ret) {
+ puts("Failed to set DVI encoder\n");
+ return;
+ }
+
+ /* Program pixel clock */
+ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
+ ((pixval << PXCK_BITS_START) & PXCK_MASK));
+
+ /* enable clock*/
+ out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
+ ((pixval << PXCK_BITS_START) & PXCK_MASK));
+}
+
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
+{
+ u32 pixel_format;
+ u8 sw;
+
+ /*Configure Display ouput port as HDMI*/
+ sw = CPLD_READ(sfp_ctl_status);
+ CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP));
+
+ pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
+ (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
+ (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
+ (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
+ (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
+
+ printf("DIU: Switching to monitor DVI @ %ux%u\n", xres, yres);
+
+ return fsl_diu_init(xres, yres, pixel_format, 0);
+}
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index c628c95..3822a37 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -11,6 +11,7 @@
#include <mmc.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
+#include <asm/mpc85xx_gpio.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -55,6 +56,11 @@ void board_init_f(ulong bootflag)
/* Update GD pointer */
gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+#ifdef CONFIG_DEEP_SLEEP
+ /* disable the console if boot from deep sleep */
+ if (in_be32(&gur->scrtsr[0]) & (1 << 3))
+ gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+#endif
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("" : : : "memory");
@@ -120,3 +126,16 @@ void board_init_r(gd_t *gd, ulong dest_addr)
nand_boot();
#endif
}
+
+#ifdef CONFIG_DEEP_SLEEP
+void board_mem_sleep_setup(void)
+{
+ void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+
+ /* does not provide HW signals for power management */
+ clrbits_8(cpld_base + 0x17, 0x40);
+ /* Disable MCKE isolation */
+ gpio_set_value(2, 0);
+ udelay(1);
+}
+#endif
diff --git a/board/freescale/t4qds/README b/board/freescale/t4qds/README
new file mode 100644
index 0000000..3962fee
--- /dev/null
+++ b/board/freescale/t4qds/README
@@ -0,0 +1,194 @@
+Overview
+--------
+The T4240QDS is a high-performance computing evaluation, development and test
+platform supporting the T4240 QorIQ™ Power Architecture™ processor. T4240QDS is
+optimized to support the high-bandwidth DDR3 memory ports, as well as the
+highly-configurable SerDes ports. The system is lead-free and RoHS-compliant.
+
+Board Features
+ SERDES Connections
+ 32 lanes grouped into four 8-lane banks
+ Two “front side” banks dedicated to Ethernet
+ - High-speed crosspoint switch fabric on selected lanes
+ - Two PCI Express slots with side-band connector supporting
+ - SGMII
+ - XAUI
+ - HiGig
+ - I-pass connectors allow board-to-board and loopback support
+ Two “back side” banks dedicated to other protocols
+ - High-speed crosspoint switch fabric on all lanes
+ - Four PCI Express slots with side-band connector supporting
+ - PCI Express 3.0
+ - SATA 2.0
+ - SRIO 2.0
+ - Supports 4X Aurora debug with two connectors
+ DDR Controllers
+ Three independant 64-bit DDR3 controllers
+ Supports rates of 1866 up to 2133 MHz data-rate
+ Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
+ DDR power supplies 1.5V to all devices with automatic tracking of VTT.
+ Power software-switchable to 1.35V if software detects all DDR3LP devices.
+ MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and
+ 2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time
+ increases by 1 clock.
+
+ IFC/Local Bus
+ NAND flash: 8-bit, async or sync, up to 2GB.
+ NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB
+ NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
+ - NOR devices support 16 virtual banks
+ GASIC: Minimal target within Qixis FPGA
+ PromJET rapid memory download support
+ Address demultiplexing handled within FPGA.
+ - Flexible demux allows 8 or 16 bit evaluation.
+ IFC Debug/Development card
+ - Support for 32-bit devices
+ Ethernet
+ Support two on-board RGMII 10/100/1G ethernet ports.
+ SGMII and XAUI support via SERDES block (see above).
+ 1588 support via Symmetricom board.
+ QIXIS System Logic FPGA
+ Manages system power and reset sequencing
+ Manages DUT, board, clock, etc. configuration for dynamic shmoo
+ Collects V-I-T data in background for code/power profiling.
+ Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion)
+ General fault monitoring and logging
+ Runs from ATX “hot” power rails allowing operation while system is off.
+ Clocks
+ System and DDR clock (SYSCLK, “DDRCLK”)
+ - Switch selectable to one of 16 common settings in the interval 33MHz-166MHz.
+ - Software selectable in 1MHz increments from 1-200MHz.
+ SERDES clocks
+ - Provides clocks to all SerDes blocks and slots
+ - 100, 125 and 156.25 MHz
+ Power Supplies
+ Dedicated regulators for VDD
+ - Adjustable from (0.7V to 1.3V at 80A
+ - Regulators can be controlled by VID and/or software
+ Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A
+ - VTT/MVREF automatically track operating voltage
+ Dedicated regulators/filters for AVDD supplies
+ Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, POVDD, etc.
+ USB
+ Supports two USB 2.0 ports with integrated PHYs
+ - One type A, one type micro-AB with 1.0A power per port.
+ Other IO
+ eSDHC/MMC
+ - SDHC card slot
+ eSPI port
+ - High-speed serial flash
+ Two Serial port
+ Four I2C ports
+ XFI
+ XFI is supported on T4QDS-XFI board which removed slot3 and routed
+ four Lanes A/B/C/D to a SFP+ cages, which to house fiber cable or
+ direct attach cable(copper), the copper cable is used to emulate
+ 10GBASE-KR scenario.
+ So, for XFI usage, there are two scenarios, one will use fiber cable,
+ another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
+ introduced to indicate a XFI port will use copper cable, and U-boot
+ will fixup the dtb accordingly.
+ It's used as: fsl_10gkr_copper:<10g_mac_name>
+ The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2, they
+ do not have to be coexist in hwconfig. If a MAC is listed in the env
+ "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
+ will be used by default.
+ for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2" in
+ hwconfig, then both four XFI ports will use copper cable.
+ set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
+ XFI ports will use copper cable, the other two XFI ports will use fiber
+ cable.
+
+Memory map
+----------
+The addresses in brackets are physical addresses.
+
+0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB)
+0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory
+0x0_f000_0000 (0xf_0000_0000) - 0x0_f1ff_ffff 32MB DCSR (includes trace buffers)
+0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan
+0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan
+0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO
+0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash
+0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff 16MB CCSR
+0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff 4KB QIXIS
+0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores
+
+The physical address of the last (boot page translation) varies with the actual DDR size.
+
+Voltage ID and VDD override
+--------------------
+T4240 has a VID feature. U-boot reads the VID efuses and adjust the voltage
+accordingly. The voltage can also be override by command vdd_override. The
+syntax is
+
+vdd_override <voltage in mV>, eg. 1050 is for 1.050v.
+
+Upon success, the actual voltage will be read back. The value is checked
+for safety and any invalid value will not adjust the voltage.
+
+Another way to override VDD is to use environmental variable, in case of using
+command is too late for some debugging. The syntax is
+
+setenv t4240qds_vdd_mv <voltage in mV>
+saveenv
+reset
+
+The override voltage takes effect when booting.
+
+Note: voltage adjustment needs to be done step by step. Changing voltage too
+rapidly may cause current surge. The voltage stepping is done by software.
+Users can set the final voltage directly.
+
+2-stage NAND/SD boot loader
+-------------------------------
+PBL initializes the internal SRAM and copy SPL(160K) in SRAM.
+SPL further initialise DDR using SPD and environment variables
+and copy u-boot(768 KB) from NAND/SD device to DDR.
+Finally SPL transers control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area | Address |
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB) |
+-------------------------------------------------
+|GD, BD | 0xFFFC8000 (4KB) |
+-------------------------------------------------
+|ENV | 0xFFFC9000 (8KB) |
+-------------------------------------------------
+|HEAP | 0xFFFCB000 (50KB) |
+-------------------------------------------------
+|STACK | 0xFFFD8000 (22KB) |
+-------------------------------------------------
+|U-boot SPL | 0xFFFD8000 (160KB) |
+-------------------------------------------------
+
+NAND Flash memory Map on T4QDS
+--------------------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot img 1MB
+0x140000 0x15FFFF u-boot env 128KB
+0x160000 0x17FFFF FMAN Ucode 128KB
+
+Micro SD Card memory Map on T4QDS
+----------------------------------------------------
+Block #blocks Definition Size
+0x008 2048 u-boot img 1MB
+0x800 0016 u-boot env 8KB
+0x820 0128 FMAN ucode 64KB
+
+Switch Settings: (ON is 1, OFF is 0)
+===============
+NAND boot SW setting:
+SW1[1:8] = 10000010
+SW2[1.1] = 0
+SW6[1:4] = 1001
+
+SD boot SW setting:
+SW1[1:8] = 00100000
+SW2[1.1] = 0
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index 6210e46..9b416b1 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -23,6 +23,7 @@
#include <phy.h>
#include <asm/fsl_dtsec.h>
#include <asm/fsl_serdes.h>
+#include <hwconfig.h>
#include "../common/qixis.h"
#include "../common/fman.h"
@@ -173,6 +174,10 @@ void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
enum fm_port port, int offset)
{
int interface = fm_info_get_enet_if(port);
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+ prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
if (interface == PHY_INTERFACE_MODE_SGMII ||
interface == PHY_INTERFACE_MODE_QSGMII) {
@@ -262,6 +267,76 @@ void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
default:
break;
}
+ } else if (interface == PHY_INTERFACE_MODE_XGMII &&
+ ((prtcl2 == 55) || (prtcl2 == 57))) {
+ /*
+ * if the 10G is XFI, check hwconfig to see what is the
+ * media type, there are two types, fiber or copper,
+ * fix the dtb accordingly.
+ */
+ int media_type = 0;
+ struct fixed_link f_link;
+ char lane_mode[20] = {"10GBASE-KR"};
+ char buf[32] = "serdes-2,";
+ int off;
+
+ switch (port) {
+ case FM1_10GEC1:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
+ media_type = 1;
+ fdt_set_phy_handle(blob, prop, pa,
+ "phy_xfi1");
+ sprintf(buf, "%s%s%s", buf, "lane-a,",
+ (char *)lane_mode);
+ }
+ break;
+ case FM1_10GEC2:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
+ media_type = 1;
+ fdt_set_phy_handle(blob, prop, pa,
+ "phy_xfi2");
+ sprintf(buf, "%s%s%s", buf, "lane-b,",
+ (char *)lane_mode);
+ }
+ break;
+ case FM2_10GEC1:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) {
+ media_type = 1;
+ fdt_set_phy_handle(blob, prop, pa,
+ "phy_xfi3");
+ sprintf(buf, "%s%s%s", buf, "lane-d,",
+ (char *)lane_mode);
+ }
+ break;
+ case FM2_10GEC2:
+ if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) {
+ media_type = 1;
+ fdt_set_phy_handle(blob, prop, pa,
+ "phy_xfi4");
+ sprintf(buf, "%s%s%s", buf, "lane-c,",
+ (char *)lane_mode);
+ }
+ break;
+ default:
+ return;
+ }
+
+ if (!media_type) {
+ /* fixed-link is used for XFI fiber cable */
+ fdt_delprop(blob, offset, "phy-handle");
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 10000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ fdt_setprop(blob, offset, "fixed-link", &f_link,
+ sizeof(f_link));
+ } else {
+ /* set property for copper cable */
+ off = fdt_node_offset_by_compat_reg(blob,
+ "fsl,fman-memac-mdio", pa + 0x1000);
+ fdt_setprop_string(blob, off, "lane-instance", buf);
+ }
}
}
@@ -295,8 +370,23 @@ void fdt_fixup_board_enet(void *fdt)
break;
case PHY_INTERFACE_MODE_XGMII:
/* check if it's XFI interface for 10g */
- if ((prtcl2 == 56) || (prtcl2 == 57)) {
- fdt_status_okay_by_alias(fdt, "emi2_xfislot3");
+ if ((prtcl2 == 55) || (prtcl2 == 57)) {
+ if (i == FM1_10GEC1 && hwconfig_sub(
+ "fsl_10gkr_copper", "fm1_10g1"))
+ fdt_status_okay_by_alias(
+ fdt, "xfi_pcs_mdio1");
+ if (i == FM1_10GEC2 && hwconfig_sub(
+ "fsl_10gkr_copper", "fm1_10g2"))
+ fdt_status_okay_by_alias(
+ fdt, "xfi_pcs_mdio2");
+ if (i == FM2_10GEC1 && hwconfig_sub(
+ "fsl_10gkr_copper", "fm2_10g1"))
+ fdt_status_okay_by_alias(
+ fdt, "xfi_pcs_mdio3");
+ if (i == FM2_10GEC2 && hwconfig_sub(
+ "fsl_10gkr_copper", "fm2_10g2"))
+ fdt_status_okay_by_alias(
+ fdt, "xfi_pcs_mdio4");
break;
}
switch (i) {
@@ -460,7 +550,7 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
- if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
+ if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC9,
slot_qsgmii_phyaddr[1][3]);
fm_info_set_phy_address(FM1_DTSEC10,
@@ -475,7 +565,7 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
- if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
+ if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC9,
slot_qsgmii_phyaddr[1][2]);
fm_info_set_phy_address(FM1_DTSEC10,
@@ -490,7 +580,7 @@ int board_eth_init(bd_t *bis)
case 48:
fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
- if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
+ if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC10,
slot_qsgmii_phyaddr[1][2]);
fm_info_set_phy_address(FM1_DTSEC9,
@@ -567,13 +657,18 @@ int board_eth_init(bd_t *bis)
idx = i - FM1_10GEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
- lane = serdes_get_first_lane(FSL_SRDS_1,
+ if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
+ /* A fake PHY address to make U-boot happy */
+ fm_info_set_phy_address(i, i);
+ } else {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
XAUI_FM1_MAC9 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot_fsm1[lane];
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot_fsm1[lane];
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+ }
mdio_mux[i] = EMI2;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
@@ -666,7 +761,7 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
- case 56:
+ case 55:
case 57:
/* XFI in Slot3, SGMII in Slot4 */
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
@@ -743,13 +838,18 @@ int board_eth_init(bd_t *bis)
idx = i - FM2_10GEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
- lane = serdes_get_first_lane(FSL_SRDS_2,
+ if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) {
+ /* A fake PHY address to make U-boot happy */
+ fm_info_set_phy_address(i, i);
+ } else {
+ lane = serdes_get_first_lane(FSL_SRDS_2,
XAUI_FM2_MAC9 + idx);
- if (lane < 0)
- break;
- slot = lane_to_slot_fsm2[lane];
- if (QIXIS_READ(present2) & (1 << (slot - 1)))
- fm_disable_port(i);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot_fsm2[lane];
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+ }
mdio_mux[i] = EMI2;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c
index e90186e..3edc915 100644
--- a/board/gateworks/gw_ventana/eeprom.c
+++ b/board/gateworks/gw_ventana/eeprom.c
@@ -6,7 +6,10 @@
*/
#include <common.h>
+#include <errno.h>
#include <i2c.h>
+#include <malloc.h>
+#include <asm/bitops.h>
#include "gsc.h"
#include "ventana_eeprom.h"
@@ -38,14 +41,12 @@ read_eeprom(int bus, struct ventana_board_info *info)
/* read eeprom config section */
if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) {
puts("EEPROM: Failed to read EEPROM\n");
- info->model[0] = 0;
return GW_UNKNOWN;
}
/* sanity checks */
if (info->model[0] != 'G' || info->model[1] != 'W') {
puts("EEPROM: Invalid Model in EEPROM\n");
- info->model[0] = 0;
return GW_UNKNOWN;
}
@@ -55,7 +56,6 @@ read_eeprom(int bus, struct ventana_board_info *info)
if ((info->chksum[0] != chksum>>8) ||
(info->chksum[1] != (chksum&0xff))) {
puts("EEPROM: Failed EEPROM checksum\n");
- info->model[0] = 0;
return GW_UNKNOWN;
}
@@ -87,3 +87,165 @@ read_eeprom(int bus, struct ventana_board_info *info)
}
return type;
}
+
+/* list of config bits that the bootloader will remove from dtb if not set */
+struct ventana_eeprom_config econfig[] = {
+ { "eth0", "ethernet0", EECONFIG_ETH0 },
+ { "eth1", "ethernet1", EECONFIG_ETH1 },
+ { "sata", "ahci0", EECONFIG_SATA },
+ { "pcie", NULL, EECONFIG_PCIE},
+ { "lvds0", NULL, EECONFIG_LVDS0 },
+ { "lvds1", NULL, EECONFIG_LVDS1 },
+ { "usb0", NULL, EECONFIG_USB0 },
+ { "usb1", NULL, EECONFIG_USB1 },
+ { "mmc0", NULL, EECONFIG_SD0 },
+ { "mmc1", NULL, EECONFIG_SD1 },
+ { "mmc2", NULL, EECONFIG_SD2 },
+ { "mmc3", NULL, EECONFIG_SD3 },
+ { "uart0", NULL, EECONFIG_UART0 },
+ { "uart1", NULL, EECONFIG_UART1 },
+ { "uart2", NULL, EECONFIG_UART2 },
+ { "uart3", NULL, EECONFIG_UART3 },
+ { "uart4", NULL, EECONFIG_UART4 },
+ { "ipu0", NULL, EECONFIG_IPU0 },
+ { "ipu1", NULL, EECONFIG_IPU1 },
+ { "can0", NULL, EECONFIG_FLEXCAN },
+ { "i2c0", NULL, EECONFIG_I2C0 },
+ { "i2c1", NULL, EECONFIG_I2C1 },
+ { "i2c2", NULL, EECONFIG_I2C2 },
+ { "vpu", NULL, EECONFIG_VPU },
+ { "csi0", NULL, EECONFIG_CSI0 },
+ { "csi1", NULL, EECONFIG_CSI1 },
+ { "spi0", NULL, EECONFIG_ESPCI0 },
+ { "spi1", NULL, EECONFIG_ESPCI1 },
+ { "spi2", NULL, EECONFIG_ESPCI2 },
+ { "spi3", NULL, EECONFIG_ESPCI3 },
+ { "spi4", NULL, EECONFIG_ESPCI4 },
+ { "spi5", NULL, EECONFIG_ESPCI5 },
+ { "gps", "pps", EECONFIG_GPS },
+ { "hdmi_in", NULL, EECONFIG_HDMI_IN },
+ { "hdmi_out", NULL, EECONFIG_HDMI_OUT },
+ { "cvbs_in", NULL, EECONFIG_VID_IN },
+ { "cvbs_out", NULL, EECONFIG_VID_OUT },
+ { "nand", NULL, EECONFIG_NAND },
+ { /* Sentinel */ }
+};
+
+#ifdef CONFIG_CMD_EECONFIG
+static struct ventana_eeprom_config *get_config(const char *name)
+{
+ struct ventana_eeprom_config *cfg = econfig;
+
+ while (cfg->name) {
+ if (0 == strcmp(name, cfg->name))
+ return cfg;
+ cfg++;
+ }
+ return NULL;
+}
+
+static u8 econfig_bytes[sizeof(ventana_info.config)];
+static int econfig_init = -1;
+
+int do_econfig(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct ventana_eeprom_config *cfg;
+ struct ventana_board_info *info = &ventana_info;
+ int i;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ /* initialize */
+ if (econfig_init != 1) {
+ memcpy(econfig_bytes, info->config, sizeof(econfig_bytes));
+ econfig_init = 1;
+ }
+
+ /* list configs */
+ if ((strncmp(argv[1], "list", 4) == 0)) {
+ cfg = econfig;
+ while (cfg->name) {
+ printf("%s: %d\n", cfg->name,
+ test_bit(cfg->bit, econfig_bytes) ? 1 : 0);
+ cfg++;
+ }
+ }
+
+ /* save */
+ else if ((strncmp(argv[1], "save", 4) == 0)) {
+ unsigned char *buf = (unsigned char *)info;
+ int chksum;
+
+ /* calculate new checksum */
+ memcpy(info->config, econfig_bytes, sizeof(econfig_bytes));
+ for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
+ chksum += buf[i];
+ debug("old chksum:0x%04x\n",
+ (info->chksum[0] << 8) | info->chksum[1]);
+ debug("new chksum:0x%04x\n", chksum);
+ info->chksum[0] = chksum >> 8;
+ info->chksum[1] = chksum & 0xff;
+
+ /* write new config data */
+ if (gsc_i2c_write(GSC_EEPROM_ADDR, info->config - (u8 *)info,
+ 1, econfig_bytes, sizeof(econfig_bytes))) {
+ printf("EEPROM: Failed updating config\n");
+ return CMD_RET_FAILURE;
+ }
+
+ /* write new config data */
+ if (gsc_i2c_write(GSC_EEPROM_ADDR, info->chksum - (u8 *)info,
+ 1, info->chksum, 2)) {
+ printf("EEPROM: Failed updating checksum\n");
+ return CMD_RET_FAILURE;
+ }
+
+ printf("Config saved to EEPROM\n");
+ }
+
+ /* get config */
+ else if (argc == 2) {
+ cfg = get_config(argv[1]);
+ if (cfg) {
+ printf("%s: %d\n", cfg->name,
+ test_bit(cfg->bit, econfig_bytes) ? 1 : 0);
+ } else {
+ printf("invalid config: %s\n", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+ }
+
+ /* set config */
+ else if (argc == 3) {
+ cfg = get_config(argv[1]);
+ if (cfg) {
+ if (simple_strtol(argv[2], NULL, 10)) {
+ test_and_set_bit(cfg->bit, econfig_bytes);
+ printf("Enabled %s\n", cfg->name);
+ } else {
+ test_and_clear_bit(cfg->bit, econfig_bytes);
+ printf("Disabled %s\n", cfg->name);
+ }
+ } else {
+ printf("invalid config: %s\n", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+ }
+
+ else
+ return CMD_RET_USAGE;
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ econfig, 3, 0, do_econfig,
+ "EEPROM configuration",
+ "list - list config\n"
+ "save - save config to EEPROM\n"
+ "<name> - get config 'name'\n"
+ "<name> [0|1] - set config 'name' to value\n"
+);
+
+#endif /* CONFIG_CMD_EECONFIG */
diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c
index 37966ab..1cf38d4 100644
--- a/board/gateworks/gw_ventana/gsc.c
+++ b/board/gateworks/gw_ventana/gsc.c
@@ -57,7 +57,7 @@ int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
break;
mdelay(10);
}
- mdelay(1);
+ mdelay(100);
return ret;
}
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 9d2651f..a222921 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -50,10 +50,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define GP_RS232_EN IMX_GPIO_NR(2, 11)
#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
-/* I2C bus numbers */
-#define I2C_GSC 0
-#define I2C_PMIC 1
-
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@@ -78,11 +74,18 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
+
+
/*
* EEPROM board info struct populated by read_eeprom so that we only have to
* read it once.
*/
-static struct ventana_board_info ventana_info;
+struct ventana_board_info ventana_info;
int board_type;
@@ -187,7 +190,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
/* CD */
- IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
};
/* ENET */
@@ -211,7 +214,7 @@ iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* PHY nRST */
- IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
};
/* NAND */
@@ -281,10 +284,10 @@ static void setup_iomux_uart(void)
#ifdef CONFIG_USB_EHCI_MX6
iomux_v3_cfg_t const usb_pads[] = {
- IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL)),
- IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL)),
+ IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
+ IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
/* OTG PWR */
- IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
};
int board_ehci_hcd_init(int port)
@@ -296,15 +299,13 @@ int board_ehci_hcd_init(int port)
/* Reset USB HUB (present on GW54xx/GW53xx) */
switch (info->model[3]) {
case '3': /* GW53xx */
- SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 |
- MUX_PAD_CTRL(NO_PAD_CTRL));
+ SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
mdelay(2);
gpio_set_value(IMX_GPIO_NR(1, 9), 1);
break;
case '4': /* GW54xx */
- SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 |
- MUX_PAD_CTRL(NO_PAD_CTRL));
+ SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
mdelay(2);
gpio_set_value(IMX_GPIO_NR(1, 16), 1);
@@ -426,7 +427,7 @@ static void enable_lvds(struct display_info_t const *dev)
writel(reg, &iomux->gpr[2]);
/* Enable Backlight */
- SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL));
+ SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
}
@@ -523,7 +524,7 @@ static void setup_display(void)
writel(reg, &iomux->gpr[3]);
/* Backlight CABEN on LVDS connector */
- SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL));
+ SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
}
#endif /* CONFIG_VIDEO_IPUV3 */
@@ -535,118 +536,128 @@ static void setup_display(void)
/* common to add baseboards */
static iomux_v3_cfg_t const gw_gpio_pads[] = {
/* MSATA_EN */
- IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
/* RS232_EN# */
- IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
};
/* prototype */
static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
/* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* RS485_EN */
- IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
- IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
- IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
/* VID_EN */
- IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
/* DIOI2C_DIS# */
- IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
/* PCICK_SSON */
- IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
/* PCI_RST# */
- IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
/* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
- IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
- IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
/* GPS_SHDN */
- IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
/* VID_PWR */
- IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
/* PCI_RST# */
- IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
/* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
- IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
- IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
/* MX6_LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* GPS_SHDN */
- IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
/* USBOTG_SEL */
- IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
/* VID_PWR */
- IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
/* PCI_RST# */
- IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
/* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
- IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
- IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
+ /* DIOI2C_DIS# */
+ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
/* MX6_LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* GPS_SHDN */
- IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
/* VID_EN */
- IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
/* PCI_RST# */
- IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
};
static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
/* PANLEDG# */
- IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
/* PANLEDR# */
- IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
/* MX6_LOCLED# */
- IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
/* MIPI_DIO */
- IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
/* RS485_EN */
- IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
/* IOEXP_PWREN# */
- IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
/* IOEXP_IRQ# */
- IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
- /* DIOI2C_DIS# */
- IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
/* DIOI2C_DIS# */
- IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
/* PCICK_SSON */
- IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
/* PCI_RST# */
- IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
+ /* VID_EN */
+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
+ /* PCIESKT_WDIS# */
+ IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
};
/*
@@ -677,6 +688,7 @@ struct ventana {
int dioi2c_en;
int pcie_sson;
int usb_sel;
+ int wdis;
};
struct ventana gpio_cfg[] = {
@@ -762,6 +774,7 @@ struct ventana gpio_cfg[] = {
.mezz_irq = IMX_GPIO_NR(2, 18),
.gps_shdn = IMX_GPIO_NR(1, 2),
.vidin_en = IMX_GPIO_NR(5, 20),
+ .wdis = IMX_GPIO_NR(7, 12),
},
/* GW52xx */
@@ -805,6 +818,7 @@ struct ventana gpio_cfg[] = {
.gps_shdn = IMX_GPIO_NR(1, 27),
.vidin_en = IMX_GPIO_NR(3, 31),
.usb_sel = IMX_GPIO_NR(1, 2),
+ .wdis = IMX_GPIO_NR(7, 12),
},
/* GW53xx */
@@ -847,6 +861,7 @@ struct ventana gpio_cfg[] = {
.mezz_irq = IMX_GPIO_NR(2, 18),
.gps_shdn = IMX_GPIO_NR(1, 27),
.vidin_en = IMX_GPIO_NR(3, 31),
+ .wdis = IMX_GPIO_NR(7, 12),
},
/* GW54xx */
@@ -891,6 +906,7 @@ struct ventana gpio_cfg[] = {
.vidin_en = IMX_GPIO_NR(3, 31),
.dioi2c_en = IMX_GPIO_NR(4, 5),
.pcie_sson = IMX_GPIO_NR(1, 20),
+ .wdis = IMX_GPIO_NR(5, 17),
},
};
@@ -902,8 +918,8 @@ int power_init_board(void)
/* configure PFUZE100 PMIC */
if (board_type == GW54xx || board_type == GW54proto) {
- power_pfuze100_init(I2C_PMIC);
- p = pmic_get("PFUZE100_PMIC");
+ power_pfuze100_init(CONFIG_I2C_PMIC);
+ p = pmic_get("PFUZE100");
if (p && !pmic_probe(p)) {
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
@@ -924,7 +940,7 @@ int power_init_board(void)
/* configure LTC3676 PMIC */
else {
- power_ltc3676_init(I2C_PMIC);
+ power_ltc3676_init(CONFIG_I2C_PMIC);
p = pmic_get("LTC3676_PMIC");
if (p && !pmic_probe(p)) {
puts("PMIC: LTC3676\n");
@@ -975,12 +991,10 @@ static void setup_board_gpio(int board)
gpio_direction_output(GP_MSATA_SEL, 0);
}
- /*
- * assert PCI_RST# (released by OS when clock is valid)
- * TODO: figure out why leaving this de-asserted from PCI scan on boot
- * causes linux pcie driver to hang during enumeration
- */
+#if !defined(CONFIG_CMD_PCI)
+ /* assert PCI_RST# (released by OS when clock is valid) */
gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
+#endif
/* turn off (active-high) user LED's */
for (i = 0; i < 4; i++) {
@@ -1016,21 +1030,27 @@ static void setup_board_gpio(int board)
if (gpio_cfg[board].usb_sel)
gpio_direction_output(gpio_cfg[board].usb_sel, 0);
+ /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
+ if (gpio_cfg[board].wdis)
+ gpio_direction_output(gpio_cfg[board].wdis, 1);
+
/*
* Configure DIO pinmux/padctl registers
* see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
*/
for (i = 0; i < 4; i++) {
struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
- unsigned ctrl = DIO_PAD_CTRL;
+ iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
sprintf(arg, "dio%d", i);
if (!hwconfig(arg))
continue;
s = hwconfig_subarg(arg, "padctrl", &len);
- if (s)
- ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff;
+ if (s) {
+ ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
+ & 0x1ffff) | MUX_MODE_SION;
+ }
if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
if (!quiet) {
printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
@@ -1039,7 +1059,7 @@ static void setup_board_gpio(int board)
cfg->gpio_param);
}
imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
- MUX_PAD_CTRL(ctrl));
+ ctrl);
gpio_direction_input(cfg->gpio_param);
} else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
cfg->pwm_padmux) {
@@ -1122,8 +1142,7 @@ int dram_init(void)
int board_init(void)
{
- struct iomuxc_base_regs *const iomuxc_regs
- = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
clrsetbits_le32(&iomuxc_regs->gpr[1],
IOMUXC_GPR1_OTG_ID_MASK,
@@ -1152,7 +1171,7 @@ int board_init(void)
setup_sata();
#endif
/* read Gateworks EEPROM into global struct (used later) */
- board_type = read_eeprom(I2C_GSC, &ventana_info);
+ board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
/* board-specifc GPIO iomux */
SETUP_IOMUX_PADS(gw_gpio_pads);
@@ -1200,7 +1219,7 @@ int checkboard(void)
return 0;
/* Display GSC firmware revision/CRC/status */
- i2c_set_bus_num(I2C_GSC);
+ i2c_set_bus_num(CONFIG_I2C_GSC);
if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
printf("GSC: v%d", buf[0]);
if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
@@ -1264,6 +1283,10 @@ int misc_init_r(void)
else if (is_cpu_type(MXC_CPU_MX6DL) ||
is_cpu_type(MXC_CPU_MX6SOLO))
cputype = "imx6dl";
+ if (8 << (ventana_info.nand_flash_size-1) >= 2048)
+ setenv("flash_layout", "large");
+ else
+ setenv("flash_layout", "normal");
memset(str, 0, sizeof(str));
for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
str[i] = tolower(info->model[i]);
@@ -1326,7 +1349,7 @@ int misc_init_r(void)
*
* Disable the boot watchdog and display/clear the timeout flag if set
*/
- i2c_set_bus_num(I2C_GSC);
+ i2c_set_bus_num(CONFIG_I2C_GSC);
if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
reg |= (1 << GSC_SC_CTRL1_WDDIS);
if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
@@ -1336,7 +1359,7 @@ int misc_init_r(void)
}
if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1)) {
if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
- puts("GSC boot watchdog timeout detected");
+ puts("GSC boot watchdog timeout detected\n");
reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1);
}
@@ -1347,74 +1370,6 @@ int misc_init_r(void)
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-/* FDT aliases associated with EEPROM config bits */
-const char *fdt_aliases[] = {
- "ethernet0",
- "ethernet1",
- "hdmi_out",
- "ahci0",
- "pcie",
- "ssi0",
- "ssi1",
- "lcd0",
- "lvds0",
- "lvds1",
- "usb0",
- "usb1",
- "mmc0",
- "mmc1",
- "mmc2",
- "mmc3",
- "uart0",
- "uart1",
- "uart2",
- "uart3",
- "uart4",
- "ipu0",
- "ipu1",
- "can0",
- "mipi_dsi",
- "mipi_csi",
- "tzasc0",
- "tzasc1",
- "i2c0",
- "i2c1",
- "i2c2",
- "vpu",
- "csi0",
- "csi1",
- "caam",
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- "spi0",
- "spi1",
- "spi2",
- "spi3",
- "spi4",
- "spi5",
- NULL,
- NULL,
- "pps",
- NULL,
- NULL,
- NULL,
- "hdmi_in",
- "cvbs_out",
- "cvbs_in",
- "nand",
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL,
-};
-
/*
* called prior to booting kernel or by 'fdt boardsetup' command
*
@@ -1426,8 +1381,8 @@ const char *fdt_aliases[] = {
*/
void ft_board_setup(void *blob, bd_t *bd)
{
- int bit;
struct ventana_board_info *info = &ventana_info;
+ struct ventana_eeprom_config *cfg;
struct node_info nodes[] = {
{ "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
{ "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
@@ -1462,9 +1417,17 @@ void ft_board_setup(void *blob, bd_t *bd)
* remove nodes by alias path if EEPROM config tells us the
* peripheral is not loaded on the board.
*/
- for (bit = 0; bit < 64; bit++) {
- if (!test_bit(bit, info->config))
- fdt_del_node_and_alias(blob, fdt_aliases[bit]);
+ if (getenv("fdt_noconfig")) {
+ puts(" Skiping periperhal config (fdt_noconfig defined)\n");
+ return;
+ }
+ cfg = econfig;
+ while (cfg->name) {
+ if (!test_bit(cfg->bit, info->config)) {
+ fdt_del_node_and_alias(blob, cfg->dtalias ?
+ cfg->dtalias : cfg->name);
+ }
+ cfg++;
}
}
#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h
index 5b065be..d64b910 100644
--- a/board/gateworks/gw_ventana/ventana_eeprom.h
+++ b/board/gateworks/gw_ventana/ventana_eeprom.h
@@ -110,8 +110,19 @@ enum {
GW53xx,
GW54xx,
GW_UNKNOWN,
+ GW_BADCRC,
};
+/* config items */
+struct ventana_eeprom_config {
+ const char *name; /* name of item */
+ const char *dtalias; /* name of dt node to remove if not set */
+ int bit; /* bit within config */
+};
+
+extern struct ventana_eeprom_config econfig[];
+extern struct ventana_board_info ventana_info;
+
int read_eeprom(int bus, struct ventana_board_info *);
#endif
diff --git a/board/gen860t/Kconfig b/board/gen860t/Kconfig
deleted file mode 100644
index 438f7cc..0000000
--- a/board/gen860t/Kconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-if TARGET_GEN860T
-
-config SYS_BOARD
- string
- default "gen860t"
-
-config SYS_CONFIG_NAME
- string
- default "GEN860T"
-
-endif
diff --git a/board/gen860t/MAINTAINERS b/board/gen860t/MAINTAINERS
deleted file mode 100644
index c5d3da3..0000000
--- a/board/gen860t/MAINTAINERS
+++ /dev/null
@@ -1,7 +0,0 @@
-GEN860T BOARD
-M: Keith Outwater <Keith_Outwater@mvis.com>
-S: Orphan (since 2014-06)
-F: board/gen860t/
-F: include/configs/GEN860T.h
-F: configs/GEN860T_defconfig
-F: configs/GEN860T_SC_defconfig
diff --git a/board/gen860t/Makefile b/board/gen860t/Makefile
deleted file mode 100644
index 86ae5e8..0000000
--- a/board/gen860t/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = gen860t.o flash.o beeper.o fpga.o ioport.o
diff --git a/board/gen860t/README b/board/gen860t/README
deleted file mode 100644
index 3ef8ae1..0000000
--- a/board/gen860t/README
+++ /dev/null
@@ -1,131 +0,0 @@
-This directory contains board specific code for a generic MPC860T based
-embedded computer, called 'GEN860T'. The design is generic in the sense that
-common, readily available components are used and that the architecture of the
-system is relatively straightforward:
-
- One eight bit wide boot (FLASH) memory
- 32 bit main memory using SDRAM
- DOC 2000+
- Ethernet PHY
- Some I2C peripheral devices: Atmel AT24C256 EEPROM, Maxim DS1337 RTC.
- Some other miscellaneous peripherals
-
-NOTE: There are references to a XIlinx FPGA and Mil-Std 1553 databus in this
-port. I guess the computer is not as generic as I first said 8) However,
-these extras can be safely ignored.
-
-Given the GEN860T files, it should be pretty easy to reverse engineer the
-hardware configuration, if that's useful to you. Hopefully, this code will
-be useful to someone as a basis for a port to a new system or as a head start
-on a custom design. If you end up using any of this, I would appreciate
-hearing from you, especially if you discover bugs or find ways to improve the
-quality of this U-Boot port.
-
-Here are the salient features of the system:
-Clock : 33.3 Mhz oscillator
-Processor core frequency : 66.6 Mhz if in 1:2:1 mode; can also run 1:1
-Bus frequency : 33.3 Mhz
-
-Main memory:
- Type : SDRAM
- Width : 32 bits
- Size : 64 mibibytes
- Chip : Two Micron MT48LC16M16A2TG-7E
- CS : MPC860T CS1*/UPMA
- UPMA CONNECTIONS:
- SDRAM A10 : GPLA0*
- SDRAM CAS* : GPLA2*
- SDRAM WE* : GPLA3*
- SDRAM RAS* : GPLA4*
-
-Boot memory:
- Type : FLASH
- Width : 8 bits
- Size : 16 mibibytes
- Chip : One Intel 28F128J3A (StrataFlash)
- CS : MPC860T CS0*/GPCM (this is the "boot" chip select)
-
-EEPROM memory:
- Type : Serial I2C EEPROM
- Width : 8 bits
- Size : 32 kibibytes
- Chip : One Atmel AT25C256
- CS : 0x50 (external I2C address pins on device are tied to GND)
-
-Filesystem memory:
- Type : NAND FLASH (Toshiba)
- Width : 8 bits (i.e. interface to DOC is 8 bits)
- Size : 32 mibibytes
- Chip : One DiskOnCHip Millenium Plus (DOC 2000+)
- CS : MPC860T CS2*/GPCM
-
-Network support:
- MAC : MPC86OT FEC (Fast Ethernet Controller)
- PHY : Intel LXT971A
- MII Addr: 0x0 (hardwired on the board)
- MII IRQ :
-
-Console:
- RS-232 on SMC1 (Maxim MAX3232 LVCMOS-RS232 level shifter)
-
-Real Time Clock:
- Type : Low power, I2C interface
- Chip : Maxim DS1337
- CS : Address 0x68 on I2C bus
-
- The MPC860T's internal RTC has a defect in Mask rev D that increases
- the current drain on the KAPWR line to 10 mA. Since this is an
- unreasonable amount of current draw for a RTC, and Motorola does not
- plan to fix this in future mask revisions, a serial (I2C) RTC that
- works has been included instead. NOTE that the DS1337 can be
- configured to output a 32768 Hz clock while the main power is on.
- This clock output has been routed to the MPC860T's EXTAL pin to allow
- the internal RTC to be used. NOTE also that due to yet another
- defect in the rev D mask, the RTC does not operate reliably when the
- internal RTC divisor is set to use a 32768 Hz reference. So just use
- the I2C RTC.
-
-Miscellaneous:
- Xilinx Virtex FPGA on CS3*/GPCM.
- Virtex FPGA slave SelectMap interface on cs4*/UPMB.
- Mil-Std 1553 databus interface on CS5*/GPCM.
- Audio sounder (beeper) with digital volume control connected to SPKROUT.
-
-SC variant:
- A reduced-feature version of the GEN860T port is also supported: GEN860T_SC.
- The 'SC' variant only provides support for the Virtex FPGA, SDRAM main
- memory, EEPROM and flash memory. The system clock frequency is reduced
- to 24 MHz.
-
-Issues:
- The DOC 2000+ returns 0x40 as its device ID when probed using the method
- desxribed in the DOC datasheet. Unfortunately, the U-Boot DOC driver
- does not recognize this device. As of this writing, it seems that MTD
- does not support the DOC 2000+ either.
-
-Status:
- Everything appears to work except DOC support. As of this writing,
- David Woodhouse has stated on the MTD mailing list that he has no
- knowledge of the DOC Millineum Plus and therfore there is no support
- in MTD for this device. I wish I had known this sooner :(
-
-The GEN860T board specific files and configuration is based on the work
-of others who have contributed to U-Boot. The copyright and license notices
-of these authors have been retained wherever their code has been reused.
-All new code to support the GEN860T board is:
-
- (C) Copyright 2001-2003
- Keith Outwater (keith_outwater@mvis.com)
-
-and the following license applies:
-
-SPDX-License-Identifier: GPL-2.0+
-
-Thanks to Wolfgang Denk for a great software package and to everyone
-who contributed to its development.
-
-Keith Outwater
-Sr. Staff Engineer
-Microvision, Inc.
-<keith_outwater@mvis.com>
-<outwater@eskimo.com>
diff --git a/board/gen860t/beeper.c b/board/gen860t/beeper.c
deleted file mode 100644
index 0bebca9..0000000
--- a/board/gen860t/beeper.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * (C) Copyright 2002
- * Keith Outwater, keith_outwater@mvis.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <asm/8xx_immap.h>
-#include <linux/ctype.h>
-
-/*
- * Basic beeper support for the GEN860T board. The GEN860T includes
- * an audio sounder driven by a Phillips TDA8551 amplifier. The
- * TDA8551 features a digital volume control which uses a "trinary"
- * input (high/high-Z/low) to set volume. The 860's SPKROUT pin
- * drives the amplifier input.
- */
-
-/*
- * Initialize beeper-related hardware. Initialize timer 1 for use with
- * the beeper. Use 66 MHz internal clock with prescale of 33 to get
- * 1 uS period per count.
- * FIXME: we should really compute the prescale based on the reported
- * core clock frequency.
- */
-void init_beeper (void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_RST1 | TGCR_STP1;
- immap->im_cpmtimer.cpmt_tmr1 = ((33 << TMR_PS_SHIFT) & TMR_PS_MSK)
- | TMR_OM | TMR_FRR | TMR_ICLK_IN_GEN;
- immap->im_cpmtimer.cpmt_tcn1 = 0;
- immap->im_cpmtimer.cpmt_ter1 = 0xffff;
- immap->im_cpmtimer.cpmt_tgcr |= TGCR_RST1;
-}
-
-/*
- * Set beeper frequency. Max allowed frequency is 2.5 KHz. This limit
- * is mostly arbitrary, but the beeper isn't really much good beyond this
- * frequency.
- */
-void set_beeper_frequency (uint frequency)
-{
-#define FREQ_LIMIT 2500
-
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- /*
- * Compute timer ticks given desired frequency. The timer is set up
- * to count 0.5 uS per tick and it takes two ticks per cycle (Hz).
- */
- if (frequency > FREQ_LIMIT)
- frequency = FREQ_LIMIT;
- frequency = 1000000 / frequency;
- immap->im_cpmtimer.cpmt_trr1 = (ushort) frequency;
-}
-
-/*
- * Turn the beeper on
- */
-void beeper_on (void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_STP1;
-}
-
-/*
- * Turn the beeper off
- */
-void beeper_off (void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- immap->im_cpmtimer.cpmt_tgcr |= TGCR_STP1;
-}
-
-/*
- * Increase or decrease the beeper volume. Volume can be set
- * from off to full in 64 steps. To increase volume, the output
- * pin is actively driven high, then returned to tristate.
- * To decrease volume, output a low on the port pin (no need to
- * change pin mode to tristate) then output a high to go back to
- * tristate.
- */
-void set_beeper_volume (int steps)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- int i;
-
- if (steps >= 0) {
- for (i = 0; i < (steps >= 64 ? 64 : steps); i++) {
- immap->im_cpm.cp_pbodr &= ~(0x80000000 >> 19);
- udelay (1);
- immap->im_cpm.cp_pbodr |= (0x80000000 >> 19);
- udelay (1);
- }
- } else {
- for (i = 0; i > (steps <= -64 ? -64 : steps); i--) {
- immap->im_cpm.cp_pbdat &= ~(0x80000000 >> 19);
- udelay (1);
- immap->im_cpm.cp_pbdat |= (0x80000000 >> 19);
- udelay (1);
- }
- }
-}
-
-/*
- * Check the environment to see if the beeper needs beeping.
- * Controlled by a sequence of the form:
- * freq/delta volume/on time/off time;... where:
- * freq = frequency in Hz (0 - 2500)
- * delta volume = volume steps up or down (-64 <= vol <= 64)
- * on time = time in mS
- * off time = time in mS
- *
- * Return 1 on success, 0 on failure
- */
-int do_beeper (char *sequence)
-{
-#define DELIMITER ';'
-
- int args[4];
- int i;
- int val;
- char *p = sequence;
- char *tp;
-
- /*
- * Parse the control sequence. This is a really simple parser
- * without any real error checking. You can probably blow it
- * up really easily.
- */
- if (*p == '\0' || !isdigit (*p)) {
- printf ("%s:%d: null or invalid string (%s)\n",
- __FILE__, __LINE__, p);
- return 0;
- }
-
- i = 0;
- while (*p != '\0') {
- while (*p != DELIMITER) {
- if (i > 3)
- i = 0;
- val = (int) simple_strtol (p, &tp, 0);
- if (tp == p) {
- printf ("%s:%d: no digits or bad format\n",
- __FILE__, __LINE__);
- return 0;
- } else {
- args[i] = val;
- }
-
- i++;
- if (*tp == DELIMITER)
- p = tp;
- else
- p = ++tp;
- }
- p++;
-
- /*
- * Well, we got something that has a chance of being correct
- */
-#if 0
- for (i = 0; i < 4; i++) {
- printf ("%s:%d:arg %d = %d\n", __FILE__, __LINE__, i,
- args[i]);
- }
- printf ("\n");
-#endif
- set_beeper_frequency (args[0]);
- set_beeper_volume (args[1]);
- beeper_on ();
- udelay (1000 * args[2]);
- beeper_off ();
- udelay (1000 * args[3]);
- }
- return 1;
-}
diff --git a/board/gen860t/beeper.h b/board/gen860t/beeper.h
deleted file mode 100644
index 0734fca..0000000
--- a/board/gen860t/beeper.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * (C) Copyright 2002
- * Keith Outwater, keith_outwater@mvis.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-void init_beeper(void);
-void set_beeper_frequency(uint frequency);
-void beeper_on(void);
-void beeper_off(void);
-void set_beeper_volume(int steps);
-int do_beeper(char *sequence);
diff --git a/board/gen860t/flash.c b/board/gen860t/flash.c
deleted file mode 100644
index ca1ed3d..0000000
--- a/board/gen860t/flash.c
+++ /dev/null
@@ -1,628 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * Keith Outwater, keith_outwater@mvsi.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*
- * Use buffered writes to flash by default - they are about 32x faster than
- * single byte writes.
- */
-#ifndef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER
-#define CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER
-#endif
-
-/*
- * Max time to wait (in mS) for flash device to allocate a write buffer.
- */
-#ifndef CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT
-#define CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT 100
-#endif
-
-/*
- * These functions support a single Intel StrataFlash device (28F128J3A)
- * in byte mode only!. The flash routines are very basic and simple
- * since there isn't really any remapping necessary.
- */
-
-/*
- * Intel SCS (Scalable Command Set) command definitions
- * (taken from 28F128J3A datasheet)
- */
-#define SCS_READ_CMD 0xff
-#define SCS_READ_ID_CMD 0x90
-#define SCS_QUERY_CMD 0x98
-#define SCS_READ_STATUS_CMD 0x70
-#define SCS_CLEAR_STATUS_CMD 0x50
-#define SCS_WRITE_BUF_CMD 0xe8
-#define SCS_PROGRAM_CMD 0x40
-#define SCS_BLOCK_ERASE_CMD 0x20
-#define SCS_BLOCK_ERASE_RESUME_CMD 0xd0
-#define SCS_PROGRAM_RESUME_CMD 0xd0
-#define SCS_BLOCK_ERASE_SUSPEND_CMD 0xb0
-#define SCS_SET_BLOCK_LOCK_CMD 0x60
-#define SCS_CLR_BLOCK_LOCK_CMD 0x60
-
-/*
- * SCS status/extended status register bit definitions
- */
-#define SCS_SR7 0x80
-#define SCS_XSR7 0x80
-
-/*---------------------------------------------------------------------*/
-#if 0
-#define DEBUG_FLASH
-#endif
-
-#ifdef DEBUG_FLASH
-#define PRINTF(fmt,args...) printf(fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_char *addr, flash_info_t *info);
-static int write_data8 (flash_info_t *info, ulong dest, uchar data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- * Initialize the flash memory.
- */
-unsigned long
-flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0;
- int i;
-
- for (i= 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /*
- * The gen860t board only has one FLASH memory device, so the
- * FLASH Bank configuration is done statically.
- */
- PRINTF("\n## Get flash bank 1 size @ 0x%08x\n", FLASH_BASE0_PRELIM);
- size_b0 = flash_get_size((vu_char *)FLASH_BASE0_PRELIM, &flash_info[0]);
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0: "
- "ID 0x%lx, Size = 0x%08lx = %ld MB\n",
- flash_info[0].flash_id,size_b0, size_b0 << 20);
- }
-
- PRINTF("## Before remap:\n"
- " BR0: 0x%08x OR0: 0x%08x\n BR1: 0x%08x OR1: 0x%08x\n",
- memctl->memc_br0, memctl->memc_or0,
- memctl->memc_br1, memctl->memc_or1);
-
- /*
- * Remap FLASH according to real size
- */
- memctl->memc_or0 |= (-size_b0 & 0xFFFF8000);
- memctl->memc_br0 |= (CONFIG_SYS_FLASH_BASE & BR_BA_MSK);
-
- PRINTF("## After remap:\n"
- " BR0: 0x%08x OR0: 0x%08x\n", memctl->memc_br0, memctl->memc_or0);
-
- /*
- * Re-do sizing to get full correct info
- */
- size_b0 = flash_get_size ((vu_char *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
- flash_info[0].size = size_b0;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /*
- * Monitor protection is ON by default
- */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /*
- * Environment protection ON by default
- */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-#endif
-
- PRINTF("## Final Flash bank size: 0x%08lx\n",size_b0);
- return (size_b0);
-}
-
-
-/*-----------------------------------------------------------------------
- * Fill in the FLASH offset table
- */
-static void
-flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base;
- base += 1024 * 128;
- }
- return;
-
- default:
- printf ("Don't know sector offsets for FLASH"
- " type 0x%lx\n", info->flash_id);
- return;
- }
-}
-
-
-/*-----------------------------------------------------------------------
- * Display FLASH device info
- */
-void
-flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL:
- printf ("Intel ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F128J3A:
- printf ("28F128J3A (128Mbit = 128K x 128)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- if (info->size >= (1024 * 1024)) {
- i = 20;
- } else {
- i = 10;
- }
- printf (" Size: %ld %cB in %d Sectors\n",
- info->size >> i,
- (i == 20) ? 'M' : 'k',
- info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-
-/*-----------------------------------------------------------------------
- * Get size and other information for a FLASH device.
- * NOTE: The following code cannot be run from FLASH!
- */
-static
-ulong flash_get_size (vu_char *addr, flash_info_t *info)
-{
-#define NO_FLASH 0
-
- vu_char value[2];
-
- /*
- * Try to read the manufacturer ID
- */
- addr[0] = SCS_READ_CMD;
- addr[0] = SCS_READ_ID_CMD;
- value[0] = addr[0];
- value[1] = addr[2];
- addr[0] = SCS_READ_CMD;
-
- PRINTF("Manuf. ID @ 0x%08lx: 0x%02x\n", (ulong)addr, value[0]);
- switch (value[0]) {
- case (INTEL_MANUFACT & 0xff):
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (NO_FLASH);
- }
-
- /*
- * Read the device ID
- */
- PRINTF("Device ID @ 0x%08lx: 0x%02x\n", (ulong)(&addr[2]), value[1]);
- switch (value[1]) {
- case (INTEL_ID_28F128J3A & 0xff):
- info->flash_id += FLASH_28F128J3A;
- info->sector_count = 128;
- info->size = 16 * 1024 * 1024;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (NO_FLASH);
- }
-
- if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
- printf ("** ERROR: sector count %d > max (%d) **\n",
- info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- }
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- * Erase the specified sectors in the specified FLASH device
- */
-int
-flash_erase(flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
- printf ("Can erase only Intel flash types - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer (0);
- last = start;
-
- /*
- * Start erase on unprotected sectors
- */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_char *addr = (uchar *)(info->start[sect]);
- vu_char status;
-
- /*
- * Disable interrupts which might cause a timeout
- */
- flag = disable_interrupts();
-
- *addr = SCS_CLEAR_STATUS_CMD;
- *addr = SCS_BLOCK_ERASE_CMD;
- *addr = SCS_BLOCK_ERASE_RESUME_CMD;
-
- /*
- * Re-enable interrupts if necessary
- */
- if (flag)
- enable_interrupts();
-
- /*
- * Wait at least 80us - let's wait 1 ms
- */
- udelay (1000);
-
- while (((status = *addr) & SCS_SR7) != SCS_SR7) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = SCS_BLOCK_ERASE_SUSPEND_CMD;
- *addr = SCS_READ_CMD;
- return 1;
- }
-
- /*
- * Show that we're waiting
- */
- if ((now - last) > 1000) { /* 1 second */
- putc ('.');
- last = now;
- }
- }
- *addr = SCS_READ_CMD;
- }
- }
- printf (" done\n");
- return 0;
-}
-
-
-#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER
-/*
- * Allocate a flash buffer, fill it with data and write it to the flash.
- * 0 - OK
- * 1 - Timeout on buffer request
- *
- * NOTE: After the last call to this function, WSM status needs to be checked!
- */
-static int
-write_flash_buffer8(flash_info_t *info_p, vu_char *src_p, vu_char *dest_p,
- uint count)
-{
- vu_char *block_addr_p = NULL;
- vu_char *start_addr_p = NULL;
- ulong blocksize = info_p->size / (ulong)info_p->sector_count;
-
- int i;
- uint time = get_timer(0);
-
- PRINTF("%s:%d: src: 0x%p dest: 0x%p count: %d\n",
- __FUNCTION__, __LINE__, src_p, dest_p, count);
-
- /*
- * What block are we in? We already know that the source address is
- * in the flash address range, but we also can't cross a block boundary.
- * We assume that the block does not cross a boundary (we'll check before
- * calling this function).
- */
- for (i = 0; i < info_p->sector_count; ++i) {
- if ( ((ulong)dest_p >= info_p->start[i]) &&
- ((ulong)dest_p < (info_p->start[i] + blocksize)) ) {
- PRINTF("%s:%d: Dest addr 0x%p is in block %d @ 0x%.8lx\n",
- __FUNCTION__, __LINE__, dest_p, i, info_p->start[i]);
- block_addr_p = (vu_char *)info_p->start[i];
- break;
- }
- }
-
- /*
- * Request a buffer
- */
- *block_addr_p = SCS_WRITE_BUF_CMD;
- while ((*block_addr_p & SCS_XSR7) != SCS_XSR7) {
- if (get_timer(time) > CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT) {
- PRINTF("%s:%d: Buffer allocation timeout @ 0x%p (waited %d mS)\n",
- __FUNCTION__, __LINE__, block_addr_p,
- CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT);
- return 1;
- }
- *block_addr_p = SCS_WRITE_BUF_CMD;
- }
-
- /*
- * Fill the buffer with data
- */
- start_addr_p = dest_p;
- *block_addr_p = count - 1; /* flash device wants count - 1 */
- PRINTF("%s:%d: Fill buffer at block addr 0x%p\n",
- __FUNCTION__, __LINE__, block_addr_p);
- for (i = 0; i < count; i++) {
- *start_addr_p++ = *src_p++;
- }
-
- /*
- * Flush buffer to flash
- */
- *block_addr_p = SCS_PROGRAM_RESUME_CMD;
-#if 1
- time = get_timer(0);
- while ((*block_addr_p & SCS_SR7) != SCS_SR7) {
- if (get_timer(time) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- PRINTF("%s:%d: Write timeout @ 0x%p (waited %d mS)\n",
- __FUNCTION__, __LINE__, block_addr_p, CONFIG_SYS_FLASH_WRITE_TOUT);
- return 1;
- }
- }
-
-#endif
- return 0;
-}
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-int
-write_buff(flash_info_t *info_p, uchar *src_p, ulong addr, ulong count)
-{
- int rc = 0;
-#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER
-#define FLASH_WRITE_BUF_SIZE 0x00000020 /* 32 bytes */
- int i;
- uint bufs;
- ulong buf_count;
- vu_char *sp;
- vu_char *dp;
-#else
- ulong wp;
-#endif
-
- PRINTF("\n%s:%d: src: 0x%.8lx dest: 0x%.8lx size: %d (0x%.8lx)\n",
- __FUNCTION__, __LINE__, (ulong)src_p, addr, (uint)count, count);
-
- if (info_p->flash_id == FLASH_UNKNOWN) {
- return 4;
- }
-
-#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER
- sp = src_p;
- dp = (uchar *)addr;
-
- /*
- * For maximum performance, we want to align the start address to
- * the beginning of a write buffer boundary (i.e. A4-A0 of the
- * start address = 0). See how many bytes are required to get to a
- * write-buffer-aligned address. If that number is non-zero, do
- * non buffered writes of the non-aligned data. By doing non-buffered
- * writes, we avoid the problem of crossing a block (sector) boundary
- * with buffered writes.
- */
- buf_count = FLASH_WRITE_BUF_SIZE - (addr & (FLASH_WRITE_BUF_SIZE - 1));
- if (buf_count == FLASH_WRITE_BUF_SIZE) { /* already on a boundary */
- buf_count = 0;
- }
- if (buf_count > count) { /* not a full buffers worth of data to write */
- buf_count = count;
- }
- count -= buf_count;
-
- PRINTF("%s:%d: Write buffer alignment count = %ld\n",
- __FUNCTION__, __LINE__, buf_count);
- while (buf_count-- >= 1) {
- if ((rc = write_data8(info_p, (ulong)dp++, *sp++)) != 0) {
- return (rc);
- }
- }
-
- PRINTF("%s:%d: count = %ld\n", __FUNCTION__, __LINE__, count);
- if (count == 0) { /* all done */
- PRINTF("%s:%d: Less than 1 buffer (%d) worth of bytes\n",
- __FUNCTION__, __LINE__, FLASH_WRITE_BUF_SIZE);
- return (rc);
- }
-
- /*
- * Now that we are write buffer aligned, write full or partial buffers.
- * The fact that we are write buffer aligned automatically avoids
- * crossing a block address during a write buffer operation.
- */
- bufs = count / FLASH_WRITE_BUF_SIZE;
- PRINTF("%s:%d: %d (0x%x) buffers to write\n", __FUNCTION__, __LINE__,
- bufs, bufs);
- while (bufs >= 1) {
- rc = write_flash_buffer8(info_p, sp, dp, FLASH_WRITE_BUF_SIZE);
- if (rc != 0) {
- PRINTF("%s:%d: ** Error writing buf %d\n",
- __FUNCTION__, __LINE__, bufs);
- return (rc);
- }
- bufs--;
- sp += FLASH_WRITE_BUF_SIZE;
- dp += FLASH_WRITE_BUF_SIZE;
- }
-
- /*
- * Do the leftovers
- */
- i = count % FLASH_WRITE_BUF_SIZE;
- PRINTF("%s:%d: %d (0x%x) leftover bytes\n", __FUNCTION__, __LINE__, i, i);
- if (i > 0) {
- rc = write_flash_buffer8(info_p, sp, dp, i);
- }
-
- sp = (vu_char*)info_p->start[0];
- *sp = SCS_READ_CMD;
- return (rc);
-
-#else
- wp = addr;
- while (count-- >= 1) {
- if((rc = write_data8(info_p, wp++, *src_p++)) != 0)
- return (rc);
- }
- return 0;
-#endif
-}
-
-
-/*-----------------------------------------------------------------------
- * Write a byte to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int
-write_data8 (flash_info_t *info, ulong dest, uchar data)
-{
- vu_char *addr = (vu_char *)dest;
- vu_char status;
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *addr = SCS_PROGRAM_CMD;
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer (0);
-
- while (((status = *addr) & SCS_SR7) != SCS_SR7) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *addr = SCS_READ_CMD;
- return (1);
- }
- }
- *addr = SCS_READ_CMD;
- return (0);
-}
-
-/* vim: set ts=4 sw=4 tw=78: */
diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c
deleted file mode 100644
index dd0ef70..0000000
--- a/board/gen860t/fpga.c
+++ /dev/null
@@ -1,362 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Virtex2 FPGA configuration support for the GEN860T computer
- */
-
-#include <common.h>
-#include <virtex2.h>
-#include <command.h>
-#include "fpga.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_FPGA)
-
-#if 0
-#define GEN860T_FPGA_DEBUG
-#endif
-
-#ifdef GEN860T_FPGA_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-/*
- * Port bit numbers for the Selectmap controls
- */
-#define FPGA_INIT_BIT_NUM 22 /* PB22 */
-#define FPGA_RESET_BIT_NUM 11 /* PC11 */
-#define FPGA_DONE_BIT_NUM 16 /* PB16 */
-#define FPGA_PROGRAM_BIT_NUM 7 /* PA7 */
-
-/* Note that these are pointers to code that is in Flash. They will be
- * relocated at runtime.
- */
-xilinx_virtex2_slave_selectmap_fns fpga_fns = {
- fpga_pre_config_fn,
- fpga_pgm_fn,
- fpga_init_fn,
- fpga_err_fn,
- fpga_done_fn,
- fpga_clk_fn,
- fpga_cs_fn,
- fpga_wr_fn,
- fpga_read_data_fn,
- fpga_write_data_fn,
- fpga_busy_fn,
- fpga_abort_fn,
- fpga_post_config_fn
-};
-
-xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
- {xilinx_virtex2,
- slave_selectmap,
- XILINX_XC2V3000_SIZE,
- (void *) &fpga_fns,
- 0}
-};
-
-/*
- * Display FPGA revision information
- */
-void print_fpga_revision (void)
-{
- vu_long *rev_p = (vu_long *) 0x60000008;
-
- printf ("FPGA Revision 0x%.8lx"
- " (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n",
- *rev_p,
- ((*rev_p >> 28) & 0xf),
- ((*rev_p >> 20) & 0xff),
- ((*rev_p >> 12) & 0xff),
- ((*rev_p >> 8) & 0xf), (*rev_p & 0xff));
-}
-
-
-/*
- * Perform a simple test of the FPGA to processor interface using the FPGA's
- * inverting bus test register. The great thing about doing a read/write
- * test on a register that inverts it's contents is that you avoid any
- * problems with bus charging.
- * Return 0 on failure, 1 on success.
- */
-int test_fpga_ibtr (void)
-{
- vu_long *ibtr_p = (vu_long *) 0x60000010;
- vu_long readback;
- vu_long compare;
- int i;
- int j;
- int k;
- int pass = 1;
-
- static const ulong bitpattern[] = {
- 0xdeadbeef, /* magic ID pattern for debug */
- 0x00000001, /* single bit */
- 0x00000003, /* two adjacent bits */
- 0x00000007, /* three adjacent bits */
- 0x0000000F, /* four adjacent bits */
- 0x00000005, /* two non-adjacent bits */
- 0x00000015, /* three non-adjacent bits */
- 0x00000055, /* four non-adjacent bits */
- 0xaaaaaaaa, /* alternating 1/0 */
- };
-
- for (i = 0; i < 1024; i++) {
- for (j = 0; j < 31; j++) {
- for (k = 0;
- k < sizeof (bitpattern) / sizeof (bitpattern[0]);
- k++) {
- *ibtr_p = compare = (bitpattern[k] << j);
- readback = *ibtr_p;
- if (readback != ~compare) {
- printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback);
- pass = 0;
- break;
- }
- }
- if (!pass)
- break;
- }
- if (!pass)
- break;
- }
- if (pass) {
- printf ("FPGA inverting bus test passed\n");
- print_fpga_revision ();
- } else {
- printf ("** FPGA inverting bus test failed\n");
- }
- return pass;
-}
-
-
-/*
- * Set the active-low FPGA reset signal.
- */
-void fpga_reset (int assert)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__);
- if (assert) {
- immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM);
- PRINTF ("asserted\n");
- } else {
- immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM);
- PRINTF ("deasserted\n");
- }
-}
-
-
-/*
- * Initialize the SelectMap interface. We assume that the mode and the
- * initial state of all of the port pins have already been set!
- */
-void fpga_selectmap_init (void)
-{
- PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__,
- __LINE__);
- fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */
-}
-
-
-/*
- * Initialize the fpga. Return 1 on success, 0 on failure.
- */
-int gen860t_init_fpga (void)
-{
- int i;
-
- PRINTF ("%s:%d: Initialize FPGA interface\n",
- __FUNCTION__, __LINE__);
- fpga_init ();
- fpga_selectmap_init ();
-
- for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
- PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
- fpga_add (fpga_xilinx, &fpga[i]);
- }
- return 1;
-}
-
-
-/*
- * Set the FPGA's active-low SelectMap program line to the specified level
- */
-int fpga_pgm_fn (int assert, int flush, int cookie)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
-
- if (assert) {
- immap->im_ioport.iop_padat &=
- ~(0x8000 >> FPGA_PROGRAM_BIT_NUM);
- PRINTF ("asserted\n");
- } else {
- immap->im_ioport.iop_padat |=
- (0x8000 >> FPGA_PROGRAM_BIT_NUM);
- PRINTF ("deasserted\n");
- }
- return assert;
-}
-
-
-/*
- * Test the state of the active-low FPGA INIT line. Return 1 on INIT
- * asserted (low).
- */
-int fpga_init_fn (int cookie)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
- if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) {
- PRINTF ("high\n");
- return 0;
- } else {
- PRINTF ("low\n");
- return 1;
- }
-}
-
-
-/*
- * Test the state of the active-high FPGA DONE pin
- */
-int fpga_done_fn (int cookie)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
- if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) {
- PRINTF ("high\n");
- return FPGA_SUCCESS;
- } else {
- PRINTF ("low\n");
- return FPGA_FAIL;
- }
-}
-
-
-/*
- * Read FPGA SelectMap data.
- */
-int fpga_read_data_fn (unsigned char *data, int cookie)
-{
- vu_char *p = (vu_char *) SELECTMAP_BASE;
-
- *data = *p;
-#if 0
- PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data);
-#endif
- return (int) data;
-}
-
-
-/*
- * Write data to the FPGA SelectMap port
- */
-int fpga_write_data_fn (unsigned char data, int flush, int cookie)
-{
- vu_char *p = (vu_char *) SELECTMAP_BASE;
-
-#if 0
- PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data);
-#endif
- *p = data;
- return (int) data;
-}
-
-
-/*
- * Abort and FPGA operation
- */
-int fpga_abort_fn (int cookie)
-{
- PRINTF ("%s:%d: FPGA program sequence aborted\n",
- __FUNCTION__, __LINE__);
- return FPGA_FAIL;
-}
-
-
-/*
- * FPGA pre-configuration function. Just make sure that
- * FPGA reset is asserted to keep the FPGA from starting up after
- * configuration.
- */
-int fpga_pre_config_fn (int cookie)
-{
- PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
- fpga_reset(true);
- return 0;
-}
-
-
-/*
- * FPGA post configuration function. Blip the FPGA reset line and then see if
- * the FPGA appears to be running.
- */
-int fpga_post_config_fn (int cookie)
-{
- int rc;
-
- PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
- fpga_reset(true);
- udelay (1000);
- fpga_reset(false);
- udelay (1000);
-
- /*
- * Use the FPGA,s inverting bus test register to do a simple test of the
- * processor interface.
- */
- rc = test_fpga_ibtr ();
- return rc;
-}
-
-
-/*
- * Clock, chip select and write signal assert functions and error check
- * and busy functions. These are only stubs because the GEN860T selectmap
- * interface handles sequencing of control signals automatically (it uses
- * a memory-mapped interface to the FPGA SelectMap port). The design of
- * the interface guarantees that the SelectMap port cannot be overrun so
- * no busy check is needed. A configuration error is signalled by INIT
- * going low during configuration, so there is no need for a separate error
- * function.
- */
-int fpga_clk_fn (int assert_clk, int flush, int cookie)
-{
- return assert_clk;
-}
-
-int fpga_cs_fn (int assert_cs, int flush, int cookie)
-{
- return assert_cs;
-}
-
-int fpga_wr_fn (int assert_write, int flush, int cookie)
-{
- return assert_write;
-}
-
-int fpga_err_fn (int cookie)
-{
- return 0;
-}
-
-int fpga_busy_fn (int cookie)
-{
- return 0;
-}
-#endif
diff --git a/board/gen860t/fpga.h b/board/gen860t/fpga.h
deleted file mode 100644
index 95c15c4..0000000
--- a/board/gen860t/fpga.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Virtex2 FPGA configuration support for the GEN860T computer
- */
-
-extern int gen860t_init_fpga(void);
-extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int fpga_init_fn(int cookie);
-extern int fpga_err_fn(int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
-extern int fpga_wr_fn(int assert_write, int flush, int cookie);
-extern int fpga_read_data_fn(unsigned char *data, int cookie);
-extern int fpga_write_data_fn(unsigned char data, int flush, int cookie);
-extern int fpga_busy_fn(int cookie);
-extern int fpga_abort_fn(int cookie );
-extern int fpga_pre_config_fn(int cookie );
-extern int fpga_post_config_fn(int cookie );
diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c
deleted file mode 100644
index fe139f4..0000000
--- a/board/gen860t/gen860t.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * Keith Outwater, keith_outwater@mvis.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <virtex2.h>
-#include <common.h>
-#include <mpc8xx.h>
-#include <asm/8xx_immap.h>
-#include "beeper.h"
-#include "fpga.h"
-#include "ioport.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_STATUS_LED
-#include <status_led.h>
-#endif
-
-#if defined(CONFIG_CMD_MII) && defined(CONFIG_MII)
-#include <net.h>
-#endif
-
-#if 0
-#define GEN860T_DEBUG
-#endif
-
-#ifdef GEN860T_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-/*
- * The following UPM init tables were generated automatically by
- * Motorola's MCUINIT program. See the README file for UPM to
- * SDRAM pin assignments if you want to type this data into
- * MCUINIT in order to reverse engineer the waveforms.
- */
-
-/*
- * UPM initialization tables for MICRON MT48LC16M16A2TG SDRAM devices
- * (UPMA) and Virtex FPGA SelectMap interface (UPMB).
- * NOTE that unused areas of the table are used to hold NOP, precharge
- * and mode register set sequences.
- *
- */
-#define UPMA_NOP_ADDR 0x5
-#define UPMA_PRECHARGE_ADDR 0x6
-#define UPMA_MRS_ADDR 0x12
-
-#define UPM_SINGLE_READ_ADDR 0x00
-#define UPM_BURST_READ_ADDR 0x08
-#define UPM_SINGLE_WRITE_ADDR 0x18
-#define UPM_BURST_WRITE_ADDR 0x20
-#define UPM_REFRESH_ADDR 0x30
-
-const uint sdram_upm_table[] = {
- /* single read (offset 0x00 in upm ram) */
- 0x0e0fdc04, 0x01adfc04, 0x0fbffc00, 0x1fff5c05,
- 0xffffffff, 0x0fffffcd, 0x0fff0fce, 0xefcfffff,
- /* burst read (offset 0x08 in upm ram) */
- 0x0f0fdc04, 0x00fdfc04, 0xf0fffc00, 0xf0fffc00,
- 0xf1fffc00, 0xfffffc00, 0xfffffc05, 0xffffffff,
- 0xffffffff, 0xffffffff, 0x0ffffff4, 0x1f3d5ff4,
- 0xfffffff4, 0xfffffff5, 0xffffffff, 0xffffffff,
- /* single write (offset 0x18 in upm ram) */
- 0x0f0fdc04, 0x00ad3c00, 0x1fff5c05, 0xffffffff,
- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- /* burst write (offset 0x20 in upm ram) */
- 0x0f0fdc00, 0x10fd7c00, 0xf0fffc00, 0xf0fffc00,
- 0xf1fffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
- 0xffffffff, 0xffffffff, 0xffffffff, 0xfffff7ff,
- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- /* refresh (offset 0x30 in upm ram) */
- 0x1ffddc84, 0xfffffc04, 0xfffffc04, 0xfffffc84,
- 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- /* exception (offset 0x3C in upm ram) */
-};
-
-const uint selectmap_upm_table[] = {
- /* single read (offset 0x00 in upm ram) */
- 0x88fffc06, 0x00fff404, 0x00fffc04, 0x33fffc00,
- 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
- /* burst read (offset 0x08 in upm ram) */
- 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- /* single write (offset 0x18 in upm ram) */
- 0x88fffc04, 0x00fff400, 0x77fffc05, 0xffffffff,
- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- /* burst write (offset 0x20 in upm ram) */
- 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- /* refresh (offset 0x30 in upm ram) */
- 0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- /* exception (offset 0x3C in upm ram) */
- 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff
-};
-
-/*
- * Check board identity. Always successful (gives information only)
- */
-int checkboard (void)
-{
- char *s;
- char buf[64];
- int i;
-
- i = getenv_f("board_id", buf, sizeof (buf));
- s = (i > 0) ? buf : NULL;
-
- if (s) {
- printf ("%s ", s);
- } else {
- printf ("<unknown> ");
- }
-
- i = getenv_f("serial#", buf, sizeof (buf));
- s = (i > 0) ? buf : NULL;
-
- if (s) {
- printf ("S/N %s\n", s);
- } else {
- printf ("S/N <unknown>\n");
- }
-
- printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk));
- printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk));
- return (0);
-}
-
-/*
- * Initialize SDRAM
- */
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
-
- upmconfig (UPMA,
- (uint *) sdram_upm_table,
- sizeof (sdram_upm_table) / sizeof (uint)
- );
-
- /*
- * Setup MAMR register
- */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
- memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
-
- /*
- * Map CS1* to SDRAM bank
- */
- memctl->memc_or1 = CONFIG_SYS_OR1;
- memctl->memc_br1 = CONFIG_SYS_BR1;
-
- /*
- * Perform SDRAM initialization sequence:
- * 1. Apply at least one NOP command
- * 2. 100 uS delay (JEDEC standard says 200 uS)
- * 3. Issue 4 precharge commands
- * 4. Perform two refresh cycles
- * 5. Program mode register
- *
- * Program SDRAM for standard operation, sequential burst, burst length
- * of 4, CAS latency of 2.
- */
- memctl->memc_mar = 0x00000000;
- memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
- MCR_MLCF (0) | UPMA_NOP_ADDR;
- udelay (200);
- memctl->memc_mar = 0x00000000;
- memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
- MCR_MLCF (4) | UPMA_PRECHARGE_ADDR;
-
- memctl->memc_mar = 0x00000000;
- memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
- MCR_MLCF (2) | UPM_REFRESH_ADDR;
-
- memctl->memc_mar = 0x00000088;
- memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
- MCR_MLCF (1) | UPMA_MRS_ADDR;
-
- memctl->memc_mar = 0x00000000;
- memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
- MCR_MLCF (0) | UPMA_NOP_ADDR;
- /*
- * Enable refresh
- */
- memctl->memc_mamr |= MAMR_PTAE;
-
- return (SDRAM_SIZE);
-}
-
-/*
- * Disk On Chip (DOC) Millenium initialization.
- * The DOC lives in the CS2* space
- */
-#if defined(CONFIG_CMD_DOC)
-void doc_init (void)
-{
- printf ("Probing at 0x%.8x: ", DOC_BASE);
- doc_probe (DOC_BASE);
-}
-#endif
-
-/*
- * Miscellaneous intialization
- */
-int misc_init_r (void)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immr->im_memctl;
-
- /*
- * Set up UPMB to handle the Virtex FPGA SelectMap interface
- */
- upmconfig (UPMB, (uint *) selectmap_upm_table,
- sizeof (selectmap_upm_table) / sizeof (uint));
-
- memctl->memc_mbmr = 0x0;
-
- config_mpc8xx_ioports (immr);
-
-#if defined(CONFIG_CMD_MII)
- mii_init ();
-#endif
-
-#if defined(CONFIG_FPGA)
- gen860t_init_fpga ();
-#endif
- return 0;
-}
-
-/*
- * Final init hook before entering command loop.
- */
-int last_stage_init (void)
-{
-#if !defined(CONFIG_SC)
- char buf[256];
- int i;
-
- /*
- * Turn the beeper volume all the way down in case this is a warm boot.
- */
- set_beeper_volume (-64);
- init_beeper ();
-
- /*
- * Read the environment to see what to do with the beeper
- */
- i = getenv_f("beeper", buf, sizeof (buf));
- if (i > 0) {
- do_beeper (buf);
- }
-#endif
- return 0;
-}
-
-/*
- * Stub to make POST code happy. Can't self-poweroff, so just hang.
- */
-void board_poweroff (void)
-{
- puts ("### Please power off the board ###\n");
- while (1);
-}
diff --git a/board/gen860t/ioport.c b/board/gen860t/ioport.c
deleted file mode 100644
index 7cd209b..0000000
--- a/board/gen860t/ioport.c
+++ /dev/null
@@ -1,331 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#include <asm/8xx_immap.h>
-#include "ioport.h"
-
-#if 0
-#define IOPORT_DEBUG
-#endif
-
-#ifdef IOPORT_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-/*
- * The ioport configuration table.
- */
-const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = {
- /*
- * Port A configuration
- * Pin Signal Type Active Initial state
- * PA7 fpgaProgramLowOut Out Low High
- * PA1 fpgaCoreVoltageFailLow In Low N/A
- */
- { /* conf ppar psor pdir podr pdat pint function */
- /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* No pin */
- /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* No pin */
- /* PA15 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PA14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PA13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PA12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PA11 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PA10 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PA9 */ { 1, 0, 0, 1, 0, 0, 0 }, /* grn bicolor LED 1*/
- /* PA8 */ { 1, 0, 0, 1, 0, 0, 0 }, /* red bicolor LED 1*/
- /* PA7 */ { 1, 0, 0, 1, 0, 1, 0 }, /* fpgaProgramLow */
- /* PA6 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PA5 */ { 1, 0, 0, 1, 0, 0, 0 }, /* grn bicolor LED 0*/
- /* PA4 */ { 1, 0, 0, 1, 0, 0, 0 }, /* red bicolor LED 0*/
- /* PA3 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PA2 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
-#if !defined(CONFIG_SC)
- /* PA1 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaCoreVoltageFail*/
-#else
- /* PA1 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
-#endif
- /* PA0 */ { 0, 0, 0, 0, 0, 0, 0 } /* */
- },
-
- /*
- * Port B configuration
- * Pin Signal Type Active Initial state
- * PB14 docBusyLowIn In Low X
- * PB15 gpio1Sig Out High Low
- * PB16 fpgaDoneBi In High X
- * PB17 swBitOkLowOut Out Low High
- * PB19 speakerVolSig Out/Hi-Z High/Low High (Hi-Z)
- * PB22 fpgaInitLowBi In Low X
- * PB23 batteryOkSig In High X
- * PB31 pulseCatcherClr Out High 0
- */
- { /* conf ppar psor pdir podr pdat pint function */
-#if !defined(CONFIG_SC)
- /* PB31 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
-#else
- /* PB31 */ { 1, 0, 0, 1, 0, 0, 0 }, /* pulseCatcherClr */
-#endif
- /* PB30 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PB29 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PB28 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PB27 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PB26 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PB25 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PB24 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
-#if !defined(CONFIG_SC)
- /* PB23 */ { 1, 0, 0, 0, 0, 0, 0 }, /* batteryOk */
-#else
- /* PB23 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
-#endif
- /* PB22 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaInitLowBi */
- /* PB21 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PB20 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
-#if !defined(CONFIG_SC)
- /* PB19 */ { 1, 0, 0, 1, 1, 1, 0 }, /* speakerVol */
-#else
- /* PB19 */ { 0, 0, 0, 1, 1, 1, 0 }, /* */
-#endif
- /* PB18 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PB17 */ { 1, 0, 0, 1, 0, 1, 0 }, /* swBitOkLow */
- /* PB16 */ { 1, 0, 0, 0, 0, 0, 0 }, /* fpgaDone */
- /* PB15 */ { 1, 0, 0, 1, 0, 0, 0 }, /* gpio1 */
-#if !defined(CONFIG_SC)
- /* PB14 */ { 1, 0, 0, 0, 0, 0, 0 } /* docBusyLow */
-#else
- /* PB14 */ { 0, 0, 0, 0, 0, 0, 0 } /* */
-#endif
- },
-
- /*
- * Port C configuration
- * Pin Signal Type Active Initial state
- * PC4 i2cBus1EnSig Out High High
- * PC5 i2cBus2EnSig Out High High
- * PC6 gpio0Sig Out High Low
- * PC8 i2cBus3EnSig Out High High
- * PC10 i2cBus4EnSig Out High High
- * PC11 fpgaResetLowOut Out Low High
- * PC12 systemBitOkIn In High X
- * PC15 selfDreqLow In Low X
- */
- { /* conf ppar psor pdir podr pdat pint function */
- /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PC15 */ { 1, 0, 0, 0, 0, 0, 0 }, /* selfDreqLowIn */
- /* PC14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PC13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
-#if !defined(CONFIG_SC)
- /* PC12 */ { 1, 0, 0, 0, 0, 0, 0 }, /* systemBitOkIn */
-#else
- /* PC12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
-#endif
- /* PC11 */ { 1, 0, 0, 1, 0, 1, 0 }, /* fpgaResetLowOut */
-#if !defined(CONFIG_SC)
- /* PC10 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus4EnSig */
-#else
- /* PC10 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */
-#endif
- /* PC9 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
-#if !defined(CONFIG_SC)
- /* PC8 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus3EnSig */
-#else
- /* PC8 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */
-#endif
- /* PC7 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PC6 */ { 1, 0, 0, 1, 0, 1, 0 }, /* gpio0 */
-#if !defined(CONFIG_SC)
- /* PC5 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus2EnSig */
- /* PC4 */ { 1, 0, 0, 1, 0, 1, 0 }, /* i2cBus1EnSig */
-#else
- /* PC5 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */
- /* PC4 */ { 0, 0, 0, 1, 0, 1, 0 }, /* */
-#endif
- /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* N/A */ { 0, 0, 0, 0, 0, 0, 0 } /* */
- },
-
- /*
- * Port D configuration
- */
- { /* conf ppar psor pdir podr pdat pint function */
- /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PD15 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PD14 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PD13 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PD12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PD11 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PD10 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PD9 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PD8 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PD7 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PD6 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PD5 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PD4 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* PD3 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */
- /* N/A */ { 0, 0, 0, 0, 0, 0, 0 } /* */
- }
-};
-
-/*
- * Configure the MPC8XX I/O ports per the ioport configuration table
- * (taken from ./arch/powerpc/cpu/mpc8260/cpu_init.c)
- */
-void config_mpc8xx_ioports (volatile immap_t * immr)
-{
- int portnum;
-
- for (portnum = 0; portnum < NUM_PORTS; portnum++) {
- uint pmsk = 0, ppar = 0, psor = 0, pdir = 0;
- uint podr = 0, pdat = 0, pint = 0;
- uint msk = 1;
- mpc8xx_iop_conf_t *iopc =
- (mpc8xx_iop_conf_t *) & iop_conf_tab[portnum][0];
- mpc8xx_iop_conf_t *eiopc = iopc + PORT_BITS;
-
- /*
- * For all ports except port B, ignore the two don't care entries
- * in the configuration tables.
- */
- if (portnum != 1) {
- iopc = (mpc8xx_iop_conf_t *) &
- iop_conf_tab[portnum][2];
- }
-
- /*
- * NOTE: index 0 refers to pin 17, index 17 refers to pin 0
- */
- while (iopc < eiopc) {
- if (iopc->conf) {
- pmsk |= msk;
- if (iopc->ppar)
- ppar |= msk;
- if (iopc->psor)
- psor |= msk;
- if (iopc->pdir)
- pdir |= msk;
- if (iopc->podr)
- podr |= msk;
- if (iopc->pdat)
- pdat |= msk;
- if (iopc->pint)
- pint |= msk;
- }
- msk <<= 1;
- iopc++;
- }
-
- PRINTF ("%s:%d:\n portnum=%d ", __FUNCTION__, __LINE__,
- portnum);
-#ifdef IOPORT_DEBUG
- switch (portnum) {
- case 0:
- printf ("(A)\n");
- break;
- case 1:
- printf ("(B)\n");
- break;
- case 2:
- printf ("(C)\n");
- break;
- case 3:
- printf ("(D)\n");
- break;
- default:
- printf ("(?)\n");
- break;
- }
-#endif
- PRINTF (" ppar=0x%.8x pdir=0x%.8x podr=0x%.8x\n"
- " pdat=0x%.8x psor=0x%.8x pint=0x%.8x pmsk=0x%.8x\n",
- ppar, pdir, podr, pdat, psor, pint, pmsk);
-
- /*
- * Have to handle the ioports on a port-by-port basis since there
- * are three different flavors.
- */
- if (pmsk != 0) {
- uint tpmsk = ~pmsk;
-
- if (0 == portnum) { /* port A */
- immr->im_ioport.iop_papar &= tpmsk;
- immr->im_ioport.iop_padat =
- (immr->im_ioport.
- iop_padat & tpmsk) | pdat;
- immr->im_ioport.iop_padir =
- (immr->im_ioport.
- iop_padir & tpmsk) | pdir;
- immr->im_ioport.iop_paodr =
- (immr->im_ioport.
- iop_paodr & tpmsk) | podr;
- immr->im_ioport.iop_papar |= ppar;
- } else if (1 == portnum) { /* port B */
- immr->im_cpm.cp_pbpar &= tpmsk;
- immr->im_cpm.cp_pbdat =
- (immr->im_cpm.
- cp_pbdat & tpmsk) | pdat;
- immr->im_cpm.cp_pbdir =
- (immr->im_cpm.
- cp_pbdir & tpmsk) | pdir;
- immr->im_cpm.cp_pbodr =
- (immr->im_cpm.
- cp_pbodr & tpmsk) | podr;
- immr->im_cpm.cp_pbpar |= ppar;
- } else if (2 == portnum) { /* port C */
- immr->im_ioport.iop_pcpar &= tpmsk;
- immr->im_ioport.iop_pcdat =
- (immr->im_ioport.
- iop_pcdat & tpmsk) | pdat;
- immr->im_ioport.iop_pcdir =
- (immr->im_ioport.
- iop_pcdir & tpmsk) | pdir;
- immr->im_ioport.iop_pcint =
- (immr->im_ioport.
- iop_pcint & tpmsk) | pint;
- immr->im_ioport.iop_pcso =
- (immr->im_ioport.
- iop_pcso & tpmsk) | psor;
- immr->im_ioport.iop_pcpar |= ppar;
- } else if (3 == portnum) { /* port D */
- immr->im_ioport.iop_pdpar &= tpmsk;
- immr->im_ioport.iop_pddat =
- (immr->im_ioport.
- iop_pddat & tpmsk) | pdat;
- immr->im_ioport.iop_pddir =
- (immr->im_ioport.
- iop_pddir & tpmsk) | pdir;
- immr->im_ioport.iop_pdpar |= ppar;
- }
- }
- }
-
- PRINTF ("%s:%d: Port A:\n papar=0x%.4x padir=0x%.4x"
- " paodr=0x%.4x\n padat=0x%.4x\n", __FUNCTION__, __LINE__,
- immr->im_ioport.iop_papar, immr->im_ioport.iop_padir,
- immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat);
- PRINTF ("%s:%d: Port B:\n pbpar=0x%.8x pbdir=0x%.8x"
- " pbodr=0x%.8x\n pbdat=0x%.8x\n", __FUNCTION__, __LINE__,
- immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir,
- immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat);
- PRINTF ("%s:%d: Port C:\n pcpar=0x%.4x pcdir=0x%.4x"
- " pcdat=0x%.4x\n pcso=0x%.4x pcint=0x%.4x\n ",
- __FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar,
- immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat,
- immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint);
- PRINTF ("%s:%d: Port D:\n pdpar=0x%.4x pddir=0x%.4x"
- " pddat=0x%.4x\n", __FUNCTION__, __LINE__,
- immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir,
- immr->im_ioport.iop_pddat);
-}
diff --git a/board/gen860t/ioport.h b/board/gen860t/ioport.h
deleted file mode 100644
index 4ac2aa4..0000000
--- a/board/gen860t/ioport.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * Keith Outwater, keith_outwater@mvis.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define NUM_PORTS 4
-#define PORT_BITS 18
-
-/*
- * This structure provides configuration information for one port pin.
- * We include all fields needed to initialize any of the ioports.
- */
-typedef struct {
- unsigned char conf:1; /* If 1, configure this port */
- unsigned char ppar:1; /* Port Pin Assignment Register */
- unsigned char psor:1; /* Port Special Options Register */
- unsigned char pdir:1; /* Port Data Direction Register */
- unsigned char podr:1; /* Port Open Drain Register */
- unsigned char pdat:1; /* Port Data Register */
- unsigned char pint:1; /* Port Interrupt Register */
-} mpc8xx_iop_conf_t;
-
-extern void config_mpc8xx_ioports(volatile immap_t *immr);
diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds
deleted file mode 100644
index 7a4a763..0000000
--- a/board/gen860t/u-boot-flashenv.lds
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Linker command file for the GEN860T board when the environment is
- * stored in flash memory.
- *
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /*
- * Read-only sections, merged into text segment:
- */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /*
- * Read-write section, merged into data segment:
- */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- KEEP(*(.got))
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data:
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-
- .ppcenv:
- {
- . = env_offset;
- common/env_embedded.o
- }
-}
diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds
deleted file mode 100644
index 3371c0a..0000000
--- a/board/gen860t/u-boot.lds
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Linker command file for the GEN860T board.
- *
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /*
- * Read-only sections, merged into text segment:
- */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /*
- * Read-write section, merged into data segment:
- */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
index cd08379..4a73613 100644
--- a/board/keymile/kmp204x/kmp204x.c
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -108,8 +108,8 @@ int board_early_init_f(void)
/* and enable WD on it */
qrio_wdmask(BFTIC4_RST, true);
- /* set the ZL30138's prstcfg to reset at power-up and unit reset only */
- qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* set the ZL30138's prstcfg to reset at power-up only */
+ qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
/* and take it out of reset as soon as possible (needed for Hooper) */
qrio_prst(ZL30158_RST, false, false);
@@ -158,8 +158,8 @@ int misc_init_f(void)
qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
qrio_prst(ETH_FRONT_PHY_RST, false, false);
- /* set the ZL30343 prstcfg to reset at power-up and unit reset only */
- qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* set the ZL30343 prstcfg to reset at power-up only */
+ qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
/* and enable the WD on it */
qrio_wdmask(ZL30343_RST, true);
diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c
index 50e8d82..5427de5 100644
--- a/board/prodrive/alpr/nand.c
+++ b/board/prodrive/alpr/nand.c
@@ -93,6 +93,7 @@ static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
}
}
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
{
int i;
@@ -103,6 +104,7 @@ static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len
return 0;
}
+#endif
static int alpr_nand_dev_ready(struct mtd_info *mtd)
{
@@ -128,7 +130,9 @@ int board_nand_init(struct nand_chip *nand)
nand->read_byte = alpr_nand_read_byte;
nand->write_buf = alpr_nand_write_buf;
nand->read_buf = alpr_nand_read_buf;
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
nand->verify_buf = alpr_nand_verify_buf;
+#endif
nand->dev_ready = alpr_nand_dev_ready;
return 0;
diff --git a/board/psyent/common/AMDLV065D.c b/board/psyent/common/AMDLV065D.c
deleted file mode 100644
index 64cb970..0000000
--- a/board/psyent/common/AMDLV065D.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <common.h>
-#include <asm/io.h>
-
-#define SECTSZ (64 * 1024)
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*----------------------------------------------------------------------*/
-unsigned long flash_init (void)
-{
- int i;
- unsigned long addr;
- flash_info_t *fli = &flash_info[0];
-
- fli->size = CONFIG_SYS_FLASH_SIZE;
- fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
-
- addr = CONFIG_SYS_FLASH_BASE;
- for (i = 0; i < fli->sector_count; ++i) {
- fli->start[i] = addr;
- addr += SECTSZ;
- fli->protect[i] = 1;
- }
-
- return (CONFIG_SYS_FLASH_SIZE);
-}
-/*--------------------------------------------------------------------*/
-void flash_print_info (flash_info_t * info)
-{
- int i, k;
- int erased;
- unsigned long *addr;
-
- printf (" Size: %ld KB in %d Sectors\n",
- info->size >> 10, info->sector_count);
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
-
- /* Check if whole sector is erased */
- erased = 1;
- addr = (unsigned long *) info->start[i];
- for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) {
- if ( readl(addr++) != (unsigned long)-1) {
- erased = 0;
- break;
- }
- }
-
- /* Print the info */
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " ");
- }
- printf ("\n");
-}
-
-/*-------------------------------------------------------------------*/
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- unsigned char *addr = (unsigned char *) info->start[0];
- unsigned char *addr2;
- int prot, sect;
- ulong start;
-
- /* Some sanity checking */
- if ((s_first < 0) || (s_first > s_last)) {
- printf ("- no sectors to erase\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- /* It's ok to erase multiple sectors provided we don't delay more
- * than 50 usec between cmds ... at which point the erase time-out
- * occurs. So don't go and put printf() calls in the loop ... it
- * won't be very helpful ;-)
- */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (unsigned char *) info->start[sect];
- writeb (0xaa, addr);
- writeb (0x55, addr);
- writeb (0x80, addr);
- writeb (0xaa, addr);
- writeb (0x55, addr);
- writeb (0x30, addr2);
- /* Now just wait for 0xff & provide some user
- * feedback while we wait.
- */
- start = get_timer (0);
- while ( readb (addr2) != 0xff) {
- udelay (1000 * 1000);
- putc ('.');
- if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("timeout\n");
- return 1;
- }
- }
- }
- }
- printf ("\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-
- vu_char *cmd = (vu_char *) info->start[0];
- vu_char *dst = (vu_char *) addr;
- unsigned char b;
- ulong start;
-
- while (cnt) {
- /* Check for sufficient erase */
- b = *src;
- if ((readb (dst) & b) != b) {
- printf ("%02x : %02x\n", readb (dst), b);
- return (2);
- }
-
- writeb (0xaa, cmd);
- writeb (0x55, cmd);
- writeb (0xa0, cmd);
- writeb (dst, b);
-
- /* Verify write */
- start = get_timer (0);
- while (readb (dst) != b) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return 1;
- }
- }
- dst++;
- src++;
- cnt--;
- }
-
- return (0);
-}
diff --git a/board/psyent/pci5441/Kconfig b/board/psyent/pci5441/Kconfig
deleted file mode 100644
index d722f31..0000000
--- a/board/psyent/pci5441/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_PCI5441
-
-config SYS_BOARD
- string
- default "pci5441"
-
-config SYS_VENDOR
- string
- default "psyent"
-
-config SYS_CONFIG_NAME
- string
- default "PCI5441"
-
-endif
diff --git a/board/psyent/pci5441/MAINTAINERS b/board/psyent/pci5441/MAINTAINERS
deleted file mode 100644
index f1f10e9..0000000
--- a/board/psyent/pci5441/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PCI5441 BOARD
-M: Scott McNutt <smcnutt@psyent.com>
-S: Maintained
-F: board/psyent/pci5441/
-F: include/configs/PCI5441.h
-F: configs/PCI5441_defconfig
diff --git a/board/psyent/pci5441/Makefile b/board/psyent/pci5441/Makefile
deleted file mode 100644
index 364f163..0000000
--- a/board/psyent/pci5441/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := pci5441.o ../common/AMDLV065D.o
diff --git a/board/psyent/pci5441/config.mk b/board/psyent/pci5441/config.mk
deleted file mode 100644
index 776fa8a..0000000
--- a/board/psyent/pci5441/config.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2004, Psyent Corporation <www.psyent.com>
-# Scott McNutt <smcnutt@psyent.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0x018e0000
-
-PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
diff --git a/board/psyent/pci5441/pci5441.c b/board/psyent/pci5441/pci5441.c
deleted file mode 100644
index 6d619e5..0000000
--- a/board/psyent/pci5441/pci5441.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-int board_early_init_f (void)
-{
- return 0;
-}
-
-int checkboard (void)
-{
- puts ("BOARD : Psyent PCI-5441\n");
- return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
- return (0);
-}
diff --git a/board/psyent/pk1c20/Kconfig b/board/psyent/pk1c20/Kconfig
deleted file mode 100644
index 75f6cd1..0000000
--- a/board/psyent/pk1c20/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_PK1C20
-
-config SYS_BOARD
- string
- default "pk1c20"
-
-config SYS_VENDOR
- string
- default "psyent"
-
-config SYS_CONFIG_NAME
- string
- default "PK1C20"
-
-endif
diff --git a/board/psyent/pk1c20/MAINTAINERS b/board/psyent/pk1c20/MAINTAINERS
deleted file mode 100644
index 32b901a..0000000
--- a/board/psyent/pk1c20/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PK1C20 BOARD
-M: Scott McNutt <smcnutt@psyent.com>
-S: Maintained
-F: board/psyent/pk1c20/
-F: include/configs/PK1C20.h
-F: configs/PK1C20_defconfig
diff --git a/board/psyent/pk1c20/Makefile b/board/psyent/pk1c20/Makefile
deleted file mode 100644
index 5450f93..0000000
--- a/board/psyent/pk1c20/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := pk1c20.o led.o ../common/AMDLV065D.o
diff --git a/board/psyent/pk1c20/config.mk b/board/psyent/pk1c20/config.mk
deleted file mode 100644
index 83cfadc..0000000
--- a/board/psyent/pk1c20/config.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2004, Psyent Corporation <www.psyent.com>
-# Scott McNutt <smcnutt@psyent.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE = 0x01fc0000
-
-PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
diff --git a/board/psyent/pk1c20/led.c b/board/psyent/pk1c20/led.c
deleted file mode 100644
index 580d590..0000000
--- a/board/psyent/pk1c20/led.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <nios2-io.h>
-#include <status_led.h>
-
-/* The LED port is configured as output only, so we
- * must track the state manually.
- */
-static led_id_t val = 0;
-
-void __led_init (led_id_t mask, int state)
-{
- nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
-
- if (state == STATUS_LED_ON)
- val &= ~mask;
- else
- val |= mask;
- writel (val, &pio->data);
-}
-
-void __led_set (led_id_t mask, int state)
-{
- nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
-
- if (state == STATUS_LED_ON)
- val &= ~mask;
- else
- val |= mask;
- writel (val, &pio->data);
-}
-
-void __led_toggle (led_id_t mask)
-{
- nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
-
- val ^= mask;
- writel (val, &pio->data);
-}
diff --git a/board/psyent/pk1c20/pk1c20.c b/board/psyent/pk1c20/pk1c20.c
deleted file mode 100644
index 0b4c9f8..0000000
--- a/board/psyent/pk1c20/pk1c20.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-int board_early_init_f (void)
-{
- return 0;
-}
-
-int checkboard (void)
-{
- puts ("BOARD : Psyent PK-1C20\n");
- return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
- return (0);
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_SMC91111
- rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile
index 41d0cc3..93347ef 100644
--- a/board/samsung/common/Makefile
+++ b/board/samsung/common/Makefile
@@ -6,7 +6,7 @@
#
obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
-obj-$(CONFIG_THOR_FUNCTION) += thor.o
+obj-$(CONFIG_USBDOWNLOAD_GADGET) += gadget.o
obj-$(CONFIG_MISC_COMMON) += misc.o
ifndef CONFIG_SPL_BUILD
diff --git a/board/samsung/common/thor.c b/board/samsung/common/gadget.c
index 1c7630d..6a1e57f 100644
--- a/board/samsung/common/thor.c
+++ b/board/samsung/common/gadget.c
@@ -13,6 +13,9 @@ int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
if (!strcmp(name, "usb_dnl_thor")) {
put_unaligned(CONFIG_G_DNL_THOR_VENDOR_NUM, &dev->idVendor);
put_unaligned(CONFIG_G_DNL_THOR_PRODUCT_NUM, &dev->idProduct);
+ } else if (!strcmp(name, "usb_dnl_ums")) {
+ put_unaligned(CONFIG_G_DNL_UMS_VENDOR_NUM, &dev->idVendor);
+ put_unaligned(CONFIG_G_DNL_UMS_PRODUCT_NUM, &dev->idProduct);
} else {
put_unaligned(CONFIG_G_DNL_VENDOR_NUM, &dev->idVendor);
put_unaligned(CONFIG_G_DNL_PRODUCT_NUM, &dev->idProduct);
diff --git a/board/sixnet/Kconfig b/board/sixnet/Kconfig
deleted file mode 100644
index 2c1b995..0000000
--- a/board/sixnet/Kconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-if TARGET_SXNI855T
-
-config SYS_BOARD
- string
- default "sixnet"
-
-config SYS_CONFIG_NAME
- string
- default "SXNI855T"
-
-endif
diff --git a/board/sixnet/MAINTAINERS b/board/sixnet/MAINTAINERS
deleted file mode 100644
index eedb409..0000000
--- a/board/sixnet/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SIXNET BOARD
-M: Dave Ellis <DGE@sixnetio.com>
-S: Orphan (since 2014-06)
-F: board/sixnet/
-F: include/configs/SXNI855T.h
-F: configs/SXNI855T_defconfig
diff --git a/board/sixnet/Makefile b/board/sixnet/Makefile
deleted file mode 100644
index 25a8d69..0000000
--- a/board/sixnet/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = sixnet.o flash.o
diff --git a/board/sixnet/flash.c b/board/sixnet/flash.c
deleted file mode 100644
index 75bc3eb..0000000
--- a/board/sixnet/flash.c
+++ /dev/null
@@ -1,774 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-/* environment.h defines the various CONFIG_ENV_... values in terms
- * of whichever ones are given in the configuration file.
- */
-#include <environment.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
- * has nothing to do with the flash chip being 8-bit or 16-bit.
- */
-#ifdef CONFIG_FLASH_16BIT
-typedef unsigned short FLASH_PORT_WIDTH;
-typedef volatile unsigned short FLASH_PORT_WIDTHV;
-#define FLASH_ID_MASK 0xFFFF
-#else
-typedef unsigned long FLASH_PORT_WIDTH;
-typedef volatile unsigned long FLASH_PORT_WIDTHV;
-#define FLASH_ID_MASK 0xFFFFFFFF
-#endif
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define ORMASK(size) ((-size) & OR_AM_MSK)
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV *addr, flash_info_t *info);
-static void flash_reset(flash_info_t *info);
-static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
-static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
-static void flash_get_offsets(ulong base, flash_info_t *info);
-#ifdef CONFIG_SYS_FLASH_PROTECTION
-static void flash_sync_real_protect(flash_info_t *info);
-#endif
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- size_b = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_info[0].size = size_b;
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n",size_b);
- }
-
- /* Remap FLASH according to real size, so only at proper address */
- memctl->memc_or0 = (memctl->memc_or0 & ~OR_AM_MSK) | ORMASK(size_b);
-
- /* Do this again (was done already in flast_get_size), just
- * in case we move it when remap the FLASH.
- */
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#ifdef CONFIG_SYS_FLASH_PROTECTION
- /* read the hardware protection status (if any) into the
- * protection array in flash_info.
- */
- flash_sync_real_protect(&flash_info[0]);
-#endif
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_ADDR
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_ADDR_REDUND
- flash_protect ( FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[0]);
-#endif
-
- return (size_b);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t *info)
-{
- FPWV *base = (FPWV *)(info->start[0]);
-
- /* Put FLASH back in read mode */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
- *base = (FPW)0x00FF00FF; /* Intel Read Mode */
- else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
- *base = (FPW)0x00F000F0; /* AMD Read Mode */
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
- && (info->flash_id & FLASH_BTYPE)) {
- int bootsect_size; /* number of bytes/boot sector */
- int sect_size; /* number of bytes/regular sector */
-
- bootsect_size = 0x00002000 * (sizeof(FPW)/2);
- sect_size = 0x00010000 * (sizeof(FPW)/2);
-
- /* set sector offsets for bottom boot block type */
- for (i = 0; i < 8; ++i) {
- info->start[i] = base + (i * bootsect_size);
- }
- for (i = 8; i < info->sector_count; i++) {
- info->start[i] = base + ((i - 7) * sect_size);
- }
- }
- else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
- && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
-
- int sect_size; /* number of bytes/sector */
-
- sect_size = 0x00010000 * (sizeof(FPW)/2);
-
- /* set up sector start address table (uniform sector type) */
- for( i = 0; i < info->sector_count; i++ )
- info->start[i] = base + (i * sect_size);
- }
- else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
- && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) {
-
- int sect_size; /* number of bytes/sector */
-
- sect_size = 0x00010000 * (sizeof(FPW)/2);
-
- /* set up sector start address table (top boot sector type) */
- for (i = 0; i < info->sector_count - 3; i++)
- info->start[i] = base + (i * sect_size);
- i = info->sector_count - 1;
- info->start[i--] = base + (info->size - 0x00004000) * (sizeof(FPW)/2);
- info->start[i--] = base + (info->size - 0x00006000) * (sizeof(FPW)/2);
- info->start[i--] = base + (info->size - 0x00008000) * (sizeof(FPW)/2);
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
- uchar *boottype;
- uchar *bootletter;
- char *fmt;
- uchar botbootletter[] = "B";
- uchar topbootletter[] = "T";
- uchar botboottype[] = "bottom boot sector";
- uchar topboottype[] = "top boot sector";
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("STM "); break;
- case FLASH_MAN_INTEL: printf ("INTEL "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- /* check for top or bottom boot, if it applies */
- if (info->flash_id & FLASH_BTYPE) {
- boottype = botboottype;
- bootletter = botbootletter;
- }
- else {
- boottype = topboottype;
- bootletter = topbootletter;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM800T:
- fmt = "29LV800B%s (8 Mbit, %s)\n";
- break;
- case FLASH_AM640U:
- fmt = "29LV641D (64 Mbit, uniform sectors)\n";
- break;
- case FLASH_28F800C3B:
- case FLASH_28F800C3T:
- fmt = "28F800C3%s (8 Mbit, %s)\n";
- break;
- case FLASH_INTEL800B:
- case FLASH_INTEL800T:
- fmt = "28F800B3%s (8 Mbit, %s)\n";
- break;
- case FLASH_28F160C3B:
- case FLASH_28F160C3T:
- fmt = "28F160C3%s (16 Mbit, %s)\n";
- break;
- case FLASH_INTEL160B:
- case FLASH_INTEL160T:
- fmt = "28F160B3%s (16 Mbit, %s)\n";
- break;
- case FLASH_28F320C3B:
- case FLASH_28F320C3T:
- fmt = "28F320C3%s (32 Mbit, %s)\n";
- break;
- case FLASH_INTEL320B:
- case FLASH_INTEL320T:
- fmt = "28F320B3%s (32 Mbit, %s)\n";
- break;
- case FLASH_28F640C3B:
- case FLASH_28F640C3T:
- fmt = "28F640C3%s (64 Mbit, %s)\n";
- break;
- case FLASH_INTEL640B:
- case FLASH_INTEL640T:
- fmt = "28F640B3%s (64 Mbit, %s)\n";
- break;
- default:
- fmt = "Unknown Chip Type\n";
- break;
- }
-
- printf (fmt, bootletter, boottype);
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20,
- info->sector_count);
-
- printf (" Sector Start Addresses:");
-
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0) {
- printf ("\n ");
- }
-
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
-
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size (FPWV *addr, flash_info_t *info)
-{
- /* Write auto select command: read Manufacturer ID */
-
- /* Write auto select command sequence and test FLASH answer */
- addr[0x0555] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
- addr[0x02AA] = (FPW)0x00550055; /* for AMD, Intel ignores this */
- addr[0x0555] = (FPW)0x00900090; /* selects Intel or AMD */
-
- /* The manufacturer codes are only 1 byte, so just use 1 byte.
- * This works for any bus width and any FLASH device width.
- */
- switch (addr[0] & 0xff) {
-
- case (uchar)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
-
- case (uchar)INTEL_MANUFACT:
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
- }
-
- /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
- if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
-
- case (FPW)AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000 * (sizeof(FPW)/2);
- break; /* => 1 or 2 MiB */
-
- case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
- info->flash_id += FLASH_AM640U;
- info->sector_count = 128;
- info->size = 0x00800000 * (sizeof(FPW)/2);
- break; /* => 8 or 16 MB */
-
- case (FPW)INTEL_ID_28F800C3B:
- info->flash_id += FLASH_28F800C3B;
- info->sector_count = 23;
- info->size = 0x00100000 * (sizeof(FPW)/2);
- break; /* => 1 or 2 MB */
-
- case (FPW)INTEL_ID_28F800B3B:
- info->flash_id += FLASH_INTEL800B;
- info->sector_count = 23;
- info->size = 0x00100000 * (sizeof(FPW)/2);
- break; /* => 1 or 2 MB */
-
- case (FPW)INTEL_ID_28F160C3B:
- info->flash_id += FLASH_28F160C3B;
- info->sector_count = 39;
- info->size = 0x00200000 * (sizeof(FPW)/2);
- break; /* => 2 or 4 MB */
-
- case (FPW)INTEL_ID_28F160B3B:
- info->flash_id += FLASH_INTEL160B;
- info->sector_count = 39;
- info->size = 0x00200000 * (sizeof(FPW)/2);
- break; /* => 2 or 4 MB */
-
- case (FPW)INTEL_ID_28F320C3B:
- info->flash_id += FLASH_28F320C3B;
- info->sector_count = 71;
- info->size = 0x00400000 * (sizeof(FPW)/2);
- break; /* => 4 or 8 MB */
-
- case (FPW)INTEL_ID_28F320B3B:
- info->flash_id += FLASH_INTEL320B;
- info->sector_count = 71;
- info->size = 0x00400000 * (sizeof(FPW)/2);
- break; /* => 4 or 8 MB */
-
- case (FPW)INTEL_ID_28F640C3B:
- info->flash_id += FLASH_28F640C3B;
- info->sector_count = 135;
- info->size = 0x00800000 * (sizeof(FPW)/2);
- break; /* => 8 or 16 MB */
-
- case (FPW)INTEL_ID_28F640B3B:
- info->flash_id += FLASH_INTEL640B;
- info->sector_count = 135;
- info->size = 0x00800000 * (sizeof(FPW)/2);
- break; /* => 8 or 16 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* => no or unknown flash */
- }
-
- flash_get_offsets((ulong)addr, info);
-
- /* Put FLASH back in read mode */
- flash_reset(info);
-
- return (info->size);
-}
-
-#ifdef CONFIG_SYS_FLASH_PROTECTION
-/*-----------------------------------------------------------------------
- */
-
-static void flash_sync_real_protect(flash_info_t *info)
-{
- FPWV *addr = (FPWV *)(info->start[0]);
- FPWV *sect;
- int i;
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F800C3B:
- case FLASH_28F800C3T:
- case FLASH_28F160C3B:
- case FLASH_28F160C3T:
- case FLASH_28F320C3B:
- case FLASH_28F320C3T:
- case FLASH_28F640C3B:
- case FLASH_28F640C3T:
- /* check for protected sectors */
- *addr = (FPW)0x00900090;
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02.
- * D0 = 1 for each device if protected.
- * If at least one device is protected the sector is marked
- * protected, but mixed protected and unprotected devices
- * within a sector should never happen.
- */
- sect = (FPWV *)(info->start[i]);
- info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0;
- }
-
- /* Put FLASH back in read mode */
- flash_reset(info);
- break;
-
- case FLASH_AM640U:
- case FLASH_AM800T:
- default:
- /* no hardware protect that we support */
- break;
- }
-}
-#endif
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- FPWV *addr;
- int flag, prot, sect;
- int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
- ulong start, now, last;
- int rcode = 0;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_INTEL800B:
- case FLASH_INTEL160B:
- case FLASH_INTEL320B:
- case FLASH_INTEL640B:
- case FLASH_28F800C3B:
- case FLASH_28F160C3B:
- case FLASH_28F320C3B:
- case FLASH_28F640C3B:
- case FLASH_AM640U:
- case FLASH_AM800T:
- break;
- case FLASH_UNKNOWN:
- default:
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- start = get_timer(0);
- last = start;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
-
- if (info->protect[sect] != 0) /* protected, skip it */
- continue;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr = (FPWV *)(info->start[sect]);
- if (intel) {
- *addr = (FPW)0x00500050; /* clear status register */
- *addr = (FPW)0x00200020; /* erase setup */
- *addr = (FPW)0x00D000D0; /* erase confirm */
- }
- else {
- /* must be AMD style if not Intel */
- FPWV *base; /* first address in bank */
-
- base = (FPWV *)(info->start[0]);
- base[0x0555] = (FPW)0x00AA00AA; /* unlock */
- base[0x02AA] = (FPW)0x00550055; /* unlock */
- base[0x0555] = (FPW)0x00800080; /* erase mode */
- base[0x0555] = (FPW)0x00AA00AA; /* unlock */
- base[0x02AA] = (FPW)0x00550055; /* unlock */
- *addr = (FPW)0x00300030; /* erase sector */
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 50us for AMD, 80us for Intel.
- * Let's wait 1 ms.
- */
- udelay (1000);
-
- while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
-
- if (intel) {
- /* suspend erase */
- *addr = (FPW)0x00B000B0;
- }
-
- flash_reset(info); /* reset to read mode */
- rcode = 1; /* failed */
- break;
- }
-
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- flash_reset(info); /* reset to read mode */
- }
-
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
- int bytes; /* number of bytes to program in current word */
- int left; /* number of bytes left to program */
- int i, res;
-
- for (left = cnt, res = 0;
- left > 0 && res == 0;
- addr += sizeof(data), left -= sizeof(data) - bytes) {
-
- bytes = addr & (sizeof(data) - 1);
- addr &= ~(sizeof(data) - 1);
-
- /* combine source and destination data so can program
- * an entire word of 16 or 32 bits
- */
- for (i = 0; i < sizeof(data); i++) {
- data <<= 8;
- if (i < bytes || i - bytes >= left )
- data += *((uchar *)addr + i);
- else
- data += *src++;
- }
-
- /* write one word to the flash */
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- res = write_word_amd(info, (FPWV *)addr, data);
- break;
- case FLASH_MAN_INTEL:
- res = write_word_intel(info, (FPWV *)addr, data);
- break;
- default:
- /* unknown flash type, error! */
- printf ("missing or unknown FLASH type\n");
- res = 1; /* not really a timeout, but gives error */
- break;
- }
- }
-
- return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
-{
- ulong start;
- int flag;
- int res = 0; /* result, assume success */
- FPWV *base; /* first address in flash bank */
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest & data) != data) {
- return (2);
- }
-
-
- base = (FPWV *)(info->start[0]);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- base[0x0555] = (FPW)0x00AA00AA; /* unlock */
- base[0x02AA] = (FPW)0x00550055; /* unlock */
- base[0x0555] = (FPW)0x00A000A0; /* selects program mode */
-
- *dest = data; /* start programming the data */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer (0);
-
- /* data polling for D7 */
- while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *dest = (FPW)0x00F000F0; /* reset bank */
- res = 1;
- }
- }
-
- return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for Intel FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
-{
- ulong start;
- int flag;
- int res = 0; /* result, assume success */
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest & data) != data) {
- return (2);
- }
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- *dest = (FPW)0x00500050; /* clear status register */
- *dest = (FPW)0x00FF00FF; /* make sure in read mode */
- *dest = (FPW)0x00400040; /* program setup */
-
- *dest = data; /* start programming the data */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer (0);
-
- while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- *dest = (FPW)0x00B000B0; /* Suspend program */
- res = 1;
- }
- }
-
- if (res == 0 && (*dest & (FPW)0x00100010))
- res = 1; /* write failed, time out error is close enough */
-
- *dest = (FPW)0x00500050; /* clear status register */
- *dest = (FPW)0x00FF00FF; /* make sure in read mode */
-
- return (res);
-}
-
-#ifdef CONFIG_SYS_FLASH_PROTECTION
-/*-----------------------------------------------------------------------
- */
-int flash_real_protect (flash_info_t * info, long sector, int prot)
-{
- int rcode = 0; /* assume success */
- FPWV *addr; /* address of sector */
- FPW value;
-
- addr = (FPWV *) (info->start[sector]);
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F800C3B:
- case FLASH_28F800C3T:
- case FLASH_28F160C3B:
- case FLASH_28F160C3T:
- case FLASH_28F320C3B:
- case FLASH_28F320C3T:
- case FLASH_28F640C3B:
- case FLASH_28F640C3T:
- flash_reset (info); /* make sure in read mode */
- *addr = (FPW) 0x00600060L; /* lock command setup */
- if (prot)
- *addr = (FPW) 0x00010001L; /* lock sector */
- else
- *addr = (FPW) 0x00D000D0L; /* unlock sector */
- flash_reset (info); /* reset to read mode */
-
- /* now see if it really is locked/unlocked as requested */
- *addr = (FPW) 0x00900090;
- /* read sector protection at sector address, (A7 .. A0) = 0x02.
- * D0 = 1 for each device if protected.
- * If at least one device is protected the sector is marked
- * protected, but return failure. Mixed protected and
- * unprotected devices within a sector should never happen.
- */
- value = addr[2] & (FPW) 0x00010001;
- if (value == 0)
- info->protect[sector] = 0;
- else if (value == (FPW) 0x00010001)
- info->protect[sector] = 1;
- else {
- /* error, mixed protected and unprotected */
- rcode = 1;
- info->protect[sector] = 1;
- }
- if (info->protect[sector] != prot)
- rcode = 1; /* failed to protect/unprotect as requested */
-
- /* reload all protection bits from hardware for now */
- flash_sync_real_protect (info);
- break;
-
- case FLASH_AM640U:
- case FLASH_AM800T:
- default:
- /* no hardware protect that we support */
- info->protect[sector] = prot;
- break;
- }
-
- return rcode;
-}
-#endif
diff --git a/board/sixnet/fpgadata.c b/board/sixnet/fpgadata.c
deleted file mode 100644
index 2d3a7b3..0000000
--- a/board/sixnet/fpgadata.c
+++ /dev/null
@@ -1,1719 +0,0 @@
- 0xff, 0x87, 0xff, 0x88, 0x7f, 0xff, 0xf9, 0xff,
- 0xff, 0xf5, 0xff, 0x8f, 0xff, 0xf0, 0x8f, 0xf9,
- 0xff, 0xef, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xf0,
- 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0xf1, 0xcf,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef,
- 0x7f, 0x7b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x77, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0x86, 0xf6, 0xf0, 0xff,
- 0xf0, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x0f, 0x7f,
- 0xc1, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xf8, 0xff, 0xff, 0xf6, 0xf0, 0xff, 0xff,
- 0x7f, 0x8f, 0x7f, 0xf0, 0xff, 0x0f, 0x7f, 0xff,
- 0xff, 0xff, 0xff, 0x8f, 0x7f,
- 0xff, 0xf8, 0xf7, 0x8f, 0xcf, 0xf0, 0xf6, 0xff,
- 0xff, 0xef, 0xff, 0xfb, 0x7f, 0x2f, 0x1f, 0x71,
- 0xf5, 0xff, 0xff, 0xef, 0x7f,
- 0xff, 0x7f, 0xff, 0xf7, 0xf6, 0xfe, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xf7, 0x7f, 0x77, 0xf7, 0xff, 0xfb,
- 0x0f, 0xff, 0xf0, 0xff, 0xff, 0x7f, 0xff, 0xff,
- 0xfe, 0xff, 0x8f, 0x7f, 0xf1,
- 0xff, 0xff, 0xfa, 0xce, 0xff, 0xfd, 0xff, 0xff,
- 0x9f, 0xff, 0x8e, 0xff, 0xf0, 0xbf, 0x7f, 0xf5,
- 0xff, 0xef, 0x9f, 0xfd, 0x81,
- 0xff, 0xf9, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff,
- 0xff, 0xef, 0x9f, 0xfb, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0x7f,
- 0xff, 0x77, 0xfa, 0xb6, 0xff, 0x78, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xbf, 0xfd, 0x0f, 0x7f, 0xf1,
- 0xff, 0xff, 0xff, 0xff, 0x8f,
- 0xff, 0xf6, 0xf7, 0xf6, 0x7f, 0xbf, 0xff, 0xff,
- 0xff, 0xff, 0xef, 0xbf, 0xf2, 0x7f, 0xef, 0xff,
- 0xfe, 0xfb, 0xff, 0xef, 0xff,
- 0xff, 0xf7, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xbf,
- 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x7f, 0xff, 0xff,
- 0xff, 0xf7, 0xff, 0xf7, 0xcf, 0x8f, 0xff, 0xf0,
- 0xef, 0xf9, 0xfb, 0xff, 0xff, 0xff, 0x9f, 0x0f,
- 0x65, 0xe1, 0xfb, 0x7b, 0xf3,
- 0xff, 0xf7, 0xf6, 0xfe, 0xff, 0x8f, 0xf6, 0xe8,
- 0xf6, 0xf1, 0xff, 0xff, 0xff, 0xf9, 0xff, 0xff,
- 0x6f, 0x61, 0xf1, 0xfb, 0xff,
- 0xff, 0xde, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff,
- 0xf7, 0xbf, 0xff, 0xd4, 0x8f, 0x0f, 0x71, 0xc1,
- 0x6f, 0xd1, 0xeb, 0x5f, 0xfd,
- 0xff, 0x9f, 0xff, 0xfb, 0xff, 0x8f, 0x9f, 0xf7,
- 0x9f, 0xff, 0xf4, 0xb7, 0xfd, 0xff, 0xfe, 0x8f,
- 0xbf, 0x71, 0x1f, 0xff, 0x7f,
- 0xff, 0xfd, 0x87, 0x87, 0xf0, 0x70, 0x1f, 0xf7,
- 0xbf, 0xff, 0xff, 0xff, 0x8f, 0x0f, 0x71, 0x81,
- 0xbf, 0x3e, 0x7f, 0x7f, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, 0x7f, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xf1, 0xff, 0xff, 0xff, 0xff,
- 0xbf, 0xff, 0x07, 0xff, 0xf0, 0xff, 0xff, 0xff,
- 0xfe, 0xff, 0xff, 0xf7, 0x8d, 0x7f, 0xf1, 0xff,
- 0xff, 0x9f, 0x6f, 0xf1, 0xff,
- 0xbf, 0x71, 0x87, 0xfe, 0xf0, 0x8f, 0x8f, 0xf0,
- 0xfb, 0xcb, 0xff, 0xf0, 0x8f, 0x7f, 0xf1, 0x8f,
- 0x1e, 0xe1, 0x7e, 0x91, 0x7f,
- 0xbf, 0x1a, 0xff, 0x71, 0xff, 0x9f, 0x8f, 0xf6,
- 0xf8, 0xdf, 0xf7, 0xf4, 0xff, 0xff, 0xff, 0x8f,
- 0x1f, 0xf0, 0x7f, 0x97, 0xff,
- 0xbf, 0x97, 0xff, 0xfb, 0xbf, 0xdf, 0xff, 0xf7,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaf, 0xdf,
- 0xf9, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xdf, 0xff, 0xf1, 0xff,
- 0xff, 0x9f, 0xfc, 0xfb, 0xff, 0xf0, 0xfe, 0xff,
- 0xff, 0xff, 0x9d, 0xff, 0xf4, 0xcf, 0xff, 0x7f,
- 0xf7, 0xff, 0xff, 0xff, 0xcf,
- 0xff, 0x97, 0xff, 0xfa, 0xff, 0x8f, 0xf8, 0xf0,
- 0xff, 0xff, 0xff, 0xdf, 0xff, 0xfd, 0xff, 0x0f,
- 0x7f, 0xe1, 0xff, 0xf1, 0xff,
- 0xff, 0x83, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x7f, 0x6f, 0x7f, 0x77, 0x7d, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x8f, 0x6f, 0xf1,
- 0xff, 0xd7, 0xff, 0xfe, 0xff, 0xff, 0x9f, 0xfd,
- 0x78, 0xef, 0xff, 0xbf, 0xff, 0xf5, 0xff, 0xff,
- 0xbf, 0x0f, 0x79, 0xd1, 0xff,
- 0xff, 0xd2, 0xff, 0x72, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0xfe, 0x70, 0x9d, 0xff, 0xf4, 0xff, 0xfe,
- 0xff, 0xff, 0xff, 0xbf, 0x7f,
- 0xff, 0x07, 0xff, 0x78, 0xff, 0x9f, 0xff, 0xfe,
- 0xff, 0x77, 0x7f, 0x8f, 0x7f, 0xf0, 0xff, 0x8f,
- 0x7f, 0xe1, 0x0f, 0x71, 0xf1,
- 0xff, 0xfe, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff,
- 0x7f, 0xfd, 0xff, 0xba, 0x7f, 0xff, 0xff, 0xff,
- 0xff, 0xef, 0x7f, 0xa1, 0x7f,
- 0xff, 0xbd, 0x7f, 0xf7, 0xf9, 0xfd, 0xfb, 0xff,
- 0xff, 0x8f, 0xbf, 0xb7, 0x8f, 0xaf, 0xdf, 0xff,
- 0xff, 0xff, 0xff, 0x5f, 0xeb,
- 0xbf, 0xfd, 0xf8, 0xff, 0xff, 0xfb, 0xff, 0xfb,
- 0xff, 0xf7, 0xcf, 0xfb, 0xf0, 0xff, 0xff, 0xdf,
- 0xff, 0xff, 0xef, 0x7f, 0xab,
- 0xff, 0xfd, 0xfa, 0xbf, 0x8f, 0xbf, 0xca, 0xfe,
- 0xff, 0xff, 0xdf, 0x6f, 0xd4, 0xf6, 0x0f, 0x3f,
- 0x11, 0xf9, 0xff, 0x7f, 0x8b,
- 0xbf, 0xff, 0x8f, 0xff, 0xc0, 0xfb, 0xf5, 0xef,
- 0xf7, 0x7f, 0xff, 0xff, 0xfb, 0x7f, 0xff, 0x7f,
- 0xff, 0x6f, 0xff, 0xff, 0xff,
- 0xbf, 0x87, 0xbb, 0xf8, 0xfb, 0xcf, 0xfe, 0xfe,
- 0xff, 0xef, 0xff, 0xfb, 0x7f, 0xff, 0xff, 0x8f,
- 0xff, 0xe1, 0x7f, 0x7b, 0xff,
- 0xbf, 0x80, 0x89, 0x88, 0xb0, 0xf5, 0xf0, 0xff,
- 0xf7, 0xdf, 0xfe, 0x7c, 0x8f, 0x0f, 0x71, 0xe1,
- 0xff, 0xf1, 0xe5, 0x0e, 0x2b,
- 0xff, 0xff, 0xff, 0xbf, 0xff, 0xcf, 0xf5, 0x9f,
- 0xff, 0xff, 0xfe, 0xff, 0x8f, 0x7f, 0x71, 0x8f,
- 0xff, 0x91, 0x7f, 0xfb, 0xff,
- 0xff, 0x7f, 0x7f, 0xcf, 0x8a, 0xff, 0xf0, 0xff,
- 0x57, 0xfe, 0xfb, 0x8f, 0xff, 0xf0, 0xff, 0x7e,
- 0xff, 0xff, 0x9a, 0xff, 0xf1,
- 0xff, 0xff, 0xcf, 0xb7, 0xce, 0xff, 0xf4, 0xff,
- 0xff, 0x7f, 0xf7, 0xfb, 0xff, 0xfe, 0xff, 0x7f,
- 0xff, 0xfd, 0xfe, 0x75, 0xfd,
- 0xff, 0xef, 0xcf, 0xff, 0xf5, 0xff, 0xf5, 0xff,
- 0xf7, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x7f, 0xff,
- 0xcf, 0x7f, 0x31, 0x7f, 0xff,
- 0x3f, 0x78, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0x0f, 0x0f, 0xf1, 0xf1, 0xdf, 0xff, 0xff,
- 0xff, 0x9f, 0xff, 0x84, 0x0e,
- 0xff, 0xf8, 0x7f, 0xf7, 0x7f, 0xff, 0xff, 0x8f,
- 0x8f, 0x80, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff,
- 0xfe, 0x9f, 0x8e, 0x05, 0x71,
- 0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, 0xff,
- 0xff, 0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff,
- 0xfe, 0xff, 0xff, 0x8f, 0x0f,
- 0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x8e, 0x0f, 0x71,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x7f, 0xf7, 0xff, 0xff, 0x8f, 0xff,
- 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0x7f, 0xf0, 0xff, 0xff,
- 0x7f, 0xf8, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0x9f, 0xff, 0x8f, 0x7e,
- 0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xfe, 0xff, 0x8f,
- 0xff, 0x87, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xf0, 0xff, 0xff,
- 0xff, 0xff, 0x8e, 0x7f, 0xf1,
- 0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0x8f, 0x7f,
- 0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0x8f,
- 0xff, 0xf0, 0x0f, 0xff, 0x70, 0xff, 0x8f, 0x7e,
- 0xf1, 0xdf, 0xff, 0xfb, 0x8e,
- 0xff, 0x80, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xaf, 0x7f, 0x84, 0xff, 0xf1, 0xff, 0xfe,
- 0xff, 0xff, 0xfe, 0x8f, 0x7f,
- 0xff, 0x80, 0xff, 0xf8, 0xff, 0x7f, 0xff, 0xff,
- 0x7f, 0x8f, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0x8f, 0x7f,
- 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0x7f, 0xf0, 0xdf, 0xdf, 0xff, 0xdf, 0xff,
- 0xff, 0xff, 0x8f, 0x7f, 0xf1,
- 0xff, 0xfd, 0xff, 0xff, 0xff, 0x0f, 0xff, 0x80,
- 0xff, 0xf0, 0xff, 0xff, 0xdf, 0xff, 0xdf, 0x8e,
- 0x0f, 0x01, 0x71, 0xf1, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xdf, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xfe,
- 0xbf, 0x87, 0xf8, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x7f, 0xff, 0x8f, 0x8f, 0xd0, 0xf0, 0xdf, 0xfe,
- 0xff, 0xff, 0xff, 0xff, 0x8f,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd,
- 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x7f, 0xff, 0xff,
- 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd,
- 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xfe,
- 0xff, 0xdf, 0xff, 0xfb, 0xff,
- 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xfd,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xaf, 0xfe, 0xf5, 0xff, 0xff,
- 0xff, 0xff, 0x0f, 0x8f, 0xf0, 0x80, 0xff, 0xf0,
- 0xff, 0xff, 0xff, 0xff, 0x1f, 0xaf, 0x71, 0xa7,
- 0x6f, 0xf5, 0xfe, 0xff, 0xff,
- 0xff, 0x77, 0x79, 0x8f, 0xff, 0xf0, 0x8f, 0xff,
- 0x00, 0xff, 0xd0, 0x4f, 0x3d, 0xf0, 0xf7, 0xfd,
- 0x8f, 0x7f, 0x81, 0x7f, 0xd1,
- 0xff, 0xcd, 0xff, 0xff, 0x8f, 0x0f, 0x70, 0xf0,
- 0xff, 0x7f, 0x7f, 0xff, 0xff, 0xdb, 0x8d, 0x4b,
- 0x73, 0xf9, 0xff, 0xdf, 0xff,
- 0x3f, 0xfc, 0xff, 0x8f, 0xff, 0xf2, 0x8f, 0x8f,
- 0x70, 0x7a, 0x3f, 0xbc, 0xf7, 0xdb, 0xff, 0xf9,
- 0xff, 0xff, 0xff, 0xff, 0xee,
- 0xff, 0xe8, 0xf7, 0x8f, 0xfd, 0x80, 0xff, 0xf0,
- 0x9f, 0xa5, 0x7a, 0xf4, 0x6f, 0x3f, 0xcf, 0x07,
- 0x6a, 0xe1, 0xff, 0x8f, 0x7f,
- 0xff, 0xff, 0x77, 0xf1, 0x8f, 0x8f, 0xf0, 0xf0,
- 0xbf, 0xff, 0xe7, 0x7f, 0x8f, 0x24, 0x03, 0x77,
- 0xf3, 0xff, 0xfe, 0xff, 0xff,
- 0xbf, 0x9f, 0x77, 0x8b, 0xff, 0xf0, 0xff, 0xef,
- 0x7d, 0x7f, 0xff, 0x9f, 0xeb, 0x3d, 0xff, 0xf7,
- 0xff, 0xfb, 0xfe, 0xff, 0xdf,
- 0xff, 0xff, 0x77, 0xff, 0x8f, 0x8f, 0xf0, 0xf0,
- 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbb, 0x5d,
- 0xf5, 0xbb, 0xef, 0xff, 0xff,
- 0xff, 0x7f, 0x8f, 0x8f, 0xf0, 0xf8, 0xff, 0xff,
- 0xf7, 0x7f, 0xff, 0xff, 0xaf, 0xbf, 0x75, 0xb7,
- 0xff, 0xf7, 0xff, 0xff, 0xff,
- 0xff, 0x7f, 0x87, 0x7f, 0xf8, 0xff, 0xf7, 0xf7,
- 0x8f, 0xff, 0xf0, 0x7f, 0xf7, 0xff, 0xad, 0xff,
- 0xf7, 0xee, 0x9f, 0xff, 0xf5,
- 0xff, 0xf8, 0x07, 0xff, 0x80, 0x8f, 0x80, 0x80,
- 0xf0, 0x8f, 0x7f, 0x70, 0x4f, 0x0f, 0x79, 0xf1,
- 0xfd, 0xff, 0xef, 0x8f, 0x7f,
- 0xbf, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x8f, 0xff, 0xd0, 0xbf, 0xdb, 0xe5,
- 0x3b, 0xfe, 0xf7, 0xff, 0x8f,
- 0xff, 0xff, 0x8f, 0x77, 0x80, 0xff, 0xf0, 0xff,
- 0xff, 0x7f, 0xff, 0xff, 0xbd, 0xef, 0x07, 0x7f,
- 0xf1, 0xfe, 0xff, 0xfe, 0xff,
- 0x7f, 0x7f, 0xff, 0xf7, 0xf7, 0xff, 0xf7, 0x8f,
- 0xbf, 0x70, 0xf5, 0x7f, 0xff, 0xef, 0x3f, 0x7d,
- 0xf7, 0xff, 0xff, 0xfe, 0xfe,
- 0xff, 0x97, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff,
- 0x7e, 0xff, 0xff, 0x9f, 0xdf, 0xf7, 0x3b, 0xff,
- 0xf7, 0xff, 0x7f, 0xfe, 0xff,
- 0x3f, 0x78, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0x1f, 0x1f, 0xf1, 0xf1, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0x80, 0x0e,
- 0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0x8f,
- 0x9f, 0x80, 0xe1, 0xf1, 0xff, 0xff, 0xef, 0xff,
- 0xfe, 0x9f, 0x0e, 0x01, 0x71,
- 0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, 0xff,
- 0xff, 0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xef,
- 0xfe, 0xef, 0xff, 0x8f, 0x0f,
- 0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x9f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x8e, 0x0f, 0x71,
- 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xef, 0xff, 0xff, 0xef, 0xfe, 0xef,
- 0xef, 0xff, 0xff, 0xef, 0xff,
- 0xff, 0xf7, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff,
- 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0x7f, 0xe0, 0xff, 0xff,
- 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0x8f, 0x7e,
- 0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xef, 0xff, 0xff,
- 0xff, 0xff, 0xee, 0xef, 0x9f,
- 0xff, 0x07, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xe0, 0xff, 0xff,
- 0xff, 0xef, 0x8e, 0x7f, 0xf1,
- 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
- 0xef, 0xff, 0xfe, 0x8f, 0x7f,
- 0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0xdf,
- 0xff, 0xf0, 0x0f, 0xff, 0x70, 0xff, 0x8f, 0x7e,
- 0xe1, 0xdf, 0xff, 0xf7, 0x8e,
- 0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
- 0xff, 0x8f, 0x7f, 0x80, 0xff, 0xf1, 0xff, 0xff,
- 0xff, 0xef, 0xfe, 0x8f, 0x7f,
- 0xff, 0x80, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x7f, 0x8f, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xfe,
- 0xff, 0xff, 0xff, 0x8f, 0x7f,
- 0xff, 0x7f, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
- 0x1f, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x8f, 0x7e, 0xf1,
- 0xff, 0xff, 0xff, 0xf7, 0xff, 0x0f, 0x8f, 0x80,
- 0xf7, 0xe0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x9e,
- 0x6f, 0x91, 0x71, 0xf1, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
- 0xff, 0xff, 0xef, 0xff, 0xff,
- 0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff,
- 0xff, 0xff, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xdf, 0x8f,
- 0xff, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xfe,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xfe,
- 0xff, 0xef, 0xff, 0xd7, 0xff,
- 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0x8f, 0xff,
- 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xff,
- 0xff, 0xfe, 0xf9, 0xdf, 0xff,
- 0xff, 0xff, 0x8f, 0xbf, 0xf7, 0x9f, 0xf8, 0xf0,
- 0xff, 0xff, 0x77, 0xff, 0x0e, 0x1f, 0x61, 0x81,
- 0x7f, 0xf1, 0xfe, 0xff, 0xff,
- 0xff, 0x7f, 0xb9, 0xcf, 0xff, 0xff, 0x0f, 0xff,
- 0x00, 0xff, 0xd0, 0x7f, 0x75, 0x8b, 0x7f, 0xf1,
- 0x8f, 0x7f, 0x80, 0x7e, 0x91,
- 0xff, 0xbf, 0xdf, 0xff, 0xa7, 0x47, 0x70, 0xf7,
- 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0x0f,
- 0x61, 0xf1, 0xef, 0xff, 0xff,
- 0x7f, 0xfe, 0xef, 0x5f, 0xf7, 0xff, 0xff, 0xff,
- 0xff, 0xe7, 0xb7, 0xfc, 0xeb, 0x9f, 0x7f, 0xf1,
- 0x9f, 0x0f, 0x71, 0xf1, 0xee,
- 0xff, 0xf0, 0xf7, 0x3f, 0xef, 0x97, 0xf8, 0xe8,
- 0xff, 0x9f, 0x7f, 0xf0, 0x7f, 0x9f, 0x6f, 0x91,
- 0x7e, 0xf1, 0x9f, 0x8f, 0x57,
- 0xff, 0xff, 0x26, 0xb9, 0xb8, 0xff, 0xf0, 0xff,
- 0xff, 0xff, 0xf7, 0x7f, 0x6f, 0xf4, 0x9f, 0x1f,
- 0x71, 0xe1, 0xfe, 0x7f, 0xff,
- 0xbf, 0xff, 0x71, 0xbb, 0xe8, 0xff, 0xff, 0xf8,
- 0xbf, 0xff, 0xaf, 0xff, 0xf8, 0x9d, 0x6f, 0xf1,
- 0xbf, 0xff, 0xb7, 0xff, 0xbd,
- 0xbf, 0xff, 0xff, 0xdf, 0x97, 0xc7, 0xf7, 0xf0,
- 0xff, 0xff, 0x93, 0xff, 0xff, 0xef, 0xcf, 0x5f,
- 0xf1, 0xf7, 0xdf, 0xf5, 0x9f,
- 0xff, 0xff, 0x87, 0xbf, 0xe0, 0xbf, 0xf7, 0xff,
- 0xf7, 0x7f, 0xff, 0xff, 0x8f, 0x5f, 0x21, 0xb1,
- 0xff, 0x6d, 0xff, 0xef, 0xff,
- 0xff, 0xff, 0xd7, 0xff, 0xb8, 0xff, 0xff, 0xff,
- 0x3f, 0xef, 0xf0, 0x7f, 0xd7, 0x7f, 0xf1, 0xff,
- 0xef, 0xee, 0xbf, 0x7f, 0xf1,
- 0xff, 0xf8, 0x47, 0x0f, 0xc7, 0xf0, 0x7f, 0xf0,
- 0xf0, 0x90, 0x7f, 0x70, 0x8f, 0x2f, 0xc1, 0x0f,
- 0x11, 0x1f, 0xef, 0xaf, 0x7f,
- 0xbf, 0x7f, 0xf0, 0x9f, 0xe7, 0xf7, 0x38, 0xff,
- 0xff, 0xff, 0x8f, 0x7f, 0xf0, 0xaf, 0xff, 0xff,
- 0xbf, 0xfe, 0xfd, 0xdf, 0x8f,
- 0xff, 0xff, 0xbf, 0xf7, 0x8f, 0xff, 0xf7, 0xff,
- 0xeb, 0xff, 0xff, 0xff, 0x8d, 0x3f, 0x81, 0x7f,
- 0xd1, 0xfe, 0xdf, 0xfe, 0xff,
- 0x7f, 0xff, 0xff, 0xdf, 0xa8, 0xff, 0xf0, 0xff,
- 0xff, 0xf0, 0xf7, 0xff, 0xff, 0xff, 0xef, 0xef,
- 0xef, 0x9f, 0x7f, 0x7e, 0xfe,
- 0xff, 0xff, 0xef, 0xff, 0xa7, 0x77, 0xff, 0xff,
- 0xef, 0xff, 0xff, 0xdf, 0xff, 0xe7, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xfe, 0xff,
- 0x3f, 0x78, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xbf,
- 0xff, 0x0f, 0x0f, 0xf1, 0xe1, 0xff, 0xff, 0xef,
- 0xef, 0xff, 0xff, 0x8e, 0x0e,
- 0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0x8f,
- 0x8f, 0x80, 0xf1, 0xf1, 0xef, 0xaf, 0xaf, 0xff,
- 0xee, 0xdf, 0x0e, 0x01, 0x71,
- 0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, 0xff,
- 0xef, 0x8f, 0x9f, 0xf1, 0xe1, 0xff, 0xaf, 0xef,
- 0xfe, 0xff, 0xff, 0x8f, 0x0f,
- 0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x9f, 0x9f, 0xf1, 0xf1, 0xef, 0xff, 0xaf, 0xff,
- 0xff, 0xff, 0x8e, 0x0f, 0x71,
- 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xef, 0xbf, 0xef, 0xff,
- 0xef, 0xbf, 0xff, 0xef, 0xff,
- 0xff, 0xf7, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff,
- 0xf0, 0xff, 0xff, 0xff, 0xef, 0xff, 0xef, 0xfe,
- 0xcf, 0x3f, 0xf0, 0xff, 0xff,
- 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbf,
- 0xff, 0x88, 0xff, 0xf0, 0xff, 0xff, 0xef, 0xfe,
- 0xff, 0xff, 0xff, 0x8f, 0x6e,
- 0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x8f, 0xff, 0xe0, 0xff, 0xef, 0xff,
- 0xff, 0xff, 0xee, 0xef, 0x9f,
- 0xff, 0x8f, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xa0, 0xff, 0xfe,
- 0xff, 0xbf, 0x8e, 0x6f, 0xf1,
- 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0x8f, 0x6f,
- 0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0xcf,
- 0xff, 0xb0, 0x0f, 0xaf, 0x70, 0xff, 0x8f, 0x7e,
- 0xf1, 0xff, 0xff, 0xf1, 0x9e,
- 0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
- 0xef, 0x8f, 0x7f, 0x90, 0xff, 0xf1, 0xff, 0xff,
- 0xff, 0xaf, 0xfe, 0x8f, 0x7f,
- 0xff, 0x80, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x3f, 0xdf, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xfe,
- 0xff, 0xff, 0xff, 0x8f, 0x7f,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x9f, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xbf, 0x7e, 0xf1,
- 0xff, 0xff, 0x7f, 0xff, 0xff, 0x0f, 0xaf, 0x80,
- 0xf0, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xde,
- 0x0f, 0x91, 0x7f, 0xf1, 0xff,
- 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x7f, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xff, 0xfe,
- 0xff, 0xff, 0xbf, 0xff, 0xfb,
- 0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff,
- 0xff, 0xdf, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0x8f,
- 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x7f, 0xff, 0xff, 0xdf, 0xbf, 0xff, 0xef, 0xff,
- 0xff, 0xaf, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbf, 0xfe,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xdf, 0xff, 0xff, 0xbf, 0xff, 0xff, 0xfe,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xaf, 0xff,
- 0xf0, 0xdf, 0xff, 0xff, 0xff, 0xff, 0xbf, 0xff,
- 0xdf, 0xfe, 0xfe, 0xff, 0xff,
- 0xff, 0xff, 0x0f, 0x8f, 0xf0, 0x8f, 0xff, 0xf0,
- 0xf9, 0xff, 0xf7, 0xff, 0x0f, 0x5f, 0x29, 0x89,
- 0x77, 0xf1, 0xfa, 0xff, 0xde,
- 0xff, 0xc3, 0x3f, 0x4b, 0x7f, 0xe9, 0x0f, 0xff,
- 0x00, 0xff, 0x90, 0x0f, 0xd7, 0xff, 0x7f, 0xf9,
- 0x8f, 0x7f, 0x81, 0x7f, 0x81,
- 0xff, 0xff, 0xfb, 0x7d, 0x80, 0x46, 0x76, 0xf0,
- 0xff, 0xff, 0x6f, 0xff, 0xff, 0xad, 0xcf, 0x3f,
- 0x71, 0xf9, 0xff, 0xff, 0xff,
- 0x3f, 0xba, 0xff, 0xc7, 0xf7, 0xb9, 0xcf, 0xde,
- 0x77, 0xb7, 0x77, 0xfe, 0xff, 0xbf, 0x6f, 0xf9,
- 0xff, 0x7e, 0x79, 0xb9, 0xfe,
- 0xff, 0xe4, 0xf7, 0x8f, 0xfe, 0x07, 0xfe, 0xf8,
- 0xff, 0x89, 0x7f, 0xe8, 0x7f, 0xd7, 0x7f, 0x99,
- 0x76, 0xf1, 0xff, 0x0f, 0x7b,
- 0xbf, 0xff, 0xb6, 0xb9, 0x8f, 0xdf, 0xf6, 0xff,
- 0xff, 0xf7, 0xff, 0xff, 0x8f, 0xdd, 0x87, 0x7f,
- 0x71, 0xf1, 0xfe, 0xff, 0xff,
- 0xff, 0x7f, 0xf1, 0x8a, 0xff, 0xff, 0xff, 0xff,
- 0xbf, 0xff, 0xcf, 0xfb, 0xe8, 0x9d, 0x77, 0xa9,
- 0xff, 0x77, 0xda, 0x7f, 0xff,
- 0xbf, 0xff, 0xf7, 0xf7, 0x86, 0xe5, 0xf0, 0xe0,
- 0xff, 0xff, 0xbf, 0xff, 0xff, 0xef, 0x8f, 0x7f,
- 0xbd, 0xff, 0xff, 0xff, 0x8f,
- 0xff, 0xef, 0x86, 0x8f, 0xf0, 0xff, 0xf6, 0x9f,
- 0xff, 0x7f, 0xff, 0xff, 0xcf, 0x1f, 0x71, 0xdd,
- 0x7f, 0xe1, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xc7, 0xf7, 0xb9, 0xff, 0xff, 0xfa,
- 0x3f, 0xef, 0xf0, 0xff, 0xef, 0x7f, 0xd5, 0xff,
- 0xfb, 0xff, 0xf7, 0x6e, 0xf1,
- 0xff, 0xfc, 0xc7, 0xbf, 0xc8, 0xc0, 0x59, 0xff,
- 0xdf, 0xff, 0x7b, 0xf0, 0xa7, 0x1f, 0xa9, 0x77,
- 0x79, 0x71, 0x11, 0xff, 0x79,
- 0xbf, 0xfb, 0x70, 0xbf, 0xff, 0xf9, 0x37, 0xbe,
- 0xff, 0xff, 0x8f, 0x7f, 0xf4, 0x9f, 0xff, 0xff,
- 0xd7, 0x7f, 0xff, 0xff, 0xaf,
- 0xff, 0xff, 0x9e, 0xf7, 0x9f, 0xfe, 0xe4, 0xff,
- 0xcf, 0xcf, 0xff, 0xff, 0xdf, 0x7f, 0x8d, 0x7f,
- 0xf9, 0xfa, 0xdf, 0x9f, 0xef,
- 0x7f, 0xef, 0xff, 0xff, 0xbe, 0xfd, 0xd2, 0xdf,
- 0xff, 0x7e, 0xf7, 0xff, 0xff, 0xab, 0x97, 0xef,
- 0xf3, 0xfe, 0x7f, 0x71, 0xfe,
- 0xff, 0x9f, 0xff, 0xff, 0xb6, 0xfb, 0xf7, 0xff,
- 0xff, 0xf7, 0xff, 0xbf, 0xff, 0xb7, 0xdb, 0xff,
- 0xbb, 0xef, 0xff, 0xff, 0xff,
- 0x3f, 0x68, 0xfe, 0xfd, 0xfb, 0xff, 0xff, 0xef,
- 0xf1, 0x1e, 0x1b, 0xf1, 0xf5, 0xff, 0xff, 0xff,
- 0xff, 0x9f, 0xfb, 0x9a, 0x36,
- 0xff, 0xfc, 0x7d, 0xff, 0x73, 0xf7, 0xff, 0xaf,
- 0x9f, 0x94, 0xfd, 0xf5, 0xff, 0xf7, 0xff, 0xfb,
- 0xfe, 0xef, 0x3e, 0x07, 0x4d,
- 0xbf, 0xe8, 0xf8, 0xff, 0x7f, 0xff, 0xf7, 0xf7,
- 0xf1, 0x8f, 0xaf, 0xd1, 0xf7, 0xf9, 0xfd, 0xff,
- 0xf8, 0xdf, 0xfb, 0x8f, 0x2f,
- 0xff, 0xf8, 0x7f, 0xff, 0xf7, 0xf7, 0xff, 0xff,
- 0xa7, 0xaf, 0xf7, 0xf3, 0xdf, 0xff, 0xfd, 0xff,
- 0xfd, 0xff, 0xae, 0x0f, 0x71,
- 0xff, 0xff, 0xff, 0xf9, 0xff, 0xff, 0xf3, 0xf3,
- 0xff, 0xf3, 0xff, 0xf7, 0xfb, 0xf3, 0xff, 0xff,
- 0xff, 0xeb, 0xff, 0xf3, 0xdb,
- 0xff, 0xeb, 0x7b, 0xfb, 0xf7, 0xff, 0x8b, 0xf7,
- 0xfc, 0xf7, 0xfb, 0xff, 0xfb, 0xf3, 0xff, 0xff,
- 0x8b, 0x7f, 0xd4, 0xfb, 0xff,
- 0x7f, 0xec, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xf7,
- 0xff, 0x8e, 0xff, 0xf8, 0xf7, 0xfb, 0xfd, 0xff,
- 0xfd, 0x9f, 0xf7, 0x9f, 0x7e,
- 0xbf, 0xfb, 0x7c, 0xff, 0xf7, 0xff, 0xff, 0xfb,
- 0xfb, 0xf1, 0x8f, 0xf3, 0xdc, 0xf7, 0xfd, 0xff,
- 0xe9, 0xeb, 0xef, 0xc3, 0xb7,
- 0xff, 0x07, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xf7,
- 0x8f, 0xff, 0xf4, 0x8f, 0xfb, 0xfc, 0xff, 0xef,
- 0xff, 0xf7, 0x8f, 0x7f, 0xd1,
- 0xff, 0xfa, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff,
- 0xf3, 0x89, 0xef, 0xf8, 0xff, 0xf7, 0xff, 0xef,
- 0xef, 0xf7, 0xf3, 0xab, 0x7f,
- 0x3f, 0xf9, 0x7e, 0xf9, 0x8f, 0x7f, 0xf0, 0xef,
- 0xff, 0xfc, 0x1b, 0xff, 0x7c, 0xff, 0x8f, 0x6e,
- 0xf1, 0xf7, 0x73, 0xff, 0xa6,
- 0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
- 0xf9, 0x8f, 0x7f, 0x84, 0xff, 0xf1, 0xff, 0xff,
- 0xff, 0xff, 0xfa, 0x8f, 0x7f,
- 0xff, 0x96, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff,
- 0x57, 0xaf, 0xfb, 0x85, 0x7f, 0xf4, 0xff, 0xfe,
- 0xef, 0xff, 0xef, 0xbf, 0x53,
- 0xff, 0x7d, 0xff, 0xff, 0xe3, 0xff, 0xff, 0xff,
- 0x97, 0x71, 0xf8, 0xff, 0xff, 0xff, 0xdb, 0xef,
- 0xef, 0xe7, 0x97, 0x72, 0xfd,
- 0xff, 0xff, 0xff, 0xff, 0xf3, 0x0f, 0xe3, 0x86,
- 0xf0, 0xf4, 0xfb, 0xff, 0xdf, 0xff, 0xfb, 0x8e,
- 0x0b, 0xa5, 0x72, 0xf9, 0xff,
- 0xff, 0xfb, 0xff, 0xff, 0xf7, 0xff, 0xf3, 0xff,
- 0xf7, 0xff, 0xf3, 0xff, 0xff, 0xff, 0xfb, 0xee,
- 0xfb, 0xff, 0xef, 0xff, 0xff,
- 0xbf, 0x82, 0xf8, 0xf8, 0xf7, 0x7f, 0xf7, 0xff,
- 0xff, 0xef, 0x87, 0x87, 0xf0, 0xf0, 0xfb, 0xff,
- 0xfb, 0xf7, 0xef, 0xef, 0x87,
- 0xff, 0xf6, 0xff, 0xfa, 0xf1, 0xef, 0xf3, 0xf7,
- 0x7f, 0xff, 0xff, 0xef, 0xff, 0xf7, 0xff, 0xff,
- 0xfb, 0xf7, 0xff, 0xfe, 0xff,
- 0xff, 0xf7, 0xfb, 0xf2, 0xf3, 0xff, 0xf1, 0xf7,
- 0xff, 0xef, 0xf7, 0xef, 0xf7, 0xf7, 0xff, 0xfe,
- 0xff, 0xff, 0xef, 0xff, 0xe7,
- 0xff, 0xfb, 0xfb, 0xff, 0xf5, 0xef, 0xf7, 0xff,
- 0xff, 0xff, 0xff, 0xf7, 0x77, 0xff, 0xff, 0xfe,
- 0xff, 0xf7, 0xff, 0xef, 0xef,
- 0xff, 0xff, 0xff, 0xff, 0xf7, 0xef, 0xe5, 0xff,
- 0xfe, 0x61, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x9f, 0xef, 0xef, 0xf3, 0xf7,
- 0xff, 0xff, 0x0f, 0x9f, 0xfa, 0x87, 0xff, 0xf6,
- 0xeb, 0xff, 0xff, 0xef, 0x0f, 0x6f, 0xfd, 0x0d,
- 0x53, 0xf1, 0xf3, 0xff, 0xff,
- 0xbf, 0x1b, 0x7f, 0x96, 0xfe, 0xff, 0x8f, 0xfb,
- 0x00, 0xff, 0xb0, 0x17, 0x7c, 0x8f, 0xff, 0xfd,
- 0x8f, 0x7f, 0x81, 0x7e, 0xf1,
- 0xff, 0xfd, 0xed, 0xee, 0x9e, 0x0b, 0x79, 0xff,
- 0xfb, 0x77, 0x5b, 0xff, 0x9f, 0xff, 0x4f, 0x0f,
- 0x71, 0xf0, 0xdb, 0xff, 0xf7,
- 0x7f, 0xe7, 0xef, 0x18, 0xff, 0xff, 0x9d, 0x8e,
- 0x67, 0xbf, 0x4f, 0xff, 0xff, 0xae, 0xff, 0xf1,
- 0xeb, 0xef, 0xfd, 0xad, 0xf6,
- 0xff, 0xfc, 0xf7, 0x1f, 0xff, 0x9f, 0xfb, 0xfc,
- 0xff, 0x8f, 0x77, 0xec, 0x5f, 0x6f, 0xdf, 0x25,
- 0x7e, 0xd9, 0xe6, 0x97, 0x3f,
- 0xff, 0xf7, 0x67, 0xec, 0x92, 0xbe, 0xf1, 0xfb,
- 0xff, 0x7f, 0xdf, 0x7b, 0x5e, 0x7d, 0xe7, 0x5f,
- 0xf1, 0xf1, 0xfb, 0xff, 0xf7,
- 0xbf, 0xf7, 0x71, 0x9a, 0xfd, 0xff, 0xf7, 0xfb,
- 0x5f, 0x7f, 0xaf, 0xdf, 0xf9, 0xe7, 0x77, 0xdd,
- 0x6f, 0xf7, 0xbb, 0xff, 0x8b,
- 0xbf, 0xff, 0x77, 0xff, 0x93, 0xfe, 0xf8, 0xfe,
- 0xbf, 0xfe, 0xbf, 0xff, 0xff, 0xbf, 0xab, 0x7f,
- 0xfd, 0xff, 0xcf, 0x67, 0xff,
- 0xff, 0x7f, 0x07, 0x9f, 0xe4, 0xdb, 0xff, 0xf1,
- 0xf7, 0x7f, 0xff, 0xff, 0x8f, 0x6f, 0xd1, 0x6d,
- 0x73, 0xff, 0xff, 0xfb, 0xff,
- 0xff, 0x6f, 0x9f, 0x7b, 0xfd, 0xff, 0xf6, 0xfd,
- 0x27, 0xff, 0xfc, 0xff, 0xaf, 0xff, 0xfd, 0xfe,
- 0x7f, 0xdf, 0xff, 0x7f, 0xef,
- 0xff, 0xfe, 0x81, 0xe7, 0x93, 0x91, 0x83, 0x85,
- 0xef, 0x8f, 0x7f, 0x74, 0x8d, 0x1b, 0x2d, 0xe2,
- 0xcd, 0xe5, 0xb5, 0x9f, 0x77,
- 0xbf, 0x7f, 0xe4, 0xef, 0xff, 0xf7, 0xdb, 0xfd,
- 0x7f, 0xfe, 0xab, 0x7f, 0xfc, 0xbf, 0xff, 0xde,
- 0x77, 0xfb, 0xdf, 0xef, 0xbf,
- 0xff, 0xff, 0x1e, 0x7f, 0x8f, 0xff, 0x92, 0xf3,
- 0xdf, 0x7b, 0xff, 0x7b, 0xff, 0xdb, 0x3d, 0x5f,
- 0xf9, 0xf6, 0xff, 0xf2, 0xf7,
- 0x7f, 0x7f, 0xff, 0xff, 0xef, 0xd2, 0xf0, 0xb7,
- 0xfb, 0x7f, 0xfc, 0x77, 0xd7, 0x3f, 0xc7, 0x7f,
- 0xf3, 0xe7, 0xff, 0xfd, 0xfe,
- 0xff, 0xff, 0xef, 0x7b, 0xef, 0xf5, 0xda, 0xff,
- 0x7c, 0xff, 0xff, 0xff, 0xff, 0x7b, 0xeb, 0xfb,
- 0xef, 0xff, 0xef, 0xff, 0xff,
- 0x3f, 0x60, 0xfc, 0xfb, 0xf7, 0xff, 0xff, 0xff,
- 0xfb, 0x00, 0x0f, 0xf1, 0xf5, 0xfb, 0xff, 0xff,
- 0xff, 0xff, 0xf3, 0x86, 0x3e,
- 0xff, 0xf8, 0x7f, 0xfb, 0x73, 0xff, 0xff, 0x9f,
- 0xab, 0x8c, 0xf5, 0xd1, 0xff, 0xfb, 0xff, 0xff,
- 0xfe, 0xeb, 0x36, 0x0d, 0x49,
- 0xbf, 0xf0, 0xfc, 0xfb, 0x73, 0xff, 0xf3, 0xff,
- 0xff, 0xab, 0xa7, 0xf1, 0xf9, 0xff, 0xf7, 0xdf,
- 0xfa, 0xfb, 0xff, 0xa7, 0x3f,
- 0xff, 0xf8, 0x7f, 0xff, 0xfb, 0xfb, 0xfb, 0xff,
- 0xaf, 0x8f, 0xf9, 0xf9, 0xdf, 0xdf, 0xf7, 0xdb,
- 0xff, 0xff, 0xba, 0x2f, 0x69,
- 0xff, 0xe7, 0xfb, 0xfb, 0xff, 0xff, 0xff, 0xfb,
- 0xff, 0xfb, 0xd7, 0xff, 0xdf, 0xf7, 0xd7, 0xdf,
- 0xf3, 0xdb, 0xff, 0xdb, 0xff,
- 0xff, 0xe3, 0x7b, 0xf9, 0xfb, 0xff, 0x8f, 0xfb,
- 0xf8, 0xff, 0xff, 0xef, 0xdf, 0xf3, 0xd7, 0xdf,
- 0xa3, 0x5b, 0xc4, 0xfb, 0xef,
- 0x7f, 0xe0, 0xfd, 0xfb, 0xfb, 0xff, 0xfb, 0xeb,
- 0xff, 0x8c, 0xeb, 0xf0, 0xd3, 0xff, 0xd7, 0xff,
- 0xf7, 0xbb, 0x7f, 0x8f, 0x7e,
- 0xbf, 0xfb, 0x6c, 0xfb, 0xfb, 0xff, 0xfb, 0xff,
- 0xfb, 0xf3, 0x8b, 0xf3, 0xf4, 0xf7, 0xd7, 0xff,
- 0xf3, 0xff, 0xfe, 0xc2, 0xbf,
- 0xff, 0x87, 0x7f, 0xfa, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xf4, 0xff, 0xdf,
- 0xff, 0xfb, 0x8f, 0x7f, 0xc5,
- 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb,
- 0xf3, 0x87, 0xef, 0xfc, 0xfd, 0xfb, 0xff, 0xff,
- 0xdf, 0xff, 0xfb, 0xab, 0x7f,
- 0x3f, 0xf3, 0xfa, 0xf9, 0x8f, 0x7f, 0xf0, 0xeb,
- 0xfb, 0xec, 0x1f, 0xcf, 0x7e, 0xff, 0x8f, 0x5e,
- 0xd1, 0xbf, 0xff, 0xfe, 0xaa,
- 0xff, 0x80, 0x7d, 0xf8, 0xff, 0x7f, 0xff, 0xff,
- 0xf7, 0x8f, 0x5f, 0x8c, 0xff, 0xf1, 0xff, 0xff,
- 0xff, 0xff, 0xfa, 0x9f, 0x6f,
- 0xff, 0x9a, 0xfd, 0xfc, 0xff, 0xff, 0xff, 0xff,
- 0x6f, 0xbf, 0xd7, 0x89, 0x7f, 0xf4, 0xff, 0xfe,
- 0xff, 0xff, 0xdf, 0xbf, 0x6f,
- 0xff, 0xfd, 0xff, 0xff, 0xef, 0xff, 0xfb, 0xff,
- 0x2b, 0x73, 0xf0, 0xf3, 0xff, 0xff, 0xc3, 0xff,
- 0xff, 0xff, 0x8b, 0x62, 0xfd,
- 0xff, 0xef, 0xff, 0xff, 0xfb, 0x0f, 0x8b, 0x8e,
- 0xf0, 0xdc, 0xf7, 0xff, 0xff, 0xff, 0xfb, 0xae,
- 0x43, 0xa9, 0x73, 0xf9, 0xfb,
- 0x7f, 0xf9, 0xff, 0xff, 0xfd, 0xff, 0xf9, 0xff,
- 0xfb, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xf3, 0xfe,
- 0xf3, 0xff, 0xff, 0xff, 0xff,
- 0xbf, 0x87, 0xf8, 0xf8, 0xf9, 0x7f, 0xf9, 0xff,
- 0xff, 0x7f, 0x8f, 0x8f, 0xf0, 0xf0, 0xf3, 0xff,
- 0xf3, 0xfb, 0xff, 0xff, 0x8f,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf9, 0xff,
- 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xff,
- 0xfb, 0xef, 0xff, 0xff, 0xff,
- 0xff, 0x7f, 0xff, 0xf7, 0xf9, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xfe,
- 0xf3, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, 0xf1, 0xff,
- 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xfe,
- 0xfb, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x7f, 0xff, 0xf1, 0xff, 0x85, 0xff,
- 0xfe, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xff,
- 0xf3, 0xde, 0xff, 0xf3, 0xff,
- 0xbf, 0xff, 0x0f, 0x9f, 0xfa, 0x9f, 0xeb, 0xf2,
- 0xe7, 0xff, 0x7b, 0xff, 0x4f, 0x73, 0x31, 0x81,
- 0x5f, 0xf1, 0xfe, 0xff, 0xbf,
- 0xff, 0xaf, 0x7f, 0x94, 0xfb, 0xfe, 0x8f, 0xff,
- 0x00, 0xff, 0xf0, 0xef, 0xef, 0x5f, 0xfb, 0xf5,
- 0x8f, 0x7f, 0x81, 0x5e, 0xf1,
- 0xff, 0xf9, 0xff, 0xef, 0x86, 0x0f, 0x71, 0xf6,
- 0xff, 0x7f, 0x7f, 0x97, 0xcf, 0xfd, 0xbf, 0x5f,
- 0xf9, 0xf1, 0xf3, 0xff, 0xff,
- 0x3f, 0xdb, 0xed, 0x1e, 0xff, 0xf6, 0x95, 0x9a,
- 0x6f, 0x3d, 0xff, 0xf8, 0xfb, 0xdf, 0xf7, 0xfd,
- 0xfb, 0xf7, 0xfd, 0xed, 0xde,
- 0x7f, 0xf0, 0xf7, 0x87, 0x7f, 0x9b, 0xff, 0xec,
- 0x9f, 0xbf, 0x7f, 0xcd, 0x7f, 0xf7, 0x3b, 0xad,
- 0x7e, 0xf8, 0xff, 0xbb, 0x79,
- 0xff, 0xff, 0xe3, 0x7c, 0x01, 0x8d, 0xf5, 0xfb,
- 0xe7, 0xf7, 0xff, 0xff, 0x9e, 0x7d, 0x0f, 0x7f,
- 0xf1, 0xcd, 0xfe, 0xf7, 0xff,
- 0x3f, 0xd7, 0xf4, 0x9a, 0xf7, 0xed, 0xff, 0xf3,
- 0xb7, 0xff, 0xef, 0xff, 0xbd, 0xe7, 0x5f, 0xbd,
- 0xff, 0xef, 0xfe, 0x7f, 0xf1,
- 0x3f, 0xff, 0xe7, 0xff, 0xcf, 0xfa, 0xf8, 0xff,
- 0xff, 0xdf, 0xbf, 0xfe, 0xdf, 0xff, 0xd3, 0x1f,
- 0xfd, 0xef, 0x7f, 0xff, 0xcf,
- 0x7f, 0xff, 0x93, 0xdf, 0xf0, 0xef, 0xf3, 0xd4,
- 0x77, 0x6f, 0xff, 0xff, 0xbf, 0x7f, 0x7d, 0xfd,
- 0x7f, 0x7d, 0xff, 0xff, 0xf7,
- 0xff, 0xf7, 0xdf, 0xfb, 0xbc, 0xef, 0xff, 0xfd,
- 0xff, 0xff, 0xfc, 0x7f, 0xb7, 0xff, 0xfd, 0x5f,
- 0xcf, 0xff, 0xef, 0x7f, 0xfd,
- 0xff, 0xee, 0x87, 0xef, 0x92, 0xf0, 0x7e, 0xe5,
- 0xbf, 0x8f, 0x7f, 0x60, 0xd9, 0xdb, 0x71, 0xb3,
- 0x2d, 0x49, 0x6c, 0x29, 0x7f,
- 0xbf, 0xff, 0xe4, 0x6f, 0xf3, 0xfa, 0x57, 0xfd,
- 0xff, 0xfe, 0xb7, 0x7f, 0xfc, 0xff, 0x73, 0xdf,
- 0xf3, 0x7f, 0xfd, 0xff, 0xbf,
- 0xff, 0xef, 0x8b, 0x7f, 0x8f, 0xff, 0xf2, 0xff,
- 0xff, 0xf7, 0xfb, 0xff, 0xff, 0xdf, 0xed, 0xef,
- 0xf1, 0xf7, 0xfd, 0xdf, 0xf7,
- 0xff, 0xff, 0xff, 0xf7, 0xe7, 0xe6, 0xf1, 0xff,
- 0xdf, 0xfb, 0xe9, 0xfe, 0xbf, 0xff, 0xbf, 0x5f,
- 0xff, 0xbf, 0x0e, 0x75, 0xfa,
- 0xff, 0xff, 0xff, 0x6f, 0xfb, 0xf9, 0xff, 0xff,
- 0xf3, 0xff, 0xfb, 0xbf, 0xef, 0xff, 0xf3, 0x7f,
- 0xff, 0xff, 0xff, 0xfb, 0xff,
- 0xff, 0x38, 0xf8, 0xf7, 0xff, 0xff, 0xdf, 0x9f,
- 0xf7, 0x0b, 0x0f, 0xf5, 0xf5, 0xff, 0xff, 0xff,
- 0xbf, 0xf7, 0xf3, 0x8e, 0x0e,
- 0xbf, 0xe8, 0x6f, 0xef, 0x7f, 0xff, 0xdf, 0xdf,
- 0xef, 0x88, 0xf5, 0x91, 0xfb, 0xff, 0xff, 0xbf,
- 0xfe, 0xbf, 0xa6, 0x81, 0x71,
- 0xff, 0xf0, 0xf8, 0xff, 0x67, 0xef, 0xff, 0xb7,
- 0xf7, 0x8f, 0x2f, 0xd1, 0x41, 0xff, 0xcf, 0x5f,
- 0xfe, 0xff, 0x7b, 0x8f, 0x9f,
- 0xff, 0xf8, 0x6f, 0xef, 0xf7, 0xe7, 0xff, 0xff,
- 0xbf, 0x8f, 0xd1, 0xf1, 0xcf, 0xdf, 0xcf, 0xdf,
- 0xff, 0xff, 0x9f, 0x8f, 0xe1,
- 0xff, 0xe7, 0xff, 0xf7, 0xe7, 0x6f, 0xf7, 0xe7,
- 0xe7, 0x77, 0xef, 0xef, 0x6f, 0xff, 0xff, 0xdf,
- 0xff, 0xdf, 0xdf, 0xff, 0xff,
- 0xff, 0xa7, 0x6f, 0xff, 0xf7, 0xef, 0x97, 0xe7,
- 0xf0, 0xef, 0x7f, 0xaf, 0x4f, 0xff, 0xff, 0xdf,
- 0xbf, 0x5f, 0xe0, 0x7f, 0xef,
- 0x7f, 0xa0, 0xef, 0xff, 0xe7, 0xff, 0xf7, 0xf7,
- 0xff, 0x8b, 0xbf, 0xf8, 0xdf, 0xff, 0xcf, 0x7e,
- 0xff, 0xdf, 0x7f, 0x8e, 0x5f,
- 0xff, 0xff, 0x38, 0xff, 0xf7, 0xff, 0xf7, 0xf7,
- 0xf7, 0xf7, 0x8f, 0xf7, 0xf8, 0xf7, 0xcf, 0xff,
- 0xff, 0xff, 0xfe, 0xcb, 0x3f,
- 0x3f, 0x9f, 0x7f, 0xf8, 0xff, 0xef, 0xff, 0xff,
- 0x8f, 0xff, 0xf0, 0xaf, 0xff, 0xf0, 0xff, 0xdf,
- 0xff, 0xff, 0xae, 0x7f, 0xc1,
- 0x7f, 0xf0, 0x7f, 0xff, 0xff, 0xff, 0xef, 0xff,
- 0xf7, 0xbf, 0xbf, 0xd0, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0xff, 0xff, 0x9b, 0xff,
- 0x7f, 0xcf, 0xf8, 0xff, 0x8f, 0x6f, 0xe0, 0xd7,
- 0xf7, 0xf7, 0xff, 0xfe, 0xf0, 0xfe, 0x8f, 0x5e,
- 0xd1, 0xff, 0xdf, 0xdf, 0xbe,
- 0xff, 0x84, 0x7f, 0xf8, 0xff, 0x7f, 0xdf, 0xff,
- 0xff, 0xaf, 0x7f, 0x81, 0x7f, 0xf5, 0xff, 0xff,
- 0xff, 0xff, 0xfa, 0x9f, 0x3f,
- 0xff, 0xd8, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x7f, 0x0f, 0xff, 0x85, 0x7f, 0xf0, 0xff, 0xfe,
- 0xbf, 0xff, 0xdf, 0x6f, 0xbf,
- 0xff, 0xff, 0xff, 0xff, 0xaf, 0xff, 0xf7, 0xdf,
- 0xf7, 0x47, 0xf4, 0xff, 0xef, 0xff, 0xdf, 0x7f,
- 0xff, 0xbf, 0xcf, 0x5a, 0xf1,
- 0xff, 0xbf, 0xbf, 0xff, 0xff, 0x3f, 0x8f, 0xc0,
- 0xf3, 0xd1, 0xff, 0xfb, 0xef, 0xff, 0xdf, 0xbe,
- 0x0f, 0x25, 0xe9, 0xd1, 0xff,
- 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xf7, 0xf7,
- 0x2f, 0xaf, 0xf3, 0xfb, 0xef, 0xff, 0xff, 0xfe,
- 0xff, 0xff, 0xcf, 0xbf, 0xfb,
- 0xbf, 0x87, 0xf8, 0xf8, 0xdf, 0x7f, 0xff, 0xff,
- 0xff, 0xff, 0x8f, 0x8f, 0xe0, 0xf0, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0x8f,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x7f, 0xff, 0xff, 0xff, 0xff, 0xfb, 0xeb, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xfe,
- 0xfb, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xdf, 0xf7, 0xff, 0xff, 0xcf, 0xff,
- 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0xfe,
- 0xcf, 0xff, 0x7b, 0xfd, 0xff,
- 0xff, 0xff, 0xff, 0xf7, 0xdf, 0xff, 0xbf, 0xff,
- 0xfb, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xef, 0xff,
- 0xfb, 0xbe, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xd4, 0xbf, 0xf0,
- 0xbf, 0xff, 0xff, 0xff, 0x93, 0x2f, 0xfd, 0xad,
- 0xf7, 0x75, 0xff, 0xff, 0xfe,
- 0xbf, 0x7f, 0xff, 0x9a, 0xff, 0xf4, 0x0f, 0xff,
- 0x00, 0xde, 0xf0, 0xf3, 0xf9, 0xbf, 0x7d, 0xff,
- 0x8f, 0x7f, 0x81, 0x0f, 0xd1,
- 0xff, 0xfb, 0xdf, 0xee, 0x8b, 0x0b, 0x78, 0xf0,
- 0xff, 0xfa, 0x7f, 0xbf, 0xff, 0xd5, 0x8f, 0x8f,
- 0xe1, 0xf7, 0xfb, 0xfb, 0xff,
- 0x7f, 0xb7, 0x99, 0xef, 0xdf, 0xf4, 0xff, 0xff,
- 0xe4, 0xf4, 0x5d, 0xf6, 0xef, 0x9f, 0xef, 0xf7,
- 0x3b, 0x3f, 0xdf, 0xbf, 0xec,
- 0xff, 0xec, 0xf7, 0xb9, 0x6b, 0xbc, 0xfb, 0xf7,
- 0xef, 0xff, 0x7e, 0xfd, 0x7e, 0xbb, 0xdf, 0x85,
- 0xfe, 0xf7, 0xff, 0x7b, 0x7f,
- 0xff, 0xff, 0xa7, 0xee, 0xe7, 0x5f, 0xe0, 0xf0,
- 0xff, 0xff, 0xff, 0x5f, 0xe6, 0x6f, 0x81, 0x8d,
- 0xd5, 0xf7, 0xbf, 0xef, 0xb6,
- 0xff, 0xd7, 0xf4, 0xee, 0xb7, 0x7c, 0xff, 0xd7,
- 0xaf, 0x7f, 0xed, 0x9f, 0xe5, 0xbf, 0xf7, 0x7d,
- 0xfb, 0xb7, 0xad, 0xd7, 0xfd,
- 0xbf, 0xff, 0xff, 0xc7, 0x8b, 0xff, 0xf0, 0xf6,
- 0xff, 0xfd, 0xfb, 0xff, 0xdf, 0xbe, 0x0f, 0x7f,
- 0xd5, 0xf7, 0xff, 0xf2, 0xfe,
- 0xff, 0xff, 0xc5, 0xff, 0xf0, 0x7c, 0xff, 0xad,
- 0x7f, 0x7f, 0xef, 0xff, 0xcf, 0x4f, 0xf1, 0xf5,
- 0x7b, 0xdd, 0xff, 0xdf, 0xff,
- 0xff, 0x77, 0xef, 0xff, 0xd8, 0xbf, 0xf7, 0xf3,
- 0x5f, 0xfb, 0xf9, 0x7f, 0xe7, 0xff, 0xd7, 0x7f,
- 0xad, 0xff, 0xfb, 0xfb, 0xf3,
- 0xff, 0xcc, 0x95, 0x8f, 0xd8, 0xf3, 0xfc, 0xbc,
- 0xdc, 0xdf, 0xbb, 0x44, 0x8b, 0xcb, 0x87, 0xb1,
- 0xb7, 0xa7, 0x97, 0xee, 0xf3,
- 0xff, 0x7f, 0xb4, 0xbf, 0xff, 0xc7, 0x7f, 0xcb,
- 0xfd, 0xbf, 0x7f, 0x7f, 0x74, 0xe7, 0xdf, 0xf5,
- 0xbb, 0xcf, 0xed, 0xfe, 0xfd,
- 0xff, 0x3f, 0xfb, 0x77, 0xcc, 0xbb, 0xf0, 0xfb,
- 0xff, 0xef, 0xbe, 0xff, 0xcf, 0xff, 0x85, 0x3f,
- 0xb5, 0xff, 0xf7, 0x37, 0x7f,
- 0x3f, 0xf7, 0xbf, 0xcf, 0x9f, 0xd7, 0xf7, 0xef,
- 0xff, 0x78, 0xe7, 0xff, 0xff, 0xff, 0x1f, 0x7f,
- 0x65, 0xbf, 0xbf, 0xff, 0xe7,
- 0xff, 0xff, 0xff, 0xff, 0xdb, 0xf7, 0xdf, 0xff,
- 0x77, 0x7f, 0xff, 0xff, 0xbf, 0xbf, 0xde, 0x77,
- 0xdd, 0xff, 0xff, 0xfe, 0xff,
- 0xbf, 0x68, 0xf8, 0xff, 0xf7, 0xff, 0xcf, 0xcf,
- 0xf3, 0x17, 0x3f, 0xd5, 0xdd, 0xf7, 0xff, 0xff,
- 0xcf, 0xdf, 0x73, 0x95, 0x3f,
- 0xff, 0xac, 0x6f, 0xef, 0x77, 0xdf, 0xff, 0xf7,
- 0xbb, 0x85, 0xdd, 0xe1, 0xf7, 0xfb, 0x7b, 0xdf,
- 0xfe, 0xff, 0xb7, 0x9f, 0x79,
- 0xff, 0xd8, 0xac, 0xfb, 0x47, 0xaf, 0xeb, 0xf7,
- 0xff, 0xaf, 0x2e, 0x70, 0xd9, 0xf7, 0xfb, 0xdf,
- 0xea, 0xfb, 0xfb, 0x1b, 0x5f,
- 0xff, 0xf8, 0x6f, 0xaf, 0xd7, 0xb7, 0xeb, 0xff,
- 0xe7, 0xaf, 0x7c, 0x70, 0xfb, 0xdf, 0xff, 0x7b,
- 0xfb, 0xff, 0xda, 0x9f, 0xf9,
- 0xff, 0x95, 0xbb, 0xfd, 0xc7, 0xcf, 0xfb, 0x83,
- 0xef, 0xf3, 0xbf, 0xcf, 0x47, 0xf7, 0xe7, 0x1f,
- 0xd7, 0x8b, 0x6f, 0x33, 0xbe,
- 0xff, 0xc7, 0x6f, 0xfd, 0x97, 0x2f, 0xeb, 0xb7,
- 0xdc, 0x77, 0xd7, 0x1f, 0x67, 0xf7, 0xe7, 0x9e,
- 0xe7, 0xdb, 0x34, 0xdb, 0xfb,
- 0x7f, 0xa8, 0xef, 0xff, 0xe7, 0xef, 0xff, 0xf7,
- 0xff, 0x8b, 0xbf, 0xd8, 0xef, 0xff, 0xe7, 0xdf,
- 0xf7, 0xfb, 0xf7, 0x9f, 0x66,
- 0xff, 0xfb, 0x6c, 0xff, 0xb7, 0x9f, 0xcf, 0xcb,
- 0xbb, 0x93, 0xaf, 0xff, 0xa8, 0xff, 0xc7, 0x3f,
- 0xa7, 0xcf, 0xfe, 0xe3, 0x3f,
- 0x3f, 0xdf, 0x7b, 0xfa, 0xff, 0xff, 0xff, 0xf7,
- 0x8f, 0x3f, 0xd0, 0xd3, 0x7f, 0xfc, 0xff, 0x8e,
- 0xff, 0xf3, 0x8f, 0x4e, 0xe4,
- 0x7f, 0xb8, 0xff, 0xff, 0xff, 0xef, 0x8f, 0xdf,
- 0xf3, 0xbb, 0x3f, 0xe0, 0xf3, 0xff, 0xff, 0xef,
- 0x8f, 0xd7, 0xf3, 0xab, 0xef,
- 0x7f, 0x8f, 0xf8, 0xfb, 0x8f, 0x6f, 0xa0, 0xff,
- 0xff, 0xdc, 0xff, 0x5f, 0xfc, 0xf3, 0x8f, 0x6e,
- 0xb1, 0xf7, 0xf7, 0xf7, 0x3e,
- 0xff, 0x90, 0x7b, 0xf8, 0xff, 0x7f, 0xdf, 0xff,
- 0xfb, 0x9f, 0x7f, 0xa0, 0xf3, 0xf1, 0xff, 0xff,
- 0xdf, 0xff, 0xdb, 0xbf, 0x3f,
- 0xff, 0xdc, 0xfb, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x77, 0xaf, 0xff, 0xad, 0xf3, 0xf8, 0xff, 0xfe,
- 0xef, 0xff, 0xff, 0x6f, 0xbf,
- 0xff, 0xff, 0xcf, 0xff, 0xa3, 0xff, 0xaf, 0xcf,
- 0x93, 0xc3, 0x74, 0xef, 0xdf, 0xff, 0xab, 0x2f,
- 0xe7, 0xc7, 0xf3, 0x73, 0x79,
- 0xff, 0xff, 0xcf, 0xff, 0xc3, 0x7f, 0x83, 0xe4,
- 0xd3, 0xbc, 0x7b, 0xdb, 0xdf, 0x7f, 0x8b, 0x8e,
- 0x83, 0x01, 0x51, 0xd5, 0x7b,
- 0xff, 0xfb, 0xdf, 0xff, 0xc3, 0xef, 0xb3, 0xff,
- 0xb7, 0xff, 0xfe, 0xbf, 0xdf, 0xff, 0x8b, 0x6e,
- 0xf3, 0xfb, 0xb7, 0x1f, 0xfe,
- 0xbf, 0x82, 0xc8, 0xf8, 0xd3, 0x7f, 0xf3, 0xfb,
- 0xff, 0xef, 0x87, 0x87, 0xd0, 0x70, 0x8b, 0xff,
- 0xf3, 0xff, 0xef, 0xef, 0x87,
- 0xff, 0xff, 0xff, 0xff, 0x47, 0xff, 0xf3, 0xff,
- 0x7f, 0xff, 0xff, 0xff, 0xdf, 0x7f, 0xcb, 0xef,
- 0xf2, 0xf7, 0xff, 0xff, 0xff,
- 0xff, 0xf7, 0xef, 0xf2, 0xf7, 0xff, 0xf7, 0xff,
- 0xff, 0xff, 0xf7, 0xef, 0xdf, 0xf7, 0xca, 0x7f,
- 0xf3, 0xf7, 0xef, 0xff, 0xf6,
- 0xff, 0xfa, 0xfb, 0xff, 0xe7, 0xff, 0xf7, 0xff,
- 0xff, 0xef, 0xff, 0xf7, 0x57, 0x7f, 0xca, 0xef,
- 0xf3, 0xff, 0xff, 0xef, 0xef,
- 0xff, 0xf6, 0xeb, 0xfa, 0xf7, 0xff, 0xf7, 0x8f,
- 0xff, 0xe3, 0xf7, 0xef, 0xd7, 0xf7, 0xcb, 0x7f,
- 0xf3, 0x8f, 0x6c, 0xf2, 0xe7,
- 0xff, 0xff, 0x2f, 0xff, 0xf1, 0x9d, 0x9e, 0xf4,
- 0xff, 0xff, 0xff, 0xef, 0x0f, 0xff, 0xf1, 0x09,
- 0x3f, 0xf9, 0xbf, 0xf7, 0xfb,
- 0xff, 0xef, 0x7f, 0xf6, 0xfb, 0xf5, 0x0f, 0xdf,
- 0x00, 0xff, 0xd0, 0xbf, 0xc0, 0xbf, 0xf9, 0xff,
- 0x8f, 0x7f, 0x81, 0x6f, 0xe1,
- 0xff, 0xff, 0x9e, 0xaf, 0xf7, 0x0f, 0x18, 0xd9,
- 0xbf, 0x6f, 0x37, 0xef, 0x8f, 0xff, 0x9e, 0x06,
- 0x75, 0xf7, 0xf6, 0xff, 0xef,
- 0x7f, 0xf7, 0xcf, 0xbb, 0xfb, 0x6d, 0xfb, 0xef,
- 0x7d, 0xe9, 0xff, 0xff, 0xbf, 0xc2, 0xf7, 0x6f,
- 0xff, 0xdc, 0xff, 0xf3, 0xfa,
- 0x7f, 0x6f, 0xf7, 0xf9, 0xff, 0x6d, 0xfe, 0x9c,
- 0xbf, 0xbf, 0x7d, 0xe2, 0x7f, 0x77, 0x9f, 0xcd,
- 0xb7, 0xb5, 0xff, 0xff, 0x7f,
- 0x7f, 0xff, 0x87, 0xae, 0x86, 0xdf, 0xc0, 0xfd,
- 0xfb, 0xfa, 0xff, 0xff, 0x8e, 0x6d, 0xd5, 0x3d,
- 0xf1, 0xff, 0xfe, 0xef, 0xff,
- 0xff, 0x3f, 0xd2, 0xa4, 0xfe, 0xd9, 0xf7, 0xfe,
- 0xdf, 0xff, 0xcb, 0xff, 0xdd, 0x7e, 0xbb, 0xdd,
- 0x5f, 0xf7, 0xbf, 0xff, 0xed,
- 0xff, 0xfe, 0xf5, 0xff, 0xb7, 0xf6, 0xb4, 0xae,
- 0xfe, 0xef, 0xf7, 0xff, 0xff, 0x8f, 0x07, 0x7b,
- 0xfb, 0xff, 0x7f, 0xff, 0xf7,
- 0xff, 0x7b, 0xa3, 0xbf, 0xe3, 0xff, 0xff, 0xf7,
- 0xf7, 0xfd, 0xdf, 0xff, 0x8f, 0x7f, 0x9b, 0xdf,
- 0xfb, 0xef, 0xfe, 0xff, 0x3f,
- 0xff, 0x6f, 0xff, 0x7f, 0xb3, 0x7f, 0xdf, 0xbd,
- 0x78, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xef, 0xff,
- 0xdf, 0xee, 0x9d, 0xfd, 0xef,
- 0xff, 0xf8, 0x05, 0x8e, 0xb0, 0x58, 0xf7, 0xfc,
- 0xa4, 0x85, 0xdd, 0xbc, 0x0b, 0x05, 0x61, 0xf8,
- 0xb7, 0xff, 0xeb, 0xef, 0x7f,
- 0xbf, 0xff, 0xc7, 0xbb, 0xd8, 0x6f, 0x79, 0xde,
- 0xff, 0xff, 0xcf, 0xff, 0xba, 0xaf, 0xd9, 0x7b,
- 0xfd, 0xff, 0xf5, 0xdf, 0xbf,
- 0xff, 0xff, 0xaf, 0x7f, 0x88, 0x7f, 0xf0, 0xea,
- 0xfe, 0x7f, 0xf2, 0xff, 0xdf, 0xd7, 0x4f, 0x7f,
- 0xe3, 0xde, 0xff, 0xff, 0xf7,
- 0xff, 0x7d, 0x6f, 0x5f, 0xab, 0xff, 0x7a, 0xb6,
- 0xbf, 0x78, 0xdd, 0x7f, 0xde, 0xef, 0x4b, 0x9b,
- 0xeb, 0x7f, 0x76, 0x9f, 0xac,
- 0xff, 0xcf, 0xff, 0xff, 0xb7, 0x7f, 0xae, 0xef,
- 0xdb, 0xef, 0xff, 0xf7, 0xff, 0xfb, 0xe7, 0xfe,
- 0xbf, 0x7e, 0xfb, 0xf7, 0xfb,
- 0xff, 0xff, 0xff, 0xff, 0xcf, 0xbf, 0xff, 0xff,
- 0xf3, 0xff, 0xff, 0xff, 0xff, 0xef, 0xd7, 0xff,
- 0xe9, 0xef, 0xf2, 0xfe, 0xff,
- 0xff, 0xff, 0xff, 0xef, 0xff, 0x8d, 0xaf, 0xf2,
- 0x71, 0xff, 0xfe, 0xff, 0xff, 0x7f, 0xff, 0xcf,
- 0x0f, 0x75, 0xf1, 0xff, 0xff,
- 0x3f, 0x78, 0xbc, 0xfb, 0xfe, 0xff, 0xff, 0xbf,
- 0xf3, 0x0f, 0x3f, 0xc9, 0xe9, 0x7f, 0xf7, 0xdf,
- 0xff, 0xff, 0x57, 0x82, 0x2e,
- 0xff, 0xf8, 0x7f, 0xfb, 0x7a, 0xfb, 0xff, 0xff,
- 0xeb, 0x87, 0x9b, 0xf1, 0xe5, 0x7f, 0x75, 0x7f,
- 0xfe, 0xff, 0xbe, 0x39, 0x79,
- 0xff, 0xcd, 0xbf, 0xfd, 0x7e, 0xff, 0xfb, 0xf4,
- 0xf7, 0xed, 0x6f, 0xf3, 0x6b, 0xf7, 0xd7, 0xbf,
- 0xfe, 0xfd, 0xf7, 0x8f, 0xef,
- 0xff, 0xf8, 0x7a, 0xff, 0xfa, 0xf0, 0xff, 0xff,
- 0xe6, 0x8f, 0x9b, 0xf1, 0xad, 0xbf, 0xf7, 0xfd,
- 0xbf, 0xfd, 0xef, 0x8f, 0x3f,
- 0xbf, 0xff, 0xad, 0xfb, 0xf4, 0xbf, 0xf3, 0x90,
- 0xdd, 0xf0, 0xfa, 0xcf, 0xe7, 0xf2, 0xf7, 0x7f,
- 0xff, 0xad, 0xff, 0xf5, 0xdf,
- 0xff, 0xcb, 0x7b, 0xfa, 0xd2, 0x7f, 0xc7, 0xf3,
- 0xa9, 0xf7, 0xe7, 0x8b, 0xe7, 0xf1, 0xf7, 0x3f,
- 0x8f, 0x7f, 0xb0, 0xdf, 0xfd,
- 0x7f, 0xf8, 0xff, 0xfb, 0xf2, 0xff, 0xd2, 0xe3,
- 0xdf, 0x87, 0xd3, 0xf0, 0xed, 0xff, 0xf7, 0x7f,
- 0xff, 0xef, 0x77, 0xaa, 0x7f,
- 0xbf, 0xea, 0xfc, 0xfb, 0xb3, 0xbf, 0xb3, 0xff,
- 0xd8, 0x93, 0xab, 0xf1, 0xac, 0xff, 0xf7, 0x3f,
- 0xaf, 0xef, 0xed, 0xc7, 0xad,
- 0xff, 0xd6, 0xff, 0xfd, 0xff, 0xdf, 0xff, 0xf4,
- 0x8f, 0xbf, 0xb1, 0xed, 0xf5, 0xfb, 0xff, 0xef,
- 0xff, 0xf5, 0x8f, 0xdf, 0xf1,
- 0xff, 0xf8, 0xfe, 0xfb, 0xff, 0xdf, 0x9f, 0xf8,
- 0xf0, 0xef, 0xff, 0xd0, 0xfd, 0xf7, 0xff, 0xef,
- 0xaf, 0xf5, 0xf7, 0xce, 0x7f,
- 0x7f, 0x83, 0x7d, 0xfa, 0x8f, 0x5f, 0xd0, 0xcb,
- 0xe9, 0xbb, 0x76, 0x9f, 0x7b, 0xf7, 0x8f, 0x6e,
- 0xb1, 0xd5, 0xf7, 0x5f, 0xc6,
- 0xff, 0xa3, 0x7f, 0xfc, 0xff, 0x7f, 0xff, 0xff,
- 0xdf, 0x9f, 0x7f, 0xa8, 0x77, 0xf5, 0xff, 0xfe,
- 0xff, 0xff, 0xfe, 0x7f, 0x2d,
- 0xff, 0x96, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff,
- 0x37, 0x6f, 0xfd, 0xaf, 0x77, 0xf8, 0xff, 0xff,
- 0xef, 0xff, 0xff, 0xff, 0x4b,
- 0xff, 0x72, 0xaf, 0xff, 0xe5, 0xdf, 0x99, 0xfc,
- 0x10, 0x63, 0xf0, 0xef, 0xef, 0x7f, 0x8b, 0xef,
- 0xaf, 0xe7, 0xf5, 0xf7, 0x7d,
- 0xff, 0xef, 0x8f, 0xff, 0xa1, 0x4f, 0x81, 0xe7,
- 0xb0, 0xfa, 0xfe, 0xd7, 0xcf, 0xff, 0xca, 0xcf,
- 0x0b, 0x85, 0x71, 0xfa, 0xff,
- 0xff, 0xdd, 0xef, 0xff, 0xa4, 0xdf, 0xb1, 0xdc,
- 0xd3, 0xff, 0xf8, 0xff, 0xcf, 0x7f, 0xcb, 0x7f,
- 0xff, 0xf5, 0xff, 0xbf, 0xfd,
- 0xbf, 0x82, 0xc8, 0xf8, 0xe1, 0x7f, 0xf0, 0xdf,
- 0xff, 0xef, 0x87, 0x87, 0xc0, 0xf0, 0xca, 0x2f,
- 0xfb, 0xff, 0xef, 0xee, 0x97,
- 0xff, 0xff, 0x8f, 0xfa, 0xa5, 0xdf, 0xd1, 0xf7,
- 0x7f, 0xff, 0xff, 0xff, 0xff, 0x77, 0xdb, 0xef,
- 0xff, 0xf5, 0xfd, 0xff, 0xff,
- 0xff, 0xf6, 0x8b, 0xf2, 0x94, 0xff, 0xf1, 0xf7,
- 0xff, 0xff, 0xf7, 0xef, 0xd7, 0xf7, 0xdf, 0xee,
- 0xfb, 0xff, 0xef, 0xff, 0xf7,
- 0xff, 0xf3, 0xcb, 0xff, 0xe6, 0xff, 0xf1, 0xef,
- 0xff, 0xef, 0xff, 0xe7, 0xd7, 0x7f, 0xdb, 0x7e,
- 0xfd, 0xf7, 0xff, 0xef, 0xef,
- 0xff, 0xfe, 0xcf, 0xff, 0xc4, 0xff, 0xf2, 0x9f,
- 0xff, 0xe0, 0xf7, 0xff, 0xdf, 0xff, 0xdf, 0x7f,
- 0xdb, 0xac, 0xef, 0xf1, 0xf7,
- 0x7f, 0xef, 0x0f, 0x5f, 0xb4, 0x8f, 0xff, 0xf6,
- 0xfd, 0xff, 0x6f, 0xff, 0x8f, 0xff, 0xe9, 0x8d,
- 0x7f, 0xf1, 0xd1, 0xf7, 0xfe,
- 0xff, 0xe7, 0x7f, 0x87, 0xfd, 0xe7, 0x8f, 0x9b,
- 0x00, 0xff, 0xb0, 0x7d, 0xfd, 0xcf, 0xfb, 0xfd,
- 0x8f, 0x7f, 0x81, 0x6d, 0xd1,
- 0xff, 0xbc, 0xed, 0xff, 0x86, 0x6e, 0x10, 0xf1,
- 0xf4, 0x5f, 0x7f, 0xfe, 0x9f, 0x37, 0xc3, 0x8f,
- 0xf7, 0xe5, 0xfb, 0xff, 0xff,
- 0x7f, 0xfe, 0xff, 0xfd, 0x97, 0xff, 0xfb, 0xff,
- 0x3f, 0xff, 0xf9, 0xc3, 0x1f, 0xf8, 0xff, 0xb5,
- 0x5f, 0xef, 0xdc, 0xff, 0xbe,
- 0xff, 0xcb, 0xe7, 0xfd, 0x69, 0xe7, 0xfc, 0xb6,
- 0xef, 0x9a, 0x77, 0xb6, 0x67, 0xdf, 0xef, 0xf7,
- 0xfe, 0xdf, 0xff, 0xf5, 0x7f,
- 0xff, 0xf7, 0x97, 0xbe, 0xf4, 0xff, 0xf1, 0xba,
- 0xfe, 0xff, 0x97, 0x7f, 0xbf, 0x77, 0x55, 0xdf,
- 0xd9, 0xf1, 0xff, 0xdf, 0xff,
- 0xbf, 0xbf, 0x72, 0xf2, 0xdd, 0xff, 0xe4, 0xff,
- 0x7f, 0xef, 0xff, 0xf7, 0xfe, 0xfb, 0xb9, 0xff,
- 0xff, 0xf5, 0xff, 0xfb, 0x96,
- 0xff, 0x7f, 0xf7, 0xef, 0x83, 0xf7, 0xf7, 0xff,
- 0xdf, 0xff, 0xf7, 0xfd, 0xd5, 0x9f, 0x0f, 0x7f,
- 0xf0, 0xfb, 0xae, 0xff, 0xec,
- 0xff, 0x7b, 0x85, 0xf7, 0xf3, 0xef, 0xff, 0xf7,
- 0xff, 0xed, 0xff, 0xe7, 0x8f, 0x7f, 0xc7, 0x97,
- 0x3f, 0xfc, 0xff, 0xf7, 0xde,
- 0xff, 0xfd, 0x8b, 0xff, 0xf7, 0x1f, 0xfb, 0xff,
- 0x2f, 0xfb, 0xf7, 0xff, 0xbf, 0xff, 0xff, 0x6f,
- 0xf7, 0xf9, 0xe7, 0xff, 0x33,
- 0xff, 0x9e, 0xe7, 0x8b, 0xf0, 0x50, 0xf1, 0xde,
- 0xff, 0x9f, 0x1b, 0x28, 0x1b, 0x8d, 0xb4, 0xe1,
- 0xf5, 0xf3, 0xfe, 0xef, 0xfa,
- 0xff, 0x7f, 0xf6, 0xff, 0xfe, 0x07, 0xec, 0xfb,
- 0x7f, 0xff, 0xfd, 0xff, 0xd6, 0x8f, 0xff, 0xf9,
- 0xff, 0x37, 0x7f, 0xfb, 0xdd,
- 0xff, 0xff, 0xff, 0x63, 0xef, 0xdf, 0xfa, 0xf1,
- 0xff, 0xfc, 0xfe, 0xdf, 0xfb, 0xff, 0x8f, 0x7f,
- 0xf9, 0xeb, 0xef, 0xfd, 0xff,
- 0x7f, 0x7f, 0xfb, 0xe7, 0x9f, 0x9b, 0xe5, 0xcf,
- 0xfd, 0xf7, 0xcf, 0xff, 0xf3, 0xbf, 0x5f, 0x5d,
- 0x67, 0x9f, 0xdf, 0x7f, 0xf9,
- 0xff, 0xff, 0xff, 0x1f, 0xfe, 0xff, 0xf5, 0xdf,
- 0x5f, 0xfb, 0xfb, 0xbf, 0xcf, 0xdf, 0xfb, 0x7f,
- 0xb7, 0xff, 0xfb, 0xff, 0xf7,
- 0x3f, 0x78, 0xfc, 0xf3, 0xff, 0xff, 0xdf, 0xbf,
- 0xf3, 0x05, 0x3f, 0xc1, 0xf1, 0xff, 0xf7, 0xef,
- 0xef, 0xff, 0xfb, 0x97, 0x1f,
- 0xff, 0xd8, 0x7f, 0xfb, 0x7b, 0xfb, 0xf7, 0xbf,
- 0xbb, 0x8e, 0xd3, 0xe1, 0xff, 0xfd, 0xf7, 0xed,
- 0xfe, 0x8b, 0x5e, 0x0f, 0x69,
- 0xbf, 0xf8, 0xfc, 0xfb, 0x7b, 0xff, 0xdf, 0xed,
- 0xf7, 0x8f, 0xbf, 0xce, 0xfe, 0xff, 0xf3, 0xff,
- 0xf6, 0xff, 0xfe, 0x8f, 0x0f,
- 0xff, 0xfc, 0x7d, 0xff, 0xff, 0xfd, 0xf3, 0xff,
- 0xbf, 0x8f, 0xe3, 0xf0, 0xfe, 0xff, 0xfb, 0xff,
- 0xff, 0xff, 0xae, 0x0f, 0x5d,
- 0xff, 0xff, 0xff, 0xf3, 0xff, 0xff, 0xff, 0xd1,
- 0xfd, 0xf1, 0xd3, 0xdd, 0xfd, 0xf1, 0xfb, 0xff,
- 0xfb, 0xfd, 0xff, 0xfd, 0xf6,
- 0xff, 0xff, 0x7f, 0xfe, 0xfd, 0xff, 0x87, 0xff,
- 0xcc, 0xf3, 0xdf, 0xcb, 0xff, 0xfb, 0xfb, 0xff,
- 0x8b, 0x7f, 0xfa, 0xff, 0xff,
- 0x7f, 0xf8, 0xfe, 0xff, 0xef, 0xff, 0xff, 0xff,
- 0xff, 0x8f, 0xff, 0xe8, 0xff, 0xff, 0xf9, 0xff,
- 0xfb, 0xaf, 0x7f, 0x8f, 0x7e,
- 0xbf, 0xfb, 0x78, 0xff, 0xff, 0xff, 0xd7, 0xd3,
- 0xfd, 0xc3, 0x95, 0xc5, 0xf8, 0xff, 0xfb, 0xff,
- 0xfb, 0xff, 0xfc, 0xf2, 0x8f,
- 0xff, 0x8b, 0x7b, 0xff, 0xff, 0xdf, 0xff, 0xfd,
- 0x8f, 0xef, 0xf4, 0xb7, 0xff, 0xfe, 0xff, 0xfe,
- 0xff, 0xff, 0x8f, 0x6f, 0xf4,
- 0xff, 0xfd, 0xff, 0xfe, 0xff, 0xdf, 0xdf, 0xfd,
- 0xf1, 0xb3, 0xff, 0xd8, 0xff, 0xfd, 0xff, 0xff,
- 0xff, 0xfd, 0xf5, 0x87, 0x7f,
- 0x3f, 0xef, 0xff, 0xff, 0x8f, 0x5f, 0xf0, 0xff,
- 0xf1, 0xef, 0x39, 0xc7, 0x7e, 0xf3, 0x8f, 0x7e,
- 0xf1, 0xbd, 0xed, 0xfa, 0x9a,
- 0xff, 0x98, 0x7f, 0xfa, 0xff, 0x7f, 0xff, 0xff,
- 0xf3, 0x8f, 0x5f, 0x8a, 0xfb, 0xf1, 0xff, 0xff,
- 0xff, 0xff, 0xf7, 0xaf, 0x5f,
- 0xff, 0x86, 0xff, 0xfc, 0xff, 0xff, 0xdf, 0xff,
- 0x7f, 0xbf, 0xcb, 0xbd, 0x77, 0xf2, 0xff, 0xfe,
- 0xff, 0xff, 0xff, 0xbf, 0x77,
- 0xff, 0xff, 0xef, 0xff, 0xed, 0xdf, 0xff, 0xdd,
- 0x11, 0x73, 0xfc, 0xfc, 0xef, 0xff, 0xfb, 0xff,
- 0xfd, 0xfd, 0x9d, 0xf3, 0xff,
- 0xff, 0xf9, 0xef, 0xff, 0xf3, 0x0f, 0x83, 0x9e,
- 0xf0, 0xf0, 0xff, 0xed, 0xef, 0xff, 0xe9, 0x8e,
- 0x7b, 0x9d, 0x70, 0xe9, 0xf7,
- 0xff, 0xff, 0xef, 0xff, 0xef, 0xff, 0xf3, 0xf9,
- 0xf7, 0xff, 0xfb, 0xf3, 0xef, 0xfd, 0xeb, 0xfe,
- 0xff, 0xff, 0xff, 0xff, 0xf8,
- 0x3f, 0x87, 0xec, 0xf8, 0xe5, 0x7f, 0xfb, 0xff,
- 0xff, 0xff, 0x8f, 0x87, 0xe8, 0xf0, 0xeb, 0xff,
- 0xff, 0xfd, 0xff, 0xff, 0x97,
- 0xff, 0xff, 0xef, 0xff, 0xed, 0xdf, 0xd3, 0xbf,
- 0x7f, 0xfe, 0xff, 0xff, 0xef, 0xff, 0xe3, 0xef,
- 0xff, 0xff, 0xff, 0xfe, 0xff,
- 0xff, 0x77, 0xef, 0xfa, 0xe7, 0xff, 0xfb, 0xff,
- 0xff, 0xff, 0xef, 0xef, 0xef, 0xf7, 0xea, 0xfe,
- 0xf3, 0xff, 0xff, 0xff, 0xfe,
- 0xff, 0xf7, 0xeb, 0xf3, 0xef, 0xff, 0xf3, 0xff,
- 0xf1, 0x7f, 0xff, 0xe7, 0xe7, 0xf7, 0xea, 0xee,
- 0xf7, 0xff, 0xf1, 0xff, 0xe7,
- 0xff, 0xfb, 0x6f, 0xf6, 0xe5, 0xff, 0xeb, 0xdf,
- 0xef, 0xff, 0xff, 0xf7, 0xef, 0xff, 0xe3, 0xef,
- 0xff, 0xfe, 0xff, 0xfe, 0xf7,
- 0x7f, 0xff, 0x4f, 0x5f, 0xe1, 0xc7, 0xef, 0xf1,
- 0xfe, 0x7f, 0x7b, 0xff, 0x6f, 0xff, 0x93, 0x0b,
- 0x7f, 0xf1, 0xfa, 0xdf, 0xff,
- 0xff, 0xfb, 0x7f, 0xdf, 0xf7, 0xef, 0x8f, 0xff,
- 0x00, 0xef, 0xf0, 0xdf, 0x7f, 0xef, 0xff, 0xfb,
- 0x8f, 0x7f, 0x81, 0x6f, 0xd1,
- 0xff, 0xde, 0xff, 0xef, 0xb9, 0x49, 0x74, 0xf3,
- 0xef, 0x7b, 0x7f, 0xff, 0xeb, 0xf7, 0x85, 0x67,
- 0xf1, 0xf0, 0xe1, 0xff, 0xf7,
- 0x3f, 0xab, 0xff, 0xc4, 0xbb, 0xff, 0x8c, 0x9d,
- 0x7e, 0x3a, 0xb5, 0xbb, 0xe3, 0xfb, 0xf3, 0xcd,
- 0xe3, 0xff, 0xff, 0xff, 0xfe,
- 0xff, 0xdc, 0xf7, 0xf8, 0x77, 0x8f, 0xf7, 0xfe,
- 0x9f, 0x97, 0x7a, 0xf2, 0x7f, 0xfb, 0x8f, 0x1f,
- 0x7d, 0xfd, 0xef, 0xb1, 0x7d,
- 0xff, 0xef, 0xa6, 0xef, 0x98, 0x9d, 0xf0, 0xf4,
- 0xf4, 0xff, 0xff, 0x7f, 0x8f, 0x7f, 0x89, 0x7f,
- 0xe7, 0xff, 0xff, 0xf7, 0xfb,
- 0xbf, 0xa7, 0xb7, 0xdf, 0xba, 0xfd, 0xfe, 0xeb,
- 0xff, 0xff, 0xc4, 0xef, 0x8f, 0x7c, 0xf7, 0x8f,
- 0x7f, 0xf9, 0xfb, 0xff, 0xfb,
- 0xff, 0xff, 0xff, 0xeb, 0x87, 0xfd, 0xf4, 0xf7,
- 0x6f, 0xff, 0xbf, 0xff, 0xff, 0xef, 0xef, 0xdf,
- 0xff, 0xff, 0xff, 0xf7, 0xff,
- 0xff, 0xf7, 0x85, 0xdb, 0xf2, 0xbf, 0xd7, 0xff,
- 0xff, 0xfd, 0xff, 0xff, 0x8f, 0x7f, 0xf1, 0xaf,
- 0x7d, 0xff, 0xf7, 0xeb, 0xff,
- 0xbf, 0xfd, 0x8f, 0xff, 0xfa, 0x3f, 0xff, 0xf6,
- 0xb7, 0xff, 0xfe, 0xfb, 0x8f, 0x7f, 0xff, 0xff,
- 0xf3, 0xee, 0xbf, 0x7f, 0xff,
- 0xff, 0x67, 0xc6, 0xaf, 0xc3, 0x74, 0xf7, 0xfe,
- 0xee, 0x8a, 0x37, 0x6e, 0xec, 0x87, 0x71, 0x91,
- 0x13, 0x7d, 0xec, 0x87, 0xff,
- 0xbf, 0x7b, 0xf0, 0xef, 0xfb, 0x3f, 0xb7, 0xfc,
- 0xff, 0xff, 0x97, 0x7d, 0xe8, 0xef, 0x9d, 0x77,
- 0xfd, 0xfb, 0xff, 0xfb, 0xbf,
- 0xff, 0xff, 0xde, 0x77, 0xcd, 0xff, 0xf1, 0xfb,
- 0xff, 0xff, 0xf9, 0xe3, 0xff, 0xff, 0xef, 0xff,
- 0xff, 0xfc, 0xcf, 0xff, 0xf3,
- 0x7f, 0xff, 0xfe, 0x77, 0xaf, 0xf7, 0xf8, 0xef,
- 0xff, 0x76, 0xfa, 0xff, 0x99, 0x6d, 0x9f, 0x6f,
- 0xf1, 0xbf, 0x7f, 0x7f, 0xfc,
- 0xff, 0xff, 0xef, 0xbf, 0xeb, 0xfa, 0xdd, 0xef,
- 0xbc, 0xfd, 0xfd, 0xdf, 0xff, 0xf7, 0xff, 0xff,
- 0xd1, 0xfe, 0xff, 0xfb, 0xff,
- 0x3f, 0x70, 0xf8, 0xff, 0xf5, 0xff, 0xff, 0x9f,
- 0xf3, 0x09, 0x1f, 0xe1, 0xf3, 0xfd, 0xfd, 0xff,
- 0xef, 0xff, 0xf7, 0x8e, 0x1e,
- 0xff, 0xf8, 0x7f, 0xff, 0x77, 0xff, 0xff, 0x9b,
- 0x8f, 0x8e, 0xfb, 0xf1, 0xef, 0xe5, 0xfd, 0xef,
- 0xfe, 0x9f, 0x16, 0x03, 0x61,
- 0xbf, 0xf8, 0xfa, 0xfd, 0x73, 0xff, 0xff, 0xf7,
- 0xf7, 0x8d, 0x9f, 0xe1, 0xf1, 0xff, 0xef, 0xff,
- 0xfc, 0xff, 0xff, 0x8f, 0x0f,
- 0xff, 0xf8, 0x7f, 0xff, 0xf7, 0xf7, 0xfd, 0xff,
- 0x9f, 0x8f, 0xe1, 0xf1, 0xef, 0xff, 0xff, 0xff,
- 0xfd, 0xff, 0x8e, 0x0f, 0x7d,
- 0xff, 0xf7, 0xf9, 0xfe, 0xf3, 0x7f, 0xff, 0xf7,
- 0xf7, 0xf3, 0xfd, 0xef, 0xff, 0xf9, 0xed, 0xff,
- 0xff, 0xef, 0xff, 0xf7, 0xff,
- 0xff, 0xf7, 0x7e, 0xfe, 0xf7, 0xff, 0x8b, 0xf7,
- 0xfc, 0xeb, 0xeb, 0xed, 0xeb, 0xf9, 0xfd, 0xff,
- 0x8f, 0x7f, 0xf2, 0xfe, 0xed,
- 0x7f, 0xf8, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7,
- 0xf7, 0x8d, 0xff, 0xe8, 0xff, 0xfd, 0xef, 0xfe,
- 0xfd, 0xdf, 0xf6, 0x8f, 0x6f,
- 0xbf, 0xff, 0x78, 0xff, 0xf7, 0xff, 0xfb, 0xff,
- 0xff, 0xe3, 0x9f, 0xe5, 0xea, 0xf5, 0xfd, 0xff,
- 0xed, 0xef, 0xff, 0xf7, 0x8f,
- 0xff, 0x07, 0xff, 0xf9, 0xff, 0xff, 0xff, 0xf7,
- 0x8f, 0xff, 0xf3, 0x93, 0xff, 0xff, 0xff, 0xef,
- 0xff, 0xf7, 0x8f, 0x7f, 0xf3,
- 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xf7, 0x8b, 0xff, 0xe8, 0xfb, 0xff, 0xff, 0xef,
- 0xef, 0xf7, 0xf5, 0x8e, 0x7f,
- 0x3f, 0xec, 0xf9, 0xfc, 0x8f, 0x7f, 0xf0, 0xef,
- 0xef, 0xff, 0x1d, 0xed, 0x7e, 0xfd, 0x8f, 0x6e,
- 0xf1, 0xd7, 0xf7, 0xde, 0x8c,
- 0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
- 0xfb, 0x8f, 0x6f, 0x90, 0xff, 0xf3, 0xff, 0xff,
- 0xff, 0xff, 0xfe, 0x8f, 0x7f,
- 0xff, 0x87, 0xfb, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x7f, 0x9f, 0xff, 0x93, 0x7f, 0xf2, 0xff, 0xfe,
- 0xef, 0xff, 0xff, 0x9f, 0x69,
- 0xff, 0xfb, 0xef, 0xff, 0xf6, 0xff, 0xff, 0xff,
- 0x1f, 0x73, 0xfe, 0xf6, 0xff, 0xff, 0xff, 0xef,
- 0xef, 0xe7, 0x97, 0x77, 0xf7,
- 0xff, 0xff, 0xff, 0xff, 0xe7, 0x1f, 0x86, 0x95,
- 0xf0, 0xf6, 0xf7, 0xff, 0xff, 0xff, 0xfe, 0x8f,
- 0x6d, 0x93, 0x71, 0xf8, 0xfd,
- 0xff, 0xfe, 0xef, 0xfd, 0xf2, 0xff, 0xf6, 0xff,
- 0x6f, 0xef, 0xf7, 0xfd, 0xff, 0xff, 0xfd, 0xff,
- 0xfd, 0xff, 0xef, 0xff, 0xf5,
- 0x3f, 0x82, 0xf8, 0xf8, 0xe6, 0x7f, 0xf2, 0xff,
- 0xff, 0xff, 0x87, 0x87, 0xf0, 0xf0, 0xfc, 0xef,
- 0xfd, 0xf7, 0xef, 0xee, 0x87,
- 0xff, 0xff, 0xef, 0xff, 0xe7, 0xff, 0xf6, 0xf7,
- 0x7f, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef,
- 0xff, 0xf7, 0xff, 0xff, 0xff,
- 0xff, 0xf7, 0xff, 0xf2, 0xe6, 0xff, 0xf5, 0xf7,
- 0xff, 0xff, 0xff, 0xe7, 0xff, 0xf7, 0xff, 0xfe,
- 0xff, 0xf7, 0xef, 0xff, 0xf7,
- 0xff, 0xfa, 0xeb, 0xff, 0xe3, 0xff, 0xf5, 0xff,
- 0xff, 0xff, 0xf7, 0xef, 0xf7, 0xff, 0xfd, 0xee,
- 0xfd, 0xff, 0xff, 0xef, 0xef,
- 0xff, 0xf6, 0xfb, 0x7a, 0xe7, 0xff, 0x91, 0xef,
- 0xff, 0xe2, 0xff, 0xf7, 0xf7, 0xf7, 0xfd, 0xff,
- 0xfd, 0xef, 0xeb, 0xf5, 0xe7,
- 0xff, 0xff, 0x8f, 0xbe, 0xf1, 0x93, 0xfd, 0xf1,
- 0xff, 0xff, 0xff, 0xff, 0x2e, 0x2f, 0x59, 0x8f,
- 0x6f, 0xf9, 0xf7, 0xff, 0xfa,
- 0xff, 0x4f, 0xbf, 0xc4, 0xfb, 0xf5, 0x0f, 0xff,
- 0x00, 0xff, 0xd0, 0x7f, 0x70, 0xaf, 0x7f, 0xff,
- 0x8f, 0x7f, 0x81, 0x7f, 0xb1,
- 0xff, 0xff, 0xda, 0xff, 0x2f, 0x4f, 0x7e, 0xf9,
- 0xfb, 0xff, 0x5f, 0xef, 0xff, 0xff, 0x99, 0x29,
- 0x71, 0xf1, 0xed, 0xff, 0xff,
- 0x3f, 0xb7, 0xef, 0xdf, 0xff, 0xf9, 0xfe, 0xfd,
- 0xff, 0xff, 0xb7, 0x9f, 0xff, 0xab, 0x73, 0xfd,
- 0xad, 0x3c, 0x6b, 0xff, 0xfa,
- 0xff, 0xe8, 0xf7, 0xbf, 0x6f, 0x8f, 0xff, 0xfe,
- 0xff, 0x87, 0x7f, 0xe0, 0x7f, 0xbf, 0x5f, 0x93,
- 0x7e, 0xe4, 0xf6, 0x97, 0x7b,
- 0xff, 0xdf, 0x27, 0xaf, 0xa7, 0xff, 0xf4, 0xf6,
- 0xff, 0xff, 0xff, 0x5f, 0xdf, 0xfb, 0x87, 0x1f,
- 0x70, 0xf3, 0xfe, 0x7f, 0xfb,
- 0xbf, 0xb7, 0x61, 0xb5, 0xfc, 0xff, 0xf7, 0xff,
- 0xbf, 0xff, 0xa2, 0xff, 0xd8, 0xa1, 0x77, 0xdf,
- 0xe6, 0xff, 0xff, 0x7e, 0xc4,
- 0xff, 0xff, 0xf6, 0xd7, 0x97, 0xdb, 0xe8, 0xff,
- 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xb9, 0x3b,
- 0xf8, 0xff, 0xef, 0xe7, 0xbe,
- 0xff, 0xff, 0x86, 0xbf, 0xe2, 0xad, 0xff, 0xff,
- 0xff, 0xff, 0x9f, 0xff, 0x8f, 0x3f, 0x63, 0xcf,
- 0x7b, 0xfe, 0xff, 0xfd, 0xfe,
- 0xff, 0xff, 0xdf, 0xff, 0xba, 0x7f, 0xf7, 0xee,
- 0x17, 0xf7, 0xee, 0xef, 0x97, 0x7f, 0xf7, 0xff,
- 0xff, 0xfd, 0x9e, 0x77, 0xf3,
- 0xff, 0xfb, 0xc3, 0x8f, 0xc1, 0x70, 0x71, 0xff,
- 0xf7, 0x9f, 0x77, 0x7e, 0xb6, 0x4f, 0xb9, 0x01,
- 0x1f, 0x1b, 0x7a, 0x9a, 0x7e,
- 0xbf, 0xff, 0xf0, 0x9f, 0xef, 0x79, 0x3f, 0xf6,
- 0xff, 0xfd, 0x9d, 0x7b, 0xf2, 0xff, 0xc9, 0xf3,
- 0xff, 0x7d, 0xfb, 0xfd, 0xbf,
- 0xff, 0xfd, 0xbf, 0x77, 0x8f, 0xff, 0xf1, 0xf7,
- 0xff, 0xff, 0xff, 0xfd, 0xbb, 0x7f, 0xbf, 0x6f,
- 0xf3, 0xfe, 0xff, 0xe7, 0xbf,
- 0x7f, 0xff, 0xff, 0x5f, 0xaf, 0xf1, 0xfc, 0xf7,
- 0xff, 0x77, 0xfe, 0xff, 0xdf, 0xff, 0xdf, 0xff,
- 0xe3, 0x9e, 0x7f, 0x7a, 0xe3,
- 0xff, 0xff, 0x6f, 0xff, 0xaf, 0xfc, 0xff, 0xff,
- 0xfe, 0xfe, 0xfe, 0xff, 0xff, 0xff, 0xf3, 0xfb,
- 0xf7, 0xff, 0xf9, 0xfe, 0xff,
- 0x3f, 0x70, 0xf8, 0xff, 0xf7, 0xff, 0xff, 0xff,
- 0xff, 0x0f, 0x0f, 0xf1, 0xf1, 0xff, 0xf7, 0xff,
- 0xef, 0xff, 0xf7, 0x8c, 0x1e,
- 0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xf7, 0xff, 0x8f,
- 0x8f, 0x88, 0xf1, 0xf1, 0xef, 0xff, 0xf7, 0xff,
- 0xee, 0x97, 0x1e, 0x01, 0x61,
- 0xbf, 0xf0, 0xfa, 0xfd, 0x75, 0xff, 0xf5, 0xff,
- 0xff, 0x8f, 0x9f, 0xe1, 0xf1, 0xff, 0xf7, 0xef,
- 0xfe, 0xff, 0xff, 0x8f, 0x1f,
- 0xff, 0xfa, 0x7f, 0xff, 0xfd, 0xff, 0xfd, 0xff,
- 0x9f, 0x9f, 0xf9, 0xf9, 0xff, 0xef, 0xf7, 0xff,
- 0xff, 0xff, 0x9e, 0x0f, 0x75,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7,
- 0xff, 0xf7, 0xf7, 0xff, 0xef, 0xf7, 0xe7, 0xef,
- 0xef, 0xef, 0xff, 0xff, 0xef,
- 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff,
- 0xf8, 0xf7, 0xff, 0xf7, 0xff, 0xf7, 0xe7, 0xef,
- 0x9f, 0x6f, 0xf0, 0xff, 0xff,
- 0x7f, 0xf8, 0xff, 0xff, 0xfd, 0xff, 0xfd, 0x8f,
- 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xf7, 0xef,
- 0xf7, 0xff, 0xff, 0x9d, 0x7e,
- 0xbf, 0xff, 0x78, 0xff, 0xfd, 0xff, 0xfd, 0xf7,
- 0xff, 0xf7, 0x8f, 0xf7, 0xf0, 0xf7, 0xf7, 0xff,
- 0xf7, 0xef, 0xfe, 0xe7, 0x9f,
- 0xff, 0x8f, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0xff, 0xf8, 0x8f, 0xff, 0xf8, 0xff, 0xef,
- 0xff, 0xff, 0x8e, 0x6f, 0xe1,
- 0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xf7, 0x87, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
- 0xef, 0xef, 0xff, 0x9f, 0x7f,
- 0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0x9f,
- 0xf7, 0xfb, 0x07, 0xe7, 0x78, 0xf7, 0x8f, 0x7e,
- 0xf1, 0x9f, 0x7f, 0xff, 0x9e,
- 0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
- 0xf7, 0x8f, 0x6f, 0x80, 0xff, 0xf1, 0xff, 0xff,
- 0xef, 0xff, 0xfe, 0x9f, 0x7f,
- 0xff, 0x88, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x7f, 0x9f, 0xef, 0x81, 0x7f, 0xf0, 0xff, 0xfe,
- 0xff, 0xff, 0xef, 0x9f, 0x7f,
- 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x97, 0x77, 0xf8, 0xff, 0xef, 0xff, 0xf7, 0xff,
- 0xef, 0xef, 0x8f, 0x76, 0xf1,
- 0xff, 0xff, 0xff, 0xff, 0xf7, 0x0f, 0xf7, 0x88,
- 0xf7, 0xf0, 0xff, 0xff, 0xef, 0xff, 0xef, 0x8e,
- 0x07, 0x99, 0x61, 0xe1, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xf7,
- 0xff, 0xff, 0xf7, 0xf7, 0xef, 0xff, 0xe7, 0xee,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xf7, 0xff,
- 0xff, 0xff, 0x8f, 0x8f, 0xe0, 0xf0, 0xef, 0xff,
- 0xf7, 0xff, 0xff, 0xff, 0x8f,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff,
- 0x7f, 0xff, 0xff, 0xff, 0xef, 0xff, 0xe7, 0xff,
- 0xf6, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xef, 0xff, 0xef, 0xff,
- 0xf7, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0x6f, 0xff, 0xe7, 0xff,
- 0xf7, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xf7, 0xff,
- 0xff, 0xf7, 0xff, 0xff, 0xef, 0xff, 0xef, 0xff,
- 0x97, 0xee, 0xf9, 0xf7, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0x80, 0x88, 0xff, 0xf8,
- 0xff, 0xff, 0xf7, 0xff, 0x0f, 0x1f, 0x79, 0x9b,
- 0x7f, 0xf0, 0xfe, 0xff, 0xff,
- 0xff, 0x4f, 0x7b, 0xf7, 0xf7, 0xf8, 0x0f, 0xff,
- 0x00, 0xff, 0xd0, 0x4f, 0x75, 0x8c, 0x79, 0xff,
- 0x8f, 0x7f, 0x81, 0x7e, 0xb1,
- 0xff, 0xf7, 0xff, 0xfe, 0x8f, 0x7f, 0x70, 0xf0,
- 0xff, 0xf7, 0x7f, 0xff, 0xf7, 0xff, 0x84, 0x0e,
- 0x73, 0xff, 0xf7, 0xff, 0xff,
- 0x3f, 0xbd, 0xfd, 0xfb, 0xf7, 0xe8, 0xff, 0xff,
- 0x78, 0xf0, 0x3f, 0xbf, 0xe3, 0x9b, 0x6f, 0xff,
- 0x97, 0x1f, 0x7f, 0xcf, 0xfe,
- 0xff, 0xf8, 0xf7, 0xff, 0x8f, 0x80, 0xff, 0xf8,
- 0xff, 0x8f, 0x78, 0xf0, 0x7f, 0x9f, 0x7f, 0x9b,
- 0x7f, 0xf1, 0xff, 0x97, 0x7f,
- 0xff, 0xff, 0x07, 0xff, 0x87, 0x7f, 0xf0, 0xf8,
- 0xff, 0x7f, 0xfb, 0x7f, 0xee, 0xfb, 0x99, 0x19,
- 0x73, 0xef, 0xf7, 0xef, 0xff,
- 0xbf, 0x87, 0x04, 0xfc, 0xff, 0x08, 0xf7, 0xff,
- 0x7b, 0x7f, 0x8e, 0x8f, 0xf9, 0x98, 0x6f, 0xf3,
- 0xff, 0xef, 0xff, 0xff, 0xdf,
- 0xff, 0xff, 0x73, 0xff, 0xf7, 0x9f, 0xf8, 0xfb,
- 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x3d,
- 0x61, 0xff, 0xef, 0xff, 0xff,
- 0xff, 0x7f, 0x07, 0xff, 0xf8, 0x78, 0xff, 0xee,
- 0xfb, 0xff, 0xff, 0xff, 0x87, 0x1f, 0x71, 0xe3,
- 0xff, 0xfb, 0xff, 0xff, 0xff,
- 0xff, 0x77, 0x8b, 0x7f, 0xf8, 0x7f, 0xff, 0xff,
- 0x07, 0xe7, 0xfa, 0x77, 0x8f, 0x7f, 0xff, 0xef,
- 0xf1, 0xef, 0x9f, 0x77, 0xf9,
- 0xff, 0xf8, 0x73, 0x8f, 0xf8, 0x0f, 0x88, 0x88,
- 0xf8, 0x98, 0x77, 0x78, 0x8f, 0x6f, 0x87, 0x7b,
- 0xf7, 0xff, 0xef, 0x87, 0x6f,
- 0xbf, 0x7f, 0xf0, 0xff, 0x8f, 0x7f, 0xff, 0xff,
- 0x7e, 0xff, 0x9f, 0x7f, 0xf0, 0xff, 0xff, 0xeb,
- 0xef, 0xff, 0xfb, 0xff, 0x9f,
- 0xff, 0xff, 0xff, 0x77, 0xf8, 0x7f, 0xf8, 0xf7,
- 0xff, 0x7f, 0xf7, 0xff, 0x9f, 0x7f, 0x9b, 0x6f,
- 0xf1, 0xfe, 0xff, 0xfe, 0xff,
- 0x7f, 0x7f, 0x8f, 0xff, 0x8f, 0xff, 0x7f, 0x8f,
- 0xff, 0x70, 0xfb, 0x6f, 0xff, 0xff, 0xff, 0xf5,
- 0xf9, 0xff, 0xff, 0xff, 0xf4,
- 0xff, 0x87, 0xff, 0x74, 0xff, 0x7f, 0xff, 0xff,
- 0x7e, 0xff, 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff,
- 0xe9, 0xff, 0xf7, 0xff, 0xff,
- 0xbf, 0x78, 0xf8, 0x7f, 0xf7, 0xff, 0xff, 0xff,
- 0xf7, 0x07, 0x1f, 0xe1, 0xf1, 0xff, 0xf7, 0xff,
- 0xef, 0xef, 0xff, 0x8e, 0x0f,
- 0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0x87,
- 0x9f, 0x88, 0xf1, 0xe1, 0xff, 0xef, 0xf7, 0xef,
- 0xfe, 0x9f, 0x0f, 0x09, 0x71,
- 0xbf, 0xf0, 0xf8, 0xff, 0x77, 0xff, 0xff, 0xff,
- 0xff, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xf7, 0xff,
- 0xfe, 0xf7, 0xff, 0x8e, 0x1f,
- 0x7f, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0x8f, 0xf9, 0xf8, 0xfe, 0xff, 0xe7, 0xf7,
- 0xff, 0xff, 0x96, 0x0f, 0x61,
- 0x7f, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xf7, 0xef, 0xff, 0xf7, 0xe7, 0xef,
- 0xff, 0xe7, 0xff, 0xf7, 0xfe,
- 0xff, 0xf7, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff,
- 0xf8, 0xef, 0xef, 0xef, 0xff, 0xf7, 0xf7, 0xff,
- 0x9f, 0x67, 0xf0, 0xff, 0xff,
- 0x7f, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f,
- 0xff, 0x8f, 0xff, 0xe0, 0xf7, 0xff, 0xf7, 0xfe,
- 0xf7, 0xf7, 0xff, 0x8f, 0x6e,
- 0x3f, 0xfb, 0x7c, 0xff, 0xff, 0xff, 0xf7, 0xff,
- 0xff, 0xe7, 0x9f, 0xef, 0xf0, 0xff, 0xe7, 0xef,
- 0xf7, 0xef, 0xf6, 0xf6, 0x87,
- 0xff, 0x07, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0xff, 0xf4, 0x9f, 0xff, 0xfc, 0xff, 0xff,
- 0xff, 0xff, 0x8f, 0x7f, 0xf0,
- 0x7f, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xf7, 0x87, 0xff, 0xe8, 0xff, 0xf7, 0xff, 0xff,
- 0xef, 0xe7, 0xf7, 0x8f, 0x6f,
- 0x3f, 0xff, 0xfc, 0xff, 0x8f, 0x7f, 0xf0, 0xcf,
- 0xef, 0xe8, 0x1b, 0xef, 0x7c, 0xff, 0x8f, 0x7e,
- 0xe1, 0x97, 0x77, 0xff, 0x9e,
- 0xff, 0x80, 0x7f, 0xfc, 0xff, 0x7f, 0xff, 0xff,
- 0xf7, 0x8f, 0x7f, 0x80, 0xff, 0xf1, 0xff, 0xfe,
- 0xef, 0xff, 0xff, 0x9f, 0x7f,
- 0xff, 0x84, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x6f, 0x9f, 0xff, 0x91, 0x7f, 0xf0, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0x8f, 0x7f,
- 0xff, 0xfb, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff,
- 0x1f, 0x77, 0xf8, 0xf7, 0xef, 0xff, 0xf7, 0xff,
- 0xf7, 0xef, 0x87, 0x67, 0xf1,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x8b, 0x8c,
- 0xf0, 0xf8, 0xf7, 0xff, 0xef, 0xff, 0xe7, 0x9e,
- 0x67, 0x89, 0x77, 0xf1, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xf3, 0xff, 0xff, 0xff,
- 0xff, 0xef, 0xfb, 0xff, 0xef, 0xff, 0xe7, 0xff,
- 0xf7, 0xf7, 0xff, 0xff, 0xf7,
- 0xbf, 0x87, 0xf8, 0xf8, 0xf7, 0x7f, 0xfb, 0xff,
- 0xff, 0xff, 0x8f, 0x8f, 0xe0, 0xf0, 0xe7, 0xfe,
- 0xf7, 0xff, 0xff, 0xff, 0x8e,
- 0xff, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xfb, 0xff,
- 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xff,
- 0xf7, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xf7, 0xfb, 0xff, 0xfb, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff,
- 0xf7, 0xff, 0xff, 0xff, 0xfe,
- 0xff, 0xff, 0xff, 0xff, 0xf3, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0x7f, 0xf7, 0xff, 0x8b, 0xff,
- 0xfc, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xee, 0xff, 0xf6, 0xff,
- 0xff, 0xf7, 0x8f, 0xbf, 0xf9, 0x8f, 0xff, 0xf0,
- 0xff, 0xff, 0x7f, 0xff, 0x1f, 0x1f, 0x71, 0x89,
- 0x7f, 0xf1, 0xff, 0xff, 0xff,
- 0xff, 0x4f, 0xb8, 0xc6, 0xfb, 0xfd, 0x0f, 0xff,
- 0x00, 0xff, 0xd0, 0x7f, 0x79, 0x90, 0x7f, 0xf9,
- 0x8f, 0x7f, 0x81, 0x7f, 0x81,
- 0xff, 0xff, 0xcf, 0xff, 0xb0, 0x4f, 0x77, 0xf4,
- 0xff, 0xff, 0x7f, 0xe7, 0xee, 0xff, 0x97, 0x07,
- 0x69, 0xf1, 0xf7, 0xff, 0xff,
- 0x3f, 0xba, 0xff, 0x4d, 0xfe, 0xe5, 0xff, 0xff,
- 0x7f, 0xef, 0xbf, 0x9f, 0xe7, 0x9f, 0x77, 0xe9,
- 0x9f, 0x1f, 0x79, 0xc1, 0xfe,
- 0xff, 0xf8, 0xf7, 0x3f, 0xff, 0x9f, 0xf7, 0xf8,
- 0xff, 0x87, 0x7f, 0xf0, 0x7f, 0x97, 0x7f, 0x89,
- 0x7e, 0xf1, 0xff, 0x9f, 0x7f,
- 0xff, 0xff, 0x37, 0xbf, 0xb3, 0x7f, 0xf2, 0xff,
- 0xff, 0xf7, 0xff, 0x7f, 0x7b, 0xfe, 0x87, 0x1f,
- 0x71, 0xf1, 0xff, 0x7f, 0xfb,
- 0xff, 0xff, 0x70, 0xb7, 0xfe, 0x7b, 0xff, 0xf3,
- 0xbf, 0xf7, 0xff, 0xff, 0xf9, 0x9f, 0x7f, 0xf1,
- 0xff, 0xf7, 0xff, 0xff, 0xfb,
- 0xbf, 0xff, 0xf4, 0xcf, 0x87, 0xd8, 0xf8, 0xf8,
- 0xff, 0xff, 0x8f, 0xff, 0xe9, 0xff, 0x8f, 0x1f,
- 0x71, 0xff, 0xef, 0xff, 0x8d,
- 0xff, 0xff, 0x87, 0xbf, 0xf9, 0x3f, 0xff, 0xf7,
- 0xff, 0xff, 0xff, 0xff, 0x9f, 0x1f, 0x71, 0xf9,
- 0xff, 0x7b, 0xff, 0xfe, 0xff,
- 0xff, 0xff, 0xcb, 0xff, 0xbd, 0x7f, 0xfb, 0xff,
- 0x8f, 0xff, 0xf8, 0x7f, 0x9f, 0x7f, 0xf1, 0xef,
- 0xff, 0xf7, 0x8f, 0x7f, 0xf9,
- 0xff, 0xf8, 0x43, 0x8f, 0xc4, 0x75, 0x7d, 0xff,
- 0xff, 0x97, 0x7f, 0x78, 0x8f, 0x6f, 0x99, 0x17,
- 0x19, 0x71, 0xf9, 0x8f, 0x6f,
- 0xbf, 0x7f, 0xf0, 0x8f, 0xf6, 0x7d, 0x37, 0xff,
- 0xff, 0xff, 0x9f, 0x7f, 0xe0, 0xff, 0xff, 0xef,
- 0xff, 0xf7, 0xfb, 0xff, 0x8f,
- 0xff, 0xff, 0xbf, 0x77, 0x8e, 0xff, 0xf0, 0xff,
- 0xff, 0xf7, 0xf7, 0x7f, 0x97, 0x7f, 0x99, 0x7f,
- 0xf9, 0xfe, 0xff, 0xfe, 0xff,
- 0x7f, 0xff, 0xff, 0xcf, 0xbf, 0xf9, 0xfa, 0xff,
- 0xff, 0xff, 0xf3, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xf7, 0x8f, 0x7f, 0x71, 0xf6,
- 0xff, 0xff, 0xff, 0x7f, 0xb7, 0xfe, 0xfb, 0xff,
- 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7,
- 0xff, 0xff, 0xf7, 0xff, 0xff,
- 0x3f, 0x78, 0xf8, 0xff, 0xff, 0xff, 0xff, 0x8f,
- 0xff, 0x08, 0x0f, 0xf1, 0xf1, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0x8e, 0x0e,
- 0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0x8f,
- 0x8f, 0x80, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff,
- 0xfe, 0x8f, 0x0e, 0x01, 0x71,
- 0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff, 0xff,
- 0xff, 0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff,
- 0xfe, 0xff, 0xff, 0x8f, 0x0f,
- 0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x8e, 0x0f, 0x71,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff,
- 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0x7f, 0xf0, 0xff, 0xff,
- 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f,
- 0xff, 0x88, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0x8f, 0x7e,
- 0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xf7, 0x8f, 0xf7, 0xf0, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xfe, 0xff, 0x8f,
- 0xff, 0x87, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0xff, 0xf8, 0x8f, 0xf7, 0xf8, 0xff, 0xff,
- 0xff, 0xff, 0x8e, 0x7f, 0xf1,
- 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0x87, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0x8f, 0x7f,
- 0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0xdf,
- 0xff, 0xf6, 0x07, 0xff, 0x78, 0xff, 0x8f, 0x7e,
- 0xf1, 0x9f, 0x7f, 0xfd, 0x8e,
- 0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
- 0xf7, 0x8f, 0x7f, 0x80, 0xff, 0xf1, 0xff, 0xff,
- 0xff, 0xff, 0xfe, 0x8f, 0x7f,
- 0xff, 0x80, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x7f, 0x8f, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xfe,
- 0xff, 0xff, 0xff, 0x8f, 0x7f,
- 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0x77, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x8f, 0x6e, 0xf1,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0x8f, 0x88,
- 0xf0, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8e,
- 0x7f, 0x81, 0x7f, 0xf1, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x7f, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xfe,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff,
- 0xff, 0xff, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0x8f,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xf7, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0x87, 0xff,
- 0xf8, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xfe, 0xfe, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x3f, 0x8f, 0xf0, 0x85, 0xff, 0xf0,
- 0xff, 0xff, 0xff, 0x7f, 0x0d, 0x0f, 0x71, 0x81,
- 0x7e, 0xf1, 0xfe, 0xff, 0xff,
- 0xff, 0x5f, 0x3d, 0xf0, 0xf5, 0xfa, 0x0f, 0xff,
- 0x00, 0xff, 0x80, 0x0f, 0xf1, 0x88, 0x7f, 0xf1,
- 0x8f, 0x7e, 0x81, 0x7e, 0xc1,
- 0xff, 0xff, 0xff, 0xff, 0xba, 0x4f, 0x75, 0xfa,
- 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0x0f,
- 0x71, 0xf1, 0xff, 0xff, 0xff,
- 0x3f, 0xbf, 0xff, 0xcf, 0xff, 0xfa, 0xff, 0xfe,
- 0x7f, 0xdf, 0x7f, 0xf4, 0xff, 0x8f, 0x7f, 0xf1,
- 0x8f, 0x0f, 0x71, 0xf1, 0xbe,
- 0xff, 0xf8, 0xf7, 0xbb, 0x7f, 0x85, 0xff, 0xf0,
- 0xff, 0x8f, 0x7f, 0xf0, 0x7f, 0x87, 0x7f, 0x81,
- 0x7e, 0xf1, 0x8f, 0x0f, 0x71,
- 0xff, 0xff, 0x87, 0x8f, 0x8d, 0xfd, 0xf5, 0xff,
- 0xfb, 0xff, 0xff, 0xff, 0xf7, 0xfe, 0x8f, 0x0f,
- 0x71, 0xf1, 0xfe, 0x7f, 0xf7,
- 0xbf, 0x07, 0xc0, 0xbf, 0xf7, 0xfd, 0xff, 0xff,
- 0xbf, 0xff, 0x85, 0x8f, 0xf9, 0x8f, 0x7f, 0xf1,
- 0xff, 0x7f, 0xf6, 0xff, 0x83,
- 0xff, 0xff, 0xf4, 0xff, 0x8f, 0xda, 0xf0, 0xb6,
- 0xdf, 0xfd, 0xf6, 0xff, 0xf9, 0xff, 0x8f, 0x1f,
- 0x71, 0xfd, 0x8f, 0x7b, 0xfd,
- 0xff, 0xff, 0xb7, 0x8f, 0xf0, 0xbd, 0xff, 0xfd,
- 0xf7, 0xff, 0xff, 0xff, 0x8f, 0x0f, 0x71, 0xf1,
- 0xff, 0x7b, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xba, 0x7f, 0xf5, 0xf7,
- 0x0f, 0xf7, 0xf0, 0x7f, 0x87, 0x7f, 0xf1, 0xff,
- 0xff, 0xfe, 0x8f, 0x7f, 0xf1,
- 0xff, 0xf8, 0x47, 0x8f, 0xca, 0x70, 0x7a, 0xff,
- 0xff, 0x8f, 0x7f, 0x70, 0x8f, 0x7f, 0x81, 0x0e,
- 0x01, 0x01, 0x71, 0x81, 0x7f,
- 0xbf, 0x7f, 0xf0, 0x8f, 0xff, 0x70, 0x3f, 0xff,
- 0xfd, 0xfe, 0x8f, 0x7f, 0xf0, 0xff, 0xff, 0xff,
- 0xff, 0xfe, 0xfb, 0xff, 0x8f,
- 0xff, 0xff, 0xbf, 0x7f, 0x85, 0x7f, 0xf0, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0x81, 0x7f,
- 0x81, 0xfe, 0xf1, 0xff, 0xff,
- 0x7f, 0xff, 0xff, 0xcf, 0x87, 0xfa, 0x75, 0xff,
- 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0x8f, 0x7f, 0x70, 0xfe,
- 0xff, 0x87, 0xff, 0x4b, 0xbf, 0x7f, 0xfd, 0xff,
- 0xff, 0xff, 0xff, 0x8f, 0xff, 0xff, 0xff, 0xfe,
- 0xff, 0xfe, 0xff, 0xfe, 0xff,
- 0x3f, 0x78, 0xf8, 0xf7, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0x8f, 0x0f, 0x71, 0xf1, 0xff, 0x7f, 0xff,
- 0xff, 0xff, 0xff, 0x8e, 0x0e,
- 0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0x7f, 0x8f,
- 0x8f, 0x00, 0x71, 0xf1, 0xff, 0xff, 0xff, 0xff,
- 0xfe, 0x8f, 0x0e, 0x01, 0x71,
- 0xbf, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0x7f, 0xff,
- 0xff, 0x8f, 0x0f, 0x71, 0xf1, 0xff, 0xff, 0xff,
- 0xfe, 0xff, 0xff, 0x8f, 0x0f,
- 0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0x0f, 0x71, 0xf1, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x8e, 0x0f, 0x71,
- 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0x7f, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x7f, 0xff, 0xff, 0x7f, 0x8f, 0xff,
- 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0x7f, 0xf0, 0xff, 0xff,
- 0x7f, 0xf8, 0xff, 0xff, 0xff, 0x7f, 0x7f, 0xff,
- 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0x8f, 0x7e,
- 0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0x7f, 0xff,
- 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xfe, 0xff, 0x8f,
- 0xff, 0x07, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xf0, 0xff, 0xff,
- 0xff, 0xff, 0x8e, 0x7f, 0xf1,
- 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0x8f, 0x7f,
- 0x3f, 0xff, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0x8f,
- 0xff, 0xfc, 0x8f, 0xff, 0xf0, 0xff, 0x8f, 0x7e,
- 0xf1, 0x8f, 0x7f, 0xf3, 0x8e,
- 0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
- 0xff, 0x8f, 0x7f, 0x80, 0x7f, 0xf1, 0xff, 0xff,
- 0xff, 0xff, 0xfe, 0x8f, 0x7f,
- 0xff, 0x80, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
- 0x7f, 0x8f, 0x7f, 0x81, 0x7f, 0xf0, 0xff, 0xfe,
- 0xff, 0xff, 0xff, 0x8f, 0x7f,
- 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x8f, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x8f, 0x7f, 0xf1,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0x0f, 0xff, 0x80,
- 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x8e,
- 0x0f, 0x01, 0x71, 0xf0, 0xff,
- 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xef, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xfe,
- 0xff, 0xff, 0xff, 0xff, 0xf7,
- 0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff,
- 0x7f, 0x7f, 0x8f, 0x8f, 0xf0, 0xf0, 0xfe, 0xff,
- 0xff, 0xff, 0xff, 0xfe, 0x8f,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7e,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0x7f, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7e,
- 0xff, 0xff, 0x7f, 0xff, 0xff,
- 0xff, 0xff, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0xff,
- 0x7f, 0x7f, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f,
- 0x8f, 0xfe, 0xf0, 0xff, 0xff,
- 0xbf, 0xff, 0x0e, 0x8f, 0x70, 0x80, 0xff, 0xf0,
- 0xff, 0xff, 0xff, 0xff, 0x0f, 0x7f, 0xf1, 0x0f,
- 0x7f, 0xf1, 0xfe, 0xff, 0x9f,
- 0xbf, 0x1f, 0xfb, 0x0c, 0xff, 0xf0, 0x8f, 0xff,
- 0x00, 0xff, 0xb0, 0x3f, 0x71, 0x80, 0xff, 0xf1,
- 0x8f, 0x7f, 0x81, 0x7e, 0xc1,
- 0xff, 0xff, 0xff, 0x7f, 0x8f, 0x0f, 0x70, 0xf0,
- 0x8f, 0x7f, 0x70, 0xcf, 0x8f, 0xff, 0x71, 0x0f,
- 0x7e, 0xf1, 0x8f, 0x7f, 0xf1,
- 0x7f, 0xff, 0x7f, 0x0f, 0xff, 0x78, 0x8f, 0x8f,
- 0x70, 0x70, 0x7f, 0xfe, 0xff, 0x8f, 0xff, 0x70,
- 0xff, 0xfe, 0xff, 0xff, 0xbe,
- 0xff, 0xf8, 0xf7, 0x0b, 0xf7, 0x88, 0xf7, 0xf0,
- 0x8f, 0x8f, 0x70, 0xf0, 0x7e, 0x73, 0xff, 0x8f,
- 0x7e, 0xf0, 0xff, 0x8f, 0x7f,
- 0xff, 0x78, 0x77, 0xff, 0x8f, 0x8f, 0xf0, 0xf0,
- 0xff, 0x8f, 0x77, 0x70, 0x77, 0x7f, 0xff, 0x7f,
- 0xff, 0xff, 0xfe, 0x8f, 0x7f,
- 0xff, 0xff, 0x77, 0x8f, 0xff, 0xf0, 0xff, 0xff,
- 0x77, 0x7f, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xef, 0x7f, 0xff, 0xbf,
- 0xbf, 0xff, 0x74, 0xff, 0xff, 0x8f, 0xff, 0xfc,
- 0x0f, 0xf3, 0x8c, 0xff, 0xfd, 0xff, 0xff, 0x8f,
- 0x7f, 0xf1, 0x8f, 0x7d, 0x83,
- 0xff, 0x7f, 0x77, 0xff, 0xff, 0xff, 0xff, 0xfb,
- 0xf7, 0x7f, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0x78, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff,
- 0x0f, 0x8f, 0x70, 0x70, 0xf7, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x8e, 0x0f, 0x71,
- 0xff, 0xf8, 0xf7, 0x7f, 0xff, 0x8f, 0x8f, 0x80,
- 0x80, 0x81, 0x70, 0x70, 0x7f, 0xff, 0xff, 0xff,
- 0xff, 0x6f, 0x8f, 0x0f, 0x71,
- 0xbf, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0x7b, 0xff, 0x9f, 0xff, 0x70, 0xff, 0xff, 0xff,
- 0xff, 0x7f, 0xff, 0xfe, 0x8f,
- 0xff, 0x87, 0x7f, 0x78, 0xfe, 0xff, 0x9e, 0xff,
- 0xf2, 0x7f, 0xff, 0x0f, 0xff, 0xf0, 0xff, 0xef,
- 0xff, 0x7f, 0xff, 0xff, 0xff,
- 0x7f, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0xfe, 0x8f,
- 0xff, 0x70, 0xff, 0x7f, 0xff, 0xff, 0xdf, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xfe,
- 0xff, 0xff, 0x7f, 0xf7, 0xff, 0xfe, 0xff, 0xff,
- 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x7f, 0x7f, 0x8f, 0x8f, 0xf0, 0xf0,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xaf, 0x0f,
- 0x70, 0xd1, 0xff, 0xf8, 0xfe,
- 0xff, 0xff, 0xff, 0xf7, 0xaf, 0x8f, 0xfa, 0xf0,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0x9f, 0x8f, 0x0f,
- 0x79, 0xe1, 0xff, 0xfe, 0xff,
- 0xbf, 0xff, 0xff, 0x7a, 0x8f, 0xff, 0xf0, 0xef,
- 0xff, 0xfb, 0xff, 0xaf, 0xff, 0xfb, 0x8f, 0x7f,
- 0xf1, 0xdf, 0xff, 0xf9, 0xff,
- 0xbf, 0xff, 0xff, 0xf7, 0xff, 0xaf, 0xff, 0xba,
- 0xaf, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xef, 0xdf,
- 0xff, 0xfd, 0xbe, 0xf7, 0xf5,
- 0xff, 0xf8, 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff,
- 0xff, 0x8f, 0xf7, 0xf0, 0xff, 0xff, 0x8f, 0x3f,
- 0x11, 0xeb, 0xdb, 0xcf, 0x7f,
- 0xbf, 0xf0, 0x8f, 0x87, 0xf0, 0xf0, 0xff, 0xbf,
- 0xff, 0x8f, 0xff, 0xf1, 0x8f, 0x0f, 0x31, 0xf1,
- 0x9f, 0xdf, 0xf9, 0x85, 0x7f,
- 0xbf, 0xff, 0x8f, 0x7f, 0xf0, 0xff, 0xff, 0xff,
- 0xee, 0xff, 0xfb, 0xf7, 0x8f, 0x7f, 0xb1, 0xff,
- 0xff, 0xff, 0xff, 0xdf, 0xfd,
- 0xff, 0xff, 0xff, 0x8f, 0x8f, 0xf0, 0x80, 0xff,
- 0xf0, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x2f, 0x71,
- 0xc1, 0x7f, 0xf1, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xbf,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0xd1,
- 0x9f, 0xff, 0x7b, 0xb7, 0xff,
- 0xbf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xfe, 0x8f, 0xff, 0xf1, 0xff, 0xff,
- 0xff, 0xff, 0xbf, 0xb7, 0xff,
- 0xff, 0xa4, 0xf7, 0x88, 0xff, 0xf0, 0xaf, 0xbf,
- 0xfb, 0xef, 0xff, 0xf7, 0xff, 0x8f, 0x7f, 0xf1,
- 0xff, 0xdd, 0xf7, 0x97, 0x7f,
- 0xff, 0xff, 0xf7, 0xff, 0x8f, 0xff, 0xf0, 0xff,
- 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f,
- 0xf1, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xf7, 0xaf, 0x0f, 0xa0, 0xf0,
- 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x0f,
- 0x71, 0xb1, 0x37, 0xf7, 0xff,
- 0xff, 0xb8, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff,
- 0xff, 0x8f, 0xff, 0xf0, 0xfe, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0x8f, 0x7f,
- 0xbf, 0xff, 0xf8, 0xf7, 0xff, 0xa7, 0xff, 0xf0,
- 0xff, 0xff, 0x8f, 0xfe, 0xf0, 0xff, 0xff, 0x8f,
- 0x7f, 0xf1, 0xff, 0xff, 0xcf,
- 0xff, 0xff, 0xf7, 0x9f, 0xf7, 0xf3, 0xff, 0xff,
- 0xff, 0xff, 0x7f, 0xff, 0xff, 0xbf, 0x7f, 0xf9,
- 0xff, 0xfe, 0xff, 0xff, 0xdf,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0x7f,
- 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xbf, 0xbf,
- 0xff, 0xff, 0xff, 0xaf, 0xff, 0xf0, 0xff, 0xff,
- 0x9f, 0xfe, 0xf1, 0xff, 0xff, 0xcf, 0x7f, 0xf1,
- 0xff, 0xff, 0xdf, 0xff, 0xf1,
- 0xbf, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xbf, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0x6f,
- 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0x7f,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xbf,
- 0xff, 0xf8, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff,
- 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xcf, 0xff,
- 0xff, 0xd8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0x8f, 0xef, 0xe0, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0x8f, 0x3f,
- 0xff, 0xdf, 0xf7, 0xff, 0x0f, 0xfe, 0xf0, 0xff,
- 0xff, 0xff, 0xff, 0xef, 0xff, 0xdf, 0x8e, 0x7f,
- 0xf1, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xbf, 0xbf, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xef, 0xff, 0xbf, 0x7f, 0xe1, 0xff,
- 0xdf, 0xff, 0x7f, 0xff, 0xbf,
- 0xff, 0xa7, 0xff, 0x88, 0xff, 0xf1, 0xfe, 0xff,
- 0xff, 0xff, 0xff, 0x1f, 0xff, 0xf0, 0xcf, 0xb1,
- 0xff, 0xef, 0xff, 0x7f, 0xff,
diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c
deleted file mode 100644
index 06b2083..0000000
--- a/board/sixnet/sixnet.c
+++ /dev/null
@@ -1,578 +0,0 @@
-/*
- * (C) Copyright 2001, 2002
- * Dave Ellis, SIXNET, dge@sixnetio.com.
- * Based on code by:
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * and other contributors to U-Boot.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <jffs2/jffs2.h>
-#include <mpc8xx.h>
-#include <net.h> /* for eth_init() */
-#include <rtc.h>
-#include "sixnet.h"
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-# include <status_led.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define ORMASK(size) ((-size) & OR_AM_MSK)
-
-static long ram_size(ulong *, long);
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-void show_boot_progress (int status)
-{
-#if defined(CONFIG_STATUS_LED)
-# if defined(STATUS_LED_BOOT)
- if (status == BOOTSTAGE_ID_RUN_OS) {
- /* ready to transfer to kernel, make sure LED is proper state */
- status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE);
- }
-# endif /* STATUS_LED_BOOT */
-#endif /* CONFIG_STATUS_LED */
-}
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- * returns 0 if recognized, -1 if unknown
- */
-
-int checkboard (void)
-{
- puts ("Board: SIXNET SXNI855T\n");
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_CMD_PCMCIA)
-#error "SXNI855T has no PCMCIA port"
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-#define _not_used_ 0xffffffff
-
-/* UPMB table for dual UART. */
-
-/* this table is for 50MHz operation, it should work at all lower speeds */
-const uint duart_table[] =
-{
- /* single read. (offset 0 in upm RAM) */
- 0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04,
- 0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05,
-
- /* burst read. (offset 8 in upm RAM) */
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* single write. (offset 18 in upm RAM) */
- 0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04,
- 0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05,
-
- /* burst write. (offset 20 in upm RAM) */
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* refresh. (offset 30 in upm RAM) */
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* exception. (offset 3c in upm RAM) */
- _not_used_, _not_used_, _not_used_, _not_used_,
-};
-
-/* Load FPGA very early in boot sequence, since it must be
- * loaded before the 16C2550 serial channels can be used as
- * console channels.
- *
- * Note: Much of the configuration is not complete. The
- * stack is in DPRAM since SDRAM has not been initialized,
- * so the stack must be kept small. Global variables
- * are still in FLASH, so they cannot be written.
- * Only the FLASH, DPRAM, immap and FPGA can be addressed,
- * the other chip selects may not have been initialized.
- * The clocks have been initialized, so udelay() can be
- * used.
- */
-#define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */
-#define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */
-#define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */
-#define fpga (*(volatile unsigned char *)(CONFIG_SYS_FPGA_PROG)) /* FPGA port */
-
-int board_postclk_init (void)
-{
-
- /* the data to load to the XCSxxXL FPGA */
- static const unsigned char fpgadata[] = {
-# include "fpgadata.c"
- };
-
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-#define porta (immap->im_ioport.iop_padat)
- const unsigned char* pdata;
-
- /* /INITFPGA and DONEFPGA signals are inputs */
- immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE);
-
- /* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */
- porta &= ~FPGA_PROGRAM_L;
-
- /* Set FPGA as an output */
- immap->im_ioport.iop_padir |= FPGA_PROGRAM_L;
-
- /* delay a little to make sure FPGA sees it, really
- * only need less than a microsecond.
- */
- udelay(10);
-
- /* unassert /PROGRAM */
- porta |= FPGA_PROGRAM_L;
-
- /* delay while FPGA does last erase, indicated by
- * /INITFPGA going high. This should happen within a
- * few milliseconds.
- */
- /* ### FIXME - a timeout check would be good, maybe flash
- * the status LED to indicate the error?
- */
- while ((porta & FPGA_INIT_L) == 0)
- ; /* waiting */
-
- /* write program data to FPGA at the programming address
- * so extra /CS1 strobes at end of configuration don't actually
- * write to any registers.
- */
- fpga = 0xff; /* first write is ignored */
- fpga = 0xff; /* fill byte */
- fpga = 0xff; /* fill byte */
- fpga = 0x4f; /* preamble code */
- fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */
- fpga = 0x4b; /* field check code */
-
- pdata = fpgadata;
- /* while no error write out each of the 28 byte frames */
- while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L
- && pdata < fpgadata + sizeof(fpgadata)) {
-
- fpga = 0x4f; /* preamble code */
-
- /* 21 bytes of data in a frame */
- fpga = *(pdata++); fpga = *(pdata++);
- fpga = *(pdata++); fpga = *(pdata++);
- fpga = *(pdata++); fpga = *(pdata++);
- fpga = *(pdata++); fpga = *(pdata++);
- fpga = *(pdata++); fpga = *(pdata++);
- fpga = *(pdata++); fpga = *(pdata++);
- fpga = *(pdata++); fpga = *(pdata++);
- fpga = *(pdata++); fpga = *(pdata++);
- fpga = *(pdata++); fpga = *(pdata++);
- fpga = *(pdata++); fpga = *(pdata++);
- fpga = *(pdata++);
-
- fpga = 0x4b; /* field check code */
- fpga = 0xff; /* extended write cycle */
- fpga = 0x4b; /* extended write cycle
- * (actually 0x4b from bitgen.exe)
- */
- fpga = 0xff; /* extended write cycle */
- fpga = 0xff; /* extended write cycle */
- fpga = 0xff; /* extended write cycle */
- }
-
- fpga = 0xff; /* startup byte */
- fpga = 0xff; /* startup byte */
- fpga = 0xff; /* startup byte */
- fpga = 0xff; /* startup byte */
-
-#if 0 /* ### FIXME */
- /* If didn't load all the data or FPGA_DONE is low the load failed.
- * Maybe someday stop here and flash the status LED? The console
- * is not configured, so can't print an error message. Can't write
- * global variables to set a flag (except gd?).
- * For now it must work.
- */
-#endif
-
- /* Now that the FPGA is loaded, set up the Dual UART chip
- * selects. Must be done here since it may be used as the console.
- */
- upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint));
-
- memctl->memc_mbmr = DUART_MBMR;
- memctl->memc_or5 = DUART_OR_VALUE;
- memctl->memc_br5 = DUART_BR5_VALUE;
- memctl->memc_or6 = DUART_OR_VALUE;
- memctl->memc_br6 = DUART_BR6_VALUE;
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* base address for SRAM, assume 32-bit port, valid */
-#define NVRAM_BR_VALUE (CONFIG_SYS_SRAM_BASE | BR_PS_32 | BR_V)
-
-/* up to 64MB - will be adjusted for actual size */
-#define NVRAM_OR_PRELIM (ORMASK(CONFIG_SYS_SRAM_SIZE) \
- | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
-/*
- * Miscellaneous platform dependent initializations after running in RAM.
- */
-
-int misc_init_r (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- bd_t *bd = gd->bd;
- uchar enetaddr[6];
-
- memctl->memc_or2 = NVRAM_OR_PRELIM;
- memctl->memc_br2 = NVRAM_BR_VALUE;
-
- /* Is there any SRAM? Is it 16 or 32 bits wide? */
-
- /* First look for 32-bit SRAM */
- bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
-
- if (bd->bi_sramsize == 0) {
- /* no 32-bit SRAM, but there could be 16-bit SRAM since
- * it would report size 0 when configured for 32-bit bus.
- * Try again with a 16-bit bus.
- */
- memctl->memc_br2 |= BR_PS_16;
- bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
- }
-
- if (bd->bi_sramsize == 0) {
- memctl->memc_br2 = 0; /* disable select since nothing there */
- }
- else {
- /* adjust or2 for actual size of SRAM */
- memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
- bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
- printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10);
- }
-
-
- /* set standard MPC8xx clock so kernel will see the time
- * even if it doesn't have a DS1306 clock driver.
- * This helps with experimenting with standard kernels.
- */
- {
- ulong tim;
- struct rtc_time tmp;
-
- rtc_get(&tmp); /* get time from DS1306 RTC */
-
- /* convert to seconds since 1970 */
- tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
- tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
-
- immap->im_sitk.sitk_rtck = KAPWR_KEY;
- immap->im_sit.sit_rtc = tim;
- }
-
- /* set up ethernet address for SCC ethernet. If eth1addr
- * is present it gets a unique address, otherwise it
- * shares the FEC address.
- */
- if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
- eth_getenv_enetaddr("ethaddr", enetaddr);
- eth_setenv_enetaddr("eth1addr", enetaddr);
- }
-
- return (0);
-}
-
-#if defined(CONFIG_CMD_NAND)
-void nand_init(void)
-{
- unsigned long totlen = nand_probe(CONFIG_SYS_DFLASH_BASE);
-
- printf ("%4lu MB\n", totlen >> 20);
-}
-#endif
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'.
- *
- * The memory size MUST be a power of 2 for this to work.
- *
- * The only memory modified is 8 bytes at offset 0. This is important
- * since for the SRAM this location is reserved for autosizing, so if
- * it is modified and the board is reset before ram_size() completes
- * no damage is done. Normally even the memory at 0 is preserved. The
- * higher SRAM addresses may contain battery backed RAM disk data which
- * must never be corrupted.
- */
-
-static long ram_size(ulong *base, long maxsize)
-{
- volatile long *test_addr;
- volatile ulong *base_addr = base;
- ulong ofs; /* byte offset from base_addr */
- ulong save; /* to make test non-destructive */
- ulong save2; /* to make test non-destructive */
- long ramsize = -1; /* size not determined yet */
-
- save = *base_addr; /* save value at 0 so can restore */
- save2 = *(base_addr+1); /* save value at 4 so can restore */
-
- /* is any SRAM present? */
- *base_addr = 0x5555aaaa;
-
- /* It is important to drive the data bus with different data so
- * it doesn't remember the value and look like RAM that isn't there.
- */
- *(base_addr + 1) = 0xaaaa5555; /* use write to modify data bus */
-
- if (*base_addr != 0x5555aaaa)
- ramsize = 0; /* no RAM present, or defective */
- else {
- *base_addr = 0xaaaa5555;
- *(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */
- if (*base_addr != 0xaaaa5555)
- ramsize = 0; /* no RAM present, or defective */
- }
-
- /* now size it if any is present */
- for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) {
- test_addr = (long*)((long)base_addr + ofs); /* location to test */
-
- *base_addr = ~*test_addr;
- if (*base_addr == *test_addr)
- ramsize = ofs; /* wrapped back to 0, so this is the size */
- }
-
- *base_addr = save; /* restore value at 0 */
- *(base_addr+1) = save2; /* restore value at 4 */
- return (ramsize);
-}
-
-/* ------------------------------------------------------------------------- */
-/* sdram table based on the FADS manual */
-/* for chip MB811171622A-100 */
-
-/* this table is for 50MHz operation, it should work at all lower speeds */
-
-const uint sdram_table[] =
-{
- /* single read. (offset 0 in upm RAM) */
- 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
- 0x1ff77c47,
-
- /* precharge and Mode Register Set initialization (offset 5).
- * This is also entered at offset 6 to do Mode Register Set
- * without the precharge.
- */
- 0x1ff77c34, 0xefeabc34, 0x1fb57c35,
-
- /* burst read. (offset 8 in upm RAM) */
- 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
- 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* single write. (offset 18 in upm RAM) */
- /* FADS had 0x1f27fc04, ...
- * but most other boards have 0x1f07fc04, which
- * sets GPL0 from A11MPC to 0 1/4 clock earlier,
- * like the single read.
- * This seems better so I am going with the change.
- */
- 0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* burst write. (offset 20 in upm RAM) */
- 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
- 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* refresh. (offset 30 in upm RAM) */
- 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
- _not_used_, _not_used_, _not_used_, _not_used_,
-
- /* exception. (offset 3c in upm RAM) */
- 0x7ffffc07, _not_used_, _not_used_, _not_used_ };
-
-/* ------------------------------------------------------------------------- */
-
-#define SDRAM_MAX_SIZE 0x10000000 /* max 256 MB SDRAM */
-
-/* precharge and set Mode Register */
-#define SDRAM_MCR_PRE (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
- MCR_MB_CS3 | /* chip select */ \
- MCR_MLCF(1) | MCR_MAD(5)) /* 1 time at 0x05 */
-
-/* set Mode Register, no precharge */
-#define SDRAM_MCR_MRS (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
- MCR_MB_CS3 | /* chip select */ \
- MCR_MLCF(1) | MCR_MAD(6)) /* 1 time at 0x06 */
-
-/* runs refresh loop twice so get 8 refresh cycles */
-#define SDRAM_MCR_REFR (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
- MCR_MB_CS3 | /* chip select */ \
- MCR_MLCF(2) | MCR_MAD(0x30)) /* twice at 0x30 */
-
-/* MAMR values work in either mamr or mbmr */
-#define SDRAM_MAMR_BASE /* refresh at 50MHz */ \
- ((195 << MAMR_PTA_SHIFT) | MAMR_PTAE \
- | MAMR_DSA_1_CYCL /* 1 cycle disable */ \
- | MAMR_RLFA_1X /* Read loop 1 time */ \
- | MAMR_WLFA_1X /* Write loop 1 time */ \
- | MAMR_TLFA_4X) /* Timer loop 4 times */
-/* 8 column SDRAM */
-#define SDRAM_MAMR_8COL (SDRAM_MAMR_BASE \
- | MAMR_AMA_TYPE_0 /* Address MUX 0 */ \
- | MAMR_G0CLA_A11) /* GPL0 A11[MPC] */
-
-/* 9 column SDRAM */
-#define SDRAM_MAMR_9COL (SDRAM_MAMR_BASE \
- | MAMR_AMA_TYPE_1 /* Address MUX 1 */ \
- | MAMR_G0CLA_A10) /* GPL0 A10[MPC] */
-
-/* base address 0, 32-bit port, SDRAM UPM, valid */
-#define SDRAM_BR_VALUE (BR_PS_32 | BR_MS_UPMA | BR_V)
-
-/* up to 256MB, SAM, G5LS - will be adjusted for actual size */
-#define SDRAM_OR_PRELIM (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS)
-
-/* This is the Mode Select Register value for the SDRAM.
- * Burst length: 4
- * Burst Type: sequential
- * CAS Latency: 2
- * Write Burst Length: burst
- */
-#define SDRAM_MODE 0x22 /* CAS latency 2, burst length 4 */
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- uint size_sdram = 0;
- uint size_sdram9 = 0;
- uint base = 0; /* SDRAM must start at 0 */
- int i;
-
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
- /* Configure the refresh (mostly). This needs to be
- * based upon processor clock speed and optimized to provide
- * the highest level of performance.
- *
- * Preliminary prescaler for refresh.
- * This value is selected for four cycles in 31.2 us,
- * which gives 8192 cycles in 64 milliseconds.
- * This may be too fast, but works for any memory.
- * It is adjusted to 4096 cycles in 64 milliseconds if
- * possible once we know what memory we have.
- *
- * We have to be careful changing UPM registers after we
- * ask it to run these commands.
- *
- * PTA - periodic timer period for our design is
- * 50 MHz x 31.2us
- * --------------- = 195
- * 1 x 8 x 1
- *
- * 50MHz clock
- * 31.2us refresh interval
- * SCCR[DFBRG] 0
- * PTP divide by 8
- * 1 chip select
- */
- memctl->memc_mptpr = MPTPR_PTP_DIV8; /* 0x0800 */
- memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */
-
- /* The SDRAM Mode Register value is shifted left 2 bits since
- * A30 and A31 don't connect to the SDRAM for 32-bit wide memory.
- */
- memctl->memc_mar = SDRAM_MODE << 2; /* MRS code */
- udelay(200); /* SDRAM needs 200uS before set it up */
-
- /* Now run the precharge/nop/mrs commands. */
- memctl->memc_mcr = SDRAM_MCR_PRE;
- udelay(2);
-
- /* Run 8 refresh cycles (2 sets of 4) */
- memctl->memc_mcr = SDRAM_MCR_REFR; /* run refresh twice */
- udelay(2);
-
- /* some brands want Mode Register set after the refresh
- * cycles. This shouldn't hurt anything for the brands
- * that were happy with the first time we set it.
- */
- memctl->memc_mcr = SDRAM_MCR_MRS;
- udelay(2);
-
- memctl->memc_mamr = SDRAM_MAMR_8COL; /* enable refresh */
- memctl->memc_or3 = SDRAM_OR_PRELIM;
- memctl->memc_br3 = SDRAM_BR_VALUE + base;
-
- /* Some brands need at least 10 DRAM accesses to stabilize.
- * It wont hurt the brands that don't.
- */
- for (i=0; i<10; ++i) {
- volatile ulong *addr = (volatile ulong *)base;
- ulong val;
-
- val = *(addr + i);
- *(addr + i) = val;
- }
-
- /* Check SDRAM memory Size in 8 column mode.
- * For a 9 column memory we will get half the actual size.
- */
- size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE);
-
- /* Check SDRAM memory Size in 9 column mode.
- * For an 8 column memory we will see at most 4 megabytes.
- */
- memctl->memc_mamr = SDRAM_MAMR_9COL;
- size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE);
-
- if (size_sdram < size_sdram9) /* leave configuration at 9 columns */
- size_sdram = size_sdram9;
- else /* go back to 8 columns */
- memctl->memc_mamr = SDRAM_MAMR_8COL;
-
- /* adjust or3 for actual size of SDRAM
- */
- memctl->memc_or3 |= ORMASK(size_sdram);
-
- /* Adjust refresh rate depending on SDRAM type.
- * For types > 128 MBit (32 Mbyte for 2 x16 devices) leave
- * it at the current (fast) rate.
- * For 16, 64 and 128 MBit half the rate will do.
- */
- if (size_sdram <= 32 * 1024 * 1024)
- memctl->memc_mptpr = MPTPR_PTP_DIV16; /* 0x0400 */
-
- return (size_sdram);
-}
diff --git a/board/sixnet/sixnet.h b/board/sixnet/sixnet.h
deleted file mode 100644
index 046c9de..0000000
--- a/board/sixnet/sixnet.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Memory map:
- *
- * ff100000 -> ff13ffff : FPGA CS1
- * ff030000 -> ff03ffff : EXPANSION CS7
- * ff020000 -> ff02ffff : DATA FLASH CS4
- * ff018000 -> ff01ffff : UART B CS6/UPMB
- * ff010000 -> ff017fff : UART A CS5/UPMB
- * ff000000 -> ff00ffff : IMAP internal to the MPC855T
- * f8000000 -> fbffffff : FLASH CS0 up to 64MB
- * f4000000 -> f7ffffff : NVSRAM CS2 up to 64MB
- * 00000000 -> 0fffffff : SDRAM CS3/UPMA up to 256MB
- */
diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds
deleted file mode 100644
index 7ee2012..0000000
--- a/board/sixnet/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/socrates/nand.c b/board/socrates/nand.c
index 3802c7e..7394478 100644
--- a/board/socrates/nand.c
+++ b/board/socrates/nand.c
@@ -18,7 +18,9 @@ static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
static u_char sc_nand_read_byte(struct mtd_info *mtd);
static u16 sc_nand_read_word(struct mtd_info *mtd);
static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
+#endif
static int sc_nand_device_ready(struct mtd_info *mtdinfo);
#define FPGA_NAND_CMD_MASK (0x7 << 28)
@@ -100,6 +102,7 @@ static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
}
}
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
/**
* sc_nand_verify_buf - Verify chip data against buffer
* @mtd: MTD device structure
@@ -116,6 +119,7 @@ static int sc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
}
return 0;
}
+#endif
/**
* sc_nand_device_ready - Check the NAND device is ready for next command.
@@ -174,7 +178,9 @@ int board_nand_init(struct nand_chip *nand)
nand->read_word = sc_nand_read_word;
nand->write_buf = sc_nand_write_buf;
nand->read_buf = sc_nand_read_buf;
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
nand->verify_buf = sc_nand_verify_buf;
+#endif
return 0;
}
diff --git a/board/solidrun/hummingboard/hummingboard.c b/board/solidrun/hummingboard/hummingboard.c
index 2e2fb2a..6d204b3 100644
--- a/board/solidrun/hummingboard/hummingboard.c
+++ b/board/solidrun/hummingboard/hummingboard.c
@@ -144,8 +144,7 @@ int board_phy_config(struct phy_device *phydev)
int board_eth_init(bd_t *bis)
{
- struct iomuxc_base_regs *const iomuxc_regs =
- (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret = enable_fec_anatop_clock(ENET_25MHz);
if (ret)
diff --git a/board/stx/stxxtc/Kconfig b/board/stx/stxxtc/Kconfig
deleted file mode 100644
index c444cff..0000000
--- a/board/stx/stxxtc/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_STXXTC
-
-config SYS_BOARD
- string
- default "stxxtc"
-
-config SYS_VENDOR
- string
- default "stx"
-
-config SYS_CONFIG_NAME
- string
- default "stxxtc"
-
-endif
diff --git a/board/stx/stxxtc/MAINTAINERS b/board/stx/stxxtc/MAINTAINERS
deleted file mode 100644
index 5ea36b2..0000000
--- a/board/stx/stxxtc/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-STXXTC BOARD
-M: Dan Malek <dan@embeddedalley.com>
-S: Orphan (since 2014-06)
-F: board/stx/stxxtc/
-F: include/configs/stxxtc.h
-F: configs/stxxtc_defconfig
diff --git a/board/stx/stxxtc/Makefile b/board/stx/stxxtc/Makefile
deleted file mode 100644
index 6738d4e..0000000
--- a/board/stx/stxxtc/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = stxxtc.o
diff --git a/board/stx/stxxtc/README.stxxtc b/board/stx/stxxtc/README.stxxtc
deleted file mode 100644
index 7d9d4d3..0000000
--- a/board/stx/stxxtc/README.stxxtc
+++ /dev/null
@@ -1,59 +0,0 @@
-
-
-First, some build notes on the Silicon Turnkey eXpress XTc.
-
-This board has both 87x/88x procesor options at various
-frequencies. The configuration file has some macros for setting
-the clock speed, not all have been tested. They all have
-a 10MHz input clock. Please do not check in a configuration
-file that selects a high speed not available on all processors.
-We chose the 66MHz core and bus speed, which should be OK on
-all boards. If you have a processor, lucky you! :-)
-Just build a new configuration with that speed, check
-the macro configuration to ensure it's correct. If the
-macro is updated, please check that in, but keep default
-processor speed.
-
-The board is likely to have more than 1Mbyte of NOR boot flash.
-It was also configured with a high boot vector (Dan's fault)
-so the standard 8xx mapping doesn't work well. We had to move
-the addresses around a little bit so one copy would work. The
-flash got fragmented, and we are working on a better solution.
-There is an "xtc.cfg" floating around for the BDI2000, use
-that for programming a new version of U-Boot. You can probably
-find it on the Silicon Turnkey eXpress (www.silicontkx.com),
-Embedded Alley Solutions (embeddedalley.com), or Denx (denx.de)
-servers.
-
-The board will also have various SDRAM sizes, but the code
-should automatically determine the amount of memory.
-
-There are a couple of different board versions, visually
-they use different BGA or surface mount memory parts. However,
-they are logically the same board.
-
-Now, some operational notes.
-
-The board has the option of sporting two FEC Ethernet ports.
-The second port isn't configured to be automatically available
-because it would cause U-Boot to generate a board data structure
-(the bd_t) with multiple MAC addresses and be incompatible with
-standard 8xx kernel builds. You can use/test the second FEC
-in U-Boot by assigning an 'eth1addr' and selecting the second
-FEC as the port to use.
-
-Since this is just a development board and not a product, STx
-does not assign unique MAC addresses. We just pilfer the
-"default" ones used by Wolfgang on some other boards. Please
-ensure you assign unique MAC addresses when using these boards.
-
-The serial port baud rate is 38400, because that's the way
-I like it :-)
-
-Thanks to Pantelis for lots of the work on this board port.
-
-Have Fun!
-
- -- Dan
-
-15 August 2005
diff --git a/board/stx/stxxtc/stxxtc.c b/board/stx/stxxtc/stxxtc.c
deleted file mode 100644
index 1996efb..0000000
--- a/board/stx/stxxtc/stxxtc.c
+++ /dev/null
@@ -1,592 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * (C) Copyright 2005
- * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * U-Boot port on STx XTc board
- * Mostly copied from Netta
- */
-
-#include <common.h>
-#include <miiphy.h>
-
-#include "mpc8xx.h"
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-#endif
-
-/****************************************************************/
-
-/* some sane bit macros */
-#define _BD(_b) (1U << (31-(_b)))
-#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
-
-#define _BW(_b) (1U << (15-(_b)))
-#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
-
-#define _BB(_b) (1U << (7-(_b)))
-#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
-
-#define _B(_b) _BD(_b)
-#define _BR(_l, _h) _BDR(_l, _h)
-
-/****************************************************************/
-
-/*
- * Check Board Identity:
- *
- * Return 1 always.
- */
-
-int checkboard(void)
-{
- printf ("Silicon Turnkey eXpress XTc\n");
- return (0);
-}
-
-/****************************************************************/
-
-#define _NOT_USED_ 0xFFFFFFFF
-
-/****************************************************************/
-
-#define CS_0000 0x00000000
-#define CS_0001 0x10000000
-#define CS_0010 0x20000000
-#define CS_0011 0x30000000
-#define CS_0100 0x40000000
-#define CS_0101 0x50000000
-#define CS_0110 0x60000000
-#define CS_0111 0x70000000
-#define CS_1000 0x80000000
-#define CS_1001 0x90000000
-#define CS_1010 0xA0000000
-#define CS_1011 0xB0000000
-#define CS_1100 0xC0000000
-#define CS_1101 0xD0000000
-#define CS_1110 0xE0000000
-#define CS_1111 0xF0000000
-
-#define BS_0000 0x00000000
-#define BS_0001 0x01000000
-#define BS_0010 0x02000000
-#define BS_0011 0x03000000
-#define BS_0100 0x04000000
-#define BS_0101 0x05000000
-#define BS_0110 0x06000000
-#define BS_0111 0x07000000
-#define BS_1000 0x08000000
-#define BS_1001 0x09000000
-#define BS_1010 0x0A000000
-#define BS_1011 0x0B000000
-#define BS_1100 0x0C000000
-#define BS_1101 0x0D000000
-#define BS_1110 0x0E000000
-#define BS_1111 0x0F000000
-
-#define GPL0_AAAA 0x00000000
-#define GPL0_AAA0 0x00200000
-#define GPL0_AAA1 0x00300000
-#define GPL0_000A 0x00800000
-#define GPL0_0000 0x00A00000
-#define GPL0_0001 0x00B00000
-#define GPL0_111A 0x00C00000
-#define GPL0_1110 0x00E00000
-#define GPL0_1111 0x00F00000
-
-#define GPL1_0000 0x00000000
-#define GPL1_0001 0x00040000
-#define GPL1_1110 0x00080000
-#define GPL1_1111 0x000C0000
-
-#define GPL2_0000 0x00000000
-#define GPL2_0001 0x00010000
-#define GPL2_1110 0x00020000
-#define GPL2_1111 0x00030000
-
-#define GPL3_0000 0x00000000
-#define GPL3_0001 0x00004000
-#define GPL3_1110 0x00008000
-#define GPL3_1111 0x0000C000
-
-#define GPL4_0000 0x00000000
-#define GPL4_0001 0x00001000
-#define GPL4_1110 0x00002000
-#define GPL4_1111 0x00003000
-
-#define GPL5_0000 0x00000000
-#define GPL5_0001 0x00000400
-#define GPL5_1110 0x00000800
-#define GPL5_1111 0x00000C00
-#define LOOP 0x00000080
-
-#define EXEN 0x00000040
-
-#define AMX_COL 0x00000000
-#define AMX_ROW 0x00000020
-#define AMX_MAR 0x00000030
-
-#define NA 0x00000008
-
-#define UTA 0x00000004
-
-#define TODT 0x00000002
-
-#define LAST 0x00000001
-
-#define A10_AAAA GPL0_AAAA
-#define A10_AAA0 GPL0_AAA0
-#define A10_AAA1 GPL0_AAA1
-#define A10_000A GPL0_000A
-#define A10_0000 GPL0_0000
-#define A10_0001 GPL0_0001
-#define A10_111A GPL0_111A
-#define A10_1110 GPL0_1110
-#define A10_1111 GPL0_1111
-
-#define RAS_0000 GPL1_0000
-#define RAS_0001 GPL1_0001
-#define RAS_1110 GPL1_1110
-#define RAS_1111 GPL1_1111
-
-#define CAS_0000 GPL2_0000
-#define CAS_0001 GPL2_0001
-#define CAS_1110 GPL2_1110
-#define CAS_1111 GPL2_1111
-
-#define WE_0000 GPL3_0000
-#define WE_0001 GPL3_0001
-#define WE_1110 GPL3_1110
-#define WE_1111 GPL3_1111
-
-/* #define CAS_LATENCY 3 */
-#define CAS_LATENCY 2
-
-const uint sdram_table[0x40] = {
-
-#if CAS_LATENCY == 3
- /* RSS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_,
-
- /* RBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* WSS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* WBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-#endif
-
-#if CAS_LATENCY == 2
- /* RSS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
-
- /* RBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
- CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* WSS */
- CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
- CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
- _NOT_USED_,
-
- /* WBS */
- CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
- CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
- CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
- CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
- CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
- _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
-
-#endif
-
- /* UPT */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
- CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
-
- /* EXC */
- CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
- _NOT_USED_,
-
- /* REG */
- CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
- CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
-};
-
-static const uint nandcs_table[0x40] = {
- /* RSS */
- CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
- CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
- CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
- CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
- CS_0000 | GPL4_0000 | GPL5_1111,
- CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
- CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
- CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */
-
- /* RBS */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* WSS */
- CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
- CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
- CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
- CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
- CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
- CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
- CS_0000 | GPL4_1111 | GPL5_1111,
- CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
-
- /* WBS */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* UPT */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /* EXC */
- CS_0001 | LAST,
- _NOT_USED_,
-
- /* REG */
- CS_1110 ,
- CS_0001 | LAST,
-};
-
-/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
-/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
-#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
-
-/* 9 */
-#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
- MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
-
-void check_ram(unsigned int addr, unsigned int size)
-{
- unsigned int i, j, v, vv;
- volatile unsigned int *p;
- unsigned int pv;
-
- p = (unsigned int *)addr;
- pv = (unsigned int)p;
- for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
- *p++ = pv;
-
- p = (unsigned int *)addr;
- for (i = 0; i < size / sizeof(unsigned int); i++) {
- v = (unsigned int)p;
- vv = *p;
- if (vv != v) {
- printf("%p: read %08x instead of %08x\n", p, vv, v);
- hang();
- }
- p++;
- }
-
- for (j = 0; j < 5; j++) {
- switch (j) {
- case 0: v = 0x00000000; break;
- case 1: v = 0xffffffff; break;
- case 2: v = 0x55555555; break;
- case 3: v = 0xaaaaaaaa; break;
- default:v = 0xdeadbeef; break;
- }
- p = (unsigned int *)addr;
- for (i = 0; i < size / sizeof(unsigned int); i++) {
- *p = v;
- vv = *p;
- if (vv != v) {
- printf("%p: read %08x instead of %08x\n", p, vv, v);
- hang();
- }
- *p = ~v;
- p++;
- }
- }
-}
-
-#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0)
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size;
- u32 d1, d2;
-
- upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
-
- /*
- * Preliminary prescaler for refresh
- */
- memctl->memc_mptpr = MPTPR_PTP_DIV8;
-
- memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
-
- /*
- * Map controller bank 3 to the SDRAM bank at preliminary address.
- */
- memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
- memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
-
- memctl->memc_mamr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */
-
- udelay(200);
-
- /* perform SDRAM initialisation sequence */
- memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
- udelay(1);
-
- memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
- udelay(1);
-
- memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
- udelay(1);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay(10000);
-
-
- d1 = 0xAA55AA55;
- *(volatile u32 *)0 = d1;
- d2 = *(volatile u32 *)0;
- if (d1 != d2) {
- printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
- DO_LOOP;
- }
-
- d1 = 0x55AA55AA;
- *(volatile u32 *)0 = d1;
- d2 = *(volatile u32 *)0;
- if (d1 != d2) {
- printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
- DO_LOOP;
- }
-
- d1 = 0x12345678;
- *(volatile u32 *)0 = d1;
- d2 = *(volatile u32 *)0;
- if (d1 != d2) {
- printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
- DO_LOOP;
- }
-
- size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
-
- return size;
-}
-
-/* ------------------------------------------------------------------------- */
-
-void reset_phys(void)
-{
- int phyno;
- unsigned short v;
-
- udelay(10000);
- /* reset the damn phys */
- mii_init();
-
- for (phyno = 0; phyno < 32; ++phyno) {
- miiphy_read("FEC", phyno, MII_PHYSID1, &v);
- if (v == 0xFFFF)
- continue;
- miiphy_write("FEC", phyno, MII_BMCR, BMCR_PDOWN);
- udelay(10000);
- miiphy_write("FEC", phyno, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
- udelay(10000);
- }
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* GP = general purpose, SP = special purpose (on chip peripheral) */
-
-/* bits that can have a special purpose or can be configured as inputs/outputs */
-#define PA_GP_INMASK _BW(6)
-#define PA_GP_OUTMASK (_BW(7))
-#define PA_SP_MASK 0
-#define PA_ODR_VAL 0
-#define PA_GP_OUTVAL (_BW(7))
-#define PA_SP_DIRVAL 0
-
-#define PB_GP_INMASK 0
-#define PB_GP_OUTMASK (_B(23))
-#define PB_SP_MASK 0
-#define PB_ODR_VAL 0
-#define PB_GP_OUTVAL (_B(23))
-#define PB_SP_DIRVAL 0
-
-#define PC_GP_INMASK 0
-#define PC_GP_OUTMASK (_BW(15))
-
-#define PC_SP_MASK 0
-#define PC_SOVAL 0
-#define PC_INTVAL 0
-#define PC_GP_OUTVAL 0
-#define PC_SP_DIRVAL 0
-
-#define PE_GP_INMASK 0
-#define PE_GP_OUTMASK 0
-#define PE_GP_OUTVAL 0
-
-#define PE_SP_MASK 0
-#define PE_ODR_VAL 0
-#define PE_SP_DIRVAL 0
-
-int board_early_init_f(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile iop8xx_t *ioport = &immap->im_ioport;
- volatile cpm8xx_t *cpm = &immap->im_cpm;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- (void)ioport;
- (void)cpm;
-#if 1
- /* NAND chip select */
- upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
- memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
- memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB);
- memctl->memc_mbmr = 0; /* all clear */
-#endif
-
- memctl->memc_br5 &= ~BR_V;
- memctl->memc_br6 &= ~BR_V;
- memctl->memc_br7 &= ~BR_V;
-
-#if 1
- ioport->iop_padat = PA_GP_OUTVAL;
- ioport->iop_paodr = PA_ODR_VAL;
- ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
- ioport->iop_papar = PA_SP_MASK;
-
- cpm->cp_pbdat = PB_GP_OUTVAL;
- cpm->cp_pbodr = PB_ODR_VAL;
- cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
- cpm->cp_pbpar = PB_SP_MASK;
-
- ioport->iop_pcdat = PC_GP_OUTVAL;
- ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
- ioport->iop_pcso = PC_SOVAL;
- ioport->iop_pcint = PC_INTVAL;
- ioport->iop_pcpar = PC_SP_MASK;
-
- cpm->cp_pedat = PE_GP_OUTVAL;
- cpm->cp_peodr = PE_ODR_VAL;
- cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
- cpm->cp_pepar = PE_SP_MASK;
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_HW_WATCHDOG
-
-void hw_watchdog_reset(void)
-{
- /* XXX add here the really funky stuff */
-}
-
-#endif
-
-#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
-int overwrite_console(void)
-{
- /* printf("overwrite_console called\n"); */
- return 0;
-}
-#endif
-
-extern int drv_phone_init(void);
-extern int drv_phone_use_me(void);
-extern int drv_phone_is_idle(void);
-
-int misc_init_r(void)
-{
- return 0;
-}
-
-int last_stage_init(void)
-{
- reset_phys();
-
- return 0;
-}
diff --git a/board/stx/stxxtc/u-boot.lds b/board/stx/stxxtc/u-boot.lds
deleted file mode 100644
index 0dff5a4..0000000
--- a/board/stx/stxxtc/u-boot.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/stx/stxxtc/u-boot.lds.debug b/board/stx/stxxtc/u-boot.lds.debug
deleted file mode 100644
index a198cf9..0000000
--- a/board/stx/stxxtc/u-boot.lds.debug
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index b06b5e0..c61c650 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -1,17 +1,5 @@
if TARGET_SUN4I
-config SYS_CPU
- string
- default "armv7"
-
-config SYS_BOARD
- string
- default "sunxi"
-
-config SYS_SOC
- string
- default "sunxi"
-
config SYS_CONFIG_NAME
string
default "sun4i"
@@ -20,25 +8,21 @@ endif
if TARGET_SUN5I
-config SYS_CPU
+config SYS_CONFIG_NAME
string
- default "armv7"
+ default "sun5i"
-config SYS_BOARD
- string
- default "sunxi"
+endif
-config SYS_SOC
- string
- default "sunxi"
+if TARGET_SUN7I
config SYS_CONFIG_NAME
string
- default "sun5i"
+ default "sun7i"
endif
-if TARGET_SUN7I
+if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN7I
config SYS_CPU
string
@@ -52,8 +36,7 @@ config SYS_SOC
string
default "sunxi"
-config SYS_CONFIG_NAME
- string
- default "sun7i"
+config FTDFILE
+ string "Default ftdfile env setting for this board"
endif
diff --git a/board/svm_sc8xx/Kconfig b/board/svm_sc8xx/Kconfig
deleted file mode 100644
index 522b1a8..0000000
--- a/board/svm_sc8xx/Kconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-if TARGET_SVM_SC8XX
-
-config SYS_BOARD
- string
- default "svm_sc8xx"
-
-config SYS_CONFIG_NAME
- string
- default "svm_sc8xx"
-
-endif
diff --git a/board/svm_sc8xx/MAINTAINERS b/board/svm_sc8xx/MAINTAINERS
deleted file mode 100644
index c19bcae..0000000
--- a/board/svm_sc8xx/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-SVM_SC8XX BOARD
-M: John Zhan <zhanz@sinovee.com>
-S: Orphan (since 2014-06)
-F: board/svm_sc8xx/
-F: include/configs/svm_sc8xx.h
-F: configs/svm_sc8xx_defconfig
diff --git a/board/svm_sc8xx/Makefile b/board/svm_sc8xx/Makefile
deleted file mode 100644
index 4c0b4a3..0000000
--- a/board/svm_sc8xx/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = svm_sc8xx.o flash.o
diff --git a/board/svm_sc8xx/flash.c b/board/svm_sc8xx/flash.c
deleted file mode 100644
index 8a04de8..0000000
--- a/board/svm_sc8xx/flash.c
+++ /dev/null
@@ -1,666 +0,0 @@
-/*
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-#ifndef CONFIG_ENV_ADDR
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#endif
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word(flash_info_t *info, ulong dest, ulong data);
-
-#ifdef CONFIG_BOOT_8B
-static int my_in_8(unsigned char *addr);
-static void my_out_8(unsigned char *addr, int val);
-#endif
-#ifdef CONFIG_BOOT_16B
-static int my_in_be16(unsigned short *addr);
-static void my_out_be16(unsigned short *addr, int val);
-#endif
-#ifdef CONFIG_BOOT_32B
-static unsigned my_in_be32(unsigned *addr);
-static void my_out_be32(unsigned *addr, int val);
-#endif
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- unsigned long size_b0, size_b1;
- int i;
-
- size_b0 = 0;
- size_b1 = 0;
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
-#ifdef CONFIG_SYS_DOC_BASE
-#ifndef CONFIG_FEL8xx_AT
- /* 32k bytes */
- memctl->memc_or5 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC);
- memctl->memc_br5 = CONFIG_SYS_DOC_BASE | 0x401;
-#else
- /* 32k bytes */
- memctl->memc_or3 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC);
- memctl->memc_br3 = CONFIG_SYS_DOC_BASE | 0x401;
-#endif
-#endif
-#if defined(CONFIG_BOOT_8B)
- size_b0 = 0x80000; /* 512 K */
-
- flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM040;
- flash_info[0].sector_count = 8;
- flash_info[0].size = 0x00080000;
-
- /* set up sector start address table */
- for (i = 0; i < flash_info[0].sector_count; i++)
- flash_info[0].start[i] = 0x40000000 + (i * 0x10000);
-
- /* protect all sectors */
- for (i = 0; i < flash_info[0].sector_count; i++)
- flash_info[0].protect[i] = 0x1;
-
-#elif defined(CONFIG_BOOT_16B)
- size_b0 = 0x400000; /* 4MB , assume AMD29LV320B */
-
- flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM320B;
- flash_info[0].sector_count = 67;
- flash_info[0].size = 0x00400000;
-
- /* set up sector start address table */
- flash_info[0].start[0] = 0x40000000;
- flash_info[0].start[1] = 0x40000000 + 0x4000;
- flash_info[0].start[2] = 0x40000000 + 0x6000;
- flash_info[0].start[3] = 0x40000000 + 0x8000;
-
- for (i = 4; i < flash_info[0].sector_count; i++) {
- flash_info[0].start[i] =
- 0x40000000 + 0x10000 + ((i - 4) * 0x10000);
- }
-
- /* protect all sectors */
- for (i = 0; i < flash_info[0].sector_count; i++)
- flash_info[0].protect[i] = 0x1;
-#endif
-
-#ifdef CONFIG_BOOT_32B
-
- /* Static FLASH Bank configuration here - FIXME XXX */
- size_b0 = flash_get_size((vu_long *) FLASH_BASE0_PRELIM,
- &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0 << 20);
- }
-
- size_b1 = flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
- &flash_info[1]);
-
- if (size_b1 > size_b0) {
- printf("## ERROR: "
- "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
- size_b1, size_b1 << 20, size_b0, size_b0 << 20);
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[0].sector_count = -1;
- flash_info[1].sector_count = -1;
- flash_info[0].size = 0;
- flash_info[1].size = 0;
-
- return 0;
- }
-
- /* Remap FLASH according to real size */
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH |
- (-size_b0 & OR_AM_MSK);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
- BR_MS_GPCM | BR_V;
-
- /* Re-do sizing to get full correct info */
- size_b0 = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE,
- &flash_info[0]);
-
- flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-#endif
-
- if (size_b1) {
- memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH |
- (-size_b1 & 0xFFFF8000);
- memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE +
- size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-
- /* Re-do sizing to get full correct info */
- size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE +
- size_b0), &flash_info[1]);
-
- flash_get_offsets(CONFIG_SYS_FLASH_BASE + size_b0,
- &flash_info[1]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[1]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[1]);
-#endif
- } else {
- memctl->memc_br1 = 0; /* invalidate bank */
-
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].sector_count = -1;
- }
-
- flash_info[0].size = size_b0;
- flash_info[1].size = size_b1;
-
-
-#endif /* CONFIG_BOOT_32B */
-
- return size_b0 + size_b1;
-}
-
-
-void flash_print_info(flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- printf("AMD ");
- break;
- case FLASH_MAN_FUJ:
- printf("FUJITSU ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B:
- printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T:
- printf("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B:
- printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T:
- printf("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B:
- printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T:
- printf("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B:
- printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T:
- printf("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- break;
- }
-
- printf(" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf("\n");
- return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-int flash_erase(flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long *) (info->start[0]);
- int flag, prot, sect, l_sect, in_mid, in_did;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN)
- printf("- missing\n");
- else
- printf("- no sectors to erase\n");
-
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect])
- prot++;
- }
-
- if (prot) {
- printf("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
-#if defined(CONFIG_BOOT_8B)
- my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa);
- my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55);
- my_out_8((unsigned char *)((ulong)addr + 0x555), 0x90);
-
- in_mid = my_in_8((unsigned char *)addr);
- in_did = my_in_8((unsigned char *)((ulong)addr + 1));
-
- printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did);
-
- my_out_8((unsigned char *)addr, 0xf0);
- udelay(1);
-
- my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa);
- my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55);
- my_out_8((unsigned char *)((ulong)addr + 0x555), 0x80);
- my_out_8((unsigned char *)((ulong)addr + 0x555), 0xaa);
- my_out_8((unsigned char *)((ulong)addr + 0x2aa), 0x55);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long *) (info->start[sect]);
- /*addr[0] = 0x00300030; */
- my_out_8((unsigned char *)((ulong)addr), 0x30);
- l_sect = sect;
- }
- }
-#elif defined(CONFIG_BOOT_16B)
- my_out_be16((unsigned short *)((ulong)addr + (0xaaa)), 0xaa);
- my_out_be16((unsigned short *)((ulong)addr + (0x554)), 0x55);
- my_out_be16((unsigned short *)((ulong)addr + (0xaaa)), 0x90);
- in_mid = my_in_be16((unsigned short *)addr);
- in_did = my_in_be16((unsigned short *)((ulong)addr + 2));
- printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did);
- my_out_be16((unsigned short *)addr, 0xf0);
- udelay(1);
- my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa);
- my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55);
- my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0x80);
- my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa);
- my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55);
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long *) (info->start[sect]);
- my_out_be16((unsigned short *)((ulong)addr), 0x30);
- l_sect = sect;
- }
- }
-
-#elif defined(CONFIG_BOOT_32B)
- my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa);
- my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55);
- my_out_be32((unsigned *)((ulong)addr + 0x1554), 0x90);
-
- in_mid = my_in_be32((unsigned *)addr);
- in_did = my_in_be32((unsigned *)((ulong)addr + 4));
-
- printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did);
-
- my_out_be32((unsigned *) addr, 0xf0);
- udelay(1);
-
- my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa);
- my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55);
- my_out_be32((unsigned *)((ulong)addr + 0x1554), 0x80);
- my_out_be32((unsigned *)((ulong)addr + 0x1554), 0xaa);
- my_out_be32((unsigned *)((ulong)addr + 0xaa8), 0x55);
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long *) (info->start[sect]);
- my_out_be32((unsigned *)((ulong)addr), 0x00300030);
- l_sect = sect;
- }
- }
-
-#else
-#error CONFIG_BOOT_(size)B missing.
-#endif
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay(1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer(0);
- last = start;
- addr = (vu_long *) (info->start[l_sect]);
-#if defined(CONFIG_BOOT_8B)
- while ((my_in_8((unsigned char *) addr) & 0x80) != 0x80)
-#elif defined(CONFIG_BOOT_16B)
- while ((my_in_be16((unsigned short *) addr) & 0x0080) != 0x0080)
-#elif defined(CONFIG_BOOT_32B)
- while ((my_in_be32((unsigned *) addr) & 0x00800080) != 0x00800080)
-#else
-#error CONFIG_BOOT_(size)B missing.
-#endif
- {
- now = get_timer(start);
- if (now > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc('.');
- last = now;
- }
- }
-DONE:
- /* reset to read mode */
- addr = (volatile unsigned long *) info->start[0];
-
-#if defined(CONFIG_BOOT_8B)
- my_out_8((unsigned char *) addr, 0xf0);
-#elif defined(CONFIG_BOOT_16B)
- my_out_be16((unsigned short *) addr, 0x00f0);
-#elif defined(CONFIG_BOOT_32B)
- my_out_be32((unsigned *) addr, 0x00F000F0); /* reset bank */
-#else
-#error CONFIG_BOOT_(size)B missing.
-#endif
- printf(" done\n");
- return 0;
-}
-
-/*
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- l = addr - wp;
-
- if (l != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- rc = write_word(info, wp, data);
-
- if (rc != 0)
- return rc;
-
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i)
- data = (data << 8) | *src++;
-
- rc = write_word(info, wp, data);
-
- if (rc != 0)
- return rc;
-
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0)
- return 0;
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp)
- data = (data << 8) | (*(uchar *) cp);
-
- return write_word(info, wp, data);
-}
-
-/*
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word(flash_info_t *info, ulong dest, ulong data)
-{
- ulong addr = (ulong) (info->start[0]);
- ulong start;
- int flag;
- ulong i;
- int data_short[2];
-
- /* Check if Flash is (sufficiently) erased */
- if (((ulong)*(ulong *)dest & data) != data)
- return 2;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-#if defined(CONFIG_BOOT_8B)
-#ifdef DEBUG
- {
- int in_mid, in_did;
-
- my_out_8((unsigned char *) (addr + 0x555), 0xaa);
- my_out_8((unsigned char *) (addr + 0x2aa), 0x55);
- my_out_8((unsigned char *) (addr + 0x555), 0x90);
-
- in_mid = my_in_8((unsigned char *) addr);
- in_did = my_in_8((unsigned char *) (addr + 1));
-
- printf(" man ID=0x%x, dev ID=0x%x.\n", in_mid, in_did);
-
- my_out_8((unsigned char *) addr, 0xf0);
- udelay(1);
- }
-#endif
- {
- int data_ch[4];
-
- data_ch[0] = (int) ((data >> 24) & 0xff);
- data_ch[1] = (int) ((data >> 16) & 0xff);
- data_ch[2] = (int) ((data >> 8) & 0xff);
- data_ch[3] = (int) (data & 0xff);
-
- for (i = 0; i < 4; i++) {
- my_out_8((unsigned char *) (addr + 0x555), 0xaa);
- my_out_8((unsigned char *) (addr + 0x2aa), 0x55);
- my_out_8((unsigned char *) (addr + 0x555), 0xa0);
- my_out_8((unsigned char *) (dest + i), data_ch[i]);
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer(0);
- while ((my_in_8((unsigned char *)(dest + i))) !=
- (data_ch[i])) {
- if (get_timer(start) >
- CONFIG_SYS_FLASH_WRITE_TOUT) {
- return 1;
- }
- }
- } /* for */
- }
-#elif defined(CONFIG_BOOT_16B)
- data_short[0] = (int) (data >> 16) & 0xffff;
- data_short[1] = (int) data & 0xffff;
- for (i = 0; i < 2; i++) {
- my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xaa);
- my_out_be16((unsigned short *)((ulong)addr + 0x554), 0x55);
- my_out_be16((unsigned short *)((ulong)addr + 0xaaa), 0xa0);
- my_out_be16((unsigned short *)(dest + (i * 2)),
- data_short[i]);
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer(0);
- while ((my_in_be16((unsigned short *)(dest + (i * 2)))) !=
- (data_short[i])) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
- return 1;
- }
- }
-#elif defined(CONFIG_BOOT_32B)
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00A000A0;
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer(0);
- while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
- return 1;
- }
-#endif
- return 0;
-}
-
-#ifdef CONFIG_BOOT_8B
-static int my_in_8(unsigned char *addr)
-{
- int ret;
- __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr));
-
- return ret;
-}
-
-static void my_out_8(unsigned char *addr, int val)
-{
- __asm__ __volatile__("stb%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val));
-}
-#endif
-#ifdef CONFIG_BOOT_16B
-static int my_in_be16(unsigned short *addr)
-{
- int ret;
- __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr));
-
- return ret;
-}
-
-static void my_out_be16(unsigned short *addr, int val)
-{
- __asm__ __volatile__("sth%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val));
-}
-#endif
-#ifdef CONFIG_BOOT_32B
-static unsigned my_in_be32(unsigned *addr)
-{
- unsigned ret;
- __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio":"=r"(ret):"m"(*addr));
-
- return ret;
-}
-
-static void my_out_be32(unsigned *addr, int val)
-{
- __asm__ __volatile__("stw%U0%X0 %1,%0; eieio":"=m"(*addr):"r"(val));
-}
-#endif
diff --git a/board/svm_sc8xx/svm_sc8xx.c b/board/svm_sc8xx/svm_sc8xx.c
deleted file mode 100644
index 5db4850..0000000
--- a/board/svm_sc8xx/svm_sc8xx.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * (C) Copyright 2000, 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-/* ------------------------------------------------------------------------- */
-const uint sdram_table[] =
-{
-/*-----------------
- UPM A contents:
------------------ */
-/*---------------------------------------------------
- Read Single Beat Cycle. Offset 0 in the RAM array.
----------------------------------------------------- */
-0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00 ,
-0x1ff77c47, 0x1ff77c35, 0xefeabc34, 0x1fb57c35 ,
-/*------------------------------------------------
- Read Burst Cycle. Offset 0x8 in the RAM array.
------------------------------------------------- */
-0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
-0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
-0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-/*-------------------------------------------------------
- Write Single Beat Cycle. Offset 0x18 in the RAM array
-------------------------------------------------------- */
-0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47 ,
-0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff ,
-/*-------------------------------------------------
- Write Burst Cycle. Offset 0x20 in the RAM array
-------------------------------------------------- */
-0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
-0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xffffffff,
-0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff ,
-0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff ,
-/*------------------------------------------------------------------------
- Periodic Timer Expired. For DRAM refresh. Offset 0x30 in the RAM array
------------------------------------------------------------------------- */
-0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff,
-0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff ,
-/*-----------
-* Exception:
-* ----------- */
-0x7ffefc07, 0xffffffff, 0xffffffff, 0xffffffff ,
-};
-
-/* ------------------------------------------------------------------------- */
-/*
- * Check Board Identity:
- *
- * Test ID string (SVM8...)
- *
- * Return 1 for "SC8xx" type, 0 else.
- */
-
-int checkboard(void)
-{
- char buf[64];
- int i;
- int l = getenv_f("serial#", buf, sizeof(buf));
-
- if (l < 0 || strncmp(buf, "SVM8", 4)) {
- printf("### No HW ID - assuming SVM SC8xx\n");
- return (0);
- }
-
- for (i = 0; i < l; ++i) {
- if (buf[i] == ' ')
- break;
- putc(buf[i]);
- }
-
- putc('\n');
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size_b0 = 0;
-
- upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-#if defined (CONFIG_SDRAM_16M)
- memctl->memc_mamr = 0x00802114 | CONFIG_SYS_MxMR_PTx;
- memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
- udelay(1);
- memctl->memc_mcr = 0x80002830;
- udelay(1);
- memctl->memc_mar = 0x00000088;
- udelay(1);
- memctl->memc_mcr = 0x80002106;
- udelay(1);
- memctl->memc_or1 = 0xff000a00;
- size_b0 = 0x01000000;
-#elif defined (CONFIG_SDRAM_32M)
- memctl->memc_mamr = 0x00904114 | CONFIG_SYS_MxMR_PTx;
- memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
- udelay(1);
- memctl->memc_mcr = 0x80002830;
- udelay(1);
- memctl->memc_mar = 0x00000088;
- udelay(1);
- memctl->memc_mcr = 0x80002106;
- udelay(1);
- memctl->memc_or1 = 0xfe000a00;
- size_b0 = 0x02000000;
-#elif defined (CONFIG_SDRAM_64M)
- memctl->memc_mamr = 0x00a04114 | CONFIG_SYS_MxMR_PTx;
- memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
- udelay(1);
- memctl->memc_mcr = 0x80002830;
- udelay(1);
- memctl->memc_mar = 0x00000088;
- udelay(1);
- memctl->memc_mcr = 0x80002106;
- udelay(1);
- memctl->memc_or1 = 0xfc000a00;
- size_b0 = 0x04000000;
-#else
-#error SDRAM size configuration missing.
-#endif
- memctl->memc_br1 = 0x00000081;
- udelay(200);
- return (size_b0 );
-}
-
-#if defined(CONFIG_CMD_DOC)
-void doc_init (void)
-{
- doc_probe (CONFIG_SYS_DOC_BASE);
-}
-#endif
diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds
deleted file mode 100644
index df564e9..0000000
--- a/board/svm_sc8xx/u-boot.lds
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- lib/built-in.o (.text*)
- net/built-in.o (.text*)
- arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
- arch/powerpc/lib/built-in.o (.text*)
- board/svm_sc8xx/built-in.o (.text*)
- *(.text.*printf)
- *(.text.do_mem_*)
- *(.text.flash*)
- *(.text.run_command)
- *(.text.main_loop)
- *(.text.srec_decode)
-
- . = env_offset;
- common/env_embedded.o (.ppcenv*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/svm_sc8xx/u-boot.lds.debug b/board/svm_sc8xx/u-boot.lds.debug
deleted file mode 100644
index b2c562c..0000000
--- a/board/svm_sc8xx/u-boot.lds.debug
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
diff --git a/board/ti/omap5912osk/MAINTAINERS b/board/ti/omap5912osk/MAINTAINERS
deleted file mode 100644
index 43ffb9b..0000000
--- a/board/ti/omap5912osk/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-OMAP5912OSK BOARD
-M: Rishi Bhattacharya <rishi@ti.com>
-S: Maintained
-F: board/ti/omap5912osk/
-F: include/configs/omap5912osk.h
-F: configs/omap5912osk_defconfig
diff --git a/board/ti/omap5912osk/Makefile b/board/ti/omap5912osk/Makefile
deleted file mode 100644
index d7c0ebd..0000000
--- a/board/ti/omap5912osk/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := omap5912osk.o
-obj-y += lowlevel_init.o
diff --git a/board/ti/omap5912osk/config.mk b/board/ti/omap5912osk/config.mk
deleted file mode 100644
index 5b8d952..0000000
--- a/board/ti/omap5912osk/config.mk
+++ /dev/null
@@ -1,30 +0,0 @@
-#
-# (C) Copyright 2002-2004
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2003
-# Texas Instruments, <www.ti.com>
-# Kshitij Gupta <Kshitij@ti.com>
-#
-# (C) Copyright 2004
-# Texas Instruments, <www.ti.com>
-# Rishi Bhattacharya <rishi@ti.com>
-#
-# TI OSK board with OMAP5912 (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# OSK has 1 bank of 32 MB SDRAM
-# Physical Address:
-# 1000'0000 to 1200'0000
-#
-#
-# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
-# (mem base + reserved)
-#
-# When running from RAM use address 1108'0000, otherwise when
-# booting from NOR flash link to address 0000'0000.
-#
-
-CONFIG_SYS_TEXT_BASE = 0x00000000
-#CONFIG_SYS_TEXT_BASE = 0x11080000
diff --git a/board/ti/omap5912osk/lowlevel_init.S b/board/ti/omap5912osk/lowlevel_init.S
deleted file mode 100644
index e05a1c7..0000000
--- a/board/ti/omap5912osk/lowlevel_init.S
+++ /dev/null
@@ -1,477 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-
-#if defined(CONFIG_OMAP1610)
-#include <./configs/omap1510.h>
-#endif
-
-.globl lowlevel_init
-lowlevel_init:
-
- /*------------------------------------------------------*
- * Ensure i-cache is enabled *
- * To configure TC regs without fetching instruction *
- *------------------------------------------------------*/
- mrc p15, 0, r0, c1, c0
- orr r0, r0, #0x1000
- mcr p15, 0, r0, c1, c0
-
- /*------------------------------------------------------*
- *mask all IRQs by setting all bits in the INTMR default*
- *------------------------------------------------------*/
- mov r1, #0xffffffff
- ldr r0, =REG_IHL1_MIR
- str r1, [r0]
- ldr r0, =REG_IHL2_MIR
- str r1, [r0]
-
- /*------------------------------------------------------*
- * Set up ARM CLM registers (IDLECT1) *
- *------------------------------------------------------*/
- ldr r0, REG_ARM_IDLECT1
- ldr r1, VAL_ARM_IDLECT1
- str r1, [r0]
-
- /*------------------------------------------------------*
- * Set up ARM CLM registers (IDLECT2) *
- *------------------------------------------------------*/
- ldr r0, REG_ARM_IDLECT2
- ldr r1, VAL_ARM_IDLECT2
- str r1, [r0]
-
- /*------------------------------------------------------*
- * Set up ARM CLM registers (IDLECT3) *
- *------------------------------------------------------*/
- ldr r0, REG_ARM_IDLECT3
- ldr r1, VAL_ARM_IDLECT3
- str r1, [r0]
-
- mov r1, #0x01 /* PER_EN bit */
- ldr r0, REG_ARM_RSTCT2
- strh r1, [r0] /* CLKM; Peripheral reset. */
-
- /* Set CLKM to Sync-Scalable */
- mov r1, #0x1000
- ldr r0, REG_ARM_SYSST
-
- mov r2, #0
-1: cmp r2, #1
- streqh r1, [r0]
- add r2, r2, #1
- cmp r2, #0x100 /* wait for any bubbles to finish */
- bne 1b
-
- ldr r1, VAL_ARM_CKCTL
- ldr r0, REG_ARM_CKCTL
- strh r1, [r0]
-
- /* a few nops to let settle */
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
- /* setup DPLL 1 */
- /* Ramp up the clock to 96Mhz */
- ldr r1, VAL_DPLL1_CTL
- ldr r0, REG_DPLL1_CTL
- strh r1, [r0]
- ands r1, r1, #0x10 /* Check if PLL is enabled. */
- beq lock_end /* Do not look for lock if BYPASS selected */
-2:
- ldrh r1, [r0]
- ands r1, r1, #0x01 /* Check the LOCK bit.*/
- beq 2b /* loop until bit goes hi. */
-lock_end:
-
- /*------------------------------------------------------*
- * Turn off the watchdog during init... *
- *------------------------------------------------------*/
- ldr r0, REG_WATCHDOG
- ldr r1, WATCHDOG_VAL1
- str r1, [r0]
- ldr r1, WATCHDOG_VAL2
- str r1, [r0]
- ldr r0, REG_WSPRDOG
- ldr r1, WSPRDOG_VAL1
- str r1, [r0]
- ldr r0, REG_WWPSDOG
-
-watch1Wait:
- ldr r1, [r0]
- tst r1, #0x10
- bne watch1Wait
-
- ldr r0, REG_WSPRDOG
- ldr r1, WSPRDOG_VAL2
- str r1, [r0]
- ldr r0, REG_WWPSDOG
-watch2Wait:
- ldr r1, [r0]
- tst r1, #0x10
- bne watch2Wait
-
- /* Set memory timings corresponding to the new clock speed */
- ldr r3, VAL_SDRAM_CONFIG_SDF0
-
- /* Check execution location to determine current execution location
- * and branch to appropriate initialization code.
- */
- mov r0, #0x10000000 /* Load physical SDRAM base. */
- mov r1, pc /* Get current execution location. */
- cmp r1, r0 /* Compare. */
- bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */
-
- /* identify the device revision, -- TMX or TMP(TMS) */
- ldr r0, REG_DEVICE_ID
- ldr r1, [r0]
-
- ldr r0, VAL_DEVICE_ID_TMP
- mov r1, r1, lsl #15
- mov r1, r1, lsr #16
- cmp r0, r1
- bne skip_TMP_Patch
-
- /* Enable TMP/TMS device new features */
- mov r0, #1
- ldr r1, REG_TC_EMIFF_DOUBLER
- str r0, [r1]
-
- /* Enable new ac parameters */
- mov r0, #0x0b
- ldr r1, REG_SDRAM_CONFIG2
- str r0, [r1]
-
- ldr r3, VAL_SDRAM_CONFIG_SDF1
-
-skip_TMP_Patch:
-
- /*
- * Delay for SDRAM initialization.
- */
- mov r0, #0x1800 /* value should be checked */
-3:
- subs r0, r0, #0x1 /* Decrement count */
- bne 3b
-
- /*
- * Set SDRAM control values. Disable refresh before MRS command.
- */
-
- /* mobile ddr operation */
- ldr r0, REG_SDRAM_OPERATION
- mov r2, #07
- str r2, [r0]
-
- /* config register */
- ldr r0, REG_SDRAM_CONFIG
- str r3, [r0]
-
- /* manual command register */
- ldr r0, REG_SDRAM_MANUAL_CMD
-
- /* issue set cke high */
- mov r1, #CMD_SDRAM_CKE_SET_HIGH
- str r1, [r0]
-
- /* issue nop */
- mov r1, #CMD_SDRAM_NOP
- str r1, [r0]
-
- mov r2, #0x0100
-waitMDDR1:
- subs r2, r2, #1
- bne waitMDDR1 /* delay loop */
-
- /* issue precharge */
- mov r1, #CMD_SDRAM_PRECHARGE
- str r1, [r0]
-
- /* issue autorefresh x 2 */
- mov r1, #CMD_SDRAM_AUTOREFRESH
- str r1, [r0]
- str r1, [r0]
-
- /* mrs register ddr mobile */
- ldr r0, REG_SDRAM_MRS
- mov r1, #0x33
- str r1, [r0]
-
- /* emrs1 low-power register */
- ldr r0, REG_SDRAM_EMRS1
- /* self refresh on all banks */
- mov r1, #0
- str r1, [r0]
-
- ldr r0, REG_DLL_URD_CONTROL
- ldr r1, DLL_URD_CONTROL_VAL
- str r1, [r0]
-
- ldr r0, REG_DLL_LRD_CONTROL
- ldr r1, DLL_LRD_CONTROL_VAL
- str r1, [r0]
-
- ldr r0, REG_DLL_WRT_CONTROL
- ldr r1, DLL_WRT_CONTROL_VAL
- str r1, [r0]
-
- /* delay loop */
- mov r0, #0x0100
-waitMDDR2:
- subs r0, r0, #1
- bne waitMDDR2
-
- /*
- * Delay for SDRAM initialization.
- */
- mov r0, #0x1800
-4:
- subs r0, r0, #1 /* Decrement count. */
- bne 4b
- b common_tc
-
-skip_sdram:
- ldr r0, REG_SDRAM_CONFIG
- str r3, [r0]
-
-common_tc:
- /* slow interface */
- ldr r1, VAL_TC_EMIFS_CS0_CONFIG
- ldr r0, REG_TC_EMIFS_CS0_CONFIG
- str r1, [r0] /* Chip Select 0 */
-
- ldr r1, VAL_TC_EMIFS_CS1_CONFIG
- ldr r0, REG_TC_EMIFS_CS1_CONFIG
- str r1, [r0] /* Chip Select 1 */
-
- ldr r1, VAL_TC_EMIFS_CS3_CONFIG
- ldr r0, REG_TC_EMIFS_CS3_CONFIG
- str r1, [r0] /* Chip Select 3 */
-
- ldr r1, VAL_TC_EMIFS_DWS
- ldr r0, REG_TC_EMIFS_DWS
- str r1, [r0] /* Enable EMIFS.RDY for CS1 (ether) */
-
-#ifdef CONFIG_H2_OMAP1610
- /* inserting additional 2 clock cycle hold time for LAN */
- ldr r0, REG_TC_EMIFS_CS1_ADVANCED
- ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
- str r1, [r0]
-#endif
- /* Start MPU Timer 1 */
- ldr r0, REG_MPU_LOAD_TIMER
- ldr r1, VAL_MPU_LOAD_TIMER
- str r1, [r0]
-
- ldr r0, REG_MPU_CNTL_TIMER
- ldr r1, VAL_MPU_CNTL_TIMER
- str r1, [r0]
-
- /*
- * Setup a temporary stack
- */
- ldr sp, SRAM_STACK
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-
- /*
- * Save the old lr(passed in ip) and the current lr to stack
- */
- push {ip, lr}
-
- /*
- * go setup pll, mux, memory
- */
- bl s_init
- pop {ip, pc}
-
- /* back to arch calling code */
- mov pc, lr
-
- /* the literal pools origin */
- .ltorg
-
-REG_DEVICE_ID: /* 32 bits */
- .word 0xfffe2004
-REG_TC_EMIFS_CONFIG:
- .word 0xfffecc0c
-REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
- .word 0xfffecc10
-REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
- .word 0xfffecc14
-REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
- .word 0xfffecc18
-REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
- .word 0xfffecc1c
-REG_TC_EMIFS_DWS: /* 32 bits */
- .word 0xfffecc40
-#ifdef CONFIG_H2_OMAP1610
-REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
- .word 0xfffecc54
-#endif
-
-/* MPU clock/reset/power mode control registers */
-REG_ARM_CKCTL: /* 16 bits */
- .word 0xfffece00
-REG_ARM_IDLECT3: /* 16 bits */
- .word 0xfffece24
-REG_ARM_IDLECT2: /* 16 bits */
- .word 0xfffece08
-REG_ARM_IDLECT1: /* 16 bits */
- .word 0xfffece04
-REG_ARM_RSTCT2: /* 16 bits */
- .word 0xfffece14
-REG_ARM_SYSST: /* 16 bits */
- .word 0xfffece18
-
-/* DPLL control registers */
-REG_DPLL1_CTL: /* 16 bits */
- .word 0xfffecf00
-
-/* Watch Dog register */
-/* secure watchdog stop */
-REG_WSPRDOG:
- .word 0xfffeb048
-/* watchdog write pending */
-REG_WWPSDOG:
- .word 0xfffeb034
-
-WSPRDOG_VAL1:
- .word 0x0000aaaa
-WSPRDOG_VAL2:
- .word 0x00005555
-
-/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
- counter @8192 rows, 10 ns, 8 burst */
-REG_SDRAM_CONFIG:
- .word 0xfffecc20
-REG_SDRAM_CONFIG2:
- .word 0xfffecc3c
-REG_TC_EMIFF_DOUBLER: /* 32 bits */
- .word 0xfffecc60
-
-/* Operation register */
-REG_SDRAM_OPERATION:
- .word 0xfffecc80
-
-/* Manual command register */
-REG_SDRAM_MANUAL_CMD:
- .word 0xfffecc84
-
-/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
-REG_SDRAM_MRS:
- .word 0xfffecc70
-
-/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
-REG_SDRAM_EMRS1:
- .word 0xfffecc78
-
-/* WRT DLL register */
-REG_DLL_WRT_CONTROL:
- .word 0xfffecc68
-DLL_WRT_CONTROL_VAL:
- .word 0x03f00002 /* Phase of 72deg, write offset +31 */
-
-/* URD DLL register */
-REG_DLL_URD_CONTROL:
- .word 0xfffeccc0
-DLL_URD_CONTROL_VAL:
- .word 0x00800002 /* Phase of 72deg, read offset +31 */
-
-/* LRD DLL register */
-REG_DLL_LRD_CONTROL:
- .word 0xfffecccc
-DLL_LRD_CONTROL_VAL:
- .word 0x00800002 /* read offset +31 */
-
-REG_WATCHDOG:
- .word 0xfffec808
-WATCHDOG_VAL1:
- .word 0x000000f5
-WATCHDOG_VAL2:
- .word 0x000000a0
-
-REG_MPU_LOAD_TIMER:
- .word 0xfffec504
-REG_MPU_CNTL_TIMER:
- .word 0xfffec500
-VAL_MPU_LOAD_TIMER:
- .word 0xffffffff
-VAL_MPU_CNTL_TIMER:
- .word 0xffffffa1
-
-/* 96 MHz Samsung Mobile DDR */
-/* Original setting for TMX device */
-VAL_SDRAM_CONFIG_SDF0:
- .word 0x0014e6fe
-
-/* NEW_SYS_FREQ mode (valid only TMP/TMS devices) */
-VAL_SDRAM_CONFIG_SDF1:
- .word 0x0114e6fe
-
-VAL_ARM_CKCTL:
- .word 0x2000 /* was: 0x3000, now use CLK_REF for timer input */
-VAL_DPLL1_CTL:
- .word 0x2830
-
-#ifdef CONFIG_OSK_OMAP5912
-VAL_TC_EMIFS_CS0_CONFIG:
- .word 0x002130b0
-VAL_TC_EMIFS_CS1_CONFIG:
- .word 0x00001133
-VAL_TC_EMIFS_CS2_CONFIG:
- .word 0x000055f0
-VAL_TC_EMIFS_CS3_CONFIG:
- .word 0x88013141
-VAL_TC_EMIFS_DWS: /* Enable EMIFS.RDY for CS1 access (ether) */
- .word 0x000000c0
-VAL_DEVICE_ID_TMP: /* TMP/TMS=0xb65f, TMX=0xb58c */
- .word 0xb65f
-#endif
-
-#ifdef CONFIG_H2_OMAP1610
-VAL_TC_EMIFS_CS0_CONFIG:
- .word 0x00203331
-VAL_TC_EMIFS_CS1_CONFIG:
- .word 0x8180fff3
-VAL_TC_EMIFS_CS2_CONFIG:
- .word 0xf800f22a
-VAL_TC_EMIFS_CS3_CONFIG:
- .word 0x88013141
-VAL_TC_EMIFS_CS1_ADVANCED:
- .word 0x00000022
-#endif
-
-VAL_ARM_IDLECT1:
- .word 0x00000400
-VAL_ARM_IDLECT2:
- .word 0x00000886
-VAL_ARM_IDLECT3:
- .word 0x00000015
-
-SRAM_STACK:
- .word CONFIG_SYS_INIT_SP_ADDR
-
-/* command values */
-.equ CMD_SDRAM_NOP, 0x00000000
-.equ CMD_SDRAM_PRECHARGE, 0x00000001
-.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
-.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007
diff --git a/board/ti/omap5912osk/omap5912osk.c b/board/ti/omap5912osk/omap5912osk.c
deleted file mode 100644
index 88a7310..0000000
--- a/board/ti/omap5912osk/omap5912osk.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Rishi Bhattacharya <rishi@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#if defined(CONFIG_OMAP1610)
-#include <./configs/omap1510.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void flash__init (void);
-void ether__init (void);
-void set_muxconf_regs (void);
-void peripheral_power_enable (void);
-
-#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
-
-static inline void delay (unsigned long loops)
-{
- __asm__ volatile ("1:\n"
- "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
- gd->bd->bi_arch_number = MACH_TYPE_OMAP_OSK;
-
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x10000100;
-
- flash__init();
- ether__init();
-
- return 0;
-}
-
-void s_init(void)
-{
- /* Configure MUX settings */
- set_muxconf_regs ();
- peripheral_power_enable ();
-
-/* this speeds up your boot a quite a bit. However to make it
- * work, you need make sure your kernel startup flush bug is fixed.
- * ... rkw ...
- */
- icache_enable ();
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-void flash__init (void)
-{
-#define EMIFS_GlB_Config_REG 0xfffecc0c
- unsigned int regval;
- regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
- /* Turn off write protection for flash devices. */
- regval = regval | 0x0001;
- *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
-}
-/*************************************************************
- Routine:ether__init
- Description: take the Ethernet controller out of reset and wait
- for the EEPROM load to complete.
-*************************************************************/
-void ether__init (void)
-{
-#define ETH_CONTROL_REG 0x0480000b
- int i;
-
- *((volatile unsigned short *) 0xfffece08) = 0x03FF;
- *((volatile unsigned short *) 0xfffb3824) = 0x8000;
- *((volatile unsigned short *) 0xfffb3830) = 0x0000;
- *((volatile unsigned short *) 0xfffb3834) = 0x0009;
- *((volatile unsigned short *) 0xfffb3838) = 0x0009;
- *((volatile unsigned short *) 0xfffb3818) = 0x0002;
- *((volatile unsigned short *) 0xfffb382C) = 0x0048;
- *((volatile unsigned short *) 0xfffb3824) = 0x8603;
- udelay (3);
- for (i=0;i<2000;i++);
- *((volatile unsigned short *) 0xfffb381C) = 0x6610;
- udelay (30);
- for (i=0;i<10000;i++);
-
- *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
- udelay (3);
-
-
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
-
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-/******************************************************
- Routine: set_muxconf_regs
- Description: Setting up the configuration Mux registers
- specific to the hardware
-*******************************************************/
-void set_muxconf_regs (void)
-{
- volatile unsigned int *MuxConfReg;
- /* set each registers to its reset value; */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
- /* setup for UART1 */
- *MuxConfReg &= ~(0x02000000); /* bit 25 */
- /* setup for UART2 */
- *MuxConfReg &= ~(0x01000000); /* bit 24 */
- /* Disable Uwire CS Hi-Z */
- *MuxConfReg |= 0x08000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
- /*setup mux for UART3 */
- *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */
- *MuxConfReg &= ~0x0000003e;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
- /* Disable Uwire CS Hi-Z */
- *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
- /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */
- /* hardware will actually use TX and RTS based on bit 25 in */
- /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */
- *MuxConfReg |= 0x00201000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
- /* setup for UART2 */
- /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */
- /* hardware will actually use TX and RTS based on bit 24 in */
- /* FUNC_MUX_CTRL_0. */
- *MuxConfReg |= 0x09000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_D);
- *MuxConfReg |= 0x00000020;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
- *MuxConfReg = 0x00000000;
- /* mux setup for SD/MMC driver */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
- *MuxConfReg &= 0xFFFE0FFF;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
- /* bit 13 for MMC2 XOR_CLK */
- *MuxConfReg &= ~(0x00002000);
- /* bit 29 for UART 1 */
- *MuxConfReg &= ~(0x00002000);
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
- /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
- *MuxConfReg |= 0x000C0000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
- *MuxConfReg &= ~(0x00000070);
- *MuxConfReg &= ~(0x00000008);
- *MuxConfReg |= 0x00000003;
- *MuxConfReg |= 0x00000180;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
- /* bit 17, software controls VBUS */
- *MuxConfReg &= ~(0x00020000);
- /* Enable USB 48 and 12M clocks */
- *MuxConfReg |= 0x00000200;
- *MuxConfReg &= ~(0x00000180);
- /*2.75V for MMCSDIO1 */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
- *MuxConfReg = 0x00001FE7;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
- *MuxConfReg = 0x00000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
- *MuxConfReg = 0x00000000;
- /* Turn on UART2 48 MHZ clock */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
- *MuxConfReg |= 0x40000000;
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
- /* setup for USB VBus detection OMAP161x */
- *MuxConfReg |= 0x00040000; /* bit 18 */
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
- /* PullUps for SD/MMC driver */
- *MuxConfReg |= ~(0xFFFE0FFF);
- MuxConfReg =
- (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
- *MuxConfReg = COMP_MODE_ENABLE;
-}
-
-/******************************************************
- Routine: peripheral_power_enable
- Description: Enable the power for UART1
-*******************************************************/
-void peripheral_power_enable (void)
-{
-#define UART1_48MHZ_ENABLE ((unsigned short)0x0200)
-#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834)
-
- *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- puts("Board: OSK5912");
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return (0);
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_LAN91C96
- rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-#endif
- return rc;
-}
-#endif
diff --git a/board/tqc/tqm8272/nand.c b/board/tqc/tqm8272/nand.c
index 4925b8d..7fb2dfa 100644
--- a/board/tqc/tqm8272/nand.c
+++ b/board/tqc/tqm8272/nand.c
@@ -188,6 +188,7 @@ static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int
*base = buf[i];
}
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
@@ -199,6 +200,7 @@ static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int
return -1;
return 0;
}
+#endif
#endif /* #ifndef CONFIG_NAND_SPL */
void board_nand_select_device(struct nand_chip *nand, int chip)
@@ -247,8 +249,10 @@ int board_nand_init(struct nand_chip *nand)
#ifndef CONFIG_NAND_SPL
nand->write_buf = tqm8272_write_buf;
nand->read_buf = tqm8272_read_buf;
+#if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
nand->verify_buf = tqm8272_verify_buf;
#endif
+#endif
/*
* Select required NAND chip
diff --git a/board/tqc/tqma6/Makefile b/board/tqc/tqma6/Makefile
new file mode 100644
index 0000000..9ee6920
--- /dev/null
+++ b/board/tqc/tqma6/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2014, Markus Niebel <Markus.Niebel@tq-group.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := tqma6.o
+
+obj-$(CONFIG_MBA6) += tqma6_mba6.o
diff --git a/board/tqc/tqma6/README b/board/tqc/tqma6/README
new file mode 100644
index 0000000..2c012e7
--- /dev/null
+++ b/board/tqc/tqma6/README
@@ -0,0 +1,35 @@
+U-Boot for the TQ Systems TQMa6 modules
+
+This file contains information for the port of
+U-Boot to the TQ Systems TQMa6 modules.
+
+1. Boot source
+--------------
+
+The following boot source is supported:
+
+- SD/eMMC
+- SPI NOR
+
+2. Building
+------------
+
+To build U-Boot for the TQ Systems TQMa6 modules:
+
+ make tqma6<x>_<baseboard>_<boot>_config
+ make
+
+x is a placeholder for the CPU variant
+q - means i.MX6Q/D: TQMa6Q (i.MX6Q) and TQMa6D (i.MX6D)
+s - means i.MX6S: TQMa6S (i.MX6S)
+
+baseboard is a placeholder for the boot device
+mmc - means eMMC
+spi - mean SPI NOR
+
+This gives the following configurations:
+
+tqma6q_mba6_mmc_config
+tqma6q_mba6_spi_config
+tqma6s_mba6_mmc_config
+tqma6s_mba6_spi_config
diff --git a/board/tqc/tqma6/clocks.cfg b/board/tqc/tqma6/clocks.cfg
new file mode 100644
index 0000000..d9dd273
--- /dev/null
+++ b/board/tqc/tqma6/clocks.cfg
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ * Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0x00FFF300
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c
new file mode 100644
index 0000000..b552bb8
--- /dev/null
+++ b/board/tqc/tqma6/tqma6.c
@@ -0,0 +1,262 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
+ * Author: Markus Niebel <markus.niebel@tq-group.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <libfdt.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <power/pfuze100_pmic.h>
+#include <power/pmic.h>
+
+#include "tqma6_bb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+static const uint16_t tqma6_emmc_dsr = 0x0100;
+
+/* eMMC on USDHCI3 always present */
+static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
+ NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
+ /* eMMC reset */
+ NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL),
+};
+
+/*
+ * According to board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 eMMC (SD3) on TQMa6
+ * mmc1 .. n optional slots used on baseboard
+ */
+struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
+ .esdhc_base = USDHC3_BASE_ADDR,
+ .max_bus_width = 8,
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+ /* eMMC/uSDHC3 is always present */
+ ret = 1;
+ else
+ ret = tqma6_bb_board_mmc_getcd(mmc);
+
+ return ret;
+}
+
+int board_mmc_getwp(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+ /* eMMC/uSDHC3 is always present */
+ ret = 0;
+ else
+ ret = tqma6_bb_board_mmc_getwp(mmc);
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
+ ARRAY_SIZE(tqma6_usdhc3_pads));
+ tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
+ puts("Warning: failed to initialize eMMC dev\n");
+ } else {
+ struct mmc *mmc = find_mmc_device(0);
+ if (mmc)
+ mmc_set_dsr(mmc, tqma6_emmc_dsr);
+ }
+
+ tqma6_bb_board_mmc_init(bis);
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
+ /* SS1 */
+ NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
+};
+
+static unsigned const tqma6_ecspi1_cs[] = {
+ IMX_GPIO_NR(3, 19),
+};
+
+static void tqma6_iomuxc_spi(void)
+{
+ unsigned i;
+
+ for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
+ gpio_direction_output(tqma6_ecspi1_cs[i], 1);
+ imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
+ ARRAY_SIZE(tqma6_ecspi1_pads));
+}
+
+static struct i2c_pads_info tqma6_i2c3_pads = {
+ /* I2C3: on board LM75, M24C64, */
+ .scl = {
+ .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL,
+ I2C_PAD_CTRL),
+ .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05,
+ I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(1, 5)
+ },
+ .sda = {
+ .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA,
+ I2C_PAD_CTRL),
+ .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06,
+ I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+};
+
+static void tqma6_setup_i2c(void)
+{
+ /* use logical index for bus, e.g. I2C1 -> 0 */
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
+}
+
+int board_early_init_f(void)
+{
+ return tqma6_bb_board_early_init_f();
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ tqma6_iomuxc_spi();
+ tqma6_setup_i2c();
+
+ tqma6_bb_board_init();
+
+ return 0;
+}
+
+static const char *tqma6_get_boardname(void)
+{
+ u32 cpurev = get_cpu_rev();
+
+ switch ((cpurev & 0xFF000) >> 12) {
+ case MXC_CPU_MX6SOLO:
+ return "TQMa6S";
+ break;
+ case MXC_CPU_MX6DL:
+ return "TQMa6DL";
+ break;
+ case MXC_CPU_MX6D:
+ return "TQMa6D";
+ break;
+ case MXC_CPU_MX6Q:
+ return "TQMa6Q";
+ break;
+ default:
+ return "??";
+ };
+}
+
+int board_late_init(void)
+{
+ struct pmic *p;
+ u32 reg;
+
+ setenv("board_name", tqma6_get_boardname());
+
+ /*
+ * configure PFUZE100 PMIC:
+ * TODO: should go to power_init_board if bus switching is
+ * fixed in generic power code
+ */
+ power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
+ p = pmic_get("PFUZE100");
+ if (p && !pmic_probe(p)) {
+ pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+ }
+
+ tqma6_bb_board_late_init();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: %s on a %s\n", tqma6_get_boardname(),
+ tqma6_bb_get_boardname());
+ return 0;
+}
+
+/*
+ * Device Tree Support
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ /* bring in eMMC dsr settings */
+ do_fixup_by_path_u32(blob,
+ "/soc/aips-bus@02100000/usdhc@02198000",
+ "dsr", tqma6_emmc_dsr, 2);
+ tqma6_bb_ft_board_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/tqc/tqma6/tqma6_bb.h b/board/tqc/tqma6/tqma6_bb.h
new file mode 100644
index 0000000..9d072d2
--- /dev/null
+++ b/board/tqc/tqma6/tqma6_bb.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2013, 2014 TQ Systems
+ * Author: Markus Niebel <markus.niebel@tq-group.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __TQMA6_BB__
+#define __TQMA6_BB
+
+#include <common.h>
+
+int tqma6_bb_board_mmc_getwp(struct mmc *mmc);
+int tqma6_bb_board_mmc_getcd(struct mmc *mmc);
+int tqma6_bb_board_mmc_init(bd_t *bis);
+
+int tqma6_bb_board_early_init_f(void);
+int tqma6_bb_board_init(void);
+int tqma6_bb_board_late_init(void);
+int tqma6_bb_checkboard(void);
+
+const char *tqma6_bb_get_boardname(void);
+/*
+ * Device Tree Support
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+void tqma6_bb_ft_board_setup(void *blob, bd_t *bd);
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+
+#endif
diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c
new file mode 100644
index 0000000..fd59287
--- /dev/null
+++ b/board/tqc/tqma6/tqma6_mba6.c
@@ -0,0 +1,361 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
+ * Author: Markus Niebel <markus.niebel@tq-group.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
+
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <libfdt.h>
+#include <malloc.h>
+#include <i2c.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+
+#include "tqma6_bb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#if defined(CONFIG_MX6Q)
+
+#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790
+#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac
+
+#elif defined(CONFIG_MX6S)
+
+#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768
+#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788
+
+#else
+
+#error "need to define target CPU"
+
+#endif
+
+#define ENET_RX_PAD_CTRL (PAD_CTL_DSE_34ohm)
+#define ENET_TX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_34ohm)
+#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_34ohm)
+#define ENET_MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_60ohm)
+
+/* disable on die termination for RGMII */
+#define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000
+/* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */
+#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V 0x00080000
+/* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */
+#define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V 0x000C0000
+
+#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 25)
+
+static iomux_v3_cfg_t const mba6_enet_pads[] = {
+ NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_MDIO_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_MDIO_PAD_CTRL),
+
+ NEW_PAD_CTRL(MX6_PAD_RGMII_TXC__RGMII_TXC, ENET_TX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_TD0__RGMII_TD0, ENET_TX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_TD1__RGMII_TD1, ENET_TX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_TD2__RGMII_TD2, ENET_TX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_TD3__RGMII_TD3, ENET_TX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL,
+ ENET_TX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_CLK_PAD_CTRL),
+ /*
+ * these pins are also used for config strapping by phy
+ */
+ NEW_PAD_CTRL(MX6_PAD_RGMII_RD0__RGMII_RD0, ENET_RX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_RD1__RGMII_RD1, ENET_RX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_RD2__RGMII_RD2, ENET_RX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_RD3__RGMII_RD3, ENET_RX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_RXC__RGMII_RXC, ENET_RX_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL,
+ ENET_RX_PAD_CTRL),
+ /* KSZ9031 PHY Reset */
+ NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__GPIO1_IO25, GPIO_OUT_PAD_CTRL),
+};
+
+static void mba6_setup_iomuxc_enet(void)
+{
+ __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
+ (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
+ __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
+ (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
+
+ imx_iomux_v3_setup_multiple_pads(mba6_enet_pads,
+ ARRAY_SIZE(mba6_enet_pads));
+
+ /* Reset PHY */
+ gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
+ /* Need delay 10ms after power on according to KSZ9031 spec */
+ udelay(1000 * 10);
+ gpio_set_value(ENET_PHY_RESET_GPIO, 1);
+ /*
+ * KSZ9031 manual: 100 usec wait time after reset before communication
+ * over MDIO
+ * BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on
+ * reset before the phy sees a high level
+ */
+ udelay(200);
+}
+
+static iomux_v3_cfg_t const mba6_uart2_pads[] = {
+ NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL),
+};
+
+static void mba6_setup_iomuxc_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads,
+ ARRAY_SIZE(mba6_uart2_pads));
+}
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
+#define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2)
+
+int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+
+ return ret;
+}
+
+int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+ ret = gpio_get_value(USDHC2_WP_GPIO);
+
+ return ret;
+}
+
+static struct fsl_esdhc_cfg mba6_usdhc_cfg = {
+ .esdhc_base = USDHC2_BASE_ADDR,
+ .max_bus_width = 4,
+};
+
+static iomux_v3_cfg_t const mba6_usdhc2_pads[] = {
+ NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC_CLK_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
+ /* CD */
+ NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, GPIO_IN_PAD_CTRL),
+ /* WP */
+ NEW_PAD_CTRL(MX6_PAD_GPIO_2__GPIO1_IO02, GPIO_IN_PAD_CTRL),
+};
+
+int tqma6_bb_board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(mba6_usdhc2_pads,
+ ARRAY_SIZE(mba6_usdhc2_pads));
+ gpio_direction_input(USDHC2_CD_GPIO);
+ gpio_direction_input(USDHC2_WP_GPIO);
+
+ mba6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ if (fsl_esdhc_initialize(bis, &mba6_usdhc_cfg))
+ puts("Warning: failed to initialize SD\n");
+
+ return 0;
+}
+
+static struct i2c_pads_info mba6_i2c1_pads = {
+/* I2C1: MBa6x */
+ .scl = {
+ .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__I2C1_SCL,
+ I2C_PAD_CTRL),
+ .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__GPIO5_IO27,
+ I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(5, 27)
+ },
+ .sda = {
+ .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__I2C1_SDA,
+ I2C_PAD_CTRL),
+ .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__GPIO5_IO26,
+ I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(5, 26)
+ }
+};
+
+static void mba6_setup_i2c(void)
+{
+ /* use logical index for bus, e.g. I2C1 -> 0 */
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads);
+}
+
+
+static iomux_v3_cfg_t const mba6_ecspi1_pads[] = {
+ NEW_PAD_CTRL(MX6_PAD_EIM_D24__GPIO3_IO24, SPI_PAD_CTRL),
+ NEW_PAD_CTRL(MX6_PAD_EIM_D25__GPIO3_IO25, SPI_PAD_CTRL),
+};
+
+static unsigned const mba6_ecspi1_cs[] = {
+ IMX_GPIO_NR(3, 24),
+ IMX_GPIO_NR(3, 25),
+};
+
+static void mba6_setup_iomuxc_spi(void)
+{
+ unsigned i;
+
+ for (i = 0; i < ARRAY_SIZE(mba6_ecspi1_cs); ++i)
+ gpio_direction_output(mba6_ecspi1_cs[i], 1);
+ imx_iomux_v3_setup_multiple_pads(mba6_ecspi1_pads,
+ ARRAY_SIZE(mba6_ecspi1_pads));
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+/*
+ * optimized pad skew values depends on CPU variant on the TQMa6x module:
+ * i.MX6Q/D or i.MX6DL/S
+ */
+#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q)
+#define MBA6X_KSZ9031_CTRL_SKEW 0x0032
+#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
+#define MBA6X_KSZ9031_RX_SKEW 0x3333
+#define MBA6X_KSZ9031_TX_SKEW 0x2036
+#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#define MBA6X_KSZ9031_CTRL_SKEW 0x0030
+#define MBA6X_KSZ9031_CLK_SKEW 0x03ff
+#define MBA6X_KSZ9031_RX_SKEW 0x3333
+#define MBA6X_KSZ9031_TX_SKEW 0x2052
+#else
+#error
+#endif
+ /* min rx/tx ctrl delay */
+ ksz9031_phy_extended_write(phydev, 2,
+ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
+ MBA6X_KSZ9031_CTRL_SKEW);
+ /* min rx delay */
+ ksz9031_phy_extended_write(phydev, 2,
+ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
+ MBA6X_KSZ9031_RX_SKEW);
+ /* max tx delay */
+ ksz9031_phy_extended_write(phydev, 2,
+ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
+ MBA6X_KSZ9031_TX_SKEW);
+ /* rx/tx clk skew */
+ ksz9031_phy_extended_write(phydev, 2,
+ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
+ MBA6X_KSZ9031_CLK_SKEW);
+
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ uint32_t base = IMX_FEC_BASE;
+ struct mii_dev *bus = NULL;
+ struct phy_device *phydev = NULL;
+ int ret;
+
+ bus = fec_get_miibus(base, -1);
+ if (!bus)
+ return 0;
+ /* scan phy */
+ phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
+ PHY_INTERFACE_MODE_RGMII);
+
+ if (!phydev) {
+ free(bus);
+ puts("No phy found\n");
+ return 0;
+ }
+ ret = fec_probe(bis, -1, base, bus, phydev);
+ if (ret) {
+ puts("FEC MXC: probe failed\n");
+ free(phydev);
+ free(bus);
+ }
+
+ return 0;
+}
+
+int tqma6_bb_board_early_init_f(void)
+{
+ mba6_setup_iomuxc_uart();
+
+ return 0;
+}
+
+int tqma6_bb_board_init(void)
+{
+ mba6_setup_i2c();
+ mba6_setup_iomuxc_spi();
+ /* do it here - to have reset completed */
+ mba6_setup_iomuxc_enet();
+
+ return 0;
+}
+
+int tqma6_bb_board_late_init(void)
+{
+ return 0;
+}
+
+const char *tqma6_bb_get_boardname(void)
+{
+ return "MBa6x";
+}
+
+/*
+ * Device Tree Support
+ */
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+void tqma6_bb_ft_board_setup(void *blob, bd_t *bd)
+{
+ /* TBD */
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/tqc/tqma6/tqma6q.cfg b/board/tqc/tqma6/tqma6q.cfg
new file mode 100644
index 0000000..f54dff7
--- /dev/null
+++ b/board/tqc/tqma6/tqma6q.cfg
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+#if defined(CONFIG_TQMA6X_MMC_BOOT)
+BOOT_FROM sd
+#elif defined(CONFIG_TQMA6X_SPI_BOOT)
+BOOT_FROM spi
+#endif
+
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* TQMa6Q/D DDR config Rev. 0100B */
+/* IOMUX configuration */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
+DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030
+
+/* memory interface calibration values */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001B0013
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018001B
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001B0016
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012001C
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43400350
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x023E032C
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43400348
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03300304
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x3C323436
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38383242
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3E3C4440
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4236483E
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+
+/* configure memory interface */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
+DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x545A79B4
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x005A1023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00088032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x09308030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025536
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
+#include "clocks.cfg"
diff --git a/board/tqc/tqma6/tqma6s.cfg b/board/tqc/tqma6/tqma6s.cfg
new file mode 100644
index 0000000..24d4e2f
--- /dev/null
+++ b/board/tqc/tqma6/tqma6s.cfg
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+#if defined(CONFIG_TQMA6X_MMC_BOOT)
+BOOT_FROM sd
+#elif defined(CONFIG_TQMA6X_SPI_BOOT)
+BOOT_FROM spi
+#endif
+
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* TQMa6S DDR config Rev. 0100B */
+/* IOMUX configuration */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008000
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030
+DATA 4, MX6_IOM_DRAM_CAS, 0x00008030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00008030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030
+DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
+DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000000
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000
+
+/* memory interface calibration values */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
+DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380000
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0014000E
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00120014
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00000000
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00000000
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x0240023C
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0228022C
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x00000000
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x00000000
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4A4A4E4A
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x00000000
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36362A32
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x00000000
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x00000000
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x00000000
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x00000000
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x00000000
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000000
+
+/* configure memory interface */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
+DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
+DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
+DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
+
+#include "clocks.cfg"