diff options
Diffstat (limited to 'board')
31 files changed, 556 insertions, 83 deletions
diff --git a/board/advantech/som-db5800-som-6867/Kconfig b/board/advantech/som-db5800-som-6867/Kconfig index f6f3748..fac562a 100644 --- a/board/advantech/som-db5800-som-6867/Kconfig +++ b/board/advantech/som-db5800-som-6867/Kconfig @@ -21,6 +21,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR if !EFI_STUB select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 + select BOARD_EARLY_INIT_F + select SPI_FLASH_MACRONIX config PCIE_ECAM_BASE default 0xe0000000 diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c index 5bed2c1..6158795 100644 --- a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c +++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c @@ -17,8 +17,3 @@ int board_early_init_f(void) return 0; } - -int arch_early_init_r(void) -{ - return 0; -} diff --git a/board/congatec/conga-qeval20-qa3-e3845/Kconfig b/board/congatec/conga-qeval20-qa3-e3845/Kconfig index 24b8f69..c2649d2 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/Kconfig +++ b/board/congatec/conga-qeval20-qa3-e3845/Kconfig @@ -21,7 +21,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR if !EFI_STUB select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 + select BOARD_EARLY_INIT_F select BOARD_LATE_INIT + select SPI_FLASH_STMICRO config PCIE_ECAM_BASE default 0xe0000000 diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c index 7a5b765..1283eeb 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c +++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c @@ -28,11 +28,6 @@ int board_early_init_f(void) return 0; } -int arch_early_init_r(void) -{ - return 0; -} - int board_late_init(void) { struct udevice *dev; diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig index 3ff64f4..cfa1d50 100644 --- a/board/coreboot/coreboot/Kconfig +++ b/board/coreboot/coreboot/Kconfig @@ -12,6 +12,17 @@ config SYS_SOC config SYS_TEXT_BASE default 0x01110000 +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + imply SPI_FLASH_ATMEL + imply SPI_FLASH_EON + imply SPI_FLASH_GIGADEVICE + imply SPI_FLASH_MACRONIX + imply SPI_FLASH_SPANSION + imply SPI_FLASH_STMICRO + imply SPI_FLASH_SST + imply SPI_FLASH_WINBOND + comment "coreboot-specific options" config SYS_CONFIG_NAME diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile index 27ebe78..4f2ac89 100644 --- a/board/coreboot/coreboot/Makefile +++ b/board/coreboot/coreboot/Makefile @@ -12,4 +12,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += coreboot_start.o coreboot.o +obj-y += coreboot_start.o diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c deleted file mode 100644 index bb7f778..0000000 --- a/board/coreboot/coreboot/coreboot.c +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (C) 2013 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <cros_ec.h> -#include <asm/gpio.h> - -int arch_early_init_r(void) -{ - return 0; -} diff --git a/board/dfi/dfi-bt700/Kconfig b/board/dfi/dfi-bt700/Kconfig index fca8b53..81a2575 100644 --- a/board/dfi/dfi-bt700/Kconfig +++ b/board/dfi/dfi-bt700/Kconfig @@ -21,7 +21,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR if !EFI_STUB select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 + select BOARD_EARLY_INIT_F select BOARD_LATE_INIT + select SPI_FLASH_STMICRO config PCIE_ECAM_BASE default 0xe0000000 diff --git a/board/efi/efi-x86/efi.c b/board/efi/efi-x86/efi.c index 1fbe36a..2adc202 100644 --- a/board/efi/efi-x86/efi.c +++ b/board/efi/efi-x86/efi.c @@ -5,9 +5,3 @@ */ #include <common.h> -#include <asm/gpio.h> - -int arch_early_init_r(void) -{ - return 0; -} diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 2cd4fba..dfe5d20 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -81,7 +81,13 @@ int fsl_setenv_chain_of_trust(void) * bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) */ setenv("bootdelay", "0"); + +#ifdef CONFIG_ARM + setenv("secureboot", "y"); +#else setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD); +#endif + return 0; } #endif diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c index 6cb5692..0c65ec7 100644 --- a/board/freescale/qemu-ppce500/qemu-ppce500.c +++ b/board/freescale/qemu-ppce500/qemu-ppce500.c @@ -50,13 +50,19 @@ uint64_t get_phys_ccsrbar_addr_early(void) { void *fdt = get_fdt_virt(); uint64_t r; + int size, node; + u32 naddr; + const fdt32_t *prop; /* * To be able to read the FDT we need to create a temporary TLB * map for it. */ map_fdt_as(10); - r = fdt_get_base_address(fdt, fdt_path_offset(fdt, "/soc")); + node = fdt_path_offset(fdt, "/soc"); + naddr = fdt_address_cells(fdt, node); + prop = fdt_getprop(fdt, node, "ranges", &size); + r = fdt_translate_address(fdt, node, prop + naddr); disable_tlb(10); return r; diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 8999b58..944716d 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_IVYBRIDGE select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_WINBOND config PCIE_ECAM_BASE default 0xf0000000 diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 42615e1..dc22592 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -5,19 +5,3 @@ */ #include <common.h> -#include <cros_ec.h> -#include <dm.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include <asm/pci.h> -#include <asm/arch/pch.h> - -int arch_early_init_r(void) -{ - return 0; -} - -int board_early_init_f(void) -{ - return 0; -} diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig index f2b9481..afbfe53 100644 --- a/board/google/chromebook_samus/Kconfig +++ b/board/google/chromebook_samus/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_BROADWELL select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_WINBOND config PCIE_ECAM_BASE default 0xf0000000 diff --git a/board/google/chromebook_samus/samus.c b/board/google/chromebook_samus/samus.c index 3c3f5d4..5b5eb19 100644 --- a/board/google/chromebook_samus/samus.c +++ b/board/google/chromebook_samus/samus.c @@ -5,14 +5,3 @@ */ #include <common.h> -#include <asm/cpu.h> - -int arch_early_init_r(void) -{ - return cpu_run_reference_code(); -} - -int board_early_init_f(void) -{ - return 0; -} diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig index 2af3aa9..875df9d 100644 --- a/board/google/chromebox_panther/Kconfig +++ b/board/google/chromebox_panther/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_IVYBRIDGE select HAVE_INTEL_ME select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_WINBOND config SYS_CAR_ADDR hex diff --git a/board/google/chromebox_panther/panther.c b/board/google/chromebox_panther/panther.c index e3baf88..2adc202 100644 --- a/board/google/chromebox_panther/panther.c +++ b/board/google/chromebox_panther/panther.c @@ -5,14 +5,3 @@ */ #include <common.h> -#include <asm/arch/pch.h> - -int arch_early_init_r(void) -{ - return 0; -} - -int board_early_init_f(void) -{ - return 0; -} diff --git a/board/intel/bayleybay/Kconfig b/board/intel/bayleybay/Kconfig index 597228f..a622499 100644 --- a/board/intel/bayleybay/Kconfig +++ b/board/intel/bayleybay/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_WINBOND config PCIE_ECAM_BASE default 0xe0000000 diff --git a/board/intel/cougarcanyon2/Kconfig b/board/intel/cougarcanyon2/Kconfig index 95a617b..ed76448 100644 --- a/board/intel/cougarcanyon2/Kconfig +++ b/board/intel/cougarcanyon2/Kconfig @@ -21,5 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_IVYBRIDGE select HAVE_FSP select BOARD_ROMSIZE_KB_2048 + select BOARD_EARLY_INIT_F + select SPI_FLASH_WINBOND endif diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig index b30701a..1eed227 100644 --- a/board/intel/crownbay/Kconfig +++ b/board/intel/crownbay/Kconfig @@ -20,5 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR select INTEL_QUEENSBAY select BOARD_ROMSIZE_KB_1024 + select BOARD_EARLY_INIT_F + select SPI_FLASH_SST endif diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig index 87a0ec4..1416c89 100644 --- a/board/intel/galileo/Kconfig +++ b/board/intel/galileo/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR select INTEL_QUARK select BOARD_ROMSIZE_KB_1024 + select SPI_FLASH_WINBOND config SMBIOS_PRODUCT_NAME default "GalileoGen2" diff --git a/board/intel/galileo/galileo.c b/board/intel/galileo/galileo.c index 568bd4d..2fe1923 100644 --- a/board/intel/galileo/galileo.c +++ b/board/intel/galileo/galileo.c @@ -9,11 +9,6 @@ #include <asm/arch/device.h> #include <asm/arch/quark.h> -int board_early_init_f(void) -{ - return 0; -} - /* * Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin. * diff --git a/board/intel/minnowmax/Kconfig b/board/intel/minnowmax/Kconfig index 7e975f9..a8668e4 100644 --- a/board/intel/minnowmax/Kconfig +++ b/board/intel/minnowmax/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR if !EFI_STUB select INTEL_BAYTRAIL select BOARD_ROMSIZE_KB_8192 + select SPI_FLASH_STMICRO config PCIE_ECAM_BASE default 0xe0000000 diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c index 99aed53..5bdb2fd 100644 --- a/board/intel/minnowmax/minnowmax.c +++ b/board/intel/minnowmax/minnowmax.c @@ -12,11 +12,6 @@ #define GPIO_BANKE_NAME "gpioe" -int arch_early_init_r(void) -{ - return 0; -} - int misc_init_r(void) { struct udevice *dev; diff --git a/board/renesas/ulcb/Kconfig b/board/renesas/ulcb/Kconfig new file mode 100644 index 0000000..1e9a10d --- /dev/null +++ b/board/renesas/ulcb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ULCB + +config SYS_SOC + default "rmobile" + +config SYS_BOARD + default "ulcb" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "ulcb" + +endif diff --git a/board/renesas/ulcb/MAINTAINERS b/board/renesas/ulcb/MAINTAINERS new file mode 100644 index 0000000..e7cdc52 --- /dev/null +++ b/board/renesas/ulcb/MAINTAINERS @@ -0,0 +1,7 @@ +ULCB BOARD +M: Marek Vasut <marek.vasut+renesas@gmail.com> +S: Maintained +F: board/renesas/ulcb/ +F: include/configs/ulcb.h +F: configs/r8a7795_ulcb_defconfig +F: configs/r8a7796_ulcb_defconfig diff --git a/board/renesas/ulcb/Makefile b/board/renesas/ulcb/Makefile new file mode 100644 index 0000000..6fe0b48 --- /dev/null +++ b/board/renesas/ulcb/Makefile @@ -0,0 +1,9 @@ +# +# board/renesas/ulcb/Makefile +# +# Copyright (C) 2017 Renesas Electronics Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := ulcb.o cpld.o ../rcar-common/common.o diff --git a/board/renesas/ulcb/cpld.c b/board/renesas/ulcb/cpld.c new file mode 100644 index 0000000..f9384b0 --- /dev/null +++ b/board/renesas/ulcb/cpld.c @@ -0,0 +1,167 @@ +/* + * ULCB board CPLD access support + * + * Copyright (C) 2017 Renesas Electronics Corporation + * Copyright (C) 2017 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/gpio.h> + +#define SCLK GPIO_GP_6_8 +#define SSTBZ GPIO_GP_2_3 +#define MOSI GPIO_GP_6_7 +#define MISO GPIO_GP_6_10 + +#define CPLD_ADDR_MODE 0x00 /* RW */ +#define CPLD_ADDR_MUX 0x02 /* RW */ +#define CPLD_ADDR_DIPSW6 0x08 /* R */ +#define CPLD_ADDR_RESET 0x80 /* RW */ +#define CPLD_ADDR_VERSION 0xFF /* R */ + +static int cpld_initialized; + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + /* Always valid */ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* Always active */ +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* Always active */ +} + +void ulcb_softspi_sda(int set) +{ + gpio_set_value(MOSI, set); +} + +void ulcb_softspi_scl(int set) +{ + gpio_set_value(SCLK, set); +} + +unsigned char ulcb_softspi_read(void) +{ + return !!gpio_get_value(MISO); +} + +static void cpld_rw(u8 write) +{ + gpio_set_value(MOSI, write); + gpio_set_value(SSTBZ, 0); + gpio_set_value(SCLK, 1); + gpio_set_value(SCLK, 0); + gpio_set_value(SSTBZ, 1); +} + +static u32 cpld_read(u8 addr) +{ + u32 data = 0; + + spi_xfer(NULL, 8, &addr, NULL, SPI_XFER_BEGIN | SPI_XFER_END); + + cpld_rw(0); + + spi_xfer(NULL, 32, NULL, &data, SPI_XFER_BEGIN | SPI_XFER_END); + + return swab32(data); +} + +static void cpld_write(u8 addr, u32 data) +{ + data = swab32(data); + + spi_xfer(NULL, 32, &data, NULL, SPI_XFER_BEGIN | SPI_XFER_END); + + spi_xfer(NULL, 8, NULL, &addr, SPI_XFER_BEGIN | SPI_XFER_END); + + cpld_rw(1); +} + +static void cpld_init(void) +{ + if (cpld_initialized) + return; + + /* PULL-UP on MISO line */ + setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4); + + gpio_request(SCLK, NULL); + gpio_request(SSTBZ, NULL); + gpio_request(MOSI, NULL); + gpio_request(MISO, NULL); + + gpio_direction_output(SCLK, 0); + gpio_direction_output(SSTBZ, 1); + gpio_direction_output(MOSI, 0); + gpio_direction_input(MISO); + + /* Dummy read */ + cpld_read(CPLD_ADDR_VERSION); + + cpld_initialized = 1; +} + +static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + u32 addr, val; + + cpld_init(); + + if (argc == 2 && strcmp(argv[1], "info") == 0) { + printf("CPLD version:\t\t\t0x%08x\n", + cpld_read(CPLD_ADDR_VERSION)); + printf("H3 Mode setting (MD0..28):\t0x%08x\n", + cpld_read(CPLD_ADDR_MODE)); + printf("Multiplexer settings:\t\t0x%08x\n", + cpld_read(CPLD_ADDR_MUX)); + printf("DIPSW (SW6):\t\t\t0x%08x\n", + cpld_read(CPLD_ADDR_DIPSW6)); + return 0; + } + + if (argc < 3) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[2], NULL, 16); + if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE || + addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_DIPSW6 || + addr == CPLD_ADDR_RESET)) { + printf("Invalid CPLD register address\n"); + return CMD_RET_USAGE; + } + + if (argc == 3 && strcmp(argv[1], "read") == 0) { + printf("0x%x\n", cpld_read(addr)); + } else if (argc == 4 && strcmp(argv[1], "write") == 0) { + val = simple_strtoul(argv[3], NULL, 16); + cpld_write(addr, val); + } + + return 0; +} + +U_BOOT_CMD( + cpld, 4, 1, do_cpld, + "CPLD access", + "info\n" + "cpld read addr\n" + "cpld write addr val\n" +); + +void reset_cpu(ulong addr) +{ + cpld_init(); + cpld_write(CPLD_ADDR_RESET, 1); +} diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c new file mode 100644 index 0000000..4005ec8 --- /dev/null +++ b/board/renesas/ulcb/ulcb.c @@ -0,0 +1,257 @@ +/* + * board/renesas/ulcb/ulcb.c + * This file is ULCB board support. + * + * Copyright (C) 2017 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <netdev.h> +#include <dm.h> +#include <dm/platform_data/serial_sh.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> +#include <asm/arch/sh_sdhi.h> +#include <i2c.h> +#include <mmc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define CPGWPCR 0xE6150904 +#define CPGWPR 0xE615090C + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + writel(0xA5A50000, CPGWPCR); + writel(0xFFFFFFFF, CPGWPR); +} + +#define GSX_MSTP112 BIT(12) /* 3DG */ +#define TMU0_MSTP125 BIT(25) /* secure */ +#define TMU1_MSTP124 BIT(24) /* non-secure */ +#define SCIF2_MSTP310 BIT(10) /* SCIF2 */ +#define ETHERAVB_MSTP812 BIT(12) +#define DVFS_MSTP926 BIT(26) +#define SD0_MSTP314 BIT(14) +#define SD1_MSTP313 BIT(13) +#define SD2_MSTP312 BIT(12) /* either MMC0 */ + +#define SD0CKCR 0xE6150074 +#define SD1CKCR 0xE6150078 +#define SD2CKCR 0xE6150268 +#define SD3CKCR 0xE615026C + +int board_early_init_f(void) +{ + /* TMU0,1 */ /* which use ? */ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); + /* SCIF2 */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310); + /* EHTERAVB */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812); + /* eMMC */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312); + /* SDHI0 */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314); + + writel(0, SD0CKCR); + writel(0, SD1CKCR); + writel(0, SD2CKCR); + writel(0, SD3CKCR); + +#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) + /* DVFS for reset */ + mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926); +#endif + return 0; +} + +/* SYSC */ +/* R/- 32 Power status register 2(3DG) */ +#define SYSC_PWRSR2 0xE6180100 +/* -/W 32 Power resume control register 2 (3DG) */ +#define SYSC_PWRONCR2 0xE618010C + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; + + /* Init PFC controller */ +#if defined(CONFIG_R8A7795) + r8a7795_pinmux_init(); +#elif defined(CONFIG_R8A7796) + r8a7796_pinmux_init(); +#endif + + /* USB1 pull-up */ + setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); + +#ifdef CONFIG_RAVB + /* EtherAVB Enable */ + /* GPSR2 */ + gpio_request(GPIO_GFN_AVB_AVTP_CAPTURE_A, NULL); + gpio_request(GPIO_GFN_AVB_AVTP_MATCH_A, NULL); + gpio_request(GPIO_GFN_AVB_LINK, NULL); + gpio_request(GPIO_GFN_AVB_PHY_INT, NULL); + gpio_request(GPIO_GFN_AVB_MAGIC, NULL); + gpio_request(GPIO_GFN_AVB_MDC, NULL); + + /* IPSR0 */ + gpio_request(GPIO_IFN_AVB_MDC, NULL); + gpio_request(GPIO_IFN_AVB_MAGIC, NULL); + gpio_request(GPIO_IFN_AVB_PHY_INT, NULL); + gpio_request(GPIO_IFN_AVB_LINK, NULL); + gpio_request(GPIO_IFN_AVB_AVTP_MATCH_A, NULL); + gpio_request(GPIO_IFN_AVB_AVTP_CAPTURE_A, NULL); + /* IPSR1 */ + gpio_request(GPIO_FN_AVB_AVTP_PPS, NULL); + /* IPSR2 */ + gpio_request(GPIO_FN_AVB_AVTP_MATCH_B, NULL); + /* IPSR3 */ + gpio_request(GPIO_FN_AVB_AVTP_CAPTURE_B, NULL); + + /* AVB_PHY_RST */ + gpio_request(GPIO_GP_2_10, NULL); + gpio_direction_output(GPIO_GP_2_10, 0); + mdelay(20); + gpio_set_value(GPIO_GP_2_10, 1); + udelay(1); +#endif + + return 0; +} + +static struct eth_pdata salvator_x_ravb_platdata = { + .iobase = 0xE6800000, + .phy_interface = 0, + .max_speed = 1000, +}; + +U_BOOT_DEVICE(salvator_x_ravb) = { + .name = "ravb", + .platdata = &salvator_x_ravb_platdata, +}; + +#ifdef CONFIG_SH_SDHI +int board_mmc_init(bd_t *bis) +{ + int ret = -ENODEV; + + /* SDHI0 */ + gpio_request(GPIO_GFN_SD0_DAT0, NULL); + gpio_request(GPIO_GFN_SD0_DAT1, NULL); + gpio_request(GPIO_GFN_SD0_DAT2, NULL); + gpio_request(GPIO_GFN_SD0_DAT3, NULL); + gpio_request(GPIO_GFN_SD0_CLK, NULL); + gpio_request(GPIO_GFN_SD0_CMD, NULL); + gpio_request(GPIO_GFN_SD0_CD, NULL); + gpio_request(GPIO_GFN_SD0_WP, NULL); + + gpio_request(GPIO_GP_5_2, NULL); + gpio_request(GPIO_GP_5_1, NULL); + gpio_direction_output(GPIO_GP_5_2, 1); /* power on */ + gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, + SH_SDHI_QUIRK_64BIT_BUF); + if (ret) + return ret; + + /* SDHI1/SDHI2 eMMC */ + gpio_request(GPIO_GFN_SD1_DAT0, NULL); + gpio_request(GPIO_GFN_SD1_DAT1, NULL); + gpio_request(GPIO_GFN_SD1_DAT2, NULL); + gpio_request(GPIO_GFN_SD1_DAT3, NULL); + gpio_request(GPIO_GFN_SD2_DAT0, NULL); + gpio_request(GPIO_GFN_SD2_DAT1, NULL); + gpio_request(GPIO_GFN_SD2_DAT2, NULL); + gpio_request(GPIO_GFN_SD2_DAT3, NULL); + gpio_request(GPIO_GFN_SD2_CLK, NULL); +#if defined(CONFIG_R8A7795) + gpio_request(GPIO_GFN_SD2_CMD, NULL); +#elif defined(CONFIG_R8A7796) + gpio_request(GPIO_FN_SD2_CMD, NULL); +#else +#error Only R8A7795 and R87796 is supported +#endif + gpio_request(GPIO_GP_5_3, NULL); + gpio_request(GPIO_GP_5_9, NULL); + gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */ + gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1, + SH_SDHI_QUIRK_64BIT_BUF); + + return ret; +} +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; +#if (CONFIG_NR_DRAM_BANKS >= 2) + gd->ram_size += PHYS_SDRAM_2_SIZE; +#endif +#if (CONFIG_NR_DRAM_BANKS >= 3) + gd->ram_size += PHYS_SDRAM_3_SIZE; +#endif +#if (CONFIG_NR_DRAM_BANKS >= 4) + gd->ram_size += PHYS_SDRAM_4_SIZE; +#endif + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +#if (CONFIG_NR_DRAM_BANKS >= 2) + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +#endif +#if (CONFIG_NR_DRAM_BANKS >= 3) + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; +#endif +#if (CONFIG_NR_DRAM_BANKS >= 4) + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; +#endif + return 0; +} + +const struct rmobile_sysinfo sysinfo = { + CONFIG_RCAR_BOARD_STRING +}; + +static const struct sh_serial_platdata serial_platdata = { + .base = SCIF2_BASE, + .type = PORT_SCIF, + .clk = CONFIG_SH_SCIF_CLK_FREQ, + .clk_mode = INT_CLK, +}; + +U_BOOT_DEVICE(salvator_x_scif2) = { + .name = "serial_sh", + .platdata = &serial_platdata, +}; diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index 43766e0..f4411f0 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -10,7 +10,9 @@ # obj-y += board.o obj-$(CONFIG_SUNXI_GMAC) += gmac.o +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_SUNXI_AHCI) += ahci.o +endif obj-$(CONFIG_MACH_SUN4I) += dram_sun4i_auto.o obj-$(CONFIG_MACH_SUN5I) += dram_sun5i_auto.o obj-$(CONFIG_MACH_SUN7I) += dram_sun5i_auto.o diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c index 522e54a..a79b80c 100644 --- a/board/sunxi/ahci.c +++ b/board/sunxi/ahci.c @@ -1,5 +1,6 @@ #include <common.h> #include <ahci.h> +#include <dm.h> #include <scsi.h> #include <errno.h> #include <asm/io.h> @@ -13,9 +14,8 @@ /* This magic PHY initialisation was taken from the Allwinner releases * and Linux driver, but is completely undocumented. */ -static int sunxi_ahci_phy_init(u32 base) +static int sunxi_ahci_phy_init(u8 *reg_base) { - u8 *reg_base = (u8 *)base; u32 reg_val; int timeout; @@ -70,10 +70,65 @@ static int sunxi_ahci_phy_init(u32 base) return 0; } +#ifndef CONFIG_DM_SCSI void scsi_init(void) { - if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0) + if (sunxi_ahci_phy_init((u8 *)SUNXI_SATA_BASE) < 0) return; ahci_init((void __iomem *)SUNXI_SATA_BASE); } +#else +static int sunxi_sata_probe(struct udevice *dev) +{ + ulong base; + u8 *reg; + int ret; + + base = dev_read_addr(dev); + if (base == FDT_ADDR_T_NONE) { + debug("%s: Failed to find address (err=%d\n)", __func__, ret); + return -EINVAL; + } + reg = (u8 *)base; + ret = sunxi_ahci_phy_init(reg); + if (ret) { + debug("%s: Failed to init phy (err=%d\n)", __func__, ret); + return ret; + } + ret = ahci_probe_scsi(dev, base); + if (ret) { + debug("%s: Failed to probe (err=%d\n)", __func__, ret); + return ret; + } + + return 0; +} + +static int sunxi_sata_bind(struct udevice *dev) +{ + struct udevice *scsi_dev; + int ret; + + ret = ahci_bind_scsi(dev, &scsi_dev); + if (ret) { + debug("%s: Failed to bind (err=%d\n)", __func__, ret); + return ret; + } + + return 0; +} + +static const struct udevice_id sunxi_ahci_ids[] = { + { .compatible = "allwinner,sun4i-a10-ahci" }, + { } +}; + +U_BOOT_DRIVER(ahci_sunxi_drv) = { + .name = "ahci_sunxi", + .id = UCLASS_AHCI, + .of_match = sunxi_ahci_ids, + .bind = sunxi_sata_bind, + .probe = sunxi_sata_probe, +}; +#endif |