diff options
Diffstat (limited to 'drivers/phy/marvell/comphy_hpipe.h')
| -rw-r--r-- | drivers/phy/marvell/comphy_hpipe.h | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h index 1e294fb..5edd0ad 100644 --- a/drivers/phy/marvell/comphy_hpipe.h +++ b/drivers/phy/marvell/comphy_hpipe.h @@ -254,6 +254,11 @@ #define HPIPE_EXT_SELLV_RXSAMPL_MASK \ (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) +#define HPIPE_VDD_CAL_0_REG 0x108 +#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15 +#define HPIPE_CAL_VDD_CONT_MODE_MASK \ + (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET) + #define HPIPE_PCIE_REG0 0x120 #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 #define HPIPE_PCIE_IDLE_SYNC_MASK \ @@ -301,6 +306,9 @@ (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET) #define HPIPE_SPD_DIV_FORCE_REG 0x154 +#define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7 +#define HPIPE_TXDIGCK_DIV_FORCE_MASK \ + (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET) #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8 #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \ (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) @@ -317,6 +325,9 @@ #define HPIPE_PLLINTP_REG1 0x150 #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C +#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6 +#define HPIPE_RX_SAMPLER_OS_GAIN_MASK \ + (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET) #define HPIPE_SMAPLER_OFFSET 12 #define HPIPE_SMAPLER_MASK \ (0x1 << HPIPE_SMAPLER_OFFSET) @@ -363,6 +374,21 @@ #define HPIPE_OS_PH_VALID_MASK \ (0x1 << HPIPE_OS_PH_VALID_OFFSET) +#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214 +#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7 +#define HPIPE_TRAIN_PAT_NUM_MASK \ + (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET) + +#define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220 +#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12 +#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \ + (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET) + +#define HPIPE_DME_REG 0x228 +#define HPIPE_DME_ETHERNET_MODE_OFFSET 7 +#define HPIPE_DME_ETHERNET_MODE_MASK \ + (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET) + #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 #define HPIPE_TX_TRAIN_P2P_HOLD_MASK \ @@ -388,6 +414,9 @@ #define HPIPE_PCIE_REG3 0x290 #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 +#define HPIPE_RX_TRAIN_TIMER_OFFSET 0 +#define HPIPE_RX_TRAIN_TIMER_MASK \ + (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET) #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 #define HPIPE_TX_TRAIN_START_SQ_EN_MASK \ (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) @@ -408,6 +437,12 @@ #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \ (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) +#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8 +#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET) +#define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9 +#define HPIPE_TX_TRAIN_PAT_SEL_MASK \ + (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET) #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 @@ -470,6 +505,11 @@ #define HPIPE_G3_DFE_RES_MASK \ (0x3 << HPIPE_G3_DFE_RES_OFFSET) +#define HPIPE_TX_PRESET_INDEX_REG 0x468 +#define HPIPE_TX_PRESET_INDEX_OFFSET 0 +#define HPIPE_TX_PRESET_INDEX_MASK \ + (0xf << HPIPE_TX_PRESET_INDEX_OFFSET) + #define HPIPE_DFE_CTRL_28_REG 0x49C #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 #define HPIPE_DFE_CTRL_28_PIPE4_MASK \ |