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-rw-r--r--include/configs/kilauea.h108
1 files changed, 95 insertions, 13 deletions
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index a596768..035a40e 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -1,4 +1,7 @@
/*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ * Grant Erickson <gerickson@nuovations.com>
+ *
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
@@ -54,20 +57,56 @@
#define CFG_MONITOR_BASE (TEXT_BASE)
/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer
- *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */
-#define CFG_INIT_RAM_END (4 << 10)
+ * Initial RAM & Stack Pointer Configuration Options
+ *
+ * There are traditionally three options for the primordial
+ * (i.e. initial) stack usage on the 405-series:
+ *
+ * 1) On-chip Memory (OCM) (i.e. SRAM)
+ * 2) Data cache
+ * 3) SDRAM
+ *
+ * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
+ * the latter of which is less than desireable since it requires
+ * setting up the SDRAM and ECC in assembly code.
+ *
+ * To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip
+ * select on the External Bus Controller (EBC) and then select a
+ * value for 'CFG_INIT_RAM_ADDR' outside of the range of valid,
+ * physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and
+ * select a value for 'CFG_INIT_RAM_ADDR' within the range of valid,
+ * physical SDRAM to use (3).
+ *-----------------------------------------------------------------------*/
+
+#define CFG_INIT_DCACHE_CS 4
+
+#if defined(CFG_INIT_DCACHE_CS)
+#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */
+#else
+#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + (32 << 20)) /* 32 MiB */
+#endif /* defined(CFG_INIT_DCACHE_CS) */
+
+#define CFG_INIT_RAM_END (4 << 10) /* 4 KiB */
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-/* reserve some memory for POST and BOOT limit info */
-#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
-/* extra data in init-ram */
-#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
-#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8)
-#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12)
-#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */
+/*
+ * If the data cache is being used for the primordial stack and global
+ * data area, the POST word must be placed somewhere else. The General
+ * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
+ * its compare and mask register contents across reset, so it is used
+ * for the POST word.
+ */
+
+#if defined(CFG_INIT_DCACHE_CS)
+# define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+# define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
+#else
+# define CFG_INIT_EXTRA_SIZE 16
+# define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE)
+# define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
+# define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR
+#endif /* defined(CFG_INIT_DCACHE_CS) */
/*-----------------------------------------------------------------------
* Serial Port
@@ -187,6 +226,50 @@
*----------------------------------------------------------------------*/
#define CFG_MBYTES_SDRAM (256) /* 256MB */
+#define CFG_SDRAM0_MB0CF_BASE (( 0 << 20) + CFG_SDRAM_BASE)
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+#define CFG_SDRAM0_MB0CF ((CFG_SDRAM0_MB0CF_BASE >> 3) | \
+ SDRAM_RXBAS_SDSZ_256MB | \
+ SDRAM_RXBAS_SDAM_MODE7 | \
+ SDRAM_RXBAS_SDBE_ENABLE)
+#define CFG_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
+#define CFG_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
+#define CFG_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
+#define CFG_SDRAM0_MCOPT1 0x04322000
+#define CFG_SDRAM0_MCOPT2 0x00000000
+#define CFG_SDRAM0_MODT0 0x01800000
+#define CFG_SDRAM0_MODT1 0x00000000
+#define CFG_SDRAM0_CODT 0x0080f837
+#define CFG_SDRAM0_RTR 0x06180000
+#define CFG_SDRAM0_INITPLR0 0xa8380000
+#define CFG_SDRAM0_INITPLR1 0x81900400
+#define CFG_SDRAM0_INITPLR2 0x81020000
+#define CFG_SDRAM0_INITPLR3 0x81030000
+#define CFG_SDRAM0_INITPLR4 0x81010404
+#define CFG_SDRAM0_INITPLR5 0x81000542
+#define CFG_SDRAM0_INITPLR6 0x81900400
+#define CFG_SDRAM0_INITPLR7 0x8D080000
+#define CFG_SDRAM0_INITPLR8 0x8D080000
+#define CFG_SDRAM0_INITPLR9 0x8D080000
+#define CFG_SDRAM0_INITPLR10 0x8D080000
+#define CFG_SDRAM0_INITPLR11 0x81000442
+#define CFG_SDRAM0_INITPLR12 0x81010780
+#define CFG_SDRAM0_INITPLR13 0x81010400
+#define CFG_SDRAM0_INITPLR14 0x00000000
+#define CFG_SDRAM0_INITPLR15 0x00000000
+#define CFG_SDRAM0_RQDC 0x80000038
+#define CFG_SDRAM0_RFDC 0x00000209
+#define CFG_SDRAM0_RDCC 0x40000000
+#define CFG_SDRAM0_DLCR 0x030000a5
+#define CFG_SDRAM0_CLKTR 0x80000000
+#define CFG_SDRAM0_WRDTR 0x00000000
+#define CFG_SDRAM0_SDTR1 0x80201000
+#define CFG_SDRAM0_SDTR2 0x32204232
+#define CFG_SDRAM0_SDTR3 0x080b0d1a
+#define CFG_SDRAM0_MMODE 0x00000442
+#define CFG_SDRAM0_MEMODE 0x00000404
+
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
@@ -319,8 +402,7 @@
#define CONFIG_CMD_SNTP
/* POST support */
-#define CONFIG_POST (CFG_POST_MEMORY | \
- CFG_POST_CACHE | \
+#define CONFIG_POST (CFG_POST_CACHE | \
CFG_POST_CPU | \
CFG_POST_ETHER | \
CFG_POST_I2C | \