diff options
Diffstat (limited to 'include/configs/simc-t10xx.h')
| -rw-r--r-- | include/configs/simc-t10xx.h | 458 |
1 files changed, 315 insertions, 143 deletions
diff --git a/include/configs/simc-t10xx.h b/include/configs/simc-t10xx.h index 09a9d6d..1c0c677 100644 --- a/include/configs/simc-t10xx.h +++ b/include/configs/simc-t10xx.h @@ -1,5 +1,5 @@ /* - * Copyright 2016 Scalys B.V. + * Copyright 2017 Scalys B.V. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,56 +10,103 @@ #include "simc-t10x0.h" #include <generated/autoconf.h> + + +#define CONFIG_MTD_UBI_WL_THRESHOLD 4096 +#define CONFIG_MTD_UBI_BEB_LIMIT 20 + + #define MPC85XX_GPIO_NR(port, pin) ((((port)-1)*32)+((pin)&31)) /* * SIMC-T10xx board configuration file */ -#define CONFIG_PHYS_64BIT -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) /* MT29F8G08ABBCAH4*/ /* * System and DDR clock */ -#if defined(CONFIG_SYS_CLK_FREQ_66) -#define CONFIG_SYS_CLK_FREQ 66666666 /* 66.6 MHz */ -#elif defined(CONFIG_SYS_CLK_FREQ_100) #define CONFIG_SYS_CLK_FREQ 100000000 /* 100 MHz */ -#endif - #define CONFIG_DDR_CLK_FREQ 133333333 /* 133.33MHz */ #ifdef CONFIG_RAMBOOT_PBL -/* PBI commands are cpu independent for now */ -/*#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg*/ - -#ifdef CONFIG_SECURE_BOOT -/* Secure boot enabled */ -#define CONFIG_SYS_FSL_PBL_PBI \ - $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_nand_secure_pbi.cfg +/* We have to specify all the PBL and RCW since they are used without being + * proccessed by the preprocessor */ +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_NAND_FLASH_BOOT) +/* Secure boot from NAND flash */ +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_nand_secure_pbi.cfg +#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_NOR_FLASH_BOOT) +/* Secure boot from NOR flash */ +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_nor_secure_pbi.cfg +#elif defined(CONFIG_NAND_FLASH_BOOT) +/* normal boot from NAND flash */ +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_nand_pbi.cfg +#elif defined(CONFIG_NOR_FLASH_BOOT) +/* normal boot from NOR flash */ +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_nor_pbi.cfg +#elif defined(CONFIG_SPI_FLASH_BOOT) +/* normal boot frop SPI flash */ +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_spi_pbi.cfg +#elif defined(CONFIG_SDHC_FLASH_BOOT) +/* normal boot fro sdhc flash */ +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_sdhc_pbi.cfg #else -/* Secure boot disabled */ -#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg +/* unknown configuration, this should not happen */ +#error Invalid Boot configuration #endif - - - /* Set the RCW config depending on the CPU type */ +#if ( defined(CONFIG_PPC_T1022) || defined(CONFIG_PPC_T1042)) && \ + defined(CONFIG_SECURE_BOOT) && defined(CONFIG_NAND_FLASH_BOOT) +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x2_nand_secure_rcw.cfg +#elif ( defined(CONFIG_PPC_T1022) || defined(CONFIG_PPC_T1042)) && \ + defined(CONFIG_SECURE_BOOT) && defined(CONFIG_NOR_FLASH_BOOT) +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x2_nor_secure_rcw.cfg +#elif ( defined(CONFIG_PPC_T1022) || defined(CONFIG_PPC_T1042)) && \ + defined(CONFIG_NAND_FLASH_BOOT) +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x2_nand_rcw.cfg +#elif ( defined(CONFIG_PPC_T1022) || defined(CONFIG_PPC_T1042)) && \ + defined(CONFIG_NOR_FLASH_BOOT) +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x2_nor_rcw.cfg +#elif ( defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1040)) && \ + defined(CONFIG_SECURE_BOOT) && defined(CONFIG_NAND_FLASH_BOOT) +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x0_nand_secure_rcw.cfg +#elif ( defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1040)) && \ + defined(CONFIG_SECURE_BOOT) && defined(CONFIG_NOR_FLASH_BOOT) +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x0_nor_secure_rcw.cfg +#elif ( defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1040)) && \ + defined(CONFIG_NAND_FLASH_BOOT) +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x0_nand_rcw.cfg +#elif ( defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1040)) && \ + defined(CONFIG_NOR_FLASH_BOOT) +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x0_nor_rcw.cfg +#elif ( defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1040)) && \ + defined(CONFIG_SPI_FLASH_BOOT) +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x0_spi_rcw.cfg +#elif ( defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1040)) && \ + defined(CONFIG_SDHC_FLASH_BOOT) +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x0_sdhc_rcw.cfg +#else +/* unknown configuration, this should not happen */ +#error Invalid Boot configuration +#endif + +#if 0 #if defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1022_rcw.cfg #elif defined(CONFIG_PPC_T1040) #ifdef CONFIG_SECURE_BOOT #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1040_nand_secure_rcw.cfg #else -#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1040_rcw.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1040_nor_rcw.cfg +/*#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1040_rcw.cfg*/ #endif #endif +#endif #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT #define CONFIG_SPL_ENV_SUPPORT @@ -72,7 +119,6 @@ #define CONFIG_SPL_I2C_SUPPORT #define CONFIG_SPL_DRIVERS_MISC_SUPPORT -#define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x30001000 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 #define CONFIG_SPL_PAD_TO 0x40000 @@ -89,10 +135,9 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 1 -#ifdef CONFIG_NAND +#ifdef CONFIG_NAND_FLASH #define CONFIG_SPL_NAND_SUPPORT - #define CONFIG_SYS_NAND_U_BOOT_SIZE ( (2048-256) *1024) #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) @@ -100,10 +145,16 @@ #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) +#ifndef CONFIG_SDHC_FLASH_BOOT #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #define CONFIG_SPL_NAND_BOOT +#endif #endif /* CONFIG_NAND */ +#ifdef CONFIG_SDHC_FLASH_BOOT +#define CONFIG_SDCARD +#endif + #ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC #define CONFIG_SPL_MMC_SUPPORT @@ -122,10 +173,7 @@ #endif /* CONFIG_RAMBOOT_PBL */ /* High Level Configuration Options */ -#define CONFIG_E500 /* BOOKE e500 family */ #include <asm/config_mpc85xx.h> -#define CONFIG_BOOKE -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */ @@ -138,15 +186,11 @@ #endif /* CONFIG_RESET_VECTOR_ADDRESS */ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS -#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ - -#define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCI_INDIRECT_BRIDGE - /* The number of available PCI controllers depends on the RCW */ #define CONFIG_PCIE1 /* PCIE controler 1 */ #define CONFIG_PCIE2 /* PCIE controler 2 */ @@ -156,10 +200,16 @@ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_FSL_LAW /* Use common FSL init code */ - #define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x200000 /* Refer to mtdparts */ +/* + * CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|SATA|SPI_FLASH|NVRAM|MMC|FAT|EXT4|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE + */ +#if 0 +/* TODO: move env to boot source */ #if defined(CONFIG_SDCARD) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_MMC @@ -177,6 +227,7 @@ #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif /* CONFIG_SPIFLASH */ +#endif /* * These can be toggled for performance analysis, otherwise use default. @@ -198,7 +249,8 @@ #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ /* #define CONFIG_SYS_DRAM_TEST Executes a memoty test at U-Boot start */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x00200000 #define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_SYS_ALT_MEMTEST @@ -244,16 +296,16 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL (4) #define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SDRAM_SIZE 8192 /* In MByte, for fixed parameter use */ /* * IFC Definitions */ +#ifdef CONFIG_NOR_FLASH #define CONFIG_SYS_FLASH_BASE 0xe8000000 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) - +#endif /* NAND Flash on IFC */ #define CONFIG_NAND_FSL_IFC @@ -274,11 +326,11 @@ CSOR_NAND_RAL_3 | /* RAL = 3Byes */ \ CSOR_NAND_PGS_2K | /* Page Size = 2K */ \ CSOR_NAND_SPRZ_128 | /* Spare size = 128 */ \ - CSOR_NAND_PB(64)) /* Pages Per Block = 64 */ + CSOR_NAND_PB(64) | /* Pages Per Block = 64 */ \ + CSOR_NAND_BCTLD) /* Buffer control disable */ #define CONFIG_SYS_NAND_ONFI_DETECTION -/* ONFI NAND Flash mode0 Timing Params */ #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ @@ -293,43 +345,59 @@ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0xa) #define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 /*#define CONFIG_CMD_NAND*/ + +/* NOR configuation */ +/*#define CONFIG_SYS_NO_FLASH*/ +#define CONFIG_MTD +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_PROTECTION +/*#define CONFIG_SYS_NOR_BASE (0xe8000000) +#define CONFIG_SYS_NOR_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NOR_BASE) +*/ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) + + #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#if defined(CONFIG_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif + +#define CONFIG_SYS_NOR_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) + +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) + +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | /* AVD Toggle Enable during Burst Program */ \ + CSOR_NOR_ADM_SHIFT(7) | /* Address Data Multiplexing Shift */ \ + CSOR_NOR_TRHZ_80) | /* Time for Read Enable High to Output High Impedance */ \ + CSOR_NAND_BCTLD /* Buffer control disable */ + + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE @@ -473,13 +541,12 @@ #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #endif -#define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_E1000 #define CONFIG_E1000_SPI #define CONFIG_CMD_E1000 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_DOS_PARTITION +/* #define CONFIG_DOS_PARTITION */ #endif /* CONFIG_PCI */ /* SATA */ @@ -499,9 +566,10 @@ #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA #define CONFIG_LBA48 -#define CONFIG_DOS_PARTITION +/* #define CONFIG_DOS_PARTITION */ #endif +#define CONFIG_SPI_FLASH_MTD #define CONFIG_USB_EHCI_FSL #define CONFIG_HAS_FSL_DR_USB @@ -510,17 +578,15 @@ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif /* CONFIG_USB_EHCI*/ -#define CONFIG_MMC - #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_CMD_MMC -#define CONFIG_GENERIC_MMC +/* #define CONFIG_GENERIC_MMC */ #define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION +/*#define CONFIG_CMD_FAT*/ +/* #define CONFIG_DOS_PARTITION */ #endif /* Qman/Bman */ @@ -556,8 +622,9 @@ #define CONFIG_QE #define CONFIG_U_QE -#define CONFIG_SYS_QE_FW_ADDR __stringify(CONFIG_LOADADDR) +#if 0 +/* TODO: move FMAN/QE ucode to boot source */ /* Default address of microcode for the Linux Fman driver */ #if defined(CONFIG_SDCARD) /* @@ -567,22 +634,34 @@ */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) + + +#el +#endif +#endif +#if defined(CONFIG_NAND_FLASH_BOOT) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_FMAN_FW_ADDR (0x240000) /* Refer to mtdparts: fman_ucode */ + +/* #define CONFIG_SYS_QE_FW_IN_NAND +#define CONFIG_SYS_QE_FW_LENGTH (0x10000) */ +#define CONFIG_SYS_QE_FW_ADDR (0x280000) /* Refer to mtdparts: qe_ucode */ + #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xe8240000 /* Refer to mtdparts: fman_ucode */ +#define CONFIG_SYS_QE_FW_ADDR 0xe8280000 /* Refer to mtdparts: qe_ucode */ +/* __stringify(CONFIG_LOADADDR) */ #endif - #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET -#define CONFIG_PHY_MARVELL +/*#define CONFIG_PHY_MARVELL*/ #endif #ifdef CONFIG_FMAN_ENET @@ -603,20 +682,20 @@ /* * Command line configuration. */ -#define CONFIG_CMD_ERRATA +/*#define CONFIG_CMD_ERRATA*/ #define CONFIG_CMD_GREPENV -#define CONFIG_CMD_IRQ +/*#define CONFIG_CMD_IRQ*/ #define CONFIG_CMD_MII #define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO +/*#define CONFIG_CMD_REGINFO*/ #ifdef CONFIG_PCI -#define CONFIG_CMD_PCI +/*#define CONFIG_CMD_PCI*/ #endif /* Hash command with SHA acceleration supported in hardware */ #ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH +/*#define CONFIG_CMD_HASH*/ #define CONFIG_SHA_HW_ACCEL #endif @@ -652,11 +731,12 @@ /* * Dynamic MTD Partition support with mtdparts */ -#define CONFIG_CMD_MTDPARTS +/*#define CONFIG_CMD_MTDPARTS*/ #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_NO_FLASH +/*#define CONFIG_SYS_NO_FLASH*/ #ifdef CONFIG_SECURE_BOOT @@ -673,7 +753,7 @@ /* * eSPI - Enhanced SPI */ -#define CONFIG_SPI_FLASH +#if defined(CONFIG_SPI_FLASH) #define CONFIG_FSL_ESPI #define CONFIG_SPI_FLASH_STMICRO @@ -683,104 +763,196 @@ #define CONFIG_SPI_FLASH_BAR #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 +#endif #define MTDIDS_DEFAULT \ - "nor0=fe8000000.nor," \ "nand0=fff800000.flash," \ - "spi0=spife110000.0" + "nor0=fe8000000.nor" -#define MTDPARTS_DEFAULT \ - "mtdparts=fff800000.flash:" \ +#define MTDPART_DEFAULT_PARTITIONS \ "2M@0x0(u-boot)," \ "256k(env)," \ "256k(fman_ucode)," \ - "256k(qe_ucode)," \ - "0x3fc80000(ubipart)," \ - "1M@0x3ff00000(bbt)ro" + "256k(qe_ucode)," -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* Also check for boot interruption, when bootdelay is zero */ -#define CONFIG_BAUDRATE 115200 +#ifdef CONFIG_NAND_FLASH -#define __USB_PHY_TYPE utmi +#endif +#ifdef CONFIG_NOR_FLASH + +#endif +#define MTDPARTS_DEFAULT \ + "mtdparts=fff800000.flash:" \ + MTDPART_DEFAULT_PARTITIONS \ + "0x3fc80000(ubipart_nand)," \ + "1M@0x3ff00000(bbt)ro;" \ + "fe8000000.nor:" \ + MTDPART_DEFAULT_PARTITIONS \ + "-(ubipart_nor)" + +#ifdef CONFIG_NOR_FLASH +#define NOR_ENV \ + "update-uboot-nor-nw=" \ + "dhcp; tftp ${TFTP_PATH}/u-boot-with-spl-pbl.bin.nor;" \ + "if test $? = \"0\"; then " \ + "protect off 0xe8000000 0xe81fffff;" \ + "erase 0xe8000000 0xe81fffff;" \ + "cp.w ${loadaddr} 0xe8000000 ${filesize};" \ + "fi\0" \ + "update-uboot-nor-usb=" \ + "usb start;" \ + "fatload usb 0 ${loadaddr} u-boot-with-spl-pbl.bin.nor;" \ + "if test $? = \"0\"; then " \ + "protect off 0xe8000000 0xe81fffff;" \ + "erase 0xe8000000 0xe81fffff;" \ + "cp.w ${loadaddr} 0xe8000000 ${filesize};" \ + "fi\0" \ + \ + "update-fman-ucode-nor-usb=" \ + "usb start;" \ + "fatload usb 0 ${loadaddr} fsl_fman_ucode_t1040_r1.1_106_4_17.bin;" \ + "if test $? = \"0\"; then " \ + "protect off 0xe8240000 0xe827ffff;" \ + "erase 0xe8240000 0xe827ffff;" \ + "cp.w ${loadaddr} 0xe8240000 ${filesize};" \ + "fi\0" \ + "update-qe-ucode-nor-usb=" \ + "usb start;" \ + "fatload usb 0 ${loadaddr} iram_Type_A_T1040_r1.0.bin;" \ + "if test $? = \"0\"; then " \ + "protect off 0xe8280000 0xe82bffff;" \ + "erase 0xe8280000 0xe82bffff;" \ + "cp.w ${loadaddr} 0xe8280000 ${filesize};" \ + "fi\0" \ + "update-ubi-rootfs-nor="\ + "dhcp;" \ + "ubi part ubipart_nor;" \ + "if test $? = \"0\"; then " \ + "tftp ${TFTP_PATH}/ubi_rootfs_image.nor.ubifs;" \ + "if test $? = \"0\"; then " \ + "ubi write ${loadaddr} rootfs ${filesize};" \ + "fi;" \ + "fi;" \ + "\0" \ + \ + "ubiboot-nor=" \ + "ubi part ubipart_nor;" \ + "ubifsmount ubi0:rootfs;" \ + "ubifsload ${fitaddr} /boot/fitImage.itb;" \ + "run set_ubiboot_args_nor;" \ + "bootm ${fitaddr}#conf@1" \ + "\0" \ + \ + "set_ubiboot_args_nor=setenv bootargs ${bootargs} ${mtdparts} ubi.mtd=ubipart_nor ubi.fm_autoconvert=1 root=ubi0:rootfs rw rootfstype=ubifs \0" +#else +#define NOR_ENV +#endif -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=" \ - "fsl_ddr:bank_intlv=null;"\ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ - "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - \ - "l2switchaddr=02:00:00:ba:be:00\0" \ - "ethaddr=02:00:00:ba:be:01\0" \ - "eth1addr=02:00:00:ba:be:02\0" \ - "eth2addr=02:00:00:ba:be:03\0" \ - "eth3addr=02:00:00:ba:be:04\0" \ - "eth4addr=02:00:00:ba:be:05\0" \ - \ - "autoload=no\0" \ - "fitaddr="__stringify(CONFIG_LOADADDR)"\0" \ - "TFTP_PATH=\0" \ - \ - "mtdids=" MTDIDS_DEFAULT "\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - \ - "setfans=i2c dev 0; i2c mw 0x2e 0x40 1;i2c mw 0x2e 0x7d 0x2;" \ - "i2c mw 0x2e 0x5c 0xe0;i2c mw 0x2e 0x5d 0xe0;i2c mw 0x2e 0x5e 0xe0;" \ - "i2c mw 0x2e 0x5f 0xc8;i2c mw 0x2e 0x60 0xc8;i2c mw 0x2e 0x61 0xc8;" \ - "i2c mw 0x2e 0x30 0x20;i2c mw 0x2e 0x31 0x20;i2c mw 0x2e 0x32 0x20;\0"\ - \ - "update-uboot=dhcp; tftp ${TFTP_PATH}/u-boot-with-spl-pbl.bin; if test $? = \"0\"; then nand erase.part u-boot; nand write ${loadaddr} 0 ${filesize};fi\0" \ - "update-uboot-usb=" \ +#ifdef CONFIG_NAND_FLASH +#define NAND_ENV \ + "update-uboot-nand-nw=" \ + "dhcp;" \ + "tftp ${TFTP_PATH}/u-boot-with-spl-pbl.bin.nand;" \ + "if test $? = \"0\"; then " \ + "nand erase.part u-boot;" \ + "nand write ${loadaddr} 0 ${filesize}; "\ + "fi\0" \ + "update-uboot-nand-usb=" \ "usb start;" \ - "fatload usb 0 ${loadaddr} u-boot-with-spl-pbl.bin;" \ + "fatload usb 0 ${loadaddr} u-boot-with-spl-pbl.bin.nand;" \ "nand erase.part u-boot;" \ "nand write ${loadaddr} u-boot ${filesize};" \ "\0" \ \ - "update-fman-ucode-usb=" \ + "update-fman-ucode-nand-usb=" \ "usb start;" \ "fatload usb 0 ${loadaddr} fsl_fman_ucode_t1040_r1.1_106_4_17.bin;" \ "nand erase.part fman_ucode;" \ "nand write ${loadaddr} fman_ucode ${filesize};" \ "\0" \ \ - "update-qe-ucode-usb=" \ + "update-qe-ucode-nand-usb=" \ "usb start;" \ "fatload usb 0 ${loadaddr} iram_Type_A_T1040_r1.0.bin;" \ "nand erase.part qe_ucode;" \ "nand write ${loadaddr} qe_ucode ${filesize};" \ "\0" \ - "load_qe_ucode="\ - "nand read ${loadaddr} qe_ucode;" \ - "qe fw ${loadaddr};" \ - "\0" \ - \ - "update-ubi-rootfs="\ + "update-ubi-rootfs-nand="\ "dhcp;" \ - "ubi part ubipart;" \ + "ubi part ubipart_nand;" \ "if test $? = \"0\"; then " \ - "tftp ${TFTP_PATH}/fsl-image-core-simc-t1022-tcb-02.ubifs;" \ + "tftp ${TFTP_PATH}/ubi_rootfs_image.nand.ubifs;" \ "if test $? = \"0\"; then " \ "ubi write ${loadaddr} rootfs ${filesize};" \ "fi;" \ "fi;" \ "\0" \ \ - "ubiboot=" \ - "ubi part ubipart;" \ + "ubiboot-nand=" \ + "ubi part ubipart_nand;" \ "ubifsmount ubi0:rootfs;" \ "ubifsload ${fitaddr} /boot/fitImage.itb;" \ - "run set_ubiboot_args;" \ + "run set_ubiboot_args_nand;" \ "bootm ${fitaddr}#conf@1" \ "\0" \ \ - "set_ubiboot_args=setenv bootargs ${bootargs} ${mtdparts} ubi.mtd=3 ubi.fm_autoconvert=1 root=ubi0:rootfs rw rootfstype=ubifs \0" \ + "set_ubiboot_args_nand=setenv bootargs ${bootargs} ${mtdparts} ubi.mtd=ubipart_nand ubi.fm_autoconvert=1 root=ubi0:rootfs rw rootfstype=ubifs \0" +#else +#define NAND_ENV +#endif + +#ifdef CONFIG_NAND_FLASH_BOOT +#define BOOTCMD "ubiboot-nand" +#elif defined(CONFIG_NOR_FLASH_BOOT) +#define BOOTCMD "ubiboot-nor" +#else +#define BOOTCMD "" +#endif + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 +#define CONFIG_BAUDRATE 115200 + + +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=" \ + "fsl_ddr:bank_intlv=null;"\ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ + "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + \ + "l2switchaddr=02:00:00:ba:be:00\0" \ + "ethaddr=02:00:00:ba:be:01\0" \ + "eth1addr=02:00:00:ba:be:02\0" \ + "eth2addr=02:00:00:ba:be:03\0" \ + "eth3addr=02:00:00:ba:be:04\0" \ + "eth4addr=02:00:00:ba:be:05\0" \ + \ + "autoload=no\0" \ + "fitaddr="__stringify(CONFIG_LOADADDR)"\0" \ + "TFTP_PATH=\0" \ + \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + \ + NOR_ENV \ + NAND_ENV \ + \ + "setfans=i2c dev 0; i2c mw 0x2e 0x40 1;i2c mw 0x2e 0x7d 0x2;" \ + "i2c mw 0x2e 0x5c 0xe0;i2c mw 0x2e 0x5d 0xe0;i2c mw 0x2e 0x5e 0xe0;" \ + "i2c mw 0x2e 0x5f 0xc8;i2c mw 0x2e 0x60 0xc8;i2c mw 0x2e 0x61 0xc8;" \ + "i2c mw 0x2e 0x30 0x20;i2c mw 0x2e 0x31 0x20;i2c mw 0x2e 0x32 0x20;\0"\ + \ + "probe-spi-flash=sf probe 0; if test $? = \"0\"; then " \ + "setenv mtdids \"${mtdids}\",nor1=fe110000.spi;" \ + "setenv mtdparts \"${mtdparts};\"fe110000.spi:" MTDPART_DEFAULT_PARTITIONS "-(storage);"\ + ";fi\0" \ \ "netboot=dhcp; tftp ${fitaddr} ${TFTP_PATH}/fitImage.itb; bootm ${fitaddr}#conf@1\0" \ \ - "bootcmd=run setfans; usb start; run ubiboot\0" \ + "bootcmd=run setfans; run "BOOTCMD"\0" \ \ "bootargs_sata=rootfstype=ext3 root=/dev/sda1\0" \ "bootargs=console=ttyS0,115200 rootwait panic=10\0" \ |