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Diffstat (limited to 'include/configs/simc-t10xx.h')
-rw-r--r--include/configs/simc-t10xx.h33
1 files changed, 26 insertions, 7 deletions
diff --git a/include/configs/simc-t10xx.h b/include/configs/simc-t10xx.h
index 8c6f7be..8a13e92 100644
--- a/include/configs/simc-t10xx.h
+++ b/include/configs/simc-t10xx.h
@@ -7,6 +7,8 @@
#ifndef __SIMC_T10XX_H
#define __SIMC_T10XX_H
+#include "simc-t10x0.h"
+
/*
* SIMC-T10xx board configuration file
*/
@@ -18,12 +20,27 @@
/*
* System and DDR clock
*/
-#define CONFIG_SYS_CLK_FREQ 66666666 /* 66.67MHz */
-#define CONFIG_DDR_CLK_FREQ 133333333 /* 133.33MHz */
+#if defined(CONFIG_SYS_CLK_FREQ_66)
+#define CONFIG_SYS_CLK_FREQ 66666666 /* 66.6 MHz */
+#elif defined(CONFIG_SYS_CLK_FREQ_100)
+#define CONFIG_SYS_CLK_FREQ 100000000 /* 100 MHz */
+#endif
+
+#define CONFIG_DDR_CLK_FREQ 133333333 /* 133.33MHz */
#ifdef CONFIG_RAMBOOT_PBL
+
+
+
+/* PBI commands are cpu independent for now */
#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_rcw.cfg
+
+/* Set the RCW config depending on the CPU type */
+#if defined(CONFIG_PPC_T1022)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1022_rcw.cfg
+#elif defined(CONFIG_PPC_T1040)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1040_rcw.cfg
+#endif
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
@@ -661,10 +678,12 @@
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
\
- "ethaddr=00:00:00:ca:fe:00\0" \
- "eth1addr=00:00:00:ca:fe:01\0" \
- "eth2addr=00:00:00:ca:fe:02\0" \
- "eth3addr=00:00:00:ca:fe:03\0" \
+ "l2switchaddr=02:00:00:ba:be:00\0" \
+ "ethaddr=02:00:00:ba:be:01\0" \
+ "eth1addr=02:00:00:ba:be:02\0" \
+ "eth2addr=02:00:00:ba:be:03\0" \
+ "eth3addr=02:00:00:ba:be:04\0" \
+ "eth4addr=02:00:00:ba:be:05\0" \
\
"autoload=no\0" \
"fitaddr="__stringify(CONFIG_LOADADDR)"\0" \