diff options
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/P1022DS.h | 132 | ||||
| -rw-r--r-- | include/configs/a3m071.h | 92 | ||||
| -rw-r--r-- | include/configs/amcc-common.h | 9 | ||||
| -rw-r--r-- | include/configs/corenet_ds.h | 1 | ||||
| -rw-r--r-- | include/configs/lwmon5.h | 68 | ||||
| -rw-r--r-- | include/configs/m28evk.h | 259 | ||||
| -rw-r--r-- | include/configs/microblaze-generic.h | 17 | ||||
| -rw-r--r-- | include/configs/mx28evk.h | 4 | ||||
| -rw-r--r-- | include/configs/mx31pdk.h | 1 | ||||
| -rw-r--r-- | include/configs/omap5_uevm.h | 2 | ||||
| -rw-r--r-- | include/configs/sandbox.h | 11 | ||||
| -rw-r--r-- | include/configs/tx25.h | 1 |
12 files changed, 415 insertions, 182 deletions
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 14d597a..8b13b10 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -34,6 +34,29 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif +#define CONFIG_NAND_FSL_ELBC + +#ifdef CONFIG_NAND +#define CONFIG_SPL +#define CONFIG_SPL_INIT_MINIMAL +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" + +#define CONFIG_SYS_TEXT_BASE 0x00201000 +#define CONFIG_SPL_TEXT_BASE 0xfffff000 +#define CONFIG_SPL_MAX_SIZE 4096 +#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 +#define CONFIG_SPL_RELOC_STACK 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ @@ -84,6 +107,13 @@ #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k + SPL code*/ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE +#endif + + /* DDR Setup */ #define CONFIG_DDR_SPD #define CONFIG_VERY_BIG_RAM @@ -105,6 +135,30 @@ #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ +/* These are used when DDR doesn't use SPD. */ +#define CONFIG_SYS_SDRAM_SIZE 2048 +#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 +#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 +#define CONFIG_SYS_DDR_TIMING_3 0x00010000 +#define CONFIG_SYS_DDR_TIMING_0 0x40110104 +#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 +#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca +#define CONFIG_SYS_DDR_MODE_1 0x00441221 +#define CONFIG_SYS_DDR_MODE_2 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL 0x0a280100 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 +#define CONFIG_SYS_DDR_CONTROL 0xc7000008 +#define CONFIG_SYS_DDR_CONTROL_2 0x24401041 +#define CONFIG_SYS_DDR_TIMING_4 0x00220001 +#define CONFIG_SYS_DDR_TIMING_5 0x02401400 +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 + + /* * Memory map * @@ -118,6 +172,7 @@ * Localbus non-cacheable * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable + * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable @@ -126,38 +181,84 @@ /* * Local Bus Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull #else #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif #define CONFIG_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) +#ifdef CONFIG_NAND +#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#else #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#endif -#define CONFIG_SYS_BR1_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM - -#define CONFIG_SYS_FLASH_BANKS_LIST \ - {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 1024 +#ifndef CONFIG_SYS_MONITOR_BASE +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif +#endif #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO +/* Nand Flash */ +#if defined(CONFIG_NAND_FSL_ELBC) +#define CONFIG_SYS_NAND_BASE 0xff800000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) +#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE + +/* NAND flash config */ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \ + | OR_FCM_PGS /* Large Page*/ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) +#ifdef CONFIG_NAND +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +#else +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +#endif + +#endif /* CONFIG_NAND_FSL_ELBC */ + #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_MISC_INIT_R @@ -177,6 +278,8 @@ #define PIXIS_LBMAP_SWITCH 7 #define PIXIS_LBMAP_MASK 0xF0 #define PIXIS_LBMAP_ALTBANK 0x20 +#define PIXIS_SPD 0x07 +#define PIXIS_SPD_SYSCLK_MASK 0x07 #define PIXIS_ELBC_SPI_MASK 0xc0 #define PIXIS_SPI 0x80 @@ -199,6 +302,9 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} @@ -419,7 +525,6 @@ /* * Environment */ -#ifdef CONFIG_SYS_RAMBOOT #ifdef CONFIG_RAMBOOT_SPIFLASH #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_BUS 0 @@ -433,16 +538,15 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 -#elif defined(CONFIG_NAND_U_BOOT) +#elif defined(CONFIG_NAND) #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) -#else +#elif defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #define CONFIG_ENV_SIZE 0x2000 -#endif #else #define CONFIG_ENV_IS_IN_FLASH #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h index 13f3226..e9af825 100644 --- a/include/configs/a3m071.h +++ b/include/configs/a3m071.h @@ -1,5 +1,5 @@ /* - * Copyright 2012 Stefan Roese <sr@denx.de> + * Copyright 2012-2013 Stefan Roese <sr@denx.de> * * See file CREDITS for list of people who contributed to this * project. @@ -59,6 +59,38 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_MII #define CONFIG_CMD_REGINFO +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_SERVERIP +#define CONFIG_BOOTP_MAY_FAIL +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SERVERIP +#define CONFIG_NET_RETRY_COUNT 3 +#define CONFIG_CMD_LINK_LOCAL +#define CONFIG_NETCONSOLE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_CMD_PING +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS /* needed for UBI */ +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=fc000000.flash" +#define MTDPARTS_DEFAULT "mtdparts=fc000000.flash:512k(u-boot)," \ + "256k(env)," \ + "128k(hwinfo)," \ + "1M(nvramsim)," \ + "128k(dtb)," \ + "5M(kernel)," \ + "128k(sysinfo)," \ + "7552k(root)," \ + "4M(app)," \ + "13568k(data)" +#define CONFIG_LZO /* needed for UBI */ +#define CONFIG_RBTREE /* needed for UBI */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_FIT /* * IPB Bus clocking configuration. @@ -88,7 +120,7 @@ */ #define CONFIG_SYS_FLASH_BASE 0xfc000000 #define CONFIG_SYS_FLASH_SIZE 0x02000000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000) #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 256 @@ -101,6 +133,7 @@ #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_FLASH_VERIFY /* * Environment settings @@ -109,6 +142,8 @@ #define CONFIG_ENV_SIZE 0x10000 #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) /* * Memory map @@ -121,16 +156,14 @@ #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE - -#define CONFIG_SYS_GBL_DATA_SIZE 128 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ - CONFIG_SYS_GBL_DATA_SIZE) + GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_SYS_MALLOC_LEN (1 << 20) +#define CONFIG_SYS_MONITOR_LEN (512 << 10) +#define CONFIG_SYS_MALLOC_LEN (4 << 20) #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* @@ -156,14 +189,14 @@ */ #ifdef CONFIG_A4M2K -#define CONFIG_SYS_GPS_PORT_CONFIG 0x0005C805 +#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C805 #else /* for failsave-level 0 - full failsave */ #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005 /* for failsave-level 1 - only digiboard ok */ -#define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C005 +#define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C065 /* for failsave-level 2 - all ok */ -#define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C005 +#define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C065 #endif #define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7 @@ -173,10 +206,10 @@ /* * Configuration matrix - * MSB LSB + * MSB LSB * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave ) - * failsave 1 0x1005C005 00010000000001011100000000000101 ( digib.-ver ok ) - * failsave 2 0x1005C005 00010000000001011100000000000101 ( all ok ) + * failsave 1 0x1005C065 00010000000001011100000001100101 ( digib.-ver ok ) + * failsave 2 0x1005C065 00010000000001011100000001100101 ( all ok ) * || ||| || | ||| | | | | * || ||| || | ||| | | | | bit rev name * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1 @@ -312,10 +345,12 @@ * Environment Configuration */ -#define CONFIG_BOOTDELAY 0 /* -1 disables auto-boot */ +#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS #define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_SYS_AUTOLOAD "n" + #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \ "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \ @@ -323,11 +358,10 @@ #undef CONFIG_BOOTARGS -#define CONFIG_SYS_OS_BASE 0xfc080000 -#define CONFIG_SYS_FDT_BASE 0xfc060000 +#define CONFIG_SYS_OS_BASE 0xfc200000 +#define CONFIG_SYS_FDT_BASE 0xfc1e0000 #define CONFIG_EXTRA_ENV_SETTINGS \ - "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ "netdev=eth0\0" \ "verify=no\0" \ "loadaddr=200000\0" \ @@ -344,29 +378,31 @@ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2\0" \ + "mtdargs=setenv bootargs root=/dev/mtdblock7 " \ + "rootfstype=squashfs,jffs2\0" \ + "addhost=setenv bootargs ${bootargs} " \ + "hostname=${hostname}\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} " \ "console=${consoledev},${baudrate}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdtaddr}\0" \ - "flash_mtd=run mtdargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdtaddr}\0" \ - "flash_self=run ramargs addip addtty;" \ + "flash_nfs=run nfsargs addip addtty addhost;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "flash_mtd=run mtdargs addip addtty addhost;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "flash_self=run ramargs addip addtty addhost;" \ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ "tftp ${fdt_addr_r} ${fdtfile};" \ - "run nfsargs addip addtty;" \ + "run nfsargs addip addtty addhost;" \ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \ "/u-boot-img.bin\0" \ - "update=protect off fc000000 fc03ffff; " \ - "era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000\0" \ + "update=protect off fc000000 fc07ffff; " \ + "era fc000000 fc07ffff;" \ + "cp.b ${loadaddr} fc000000 ${filesize}\0" \ "upd=run load;run update\0" \ - "bootdelay=3\0" \ - "bootcmd=run net_nfs\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_mtd" diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index f2f522d..80e5735 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -71,6 +71,7 @@ #define CONFIG_CMD_DIAG #define CONFIG_CMD_EEPROM #define CONFIG_CMD_ELF +#define CONFIG_CMD_GREPENV #define CONFIG_CMD_I2C #define CONFIG_CMD_IRQ #define CONFIG_CMD_MII @@ -78,6 +79,7 @@ #define CONFIG_CMD_NFS #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SETEXPR /* * Miscellaneous configurable options @@ -108,13 +110,14 @@ #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE /* include version env variable */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ -#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ #define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ +#define CONFIG_REGEX /* Enable regular expression support */ /* * BOOTP options */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 3f42cd9..5cc9b5a 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -714,6 +714,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ "bank_intlv=cs0_cs1;" \ + "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 2ebcd16..ba613e3 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007-2010 + * (C) Copyright 2007-2013 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * This program is free software; you can redistribute it and/or @@ -37,8 +37,12 @@ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ -#ifndef CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_LCD4_LWMON5 +#define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */ +#define CONFIG_HOSTNAME lcd4_lwmon5 +#else #define CONFIG_SYS_TEXT_BASE 0xFFF80000 +#define CONFIG_HOSTNAME lwmon5 #endif #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ @@ -56,7 +60,7 @@ * actual resources get mapped (not physical addresses) */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */ -#define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1) +#define CONFIG_SYS_MONITOR_LEN 0x80000 #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */ #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 @@ -75,9 +79,11 @@ #define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000) #define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000) +#ifndef CONFIG_LCD4_LWMON5 #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 #define CONFIG_SYS_USB_HOST 0xe0000400 +#endif /* * Initial RAM & stack pointer @@ -87,12 +93,20 @@ * content during reset (GPT0_COMP6). This way we reserve the OCM (16k) * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.) */ +#ifndef CONFIG_LCD4_LWMON5 #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#else +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE +#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) +#endif /* unused GPT0 COMP reg */ #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) #define CONFIG_SYS_OCM_SIZE (16 << 10) @@ -166,8 +180,11 @@ #define CONFIG_SYS_MBYTES_SDRAM 256 #define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ +#ifndef CONFIG_LCD4_LWMON5 #define CONFIG_DDR_ECC /* enable ECC */ +#endif +#ifndef CONFIG_LCD4_LWMON5 /* POST support */ #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ CONFIG_SYS_POST_CPU | \ @@ -276,6 +293,7 @@ #define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1) #define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE) #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ +#endif /* * I2C @@ -395,6 +413,7 @@ #define CONFIG_VIDEO_SW_CURSOR #define CONFIG_SPLASH_SCREEN +#ifndef CONFIG_LCD4_LWMON5 /* * USB/EHCI */ @@ -410,6 +429,7 @@ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_ISO_PARTITION +#endif /* * BOOTP options @@ -444,9 +464,11 @@ #define CONFIG_CMD_BMP #endif +#ifndef CONFIG_LCD4_LWMON5 #ifdef CONFIG_440EPX #define CONFIG_CMD_USB #endif +#endif /* * Miscellaneous configurable options @@ -480,11 +502,15 @@ #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ + +#ifndef CONFIG_LCD4_LWMON5 #ifndef DEBUG #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ #endif #define CONFIG_WD_PERIOD 40000 /* in usec */ #define CONFIG_WD_MAX_RATE 66600 /* in ticks */ +#endif /* * For booting Linux, the board info and command line data @@ -644,4 +670,40 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + +/* + * SPL related defines + */ +#ifdef CONFIG_LCD4_LWMON5 +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_NOR_SUPPORT +#define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */ +#define CONFIG_SYS_SPL_MAX_LEN (64 << 10) +#define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */ +#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/ppc4xx" +#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/ppc4xx/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ +#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ +#define CONFIG_SPL_SERIAL_SUPPORT + +/* Place BSS for SPL near end of SDRAM */ +#define CONFIG_SPL_BSS_START_ADDR ((256 - 1) << 20) +#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10) + +#define CONFIG_SPL_OS_BOOT +/* Place patched DT blob (fdt) at this address */ +#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000 + +#define CONFIG_SPL_TARGET "u-boot-img-spl-at-end.bin" + +/* Settings for real U-Boot to be loaded from NOR flash */ +#define CONFIG_SYS_UBOOT_BASE (-CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_UBOOT_START 0x01002100 + +#define CONFIG_SYS_OS_BASE 0xf8000000 +#define CONFIG_SYS_FDT_BASE 0xf87c0000 +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index f2725cc..4ce4058 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -23,71 +23,74 @@ /* * SoC configurations */ -#define CONFIG_MX28 /* i.MX28 SoC */ -#define CONFIG_MXS_GPIO /* GPIO control */ -#define CONFIG_SYS_HZ 1000 /* Ticks per second */ +#define CONFIG_MX28 /* i.MX28 SoC */ +#define CONFIG_MXS_GPIO /* GPIO control */ +#define CONFIG_SYS_HZ 1000 /* Ticks per second */ /* * Define M28EVK machine type by hand until it lands in mach-types */ -#define MACH_TYPE_M28EVK 3613 +#define MACH_TYPE_M28EVK 3613 -#define CONFIG_MACH_TYPE MACH_TYPE_M28EVK +#define CONFIG_MACH_TYPE MACH_TYPE_M28EVK #include <asm/arch/regs-base.h> -#define CONFIG_SYS_NO_FLASH -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ARCH_MISC_INIT +#define CONFIG_SYS_NO_FLASH +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_MISC_INIT /* * SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_NO_CPU_SUPPORT_CODE -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL +#define CONFIG_SPL_NO_CPU_SUPPORT_CODE +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT /* * U-Boot Commands */ #include <config_cmd_default.h> -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DOS_PARTITION +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_GPIO -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_MMC -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_SETEXPR -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI -#define CONFIG_CMD_USB +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_USB + +#define CONFIG_REGEX /* Enable regular expression support */ /* * Memory configurations */ -#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ -#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ -#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ -#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ +#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ +#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ +#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Point initial SP in SRAM so SPL can use it too. */ #define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 @@ -102,42 +105,42 @@ * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot * binary. In case there was more of this mess, 0x100 bytes are skipped. */ -#define CONFIG_SYS_TEXT_BASE 0x40000100 +#define CONFIG_SYS_TEXT_BASE 0x40000100 /* * U-Boot general configurations */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_PBSIZE \ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ -#define CONFIG_AUTO_COMPLETE /* Command auto complete */ -#define CONFIG_CMDLINE_EDITING /* Command history etc */ -#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER /* * Serial Driver */ -#define CONFIG_PL011_SERIAL -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ /* * MMC Driver */ #ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_BOUNCE_BUFFER -#define CONFIG_GENERIC_MMC -#define CONFIG_MXS_MMC +#define CONFIG_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_GENERIC_MMC +#define CONFIG_MXS_MMC #endif /* @@ -148,31 +151,31 @@ /* * NAND */ -#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_ENV_SIZE (16 * 1024) #ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_MXS -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x60000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x60000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE /* Environment is in NAND */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_RANGE (512 * 1024) -#define CONFIG_ENV_OFFSET 0x300000 -#define CONFIG_ENV_OFFSET_REDUND \ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_RANGE (512 * 1024) +#define CONFIG_ENV_OFFSET 0x300000 +#define CONFIG_ENV_OFFSET_REDUND \ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS -#define CONFIG_CMD_MTDPARTS -#define CONFIG_RBTREE -#define CONFIG_LZO -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS -#define MTDIDS_DEFAULT "nand0=gpmi-nand" -#define MTDPARTS_DEFAULT \ +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nand0=gpmi-nand" +#define MTDPARTS_DEFAULT \ "mtdparts=gpmi-nand:" \ "3m(bootloader)ro," \ "512k(environment)," \ @@ -182,34 +185,34 @@ "8m(ramdisk)," \ "-(filesystem)" #else -#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_NOWHERE #endif /* * Ethernet on SOC (FEC) */ #ifdef CONFIG_CMD_NET -#define CONFIG_ETHPRIME "FEC0" -#define CONFIG_FEC_MXC -#define CONFIG_MII -#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC0" +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RMII #endif /* * I2C */ #ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MXS -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_I2C_MXS +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 400000 #endif /* * EEPROM */ #ifdef CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #endif /* @@ -217,13 +220,13 @@ */ #ifdef CONFIG_CMD_DATE /* Use the internal RTC in the MXS chip */ -#define CONFIG_RTC_INTERNAL +#define CONFIG_RTC_INTERNAL #ifdef CONFIG_RTC_INTERNAL -#define CONFIG_RTC_MXS +#define CONFIG_RTC_MXS #else -#define CONFIG_RTC_M41T62 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 2000 +#define CONFIG_RTC_M41T62 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 #endif #endif @@ -231,59 +234,59 @@ * USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_MXS +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MXS #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_EHCI_MXS_PORT1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE #endif /* * SPI */ #ifdef CONFIG_CMD_SPI -#define CONFIG_HARD_SPI -#define CONFIG_MXS_SPI -#define CONFIG_SPI_HALF_DUPLEX -#define CONFIG_DEFAULT_SPI_BUS 2 -#define CONFIG_DEFAULT_SPI_CS 0 -#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 +#define CONFIG_HARD_SPI +#define CONFIG_MXS_SPI +#define CONFIG_SPI_HALF_DUPLEX +#define CONFIG_DEFAULT_SPI_BUS 2 +#define CONFIG_DEFAULT_SPI_CS 0 +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 /* SPI FLASH */ #ifdef CONFIG_CMD_SF -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SF_DEFAULT_BUS 2 -#define CONFIG_SF_DEFAULT_CS 0 -#define CONFIG_SF_DEFAULT_SPEED 40000000 -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SF_DEFAULT_BUS 2 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_ENV_SPI_BUS 2 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 40000000 -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 +#define CONFIG_ENV_SPI_BUS 2 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 40000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 #endif #endif /* * Boot Linux */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " -#define CONFIG_BOOTCOMMAND "run bootcmd_net" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_OF_LIBFDT +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " +#define CONFIG_BOOTCOMMAND "run bootcmd_net" +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_OF_LIBFDT /* * Extra Environments */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ "update_nand_full_filename=u-boot.nand\0" \ "update_nand_firmware_filename=u-boot.sb\0" \ "update_sd_firmware_filename=u-boot.sd\0" \ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index d172e56..0c4e719 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -120,6 +120,14 @@ # define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ #endif +/* watchdog */ +#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ) +# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR +# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ +# define CONFIG_HW_WATCHDOG +# define CONFIG_XILINX_TB_WATCHDOG +#endif + /* * memory layout - Example * CONFIG_SYS_TEXT_BASE = 0x1200_0000; defined in config.mk @@ -414,10 +422,17 @@ "nor0=flash-0\0"\ "mtdparts=mtdparts=flash-0:"\ "256k(u-boot),256k(env),3m(kernel),"\ - "1m(romfs),1m(cramfs),-(jffs2)\0" + "1m(romfs),1m(cramfs),-(jffs2)\0"\ + "nc=setenv stdout nc;"\ + "setenv stdin nc\0" \ + "serial=setenv stdout serial;"\ + "setenv stdin serial\0" #define CONFIG_CMDLINE_EDITING +#define CONFIG_NETCONSOLE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + /* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index d470b47..3747955 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -138,14 +138,14 @@ #define CONFIG_SYS_NAND_5_ADDR_CYCLE /* Environment is in NAND */ +#ifdef CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_ENV_RANGE (512 * 1024) -#ifndef CONFIG_ENV_OFFSET #define CONFIG_ENV_OFFSET 0x300000 -#endif #define CONFIG_ENV_OFFSET_REDUND \ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) +#endif #define CONFIG_CMD_UBI #define CONFIG_CMD_UBIFS diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 1754595..82ea4fa 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -50,6 +50,7 @@ #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" #define CONFIG_SPL_MAX_SIZE 2048 #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_TEXT_BASE 0x87dc0000 #define CONFIG_SYS_TEXT_BASE 0x87e00000 diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 240fdfc..550cabd 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -44,6 +44,8 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ #define CONFIG_ENV_OFFSET 0xE0000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_CMD_SAVEENV /* Enhance our eMMC support / experience. */ diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 406da43..788207d 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -22,15 +22,15 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_DRAM_SIZE (128 << 20) - /* Number of bits in a C 'long' on this architecture */ #define CONFIG_SANDBOX_BITS_PER_LONG 64 #define CONFIG_OF_CONTROL +#define CONFIG_OF_HOSTFILE #define CONFIG_OF_LIBFDT #define CONFIG_LMB +#define CONFIG_FIT +#define CONFIG_CMD_FDT #define CONFIG_FS_FAT #define CONFIG_FS_EXT4 @@ -74,9 +74,14 @@ #define CONFIG_SYS_MEMTEST_START 0x00100000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1000) #define CONFIG_PHYS_64BIT +#define CONFIG_SYS_FDT_LOAD_ADDR 0x1000000 /* Size of our emulated memory */ +#define CONFIG_SYS_SDRAM_BASE 0 #define CONFIG_SYS_SDRAM_SIZE (128 << 20) +#define CONFIG_SYS_TEXT_BASE 0 +#define CONFIG_SYS_MONITOR_BASE 0 +#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ diff --git a/include/configs/tx25.h b/include/configs/tx25.h index e72f8f6..d61a218 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -37,6 +37,7 @@ #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" #define CONFIG_SPL_MAX_SIZE 2048 #define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_TEXT_BASE 0x810c0000 #define CONFIG_SYS_TEXT_BASE 0x81200000 |