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Some travis QEMU tests can transfer files between the build directory
and the guest U-Boot instance. For that to work, both need to have access
to the same directory.
This patch puts the current build path into an environment variable, so
that the environment generating python scripts can extract it from there
and read the respective files.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
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The network test currently downloads files at 0MB offset of RAM start.
This works for most ARM systems, but x86 has weird memory layout constraints
on the first MB of RAM.
To not get caught into any of these, let's add a 4MB pad from start
of RAM to the default memory offset.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
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It should be 112M, to make rootfs start at 0x40000
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
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This adds support for the Asus Chromebook Flip, an RK3288-based clamshell
device which can flip into 'tablet' mode. The device tree file comes from
Linux v4.8. The SDRAM parameters are for 4GB Samsung LPDDR3.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This adds support for the Asus Chromebit, and RK3288-based device designed
to plug directly into an HDMI monitor. The device tree file comes from
Linux v4.8.
Signed-off-by: Simon Glass <sjg@chromium.org>
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It makes not sense using u8 to hold a value on a 32-bit or 64-bit machine.
It can only bloat the code by forcing the compiler to mask the value.
Change it to uint.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Update board_init() to increase the ARM clock to the maximum speed on
veyron boards. This makes quite a large difference in performance. With
this change, speed goes from about 750 DMIPS to 2720 DMIPs.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add basic support for setting the ARM clock, since this allows us to run
at maximum speed in U-Boot. Currently only a single speed is supported
(1.8GHz).
Signed-off-by: Simon Glass <sjg@chromium.org>
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The SDRAM settings are not common across all veyron models. Move the
current settings into Jerry's file.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add a comment to indicate that we are not supporting the PWM regulator
yet.
Signed-off-by: Simon Glass <sjg@chromium.org>
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At present we have a single rk3288-based Chromebook: chromebook_jerry. But
all such Chromebooks can use the same binary with only device-tree
differences. The family name is 'veyron', so rename the files accordingly.
Also update the device-tree filename since this currently differs from
Linux.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Adjust jerry to use of-platdata like other rk3288 boards. This reduces the
SPL size enough that it boots again.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Check whether a display device is in use before using it. Add a comment as
to why two displays cannot currently be used at the same time.
This allows us to remove the device-tree change that disables vopb on
jerry.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Mark a display as in use when display_enable() is called. This can avoid
a display being used by multiple video-output devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Sometimes the frame buffer is not a multiple of the cache line size.
Adjust the cache-flushing code to avoid cache warnings/errors in this
case.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This is an uncommon error but we may as well have a debug() message when
it happens.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This is not currently implemented. Add support for this so that the Chrome
OS EC can be used on jerry.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Allow this driver to be used with of-platdata on rk3288.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Some boards may want to use these subsystems with of-platdata in SPL. Add
support for this by avoiding any device tree access in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The current code assumes that the devices are ordered corresponding to
their alias value. But (for example) video1 can come before video0 in the
device tree.
Correct this, by always looking for device 0 first. After that we can fall
back to finding the first available device.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Fix a few code style nits in stdio_get_by_name().
Signed-off-by: Simon Glass <sjg@chromium.org>
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This board always boots from SPI, so update the code to support that with
of-platdata. The boot source is not currently available with of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This code incorrectly uses the oscillator. It should use the clock
selected in the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 135aa95 (clk: convert API to match reset/mailbox style)
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This code currently always selects the second source. It only worked
because both sources are set up.
With the change to only init video devices that are present in the stdout
environment variable, this fails. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
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add fix regulator node for usb vbus power control.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
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usb host vbus power is using gpio fix regulator, enable it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
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rk3036 using dwc2 usb controller, need enable relate configs for it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
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PWM_ROCKCHIP need to enable for PWM regulator, this config
is missing during rebase and new patch set in previous submission.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
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The size dram node need to be deduced by the same amount of reserved space.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
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UART,s -> UARTs, to avoid this spreading via copy&paste.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Simon Glass <sjg@chromium.org>
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Sort rk3036 before rk3288.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Simon Glass <sjg@chromium.org>
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Currently the specific set ops functions are directly
called without any check for min/max current limits for a regulator.
Check for them and proceed.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Fixed checking of current limits:
Signed-off-by: Simon Glass <sjg@chromium.org>
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Currently the specific set ops functions are directly
called without any check for voltage limits for a regulator.
Check for them and proceed.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fixed checking of voltate limits:
Signed-off-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
arch/arm/Kconfig
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In case we want to force a particular value on a regulator
irrespective of the min/max constraints for testing purposes
one can call regulator_set_value_force function.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Let get_maintainers.pl pick up the new cmd/fdt.c.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Commit ec6617c3 includes autoconf.h in image-fit.c, causing conflict
for board odroid-xu3 which overwrites CONFIG_SYS_BOARD in header
file. Move the include higher and use linux/kconfig.h instead of
generated/autoconf.h.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
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To align with SPL change 38fed8ab and 693d4c9f, add Kconfig option
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to defconfig, and remove
CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Feng Li <feng.li_2@nxp.com>
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Add serial platform data to board file.
Enable driver model for PXA serial driver.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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With em humble DM and Kconfig migraters U-Boot binary size keeps
increasing. Drop a bunch of less needed stuff to save another precious
20+ KB.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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Optional driver model handling integration.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Marek Vasut <marex@denx.de>
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Migrate the PXA serial driver to be configured via Kconfig.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Marek Vasut <marex@denx.de>
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As PSCI and secure monitor firmware framework are enabled, this patch is
to support loading 32-bit OS in such case. The default target exception
level returned to U-Boot is EL2, so the corresponding work to switch to
AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware
together.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Spin-table method is used for secondary cores to load 32-bit OS. The
architecture information will be got through checking FIT image and
saved in the os_arch element of spin-table, then the secondary cores
will check os_arch and jump to 32-bit OS or 64-bit OS automatically.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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To support loading a 32-bit OS, the execution state will change from
AArch64 to AArch32 when jumping to kernel.
The architecture information will be got through checking FIT image,
then U-Boot will load 32-bit OS or 64-bit OS automatically.
Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Remove the custom low-level initialization function and reuse the
default low-level initialization function. But this requires the
ARMV8_MULTIENTRY config option to be enabled for Exynos7420.
On Exynos7420, the boot CPU belongs to the second cluster and so
with ARMV8_MULTIENTRY config option enabled, the 'branch_if_master'
macro fails to detect the CPU as boot CPU. As a temporary workaround
the CPU_RELEASE_ADDR is set to point to '_main'.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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NXP ARMv8 SoC LS2080A release all secondary cores in one-go.
But other new SoCs like LS2088A, LS1088A release secondary
cores one by one.
Update code to release secondary cores based on SoC SVR
Add code to release cores one by one for non LS2080A SoCs
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: remove "inline" from declaration of initiator_type]
Reviewed-by: York Sun <york.sun@nxp.com>
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The QorIQ LS2088A SoC is built on layerscape architecture.
It is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)It supports TZASC module
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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