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2016-09-22configs: fsl: Move SPI/SPI-FLASH configs to defconfigJagan Teki
Moved FSL_QSPI/SPI/SPI-FLASH configs from include/configs into respective used defconfigs. - CONFIG_FSL_QSPI - CONFIG_SPI_FLASH - CONFIG_SPI_FLASH_BAR - CONFIG_SPI_FLASH_STMICRO Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-22spi: Kconfig: Move FSL_QSPI entry to non-dm placeJagan Teki
Since FSL_QSPI driver still supporting non-dm code better to move the Kconfig from DM undefined place. Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-21sf: Move flags macro's to spi_flash_params{} membersJagan Teki
This patch moves flags macro's to respective member position on spi_flash_params{}, for better readabilty and finding the respective member macro's easily. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-21sf: Add CONFIG_SPI_FLASH_USE_4K_SECTORS in spi_flashJagan Teki
Add CONFIG_SPI_FLASH_USE_4K_SECTORS in spi_flash code from header file. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-21sf: Remove SECT_32KJagan Teki
SECT_32K never used anywhere in the code. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-21spi: Remove SPI_RX_FASTJagan Teki
Removed SPI_RX_FAST since default read for spi slaves are always 1-wire fast read. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-21spi: Use mode for rx mode flagsJagan Teki
Make rx mode flags as generic to spi, earlier mode_rx is maintained separately because of some flash specific code. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-21sf: Remove e_rd_cmd from param tableJagan Teki
e_rd_cmd is maintained separately for fastest read command code, since the read commands are computed normally this e_rd_cmd is not required in spi_flash_params table. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-21sf: Simplify fastest read cmd codeJagan Teki
Fastest read command code look for fastest read command taking inputs from spi->mode_rx and flags from param table and controller mode_rx is always been a priority. Since mode_rx is always set from controller side this optimized code doesn't require much and this code required exctra overhead like 1) Maintain e_rx_cmd in param table 2) Maintain mode_rx in spi_slave {} Hence removed this code, and look for read command from normal spi->mode from spi_slave{} and params->flags Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-09-21spi: ti_qspi: Remove unnecessary udelay for AM437xVignesh R
This udelay() was added as an HACK and is no longer required. All read/write/erase operations work fine even without this delay. Hence, remove the udelay() call. Tested read/write/erase operation on AM437x SK. Also tested QSPI Boot. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-09-21spi: ti_qspi: use 128 bit transfer mode when writing to flashVignesh R
TI QSPI has four 32 bit data registers which can be used to transfer 16 bytes of data at once. The register group QSPI_SPI_DATA_REG_3, QSPI_SPI_DATA_REG_2, QSPI_SPI_DATA_REG_1 and QSPI_SPI_DATA_REG is treated as a single 128-bit word for shifting data in and out. The bit at QSPI_SPI_DATA_REG_3[31] position is the first bit to be shifted out in case of 128 bit transfer mode. Therefore the first byte to be written to flash should be at QSPI_SPI_DATA_REG_3[31-25] position. Instead of writing 1 byte at a time when interacting with SPI NOR flash, make use of all the four registers so that 16 bytes can be transferred in one go. With this patch, the flash write speed increases from ~250KBs/ to ~650KB/s on DRA74 EVM. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-09-21spi: zynq_spi: Fix infinite looping while xferLad, Prabhakar
During spi transfer, for example: sspi 1:1.0 8 ff the rx_len values will be: rx_len = 0 rx_len = 4294967295 This caused a busy looping during xfer, this patch fixes it by adding a check while reading the rx fifo Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-09-19Revert "Increase default of CONFIG_SYS_MALLOC_F_LEN for SPL_OF_CONTROL"Masahiro Yamada
This reverts commit 90c08d9e08c7a108ab904f3bbdeb558081757892. I took a closer look at this after the commit was applied, and found CONFIG_SYS_MALLOC_F_LEN=0x2000 was too much. 8KB memory for SPL is actually too big for some boards. Perhaps 0x800 is enough, but the situation varies board by board. Let's postpone our decision until we come up with a better idea. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-19A20-OLinuXino-Lime2: Enable USB gadget supportTom Rini
Based on A13-OLinuXino, enable DFU and UMS support. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini
2016-09-18Merge branch 'master' of git://www.denx.de/git/u-boot-sunxiTom Rini
2016-09-18Merge branch 'master' of git://www.denx.de/git/u-boot-arcTom Rini
2016-09-18ARM: uniphier: update DRAM init code for LD20 SoCMasahiro Yamada
Import the latest version from the Diag software. - Support LD21 SoC (including DDR chips in the package) - Per-board granule adjustment for both reference and TV boards - Misc cleanups Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: add PLL init code for LD20 SoCMasahiro Yamada
Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: collect clock/PLL init code into a single directoryMasahiro Yamada
Now PLLs for DRAM controller are initialized in SPL, and the others in U-Boot proper. Setting up all of them in a single directory will be helpful when we want to share code between SPL and U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: move PLL init code to U-Boot proper where possibleMasahiro Yamada
The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: rename CONFIG_DPLL_SSC_RATE_1PERMasahiro Yamada
Basically, this should not be configured by users. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: move XIRQ pin-mux settings of LD11/LD20Masahiro Yamada
This is the last code in the mach-uniphier/pinctrl/ directory. Push the remaining code out to delete the directory entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: consolidate System Bus pin-mux settings for LD11/LD20Masahiro Yamada
Use the pin-mux data in the pinctrl drivers by directly calling pinctrl_generic_set_state(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: dts: uniphier: include System Bus pin group node in SPL DTMasahiro Yamada
This will be needed for setting up the System Bus pin-mux via the LD11/LD20 pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: consolidate NAND pin-mux settingsMasahiro Yamada
The NAND subsystem has not supported the Driver Model yet, but the NAND pin-mux data are already in the pinctrl drivers. Use them by calling pinctrl_generic_set_state() directly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: remove ad-hoc pin-mux code for sLD3Masahiro Yamada
These settings are nicely cared by the pinctrl driver now. Remove. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: remove redundant pin-muxing for EA24 pin of sLD3 SoCMasahiro Yamada
This is enabled by default for all the supported boot modes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: uniphier: select PINCTRL and SPL_PINCTRLMasahiro Yamada
Now all UniPhier SoCs support a pinctrl driver. Select (SPL_)PINCTRL since it is mandatory even for base use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18ARM: dts: uniphier: add pinctrl device node and pinctrl propertiesMasahiro Yamada
DT-side updates to make pinctrl on sLD3 SoC really available. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18pinctrl: uniphier: add UniPhier sLD3 pinctrl driverMasahiro Yamada
Add pin-mux support for UniPhier sLD3 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18pinctrl: uniphier: support 4bit-width pin-mux register capabilityMasahiro Yamada
On LD4 SoC or later, the pin-mux registers are 8bit wide, while 4bit wide on sLD3 SoC. Support it for the sLD3 pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18sunxi: Enable USB gadget support for Sinlinx SinA33Chen-Yu Tsai
Sinlinx SinA33 has a USB OTG port, but VBUS is controlled manually from a jumper pad. Enable OTG in gadget mode, as well as the download gadget and related functions. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Enable USB host support for Sinlinx SinA33Chen-Yu Tsai
Sinlinx SinA33 has 1 USB host port. Enable EHCI_HCD support for it. Also enable USB mass storage support so we can access USB sticks. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Add mmc0 card detect pin for Sinlinx SinA33Chen-Yu Tsai
Sinlinx SinA33 uses PB4 for mmc0 card detect. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Add defconfig and dts for the NanoPi NEOJelle van der Waa
The NanoPi NEO is a simple h3 board with 512MB RAM, ethernet, one usb and one usb OTG connector. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: musb: Re-init musb controller on repeated probe callsHans de Goede
With sunxi-musb musb_lowlevel_init() can fail when a charger; or no cable is plugged into the otg port. To avoid leaking the struct musb allocated by musb_init_controller() on repeated musb_usb_probe() calls, we were caching its result. But musb_init_controller() does more, such as calling sunxi_musb_init() which enables the clocks. Not calling sunxi_musb_init() causes the musb controller to stop working after a "usb reset" since that calls musb_usb_remove() which disables the clocks. This commit fixes this by removing the caching of the struct returned from musb_init_controller(), it replaces this by free-ing the allocated memory in musb_usb_remove() and calling musb_usb_remove() on musb_usb_probe() errors to ensure proper cleanup. While at it also make musb_usb_probe() and musb_usb_remove() static. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-17sunxi: musb: Power off OTG port VBUS when disabledChen-Yu Tsai
The Linux kernel musb driver expects VBUS to be off while initializing musb. Having it on results in a repeating string of warnings, followed by an unusable peripheral. The peripheral is only usable after physically removing the OTG adapter, letting musb reset its state. This partially reverts commit c9f8947e6604 ("sunxi: usb-phy: Never power off the usb ports") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-17sunxi: axp2xx: disable ldoio0/1 at bootHans de Goede
When cold-booting the ldoio0/1 regulators are always off / the gpios are always at tristate. But when re-booting from android these are sometimes on. Disable them at axp_init time (iow as early as possible) to remove this difference between a cold boot and a reboot. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-16Makefile: Give a build error if ad-hoc CONFIG options are addedSimon Glass
New CONFIG options should be added via Kconfig. To help prevent new ad-hoc CONFIGs from being added, give a build error when these are detected. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
2016-09-16Kconfig: Add a whitelist of ad-hoc CONFIG optionsSimon Glass
Add a list of ad-hoc CONFIG options that don't use Kconfig. This can be used to check that new ones are not being added. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_YMODEM_SUPPORT to KconfigSimon Glass
Convert CONFIG_SPL_YMODEM_SUPPORT to Kconfig Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_WATCHDOG_SUPPORT to KconfigSimon Glass
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_USB_SUPPORT to KconfigSimon Glass
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_USB_HOST_SUPPORT to KconfigSimon Glass
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_USBETH_SUPPORT to KconfigSimon Glass
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_SPI_SUPPORT to KconfigSimon Glass
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_SPI_FLASH_SUPPORT to KconfigSimon Glass
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_SERIAL_SUPPORT to KconfigSimon Glass
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_SATA_SUPPORT to KconfigSimon Glass
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
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