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2017-05-08Merge branch 'next' of git://git.denx.de/u-boot-spiTom Rini
2017-05-08Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
2017-05-08ARM: keystone2: Add support for getting external clock dynamicallyLokesh Vutla
One some keystone2 platforms like K2G ICE, there is an option to switch between 24MHz or 25MHz as sysclk. But the existing driver assumes it is always 24MHz. Add support for getting all reference clocks dynamically by reading boot pins. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08ARM: k2g: Add support for dynamic programming of PLL based on SYSCLKLokesh Vutla
K2G supports various sysclk frequencies which can be determined using sysboot pins. PLLs should be configured based on this sysclock frequency. Add PLL configurations for all supported sysclk frequencies. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08configs: ks2: Enable TI_COMMON_CMD_OPTIONSLokesh Vutla
Enable TI_COMMON_CMD_OPTIONS on all keystone2 platforms. Also sync with savedefconfig. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-05-08configs: dra7xx: Enable TI_COMMON_CMD_OPTIONSLokesh Vutla
Enable TI_COMMON_CMD_OPTIONS on all dra7xx platforms. Also sync with savedefconfig. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-05-08configs: am57xx: Enable TI_COMMON_CMD_OPTIONSLokesh Vutla
Enable TI_COMMON_CMD_OPTIONS on all am57xx platforms. Also sync with savedefconfig Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-05-08configs: am43xx: Enable TI_COMMON_CMD_OPTIONSLokesh Vutla
Enable TI_COMMON_CMD_OPTIONS on all am43xx platforms. Also sync with savedefconfig. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-05-08configs: am335x: Enable TI_COMMON_CMD_OPTIONSLokesh Vutla
Enable TI_COMMON_CMD_OPTIONS on all am335x platforms. Also sync with savedefconfig. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [trini: Re-sync, add in boneblack*, evm_hs_{norboot,spiboot,usbspl} configs] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-08board: ti: Define Kconfig symbol for common cmd optionsLokesh Vutla
Instead of defining command options in every defconfig, define a common Kconfig symbol that consolidates all command options that are supported by any TI platform. Also use imply keyword so that that specific option can be disabled if not required. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08Add ARM errata workaround 852421 and 852423 for Cortex-A17Nisal Menuka
ARM errata 852421 and 852423 applies to r1p0, r1p1 and r1p2 revisions of Cortex-A17 processors. These workarounds exist in Linux kernel and I thought it would be better to add them in to U-Boot. Signed-off-by: Nisal Menuka <nisalmenuka23@gmail.com>
2017-05-08aspeed: Cleanup ast2500-u-boot.dtsi Device Treemaxims@google.com
Remove unnecessary apb and ahb nodes and just override necessary nodes/values. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: Refactor SCU to use consistent mask & shiftmaxims@google.com
Refactor SCU header to use consistent Mask & Shift values. Now, consistently, to read value from SCU register, mask needs to be applied before shift. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: Add support for Clocks needed by MACsmaxims@google.com
Add support for clocks needed by MACs to ast2500 clock driver. The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and PCLK_MAC2 for MAC1 and MAC2 respectively. The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed SDK. It is not entirely clear from the datasheet how this clock is used by MACs, so not clear if the rate would ever need to be different. So, for now, hardcoding it is probably safer. The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through hardware strapping. So, the network driver would only need to enable these clocks, no need to configure the rate. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: Enable I2C in EVB defconfigmaxims@google.com
Enable I2C driver in ast2500 Eval Board defconfig. Also enable i2c command. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: Add I2C Drivermaxims@google.com
Add Device Model based I2C driver for ast2500/ast2400 SoCs. The driver is very limited, it only supports master mode and synchronous byte-by-byte reads/writes, no DMA or Pool Buffers. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
2017-05-08aspeed: Add P-Bus clock in ast2500 clock drivermaxims@google.com
Add P-Bus Clock support to ast2500 clock driver. This is the clock used by I2C devices. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: Enable Pinctrl Driver in AST2500 EVBmaxims@google.com
Enable Pinctrl Driver in AST2500 Eval Board's defconfig Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: AST2500 Pinctrl Drivermaxims@google.com
This driver uses Generic Pinctrl framework and is compatible with the Linux driver for ast2500: it uses the same device tree configuration. Not all pins are supported by the driver at the moment, so it actually compatible with ast2400. In general, however, there are differences that in the future would be easier to maintain separately. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: Refactor AST2500 RAM Driver and Sysreset Drivermaxims@google.com
This change switches all existing users of ast2500 Watchdog to Driver Model based Watchdog driver. To perform system reset Sysreset Driver uses first Watchdog device found via uclass_first_device call. Since the system is going to be reset anyway it does not make much difference which watchdog is used. Instead of using Watchdog to reset itself, SDRAM driver now uses Reset driver to do that. These were the only users of the old Watchdog API, so that API is removed. This all is done in one change to avoid having to maintain dual API for watchdog in between. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: Device Tree configuration for Reset Drivermaxims@google.com
Add Reset Driver configuration to ast2500 SoC Device Tree and bindings for various reset signals Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: Reset Drivermaxims@google.com
Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to perform resets and thus depends on it. The actual Watchdog device used needs to be configured in Device Tree using "aspeed,wdt" property, which must be WDT phandle, for example: rst: reset-controller { compatible = "aspeed,ast2500-reset"; aspeed,wdt = <&wdt1>; } Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: Make SCU lock/unlock functions part of SCU APImaxims@google.com
Make functions for locking and unlocking SCU part of SCU API. Many drivers need to modify settings in SCU and thus need to unlock it first. This change makes it possible. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: Watchdog Timer Drivermaxims@google.com
This driver supports ast2500 and ast2400 SoCs. Only ast2500 supports reset_mask and thus the option of resettting individual peripherals using WDT. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08dm: Simple Watchdog uclassmaxims@google.com
This is a simple uclass for Watchdog Timers. It has four operations: start, restart, reset, stop. Drivers must implement start, restart and stop operations, while implementing reset is optional: It's default implementation expires watchdog timer in one clock tick. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08aspeed: Update ast2500 Device Treemaxims@google.com
Pull in the Device Tree for ast2500 from the mainline Linux kernel. The file is copied from https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08ARM: DT: STM32F746: add u-boot, dm-pre-reloc property to sub nodesVikas Manocha
This patch is required for correct SPL device tree creation by fdtgrep as fdtgrep looks for u-boot,dm-pre-reloc property of the node to include it in the spl device tree. Not adding it in these subnodes ignores the pin muxing of peripherals which is almost always in the subnodes. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08README: remove CONFIG_CMD_DATEChris Packham
CONFIG_CMD_DATE was recently moved to Kconfig. Remove the now duplicate description of the option. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08tools: moveconfig: cleanup README entiresChris Packham
The Kconfig description replaces the description in the README file so as options are migrated they can be removed from the README. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08tools: moveconfig: cleanup whitelist entriesChris Packham
After moving to KConfig and removing from all headers options should be removed from config_whitelist.txt so the build starts complaining if someone adds them back. Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08tools: moveconfig: extract helper function for user confirmationChris Packham
Avoid repetitive code dealing with asking the user for confirmation. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08rtc: Add DM support to ds1307Chris Packham
Add an implementation of the ds1307 driver that uses the driver model i2c APIs. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08igep003x: Add netboot supportPau Pajuelo
netboot allows to boot an external image using TFTP and NFS protocols Signed-off-by: Pau Pajuelo <ppajuelo@iseebcn.com> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08igep003x: Add support for IGEP SMARC AM335xPau Pajuelo
The IGEP SMARC AM335x is an industrial processor module with following highlights: o AM3352 TI processor (Up to AM3359) o Cortex-A8 ARM CPU o SMARC form factor module o Up to 512 MB DDR3 SDRAM / 512 MB FLASH o WiFi a/b/g/n and Bluetooth v4.0 on-board o Ethernet 10/100/1000 Mbps and 10/100 Mbps controller on-board o JTAG debug connector available o Designed for industrial range purposes Signed-off-by: Pau Pajuelo <ppajuelo@iseebcn.com> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08igep003x: UBIizeLadislav Michl
Convert IGEP board to use UBI volumes for U-Boot, its environment and kernel. With exception of first four sectors read by SoC BootROM whole NAND is UBI managed. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Heiko Schocher<hs@denx.de> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08igep0033: Rename to igep003xLadislav Michl
Rename igep0033 to igep003x as IGEP SMARC AM335x module (igep0034) can use the same source files. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08mtd: nand: Consolidate nand spl loaders implementationLadislav Michl
nand_spl_load_image implementation was copied over into three different drivers and now with nand_spl_read_block used for ubispl situation gets even worse. For now use least intrusive solution and #include the same implementation to nand drivers. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08ARM: am33xx: define BOOT_DEVICE_ONENANDLadislav Michl
am33xx does not support OneNAND, but we need this define anyway to let UBI SPL code compile. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08ARM: am33xx: fix typo in spl.hLadislav Michl
Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08stm32f7: remove not needed configuration from board configVikas Manocha
This patch removes: - CONFIG_CMD_MEM: enabled by default - CONFIG_DESIGNWARE_ETH : not being used anywhere. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: add support for stm32f769 disco boardVikas Manocha
This board support stm32f7 family device stm32f769-I with 2MB internal Flash & 512KB RAM. STM32F769 lines offer the performance of the Cortex-M7 core (with double precision floating point unit) running up to 216 MHz. To compile for stm32f769 board, use same defconfig as stm32f746-disco, the only difference is to pass "DEVICE_TREE=stm32f769-disco". Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: move board specific pin muxing to dtsVikas Manocha
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: increase the max no of pin configuration to 70Vikas Manocha
The number of pins to be configured could be more than 50 e.g. in case of sdram controller, there are about 56 pins (32 data lines, 12 address & some control signals). Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: sdram: correct sdram configuration as per micron sdramVikas Manocha
Actually the sdram memory on stm32f746 discovery board is micron part MT48LC_4M32_B2B5_6A. This patch does the modification required in the device tree node & driver for the same. Also we are passing here all the timing parameters in terms of clock cycles, so no need to convert time(ns or ms) to cycles. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: enable board info read from device treeVikas Manocha
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: stm32f746-disco: read memory info from device treeVikas Manocha
Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f746: to switch on user LED1 & read user buttonVikas Manocha
All discovery boards have one user button & one user LED. Here we are just reading the button status & switching ON the user LED. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08stm32f7: use stm32f7 gpio driver supporting driver modelVikas Manocha
With this gpio driver supporting DM, there is no need to enable clocks for different gpios (for pin muxing) in the board specific code. Need to increase the allocatable area required before relocation from 0x400 to 0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08ARM: DT: stm32f7: add gpio device tree nodesVikas Manocha
Also created alias for gpios for stm32f7 discovery board. Based on these aliases, it would be possible to get gpio devices by sequence. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08dm: gpio: Add driver for stm32f7 gpio controllerVikas Manocha
This patch adds gpio driver supporting driver model for stm32f7 gpio. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Christophe KERELLO <christophe.kerello@st.com> [trini: Add depends on STM32] Signed-off-by: Tom Rini <trini@konsulko.com>