summaryrefslogtreecommitdiff
path: root/arch/arm/mach-keystone
AgeCommit message (Collapse)Author
2015-10-22ARM: k2g: Add pll dataVitaly Andrianov
Add pll data for k2g Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22ARM: k2g: Add kconfig supportLokesh Vutla
Add Kconfig support Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22ARM: k2g: Add support for CPU detectionLokesh Vutla
Adding CPU detection support for Keystone2 Galileo. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22ARM: keystone2: Use dtb images by defaultLokesh Vutla
Now that OF_CONTROL is enabled on all keystone2 platforms, build the default images with DT. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-22ARM: keystone2: Fix serial port initLokesh Vutla
With CONFIG_DM_SERIAL is enabled NS16550_init() cannot be called directly. Driver probe should be taking care of this. So call this function only when DM_SERIAL is not enabled. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-10-18ARM: k2e/l: Apply WA for selecting PA clock sourceLokesh Vutla
On keystone2 Lamarr and Edison platforms, the PA clocksource mux in PLL REG1, can be changed only after enabling its clock domain. So selecting the output of PASS PLL as input to PA only after enabling the clockdomain. This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>" and based on the previous work done by "Hao Zhang <hzhang@ti.com>" Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code") Reported-by: Vitaly Andrianov <vitalya@ti.com> Tested-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-09-11bitops: introduce BIT() definitionHeiko Schocher
introduce BIT() definition, used in at91_udc gadget driver. Signed-off-by: Heiko Schocher <hs@denx.de> [remove all other occurrences of BIT(x) definition] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
2015-08-28ARM: k2l: Fix device speedsLokesh Vutla
ARM supported speeds and init value of core_pll for SDP1200 are programmed wrong as part for the device speed cleanups. Fixing it here. Thanks to "Vitaly Andrianov <vitalya@ti.com>" for bisecting this issue Fixes: c37ed9f11b61 ("ARM: keystone2: Fix dev and arm speed detection") Tested-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-28ARM: keystone2: Build MLO by defaultLokesh Vutla
MLO(NAND/MMC boot image), is used for all the ks2 platforms. Enabling it in config.mk so that these images will be automatically built upon calling make. u-boot-spi.gph is already the build target, so not including here. Reported-by: Nishanth Menon <nm@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-28ARM: keystone2: Rename u-boot-nand.gph to MLOLokesh Vutla
NAND boot mode, ROM expects an image with a gp header in the beginning and an 8bytes filled with zeros at the end. The same is true for SD boot on K2G platforms but the file name should be MLO. Renaming u-boot-nand.gph to MLO, so that same image can be used for NAND and SD boots. And also not including all the u-boot only images under CONFIG_SPL_BUILD. Reported-by: Nishanth Menon <nm@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-28ARM: keystone2: move the custom build rules out to keystone specific makefileNishanth Menon
Keystone has build rules introduced by commit ef509b9063fb7 ("k2hk: add support for k2hk SOC and EVM") and commit 0e7f2dbac6ead ("keystone: add support for NAND gpheader image"). These are not reused by other platforms for the build, hence there is no clear benefit is maintaining them in the generic makefile as a build target. move these to the keystone specific make option Original idea of using config.mk by Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-13ARM: keystone2: Use common definition for clk_get_rateLokesh Vutla
Since all the clocks are defined common, and has the same logic to get the frequencies, use a common definition for for clk_get_rate(). Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-13ARM: keystone2: Remove unsed external clocksLokesh Vutla
Remove unused external clocks and make a common definition for all keystone platforms. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-13ARM: keystone2: Cleanup init_pll definitionLokesh Vutla
This is just a cosmetic change that makes the calling of pll init code looks much cleaner. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-13ARM: keystone2: Use common structure for PLLsLokesh Vutla
Register Base addresses are same for PLLs in all keystone platforms. If a PLL is not available, the corresponding register addresses are marked as reserved. Hence use a common definition. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-13ARM: keystone2: Fix dev and arm speed detectionLokesh Vutla
Use common devspeed and armspeed definitions. Also fix reading efuse bootrom register. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-13ARM: keystone2: Cleanup PLL init codeLokesh Vutla
There are two types of PLL for all keystone platforms: Main PLL, Secondary PLL. Instead of duplicating the same definition for each secondary PLL, have a common function which does initialization for both PLLs. And also add proper register definitions. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-13ARM: keystone2: Enable CONFIG_DISPLAY_CPUINFOLokesh Vutla
Add print_cpuinfo() function and enable CONFIG_DISPLAY_CPUINFO for keystone platforms, so that cpu info can be displayed during boot. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-13ARM: keystone2: Cleanup SoC detectionLokesh Vutla
Add proper register definition for JTAG ID and cleanup cpu_is_* functions. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-07-27keystone2: add wfi in to the core_spin loopVitaly Andrianov
When core A turning of core B, via tetris DPSC it places the core B DPSC into transitional state. The core B has to execute wfi instruction to move its DPSC to the OFF state. This patch add such instruction. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-19keystone2: use correct EFUSE_BOOTROM fileds to configure speedVitaly Andrianov
The get_max_arm_speed() and get_max_dev_speed() used wrong register fields to get the maximum speeds. This commit fixes the bug. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-05-12arch: Make board selection choices optionalJoe Hershberger
By making the board selections optional, every defconfig will include the board selection when running savedefconfig so if a new board is added to the top of the list of choices the former top's defconfig will still be correct. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Rini <trini@konsulko.com>
2015-02-21ARM: keystone: move SoC headers to mach-keystone/include/machMasahiro Yamada
Move arch/arm/include/asm/arch-keystone/* -> arch/arm/mach-keystone/include/mach/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com>
2015-02-21ARM: keystone: move SoC sources to mach-keystoneMasahiro Yamada
Move arch/arm/cpu/armv7/keystone/* -> arch/arm/mach-keystone/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com>