| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-10-29 | ARM: uniphier: enable SSC for more PLLs for LD20 SoC | Masahiro Yamada | |
| For Electro-Magnetic Compatibility. Set CPLL, SPLL2, MPLL, VPPLL, GPPLL, DPLL* to SSC rate 1 percent. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> | |||
| 2016-09-18 | ARM: uniphier: add PLL init code for LD20 SoC | Masahiro Yamada | |
| Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> | |||
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index : u-boot-fsl-qoriq | |
| Freescale u-boot tree with Scalys patches | www-data |
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