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2017-04-30power: Rename CONFIG_AS3722_POWER to CONFIG_PMIC_AS3722Simon Glass
Before converting this to Kconfig, rename it to match the other PMICs. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-30arm: Re-sync ARCH_MX5 / MX51 / MX53 CONFIG optionsTom Rini
A few boards had not been fully re-synced with CONFIG_ARCH_MX5 / CONFIG_MX51 / CONFIG_MX53 being in Kconfig. Do so now. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-27Merge tag 'xilinx-fixes-for-v2017.05' of git://www.denx.de/git/u-boot-microblazeTom Rini
Xilinx fixes for v2017.05 - Fix usbotg on Miami board - Cleanup zc1751 defconfig
2017-04-27arm/lib/bootm.c: keep ARM v7M in thumb mode during boot_jump_linux()Patrice Chotard
On ARM v7M, the processor will return to ARM mode when executing a blx instruction with bit 0 of the address == 0. Always set it to 1 to stay in thumb mode. Tested on STM32f746-disco board Similar commit: f99993c10882f7dc8ec35993d5febe59aac01e6a Author: Matt Porter <mporter@konsulko.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-04-27ARM: omap2+: rename config to ARCH_OMAP2PLUS and consolidate KconfigMasahiro Yamada
In Linux, CONFIG_ARCH_OMAP2PLUS is used for OMAP2 or later SoCs. Rename CONFIG_ARCH_OMAP2 to CONFIG_ARCH_OMAP2PLUS to follow this naming. Move the OMAP2+ board/SoC choice down to mach-omap2/Kconfig to slim down the arch/arm/Kconfig level. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-04-27Kconfig: Enable FIT support by default for TI platformsAndrew F. Davis
Almost all TI defconfigs enable this already, add this as a default and remove the explicit assignment. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-04-27arm: Warn that starting with v2018.01 gcc-6 or later is requiredTom Rini
There are more and more cases where if we do not use gcc-6.0 or later we run into problems where our binaries are too large for the targets. Given the prevalence of gcc-6.0 or later toolchains at this point in time, we give notice now that starting with v2018.01 we will require gcc-6 (or later) for ARM. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-27dm: sandbox: pwm: Add a basic pwm testSimon Glass
Unfortunately a test for the PWM uclass was not included when it was submitted. This was noticed when trying to add more functionality: http://patchwork.ozlabs.org/patch/748172/ Add a simple test to get us started. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-27OMAP3: Correct name of omap34xx_gpios when using DM_GPIOAdam Ford
The name of the gpio bank under DM_GPIO appear to be a copy-paste error. This changes the name of the gpio bank from am33xx_gpios to omap34xx_gpios. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-04-27omap3: i2c: correct registerAdam Ford
The register names and offset were not correct as per the TRM for OMAP3530 and OMAP3630. Correct the naing and offsets per the documentation Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2017-04-27zynq-topic-miami.dts: Add usbotg0 alias to make USB actually workMike Looijmans
Fixes the following problem: zynq-uboot> run dfu_ram Setting bus to 1 g_dnl_register: failed!, error: -19 The cause appears to be that the USB framework is looking for a usbotg aliases, so add the alias to point to our USB device. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-04-25Merge git://git.denx.de/u-boot-sunxiTom Rini
2017-04-25Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2017-04-25Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
2017-04-25arm: socfpga: add cyclone5 based de10-nano boardDalon Westergreen
Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-04-24arm: psci: make psci usable on single core socsYuantian Tang
PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24armv8: fsl-layerscape: Add validation of PPA image from NAND and SDSumit Garg
Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24armv8: fsl-layerscape: Support loading PPA header from eMMC/SD and NAND FlashSumit Garg
Add Kconfig option to support loading PPA header from eMMC/SD and NAND Flash. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-21sunxi: add support for Lichee Pi ZeroIcenowy Zheng
Lichee Pi Zero is a development board with a V3s SoC, which features 64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not soldered in production batch), a 40-pin RGB LCD connector and some extra pins available as 2.54mm pins or stamp holes. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-21sunxi: add DTSI file for V3sIcenowy Zheng
As we have now V3s support in board code, the V3s DTSI file should also be added. Add also some CCU include headers to satisfy the DTSI file. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-21sunxi: add basic V3s supportIcenowy Zheng
Basic U-Boot support is now present for V3s. Some memory addresses are changed specially for V3s, as the original address map cannot fit into a so small DRAM. As the DRAM controller code needs a big refactor, the SPL support is disabled in this version. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20ARM: dts: uniphier: sync Device Tree with LinuxMasahiro Yamada
- Use - instead of @ for OPP tables - Add input-delay properties to Cadence eMMC nodes - Restore full license text because code-diff is annoying - Fix NAND compatible strings Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-04-20ARM: uniphier: show STM (SCP) status on boot and pinmon commandMasahiro Yamada
The SCP (System Control Processor) or what we call STM (Stand-by MPU) is integrated in LD4, Pro4, sLD8, LD6b, LD11, and LD20. For these SoCs, show the information if STM is enabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-04-20ARM: uniphier: enable PSCI sysreset for uniphier_v8_defconfigMasahiro Yamada
This configuration is supposed to be used with ARM Trusted Firmware, so the SYSTEM_RESET is implemented in BL31. Invoke PSCI instead of U-Boot's own reset code because we need to coordinate with SCP (System Control Processor) for the system-level power management. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-04-20ARM: uniphier: setup EHCI PHY paramters for LD11Masahiro Yamada
Set the same PHY parameters as the Boot ROM uses. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-04-20sunxi: Add clock support for DE2/HDMI/TCON on newer SoCsJernej Skrabec
This is needed for HDMI, which will be added later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: video: Convert lcdc to use struct display_timingJernej Skrabec
Video driver for older Allwinner SoCs uses cfb console framework which in turn uses struct ctfb_res_modes to hold timing informations. However, DM video framework uses different structure - struct display_timing. It makes more sense to convert lcdc to use new timing structure because all new drivers should use DM video framework and older drivers might be rewritten to use new framework too. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: video: Split out TCON codeJernej Skrabec
TCON unit has similar layout and functionality also on newer SoCs. This commit splits out TCON code for easier reuse later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Add support for Bananapi M2 UltraChen-Yu Tsai
The Bananapi M2 Ultra is the first publicly available development board featuring the R40 SoC. This patch add barebone dtsi/dts files for the R40 and Bananapi M2 Ultra, as well as a defconfig for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Add PSCI support for R40Chen-Yu Tsai
The R40's CPU controls are a combination of sun6i and sun7i. All controls are in the CPUCFG block, and it seems the R40 does not have a PRCM block. The core reset, power gating and clamp controls are grouped like sun6i. Last, the R40 does not have a secure SRAM block. This patch adds a PSCI implementation for CPU bring-up and hotplug for the R40. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Fix CPUCFG address for R40Chen-Yu Tsai
The R40 has the CPUCFG block at the same address as the A20. Fix it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Use H3/A64 DRAM initialization code for R40Chen-Yu Tsai
The R40 seems to have a variant of the memory controller found in the H3 and A64 SoCs. Adapt the code for use on the R40. The changes are based on released DRAM code and comparing register dumps from boot0. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Set PLL lock enable bits for R40Chen-Yu Tsai
According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has an extra "PLL lock control" register in the CCU, which controls whether the individual PLL lock status bits in each PLL's control register work or not. This patch enables it for all the PLLs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Fix watchdog reset function for R40Chen-Yu Tsai
The watchdog found on the R40 SoC is the older variant found on the A20. Add the proper "#if defines" to make it work. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Enable AXP221s in I2C mode with the R40 SoCChen-Yu Tsai
The R40 SoC uses the AXP221s in I2C mode to supply power. Some regulator's common usages have changed, and also the recommended voltage for existing usages have changed. Update the defaults to match. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Add initial support for R40Chen-Yu Tsai
The R40 is the successor to the A20. It is a hybrid of the A20, A33 and the H3. The R40's PIO controller is compatible with the A20, Reuse the A20 UART and I2C muxing code by adding the R40's macro. The display pipeline is the newer DE 2.0 variant. Block enabling video on R40 for now. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-18Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2017-04-18Merge git://git.denx.de/u-boot-x86Tom Rini
2017-04-18rockchip: Print a message when returning to the bootromSimon Glass
At present if the return to bootrom fails (e.g. because you are not using the Rockchip's bootrom's pointer table in MMC) then the board prints SPL message and hangs. Print a message first if we can, to help in understanding what happened when it hangs. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Heiko Stuebner <heiko@sntech.de>
2017-04-18arm: omap-common: add missing va_end()xypron.glpk@gmx.de
Each call of va_start must be matched by a call of va_end. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2017-04-18sysreset: psci: support system reset in a generic way with PSCIMasahiro Yamada
If the system is running PSCI firmware, the System Reset function (func ID: 0x80000009) is supposed to be handled by PSCI, that is, the SoC/board specific reset implementation should be moved to PSCI. U-Boot should call the PSCI service according to the arm-smccc manner. The arm-smccc is supported on ARMv7 or later. Especially, ARMv8 generation SoCs are likely to run ARM Trusted Firmware BL31. In this case, U-Boot is a non-secure world boot loader, so it should not be able to reset the system directly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-04-18ARM: adjust arm-smccc code for use in U-BootMasahiro Yamada
Adjust ARM SMC Calling Convention code for U-Boot: - Replace the license block with SPDX - Change path to asm-offsets.h - Define UNWIND() as no-op - Add Kconfig entry - Add asm-offsets Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-04-18ARM: import arm-smccc code from Linux 4.11-rc6Masahiro Yamada
Imports ARM SMC Calling Convention code from Linux 4.11-rc6. The files have been copied as follows: [Linux] [U-Boot] arch/arm/kernel/smccc-call.S -> arch/arm/cpu/armv7/smccc-call.S arch/arm64/kernel/smccc-call.S -> arch/arm/cpu/armv8/smccc-call.S arch/arm/include/asm/opcodes* -> arch/arm/include/asm/opcodes* include/linux/arm-smccc.h -> include/linux/arm-smccc.h Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-04-18x86: Display the SPL banner only onceSimon Glass
At present on a cold reboot we must reset the CPU to get it to full speed. With 64-bit U-Boot this happens in SPL. At present we print the banner before doing this, the end result being that we print the banner twice. Print the banner a little later (after the CPU is ready) to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2017-04-18x86: Drop leading spaces in cpu_x86_get_desc()Simon Glass
The Intel CPU name can have leading spaces. Remove them since they are not useful. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-04-17powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ramRuchika Gupta
For E6500 cores, L2 cache has been used as init_ram. L1 cache is a write through cache on E6500.If lines are not locked in both L1 and L2 caches, crashes are observed during secure boot. This patch locks/ unlocks both L1 and L2 cache to prevent the crash. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8/fsl-layerscape: fdt: avoid incorrect fixing with CONFIG_SYS_CLK_FREQYangbo Lu
Current sysclk fixing would fix all clocks with 'fixed-clock' compatible. This patch is to fix sysclk by path to avoid any incorrect fixing. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: fsl-lsch3: Instantiate TZASC configuration in 2 groupsAshish kumar
Number of TZASC instances may vary across NXP SoCs. So put TZASC configuration under instance specific defines. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: ls2080a: Add serdes2 protocol 0x51 supportSantan Kumar
Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17arm64/ls1046a: Enable ERRATUM_A008850 for ls1046a SoCShengzhou Liu
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>