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Move this option to Kconfig and update all boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
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With driver model the number of PIO ports is defined by platform data, so
remove it from the header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Remove driver model CONFIGs from the board config headers and use Kconfig
instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Remove driver model CONFIGs from the board config headers and use Kconfig
instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Remove driver model CONFIGs from the board config headers and use Kconfig
instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Remove driver model CONFIGs from the board config headers and use Kconfig
instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Remove driver model CONFIGs from the board config headers and use Kconfig
instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Remove driver model CONFIGs from the board config header and use Kconfig
instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
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These additional nodes need to be provided to get U-Boot to boot correctly
on the Canyonlands / Glacier board:
- chosen path to the console-uart
- reg-shift set to 0 in the uart device nodes
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
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This permits us to use linux/linkage.h on PowerPC machines.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This comes from the device tree or a call to get_uart_clock().
Signed-off-by: Simon Glass <sjg@chromium.org>
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Define an _end symbol indicating the end of u-boot.bin. Also add some dummy
words into the link script to ensure that u-boot.bin will always extend
that far. There may be a better way of doing this.
Signed-off-by: Simon Glass <sjg@chromium.org>
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This is required at present for device tree control. The ppc4xx does support
GPIOs but does not seem to have a proper driver. So this file is empty.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Call this function to set up our early memory.
Signed-off-by: Simon Glass <sjg@chromium.org>
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The canyonlands.h config file works with canyonlands, glacier and arches
boards. Bring in the device tree files for these from Linux 3.17.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Switch to generic board so that this board will not be broken/removed.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add a new ramboot config for glacier so that it is possible to test U-Boot
loaded over Ethernet instead of using JTAG.
Signed-off-by: Simon Glass <sjg@chromium.org>
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Many CONFIG options have an unnecessary value of 1. CONFIG_440 is set in
the various board config files. Also simplify the CONFIG_440 check in
config.mk
Signed-off-by: Simon Glass <sjg@chromium.org>
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Enable this in the Kconfig so that PowerPC boards can use device tree to
configure U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
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When booting in JTAG mode, there is no way to use soft break-points, and
no way of knowing when SPL has finished executing (so the user can issue
a 'halt' command to load u-boot.bin for example)
Add a debug output and simple loop to stop execution at the completion of
the SPL initialisation as a pseudo break-point when booting in JTAG mode
Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
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Section 4.1.2 of Freescale Application Note AN4199 describes the
configuration required to operate the mx28 from a 5V source without a
battery.
This patch changes the behaviour of the dropout control of the DC-DC
converter (refer to section 11.12.9 of the mx28 Application Processor
Reference Manual - Document Number: MCIMX28RM, Rev 2, 08/2013) to the
following:
- Always use 4P2 Linear Regulator if CONFIG_SYS_MXS_VDD5V_ONLY is defined
- Switch between 4P2 Linear Regulator and Battery, using whichever has
the highest voltage if CONFIG_SYS_MXS_VDD5V_ONLY isnot set (this is
the same as the pre-patch behaviour)
Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
Signed-off-by: Damien Gotfroi <dgotfroi@greenwatch.be>
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It is difficult to track down fail to boot issues in the mxs SPL.
Implement the following to make it easier:
- Add debug outputs to allow tracing of SPL progress in order to track
where failure to boot occurs. DEUBUG and CONFIG_SPL_SERIAL_SUPPORT must
be defined to enable debug output in SPL
- Add TODO comments where it is not clear if the code is doing what it
is meant to be doing, even tough the board boots properly (these comments
refer to existing code, not to any code added by this patch)
Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
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Should use AIPS3 configuration address 0x0227C000 to set AIPS3,
not the AIPS3 base address.
Additional, replace AIPS1_BASE_ADDR to AIPS3_ARB_BASE_ADDR to align with
AIPS1 and AIPS2, and resolve the AIPS3_ARB_BASE_ADDR undefine problem.
Signed-off-by: Ye.Li <B37916@freescale.com>
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Update fuse_bank0_regs structure according reference mannual.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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This is required for driver model.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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This patch has some parts connected together:
- Use _gd in bss section which is automatically cleared
Location at SPL_MALLOC_END wasn't cleared at all
- Use MALLOC_F_LEN(early alloc) instead of FULL MALLOC
(mem_malloc_init is not called at all)
- Simplify malloc and stack init.
At the end of SPL addr is malloc area and below is stack
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Create space for dm_init where calloc is called
and malloc_base has to be initialized.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Because it is not compatible with DM where
malloc_base has to be available early and init
has to be done in ASM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Remove one instruction in the loop which speedup
code copying.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Compile code with -fPIC to get GOT. Do not build SPL
with fPIC because it increasing SPL size for nothing.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Setup gd from ASM to be availalbe for board_init_r.
Setting it up in spl_board_init is too late when
MALLOC is used.
Space for gd is located behind MALLOC area at the end of BRAM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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It is not used at all that's why remove it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Do not use microblaze specific interrupt init function.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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DTB is added to rodata section:
[ 2] .rodata PROGBITS 84c5b60c 05c60c 00c618 00 A
0 0 4
[ 3] .dtb.init.rodata PROGBITS 84c67c30 068c30 003c80 00 A
0 0 16
[ 4] .rela.dyn RELA 84c6b8b0 06c8b0 000534 0c A
0 0 4
[ 5] .data PROGBITS 84c6bde4 06cde4 001536 00 WA
0 0 16
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Add one more debug message about enabling global interrupts.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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No functional changes just to pass checkpatch.pl.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Do not use specific macros for debugging.
Also remove compilation warning:
w+../arch/microblaze/cpu/interrupts.c: In function 'interrupt_handler':
w+../arch/microblaze/cpu/interrupts.c:153:2: warning: format '%x'
expects argument of type 'unsigned int', but argument 2 has type 'void
(*)(void *)' [-Wformat]
w+../arch/microblaze/cpu/interrupts.c:153:2: warning: format '%x'
expects argument of type 'unsigned int', but argument 4 has type 'void
*' [-Wformat]
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Just coding style cleanup - no functional changes.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Show also return address from exception which should
suggest where the problem is.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Do not save registers below r1 stack pointer because
it is not checked by stack undeflow is not able to detect
it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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This way we may have very limited set of functions implemented so we
save some space.
Also it allows us to build U-Boot for any ARC core with the same one
toolchain because we don't rely on pre-built libgcc.
For example:
* we may use little-endian toolchain but build U-Boot for ether
endianess
* we may use non-multilibbed uClibc toolchain but build U-Boot for
whatever ARC CPU flavour that current GCC supports
Private libgcc built from generic C implementation contributes only 144
bytes to .text section so we don't see significant degradation of size:
--->8---
$ arc-linux-size u-boot.libgcc-prebuilt
text data bss dec hex filename
222217 24912 214820 461949 70c7d u-boot.libgcc-prebuilt
$ arc-linux-size u-boot.libgcc-private
text data bss dec hex filename
222361 24912 214820 462093 70d0d u-boot.libgcc-private
--->8---
Also I don't notice visible performance degradation compared to
pre-built libgcc (where at least "*div*" functions are had-written in
assembly) on typical operations of downloading 10Mb uImage over TFTP and
bootm.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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As a preparation to ARCv2 port submission we're moving CPU slection
flags to a common location.
Also it will allow us to have more flexible CPU specification, not only
ISA version but CPU family as well checking CONFIG_ARC_CPU_xxx.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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Common arch_early_init_r() is used in "arc/lib/cpu.c" for all ARC boards
so there's no sense in separate per-board definitions.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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There're no other options for ARC except "generic board" so ther's no
point to define CONFIG_SYS_GENERIC_BOARD per board.
We now have it set fo all ARC boards.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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