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path: root/board/freescale/mx53ard/imximage_dd3.cfg
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2013-07-24Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-05-10Fix references to the documentation filesAnatolij Gustschin
Many boot image configuration files refer to the appropriate documentation file, but these references contain typos in the directory and file name. Fix them. Also fix reference to doc/README.SPL file. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2013-01-22imximage.cfg: run files through C preprocessorTroy Kisky
The '#' used as comments in the files cause the preprocessor trouble, so change to /* */. The mkimage command which uses this preprocessor output was moved to arch/arm/imx-common/Makefile .gitignore was updated to ignore .cfgtmp files. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
2012-04-16MX53: DDR: Fix ZQHWCTRL field TZQ_CSTroy Kisky
Currently, board files are setting this field to 0x01 which the manual says is a reserved value. Change to use the default of 0x02 - 128 cycles. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-09-04mx53: ddr3: Update DD3 initializationFabio Estevam
Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011: -change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz) -change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from "0x092080b0". This changes write recovery from 8 clocks to 6 clocks (in line with ESDCFG1[tWR]) Signed-off-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-07-04MX53: Add initial support for MX53ARDFabio Estevam
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>