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2016-06-19Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
2016-06-19Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini
2016-06-18imx: mx6ulevk: change QSPI PAD DSE to 120ohmPeng Fan
The current pad DSE for QSPI is 60ohm. This setting cause too strong drive to clock and data signals. Need to change the DSE to 120ohm for better signal quality. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-06-18imx6ulevk: fix LCD_nPWREN settingPeng Fan
Q901 is PMOS, LCD_nPWREN should be at low voltage then output is 3V3. If LCD_nPWREN is high, output is 2.4V which is not correct. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-06-18imx6ulevk: fix 74LV OE usagePeng Fan
Fix 74LV OE gpio index. gpio index is wrong, so gpio output will not have effect, since we use wrong GPIO5_IO18, but not correct GPIO5_IO8. And at the end of the initialization of 74lv init, should keep OE voltage level at LOW to make 74lv output the correct voltage. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-06-18mx7dsabresd: Fix LCD_PWR_EN output settingYe Li
LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3 is actually 1.2V. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-06-18mx6sabresd: Allow LVDS backlight to be functional after a kernel rebootMarco Franchi
Currently the LVDS backlight does not work in U-Boot after a “reboot” comand in the kernel. This problem occurs because the kernel uses this pin in PWM mode and U-Boot does not configure the backlight pin as GPIO functionality. So fix the problem by explicitly configuring the backlight pin as GPIO in U-Boot. Signed-off-by: Marco Franchi <marco.franchi@nxp.com> Acked-by: Stefano Babic <sbabic@denx.de> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-06-18Merge branch 'master' of git://git.denx.de/u-bootStefano Babic
Signed-off-by: Stefano Babic <sbabic@denx.de>
2016-06-13usb: xhci: fsl: Add workaround for USB erratum A008751Sriram Dash
This patch is doing the following: 1. Implementing the errata for LS2080. 2. Adding fixup for fdt for LS2080. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2016-06-13armv8: s32v234: Introduce basic support for s32v234evbEddy Petrișor
Add initial support for NXP's S32V234 SoC and S32V234EVB board. The S32V230 family is designed to support computation-intensive applications for image processing. The S32V234, as part of the S32V230 family, is a high-performance automotive processor designed to support safe computation-intensive applications in the area of vision and sensor fusion. Code originally writen by: Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com> Original-signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com> Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com> Signed-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>
2016-06-12Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini
2016-06-10armv8: ls2080aqds: Enable QSPI boot supportYuan Yao
This patch adds QSPI boot support for LS2080AQDS board. The QSPI boot image need to be programmed into the QSPI flash first. Then we can switch to booting from QSPI memory space. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND bootYuan Yao
Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10armv8: ls2080aqds: disable IFC NOR & QIXIS when QSPI enableYuan Yao
When QSPI is enabled, NOR flash and QIXIS can't be accessed through IFC due to pin mux. Enable I2C QIXIS access and I2C early init to read the sysclk and ddrclk. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10armv8: ls2080aqds: Select QSPI CLK div via SCFGYuan Yao
QSPI module output SCLK divisor value is configured through SCFG. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10board: ls2080a: Add "mcinitcmd" env for MC & DPL deploymentPratiyush Mohan Srivastava
Environment variable mcinitcmd is defined to initiate MC and DPL deployment from the location where it is stored (NOR, NAND, SD, SATA, USB) during booting. If this variable is not defined then macro MC_BOOT_ENV_VAR will be null and MC will not be booted and DPL will not be applied during U-boot booting. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-04Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini
2016-06-04Merge git://git.denx.de/u-boot-nand-flashTom Rini
2016-06-04freescale: Tweak various Makefiles to remove redundancy, fix aestheticsRobert P. J. Day
No intended functional change, just remove redundancies in some Makefiles, and make whitespace aesthetics uniform. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-04board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl bootShengzhou Liu
We should use unified setup_ddr_tlbs() for spl boot and non-spl boot to make sure 'M' bit is set for DDR TLB to maintain cache coherence. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-04powerpc/board: SPL: Enable malloc flag in global data.Sumit Garg
For malloc to work in SPL framework enable GD_FLG_FULL_MALLOC_INIT flag in global data after allocating memory using mem_malloc_init. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-04mtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_dataScott Wood
These functions are part of the Linux 4.6 sync. They are being added before the main sync patch in order to make it easier to address the issue across all NAND drivers (many/most of which do not closely track their Linux counterparts) separately from other merge issues. Signed-off-by: Scott Wood <oss@buserror.net>
2016-06-03armv8: ls1012a: Add support of ls1012afrdm boardPrabhakar Kushwaha
QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development platform, with a complete debugging environment. The LS1012AFRDM board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03armv8: ls1012a: Add support of ls1012ardb boardPrabhakar Kushwaha
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03armv8: ls1012a: Add support of ls1012aqds boardPrabhakar Kushwaha
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance development platform, with a complete debugging environment. The LS1012AQDS board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03board: freescale: common: Add flag for LBMAP brdcfg reg offsetAbhimanyu Saini
Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP configuration register instead of hardcoding it in set_lbmap() function. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03board: freescale: common: Conditionally compile IFC QXIS funcAbhimanyu Saini
Check if qixis supports memory-mapped read/write before compiling IFC based qixis read/write functions. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03armv8: fsl-layerscape: Organize SoC overview at common locationPrabhakar Kushwaha
SoC overviews are getting repeated across board folders. So, Organize SoC overview at common location i.e. fsl-layerscape/doc Also move README.lsch2 and README.lsch3 in same folder. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03armv8: ls1043aqds: fix usb PWRFAULT settingShaohui Xie
SCFG_USBPWRFAULT_DEDICATED instead of SCFG_USBPWRFAULT_SHARED should be used for USB 3 & 2. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03board: ls2080ardb: qds: Fix compiling issue when FSL_MC_ENET not definedYork Sun
U-Boot should continue to work without management complex (MC). Fix compiling errors and warnings. Signed-off-by: York Sun <york.sun@nxp.com>
2016-06-03board: ls102xa: Fix ICID setupVincent Siles
LS102A ref manual dictates that ICID have to be written to the MSB of the ICID register, not to the LSB. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
2016-06-03board/freescale: Update ddr clk_adjustShengzhou Liu
This patch updates clk_adjust to actual value for boards with T-series and LS-series SoCs to match the setting of clk_adjust in latest ddr driver. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-31cosmetic: mx6slevk: Minor coding-style fixSebastien Bourdelin
Fix the brace indentation in board_mmc_init(). Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
2016-05-31imx: mx6qsabreauto: drop duplicated net phy configurationPeng Fan
In 'commit d584c68ce0f5bf2f430ccfb2ba00bd506206fb91', ar8031 is changed to use ar8035_config. ar8035_config actually does the same thing as mx6_rgmii_rework, so drop mx6_rgmii_rework and board_phy_config. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Stefano Babic <sbabic@denx.de>
2016-05-27Delete tests of CONFIG_OF_LIBFDT when testing CONFIG_OF_BOARD_SETUPRobert P. J. Day
Since CONFIG_OF_BOARD_SETUP depends on CONFIG_OF_LIBFDT: config OF_BOARD_SETUP bool "Set up board-specific details in device tree before boot" depends on OF_LIBFDT ... remove superfluous tests of CONFIG_OF_LIBFDT when testing for CONFIG_OF_BOARD_SETUP. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> [trini: Typo fix: s/ifdefi/ifdef/] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-05-25Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini
2016-05-25powerpc:t4240rdb: Disable the non-existent ethernet ports on T4240RDBYing Zhang
Disable the non-existent ethernet ports on T4240RDB:FM1_DTSEC5, FM1_DTSEC6, FM2_DTSEC5 and FM2_DTSEC6. Signed-off-by: Ying Zhang <ying.zhang22455@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-24board: mx6sabresd/auto: use simpler runtime cpu dection macrosPeng Fan
Use simpler runtime cpu dection macros. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2016-05-19powerpc/t208xrdb: Update MAINTAINERS fileYork Sun
Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2016-05-19powerpc/t208xqds: Update MAINTAINERS fileYork Sun
Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2016-05-18armv8: ls1043ardb: invert irq pin polarity for AQR105 PHYShaohui Xie
To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity by setting relative bit in SCFG_INTPCR register, because AQR105 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18arch/arm, arch/powerpc: add # of SEC engines on the SOCAlex Porosanu
Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18armv8: ls1043ardb: fix types of variablesQianyu Gong
Using u16 for cfg_rcw_src and u8 for sd1refclk_sel is enough. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18armv8: ls1043a: remove redundant code in board filesQianyu Gong
gd->env_addr will be initialized in env_init() in common/env_nowhere.c if CONFIG_ENV_IS_NOWHERE is defined. So no need to do it again. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18armv8/ls1043ardb: fix the limitation of using 'cpld reset'Qianyu Gong
The current 'cpld reset' will just write global_rst register but couldn't switch to NOR boot if the board's switches are for NAND/SD boot. So need to write rcw source registers for NOR boot as well. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18arm: uniform usage of u32 in ls102x caam configVincent Siles
Mix usage of uint32_t and u32 fixed in favor of u32. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18arm: Fix SCFG ICID reg addressesVincent Siles
On the LS102x boards, in order to initialize the ICID values of masters, the dev_stream_id array holds absolute offsets from the base of SCFG. In ls102xa_config_ssmu_stream_id, the base pointer is cast to uint32_t * before adding the offset, leading to an invalid address. Casting it to void * solves the issue. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-17armv8: ls2080a: Update MAINTAINERS filePrabhakar Kushwaha
Update MAINTAINERS file for ls2080aqds and ls2080ardb platforms. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-17armv8/ls2080ardb: Update DDR timing to support more UDIMMsShengzhou Liu
Optimize DDR timing for good margins to support new Transcend and Apacer DDR4 UDIMM besides current Micron UDIMM. Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with following UDIMM on LS2080ARDB. - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z - Apacer UDIMM: 78.C1GM4.AF10B - Transcend UDIMM: TS1GLH72V1H Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-17armv8/ls1043: Add workaround for DDR erratum A-008850Shengzhou Liu
Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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