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2017-05-04sunxi: add support for Banana Pi M2 Plus boardIcenowy Zheng
Banana Pi M2 Plus is an Allwinner H3-based SBC by Sinovoip, which has already mainline device tree file that have landed into U-Boot source tree. Add a defconfig file for it and add the MAINTAINERS items. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-02ARM: sunxi: move board/sunxi/Kconfig to arch/arm/mach-sunxi/KconfigMasahiro Yamada
For the consistent location of SoC-level Kconfig. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-28sunxi: video: Add A64/H3/H5 HDMI driverJernej Skrabec
This commit adds support for HDMI output. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-28sunxi: Enable DM_I2C for A64/H3/H5Jernej Skrabec
This commits enable DM I2C support for A64/H3/H5 SoCs. It is not enabled globaly for all sunxi SoCs, because some boards use PMICs which are connected through I2C. In order to keep same functionality, PMIC drivers needs to be ported to DM too. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-28sunxi: i2c: Add support for DM I2CJernej Skrabec
This commit adds support for DM I2C on sunxi platform. It can coexist with old style sunxi I2C driver, because it is still used in SPL and by some SoCs. Because sunxi platform doesn't yet support DM clk, reset and pinctrl driver, workaround is needed to enable clocks and set resets and pinctrls. This is done by calling i2c_init_board() in board_init(). This means that CONFIG_I2Cx_ENABLE options needs to be correctly set in order to use needed I2C controller. Commit is based on the previous patch made by Philipp Tomsich Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-28sunxi: Move function for later convenienceJernej Skrabec
This commit only moves i2c_init_board() function almost to the top and doesn't have any functional changes. This is needed for a temporary workaround in next commit when support for DM I2C will be introduced. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-21sunxi: add support for Lichee Pi ZeroIcenowy Zheng
Lichee Pi Zero is a development board with a V3s SoC, which features 64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not soldered in production batch), a 40-pin RGB LCD connector and some extra pins available as 2.54mm pins or stamp holes. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-21sunxi: add basic V3s supportIcenowy Zheng
Basic U-Boot support is now present for V3s. Some memory addresses are changed specially for V3s, as the original address map cannot fit into a so small DRAM. As the DRAM controller code needs a big refactor, the SPL support is disabled in this version. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Add clock support for DE2/HDMI/TCON on newer SoCsJernej Skrabec
This is needed for HDMI, which will be added later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Add support for Bananapi M2 UltraChen-Yu Tsai
The Bananapi M2 Ultra is the first publicly available development board featuring the R40 SoC. This patch add barebone dtsi/dts files for the R40 and Bananapi M2 Ultra, as well as a defconfig for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Add PSCI support for R40Chen-Yu Tsai
The R40's CPU controls are a combination of sun6i and sun7i. All controls are in the CPUCFG block, and it seems the R40 does not have a PRCM block. The core reset, power gating and clamp controls are grouped like sun6i. Last, the R40 does not have a secure SRAM block. This patch adds a PSCI implementation for CPU bring-up and hotplug for the R40. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Enable SPL for R40Chen-Yu Tsai
Now that we can do DRAM initialization for the R40, we can enable SPL support for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Provide defaults for R40 DRAM settingsChen-Yu Tsai
These values were taken from the Banana Pi M2 Ultra fex file found in the released vendor BSP. This is the only publicly available R40 device at the time of this writing. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Add mmc[1-3] pinmux settings for R40Chen-Yu Tsai
The PIO is generally compatible with the A20, except that it routes the full 8 bits and eMMC reset pins for mmc2. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Enable AXP221s in I2C mode with the R40 SoCChen-Yu Tsai
The R40 SoC uses the AXP221s in I2C mode to supply power. Some regulator's common usages have changed, and also the recommended voltage for existing usages have changed. Update the defaults to match. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Add initial support for R40Chen-Yu Tsai
The R40 is the successor to the A20. It is a hybrid of the A20, A33 and the H3. The R40's PIO controller is compatible with the A20, Reuse the A20 UART and I2C muxing code by adding the R40's macro. The display pipeline is the newer DE 2.0 variant. Block enabling video on R40 for now. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Split up long Kconfig linesChen-Yu Tsai
Currently we have some lines in board/sunxi/Kconfig that are very long. These line either provide default values for a set of SoCs, or limit some option to a subset of sunxi SoCs. Fortunately Kconfig makes it easy to split them. The Kconfig language document states If multiple dependencies are defined, they are connected with '&&'. This means we can split existing dependencies at "&&" symbols. This applies to both the "depends on" lines and "if" expressions. This patch splits them up to one symbol per line. This will make it easier to add, remove, or modify one item at a time. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Convert CONFIG_MACPWR to KconfigMylène Josserand
Convert the CONFIG_MACPWR to Kconfig and update all the sunxi defconfigs that used it in SYS_EXTRA_OPTIONS. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20sunxi: Convert CONFIG_SATAPWR to KconfigMylène Josserand
Convert the CONFIG_SATAPWR into kconfig. Thanks to that, many SYS_EXTRA_OPTIONS can be removed from some defconfigs. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-18sunxi: Add maintainer of the NanoPi NEO AirJelle van der Waa
Add myself as maintainer of the NanoPi NEO Air board. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-08Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
2017-04-08spl: Kconfig: SPL_MMC_SUPPORT depends on GENERIC_MMCAlexandru Gagniuc
spl_mmc.c calls mmc_initialize(). This symbol is provided in drivers/mmc/mmc.c when CONFIG_GENERIC_MMC is enabled. The sunxi Kconfig case is an oddball because it redefines SPL_MMC_SUPPORT. Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> [trini: Update arch/arm/cpu/armv8/zynqmp/Kconfig] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-07arm: sunxi: Add Sunchip CX-A99 initial supportRask Ingemann Lambertsen
The Sunchip CX-A99 is a board used in some media players. It features: An Allwinner A80 ARM SoC (4 * Cortex-A7 + 4 * Cortex-A15 cores) 2 GiB or 4 GiB DDR3 DRAM AXP808 PMIC 16 GB or 32 GB eMMC SDIO Wifi/Bluetooth/FM module SD card slot 1 USB 3.0 connector 2 USB 2.0 connectors SATA connector UART connector (internally) for serial console Ethernet connector (10/100/1000 Mbit/s) HDMI connector Composite video and analog audio connector S/PDIF connector IR remote control receiver This patch adds a defconfig for the board. The DRAM settings are as found in the vendor sys_config.fex file. It has a preliminary device tree for use until a device tree is accepted upstream, after which it can be replaced by the upstream version. Signed-off-by: Rask Ingemann Lambertsen <rask@formelder.dk> [squash commits, and edited new meanful commit message] Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-07scripts: sunxi: Build an raw SPL imageMaxime Ripard
Introduce a new sunxi-spl-with-ecc.bin image with already the right header, ECC, randomizer and padding for the BROM to be able to read it. It needs to be flashed using a raw access to the NAND so that the controller doesn't change a thing to it, since we already have all the right parameters. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2017-04-05sunxi: Add OrangePi PC 2 initial supportAndre Przywara
The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC. Add a (64-bit only) defconfig defining the required options to build the U-Boot proper. Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi and changing the differing components accordingly. This is a preliminary device tree mostly for U-Boot's own sake, it is expected to be updated once the official DT gets accepted upstream. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [squash the commits, update the commit message] Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-05sunxi: introduce Allwinner H5 config optionAndre Przywara
The Allwinner H5 Soc is bascially an H3 with high SRAM and ARMv8 cores. As the peripherals and the pinmuxing are almost identical, we piggy back on the shared MACH_SUN8I_H3_H5 config symbol. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-05sunxi: prepare for sharing MACH_SUN8I_H3 config symbolAndre Przywara
The Allwinner H5 is very close to the H3 SoC, but has ARMv8 cores. To allow sharing the clocks, GPIO and driver code easily, create an architecture agnostic MACH_SUNXI_H3_H5 Kconfig symbol. Rename the existing symbol to MACH_SUNXI_H3_H5 where code is shared and let it be selected by a new shared Kconfig option. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-05sunxi: Kconfig: introduce CONFIG_SUNXI_HIGH_SRAMAndre Przywara
Traditionally Allwinner SoCs have their boot ROM mapped just below 4GB, while the first SRAM region is mapped at address 0. With the extended physical memory support of the A80 this was changed, so the BROM is now at address 0 and the SRAM region starts right behind this at 64KB. This configuration seems to be called "high SRAM". Instead of enumerating the SoCs which have copied this configuration, let's call a spade a spade and introduce a Kconfig option for this setup. SoCs implementing this (A80, A64 and H5, so far), can then select this configuration. Simplify the config header definition on the way. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-04-05sunxi: simplify ACTLR.SMP bit set #ifdefAndre Przywara
Instead of enumerating all SoC families that need that bit set, let's just express this more clearly: The SMP bits needs to be set on SMP capable ARMv7 CPUs. It's much easier in Kconfig to express it the other way round, so we use ! CPU_IS_UP and ! ARM64. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-05ARM: rename CONFIG_TIMER_CLK_FREQ to COUNTER_FREQUENCYAndre Przywara
Many ARMv8 boards define a constant COUNTER_FREQUENCY to specify the frequency of the ARM Generic Timer (aka. arch timer). ARMv7 boards traditionally used CONFIG_TIMER_CLK_FREQ for the same purpose. It seems useful to unify them. Since there are less occurences of the latter version, lets convert all users over to COUNTER_FREQUENCY. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-15sunxi: add orangepi zero defconfigIcenowy Zheng
Orange Pi Zero is a board designed by Xunlong. It has an Allwinner H2+ SoC (similar to H3, which shares the same SoC ID), 256MB/512MB RAM, Allwinner XR819 SDIO Wi-Fi, a MicroUSB port which is used to power the board (also capable of OTG), a USB Type-A socket and a MicroSD slot. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-11ARM: sunxi: remove bare default for CONFIG_MMCMasahiro Yamada
The bare default entry is wrong. Just remove it since the (real) entry in drivers/mmc/Kconfig has "default ARM || PPC || SANDBOX". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
2017-01-04sunxi: A64: enable SPLAndre Przywara
Now that the SPL is ready to be compiled in AArch64 and the DRAM init code is ready, enable SPL support for the A64 SoC and in the Pine64 defconfig. For now we keep the boot0 header in the U-Boot proper, as this allows to still use boot0 as an SPL replacement without hurting the SPL use case. We disable FEL support for now by making its compilation conditional and disabling it for ARM64, as the code isn't ready yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04sunxi: provide default DRAM config for sun50i in KconfigAndre Przywara
To avoid enumerating the very same DRAM values in defconfig files for each and every Allwinner A64 board out there, let's put some sane default values in the Kconfig file. Boards with different needs can override them at any time. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04sunxi: A64: do an RMR switch if started in AArch32 modeAndre Przywara
The Allwinner A64 SoC starts execution in AArch32 mode, and both the boot ROM and Allwinner's boot0 keep running in this mode. So U-Boot gets entered in 32-bit, although we want it to run in AArch64. By using a "magic" instruction, which happens to be an almost-NOP in AArch64 and a branch in AArch32, we differentiate between being entered in 64-bit or 32-bit mode. If in 64-bit mode, we proceed with the branch to reset, but in 32-bit mode we trigger an RMR write to bring the core into AArch64/EL3 and re-enter U-Boot at CONFIG_SYS_TEXT_BASE. This allows a 64-bit U-Boot to be both entered in 32 and 64-bit mode, so we can use the same start code for the SPL and the U-Boot proper. We use the existing custom header (boot0.h) functionality, but restrict the existing boot0 header reservation to the non-SPL build now. A SPL wouldn't need such header anyway. This allows to have both options defined and lets us use one for the SPL and the other for U-Boot proper. Also add arch/arm/mach-sunxi/rmr_switch.S, which contains the original ARM assembly code and instructions how to re-generate the encoded version. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04sunxi: introduce extra config option for boot0 headerAndre Przywara
The ENABLE_ARM_SOC_BOOT0_HOOK option is a generic option shared with other boards. To allow alternative code to be inserted, we create another, now function specific config symbol on top of it to simplify later additions. No functional change at this time. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-11-28sunxi: add support for Nintendo NES Classic EditionFUKAUMI Naoki
Add board support for sun8i_r16 Nintendo NES Classic edition. Signed-off-by: FUKAUMI Naoki <naobsd@gmail.com> [jagan: Add commit message body] Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-10-30sunxi: Add support for Cubieboard4Chen-Yu Tsai
The Cubieboard4 is an A80 SoC based development board from Cubietech. This board has a UART port, 4 USB host ports, a USB 3.0 OTG connector, HDMI and VGA outputs, a micro SD slot, 8G eMMC flash, 2G DRAM, a WiFi/BT combo chip, headphone and microphone jacks, IR receiver, and GPIO headers. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-10-30sunxi: Enable SPL support for A80 Optimus boardChen-Yu Tsai
The A80 Optimus Board was launched with the Allwinner A80 SoC. It was jointly developed by Allwinner and Merrii. This board has a UART port, a JTAG connector, 2 USB host ports, a USB 3.0 OTG connector, an HDMI output, a micro SD slot, 16G eMMC flash, 2G DRAM, a camera sensor interface, a WiFi/BT combo chip, a headphone jack, IR receiver, and additional GPIO headers. Signed-off-by: Chen-Yu Tsai <wens@csie.org> [hdegoede@redhat.com: update existing Merrii_A80_Optimus_defconfig instead of adding a new defconfig] Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-10-30sunxi: Add default zq value for sun9i (A80)Chen-Yu Tsai
Both the A80 Optimus board and the Cubieboard 4 use a zq value of 4145117, or 0x3f3fdd. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-10-30sunxi: Set default CPU clock rate to 1008 MHz for sun9i (A80)Chen-Yu Tsai
In Allwinner's SDK the A80 is clocked to 1008 MHz by default. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-10-30sunxi: add MMC pinmux setup for SDC2 on sun9iPhilipp Tomsich
The A80 can support 8-bit eMMC with reset on the PC pingroups. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-10-30sunxi: enable SPL for sun9iPhilipp Tomsich
Now that DRAM initialization and clock setup is supported, we can enable SPL for the A80. [wens@csie.org: Added commit message] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-10-30sunxi: DRAM initialisation for sun9iPhilipp Tomsich
This adds DRAM initialisation code for sun9i, which calculates the appropriate timings based on timing information for the supplied DDR3 bin and the clock speeds used. With this DRAM setup, we have verified DDR3 clocks of up to 792MHz (i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration. [wens@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> [hdegoede@redhat.com: Drop some huge non-documenting #if 0 ... #endif blocks] [hdegoede@redhat.com: Fix checkpatch warnings] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-10-23Convert CONSOLE_PRE_CONSOLE_BUFFER options to KconfigSimon Glass
Move these option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-09-20Kconfig: Move config IDENT_STRING to KconfigSiva Durga Prasad Paladugu
Move the config IDENT_STRING to Kconfig and migrate all boards [sivadur: Migrate zynq boards] Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> [trini: Update configs, add some default to sunxi Kconfig] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-18Merge branch 'master' of git://www.denx.de/git/u-boot-sunxiTom Rini
2016-09-18sunxi: Add defconfig and dts for the NanoPi NEOJelle van der Waa
The NanoPi NEO is a simple h3 board with 512MB RAM, ethernet, one usb and one usb OTG connector. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-16Convert CONFIG_SPL_SERIAL_SUPPORT to KconfigSimon Glass
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16Convert CONFIG_SPL_POWER_SUPPORT to KconfigSimon Glass
Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>