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2016-05-20mips: ath79: add AP143 reference boardWills Wang
This patch add board-level code and base DT for AP143. Signed-off-by: Wills Wang <wills.wang@live.com> [updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-20mips: ath79: add AP121 reference boardWills Wang
This patch add board-level code and base DT for AP121. Signed-off-by: Wills Wang <wills.wang@live.com> [updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-20compulab: add support for layout aware eeprom commandsNikita Kiryanov
Add layout definitions and implement functions for field printing/updating, layout detection, layout assignment, and layout parsing. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2016-05-19powerpc/t208xrdb: Update MAINTAINERS fileYork Sun
Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2016-05-19powerpc/t208xqds: Update MAINTAINERS fileYork Sun
Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2016-05-18armv8: ls1043ardb: invert irq pin polarity for AQR105 PHYShaohui Xie
To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity by setting relative bit in SCFG_INTPCR register, because AQR105 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18arch/arm, arch/powerpc: add # of SEC engines on the SOCAlex Porosanu
Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18armv8: ls1043ardb: fix types of variablesQianyu Gong
Using u16 for cfg_rcw_src and u8 for sd1refclk_sel is enough. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18armv8: ls1043a: remove redundant code in board filesQianyu Gong
gd->env_addr will be initialized in env_init() in common/env_nowhere.c if CONFIG_ENV_IS_NOWHERE is defined. So no need to do it again. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18armv8/ls1043ardb: fix the limitation of using 'cpld reset'Qianyu Gong
The current 'cpld reset' will just write global_rst register but couldn't switch to NOR boot if the board's switches are for NAND/SD boot. So need to write rcw source registers for NOR boot as well. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18arm: uniform usage of u32 in ls102x caam configVincent Siles
Mix usage of uint32_t and u32 fixed in favor of u32. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-18arm: Fix SCFG ICID reg addressesVincent Siles
On the LS102x boards, in order to initialize the ICID values of masters, the dev_stream_id array holds absolute offsets from the base of SCFG. In ls102xa_config_ssmu_stream_id, the base pointer is cast to uint32_t * before adding the offset, leading to an invalid address. Casting it to void * solves the issue. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-17Merge git://git.denx.de/u-boot-dmTom Rini
2016-05-17armv8: ls2080a: Update MAINTAINERS filePrabhakar Kushwaha
Update MAINTAINERS file for ls2080aqds and ls2080ardb platforms. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-17armv8/ls2080ardb: Update DDR timing to support more UDIMMsShengzhou Liu
Optimize DDR timing for good margins to support new Transcend and Apacer DDR4 UDIMM besides current Micron UDIMM. Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with following UDIMM on LS2080ARDB. - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z - Apacer UDIMM: 78.C1GM4.AF10B - Transcend UDIMM: TS1GLH72V1H Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-17armv8/ls1043: Add workaround for DDR erratum A-008850Shengzhou Liu
Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-05-17dm: usb: Drop the get_dev() functionSimon Glass
This function is implemented by the legacy block functions now. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-05-17dm: scsi: Rename CONFIG_CMD_SCSI to CONFIG_SCSISimon Glass
This option currently enables both the command and the SCSI functionality. Rename the existing option to CONFIG_SCSI since most of the code relates to the feature. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-05-17dm: sandbox: Add a board for sandbox without CONFIG_BLKSimon Glass
While the driver-model block device support is in progress, it is useful to build sandbox both with and without CONFIG_BLK. Add a separate board for the latter. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-05-17dm: fsl_i2c: Rename I2C register structuremario.six@gdsys.cc
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2016-05-10arm: socfpga: Update iomux and pll for c5 socdk RevEDinh Nguyen
Update the pinmux and pll configuration for the Cyclone5 RevE or later devkit. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-05-06Fix various typos, scattered over the code.Robert P. J. Day
Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller
2016-05-04ARM: tegra: import latest Jetson TK1 spreadsheetStephen Warren
This imports v11 of "Jetson TK1 Development Platform Pin Mux" from https://developer.nvidia.com/embedded/downloads. The new version defines the mux option for the MIPI pad ctrl selection. The OWR pin no longer has an entry in the configuration table because the only mux option it support is OWR, that feature isn't supported, and hence can't conflict with any other pin. This pin can only usefully be used as a GPIO. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-05-02Fix spelling of "occurred".Vagrant Cascadian
Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-02Change my mailaddressAndreas Bießmann
I'll switch my mails to my own server, so drop all gmail references. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-04-25ARM: DRA7: Add ABB setup for all domainsNishanth Menon
ABB should be initialized for all required domains voltage domain for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units and has been hard to debug. This specifically is a concern with DRA7 generation of SoCs since other than VDD_MPU, all other domains are only permitted to setup the voltages to required OPP only at boot. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2016-04-25ARM: OMAP5/DRA7: Move ABB TXDONE mask to voltage structureNishanth Menon
ABB TX_DONE mask will vary depending on ABB module. For example, 3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain, DRA7 has it on all domains with the exception of CORE, RTC. Hence, move the txdone mask definition over to structure describing voltage domain. Signed-off-by: Nishanth Menon <nm@ti.com>
2016-04-25ARM: hikey: Simplify README instructions.Peter Griffin
This patch updates and simplifies the hikey README. The old instructions were hard to follow, and convoluted. This patch also updates the link to the mcuimage.bin which was outdated. Using an outdated mcuimage.bin results in the additional a53 cores not coming online when the kernel issues PSCI requests to arm trusted firmware (ATF). Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-25ARM: hisilicon: hikey: Align memory node with upstream kernelPeter Griffin
The memory node gets automatically generated by U-Boot in arch_fixup_fdt(), before passing control to the kernel using U-Boots representation of the dram banks. However the upstream kernel uses the memory node to carve-out regions of RAM for various purposes. To make this work without changing arch_fixup_fdt() which will effect many platforms we replicate the upstream memory node layout using the dram banks. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-25ARM: hisilicon: hikey: Implement reset_cpu() for hikey.Peter Griffin
This allows the reset command to reset the board from u-boot. => reset resetting ... INFO: BL1: 0xf9810000 - 0xf9818000 [size = 32768] NOTICE: Booting Trusted Firmware NOTICE: BL1: v1.1(debug):7fb9b0e NOTICE: BL1: Built : 17:06:41, Apr 19 2016 Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-25ARM: hisilicon: hikey: Enable OF_CONTROL for hikey board.Peter Griffin
Currently only the serial pl01x driver is using DT, and the other drivers still use platform data but as more DT lands in the upstream kernel the aim is to migrate the other drivers over to DT as well to have a fully DT configured hikey u-boot. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-25MAINTAINERS: Add myself as maintainer for hikeyPeter Griffin
This patch adds myself as maintainer for the hikey U-Boot port. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-25Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini
2016-04-19Add initial support for Technexion's PICO-IMX6UL-EMMC boardFabio Estevam
Add support for Technexion's PICO-IMX6UL-EMMC board. For information about this board, please visit: http://www.technexion.com/products/pico/pico-som/pico-imx6-emmc Signed-off-by: Richard Hu <richard.hu@technexion.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-04-19board: ge: bx50v3: Fix to meet LVDS display power on timingAkshay Bhat
On a reset/reboot, the display power needs to be off for atleast 500ms before turning it back on. So add a delay to the boot process to meet the display timing requirement. Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: Stefano Babic <sbabic@denx.de>
2016-04-19board: ge: bx50v3: Use pwm for display backlightAkshay Bhat
Setup the LCD backlight brightness control pin to use PWM Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: Stefano Babic <sbabic@denx.de>
2016-04-19board: ge: bx50v3: Setup LDB_DI_CLK sourceAkshay Bhat
To generate accurate pixel clocks required by the displays we need to set the ldb_di_clk source on bx50v3 to PLL3 and b850v3 to PLL5. Since PLL5 is disabled on reset, we need to enable PLL5. Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: Stefano Babic <sbabic@denx.de>
2016-04-19board: ge: bx50v3: Split display setup functionAkshay Bhat
B450v3/B650v3 uses single channel LVDS and does not support HDMI. B850v3 uses dual channel LVDS and supports HDMI. Hence split the display setup into two different functions. Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: Stefano Babic <sbabic@denx.de>
2016-04-19board: ge: bx50v3: Disable unused pinsJustin Waters
Certain pins are not used on the i.MX6, and should have a neutral pad configuration in order to reduce electrical interference on the board. This commit defines these pins with a default value rather than relying on the system defaults. Signed-off-by: Justin Waters <justin.waters@timesys.com> Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: Stefano Babic <sbabic@denx.de>
2016-04-18board: Remove overlooked vestiges of "dave" board.Robert P. J. Day
Apparently, all "dave"-related vendor content was removed in commit 5344cc1a82fcc2817d4671696b3939b0dfa4323e; remove remaining directory board/dave/, which consists solely of board/dave/common/flash.c. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2016-04-18memory: Move TI_AEMIF config to KCONFIGLokesh Vutla
Not all Keystone2 devices has AEMIF NAND controller. So adding Kconfig entry for CONFIG_TI_AEMIF and enabling it in respective defconfigs on platforms with AEMIF controller. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-18board: ti: am57xx: Add support for am572x idk in SPLSteve Kipisz
The AM572x-IDK board (Industrial Dev Kit) is a board based on TI's AM5728x SOC which has a dual core 1.5GHz A15 processor. This board is a development platform for the Industrial market with: - 2GB of DDR3L - Dual 1Gbps Ethernet - HDMI, - PRU-ICSS - uSD - 16GB eMMC - CAN - RS-485 - PCIe - USB3.0 - Video Input Port - Industrial IO port and expansion connector The link to the data sheet and TRM can be found here: http://www.ti.com/product/AM5728 NOTE: DT support is still pending upstream kernel acceptance but we should be able to get the base system support with this patch. Signed-off-by: Schuyler Patton <spatton@ti.com> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-18board: ti: am57xx: Update EMIF SDRAM 1 and 3 TimingsSchuyler Patton
Update EMIF data based on recommendations from the now standard TI EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB data sheet Update T_RRD from 5 to 6 based on AM57xx TRM - Minimum number of DDR cycles from activate to ativate for a different bank, minus 1. Update T_CKESR from 4 to 3 based on AM57xx TRM - Minimum number of DDR clocks cycles for which SDRAM must remain in self refresh, minus 1. Signed-off-by: Schuyler Patton <spatton@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-18am57x: Move CONS_INDEX to KconfigDaniel Allred
- Move the CONS_INDEX selection out of CONFIG_SYS_EXTRA_OPTIONS and into Kconfig proper. - Edit the relevant am57x configs to remove the now unneeded CONFIG_SYS_EXTRA_OPTIONS. Signed-off-by: Daniel Allred <d-allred@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-14board: README.sandbox: Update dm test commandJagan Teki
Update dm test command with pytest instead of ./test/dm/test-dm.sh Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
2016-04-13xpress: Update <usb/ehci-fsl.h> includeTom Rini
This has been renamed to <usb/ehci-ci.h> some time ago but was missed here. Signed-off-by: Tom Rini <trini@konsulko.com>
2016-04-13Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini
2016-04-13ARM64: zynqmp: Remove netdev.h from board fileMichal Simek
Including netdev.h is causing compilation warning: + int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)); + ^ w+In file included from ../board/xilinx/zynqmp/zynqmp.c:9:0: w+../include/netdev.h:204:41: warning: ‘struct eth_device’ declared inside parameter list [enabled by default] w+../include/netdev.h:204:41: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default] This patch removes it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13ARM64: zynqmp: Make DDR detection code work on 32bit systemMichal Simek
Define u64 types to be usable on 32bit system because of 64bit address and size cells and 32bit shifts in the code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-04-13ARM: zynq: Support systems with more memory banksMichal Simek
This is example how to change u-boot to support more memory banks read from DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit v0.10.2 at 2024-11-03 12:35:17 (GMT)