| Age | Commit message (Collapse) | Author |
|---|
|
On most platforms the print_fpga_state function is never called. Only
on dlvision-10g do we, so in that case inline it. Drop it from
everywhere else to avoid extra strings.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Reinhard Pfau <reinhard.pfau@gdsys.cc>
Acked-by: Dirk Eibach <dirk.eibach@gdsys.cc>
|
|
Implement spl_start_uboot to let Falcon mode work.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
|
|
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
|
|
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
|
|
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
|
|
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
|
|
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
|
|
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
|
|
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
|
|
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
[trini: Adapt am33xx, duovero, omap_zoom1]
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
|
|
|
|
|
|
Per Vikas' request, the problem this commit is supposed to be solving is
something he doesn't see and further this introduces additional hardware
requirements.
This reverts commit 4b2fd720a7b2f78c42d1565edf4c67f378c65440.
Signed-off-by: Tom Rini <trini@konsulko.com>
|
|
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In non-secure boot scenario from NAND, this address will map to CPC
configured as SRAM. But in case of secure boot, this default address
always maps to IBR (Internal Boot ROM).
The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G
address space i.e. 0x0 - 0xDFFFFFFF.
For secure boot target from NAND, the text base for SPL is kept same as
non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will
be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000)
As a the virtual and physical address of CPC would be different. The
virtual address 0xFFFx_xxxx needs to be mapped to physical address
0xBFFx_xxxx.
Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000
and update DCFG SCRTACH1 register with location of Header required for
secure boot.
The changes are similar to
commit 467a40dfe35f48d830f01a72617207d03ca85b4d
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC
is only 256K and thus SPL framework is used.
The changes are only applicable for SPL U-Boot running out of CPC SRAM
and not the next level U-Boot loaded on DDR.
Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|
|
As part of Chain of Trust for Secure boot, the SPL U-Boot will validate
the next level U-boot image. Add a new function spl_validate_uboot to
perform the validation.
Enable hardware crypto operations in SPL using SEC block.
In case of Secure Boot, PAMU is not bypassed. For allowing SEC block
access to CPC configured as SRAM, configure PAMU.
Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
|
|
Rev A03 of P2180 requires some PMIC programming adjustments, yet the
PMIC's own OTP has not been updated. Consequently, U-Boot must make
these changes itself.
NVIDIA's syseng team has confirmed that these changes can be enabled on
all board revisions without issue.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
|
|
Signed-off-by: Tom Rini <trini@konsulko.com>
Conflicts:
arch/arm/cpu/armv8/Makefile
arch/arm/lib/bootm-fdt.c
|
|
The PPA use PSCI to make secondary cores bootup. So when PPA was
enabled, add the CONFIG_ARMV8_PSCI to identify the SMP boot-method
between PSCI and spin-table.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|
|
Fix a number of typos, including:
* "compatble" -> "compatible"
* "eanbeld" -> "enabled"
* "envrionment" -> "environment"
* "FTD" -> "FDT" (for "flattened device tree")
* "ommitted" -> "omitted"
* "overriden" -> "overridden"
* "partiton" -> "partition"
* "propogate" -> "propagate"
* "resourse" -> "resource"
* "rest in piece" -> "rest in peace"
* "suport" -> "support"
* "varible" -> "variable"
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
|
|
Introduce virtual and physical addresses in the mapping table. This change
have no impact on existing boards because they all use idential mapping.
Signed-off-by: York Sun <york.sun@nxp.com>
|
|
Secure_ram variable was put in generic global data. But only ARMv8
uses this variable. Move it to ARM specific data structure.
Signed-off-by: York Sun <york.sun@nxp.com>
|
|
|
|
The Orange Pi Lite SBC is a small H3 based SBC, with 512MB RAM,
micro-sd slot, HDMI out, 2 USB-A connectors, 1 micro-USB connector,
sdio attached rtl8189ftv wifi and an ir receiver.
The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
|
|
Now that we know that the BROM stores a value indicating the boot-source
at the beginning of SRAM, use that instead of trying to recreate the
BROM's boot probing.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
|
|
We always define CONFIG_MISC_INIT_R on sunxi and misc_init_r is never
called in the spl, so the linker will optimize it and parse_spl_header(),
of which it is the only caller, away.
On the tests I've done (Orange Pi PC build) the SPL actually becomes
8 bytes smaller with this patch.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
|
|
Currently we fill ethaddr with a fixed unique address based on the SoCs
serial (from the sid) to make sure that boards which use the integrated
emac / gmac get a fixed mac rather then a random one.
On some boards the wifi does not come with a fixed mac either, so we need
to also set eth1addr.
This commit changes the ethaddr setting code to check for ethernet%d
aliases (as fdt_fixup_ethernet does) and set an ethaddr variable for
all present aliases.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
|
|
|
|
The patch converts one of the "reserved" fields in the sunxi SPL
header to a fel_uEnv_length entry. When booting over USB ("FEL
mode"), this enables the sunxi-fel utility to pass the string
length of uEnv.txt compatible data; at the same time requesting
that this data be imported into the U-Boot environment.
If parse_spl_header() in the sunxi board.c encounters a non-zero
value in this header field, it will therefore call himport_r() to
merge the string (lines) passed via FEL into the default settings.
Environment vars can be changed this way even before U-Boot will
attempt to autoboot - specifically, this also allows overriding
"bootcmd".
With fel_script_addr set and a zero fel_uEnv_length, U-Boot is
safe to assume that data in .scr format (a mkimage-type script)
was passed at fel_script_addr, and will handle it using the
existing mechanism ("bootcmd_fel").
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
|
It is useful to be able to build SPL for sandbox. It provides additional
build coverage and allows SPL features to be tested in sandbox. However
it does not need worthwhile to always create an SPL build. It nearly
doubles the build time and the feature is (so far) seldom used.
So for now, create a separate build target for sandbox SPL. This allows
experimentation with this new feature without impacting existing workflows.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
This change is to remove a halt at about 200KiB
while sending a large(1MiB) binary to a micro controller using USART1.
USART1 is connected to a PC via an on-board ST-Link debugger
that also functions as a USB-Serial converter.
However, it seems to loss some data occasionally.
So I changed the serial port to USART6 and connected it to the PC using
an FTDI USB-Serial cable, therefore the transmission was successfully
completed.
Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
|
|
This patch adds SDRAM support for stm32f746 discovery board.
This patch depends on previous patch.
This patch is based on STM32F4 and emcraft's[1].
[1]: https://github.com/EmcraftSystems/u-boot
Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
|
|
Modify the SPL build procedure for AM437x high-security (HS) device
variants to create a secure u-boot_HS.img FIT blob that contains U-Boot
and DTB artifacts signed (and optionally encrypted) with a TI-specific
process based on the CONFIG_TI_SECURE_DEVICE config option and the
externally-provided image signing tool.
Also populate the corresponding FIT image post processing call to be
performed during SPL runtime.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
Modify the SPL build procedure for AM57xx and DRA7xx high-security (HS)
device variants to create a secure u-boot_HS.img FIT blob that contains
U-Boot and DTB artifacts signed with a TI-specific process based on the
CONFIG_TI_SECURE_DEVICE config option and the externally-provided image
signing tool.
Also populate the corresponding FIT image post processing call to be
performed during SPL runtime.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
|
|
|
Add support for Advantech SOM-DB5800 with the SOM-6867 installed.
This is very similar to conga-qeval20-qa3-e3845 in that there is a
reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867)
installed.
Currently supported:
- 2x UART (From ITE EC on SOM-6867) routed to COM3/4 connectors on
SOM-DB5800.
- 4x USB 2.0 (EHCI)
- Video
- SATA
- Ethernet
- PCIe
- Realtek ALC892 HD Audio
Pad configuration for HDA_RSTB, HDA_SYNC, HDA_CLK, HDA_SDO
HDA_SDI0 is set in DT to enable HD Audio codec.
Pin defaults for codec pin complexs are not changed.
Not supported:
- Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500)
- USB 3.0 (XHCI)
- TPM
Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
|
This patch adds support to enable and use the internal BayTrail UART
instead of the one integrated in the Super IO Winbond chip. For this,
a 2nd defconfig file is added.
This is useful for tests done for the congatec SoM used on baseboards
without such a Super IO chip.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
|
|
These boards should have maintainer entries. Add them.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
Since we lack information about the DRAM initialization for the
Allwinner A64 SoC, booting any A64 based board like the Pine64 is a bit
involved at the moment.
Add a README file to explain the process.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Move to board/sunxi/ from doc/]
Signed-off-by: Tom Rini <trini@konsulko.com>
|
|
The Parrot Board is an evaluation board with an Allwinner R16 (assumed
to be close to an Allwinner A33), 4GB of eMMC, 512MB of RAM, USB host
and OTG, a WiFi/Bluetooth combo chip, a micro SD Card reader, 2
controllable buttons, an LVDS port with separated backlight and
capacitive touch panel ports, an audio/microphone jack, a camera CSI
port, 2 sets of 22 GPIOs and an accelerometer.
The DTS file is identical to the one submitted to the upstream kernel.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
|
The switch to simple_printf was causing the SPL dram info to show as:
DRAM: u MiB
This fixes this by switching from %lu to %d for printing the DRAM size.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
|
|
DRA72-Evm revC uses dra72-evm-revc.dtb. Update the same in env vatiables.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
|
|
Align the name of the defconfig file for high-security (HS) device variants
from the AM43xx family of SoCs with the corresponding name used for the
general purpose devices. This allows for easier cross-association of those
files and also provides room to grow from an HS device part number
perspective.
Furthermore, update and cleanup associated MAINTAINERS file.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Madan Srinivas <madans@ti.com>
|
|
|
|
Get the clocks from FPGA through I2C, if IFC is disabled.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|
|
Not only am335x supports booting from NOR, i.MX6 SoCs also
supports booting from NOR. Make NOR_BOOT a common
option to let different SoCs share it.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Christophe Ricard <christophe-h.ricard@st.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Francois Retief <fgretief@spaceteq.co.za>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
|
|
Update the email address for the boards that I maintain.
Signed-off-by: Steve Rae <steve.rae@raedomain.com>
|
|
add DM and DTS support for the at91 based siemens
boards.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[rebased on current ToT]
Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
|
|
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[rebased on current ToT]
Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
|
|
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[rebase on current ToT, don't delete gurnard DTB creation]
Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
|
|
Rename B&R kwb board to brxre1
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Tom Rini <trini@konsulko.com>
|
